Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7707

1

T1

34

T3

26

T6

13

auto[1]

10413

1

T1

28

T3

29

T4

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5728	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6084	1			T1	23		T2	1		T3	14
reset_info_cp[2]	2768	1			T1	8		T3	8		T4	1
reset_info_cp[4]	3643	1			T1	14		T3	13		T4	1
reset_info_cp[8]	112	1			T1	1		T12	1		T37	1
reset_info_cp[16]	99	1			T1	1		T3	1		T6	1
reset_info_cp[32]	96	1			T3	1		T15	2		T29	1
reset_info_cp[64]	108	1			T3	1		T64	1		T68	1
reset_info_cp[128]	102	1			T1	1		T12	1		T13	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2977	1			T1	13		T3	7		T12	8
reset_info_cp[1]	auto[1]	2487	1			T1	9		T3	6		T4	1
reset_info_cp[2]	auto[0]	864	1			T1	4		T3	4		T12	7
reset_info_cp[2]	auto[1]	1904	1			T1	4		T3	4		T4	1
reset_info_cp[4]	auto[0]	1273	1			T1	6		T3	6		T12	7
reset_info_cp[4]	auto[1]	2370	1			T1	8		T3	7		T4	1
reset_info_cp[8]	auto[0]	40	1			T32	1		T101	1		T138	1
reset_info_cp[8]	auto[1]	72	1			T1	1		T12	1		T37	1
reset_info_cp[16]	auto[0]	42	1			T6	1		T47	1		T59	1
reset_info_cp[16]	auto[1]	57	1			T1	1		T3	1		T15	1
reset_info_cp[32]	auto[0]	43	1			T3	1		T32	1		T87	2
reset_info_cp[32]	auto[1]	53	1			T15	2		T29	1		T88	1
reset_info_cp[64]	auto[0]	47	1			T64	1		T101	3		T87	1
reset_info_cp[64]	auto[1]	61	1			T3	1		T68	1		T69	1
reset_info_cp[128]	auto[0]	37	1			T12	1		T70	1		T101	1
reset_info_cp[128]	auto[1]	65	1			T1	1		T13	2		T15	1