Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
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T534 /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3828359535 May 19 01:32:30 PM PDT 24 May 19 01:32:33 PM PDT 24 244375770 ps
T535 /workspace/coverage/default/19.rstmgr_sw_rst.3462940024 May 19 01:32:50 PM PDT 24 May 19 01:32:53 PM PDT 24 318191970 ps
T536 /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3206198051 May 19 01:32:56 PM PDT 24 May 19 01:33:06 PM PDT 24 1883962182 ps
T537 /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2371052905 May 19 01:33:11 PM PDT 24 May 19 01:33:14 PM PDT 24 105373707 ps
T538 /workspace/coverage/default/6.rstmgr_sw_rst.2666144939 May 19 01:32:19 PM PDT 24 May 19 01:32:23 PM PDT 24 510697207 ps
T76 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2969406656 May 19 01:48:31 PM PDT 24 May 19 01:48:33 PM PDT 24 158034906 ps
T77 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2870693584 May 19 01:48:19 PM PDT 24 May 19 01:48:20 PM PDT 24 98275793 ps
T78 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3461655907 May 19 01:48:35 PM PDT 24 May 19 01:48:41 PM PDT 24 888248035 ps
T79 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.327701644 May 19 01:48:25 PM PDT 24 May 19 01:48:30 PM PDT 24 866333301 ps
T102 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.4158278959 May 19 01:48:35 PM PDT 24 May 19 01:48:38 PM PDT 24 85648078 ps
T80 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.4160871211 May 19 01:48:37 PM PDT 24 May 19 01:48:42 PM PDT 24 157124499 ps
T81 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1135136495 May 19 01:48:33 PM PDT 24 May 19 01:48:34 PM PDT 24 118909997 ps
T95 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3110304243 May 19 01:48:25 PM PDT 24 May 19 01:48:29 PM PDT 24 340486917 ps
T96 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3599468155 May 19 01:48:33 PM PDT 24 May 19 01:48:35 PM PDT 24 130941657 ps
T97 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.247883644 May 19 01:48:25 PM PDT 24 May 19 01:48:28 PM PDT 24 308664835 ps
T98 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2636752769 May 19 01:48:23 PM PDT 24 May 19 01:48:26 PM PDT 24 118707526 ps
T539 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.863886320 May 19 01:48:33 PM PDT 24 May 19 01:48:34 PM PDT 24 78743746 ps
T100 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1250336487 May 19 01:48:29 PM PDT 24 May 19 01:48:34 PM PDT 24 879506107 ps
T111 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3269894957 May 19 01:48:28 PM PDT 24 May 19 01:48:30 PM PDT 24 124416520 ps
T540 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.111246760 May 19 01:48:23 PM PDT 24 May 19 01:48:25 PM PDT 24 94447770 ps
T148 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2790209944 May 19 01:48:27 PM PDT 24 May 19 01:48:30 PM PDT 24 802754161 ps
T99 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.119667224 May 19 01:48:35 PM PDT 24 May 19 01:48:41 PM PDT 24 465076665 ps
T120 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3213072026 May 19 01:48:32 PM PDT 24 May 19 01:48:35 PM PDT 24 173490002 ps
T541 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3310019730 May 19 01:48:26 PM PDT 24 May 19 01:48:29 PM PDT 24 472983801 ps
T542 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3741603374 May 19 01:48:25 PM PDT 24 May 19 01:48:31 PM PDT 24 814657133 ps
T543 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.804991920 May 19 01:48:14 PM PDT 24 May 19 01:48:16 PM PDT 24 76523167 ps
T544 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.4045198918 May 19 01:48:28 PM PDT 24 May 19 01:48:31 PM PDT 24 113373977 ps
T126 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2034864378 May 19 01:48:27 PM PDT 24 May 19 01:48:30 PM PDT 24 226076564 ps
T121 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.667901375 May 19 01:48:36 PM PDT 24 May 19 01:48:43 PM PDT 24 625957282 ps
T112 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.945526054 May 19 01:48:35 PM PDT 24 May 19 01:48:39 PM PDT 24 224705116 ps
T545 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3701097516 May 19 01:48:22 PM PDT 24 May 19 01:48:27 PM PDT 24 803490528 ps
T124 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2725442138 May 19 01:48:14 PM PDT 24 May 19 01:48:18 PM PDT 24 898448802 ps
T113 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.681464548 May 19 01:48:36 PM PDT 24 May 19 01:48:40 PM PDT 24 257026796 ps
T127 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3419243588 May 19 01:48:28 PM PDT 24 May 19 01:48:32 PM PDT 24 339399213 ps
T546 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1997922536 May 19 01:48:28 PM PDT 24 May 19 01:48:32 PM PDT 24 417540999 ps
T547 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1903053149 May 19 01:48:26 PM PDT 24 May 19 01:48:30 PM PDT 24 165732404 ps
T548 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2204788556 May 19 01:48:32 PM PDT 24 May 19 01:48:35 PM PDT 24 274704140 ps
T549 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1494057006 May 19 01:48:28 PM PDT 24 May 19 01:48:30 PM PDT 24 91272031 ps
T550 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3950660761 May 19 01:48:28 PM PDT 24 May 19 01:48:31 PM PDT 24 65938360 ps
T551 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.344314467 May 19 01:48:27 PM PDT 24 May 19 01:48:29 PM PDT 24 84447155 ps
T552 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2974344020 May 19 01:48:27 PM PDT 24 May 19 01:48:29 PM PDT 24 71207539 ps
T114 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1666827918 May 19 01:48:32 PM PDT 24 May 19 01:48:34 PM PDT 24 139364716 ps
T125 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.934139375 May 19 01:48:38 PM PDT 24 May 19 01:48:44 PM PDT 24 596085912 ps
T553 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1087270366 May 19 01:48:39 PM PDT 24 May 19 01:48:44 PM PDT 24 126666743 ps
T115 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2149887747 May 19 01:48:30 PM PDT 24 May 19 01:48:32 PM PDT 24 69827202 ps
T554 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.4267486841 May 19 01:48:30 PM PDT 24 May 19 01:48:32 PM PDT 24 122362800 ps
T555 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.165769486 May 19 01:48:38 PM PDT 24 May 19 01:48:43 PM PDT 24 80313707 ps
T556 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1685988331 May 19 01:48:36 PM PDT 24 May 19 01:48:41 PM PDT 24 180033413 ps
T116 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2132023849 May 19 01:48:21 PM PDT 24 May 19 01:48:22 PM PDT 24 152691613 ps
T117 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1054065411 May 19 01:48:33 PM PDT 24 May 19 01:48:36 PM PDT 24 87123558 ps
T557 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.159590560 May 19 01:48:29 PM PDT 24 May 19 01:48:31 PM PDT 24 94696527 ps
T558 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3242375309 May 19 01:48:23 PM PDT 24 May 19 01:48:26 PM PDT 24 188777627 ps
T559 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.876430216 May 19 01:48:28 PM PDT 24 May 19 01:48:32 PM PDT 24 172120771 ps
T118 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1656438680 May 19 01:48:34 PM PDT 24 May 19 01:48:37 PM PDT 24 156649182 ps
T560 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.807764520 May 19 01:48:19 PM PDT 24 May 19 01:48:20 PM PDT 24 115496558 ps
T561 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3236307830 May 19 01:48:38 PM PDT 24 May 19 01:48:44 PM PDT 24 300950290 ps
T119 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2702338423 May 19 01:48:25 PM PDT 24 May 19 01:48:26 PM PDT 24 85447946 ps
T562 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2009942729 May 19 01:48:28 PM PDT 24 May 19 01:48:31 PM PDT 24 61606379 ps
T563 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1873563878 May 19 01:48:36 PM PDT 24 May 19 01:48:40 PM PDT 24 188416274 ps
T564 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3327356343 May 19 01:48:25 PM PDT 24 May 19 01:48:28 PM PDT 24 212207545 ps
T565 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1691019779 May 19 01:48:34 PM PDT 24 May 19 01:48:38 PM PDT 24 115275705 ps
T566 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.18547448 May 19 01:48:21 PM PDT 24 May 19 01:48:24 PM PDT 24 205704078 ps
T567 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.232979024 May 19 01:48:34 PM PDT 24 May 19 01:48:41 PM PDT 24 477532137 ps
T568 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.4056498616 May 19 01:48:36 PM PDT 24 May 19 01:48:40 PM PDT 24 208496971 ps
T569 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3986434276 May 19 01:48:18 PM PDT 24 May 19 01:48:21 PM PDT 24 407412276 ps
T123 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1618311936 May 19 01:48:26 PM PDT 24 May 19 01:48:30 PM PDT 24 808542409 ps
T570 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1080971550 May 19 01:48:23 PM PDT 24 May 19 01:48:28 PM PDT 24 500447894 ps
T571 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1966705495 May 19 01:48:30 PM PDT 24 May 19 01:48:32 PM PDT 24 62190811 ps
T572 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3567946657 May 19 01:48:34 PM PDT 24 May 19 01:48:38 PM PDT 24 185119934 ps
T573 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3613895206 May 19 01:48:23 PM PDT 24 May 19 01:48:26 PM PDT 24 131249985 ps
T574 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.395840478 May 19 01:48:35 PM PDT 24 May 19 01:48:40 PM PDT 24 414081425 ps
T575 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3135645147 May 19 01:48:27 PM PDT 24 May 19 01:48:29 PM PDT 24 188523397 ps
T576 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.719528077 May 19 01:48:23 PM PDT 24 May 19 01:48:26 PM PDT 24 484733350 ps
T577 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3098642262 May 19 01:48:29 PM PDT 24 May 19 01:48:31 PM PDT 24 110109432 ps
T578 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3930753276 May 19 01:48:26 PM PDT 24 May 19 01:48:28 PM PDT 24 200108121 ps
T579 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1385815284 May 19 01:48:40 PM PDT 24 May 19 01:48:45 PM PDT 24 203496479 ps
T580 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.4215646036 May 19 01:48:28 PM PDT 24 May 19 01:48:31 PM PDT 24 238954199 ps
T581 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1114201428 May 19 01:48:36 PM PDT 24 May 19 01:48:40 PM PDT 24 62082202 ps
T582 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.431596182 May 19 01:48:25 PM PDT 24 May 19 01:48:26 PM PDT 24 98199060 ps
T583 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1731676046 May 19 01:48:29 PM PDT 24 May 19 01:48:33 PM PDT 24 524660791 ps
T584 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4282791501 May 19 01:48:28 PM PDT 24 May 19 01:48:30 PM PDT 24 85702573 ps
T585 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3830827584 May 19 01:48:32 PM PDT 24 May 19 01:48:34 PM PDT 24 60773389 ps
T122 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1769393929 May 19 01:48:27 PM PDT 24 May 19 01:48:32 PM PDT 24 792251201 ps
T586 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1881580632 May 19 01:48:26 PM PDT 24 May 19 01:48:28 PM PDT 24 134026418 ps
T587 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.699627728 May 19 01:48:29 PM PDT 24 May 19 01:48:31 PM PDT 24 68659155 ps
T588 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1272059994 May 19 01:48:18 PM PDT 24 May 19 01:48:23 PM PDT 24 807531538 ps
T146 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2112644067 May 19 01:48:31 PM PDT 24 May 19 01:48:35 PM PDT 24 799782873 ps
T589 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2757799071 May 19 01:48:13 PM PDT 24 May 19 01:48:16 PM PDT 24 363033389 ps
T590 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1242348563 May 19 01:48:29 PM PDT 24 May 19 01:48:32 PM PDT 24 120247564 ps
T591 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2425400096 May 19 01:48:23 PM PDT 24 May 19 01:48:28 PM PDT 24 901918524 ps
T592 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3480102195 May 19 01:48:36 PM PDT 24 May 19 01:48:40 PM PDT 24 88080227 ps
T593 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.75190717 May 19 01:48:34 PM PDT 24 May 19 01:48:38 PM PDT 24 194939859 ps
T594 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2142355134 May 19 01:48:34 PM PDT 24 May 19 01:48:37 PM PDT 24 179404870 ps
T595 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2752774365 May 19 01:48:26 PM PDT 24 May 19 01:48:28 PM PDT 24 63659964 ps
T596 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2270062084 May 19 01:48:16 PM PDT 24 May 19 01:48:19 PM PDT 24 365496249 ps
T597 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3875798970 May 19 01:48:35 PM PDT 24 May 19 01:48:39 PM PDT 24 127782876 ps
T598 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1455502045 May 19 01:48:22 PM PDT 24 May 19 01:48:31 PM PDT 24 1566747875 ps
T599 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1098077943 May 19 01:48:30 PM PDT 24 May 19 01:48:32 PM PDT 24 71825314 ps
T600 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3264327947 May 19 01:48:27 PM PDT 24 May 19 01:48:30 PM PDT 24 267115676 ps
T601 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.847816742 May 19 01:48:31 PM PDT 24 May 19 01:48:33 PM PDT 24 118071068 ps
T147 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.4275689235 May 19 01:48:35 PM PDT 24 May 19 01:48:39 PM PDT 24 420165965 ps
T602 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.88320615 May 19 01:48:31 PM PDT 24 May 19 01:48:35 PM PDT 24 902362015 ps
T603 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2304831110 May 19 01:48:24 PM PDT 24 May 19 01:48:26 PM PDT 24 95487145 ps
T604 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.384431357 May 19 01:48:36 PM PDT 24 May 19 01:48:39 PM PDT 24 79413180 ps
T605 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2112304411 May 19 01:48:39 PM PDT 24 May 19 01:48:44 PM PDT 24 127080734 ps
T606 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.737544677 May 19 01:48:14 PM PDT 24 May 19 01:48:16 PM PDT 24 146081018 ps
T607 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1971105014 May 19 01:48:31 PM PDT 24 May 19 01:48:33 PM PDT 24 152528434 ps
T608 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2802917160 May 19 01:48:23 PM PDT 24 May 19 01:48:25 PM PDT 24 228083238 ps
T609 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.12673932 May 19 01:48:25 PM PDT 24 May 19 01:48:28 PM PDT 24 252489495 ps
T610 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1761841457 May 19 01:48:36 PM PDT 24 May 19 01:48:42 PM PDT 24 963576060 ps
T611 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3805970277 May 19 01:48:40 PM PDT 24 May 19 01:48:45 PM PDT 24 420581438 ps
T612 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.4101458896 May 19 01:48:13 PM PDT 24 May 19 01:48:18 PM PDT 24 427070312 ps
T613 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1446592731 May 19 01:48:14 PM PDT 24 May 19 01:48:17 PM PDT 24 247198332 ps
T614 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1605060786 May 19 01:48:29 PM PDT 24 May 19 01:48:32 PM PDT 24 112647807 ps
T615 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2009145050 May 19 01:48:23 PM PDT 24 May 19 01:48:25 PM PDT 24 59615375 ps
T616 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.4213056714 May 19 01:48:20 PM PDT 24 May 19 01:48:22 PM PDT 24 161063856 ps
T617 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1928163572 May 19 01:48:32 PM PDT 24 May 19 01:48:36 PM PDT 24 754117458 ps
T618 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.4078725751 May 19 01:48:28 PM PDT 24 May 19 01:48:31 PM PDT 24 65327701 ps
T619 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1676422374 May 19 01:48:33 PM PDT 24 May 19 01:48:35 PM PDT 24 63164402 ps
T620 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.897650417 May 19 01:48:25 PM PDT 24 May 19 01:48:26 PM PDT 24 60692800 ps

Test location /workspace/coverage/default/44.rstmgr_stress_all.1739299036
Short name T3
Test name
Test status
Simulation time 1630325950 ps
CPU time 6.52 seconds
Started May 19 01:33:26 PM PDT 24
Finished May 19 01:33:36 PM PDT 24
Peak memory 208892 kb
Host smart-594d753f-9c6b-4014-a66c-1bac3f3a85c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739299036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1739299036
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.4071418050
Short name T2
Test name
Test status
Simulation time 268529730 ps
CPU time 1.78 seconds
Started May 19 01:33:10 PM PDT 24
Finished May 19 01:33:13 PM PDT 24
Peak memory 200480 kb
Host smart-38aafc8e-0f26-44bb-a34c-8bef76077789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071418050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.4071418050
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.327701644
Short name T79
Test name
Test status
Simulation time 866333301 ps
CPU time 3.59 seconds
Started May 19 01:48:25 PM PDT 24
Finished May 19 01:48:30 PM PDT 24
Peak memory 200552 kb
Host smart-fa0ef77a-af6d-49e6-9223-c09767697c24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327701644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
327701644
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1378107225
Short name T15
Test name
Test status
Simulation time 1227711062 ps
CPU time 5.61 seconds
Started May 19 01:32:33 PM PDT 24
Finished May 19 01:32:42 PM PDT 24
Peak memory 218032 kb
Host smart-f3f30b19-8235-4726-9e02-000c549fcfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378107225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1378107225
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3836975360
Short name T82
Test name
Test status
Simulation time 16516838257 ps
CPU time 29.15 seconds
Started May 19 01:32:24 PM PDT 24
Finished May 19 01:32:55 PM PDT 24
Peak memory 217596 kb
Host smart-9b9bf715-1e9f-4571-bf6a-538702a645a2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836975360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3836975360
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.119667224
Short name T99
Test name
Test status
Simulation time 465076665 ps
CPU time 3.53 seconds
Started May 19 01:48:35 PM PDT 24
Finished May 19 01:48:41 PM PDT 24
Peak memory 208744 kb
Host smart-df52d01c-8f27-400e-9091-b98a6dbba332
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119667224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.119667224
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.1652952193
Short name T70
Test name
Test status
Simulation time 3908844555 ps
CPU time 15.89 seconds
Started May 19 01:32:41 PM PDT 24
Finished May 19 01:32:59 PM PDT 24
Peak memory 209852 kb
Host smart-aa3ef6c5-25ff-4533-a030-a3f1ed573e14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652952193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1652952193
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.914668767
Short name T8
Test name
Test status
Simulation time 73818383 ps
CPU time 0.8 seconds
Started May 19 01:32:55 PM PDT 24
Finished May 19 01:32:57 PM PDT 24
Peak memory 200304 kb
Host smart-dc56b34d-7823-4cb5-a6f5-48f57f4e3d79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914668767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.914668767
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3220267426
Short name T101
Test name
Test status
Simulation time 6083777879 ps
CPU time 24.26 seconds
Started May 19 01:32:35 PM PDT 24
Finished May 19 01:33:02 PM PDT 24
Peak memory 200692 kb
Host smart-2d7c1aaa-6833-451e-8d50-b40f96f423fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220267426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3220267426
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2734428046
Short name T154
Test name
Test status
Simulation time 105572641 ps
CPU time 1.09 seconds
Started May 19 01:32:15 PM PDT 24
Finished May 19 01:32:16 PM PDT 24
Peak memory 200492 kb
Host smart-40a149a3-cb60-4261-9ed3-fc72d6ca9a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734428046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2734428046
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.4104009666
Short name T87
Test name
Test status
Simulation time 233833889 ps
CPU time 1.35 seconds
Started May 19 01:33:22 PM PDT 24
Finished May 19 01:33:27 PM PDT 24
Peak memory 200696 kb
Host smart-f0bb6dd8-a48c-4be3-9df3-e9460d7062c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104009666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.4104009666
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.88320615
Short name T602
Test name
Test status
Simulation time 902362015 ps
CPU time 3.22 seconds
Started May 19 01:48:31 PM PDT 24
Finished May 19 01:48:35 PM PDT 24
Peak memory 200576 kb
Host smart-ce3e912a-1151-4c33-93b4-425f2f63c10d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88320615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.88320615
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3323741237
Short name T53
Test name
Test status
Simulation time 1227125845 ps
CPU time 5.64 seconds
Started May 19 01:32:47 PM PDT 24
Finished May 19 01:32:53 PM PDT 24
Peak memory 221572 kb
Host smart-16b50ce6-8015-4e19-b58f-fd3ea58f5966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323741237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3323741237
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1903053149
Short name T547
Test name
Test status
Simulation time 165732404 ps
CPU time 2.4 seconds
Started May 19 01:48:26 PM PDT 24
Finished May 19 01:48:30 PM PDT 24
Peak memory 208760 kb
Host smart-f9a178c3-2825-497e-b0a1-328dd9a2bb3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903053149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1903053149
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.116888159
Short name T40
Test name
Test status
Simulation time 2185717807 ps
CPU time 8.68 seconds
Started May 19 01:33:13 PM PDT 24
Finished May 19 01:33:23 PM PDT 24
Peak memory 218224 kb
Host smart-f721811a-3308-43f6-be54-3fef6e2746f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116888159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.116888159
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3175380635
Short name T92
Test name
Test status
Simulation time 4072348700 ps
CPU time 18.53 seconds
Started May 19 01:33:00 PM PDT 24
Finished May 19 01:33:20 PM PDT 24
Peak memory 200784 kb
Host smart-9c7bcda5-a0f3-4497-a6bd-dd3230625ede
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175380635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3175380635
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1769393929
Short name T122
Test name
Test status
Simulation time 792251201 ps
CPU time 3.2 seconds
Started May 19 01:48:27 PM PDT 24
Finished May 19 01:48:32 PM PDT 24
Peak memory 200596 kb
Host smart-a0ae7053-2848-487c-8fdd-9e57ed01b0ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769393929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1769393929
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2132023849
Short name T116
Test name
Test status
Simulation time 152691613 ps
CPU time 1.18 seconds
Started May 19 01:48:21 PM PDT 24
Finished May 19 01:48:22 PM PDT 24
Peak memory 200412 kb
Host smart-02d2fd26-eee0-4a9e-a93c-8810f0b96a56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132023849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2132023849
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3015634286
Short name T22
Test name
Test status
Simulation time 189954237 ps
CPU time 0.9 seconds
Started May 19 01:32:30 PM PDT 24
Finished May 19 01:32:33 PM PDT 24
Peak memory 200264 kb
Host smart-adf48d86-fc81-473f-b421-6330b7907536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015634286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3015634286
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1103974419
Short name T159
Test name
Test status
Simulation time 243866773 ps
CPU time 1.06 seconds
Started May 19 01:32:21 PM PDT 24
Finished May 19 01:32:23 PM PDT 24
Peak memory 217580 kb
Host smart-8e2d19e3-bc51-40a8-9984-66defa96b7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103974419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1103974419
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2757799071
Short name T589
Test name
Test status
Simulation time 363033389 ps
CPU time 2.46 seconds
Started May 19 01:48:13 PM PDT 24
Finished May 19 01:48:16 PM PDT 24
Peak memory 200488 kb
Host smart-151170d4-4cc0-40e5-8f95-ee08597196bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757799071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
757799071
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1455502045
Short name T598
Test name
Test status
Simulation time 1566747875 ps
CPU time 8.1 seconds
Started May 19 01:48:22 PM PDT 24
Finished May 19 01:48:31 PM PDT 24
Peak memory 200520 kb
Host smart-370046ab-d30f-4960-88d5-5a63328abac2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455502045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
455502045
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.737544677
Short name T606
Test name
Test status
Simulation time 146081018 ps
CPU time 0.98 seconds
Started May 19 01:48:14 PM PDT 24
Finished May 19 01:48:16 PM PDT 24
Peak memory 200336 kb
Host smart-c8fa36a7-57ff-4e81-9ab0-e44af96fd4f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737544677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.737544677
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2636752769
Short name T98
Test name
Test status
Simulation time 118707526 ps
CPU time 1.3 seconds
Started May 19 01:48:23 PM PDT 24
Finished May 19 01:48:26 PM PDT 24
Peak memory 208596 kb
Host smart-d91383ad-5402-4e09-bbe9-32e11da6f175
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636752769 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2636752769
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.804991920
Short name T543
Test name
Test status
Simulation time 76523167 ps
CPU time 0.82 seconds
Started May 19 01:48:14 PM PDT 24
Finished May 19 01:48:16 PM PDT 24
Peak memory 200224 kb
Host smart-6726d225-ef51-4cc1-8ff1-14eb7a105273
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804991920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.804991920
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1446592731
Short name T613
Test name
Test status
Simulation time 247198332 ps
CPU time 1.55 seconds
Started May 19 01:48:14 PM PDT 24
Finished May 19 01:48:17 PM PDT 24
Peak memory 200580 kb
Host smart-b6763ba7-27d7-4529-9047-29aecf5e5ec7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446592731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1446592731
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.4101458896
Short name T612
Test name
Test status
Simulation time 427070312 ps
CPU time 3.19 seconds
Started May 19 01:48:13 PM PDT 24
Finished May 19 01:48:18 PM PDT 24
Peak memory 208760 kb
Host smart-fad50f63-e90a-484a-bf53-6d8180f6dc4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101458896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.4101458896
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2725442138
Short name T124
Test name
Test status
Simulation time 898448802 ps
CPU time 3.07 seconds
Started May 19 01:48:14 PM PDT 24
Finished May 19 01:48:18 PM PDT 24
Peak memory 200600 kb
Host smart-642f7a75-d2e3-49b5-9a59-6da999c62262
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725442138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2725442138
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2270062084
Short name T596
Test name
Test status
Simulation time 365496249 ps
CPU time 2.28 seconds
Started May 19 01:48:16 PM PDT 24
Finished May 19 01:48:19 PM PDT 24
Peak memory 200472 kb
Host smart-3249ad06-f1f7-4a67-b4ca-6668b8ebe451
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270062084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
270062084
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1272059994
Short name T588
Test name
Test status
Simulation time 807531538 ps
CPU time 4.27 seconds
Started May 19 01:48:18 PM PDT 24
Finished May 19 01:48:23 PM PDT 24
Peak memory 200524 kb
Host smart-4a91e8f4-23bf-4ca3-89b7-8d1689330b8b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272059994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
272059994
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2870693584
Short name T77
Test name
Test status
Simulation time 98275793 ps
CPU time 0.91 seconds
Started May 19 01:48:19 PM PDT 24
Finished May 19 01:48:20 PM PDT 24
Peak memory 200588 kb
Host smart-6925afea-c060-4b21-bf16-53e082af3f4a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870693584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
870693584
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.4213056714
Short name T616
Test name
Test status
Simulation time 161063856 ps
CPU time 1.16 seconds
Started May 19 01:48:20 PM PDT 24
Finished May 19 01:48:22 PM PDT 24
Peak memory 200440 kb
Host smart-102973a9-1b84-4d59-be84-d6579eaea741
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213056714 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.4213056714
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.4078725751
Short name T618
Test name
Test status
Simulation time 65327701 ps
CPU time 0.77 seconds
Started May 19 01:48:28 PM PDT 24
Finished May 19 01:48:31 PM PDT 24
Peak memory 200456 kb
Host smart-277d369c-9b2e-4811-8cd9-84164cd310d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078725751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.4078725751
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3110304243
Short name T95
Test name
Test status
Simulation time 340486917 ps
CPU time 2.36 seconds
Started May 19 01:48:25 PM PDT 24
Finished May 19 01:48:29 PM PDT 24
Peak memory 200588 kb
Host smart-7d135b52-43d5-4e59-8a80-2ed647b2bd8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110304243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3110304243
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3098642262
Short name T577
Test name
Test status
Simulation time 110109432 ps
CPU time 1.1 seconds
Started May 19 01:48:29 PM PDT 24
Finished May 19 01:48:31 PM PDT 24
Peak memory 208620 kb
Host smart-cbacc3ce-f192-4cd9-903a-ce09f2a57e62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098642262 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3098642262
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.159590560
Short name T557
Test name
Test status
Simulation time 94696527 ps
CPU time 0.89 seconds
Started May 19 01:48:29 PM PDT 24
Finished May 19 01:48:31 PM PDT 24
Peak memory 200312 kb
Host smart-66b85fb6-6099-4065-a66d-55d701198451
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159590560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.159590560
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1656438680
Short name T118
Test name
Test status
Simulation time 156649182 ps
CPU time 1.15 seconds
Started May 19 01:48:34 PM PDT 24
Finished May 19 01:48:37 PM PDT 24
Peak memory 200408 kb
Host smart-7b9b8112-6837-4760-8891-345d73d8c7c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656438680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1656438680
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3310019730
Short name T541
Test name
Test status
Simulation time 472983801 ps
CPU time 1.9 seconds
Started May 19 01:48:26 PM PDT 24
Finished May 19 01:48:29 PM PDT 24
Peak memory 200608 kb
Host smart-0471c2cb-4193-4dfb-848f-10e0ce9b5faa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310019730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3310019730
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1873563878
Short name T563
Test name
Test status
Simulation time 188416274 ps
CPU time 1.65 seconds
Started May 19 01:48:36 PM PDT 24
Finished May 19 01:48:40 PM PDT 24
Peak memory 208836 kb
Host smart-6fa0ef37-b44b-49ef-b5d5-d0b3078e5a2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873563878 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.1873563878
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.344314467
Short name T551
Test name
Test status
Simulation time 84447155 ps
CPU time 0.89 seconds
Started May 19 01:48:27 PM PDT 24
Finished May 19 01:48:29 PM PDT 24
Peak memory 200296 kb
Host smart-40e80060-672f-422e-b2de-78a209dff44b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344314467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.344314467
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.4215646036
Short name T580
Test name
Test status
Simulation time 238954199 ps
CPU time 1.65 seconds
Started May 19 01:48:28 PM PDT 24
Finished May 19 01:48:31 PM PDT 24
Peak memory 200564 kb
Host smart-43c90c55-8c7d-437a-b972-b779acd5bb5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215646036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.4215646036
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3419243588
Short name T127
Test name
Test status
Simulation time 339399213 ps
CPU time 2.55 seconds
Started May 19 01:48:28 PM PDT 24
Finished May 19 01:48:32 PM PDT 24
Peak memory 212492 kb
Host smart-c570e266-81b4-4d7b-85f4-3f02dd6165ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419243588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3419243588
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1997922536
Short name T546
Test name
Test status
Simulation time 417540999 ps
CPU time 1.72 seconds
Started May 19 01:48:28 PM PDT 24
Finished May 19 01:48:32 PM PDT 24
Peak memory 200640 kb
Host smart-1936a2b6-47c2-44ea-88c7-59dccd0cd15d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997922536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1997922536
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2112304411
Short name T605
Test name
Test status
Simulation time 127080734 ps
CPU time 1.38 seconds
Started May 19 01:48:39 PM PDT 24
Finished May 19 01:48:44 PM PDT 24
Peak memory 213412 kb
Host smart-2e11189f-8736-4f8c-9622-df4c5913aeb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112304411 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2112304411
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.699627728
Short name T587
Test name
Test status
Simulation time 68659155 ps
CPU time 0.8 seconds
Started May 19 01:48:29 PM PDT 24
Finished May 19 01:48:31 PM PDT 24
Peak memory 200568 kb
Host smart-94ae9813-e3a4-4156-a6fd-18b53250289c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699627728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.699627728
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.681464548
Short name T113
Test name
Test status
Simulation time 257026796 ps
CPU time 1.56 seconds
Started May 19 01:48:36 PM PDT 24
Finished May 19 01:48:40 PM PDT 24
Peak memory 200612 kb
Host smart-0cec4e21-15e9-4355-af7c-17039dd5f710
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681464548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.681464548
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.4056498616
Short name T568
Test name
Test status
Simulation time 208496971 ps
CPU time 1.5 seconds
Started May 19 01:48:36 PM PDT 24
Finished May 19 01:48:40 PM PDT 24
Peak memory 208588 kb
Host smart-86cb4998-679c-4e30-812f-229de08d795c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056498616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.4056498616
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3599468155
Short name T96
Test name
Test status
Simulation time 130941657 ps
CPU time 1.31 seconds
Started May 19 01:48:33 PM PDT 24
Finished May 19 01:48:35 PM PDT 24
Peak memory 208620 kb
Host smart-ca9db3ef-13e9-45f1-b797-941bcbff609d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599468155 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3599468155
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1966705495
Short name T571
Test name
Test status
Simulation time 62190811 ps
CPU time 0.77 seconds
Started May 19 01:48:30 PM PDT 24
Finished May 19 01:48:32 PM PDT 24
Peak memory 200348 kb
Host smart-a56f4a36-1209-4b45-a25d-f3da205ae1e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966705495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1966705495
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1666827918
Short name T114
Test name
Test status
Simulation time 139364716 ps
CPU time 1.38 seconds
Started May 19 01:48:32 PM PDT 24
Finished May 19 01:48:34 PM PDT 24
Peak memory 200472 kb
Host smart-4bf48402-058e-497a-a8b0-f6767c8d6830
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666827918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1666827918
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3236307830
Short name T561
Test name
Test status
Simulation time 300950290 ps
CPU time 2.31 seconds
Started May 19 01:48:38 PM PDT 24
Finished May 19 01:48:44 PM PDT 24
Peak memory 211288 kb
Host smart-3152950a-5a78-4e2d-9c0c-8339c28240c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236307830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3236307830
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1928163572
Short name T617
Test name
Test status
Simulation time 754117458 ps
CPU time 3.25 seconds
Started May 19 01:48:32 PM PDT 24
Finished May 19 01:48:36 PM PDT 24
Peak memory 200644 kb
Host smart-71da5817-6e52-4f8f-a005-7d376ce6db46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928163572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1928163572
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1135136495
Short name T81
Test name
Test status
Simulation time 118909997 ps
CPU time 0.99 seconds
Started May 19 01:48:33 PM PDT 24
Finished May 19 01:48:34 PM PDT 24
Peak memory 200444 kb
Host smart-5e4d5e12-9316-4b8a-a208-dd43749d5228
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135136495 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.1135136495
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1676422374
Short name T619
Test name
Test status
Simulation time 63164402 ps
CPU time 0.8 seconds
Started May 19 01:48:33 PM PDT 24
Finished May 19 01:48:35 PM PDT 24
Peak memory 200216 kb
Host smart-8b8227fc-e734-433f-bea2-5a5422178bf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676422374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1676422374
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.945526054
Short name T112
Test name
Test status
Simulation time 224705116 ps
CPU time 1.62 seconds
Started May 19 01:48:35 PM PDT 24
Finished May 19 01:48:39 PM PDT 24
Peak memory 200584 kb
Host smart-bb31b3ca-9390-4d45-8098-490c6b0fabd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945526054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_sa
me_csr_outstanding.945526054
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.4160871211
Short name T80
Test name
Test status
Simulation time 157124499 ps
CPU time 2.3 seconds
Started May 19 01:48:37 PM PDT 24
Finished May 19 01:48:42 PM PDT 24
Peak memory 208740 kb
Host smart-d0c4ed4d-f945-47ae-bc0e-4e63720f8e85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160871211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.4160871211
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.934139375
Short name T125
Test name
Test status
Simulation time 596085912 ps
CPU time 2.09 seconds
Started May 19 01:48:38 PM PDT 24
Finished May 19 01:48:44 PM PDT 24
Peak memory 200612 kb
Host smart-768336a5-85cd-42be-90ea-6a0e71918cae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934139375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.934139375
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1087270366
Short name T553
Test name
Test status
Simulation time 126666743 ps
CPU time 1.33 seconds
Started May 19 01:48:39 PM PDT 24
Finished May 19 01:48:44 PM PDT 24
Peak memory 208672 kb
Host smart-4034d339-da6a-4f20-99bd-c0e1bcfe60ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087270366 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1087270366
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3830827584
Short name T585
Test name
Test status
Simulation time 60773389 ps
CPU time 0.76 seconds
Started May 19 01:48:32 PM PDT 24
Finished May 19 01:48:34 PM PDT 24
Peak memory 200284 kb
Host smart-64a87b1a-6b25-4c02-a42c-1f64d6e8580d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830827584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3830827584
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1971105014
Short name T607
Test name
Test status
Simulation time 152528434 ps
CPU time 1.16 seconds
Started May 19 01:48:31 PM PDT 24
Finished May 19 01:48:33 PM PDT 24
Peak memory 200420 kb
Host smart-0d99754b-290b-44a3-909d-e55a98a984e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971105014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1971105014
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.847816742
Short name T601
Test name
Test status
Simulation time 118071068 ps
CPU time 1.27 seconds
Started May 19 01:48:31 PM PDT 24
Finished May 19 01:48:33 PM PDT 24
Peak memory 210600 kb
Host smart-ffd18db7-83f5-4f2c-a125-1fba6358315e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847816742 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.847816742
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.863886320
Short name T539
Test name
Test status
Simulation time 78743746 ps
CPU time 0.8 seconds
Started May 19 01:48:33 PM PDT 24
Finished May 19 01:48:34 PM PDT 24
Peak memory 200264 kb
Host smart-f115829d-522a-45f8-af5f-11ad89d43280
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863886320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.863886320
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.384431357
Short name T604
Test name
Test status
Simulation time 79413180 ps
CPU time 0.98 seconds
Started May 19 01:48:36 PM PDT 24
Finished May 19 01:48:39 PM PDT 24
Peak memory 200360 kb
Host smart-c3982bf1-b787-4c48-908e-0318c4210859
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384431357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.384431357
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1691019779
Short name T565
Test name
Test status
Simulation time 115275705 ps
CPU time 1.82 seconds
Started May 19 01:48:34 PM PDT 24
Finished May 19 01:48:38 PM PDT 24
Peak memory 208768 kb
Host smart-540441c0-5262-4ef4-b874-5ccbbb0aac40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691019779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1691019779
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.4275689235
Short name T147
Test name
Test status
Simulation time 420165965 ps
CPU time 1.77 seconds
Started May 19 01:48:35 PM PDT 24
Finished May 19 01:48:39 PM PDT 24
Peak memory 200580 kb
Host smart-a5bb665a-81bc-491a-aa8a-dfa17bcf5079
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275689235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.4275689235
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.75190717
Short name T593
Test name
Test status
Simulation time 194939859 ps
CPU time 1.82 seconds
Started May 19 01:48:34 PM PDT 24
Finished May 19 01:48:38 PM PDT 24
Peak memory 208916 kb
Host smart-34c32498-3d64-4ecb-91fe-e0f47ce52e69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75190717 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.75190717
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.165769486
Short name T555
Test name
Test status
Simulation time 80313707 ps
CPU time 0.83 seconds
Started May 19 01:48:38 PM PDT 24
Finished May 19 01:48:43 PM PDT 24
Peak memory 200352 kb
Host smart-b2c1826e-6a2d-4653-a8aa-c84fc43e8473
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165769486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.165769486
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2149887747
Short name T115
Test name
Test status
Simulation time 69827202 ps
CPU time 0.94 seconds
Started May 19 01:48:30 PM PDT 24
Finished May 19 01:48:32 PM PDT 24
Peak memory 200388 kb
Host smart-aabb1e12-6284-4cd9-bce1-b0361ce5201c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149887747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2149887747
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1685988331
Short name T556
Test name
Test status
Simulation time 180033413 ps
CPU time 2.51 seconds
Started May 19 01:48:36 PM PDT 24
Finished May 19 01:48:41 PM PDT 24
Peak memory 208760 kb
Host smart-b10f75fb-b7e7-47b3-ab49-43fb36ae9a2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685988331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1685988331
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2112644067
Short name T146
Test name
Test status
Simulation time 799782873 ps
CPU time 3.04 seconds
Started May 19 01:48:31 PM PDT 24
Finished May 19 01:48:35 PM PDT 24
Peak memory 200608 kb
Host smart-2bcd7818-7d74-448d-8bab-d951915a70a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112644067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2112644067
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2969406656
Short name T76
Test name
Test status
Simulation time 158034906 ps
CPU time 1.52 seconds
Started May 19 01:48:31 PM PDT 24
Finished May 19 01:48:33 PM PDT 24
Peak memory 208804 kb
Host smart-da87b477-2fb2-4de6-986b-fe29f7ff7097
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969406656 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2969406656
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.4158278959
Short name T102
Test name
Test status
Simulation time 85648078 ps
CPU time 0.88 seconds
Started May 19 01:48:35 PM PDT 24
Finished May 19 01:48:38 PM PDT 24
Peak memory 200320 kb
Host smart-28d2afc2-a215-4e27-9c96-6c988efe85a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158278959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.4158278959
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3567946657
Short name T572
Test name
Test status
Simulation time 185119934 ps
CPU time 1.46 seconds
Started May 19 01:48:34 PM PDT 24
Finished May 19 01:48:38 PM PDT 24
Peak memory 200656 kb
Host smart-057a90d7-314b-436d-865d-bc06bf03f6b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567946657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3567946657
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2204788556
Short name T548
Test name
Test status
Simulation time 274704140 ps
CPU time 2.03 seconds
Started May 19 01:48:32 PM PDT 24
Finished May 19 01:48:35 PM PDT 24
Peak memory 208796 kb
Host smart-c969701f-65b6-4351-bc48-43fd5ea0cc79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204788556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2204788556
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3805970277
Short name T611
Test name
Test status
Simulation time 420581438 ps
CPU time 1.82 seconds
Started May 19 01:48:40 PM PDT 24
Finished May 19 01:48:45 PM PDT 24
Peak memory 200608 kb
Host smart-c8d8815d-7b16-4349-8d20-f854be09e296
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805970277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3805970277
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1385815284
Short name T579
Test name
Test status
Simulation time 203496479 ps
CPU time 1.32 seconds
Started May 19 01:48:40 PM PDT 24
Finished May 19 01:48:45 PM PDT 24
Peak memory 208764 kb
Host smart-a245571b-c4c6-43ca-950a-6cade6cbd476
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385815284 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1385815284
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3480102195
Short name T592
Test name
Test status
Simulation time 88080227 ps
CPU time 0.91 seconds
Started May 19 01:48:36 PM PDT 24
Finished May 19 01:48:40 PM PDT 24
Peak memory 200248 kb
Host smart-00092e31-e1bd-42d2-ad4f-a3fbc1fc7d21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480102195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3480102195
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3875798970
Short name T597
Test name
Test status
Simulation time 127782876 ps
CPU time 1.2 seconds
Started May 19 01:48:35 PM PDT 24
Finished May 19 01:48:39 PM PDT 24
Peak memory 200408 kb
Host smart-7b3be2b7-aab8-43c6-afc6-5e7330519584
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875798970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3875798970
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3213072026
Short name T120
Test name
Test status
Simulation time 173490002 ps
CPU time 2.26 seconds
Started May 19 01:48:32 PM PDT 24
Finished May 19 01:48:35 PM PDT 24
Peak memory 208724 kb
Host smart-3cd73a1d-b902-4f3a-ab17-4bc88080387c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213072026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3213072026
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3461655907
Short name T78
Test name
Test status
Simulation time 888248035 ps
CPU time 3.23 seconds
Started May 19 01:48:35 PM PDT 24
Finished May 19 01:48:41 PM PDT 24
Peak memory 200624 kb
Host smart-cb63b582-c5c1-4384-9c3d-2b07bb3d0538
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461655907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3461655907
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.18547448
Short name T566
Test name
Test status
Simulation time 205704078 ps
CPU time 1.6 seconds
Started May 19 01:48:21 PM PDT 24
Finished May 19 01:48:24 PM PDT 24
Peak memory 200572 kb
Host smart-b4d12607-3b34-48d2-9f14-7f204d761655
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18547448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.18547448
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3741603374
Short name T542
Test name
Test status
Simulation time 814657133 ps
CPU time 4.47 seconds
Started May 19 01:48:25 PM PDT 24
Finished May 19 01:48:31 PM PDT 24
Peak memory 200504 kb
Host smart-c3259270-db86-4c8f-aacd-336060ebdd1c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741603374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
741603374
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.111246760
Short name T540
Test name
Test status
Simulation time 94447770 ps
CPU time 0.8 seconds
Started May 19 01:48:23 PM PDT 24
Finished May 19 01:48:25 PM PDT 24
Peak memory 200360 kb
Host smart-725f6cf4-fd72-4124-8376-82c250f874aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111246760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.111246760
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.807764520
Short name T560
Test name
Test status
Simulation time 115496558 ps
CPU time 1.09 seconds
Started May 19 01:48:19 PM PDT 24
Finished May 19 01:48:20 PM PDT 24
Peak memory 208792 kb
Host smart-e744e946-7015-4513-8b1d-9cf936df75bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807764520 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.807764520
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2752774365
Short name T595
Test name
Test status
Simulation time 63659964 ps
CPU time 0.79 seconds
Started May 19 01:48:26 PM PDT 24
Finished May 19 01:48:28 PM PDT 24
Peak memory 200340 kb
Host smart-f8f56465-a804-42fc-861d-33ba62259f10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752774365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2752774365
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3264327947
Short name T600
Test name
Test status
Simulation time 267115676 ps
CPU time 1.58 seconds
Started May 19 01:48:27 PM PDT 24
Finished May 19 01:48:30 PM PDT 24
Peak memory 200508 kb
Host smart-7d530ca5-8c7c-4b13-b7db-48253fcbaf0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264327947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3264327947
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.4045198918
Short name T544
Test name
Test status
Simulation time 113373977 ps
CPU time 1.62 seconds
Started May 19 01:48:28 PM PDT 24
Finished May 19 01:48:31 PM PDT 24
Peak memory 209068 kb
Host smart-915ef51b-4eed-4d3e-a62d-dbab42db3bfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045198918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.4045198918
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3986434276
Short name T569
Test name
Test status
Simulation time 407412276 ps
CPU time 1.74 seconds
Started May 19 01:48:18 PM PDT 24
Finished May 19 01:48:21 PM PDT 24
Peak memory 200596 kb
Host smart-d41d9ec5-73f6-4d06-8b39-ff22daefd09f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986434276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3986434276
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3327356343
Short name T564
Test name
Test status
Simulation time 212207545 ps
CPU time 1.63 seconds
Started May 19 01:48:25 PM PDT 24
Finished May 19 01:48:28 PM PDT 24
Peak memory 200556 kb
Host smart-3bf6551c-a0e1-42b6-8d60-03681bc1dced
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327356343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
327356343
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3701097516
Short name T545
Test name
Test status
Simulation time 803490528 ps
CPU time 4.5 seconds
Started May 19 01:48:22 PM PDT 24
Finished May 19 01:48:27 PM PDT 24
Peak memory 200588 kb
Host smart-6b40347a-4247-47fe-a31b-4f54e6723e56
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701097516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3
701097516
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.431596182
Short name T582
Test name
Test status
Simulation time 98199060 ps
CPU time 0.85 seconds
Started May 19 01:48:25 PM PDT 24
Finished May 19 01:48:26 PM PDT 24
Peak memory 200292 kb
Host smart-c1d8daa1-cd2b-4291-a053-67443318ce3d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431596182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.431596182
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3930753276
Short name T578
Test name
Test status
Simulation time 200108121 ps
CPU time 1.4 seconds
Started May 19 01:48:26 PM PDT 24
Finished May 19 01:48:28 PM PDT 24
Peak memory 208704 kb
Host smart-78ccc2b9-f0e4-44b5-9d1c-0de1db64a91b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930753276 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3930753276
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.897650417
Short name T620
Test name
Test status
Simulation time 60692800 ps
CPU time 0.88 seconds
Started May 19 01:48:25 PM PDT 24
Finished May 19 01:48:26 PM PDT 24
Peak memory 200292 kb
Host smart-c892f093-bafc-4dba-af58-4248dc4285c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897650417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.897650417
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.12673932
Short name T609
Test name
Test status
Simulation time 252489495 ps
CPU time 1.58 seconds
Started May 19 01:48:25 PM PDT 24
Finished May 19 01:48:28 PM PDT 24
Peak memory 200540 kb
Host smart-34fbb7e4-ae0e-4164-87b7-917cd9ec27fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12673932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_same
_csr_outstanding.12673932
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1080971550
Short name T570
Test name
Test status
Simulation time 500447894 ps
CPU time 3.33 seconds
Started May 19 01:48:23 PM PDT 24
Finished May 19 01:48:28 PM PDT 24
Peak memory 208708 kb
Host smart-39a17176-a807-4216-82e8-61adf441cea0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080971550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1080971550
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2425400096
Short name T591
Test name
Test status
Simulation time 901918524 ps
CPU time 3.15 seconds
Started May 19 01:48:23 PM PDT 24
Finished May 19 01:48:28 PM PDT 24
Peak memory 200560 kb
Host smart-7f3c244f-2c5c-451f-a00e-206d2a0b2259
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425400096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2425400096
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2802917160
Short name T608
Test name
Test status
Simulation time 228083238 ps
CPU time 1.59 seconds
Started May 19 01:48:23 PM PDT 24
Finished May 19 01:48:25 PM PDT 24
Peak memory 200500 kb
Host smart-8b25cc14-7008-46df-998b-c64ae248e7cf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802917160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
802917160
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.232979024
Short name T567
Test name
Test status
Simulation time 477532137 ps
CPU time 5.79 seconds
Started May 19 01:48:34 PM PDT 24
Finished May 19 01:48:41 PM PDT 24
Peak memory 200564 kb
Host smart-5bb10645-81e7-4a44-b4c5-7907889d977d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232979024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.232979024
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2304831110
Short name T603
Test name
Test status
Simulation time 95487145 ps
CPU time 0.89 seconds
Started May 19 01:48:24 PM PDT 24
Finished May 19 01:48:26 PM PDT 24
Peak memory 200228 kb
Host smart-9fbfbe82-8f4b-4088-a4d0-9c3d835e4089
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304831110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
304831110
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1881580632
Short name T586
Test name
Test status
Simulation time 134026418 ps
CPU time 1.06 seconds
Started May 19 01:48:26 PM PDT 24
Finished May 19 01:48:28 PM PDT 24
Peak memory 200456 kb
Host smart-7982ebbe-88f9-4f49-a91a-d572a1f87b9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881580632 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1881580632
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2009145050
Short name T615
Test name
Test status
Simulation time 59615375 ps
CPU time 0.83 seconds
Started May 19 01:48:23 PM PDT 24
Finished May 19 01:48:25 PM PDT 24
Peak memory 200352 kb
Host smart-e88cef66-8bc5-47de-9de4-f5141fd90e54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009145050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2009145050
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2702338423
Short name T119
Test name
Test status
Simulation time 85447946 ps
CPU time 0.98 seconds
Started May 19 01:48:25 PM PDT 24
Finished May 19 01:48:26 PM PDT 24
Peak memory 200420 kb
Host smart-bd373dfa-c8f8-4056-add7-f4d655dfbc5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702338423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.2702338423
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.247883644
Short name T97
Test name
Test status
Simulation time 308664835 ps
CPU time 2.11 seconds
Started May 19 01:48:25 PM PDT 24
Finished May 19 01:48:28 PM PDT 24
Peak memory 200556 kb
Host smart-d9f3dbbe-26bb-4180-8a52-82baded035a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247883644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.247883644
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.719528077
Short name T576
Test name
Test status
Simulation time 484733350 ps
CPU time 1.85 seconds
Started May 19 01:48:23 PM PDT 24
Finished May 19 01:48:26 PM PDT 24
Peak memory 200636 kb
Host smart-24d0abba-c543-4b3a-8b66-8d539975a099
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719528077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
719528077
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3613895206
Short name T573
Test name
Test status
Simulation time 131249985 ps
CPU time 1.12 seconds
Started May 19 01:48:23 PM PDT 24
Finished May 19 01:48:26 PM PDT 24
Peak memory 209204 kb
Host smart-2df40e75-37c5-4909-840d-7494ee83de00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613895206 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3613895206
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2974344020
Short name T552
Test name
Test status
Simulation time 71207539 ps
CPU time 0.77 seconds
Started May 19 01:48:27 PM PDT 24
Finished May 19 01:48:29 PM PDT 24
Peak memory 200148 kb
Host smart-6218d795-f8ef-430e-8edf-86306ab028e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974344020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2974344020
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4282791501
Short name T584
Test name
Test status
Simulation time 85702573 ps
CPU time 0.99 seconds
Started May 19 01:48:28 PM PDT 24
Finished May 19 01:48:30 PM PDT 24
Peak memory 200376 kb
Host smart-6b2c5cdb-3ca1-46c9-9c3e-a3d2c0f2e2c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282791501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.4282791501
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3242375309
Short name T558
Test name
Test status
Simulation time 188777627 ps
CPU time 2.45 seconds
Started May 19 01:48:23 PM PDT 24
Finished May 19 01:48:26 PM PDT 24
Peak memory 208800 kb
Host smart-42a4e554-2237-4de1-8662-84f9be71efe5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242375309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3242375309
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1618311936
Short name T123
Test name
Test status
Simulation time 808542409 ps
CPU time 2.78 seconds
Started May 19 01:48:26 PM PDT 24
Finished May 19 01:48:30 PM PDT 24
Peak memory 200580 kb
Host smart-59376304-4daa-479e-a52f-77c27bb60f9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618311936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1618311936
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2142355134
Short name T594
Test name
Test status
Simulation time 179404870 ps
CPU time 1.18 seconds
Started May 19 01:48:34 PM PDT 24
Finished May 19 01:48:37 PM PDT 24
Peak memory 200468 kb
Host smart-cdfc70d7-8a57-4217-aaef-cdb4dd915a5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142355134 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2142355134
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3950660761
Short name T550
Test name
Test status
Simulation time 65938360 ps
CPU time 0.79 seconds
Started May 19 01:48:28 PM PDT 24
Finished May 19 01:48:31 PM PDT 24
Peak memory 200524 kb
Host smart-81aced2d-fa57-486a-901a-734bbe2203b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950660761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3950660761
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1054065411
Short name T117
Test name
Test status
Simulation time 87123558 ps
CPU time 1.02 seconds
Started May 19 01:48:33 PM PDT 24
Finished May 19 01:48:36 PM PDT 24
Peak memory 200388 kb
Host smart-3ca6913c-025b-469c-a59f-588ec47a5416
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054065411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1054065411
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2034864378
Short name T126
Test name
Test status
Simulation time 226076564 ps
CPU time 1.82 seconds
Started May 19 01:48:27 PM PDT 24
Finished May 19 01:48:30 PM PDT 24
Peak memory 208708 kb
Host smart-40196c03-a321-407f-9e8f-00e74bf817dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034864378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2034864378
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2790209944
Short name T148
Test name
Test status
Simulation time 802754161 ps
CPU time 2.55 seconds
Started May 19 01:48:27 PM PDT 24
Finished May 19 01:48:30 PM PDT 24
Peak memory 200472 kb
Host smart-882aebbe-aad7-454a-b0c2-eca886d2ba3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790209944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.2790209944
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3135645147
Short name T575
Test name
Test status
Simulation time 188523397 ps
CPU time 1.35 seconds
Started May 19 01:48:27 PM PDT 24
Finished May 19 01:48:29 PM PDT 24
Peak memory 208592 kb
Host smart-f2e6d3e1-e9e7-4a0a-b106-5029b0517f92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135645147 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3135645147
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1114201428
Short name T581
Test name
Test status
Simulation time 62082202 ps
CPU time 0.78 seconds
Started May 19 01:48:36 PM PDT 24
Finished May 19 01:48:40 PM PDT 24
Peak memory 200300 kb
Host smart-b7a6de93-4fc2-43c4-b6ae-7033b79922b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114201428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1114201428
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1605060786
Short name T614
Test name
Test status
Simulation time 112647807 ps
CPU time 1.09 seconds
Started May 19 01:48:29 PM PDT 24
Finished May 19 01:48:32 PM PDT 24
Peak memory 200304 kb
Host smart-3a9d455a-97cd-4d5a-93de-69fd1830846e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605060786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1605060786
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.876430216
Short name T559
Test name
Test status
Simulation time 172120771 ps
CPU time 2.61 seconds
Started May 19 01:48:28 PM PDT 24
Finished May 19 01:48:32 PM PDT 24
Peak memory 212256 kb
Host smart-fee7c96d-17be-4c67-93c4-286bc6ca36f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876430216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.876430216
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1250336487
Short name T100
Test name
Test status
Simulation time 879506107 ps
CPU time 3.29 seconds
Started May 19 01:48:29 PM PDT 24
Finished May 19 01:48:34 PM PDT 24
Peak memory 200628 kb
Host smart-9578f57b-4cc9-49c5-9621-f795ed7226ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250336487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.1250336487
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1242348563
Short name T590
Test name
Test status
Simulation time 120247564 ps
CPU time 1.2 seconds
Started May 19 01:48:29 PM PDT 24
Finished May 19 01:48:32 PM PDT 24
Peak memory 208836 kb
Host smart-9c6a3de9-ab14-41b7-95fe-4f90b9ef27b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242348563 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1242348563
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2009942729
Short name T562
Test name
Test status
Simulation time 61606379 ps
CPU time 0.84 seconds
Started May 19 01:48:28 PM PDT 24
Finished May 19 01:48:31 PM PDT 24
Peak memory 200328 kb
Host smart-0a334037-5d55-473d-bac0-cc410ab59216
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009942729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.2009942729
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1098077943
Short name T599
Test name
Test status
Simulation time 71825314 ps
CPU time 0.92 seconds
Started May 19 01:48:30 PM PDT 24
Finished May 19 01:48:32 PM PDT 24
Peak memory 200632 kb
Host smart-eb09d032-e3f9-4c3d-9792-3637a22b9518
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098077943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.1098077943
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1731676046
Short name T583
Test name
Test status
Simulation time 524660791 ps
CPU time 3.33 seconds
Started May 19 01:48:29 PM PDT 24
Finished May 19 01:48:33 PM PDT 24
Peak memory 211372 kb
Host smart-1a23213f-fef4-4681-97ac-7b578c3b0f25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731676046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1731676046
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.395840478
Short name T574
Test name
Test status
Simulation time 414081425 ps
CPU time 1.89 seconds
Started May 19 01:48:35 PM PDT 24
Finished May 19 01:48:40 PM PDT 24
Peak memory 200588 kb
Host smart-3b187cdc-c74d-40c6-b7e3-23b9cb07cfb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395840478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
395840478
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.4267486841
Short name T554
Test name
Test status
Simulation time 122362800 ps
CPU time 1.03 seconds
Started May 19 01:48:30 PM PDT 24
Finished May 19 01:48:32 PM PDT 24
Peak memory 200352 kb
Host smart-833ffc3f-b59c-4648-8ed8-4cf5460920e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267486841 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.4267486841
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1494057006
Short name T549
Test name
Test status
Simulation time 91272031 ps
CPU time 0.88 seconds
Started May 19 01:48:28 PM PDT 24
Finished May 19 01:48:30 PM PDT 24
Peak memory 200232 kb
Host smart-375ae8b2-3eca-42eb-837e-3b5359294fe0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494057006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1494057006
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3269894957
Short name T111
Test name
Test status
Simulation time 124416520 ps
CPU time 1.23 seconds
Started May 19 01:48:28 PM PDT 24
Finished May 19 01:48:30 PM PDT 24
Peak memory 200592 kb
Host smart-29cb0b86-d7a2-4e4e-8bb3-d02829b347eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269894957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3269894957
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.667901375
Short name T121
Test name
Test status
Simulation time 625957282 ps
CPU time 3.82 seconds
Started May 19 01:48:36 PM PDT 24
Finished May 19 01:48:43 PM PDT 24
Peak memory 208808 kb
Host smart-ae428ca2-c690-4675-9439-14d53447663a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667901375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.667901375
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1761841457
Short name T610
Test name
Test status
Simulation time 963576060 ps
CPU time 3.18 seconds
Started May 19 01:48:36 PM PDT 24
Finished May 19 01:48:42 PM PDT 24
Peak memory 200544 kb
Host smart-6437dd8c-0b58-4c22-a235-d77becbb2752
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761841457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1761841457
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2193872915
Short name T30
Test name
Test status
Simulation time 88112495 ps
CPU time 0.86 seconds
Started May 19 01:32:17 PM PDT 24
Finished May 19 01:32:19 PM PDT 24
Peak memory 200252 kb
Host smart-2db10a7f-f629-4586-b12c-91da35232745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193872915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2193872915
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1383057480
Short name T44
Test name
Test status
Simulation time 2358974077 ps
CPU time 8.28 seconds
Started May 19 01:32:13 PM PDT 24
Finished May 19 01:32:21 PM PDT 24
Peak memory 218196 kb
Host smart-05c822dc-b4f7-4dc0-aa5a-35e179f44b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383057480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1383057480
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3540747075
Short name T408
Test name
Test status
Simulation time 82366587 ps
CPU time 0.77 seconds
Started May 19 01:32:21 PM PDT 24
Finished May 19 01:32:23 PM PDT 24
Peak memory 200300 kb
Host smart-f52e08e4-60d9-4e6a-bcd7-f730666a7338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540747075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3540747075
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.2891252948
Short name T107
Test name
Test status
Simulation time 1519219300 ps
CPU time 6.07 seconds
Started May 19 01:32:13 PM PDT 24
Finished May 19 01:32:19 PM PDT 24
Peak memory 200644 kb
Host smart-b5ba80a1-0f51-48c6-85ee-5cee4cbaf0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891252948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2891252948
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.4023740238
Short name T86
Test name
Test status
Simulation time 17603999625 ps
CPU time 26.58 seconds
Started May 19 01:32:15 PM PDT 24
Finished May 19 01:32:42 PM PDT 24
Peak memory 217732 kb
Host smart-0a8ca061-8405-4ace-9f02-893b06019f5b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023740238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.4023740238
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.4232996519
Short name T275
Test name
Test status
Simulation time 170525923 ps
CPU time 1.27 seconds
Started May 19 01:32:27 PM PDT 24
Finished May 19 01:32:30 PM PDT 24
Peak memory 200444 kb
Host smart-fc71732f-98aa-48eb-a291-f60ad77f166a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232996519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.4232996519
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.780702338
Short name T200
Test name
Test status
Simulation time 200290429 ps
CPU time 1.37 seconds
Started May 19 01:32:18 PM PDT 24
Finished May 19 01:32:20 PM PDT 24
Peak memory 200632 kb
Host smart-a398e715-fd9d-4263-a898-017c53ef72d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780702338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.780702338
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.2337870153
Short name T130
Test name
Test status
Simulation time 8159802516 ps
CPU time 26.78 seconds
Started May 19 01:32:28 PM PDT 24
Finished May 19 01:32:57 PM PDT 24
Peak memory 200300 kb
Host smart-352d2a12-49de-4d37-8d74-2b760aedb851
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337870153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2337870153
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.100980951
Short name T437
Test name
Test status
Simulation time 132779660 ps
CPU time 1.67 seconds
Started May 19 01:32:31 PM PDT 24
Finished May 19 01:32:35 PM PDT 24
Peak memory 200424 kb
Host smart-5e4e02c1-ec2d-4b3d-af18-dcde51cd5be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100980951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.100980951
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3193848335
Short name T234
Test name
Test status
Simulation time 118955325 ps
CPU time 1.06 seconds
Started May 19 01:32:17 PM PDT 24
Finished May 19 01:32:19 PM PDT 24
Peak memory 200440 kb
Host smart-b9650fb8-70e9-4651-b857-fe7f9ca77aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193848335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3193848335
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.96792191
Short name T180
Test name
Test status
Simulation time 69815059 ps
CPU time 0.73 seconds
Started May 19 01:32:17 PM PDT 24
Finished May 19 01:32:18 PM PDT 24
Peak memory 200276 kb
Host smart-f63e7f44-afa7-4973-8e92-c5a41072d0c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96792191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.96792191
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1535442105
Short name T72
Test name
Test status
Simulation time 1900597369 ps
CPU time 6.9 seconds
Started May 19 01:32:33 PM PDT 24
Finished May 19 01:32:42 PM PDT 24
Peak memory 218060 kb
Host smart-b09b740c-9917-4e56-95e4-d88c68b56a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535442105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1535442105
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.856006578
Short name T333
Test name
Test status
Simulation time 244525392 ps
CPU time 1.09 seconds
Started May 19 01:32:16 PM PDT 24
Finished May 19 01:32:18 PM PDT 24
Peak memory 217540 kb
Host smart-bcf51db4-bd19-4040-8826-7d1be828e9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856006578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.856006578
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3703226061
Short name T370
Test name
Test status
Simulation time 1381837012 ps
CPU time 5.7 seconds
Started May 19 01:32:16 PM PDT 24
Finished May 19 01:32:22 PM PDT 24
Peak memory 200600 kb
Host smart-8f050819-70ab-4e35-89e2-527bb6b518cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703226061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3703226061
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1956617115
Short name T83
Test name
Test status
Simulation time 16603248118 ps
CPU time 25.74 seconds
Started May 19 01:32:33 PM PDT 24
Finished May 19 01:33:01 PM PDT 24
Peak memory 218532 kb
Host smart-66311010-5e8b-4822-af6c-799a6a40ced6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956617115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1956617115
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.2127323194
Short name T7
Test name
Test status
Simulation time 109582371 ps
CPU time 1.19 seconds
Started May 19 01:32:17 PM PDT 24
Finished May 19 01:32:20 PM PDT 24
Peak memory 200604 kb
Host smart-b81794d3-94de-4021-b9cf-5d7695320376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127323194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2127323194
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1291413091
Short name T210
Test name
Test status
Simulation time 1299161731 ps
CPU time 5.72 seconds
Started May 19 01:32:31 PM PDT 24
Finished May 19 01:32:40 PM PDT 24
Peak memory 200284 kb
Host smart-62a05d08-8646-489a-b4c2-1dd3ec912230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291413091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1291413091
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3344654502
Short name T248
Test name
Test status
Simulation time 376069808 ps
CPU time 2.5 seconds
Started May 19 01:32:29 PM PDT 24
Finished May 19 01:32:34 PM PDT 24
Peak memory 200440 kb
Host smart-7a183b52-a51a-47d8-bbc3-ffe0e837aed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344654502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3344654502
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.161197908
Short name T452
Test name
Test status
Simulation time 171285827 ps
CPU time 1.3 seconds
Started May 19 01:32:28 PM PDT 24
Finished May 19 01:32:31 PM PDT 24
Peak memory 200660 kb
Host smart-7c216ad1-53e0-427b-9cd9-aba6812aa8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161197908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.161197908
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.582715103
Short name T404
Test name
Test status
Simulation time 70533902 ps
CPU time 0.75 seconds
Started May 19 01:32:34 PM PDT 24
Finished May 19 01:32:38 PM PDT 24
Peak memory 200284 kb
Host smart-a1971e71-6e67-4f57-bb0f-a9ef50c63c66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582715103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.582715103
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.451157595
Short name T357
Test name
Test status
Simulation time 244529771 ps
CPU time 1.01 seconds
Started May 19 01:32:35 PM PDT 24
Finished May 19 01:32:39 PM PDT 24
Peak memory 217660 kb
Host smart-a205cd85-7bf9-4984-be74-9e64b62c2ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451157595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.451157595
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.4105798142
Short name T406
Test name
Test status
Simulation time 167204760 ps
CPU time 0.83 seconds
Started May 19 01:32:26 PM PDT 24
Finished May 19 01:32:28 PM PDT 24
Peak memory 200296 kb
Host smart-3ffd1826-b2c2-447d-aed2-9e57e4a49454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105798142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.4105798142
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.654356655
Short name T321
Test name
Test status
Simulation time 811619413 ps
CPU time 4.11 seconds
Started May 19 01:32:24 PM PDT 24
Finished May 19 01:32:30 PM PDT 24
Peak memory 200648 kb
Host smart-230e5b3c-8c1a-4d64-b3f4-f7a718bb036a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654356655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.654356655
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2259538953
Short name T149
Test name
Test status
Simulation time 155855597 ps
CPU time 1.2 seconds
Started May 19 01:32:38 PM PDT 24
Finished May 19 01:32:40 PM PDT 24
Peak memory 200436 kb
Host smart-21222d1e-657f-4eb6-97db-85b326fd4c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259538953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2259538953
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1608479278
Short name T224
Test name
Test status
Simulation time 185038426 ps
CPU time 1.45 seconds
Started May 19 01:32:25 PM PDT 24
Finished May 19 01:32:28 PM PDT 24
Peak memory 200684 kb
Host smart-4fbd38d5-4597-47ef-94fb-5984585702ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608479278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1608479278
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.4196676498
Short name T505
Test name
Test status
Simulation time 7506680743 ps
CPU time 28.74 seconds
Started May 19 01:32:35 PM PDT 24
Finished May 19 01:33:06 PM PDT 24
Peak memory 210148 kb
Host smart-58b350fb-9938-4fef-822d-4dc7ab6fe056
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196676498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.4196676498
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1113478569
Short name T189
Test name
Test status
Simulation time 146581021 ps
CPU time 1.71 seconds
Started May 19 01:32:28 PM PDT 24
Finished May 19 01:32:31 PM PDT 24
Peak memory 200416 kb
Host smart-03f13ac1-ddae-4762-af82-3fd8534cd346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113478569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1113478569
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.1825871374
Short name T281
Test name
Test status
Simulation time 73111156 ps
CPU time 0.81 seconds
Started May 19 01:32:23 PM PDT 24
Finished May 19 01:32:26 PM PDT 24
Peak memory 200372 kb
Host smart-7792084b-4b69-4826-bc5d-d337f4dfaded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825871374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.1825871374
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.3348834805
Short name T410
Test name
Test status
Simulation time 82910275 ps
CPU time 0.8 seconds
Started May 19 01:32:30 PM PDT 24
Finished May 19 01:32:33 PM PDT 24
Peak memory 200328 kb
Host smart-aac40ac9-2cb7-45f3-9be7-24a7879e0765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348834805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3348834805
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3549800685
Short name T498
Test name
Test status
Simulation time 1226258503 ps
CPU time 5.82 seconds
Started May 19 01:32:30 PM PDT 24
Finished May 19 01:32:38 PM PDT 24
Peak memory 222188 kb
Host smart-b1026043-a195-49c7-ad30-5042d5a1ac60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549800685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3549800685
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3586924355
Short name T172
Test name
Test status
Simulation time 243200448 ps
CPU time 1.16 seconds
Started May 19 01:32:29 PM PDT 24
Finished May 19 01:32:32 PM PDT 24
Peak memory 217604 kb
Host smart-4ea5f834-7ea2-4bba-b236-06186eb3f646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586924355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3586924355
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.3615942542
Short name T421
Test name
Test status
Simulation time 201696038 ps
CPU time 0.9 seconds
Started May 19 01:32:26 PM PDT 24
Finished May 19 01:32:28 PM PDT 24
Peak memory 200300 kb
Host smart-0ea75b60-48e8-4f0c-8f5f-b7d7c569ce76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615942542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3615942542
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1248419006
Short name T348
Test name
Test status
Simulation time 1345913159 ps
CPU time 5.48 seconds
Started May 19 01:32:30 PM PDT 24
Finished May 19 01:32:38 PM PDT 24
Peak memory 200716 kb
Host smart-8a346b92-5f9d-4b6f-bada-627f38150173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248419006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1248419006
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2306949419
Short name T163
Test name
Test status
Simulation time 146874902 ps
CPU time 1.2 seconds
Started May 19 01:32:30 PM PDT 24
Finished May 19 01:32:34 PM PDT 24
Peak memory 200444 kb
Host smart-b401f7f7-9270-42e7-ad90-05bf5fc8dfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306949419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2306949419
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2592088137
Short name T143
Test name
Test status
Simulation time 214666111 ps
CPU time 1.48 seconds
Started May 19 01:32:26 PM PDT 24
Finished May 19 01:32:29 PM PDT 24
Peak memory 200636 kb
Host smart-e60923da-d9a5-40b0-9464-63182e952c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592088137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2592088137
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1526332338
Short name T242
Test name
Test status
Simulation time 273416857 ps
CPU time 1.93 seconds
Started May 19 01:32:39 PM PDT 24
Finished May 19 01:32:43 PM PDT 24
Peak memory 200648 kb
Host smart-59262854-fb69-4092-b01e-557aff2f0a95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526332338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1526332338
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.3633094481
Short name T93
Test name
Test status
Simulation time 141577503 ps
CPU time 1.69 seconds
Started May 19 01:32:34 PM PDT 24
Finished May 19 01:32:38 PM PDT 24
Peak memory 200468 kb
Host smart-08c89c62-fc0e-4975-84c4-7f6450cb5aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633094481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3633094481
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.902742068
Short name T484
Test name
Test status
Simulation time 301954368 ps
CPU time 1.61 seconds
Started May 19 01:32:33 PM PDT 24
Finished May 19 01:32:37 PM PDT 24
Peak memory 200696 kb
Host smart-fea9ba95-7384-4b36-b601-23fac1df599b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902742068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.902742068
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1442690630
Short name T518
Test name
Test status
Simulation time 68729812 ps
CPU time 0.77 seconds
Started May 19 01:32:34 PM PDT 24
Finished May 19 01:32:37 PM PDT 24
Peak memory 200300 kb
Host smart-e1b4fe07-3c14-4020-81d3-54106b068720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442690630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1442690630
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3530824411
Short name T133
Test name
Test status
Simulation time 1228131114 ps
CPU time 5.9 seconds
Started May 19 01:32:29 PM PDT 24
Finished May 19 01:32:38 PM PDT 24
Peak memory 218096 kb
Host smart-ac226e83-7a0d-4f16-8c84-41354900ce5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530824411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3530824411
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1669054206
Short name T392
Test name
Test status
Simulation time 243913873 ps
CPU time 1.14 seconds
Started May 19 01:32:36 PM PDT 24
Finished May 19 01:32:40 PM PDT 24
Peak memory 217500 kb
Host smart-14d3c8df-b47e-4d94-b206-1612d49bbc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669054206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1669054206
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.376611915
Short name T203
Test name
Test status
Simulation time 78898057 ps
CPU time 0.78 seconds
Started May 19 01:32:32 PM PDT 24
Finished May 19 01:32:36 PM PDT 24
Peak memory 200272 kb
Host smart-43fd6fba-3889-4d02-8e43-e1972f6c9e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376611915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.376611915
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2016544273
Short name T323
Test name
Test status
Simulation time 1564666938 ps
CPU time 6.14 seconds
Started May 19 01:32:31 PM PDT 24
Finished May 19 01:32:40 PM PDT 24
Peak memory 200600 kb
Host smart-63acd89e-fa1a-4622-850e-5c8ecc9738ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016544273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2016544273
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.4266775905
Short name T422
Test name
Test status
Simulation time 103692455 ps
CPU time 1 seconds
Started May 19 01:32:35 PM PDT 24
Finished May 19 01:32:38 PM PDT 24
Peak memory 200456 kb
Host smart-d8da3533-d66c-40e2-aece-913808473949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266775905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.4266775905
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.393948963
Short name T439
Test name
Test status
Simulation time 124948601 ps
CPU time 1.25 seconds
Started May 19 01:32:31 PM PDT 24
Finished May 19 01:32:35 PM PDT 24
Peak memory 200668 kb
Host smart-c153fd92-d887-420e-9cc1-35b059b13021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393948963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.393948963
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.582008330
Short name T329
Test name
Test status
Simulation time 9733522321 ps
CPU time 35.02 seconds
Started May 19 01:32:34 PM PDT 24
Finished May 19 01:33:12 PM PDT 24
Peak memory 200800 kb
Host smart-833c5dc4-9f9f-44ec-9423-0c2020b890e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582008330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.582008330
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2292013543
Short name T383
Test name
Test status
Simulation time 150607160 ps
CPU time 1.84 seconds
Started May 19 01:32:33 PM PDT 24
Finished May 19 01:32:38 PM PDT 24
Peak memory 200416 kb
Host smart-f956150f-0b6c-4e43-90b8-d166b3d9ad7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292013543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2292013543
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3606227895
Short name T260
Test name
Test status
Simulation time 104607901 ps
CPU time 0.92 seconds
Started May 19 01:32:34 PM PDT 24
Finished May 19 01:32:38 PM PDT 24
Peak memory 200472 kb
Host smart-df3304e1-99b4-4905-8bdf-4f09eff95ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606227895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3606227895
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.4169999010
Short name T308
Test name
Test status
Simulation time 65494193 ps
CPU time 0.76 seconds
Started May 19 01:32:36 PM PDT 24
Finished May 19 01:32:39 PM PDT 24
Peak memory 200340 kb
Host smart-674a177e-497d-46b7-bd9c-445169c3b7c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169999010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.4169999010
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3333426846
Short name T400
Test name
Test status
Simulation time 1889000181 ps
CPU time 7.31 seconds
Started May 19 01:32:38 PM PDT 24
Finished May 19 01:32:46 PM PDT 24
Peak memory 218100 kb
Host smart-a3aca06a-b006-481b-9dc2-6ed2ae5dc259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333426846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3333426846
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2482413947
Short name T135
Test name
Test status
Simulation time 244697836 ps
CPU time 1.14 seconds
Started May 19 01:32:39 PM PDT 24
Finished May 19 01:32:42 PM PDT 24
Peak memory 217656 kb
Host smart-98362d4c-7d6e-439b-a3bc-35b12a9ee5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482413947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2482413947
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2271251799
Short name T181
Test name
Test status
Simulation time 226200925 ps
CPU time 0.91 seconds
Started May 19 01:32:36 PM PDT 24
Finished May 19 01:32:39 PM PDT 24
Peak memory 200220 kb
Host smart-ea2a968c-9af3-4b76-9d11-f4303aa45cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271251799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2271251799
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2486112085
Short name T225
Test name
Test status
Simulation time 1346786125 ps
CPU time 5.85 seconds
Started May 19 01:32:34 PM PDT 24
Finished May 19 01:32:43 PM PDT 24
Peak memory 200644 kb
Host smart-2aebf071-1048-46ac-8598-8474b70bca7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486112085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2486112085
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1669380006
Short name T186
Test name
Test status
Simulation time 139703569 ps
CPU time 1.23 seconds
Started May 19 01:32:36 PM PDT 24
Finished May 19 01:32:39 PM PDT 24
Peak memory 200452 kb
Host smart-d6652574-8f64-4f75-aa5d-954c4b98e0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669380006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1669380006
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.4272705786
Short name T60
Test name
Test status
Simulation time 236281887 ps
CPU time 1.46 seconds
Started May 19 01:32:32 PM PDT 24
Finished May 19 01:32:36 PM PDT 24
Peak memory 200608 kb
Host smart-2b4c6249-df25-4d17-b773-4f344ba4c541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272705786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.4272705786
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2883248206
Short name T460
Test name
Test status
Simulation time 2417848817 ps
CPU time 11.62 seconds
Started May 19 01:32:43 PM PDT 24
Finished May 19 01:32:57 PM PDT 24
Peak memory 200828 kb
Host smart-37fc5cd0-5802-4bdc-b1b0-5d0ee3fe6f17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883248206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2883248206
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.473928436
Short name T161
Test name
Test status
Simulation time 128245444 ps
CPU time 1.55 seconds
Started May 19 01:32:32 PM PDT 24
Finished May 19 01:32:36 PM PDT 24
Peak memory 200424 kb
Host smart-a475ec28-5459-4f93-9736-d3c9843828be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473928436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.473928436
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.869891405
Short name T441
Test name
Test status
Simulation time 77402718 ps
CPU time 0.82 seconds
Started May 19 01:32:35 PM PDT 24
Finished May 19 01:32:38 PM PDT 24
Peak memory 200420 kb
Host smart-a653e02d-64c2-4304-bb7e-91125af989b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869891405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.869891405
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3714778915
Short name T309
Test name
Test status
Simulation time 64736139 ps
CPU time 0.79 seconds
Started May 19 01:32:42 PM PDT 24
Finished May 19 01:32:45 PM PDT 24
Peak memory 200288 kb
Host smart-b20e0957-0351-4c48-af89-49087b3fcf34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714778915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3714778915
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3452181486
Short name T41
Test name
Test status
Simulation time 1879010566 ps
CPU time 8.19 seconds
Started May 19 01:32:40 PM PDT 24
Finished May 19 01:32:51 PM PDT 24
Peak memory 218132 kb
Host smart-14b6584c-f018-449c-bb29-c8fe4acf693d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452181486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3452181486
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1507504385
Short name T247
Test name
Test status
Simulation time 244318678 ps
CPU time 1.15 seconds
Started May 19 01:32:34 PM PDT 24
Finished May 19 01:32:38 PM PDT 24
Peak memory 217556 kb
Host smart-3f155e3e-337b-4a13-a3d1-d28c9748d743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507504385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.1507504385
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3904405577
Short name T459
Test name
Test status
Simulation time 92818813 ps
CPU time 0.76 seconds
Started May 19 01:32:34 PM PDT 24
Finished May 19 01:32:38 PM PDT 24
Peak memory 200300 kb
Host smart-b9a0593a-1017-4c1d-a361-892480110e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904405577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3904405577
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.534874684
Short name T89
Test name
Test status
Simulation time 828748961 ps
CPU time 5 seconds
Started May 19 01:32:34 PM PDT 24
Finished May 19 01:32:42 PM PDT 24
Peak memory 200560 kb
Host smart-3099db3d-929b-4201-9469-d96fee9682fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534874684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.534874684
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2281507091
Short name T171
Test name
Test status
Simulation time 145583014 ps
CPU time 1.13 seconds
Started May 19 01:32:40 PM PDT 24
Finished May 19 01:32:43 PM PDT 24
Peak memory 200460 kb
Host smart-067c4c28-24c6-4033-8958-8f928e9e2e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281507091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2281507091
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.969778315
Short name T511
Test name
Test status
Simulation time 122105824 ps
CPU time 1.27 seconds
Started May 19 01:32:37 PM PDT 24
Finished May 19 01:32:40 PM PDT 24
Peak memory 200652 kb
Host smart-ab374a73-6e16-4226-895f-e7c186c61359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969778315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.969778315
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.460594607
Short name T399
Test name
Test status
Simulation time 288532010 ps
CPU time 1.54 seconds
Started May 19 01:32:38 PM PDT 24
Finished May 19 01:32:41 PM PDT 24
Peak memory 200508 kb
Host smart-950b5766-4150-4527-80dc-357fc4da54a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460594607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.460594607
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2910346030
Short name T311
Test name
Test status
Simulation time 498627723 ps
CPU time 2.62 seconds
Started May 19 01:32:43 PM PDT 24
Finished May 19 01:32:47 PM PDT 24
Peak memory 200452 kb
Host smart-a39ceca8-0c34-498b-ae2a-ded795e28f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910346030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2910346030
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2541939684
Short name T363
Test name
Test status
Simulation time 140071427 ps
CPU time 1.26 seconds
Started May 19 01:32:34 PM PDT 24
Finished May 19 01:32:39 PM PDT 24
Peak memory 200412 kb
Host smart-d204e55b-46d3-44e4-ae76-0e872b620f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541939684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2541939684
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3759098128
Short name T162
Test name
Test status
Simulation time 71749393 ps
CPU time 0.82 seconds
Started May 19 01:32:40 PM PDT 24
Finished May 19 01:32:43 PM PDT 24
Peak memory 200328 kb
Host smart-341f71c3-ed28-41fc-88d4-677cb0d704c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759098128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3759098128
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3817786397
Short name T13
Test name
Test status
Simulation time 2157972255 ps
CPU time 8.43 seconds
Started May 19 01:32:40 PM PDT 24
Finished May 19 01:32:51 PM PDT 24
Peak memory 229520 kb
Host smart-92ab59d8-5734-4f2f-a15f-b8e61202206a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817786397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3817786397
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.217416659
Short name T467
Test name
Test status
Simulation time 243666921 ps
CPU time 1.1 seconds
Started May 19 01:32:50 PM PDT 24
Finished May 19 01:32:52 PM PDT 24
Peak memory 217540 kb
Host smart-3394a014-3e32-434a-8541-09f73c539641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217416659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.217416659
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.28219340
Short name T432
Test name
Test status
Simulation time 189165363 ps
CPU time 0.85 seconds
Started May 19 01:32:38 PM PDT 24
Finished May 19 01:32:40 PM PDT 24
Peak memory 200300 kb
Host smart-1be82bca-4a83-45a5-a8c8-a5b5d62686c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28219340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.28219340
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3432922993
Short name T492
Test name
Test status
Simulation time 2185872465 ps
CPU time 7.57 seconds
Started May 19 01:32:36 PM PDT 24
Finished May 19 01:32:45 PM PDT 24
Peak memory 201048 kb
Host smart-29ab7c3a-0ea0-4159-8188-2fc9c00ed70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432922993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3432922993
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1811100366
Short name T63
Test name
Test status
Simulation time 171743943 ps
CPU time 1.18 seconds
Started May 19 01:32:36 PM PDT 24
Finished May 19 01:32:39 PM PDT 24
Peak memory 200488 kb
Host smart-1729b70e-c49d-4d9d-87f4-aaf803520575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811100366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1811100366
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.695466213
Short name T478
Test name
Test status
Simulation time 245737885 ps
CPU time 1.5 seconds
Started May 19 01:32:34 PM PDT 24
Finished May 19 01:32:39 PM PDT 24
Peak memory 200848 kb
Host smart-b31e519f-e01e-4f0c-bc3d-3e55901ac483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695466213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.695466213
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3087040143
Short name T429
Test name
Test status
Simulation time 4103853479 ps
CPU time 14.39 seconds
Started May 19 01:32:41 PM PDT 24
Finished May 19 01:32:58 PM PDT 24
Peak memory 200800 kb
Host smart-c884351e-fbc7-4809-995a-65fb98b6b217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087040143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3087040143
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.3976883553
Short name T184
Test name
Test status
Simulation time 147732103 ps
CPU time 1.81 seconds
Started May 19 01:32:37 PM PDT 24
Finished May 19 01:32:41 PM PDT 24
Peak memory 200460 kb
Host smart-05427fc2-12fe-4bd4-b804-e195324f4284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976883553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.3976883553
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.935708430
Short name T451
Test name
Test status
Simulation time 60658197 ps
CPU time 0.84 seconds
Started May 19 01:32:39 PM PDT 24
Finished May 19 01:32:41 PM PDT 24
Peak memory 200420 kb
Host smart-ed7d08af-459b-44a7-9754-a1ac148fe6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935708430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.935708430
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.3115121466
Short name T475
Test name
Test status
Simulation time 78699910 ps
CPU time 0.8 seconds
Started May 19 01:32:44 PM PDT 24
Finished May 19 01:32:46 PM PDT 24
Peak memory 200212 kb
Host smart-2fdc79b0-a550-41a4-b340-6b85eda88615
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115121466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3115121466
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2180610473
Short name T57
Test name
Test status
Simulation time 2364590150 ps
CPU time 8.25 seconds
Started May 19 01:32:43 PM PDT 24
Finished May 19 01:32:53 PM PDT 24
Peak memory 217392 kb
Host smart-fc5981cc-c791-47b6-bff2-4cd90132c3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180610473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2180610473
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.180094825
Short name T307
Test name
Test status
Simulation time 267073636 ps
CPU time 1.1 seconds
Started May 19 01:32:41 PM PDT 24
Finished May 19 01:32:44 PM PDT 24
Peak memory 217632 kb
Host smart-f0232e24-b6d0-44c7-b960-64dd68804bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180094825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.180094825
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.176340046
Short name T20
Test name
Test status
Simulation time 115116190 ps
CPU time 0.81 seconds
Started May 19 01:32:41 PM PDT 24
Finished May 19 01:32:44 PM PDT 24
Peak memory 200284 kb
Host smart-02e2bb22-28fe-4087-9490-954f489f3ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176340046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.176340046
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.1321280660
Short name T241
Test name
Test status
Simulation time 689487841 ps
CPU time 3.96 seconds
Started May 19 01:32:44 PM PDT 24
Finished May 19 01:32:49 PM PDT 24
Peak memory 200564 kb
Host smart-ee233176-7208-4920-bf75-8856180304e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321280660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1321280660
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2610548056
Short name T288
Test name
Test status
Simulation time 99665192 ps
CPU time 1 seconds
Started May 19 01:32:41 PM PDT 24
Finished May 19 01:32:45 PM PDT 24
Peak memory 200456 kb
Host smart-411da8d1-0c72-407d-b1e5-bd2d3ac18029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610548056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2610548056
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3720539545
Short name T378
Test name
Test status
Simulation time 123155735 ps
CPU time 1.21 seconds
Started May 19 01:32:39 PM PDT 24
Finished May 19 01:32:42 PM PDT 24
Peak memory 200928 kb
Host smart-9f23f0a7-6449-41b1-b1ad-ba79de1ba270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720539545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3720539545
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.310897851
Short name T235
Test name
Test status
Simulation time 8016510076 ps
CPU time 34.34 seconds
Started May 19 01:32:42 PM PDT 24
Finished May 19 01:33:18 PM PDT 24
Peak memory 209012 kb
Host smart-6cd3a748-e22d-410b-acc9-0afe73602e76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310897851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.310897851
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.957769478
Short name T522
Test name
Test status
Simulation time 455544378 ps
CPU time 2.7 seconds
Started May 19 01:32:42 PM PDT 24
Finished May 19 01:32:47 PM PDT 24
Peak memory 200408 kb
Host smart-61479ace-7ca2-4229-acdc-1cdcdeee8770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957769478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.957769478
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1057087562
Short name T164
Test name
Test status
Simulation time 115039722 ps
CPU time 0.96 seconds
Started May 19 01:32:41 PM PDT 24
Finished May 19 01:32:44 PM PDT 24
Peak memory 200660 kb
Host smart-5c36dc70-80db-4c01-a04f-f287ffa780b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057087562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1057087562
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1863943119
Short name T339
Test name
Test status
Simulation time 83979810 ps
CPU time 0.8 seconds
Started May 19 01:32:43 PM PDT 24
Finished May 19 01:32:46 PM PDT 24
Peak memory 200240 kb
Host smart-0c19c402-748a-483d-b601-bb1f4f7492f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863943119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1863943119
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3596634755
Short name T376
Test name
Test status
Simulation time 1880169382 ps
CPU time 7.2 seconds
Started May 19 01:32:41 PM PDT 24
Finished May 19 01:32:50 PM PDT 24
Peak memory 222192 kb
Host smart-888e322d-221c-4235-80c1-064c605ef733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596634755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3596634755
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1252714812
Short name T469
Test name
Test status
Simulation time 244277398 ps
CPU time 1.15 seconds
Started May 19 01:32:40 PM PDT 24
Finished May 19 01:32:42 PM PDT 24
Peak memory 217536 kb
Host smart-0c19c503-e8c4-461a-a8b6-f4eb6a5640e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252714812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1252714812
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3584455298
Short name T530
Test name
Test status
Simulation time 115563829 ps
CPU time 0.8 seconds
Started May 19 01:32:39 PM PDT 24
Finished May 19 01:32:41 PM PDT 24
Peak memory 200292 kb
Host smart-21770f2d-9812-44ad-b9d3-a8ad2e3fa5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584455298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3584455298
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.715341878
Short name T262
Test name
Test status
Simulation time 785115669 ps
CPU time 4.17 seconds
Started May 19 01:32:40 PM PDT 24
Finished May 19 01:32:46 PM PDT 24
Peak memory 200624 kb
Host smart-a9288fcb-7292-416f-9ddb-bbdf7a105921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715341878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.715341878
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2357915498
Short name T393
Test name
Test status
Simulation time 165331577 ps
CPU time 1.17 seconds
Started May 19 01:32:39 PM PDT 24
Finished May 19 01:32:42 PM PDT 24
Peak memory 200456 kb
Host smart-48fae477-2423-4777-996b-51cd0ca0eb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357915498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.2357915498
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.248123768
Short name T33
Test name
Test status
Simulation time 117607431 ps
CPU time 1.24 seconds
Started May 19 01:32:42 PM PDT 24
Finished May 19 01:32:45 PM PDT 24
Peak memory 200660 kb
Host smart-46731bba-96a7-401b-99e7-02e23fa0d865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248123768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.248123768
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.269392655
Short name T131
Test name
Test status
Simulation time 4563891895 ps
CPU time 17.38 seconds
Started May 19 01:32:42 PM PDT 24
Finished May 19 01:33:02 PM PDT 24
Peak memory 200768 kb
Host smart-53fa2d5c-f9a7-4abe-a7a7-ab5424a6c0bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269392655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.269392655
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2309892411
Short name T94
Test name
Test status
Simulation time 156740081 ps
CPU time 1.82 seconds
Started May 19 01:32:42 PM PDT 24
Finished May 19 01:32:46 PM PDT 24
Peak memory 200416 kb
Host smart-5beb7876-cf15-4182-a36c-30613277bd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309892411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2309892411
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.4245237179
Short name T301
Test name
Test status
Simulation time 129036558 ps
CPU time 1.12 seconds
Started May 19 01:32:42 PM PDT 24
Finished May 19 01:32:45 PM PDT 24
Peak memory 200452 kb
Host smart-7ecefbe3-ad07-40ad-a512-f5a9225a3e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245237179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.4245237179
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3670287571
Short name T352
Test name
Test status
Simulation time 94912083 ps
CPU time 0.91 seconds
Started May 19 01:32:41 PM PDT 24
Finished May 19 01:32:45 PM PDT 24
Peak memory 200248 kb
Host smart-17c7eda3-cd6c-40e5-b2e9-e891113cbe3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670287571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3670287571
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3456632350
Short name T405
Test name
Test status
Simulation time 1876712717 ps
CPU time 7.13 seconds
Started May 19 01:32:43 PM PDT 24
Finished May 19 01:32:52 PM PDT 24
Peak memory 218036 kb
Host smart-f1eedf08-351c-4d85-8107-78edb250f91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456632350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3456632350
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.108994867
Short name T295
Test name
Test status
Simulation time 243898409 ps
CPU time 1.05 seconds
Started May 19 01:32:41 PM PDT 24
Finished May 19 01:32:44 PM PDT 24
Peak memory 217576 kb
Host smart-f851ed6d-bbfb-4023-b227-344a1b1d0bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108994867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.108994867
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3829954770
Short name T389
Test name
Test status
Simulation time 186071661 ps
CPU time 0.93 seconds
Started May 19 01:32:40 PM PDT 24
Finished May 19 01:32:44 PM PDT 24
Peak memory 200260 kb
Host smart-e7c5191e-3bf3-44a0-9328-c653dfa78157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829954770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3829954770
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.747588494
Short name T108
Test name
Test status
Simulation time 1358212334 ps
CPU time 5.94 seconds
Started May 19 01:32:43 PM PDT 24
Finished May 19 01:32:51 PM PDT 24
Peak memory 200588 kb
Host smart-11e3437d-dc59-4ceb-8ffa-55e8759dbf5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747588494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.747588494
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2640765602
Short name T525
Test name
Test status
Simulation time 186942366 ps
CPU time 1.29 seconds
Started May 19 01:32:40 PM PDT 24
Finished May 19 01:32:42 PM PDT 24
Peak memory 200428 kb
Host smart-a39dd59b-e411-49a2-b898-49ab7f36e3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640765602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2640765602
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1370038003
Short name T440
Test name
Test status
Simulation time 224542202 ps
CPU time 1.51 seconds
Started May 19 01:32:42 PM PDT 24
Finished May 19 01:32:46 PM PDT 24
Peak memory 200640 kb
Host smart-cf345fa4-7134-47ad-8a5e-b6c6d235ae25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370038003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1370038003
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3905965353
Short name T168
Test name
Test status
Simulation time 130239366 ps
CPU time 1.77 seconds
Started May 19 01:32:40 PM PDT 24
Finished May 19 01:32:43 PM PDT 24
Peak memory 208612 kb
Host smart-44f33d39-6af7-487b-bd68-d40c6681784b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905965353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3905965353
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.951145858
Short name T138
Test name
Test status
Simulation time 116989372 ps
CPU time 0.93 seconds
Started May 19 01:32:41 PM PDT 24
Finished May 19 01:32:44 PM PDT 24
Peak memory 200448 kb
Host smart-172d9236-bb0f-403a-b7d5-bd303e8bf695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951145858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.951145858
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1195821287
Short name T215
Test name
Test status
Simulation time 80410905 ps
CPU time 0.98 seconds
Started May 19 01:32:49 PM PDT 24
Finished May 19 01:32:51 PM PDT 24
Peak memory 200280 kb
Host smart-0a78ec90-ad87-4ab2-bc61-73f9af2eb466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195821287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1195821287
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2285013529
Short name T337
Test name
Test status
Simulation time 1220533786 ps
CPU time 6.77 seconds
Started May 19 01:32:48 PM PDT 24
Finished May 19 01:32:56 PM PDT 24
Peak memory 222040 kb
Host smart-7fdfe581-bb2d-47e8-957b-93a89ceee24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285013529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2285013529
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.448999267
Short name T155
Test name
Test status
Simulation time 243999503 ps
CPU time 1.16 seconds
Started May 19 01:32:48 PM PDT 24
Finished May 19 01:32:50 PM PDT 24
Peak memory 217880 kb
Host smart-d139fd2f-08eb-4e8e-8ba7-8d7810749617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448999267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.448999267
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2429381135
Short name T488
Test name
Test status
Simulation time 194825637 ps
CPU time 0.95 seconds
Started May 19 01:32:54 PM PDT 24
Finished May 19 01:32:56 PM PDT 24
Peak memory 200268 kb
Host smart-d40a1407-05b1-4bc8-a919-0f8f34d62964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429381135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2429381135
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.167774555
Short name T310
Test name
Test status
Simulation time 980749841 ps
CPU time 4.55 seconds
Started May 19 01:32:49 PM PDT 24
Finished May 19 01:32:55 PM PDT 24
Peak memory 200628 kb
Host smart-e7852961-3ec2-4bff-bba9-5454e2bc7166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167774555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.167774555
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.4244988317
Short name T160
Test name
Test status
Simulation time 181914066 ps
CPU time 1.15 seconds
Started May 19 01:32:44 PM PDT 24
Finished May 19 01:32:47 PM PDT 24
Peak memory 200464 kb
Host smart-95c3e3f7-0908-4c71-819b-5a7d2ae780ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244988317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.4244988317
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.998651855
Short name T240
Test name
Test status
Simulation time 122748467 ps
CPU time 1.26 seconds
Started May 19 01:32:42 PM PDT 24
Finished May 19 01:32:46 PM PDT 24
Peak memory 200608 kb
Host smart-ab092d56-da6f-4cd7-957e-46618b6e36ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998651855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.998651855
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1817022548
Short name T211
Test name
Test status
Simulation time 1083006556 ps
CPU time 5.22 seconds
Started May 19 01:32:46 PM PDT 24
Finished May 19 01:32:52 PM PDT 24
Peak memory 200624 kb
Host smart-6316b407-2c00-440f-b5c7-deddccab4e34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817022548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1817022548
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3462940024
Short name T535
Test name
Test status
Simulation time 318191970 ps
CPU time 2.14 seconds
Started May 19 01:32:50 PM PDT 24
Finished May 19 01:32:53 PM PDT 24
Peak memory 200420 kb
Host smart-fc6ae3a5-460a-498b-a854-fb3e1acc9c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462940024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3462940024
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1117519692
Short name T481
Test name
Test status
Simulation time 257111988 ps
CPU time 1.56 seconds
Started May 19 01:32:46 PM PDT 24
Finished May 19 01:32:48 PM PDT 24
Peak memory 200376 kb
Host smart-163df802-1cbd-4aa2-856b-cdba5ff6cb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117519692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1117519692
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1868401287
Short name T424
Test name
Test status
Simulation time 75864591 ps
CPU time 0.8 seconds
Started May 19 01:32:17 PM PDT 24
Finished May 19 01:32:19 PM PDT 24
Peak memory 200300 kb
Host smart-50bd95fd-553c-4d60-a40d-097675296015
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868401287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1868401287
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3930381286
Short name T38
Test name
Test status
Simulation time 1223625008 ps
CPU time 5.83 seconds
Started May 19 01:32:33 PM PDT 24
Finished May 19 01:32:42 PM PDT 24
Peak memory 217596 kb
Host smart-d66c1f2b-ec75-413e-84bc-32dba095488d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930381286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3930381286
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3266296502
Short name T214
Test name
Test status
Simulation time 243398911 ps
CPU time 1.17 seconds
Started May 19 01:32:28 PM PDT 24
Finished May 19 01:32:31 PM PDT 24
Peak memory 217540 kb
Host smart-81523004-06b2-453d-a26a-aca5d82ad732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266296502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3266296502
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1631237007
Short name T261
Test name
Test status
Simulation time 131688778 ps
CPU time 0.82 seconds
Started May 19 01:32:25 PM PDT 24
Finished May 19 01:32:27 PM PDT 24
Peak memory 200264 kb
Host smart-9d918647-b158-452b-a1bb-fd3052c8d265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631237007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1631237007
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.341324397
Short name T508
Test name
Test status
Simulation time 1118088423 ps
CPU time 4.65 seconds
Started May 19 01:32:29 PM PDT 24
Finished May 19 01:32:36 PM PDT 24
Peak memory 200708 kb
Host smart-5c748d89-e5f2-458f-a62c-17ec87411dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341324397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.341324397
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.881348165
Short name T85
Test name
Test status
Simulation time 8283768109 ps
CPU time 15.52 seconds
Started May 19 01:32:17 PM PDT 24
Finished May 19 01:32:33 PM PDT 24
Peak memory 217816 kb
Host smart-2ee6c9f3-53d9-423a-81fa-b69fab5d2952
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881348165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.881348165
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.861228447
Short name T327
Test name
Test status
Simulation time 97200487 ps
CPU time 1 seconds
Started May 19 01:32:30 PM PDT 24
Finished May 19 01:32:33 PM PDT 24
Peak memory 200464 kb
Host smart-80ad0617-4c52-4d17-88f1-d7f2f2057d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861228447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.861228447
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3815360672
Short name T139
Test name
Test status
Simulation time 224829699 ps
CPU time 1.43 seconds
Started May 19 01:32:17 PM PDT 24
Finished May 19 01:32:20 PM PDT 24
Peak memory 200600 kb
Host smart-47d2e445-8d2f-41e6-a957-bc093c57be64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815360672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3815360672
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.4175270555
Short name T104
Test name
Test status
Simulation time 4282396554 ps
CPU time 14.77 seconds
Started May 19 01:32:18 PM PDT 24
Finished May 19 01:32:34 PM PDT 24
Peak memory 210504 kb
Host smart-88c73264-7a0f-4775-a0be-9b1d0d46f7b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175270555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.4175270555
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.317885573
Short name T533
Test name
Test status
Simulation time 152616390 ps
CPU time 1.85 seconds
Started May 19 01:32:25 PM PDT 24
Finished May 19 01:32:29 PM PDT 24
Peak memory 200468 kb
Host smart-ce36ac12-d89a-42e2-b219-acca799bca44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317885573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.317885573
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3775655080
Short name T257
Test name
Test status
Simulation time 304484697 ps
CPU time 1.64 seconds
Started May 19 01:32:23 PM PDT 24
Finished May 19 01:32:26 PM PDT 24
Peak memory 200728 kb
Host smart-2bf2a07b-9df1-4d8d-abe8-56ad3c3b9d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775655080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3775655080
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1320495049
Short name T36
Test name
Test status
Simulation time 82161845 ps
CPU time 0.85 seconds
Started May 19 01:32:51 PM PDT 24
Finished May 19 01:32:53 PM PDT 24
Peak memory 200280 kb
Host smart-eb4e89f2-db9d-4248-9b17-a5aba648401f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320495049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1320495049
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1958806831
Short name T157
Test name
Test status
Simulation time 244830744 ps
CPU time 1.04 seconds
Started May 19 01:32:54 PM PDT 24
Finished May 19 01:32:56 PM PDT 24
Peak memory 217732 kb
Host smart-3d229434-4edf-4ba2-9b1d-1d181f593400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958806831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1958806831
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1548079983
Short name T401
Test name
Test status
Simulation time 205034332 ps
CPU time 1.07 seconds
Started May 19 01:32:48 PM PDT 24
Finished May 19 01:32:50 PM PDT 24
Peak memory 200460 kb
Host smart-6b168ba5-fabe-4242-88cd-d9fae0b3218b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548079983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1548079983
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.1826833217
Short name T450
Test name
Test status
Simulation time 994545629 ps
CPU time 4.99 seconds
Started May 19 01:32:50 PM PDT 24
Finished May 19 01:32:56 PM PDT 24
Peak memory 200632 kb
Host smart-aea95644-8101-4692-a2bd-77993b6ed028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826833217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1826833217
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1938806148
Short name T418
Test name
Test status
Simulation time 100538813 ps
CPU time 0.97 seconds
Started May 19 01:32:48 PM PDT 24
Finished May 19 01:32:50 PM PDT 24
Peak memory 200444 kb
Host smart-f593ac0d-7eaa-4181-901b-e733af525aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938806148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1938806148
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3663622333
Short name T435
Test name
Test status
Simulation time 112695636 ps
CPU time 1.17 seconds
Started May 19 01:32:47 PM PDT 24
Finished May 19 01:32:49 PM PDT 24
Peak memory 200556 kb
Host smart-5277044f-7572-4c25-8154-da0a7b072e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663622333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3663622333
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.4243751184
Short name T385
Test name
Test status
Simulation time 1520618717 ps
CPU time 6.72 seconds
Started May 19 01:33:02 PM PDT 24
Finished May 19 01:33:12 PM PDT 24
Peak memory 200592 kb
Host smart-f1305b2a-2985-498e-8056-0dac79e64fbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243751184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.4243751184
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3271249998
Short name T167
Test name
Test status
Simulation time 124707465 ps
CPU time 1.52 seconds
Started May 19 01:32:45 PM PDT 24
Finished May 19 01:32:48 PM PDT 24
Peak memory 208652 kb
Host smart-141a5e34-5c9c-4f69-a248-b0e2dd59ea90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271249998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3271249998
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3245488770
Short name T174
Test name
Test status
Simulation time 61940617 ps
CPU time 0.81 seconds
Started May 19 01:33:04 PM PDT 24
Finished May 19 01:33:08 PM PDT 24
Peak memory 200336 kb
Host smart-454e4d2d-b058-434f-a408-91be0f360da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245488770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3245488770
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.960408099
Short name T28
Test name
Test status
Simulation time 76026809 ps
CPU time 0.81 seconds
Started May 19 01:32:48 PM PDT 24
Finished May 19 01:32:50 PM PDT 24
Peak memory 200276 kb
Host smart-229b7a25-7d87-4d96-8f49-f7247457671f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960408099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.960408099
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.710006714
Short name T75
Test name
Test status
Simulation time 1223837865 ps
CPU time 5.37 seconds
Started May 19 01:32:51 PM PDT 24
Finished May 19 01:32:57 PM PDT 24
Peak memory 222152 kb
Host smart-7e9fac40-d8ae-41fb-9c07-e8d60361c8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710006714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.710006714
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2834793445
Short name T526
Test name
Test status
Simulation time 244449481 ps
CPU time 1.14 seconds
Started May 19 01:33:07 PM PDT 24
Finished May 19 01:33:11 PM PDT 24
Peak memory 217428 kb
Host smart-931ade90-16fe-4c58-bbf1-3a80d51d030f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834793445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2834793445
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.536641432
Short name T188
Test name
Test status
Simulation time 95658034 ps
CPU time 0.78 seconds
Started May 19 01:32:48 PM PDT 24
Finished May 19 01:32:50 PM PDT 24
Peak memory 200292 kb
Host smart-195894b4-edb3-4f18-9532-381d57ba66b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536641432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.536641432
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.2744596577
Short name T461
Test name
Test status
Simulation time 1878135606 ps
CPU time 7.84 seconds
Started May 19 01:32:46 PM PDT 24
Finished May 19 01:32:55 PM PDT 24
Peak memory 200700 kb
Host smart-41fe2762-d909-4870-9ef2-37f376145888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744596577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2744596577
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2550923848
Short name T517
Test name
Test status
Simulation time 111612021 ps
CPU time 1 seconds
Started May 19 01:32:44 PM PDT 24
Finished May 19 01:32:47 PM PDT 24
Peak memory 200412 kb
Host smart-d3a8e10c-3655-48fd-989e-5e99bec665a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550923848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2550923848
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2765197239
Short name T190
Test name
Test status
Simulation time 253539671 ps
CPU time 1.43 seconds
Started May 19 01:32:47 PM PDT 24
Finished May 19 01:32:49 PM PDT 24
Peak memory 200700 kb
Host smart-59d1245e-a8cb-4c09-a971-96df5aa9f1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765197239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2765197239
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.885312358
Short name T501
Test name
Test status
Simulation time 2059931496 ps
CPU time 8.04 seconds
Started May 19 01:32:45 PM PDT 24
Finished May 19 01:32:54 PM PDT 24
Peak memory 210092 kb
Host smart-ba4e3c7d-3722-4c62-94c7-4db12f233fdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885312358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.885312358
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.319962895
Short name T294
Test name
Test status
Simulation time 264069023 ps
CPU time 1.97 seconds
Started May 19 01:32:47 PM PDT 24
Finished May 19 01:32:50 PM PDT 24
Peak memory 200400 kb
Host smart-fae8396c-55a2-4013-b687-5311017457c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319962895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.319962895
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2122793736
Short name T290
Test name
Test status
Simulation time 150982840 ps
CPU time 1.16 seconds
Started May 19 01:32:48 PM PDT 24
Finished May 19 01:32:50 PM PDT 24
Peak memory 200460 kb
Host smart-c59efd68-4931-4ef4-bd1a-1b0d1497cc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122793736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2122793736
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1591757031
Short name T208
Test name
Test status
Simulation time 60115833 ps
CPU time 0.79 seconds
Started May 19 01:33:00 PM PDT 24
Finished May 19 01:33:03 PM PDT 24
Peak memory 200292 kb
Host smart-0a1ad095-67f7-4754-8ce2-002f8e577de8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591757031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1591757031
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.396254476
Short name T474
Test name
Test status
Simulation time 2168335361 ps
CPU time 8.16 seconds
Started May 19 01:32:50 PM PDT 24
Finished May 19 01:32:59 PM PDT 24
Peak memory 218200 kb
Host smart-08420dcd-4464-474d-84eb-15498c2cbf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396254476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.396254476
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.949790988
Short name T297
Test name
Test status
Simulation time 244192823 ps
CPU time 1.08 seconds
Started May 19 01:32:54 PM PDT 24
Finished May 19 01:32:57 PM PDT 24
Peak memory 217568 kb
Host smart-c2a09902-65f9-43e2-9e10-bd65a753903e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949790988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.949790988
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.563236318
Short name T19
Test name
Test status
Simulation time 127329600 ps
CPU time 0.83 seconds
Started May 19 01:32:53 PM PDT 24
Finished May 19 01:32:55 PM PDT 24
Peak memory 200216 kb
Host smart-583ae6d8-8406-42dc-9e56-c08dee92cf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563236318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.563236318
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.798516500
Short name T366
Test name
Test status
Simulation time 1813327646 ps
CPU time 6.9 seconds
Started May 19 01:32:48 PM PDT 24
Finished May 19 01:32:56 PM PDT 24
Peak memory 200672 kb
Host smart-705903b6-f92a-40ee-8d28-9526135c0b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798516500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.798516500
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2833292812
Short name T134
Test name
Test status
Simulation time 144316252 ps
CPU time 1.12 seconds
Started May 19 01:32:56 PM PDT 24
Finished May 19 01:32:59 PM PDT 24
Peak memory 200460 kb
Host smart-3f6aaa1e-2780-47ae-be9d-24f2db8d2631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833292812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2833292812
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2184952858
Short name T282
Test name
Test status
Simulation time 199037931 ps
CPU time 1.44 seconds
Started May 19 01:32:49 PM PDT 24
Finished May 19 01:32:52 PM PDT 24
Peak memory 200656 kb
Host smart-230ffec0-6bd0-4fa3-a945-b53ceb0bfd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184952858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2184952858
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2557843077
Short name T457
Test name
Test status
Simulation time 8426506653 ps
CPU time 32.38 seconds
Started May 19 01:33:07 PM PDT 24
Finished May 19 01:33:42 PM PDT 24
Peak memory 200676 kb
Host smart-fb5d13db-953a-452d-aaf3-76fb66badbd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557843077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2557843077
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3127951114
Short name T471
Test name
Test status
Simulation time 359989029 ps
CPU time 2.3 seconds
Started May 19 01:32:54 PM PDT 24
Finished May 19 01:32:57 PM PDT 24
Peak memory 200452 kb
Host smart-6f2c7b6d-c7c9-44f6-b2f4-59cd488cbdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127951114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3127951114
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1527311012
Short name T374
Test name
Test status
Simulation time 122605488 ps
CPU time 1.09 seconds
Started May 19 01:32:46 PM PDT 24
Finished May 19 01:32:48 PM PDT 24
Peak memory 200460 kb
Host smart-610fcc57-35f7-4d64-b173-dd7411cb2a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527311012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1527311012
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.222184727
Short name T313
Test name
Test status
Simulation time 65409147 ps
CPU time 0.84 seconds
Started May 19 01:32:51 PM PDT 24
Finished May 19 01:32:53 PM PDT 24
Peak memory 200284 kb
Host smart-d1593192-b607-44e3-b7af-0e36a3840000
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222184727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.222184727
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3378863926
Short name T394
Test name
Test status
Simulation time 1900623035 ps
CPU time 7.95 seconds
Started May 19 01:32:54 PM PDT 24
Finished May 19 01:33:03 PM PDT 24
Peak memory 218112 kb
Host smart-ad2e3a0d-21f5-4e03-8ae9-e0ef697dd10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378863926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3378863926
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.4199007389
Short name T443
Test name
Test status
Simulation time 244655477 ps
CPU time 1.05 seconds
Started May 19 01:33:00 PM PDT 24
Finished May 19 01:33:03 PM PDT 24
Peak memory 217532 kb
Host smart-c82d8560-0b13-4ad8-9ddb-4b4fefda8cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199007389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.4199007389
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.233983939
Short name T453
Test name
Test status
Simulation time 191124454 ps
CPU time 0.9 seconds
Started May 19 01:32:56 PM PDT 24
Finished May 19 01:32:58 PM PDT 24
Peak memory 200268 kb
Host smart-cf437ea6-f920-4126-8588-d569fcb07305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233983939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.233983939
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.3078050194
Short name T103
Test name
Test status
Simulation time 838464022 ps
CPU time 4.39 seconds
Started May 19 01:32:58 PM PDT 24
Finished May 19 01:33:03 PM PDT 24
Peak memory 200664 kb
Host smart-20de80fa-fabb-4616-920a-e57050847fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078050194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3078050194
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3853187301
Short name T382
Test name
Test status
Simulation time 99041098 ps
CPU time 1.02 seconds
Started May 19 01:32:47 PM PDT 24
Finished May 19 01:32:49 PM PDT 24
Peak memory 200480 kb
Host smart-15e161e1-6fc8-4fbf-960d-447eace80b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853187301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3853187301
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.4092586186
Short name T14
Test name
Test status
Simulation time 256278223 ps
CPU time 1.6 seconds
Started May 19 01:32:48 PM PDT 24
Finished May 19 01:32:50 PM PDT 24
Peak memory 200660 kb
Host smart-c4c97062-1f76-4ec9-9f97-589b284841ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092586186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.4092586186
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.4121096718
Short name T11
Test name
Test status
Simulation time 146579517 ps
CPU time 0.99 seconds
Started May 19 01:33:01 PM PDT 24
Finished May 19 01:33:04 PM PDT 24
Peak memory 200288 kb
Host smart-c99e1c7e-c5c6-4c6d-b8f5-2676d07fa762
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121096718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.4121096718
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2078423321
Short name T462
Test name
Test status
Simulation time 153903784 ps
CPU time 1.99 seconds
Started May 19 01:32:49 PM PDT 24
Finished May 19 01:32:52 PM PDT 24
Peak memory 200424 kb
Host smart-5b8f5e25-1d10-4234-acfd-9da5590b8cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078423321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2078423321
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3437905522
Short name T227
Test name
Test status
Simulation time 197241687 ps
CPU time 1.31 seconds
Started May 19 01:33:05 PM PDT 24
Finished May 19 01:33:09 PM PDT 24
Peak memory 200336 kb
Host smart-26fb7268-ef78-4689-a5db-8548ad72643c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437905522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3437905522
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.795026564
Short name T395
Test name
Test status
Simulation time 61775978 ps
CPU time 0.77 seconds
Started May 19 01:32:46 PM PDT 24
Finished May 19 01:32:48 PM PDT 24
Peak memory 200280 kb
Host smart-1f808e44-7fdc-4a67-9e7d-cd00113872ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795026564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.795026564
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2821940283
Short name T388
Test name
Test status
Simulation time 2191165661 ps
CPU time 7.55 seconds
Started May 19 01:32:54 PM PDT 24
Finished May 19 01:33:03 PM PDT 24
Peak memory 217084 kb
Host smart-a0dc4d26-062d-43e2-a3fb-a8fa04c145ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821940283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2821940283
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1216089396
Short name T170
Test name
Test status
Simulation time 244989104 ps
CPU time 1.08 seconds
Started May 19 01:32:54 PM PDT 24
Finished May 19 01:32:57 PM PDT 24
Peak memory 217736 kb
Host smart-5d9860e5-60c0-44ab-abd5-f0a6190f0df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216089396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1216089396
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.243027814
Short name T504
Test name
Test status
Simulation time 169782436 ps
CPU time 0.88 seconds
Started May 19 01:32:49 PM PDT 24
Finished May 19 01:32:51 PM PDT 24
Peak memory 200252 kb
Host smart-7edf0ce7-8559-4c38-8ebd-0e7d5b2cb047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243027814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.243027814
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3179569583
Short name T529
Test name
Test status
Simulation time 2052638247 ps
CPU time 6.95 seconds
Started May 19 01:32:49 PM PDT 24
Finished May 19 01:32:57 PM PDT 24
Peak memory 200624 kb
Host smart-41bff3f9-15cc-444e-b51a-cd0caa48c1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179569583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3179569583
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.4226524079
Short name T468
Test name
Test status
Simulation time 100411730 ps
CPU time 1.01 seconds
Started May 19 01:32:55 PM PDT 24
Finished May 19 01:32:58 PM PDT 24
Peak memory 200460 kb
Host smart-e7d4ad30-fbaa-4ff6-8cf3-eab15269b30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226524079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.4226524079
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2640300346
Short name T312
Test name
Test status
Simulation time 252028802 ps
CPU time 1.65 seconds
Started May 19 01:32:48 PM PDT 24
Finished May 19 01:32:51 PM PDT 24
Peak memory 200640 kb
Host smart-9012d1cb-6b63-4384-aa27-bbbbae4e2c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640300346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2640300346
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.4255392731
Short name T61
Test name
Test status
Simulation time 916698982 ps
CPU time 4.39 seconds
Started May 19 01:32:54 PM PDT 24
Finished May 19 01:32:59 PM PDT 24
Peak memory 200592 kb
Host smart-f0ef84a3-3f59-4bee-a1b9-ab716f2164cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255392731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.4255392731
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2945205349
Short name T71
Test name
Test status
Simulation time 128413064 ps
CPU time 1.6 seconds
Started May 19 01:33:04 PM PDT 24
Finished May 19 01:33:09 PM PDT 24
Peak memory 208524 kb
Host smart-20f2ac33-46d8-4226-8c96-fb8b2d080ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945205349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2945205349
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2392375882
Short name T390
Test name
Test status
Simulation time 231290229 ps
CPU time 1.29 seconds
Started May 19 01:32:48 PM PDT 24
Finished May 19 01:32:51 PM PDT 24
Peak memory 200460 kb
Host smart-d9188450-ae4d-4a2e-82c7-a2e13968d78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392375882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2392375882
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.483677129
Short name T386
Test name
Test status
Simulation time 74564659 ps
CPU time 0.81 seconds
Started May 19 01:33:01 PM PDT 24
Finished May 19 01:33:05 PM PDT 24
Peak memory 200312 kb
Host smart-aeb9ff06-2912-4afc-b60a-c7d68b1076c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483677129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.483677129
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3877867208
Short name T74
Test name
Test status
Simulation time 1232715689 ps
CPU time 5.6 seconds
Started May 19 01:33:00 PM PDT 24
Finished May 19 01:33:08 PM PDT 24
Peak memory 218096 kb
Host smart-689e73b1-32ca-49c1-a053-98627880a3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877867208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3877867208
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3375968553
Short name T519
Test name
Test status
Simulation time 243698344 ps
CPU time 1.14 seconds
Started May 19 01:32:54 PM PDT 24
Finished May 19 01:32:56 PM PDT 24
Peak memory 217732 kb
Host smart-a2fa6296-a814-4e82-ad9d-89ae1e03d8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375968553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3375968553
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3175115395
Short name T430
Test name
Test status
Simulation time 149945823 ps
CPU time 0.82 seconds
Started May 19 01:32:54 PM PDT 24
Finished May 19 01:32:56 PM PDT 24
Peak memory 200160 kb
Host smart-3cb08c3e-1fac-4777-886f-6c116b27a201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175115395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3175115395
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.41438711
Short name T398
Test name
Test status
Simulation time 1486077702 ps
CPU time 5.63 seconds
Started May 19 01:32:54 PM PDT 24
Finished May 19 01:33:01 PM PDT 24
Peak memory 200552 kb
Host smart-f6eb25c9-7a55-454b-8315-5b334af44b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41438711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.41438711
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1378851831
Short name T151
Test name
Test status
Simulation time 109998142 ps
CPU time 1.07 seconds
Started May 19 01:32:54 PM PDT 24
Finished May 19 01:32:56 PM PDT 24
Peak memory 200416 kb
Host smart-485cf491-4535-4422-b294-bf626161e530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378851831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1378851831
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.1543373541
Short name T145
Test name
Test status
Simulation time 116867948 ps
CPU time 1.16 seconds
Started May 19 01:32:54 PM PDT 24
Finished May 19 01:32:56 PM PDT 24
Peak memory 200524 kb
Host smart-04d41db7-5a71-40e8-bff2-02e6fe98b2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543373541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1543373541
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3682310548
Short name T448
Test name
Test status
Simulation time 133607451 ps
CPU time 1.71 seconds
Started May 19 01:33:05 PM PDT 24
Finished May 19 01:33:10 PM PDT 24
Peak memory 200440 kb
Host smart-2ca3591a-ebd0-4205-90ea-96708eb1e4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682310548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3682310548
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2663362618
Short name T173
Test name
Test status
Simulation time 78440409 ps
CPU time 0.77 seconds
Started May 19 01:33:03 PM PDT 24
Finished May 19 01:33:06 PM PDT 24
Peak memory 200456 kb
Host smart-20e3b8b0-3143-4dea-bbce-82d2cfedb260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663362618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2663362618
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2879332433
Short name T482
Test name
Test status
Simulation time 78442698 ps
CPU time 0.82 seconds
Started May 19 01:33:02 PM PDT 24
Finished May 19 01:33:05 PM PDT 24
Peak memory 200552 kb
Host smart-845a0595-f051-4cac-8304-fddc05585918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879332433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2879332433
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1795053021
Short name T338
Test name
Test status
Simulation time 2355094674 ps
CPU time 8.58 seconds
Started May 19 01:33:03 PM PDT 24
Finished May 19 01:33:15 PM PDT 24
Peak memory 222336 kb
Host smart-dad8bdc8-349c-49cb-b329-d183fb305a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795053021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1795053021
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.556235588
Short name T527
Test name
Test status
Simulation time 243541611 ps
CPU time 1.14 seconds
Started May 19 01:32:55 PM PDT 24
Finished May 19 01:32:58 PM PDT 24
Peak memory 217720 kb
Host smart-aa20657b-d6b3-42a1-b28e-5a3c3c7c0c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556235588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.556235588
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.324258253
Short name T204
Test name
Test status
Simulation time 97956713 ps
CPU time 0.81 seconds
Started May 19 01:32:57 PM PDT 24
Finished May 19 01:32:59 PM PDT 24
Peak memory 200236 kb
Host smart-8910a9d3-4381-4a9b-a804-47800294596a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324258253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.324258253
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3762618613
Short name T59
Test name
Test status
Simulation time 1776871371 ps
CPU time 6.47 seconds
Started May 19 01:33:01 PM PDT 24
Finished May 19 01:33:10 PM PDT 24
Peak memory 200648 kb
Host smart-1f468178-f346-4be3-9d05-491b88202dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762618613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3762618613
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.283766141
Short name T365
Test name
Test status
Simulation time 103858242 ps
CPU time 1.09 seconds
Started May 19 01:32:53 PM PDT 24
Finished May 19 01:32:55 PM PDT 24
Peak memory 200408 kb
Host smart-03fe5939-1544-40cd-aa50-03aa93eff923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283766141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.283766141
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3944055390
Short name T375
Test name
Test status
Simulation time 194982437 ps
CPU time 1.33 seconds
Started May 19 01:32:55 PM PDT 24
Finished May 19 01:32:58 PM PDT 24
Peak memory 200652 kb
Host smart-742add46-780f-4093-8da2-b5a43c649576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944055390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3944055390
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.901644987
Short name T334
Test name
Test status
Simulation time 3018172795 ps
CPU time 12.8 seconds
Started May 19 01:32:57 PM PDT 24
Finished May 19 01:33:11 PM PDT 24
Peak memory 200760 kb
Host smart-1056f77f-d8b1-49d4-8b4a-eb83d6d81ff9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901644987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.901644987
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3028301938
Short name T253
Test name
Test status
Simulation time 122910476 ps
CPU time 1.62 seconds
Started May 19 01:32:52 PM PDT 24
Finished May 19 01:32:54 PM PDT 24
Peak memory 208616 kb
Host smart-105637d6-623a-4fdf-a7a9-c313afe831c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028301938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3028301938
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2312557113
Short name T456
Test name
Test status
Simulation time 263372371 ps
CPU time 1.44 seconds
Started May 19 01:32:58 PM PDT 24
Finished May 19 01:33:01 PM PDT 24
Peak memory 200452 kb
Host smart-45ce96f9-3284-49cc-a69c-08b6f77f0abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312557113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2312557113
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2285378831
Short name T277
Test name
Test status
Simulation time 1893177482 ps
CPU time 8.24 seconds
Started May 19 01:33:03 PM PDT 24
Finished May 19 01:33:14 PM PDT 24
Peak memory 217548 kb
Host smart-85e8aab8-a8ec-4729-a79b-883b419e0331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285378831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2285378831
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.230361698
Short name T16
Test name
Test status
Simulation time 243038498 ps
CPU time 1.13 seconds
Started May 19 01:33:01 PM PDT 24
Finished May 19 01:33:10 PM PDT 24
Peak memory 217540 kb
Host smart-4985cb4c-50dd-46bd-aec8-d5aa0efb76ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230361698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.230361698
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.410109313
Short name T291
Test name
Test status
Simulation time 153400247 ps
CPU time 0.87 seconds
Started May 19 01:33:00 PM PDT 24
Finished May 19 01:33:03 PM PDT 24
Peak memory 200216 kb
Host smart-1270d0b2-611c-4844-858a-e24c68fa1a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410109313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.410109313
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.3720027845
Short name T209
Test name
Test status
Simulation time 1023919685 ps
CPU time 4.33 seconds
Started May 19 01:32:51 PM PDT 24
Finished May 19 01:32:56 PM PDT 24
Peak memory 200664 kb
Host smart-09ef4a66-b350-4840-a6fc-3b0f3c3184c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720027845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.3720027845
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1303213110
Short name T199
Test name
Test status
Simulation time 172242502 ps
CPU time 1.24 seconds
Started May 19 01:32:53 PM PDT 24
Finished May 19 01:32:54 PM PDT 24
Peak memory 200440 kb
Host smart-248bd7be-9399-4bde-b857-d8de4106d8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303213110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1303213110
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.1606572053
Short name T35
Test name
Test status
Simulation time 196778262 ps
CPU time 1.45 seconds
Started May 19 01:32:57 PM PDT 24
Finished May 19 01:32:59 PM PDT 24
Peak memory 200528 kb
Host smart-a1f598fa-3b14-43e8-aaab-ff708197d6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606572053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1606572053
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2526869504
Short name T129
Test name
Test status
Simulation time 5729701948 ps
CPU time 20.97 seconds
Started May 19 01:32:51 PM PDT 24
Finished May 19 01:33:13 PM PDT 24
Peak memory 209000 kb
Host smart-43e0fd07-f4eb-4623-b96b-8a72282cbc1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526869504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2526869504
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.4085289540
Short name T287
Test name
Test status
Simulation time 318781993 ps
CPU time 2.21 seconds
Started May 19 01:33:04 PM PDT 24
Finished May 19 01:33:08 PM PDT 24
Peak memory 200424 kb
Host smart-ab352476-dd19-4fc7-937b-6e39a972259d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085289540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.4085289540
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2469271387
Short name T265
Test name
Test status
Simulation time 275276070 ps
CPU time 1.46 seconds
Started May 19 01:32:52 PM PDT 24
Finished May 19 01:32:54 PM PDT 24
Peak memory 200428 kb
Host smart-9ce5cff9-f043-4c96-857d-db8dcfe4eeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469271387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2469271387
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1815681514
Short name T438
Test name
Test status
Simulation time 67704268 ps
CPU time 0.75 seconds
Started May 19 01:33:04 PM PDT 24
Finished May 19 01:33:07 PM PDT 24
Peak memory 200292 kb
Host smart-52824465-c9a4-4251-add2-f187a7e63fad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815681514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1815681514
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2468023575
Short name T39
Test name
Test status
Simulation time 1891596653 ps
CPU time 7.74 seconds
Started May 19 01:32:58 PM PDT 24
Finished May 19 01:33:07 PM PDT 24
Peak memory 217236 kb
Host smart-bb945b2e-c641-4f2e-aa34-6ee9f6748d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468023575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2468023575
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.450129292
Short name T411
Test name
Test status
Simulation time 244107701 ps
CPU time 1.16 seconds
Started May 19 01:33:04 PM PDT 24
Finished May 19 01:33:07 PM PDT 24
Peak memory 217488 kb
Host smart-ab54ddd4-1f27-4557-86f6-f8d81bd74e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450129292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.450129292
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.40378463
Short name T207
Test name
Test status
Simulation time 236875534 ps
CPU time 0.98 seconds
Started May 19 01:33:01 PM PDT 24
Finished May 19 01:33:04 PM PDT 24
Peak memory 200292 kb
Host smart-87061663-87bd-4d0e-90bd-7aaf6304db20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40378463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.40378463
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3677618637
Short name T372
Test name
Test status
Simulation time 837365004 ps
CPU time 4.22 seconds
Started May 19 01:33:00 PM PDT 24
Finished May 19 01:33:06 PM PDT 24
Peak memory 200680 kb
Host smart-51873810-ccb2-4faf-98d9-047c65680775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677618637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3677618637
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2889748003
Short name T278
Test name
Test status
Simulation time 104230677 ps
CPU time 1.03 seconds
Started May 19 01:32:55 PM PDT 24
Finished May 19 01:32:57 PM PDT 24
Peak memory 200432 kb
Host smart-b77100c5-11fd-476b-b311-1487da873238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889748003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2889748003
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2431969050
Short name T503
Test name
Test status
Simulation time 125569982 ps
CPU time 1.17 seconds
Started May 19 01:32:59 PM PDT 24
Finished May 19 01:33:01 PM PDT 24
Peak memory 200672 kb
Host smart-1e3aa5e9-7588-4ea1-9e1f-21f6a9dfc8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431969050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2431969050
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2508714379
Short name T454
Test name
Test status
Simulation time 1831217393 ps
CPU time 10.17 seconds
Started May 19 01:32:58 PM PDT 24
Finished May 19 01:33:10 PM PDT 24
Peak memory 209956 kb
Host smart-6920331e-0111-4a3b-bbdb-04128bebb9e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508714379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2508714379
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1353367561
Short name T317
Test name
Test status
Simulation time 529873700 ps
CPU time 2.7 seconds
Started May 19 01:33:04 PM PDT 24
Finished May 19 01:33:09 PM PDT 24
Peak memory 200448 kb
Host smart-756f8b92-18e9-4d64-878f-6df7d82748c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353367561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1353367561
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3099651807
Short name T407
Test name
Test status
Simulation time 134415084 ps
CPU time 1.04 seconds
Started May 19 01:33:05 PM PDT 24
Finished May 19 01:33:09 PM PDT 24
Peak memory 200440 kb
Host smart-d1263ebf-cf68-4a64-8906-121f5481d00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099651807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3099651807
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.2611145523
Short name T269
Test name
Test status
Simulation time 72152966 ps
CPU time 0.75 seconds
Started May 19 01:33:04 PM PDT 24
Finished May 19 01:33:07 PM PDT 24
Peak memory 200296 kb
Host smart-d64b97e6-ccdd-4d16-8d34-2c2634639784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611145523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2611145523
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1116153813
Short name T412
Test name
Test status
Simulation time 1227823496 ps
CPU time 5.71 seconds
Started May 19 01:33:04 PM PDT 24
Finished May 19 01:33:12 PM PDT 24
Peak memory 217596 kb
Host smart-332a31be-042c-43f8-9e3e-2de2f8b6093b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116153813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1116153813
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3614290708
Short name T218
Test name
Test status
Simulation time 244410207 ps
CPU time 1.06 seconds
Started May 19 01:32:58 PM PDT 24
Finished May 19 01:33:00 PM PDT 24
Peak memory 217648 kb
Host smart-b10f52f9-5b5c-4e48-ac02-77c810432cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614290708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3614290708
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.4230162501
Short name T239
Test name
Test status
Simulation time 78664214 ps
CPU time 0.73 seconds
Started May 19 01:33:03 PM PDT 24
Finished May 19 01:33:06 PM PDT 24
Peak memory 200264 kb
Host smart-e6d1315f-9063-4ab5-97ad-400994f237b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230162501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.4230162501
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3963356376
Short name T232
Test name
Test status
Simulation time 841213228 ps
CPU time 4.55 seconds
Started May 19 01:33:05 PM PDT 24
Finished May 19 01:33:12 PM PDT 24
Peak memory 200636 kb
Host smart-353d6077-1410-4705-8cee-161e5ea25ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963356376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3963356376
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.77146030
Short name T359
Test name
Test status
Simulation time 141151686 ps
CPU time 1.18 seconds
Started May 19 01:32:57 PM PDT 24
Finished May 19 01:32:59 PM PDT 24
Peak memory 200468 kb
Host smart-84be3493-afbc-45da-8602-9d9764fd3bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77146030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.77146030
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3385035207
Short name T493
Test name
Test status
Simulation time 203819134 ps
CPU time 1.4 seconds
Started May 19 01:33:03 PM PDT 24
Finished May 19 01:33:07 PM PDT 24
Peak memory 200648 kb
Host smart-f1180f39-3407-4475-b2be-2defee45b1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385035207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3385035207
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3772905280
Short name T335
Test name
Test status
Simulation time 9203348470 ps
CPU time 32.48 seconds
Started May 19 01:32:59 PM PDT 24
Finished May 19 01:33:33 PM PDT 24
Peak memory 200816 kb
Host smart-9e553dd2-6b1f-46f5-ace8-9464bcc39f2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772905280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3772905280
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.40433820
Short name T270
Test name
Test status
Simulation time 445909721 ps
CPU time 2.62 seconds
Started May 19 01:33:01 PM PDT 24
Finished May 19 01:33:05 PM PDT 24
Peak memory 200472 kb
Host smart-371c34e9-32a3-4f1a-bc51-78fbd3db8ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40433820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.40433820
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1418289467
Short name T302
Test name
Test status
Simulation time 227731004 ps
CPU time 1.56 seconds
Started May 19 01:33:00 PM PDT 24
Finished May 19 01:33:04 PM PDT 24
Peak memory 200660 kb
Host smart-97d13d58-11a2-4733-92a8-ac2e8680a2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418289467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1418289467
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3176829092
Short name T252
Test name
Test status
Simulation time 75282971 ps
CPU time 0.8 seconds
Started May 19 01:32:18 PM PDT 24
Finished May 19 01:32:20 PM PDT 24
Peak memory 200200 kb
Host smart-347b1e8e-6bc9-4ad2-a461-14d20c6b1538
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176829092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3176829092
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2712714518
Short name T51
Test name
Test status
Simulation time 1897304694 ps
CPU time 7.04 seconds
Started May 19 01:32:33 PM PDT 24
Finished May 19 01:32:43 PM PDT 24
Peak memory 222064 kb
Host smart-e67f997e-470c-47f8-9edf-4d565e4575e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712714518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2712714518
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2657913899
Short name T515
Test name
Test status
Simulation time 244243868 ps
CPU time 1.15 seconds
Started May 19 01:32:26 PM PDT 24
Finished May 19 01:32:29 PM PDT 24
Peak memory 217508 kb
Host smart-393becc4-d2fa-4416-bf37-74a2f98f3b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657913899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2657913899
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3355574382
Short name T221
Test name
Test status
Simulation time 141370446 ps
CPU time 0.83 seconds
Started May 19 01:32:25 PM PDT 24
Finished May 19 01:32:28 PM PDT 24
Peak memory 200288 kb
Host smart-29ed36c3-759f-4626-998d-0e977d059613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355574382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3355574382
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2327974392
Short name T66
Test name
Test status
Simulation time 972529347 ps
CPU time 4.75 seconds
Started May 19 01:32:28 PM PDT 24
Finished May 19 01:32:35 PM PDT 24
Peak memory 200140 kb
Host smart-fc624c64-026d-4097-8ae3-e38493ba762f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327974392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2327974392
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3910414701
Short name T84
Test name
Test status
Simulation time 16529778188 ps
CPU time 29.01 seconds
Started May 19 01:32:17 PM PDT 24
Finished May 19 01:32:48 PM PDT 24
Peak memory 218492 kb
Host smart-5c115ef0-bc7e-4579-95c0-fa525851f83c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910414701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3910414701
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.4257851593
Short name T259
Test name
Test status
Simulation time 102074227 ps
CPU time 1.01 seconds
Started May 19 01:32:16 PM PDT 24
Finished May 19 01:32:18 PM PDT 24
Peak memory 200444 kb
Host smart-59ab99dc-53b9-4736-9382-a88817a337cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257851593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.4257851593
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.3337804989
Short name T506
Test name
Test status
Simulation time 108320027 ps
CPU time 1.2 seconds
Started May 19 01:32:27 PM PDT 24
Finished May 19 01:32:30 PM PDT 24
Peak memory 200660 kb
Host smart-f314f2f0-9937-4b87-8d87-181d6912ebe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337804989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3337804989
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1126155009
Short name T182
Test name
Test status
Simulation time 5474734456 ps
CPU time 20.67 seconds
Started May 19 01:32:31 PM PDT 24
Finished May 19 01:32:54 PM PDT 24
Peak memory 216596 kb
Host smart-65b57400-c415-4354-8859-20d5719db6d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126155009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1126155009
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.131779753
Short name T217
Test name
Test status
Simulation time 323325019 ps
CPU time 2.37 seconds
Started May 19 01:32:27 PM PDT 24
Finished May 19 01:32:31 PM PDT 24
Peak memory 200440 kb
Host smart-841bcfe1-73cc-496c-94fa-c4fcac977c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131779753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.131779753
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.992294342
Short name T166
Test name
Test status
Simulation time 104665715 ps
CPU time 0.91 seconds
Started May 19 01:32:31 PM PDT 24
Finished May 19 01:32:35 PM PDT 24
Peak memory 200332 kb
Host smart-86d1f846-1483-4d71-a87b-5c63d2076ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992294342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.992294342
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.2466721681
Short name T485
Test name
Test status
Simulation time 60984351 ps
CPU time 0.78 seconds
Started May 19 01:33:00 PM PDT 24
Finished May 19 01:33:03 PM PDT 24
Peak memory 200312 kb
Host smart-8576a521-8ad4-4282-9425-65885efad768
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466721681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.2466721681
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.100752495
Short name T56
Test name
Test status
Simulation time 1891959135 ps
CPU time 6.89 seconds
Started May 19 01:33:03 PM PDT 24
Finished May 19 01:33:12 PM PDT 24
Peak memory 222124 kb
Host smart-d39b7af3-89ad-4bd6-a1a5-c508460904ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100752495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.100752495
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3888778970
Short name T17
Test name
Test status
Simulation time 244774052 ps
CPU time 1.03 seconds
Started May 19 01:33:00 PM PDT 24
Finished May 19 01:33:03 PM PDT 24
Peak memory 217588 kb
Host smart-24941d2f-bddc-4699-8b07-ff4bd9c1c867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888778970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3888778970
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1142797736
Short name T464
Test name
Test status
Simulation time 120991006 ps
CPU time 0.81 seconds
Started May 19 01:33:04 PM PDT 24
Finished May 19 01:33:07 PM PDT 24
Peak memory 200276 kb
Host smart-858908a7-b15f-40ac-a70d-44a2213417b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142797736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1142797736
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2342329613
Short name T128
Test name
Test status
Simulation time 1988593954 ps
CPU time 8.01 seconds
Started May 19 01:33:04 PM PDT 24
Finished May 19 01:33:14 PM PDT 24
Peak memory 200640 kb
Host smart-a166d128-172a-4415-b08e-12dceea79fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342329613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2342329613
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.746173027
Short name T9
Test name
Test status
Simulation time 101734315 ps
CPU time 0.99 seconds
Started May 19 01:33:00 PM PDT 24
Finished May 19 01:33:02 PM PDT 24
Peak memory 200488 kb
Host smart-19816e0d-5d76-48df-b434-2cc8c89bb930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746173027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.746173027
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.1218741582
Short name T195
Test name
Test status
Simulation time 224400839 ps
CPU time 1.53 seconds
Started May 19 01:33:03 PM PDT 24
Finished May 19 01:33:08 PM PDT 24
Peak memory 200704 kb
Host smart-ce182b21-a103-4c04-9bea-b5c8b950b01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218741582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.1218741582
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1859052344
Short name T106
Test name
Test status
Simulation time 7291723072 ps
CPU time 28.89 seconds
Started May 19 01:32:56 PM PDT 24
Finished May 19 01:33:26 PM PDT 24
Peak memory 200752 kb
Host smart-d844cb77-6698-42fe-b792-e8adbe4294ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859052344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1859052344
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.29168699
Short name T489
Test name
Test status
Simulation time 298333216 ps
CPU time 2.03 seconds
Started May 19 01:33:04 PM PDT 24
Finished May 19 01:33:09 PM PDT 24
Peak memory 208636 kb
Host smart-3c051e58-deff-4e0b-81ac-446ac17c8cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29168699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.29168699
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2142006115
Short name T256
Test name
Test status
Simulation time 104245813 ps
CPU time 1.06 seconds
Started May 19 01:32:56 PM PDT 24
Finished May 19 01:32:58 PM PDT 24
Peak memory 200504 kb
Host smart-9ad613fc-776a-4088-bd45-80c104c0e7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142006115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2142006115
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2316181889
Short name T436
Test name
Test status
Simulation time 65914638 ps
CPU time 0.85 seconds
Started May 19 01:33:01 PM PDT 24
Finished May 19 01:33:04 PM PDT 24
Peak memory 200312 kb
Host smart-5b03769b-3e27-4bf5-ab86-a0ce09072247
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316181889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2316181889
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3206198051
Short name T536
Test name
Test status
Simulation time 1883962182 ps
CPU time 8.57 seconds
Started May 19 01:32:56 PM PDT 24
Finished May 19 01:33:06 PM PDT 24
Peak memory 221608 kb
Host smart-6d60e7a5-51eb-4e05-a819-23b00701b9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206198051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3206198051
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3349896587
Short name T150
Test name
Test status
Simulation time 246156451 ps
CPU time 1.08 seconds
Started May 19 01:33:06 PM PDT 24
Finished May 19 01:33:10 PM PDT 24
Peak memory 217548 kb
Host smart-cbd0685f-3e33-470e-986c-ac9fcc6d6845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349896587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3349896587
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.3308310541
Short name T27
Test name
Test status
Simulation time 98785556 ps
CPU time 0.8 seconds
Started May 19 01:33:06 PM PDT 24
Finished May 19 01:33:10 PM PDT 24
Peak memory 200292 kb
Host smart-99be32fe-1d4f-4edb-9b52-66b8cecca8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308310541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3308310541
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.123513247
Short name T358
Test name
Test status
Simulation time 1645754304 ps
CPU time 6.23 seconds
Started May 19 01:33:02 PM PDT 24
Finished May 19 01:33:10 PM PDT 24
Peak memory 200600 kb
Host smart-78c0b28a-6299-48c9-aed3-fbf0d89df66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123513247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.123513247
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.943102152
Short name T354
Test name
Test status
Simulation time 155824072 ps
CPU time 1.16 seconds
Started May 19 01:33:03 PM PDT 24
Finished May 19 01:33:07 PM PDT 24
Peak memory 200504 kb
Host smart-aeba7508-7df9-4823-87fc-42213987f1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943102152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.943102152
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.731570695
Short name T328
Test name
Test status
Simulation time 199656859 ps
CPU time 1.35 seconds
Started May 19 01:32:59 PM PDT 24
Finished May 19 01:33:01 PM PDT 24
Peak memory 200624 kb
Host smart-fd3f5291-d77a-4a8b-8cf2-bcea175bd827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731570695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.731570695
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.1956033139
Short name T426
Test name
Test status
Simulation time 2447965723 ps
CPU time 11.62 seconds
Started May 19 01:32:59 PM PDT 24
Finished May 19 01:33:12 PM PDT 24
Peak memory 200764 kb
Host smart-50eed45e-cd36-44bd-a64c-856c15aa1e7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956033139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.1956033139
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1599107825
Short name T444
Test name
Test status
Simulation time 114896876 ps
CPU time 1.52 seconds
Started May 19 01:33:03 PM PDT 24
Finished May 19 01:33:07 PM PDT 24
Peak memory 200424 kb
Host smart-49dc9602-a327-4887-9db0-3224b11d2a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599107825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1599107825
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3271774250
Short name T465
Test name
Test status
Simulation time 153658032 ps
CPU time 1.15 seconds
Started May 19 01:33:01 PM PDT 24
Finished May 19 01:33:04 PM PDT 24
Peak memory 200464 kb
Host smart-6d1ee703-a0e3-487c-9a12-35a7e61c6325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271774250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3271774250
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1589256753
Short name T175
Test name
Test status
Simulation time 64565904 ps
CPU time 0.78 seconds
Started May 19 01:33:02 PM PDT 24
Finished May 19 01:33:06 PM PDT 24
Peak memory 200208 kb
Host smart-4a27c639-5d5a-450f-b17d-53cb753e7fcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589256753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1589256753
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1381897542
Short name T318
Test name
Test status
Simulation time 1220118830 ps
CPU time 6.09 seconds
Started May 19 01:33:05 PM PDT 24
Finished May 19 01:33:14 PM PDT 24
Peak memory 217524 kb
Host smart-ddec7a6d-28f3-4b2f-94f3-cc4b3131103a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381897542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1381897542
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.328552878
Short name T409
Test name
Test status
Simulation time 245025331 ps
CPU time 1.12 seconds
Started May 19 01:33:01 PM PDT 24
Finished May 19 01:33:05 PM PDT 24
Peak memory 217532 kb
Host smart-a43d032f-c393-439b-b5e3-751313435a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328552878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.328552878
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.4006669710
Short name T24
Test name
Test status
Simulation time 216246352 ps
CPU time 0.93 seconds
Started May 19 01:33:03 PM PDT 24
Finished May 19 01:33:07 PM PDT 24
Peak memory 200304 kb
Host smart-3c253f03-46d1-4699-8974-6d0a37f0bc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006669710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.4006669710
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.3525116722
Short name T183
Test name
Test status
Simulation time 1000952574 ps
CPU time 5.27 seconds
Started May 19 01:33:07 PM PDT 24
Finished May 19 01:33:15 PM PDT 24
Peak memory 200628 kb
Host smart-c9385ec8-2ada-4d50-be70-aaee05d73764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525116722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3525116722
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.95475788
Short name T91
Test name
Test status
Simulation time 169703303 ps
CPU time 1.23 seconds
Started May 19 01:33:15 PM PDT 24
Finished May 19 01:33:17 PM PDT 24
Peak memory 200520 kb
Host smart-8c6f8fb1-8c88-4fdb-a64b-c4db2578bdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95475788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.95475788
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.852242201
Short name T273
Test name
Test status
Simulation time 195525280 ps
CPU time 1.39 seconds
Started May 19 01:33:01 PM PDT 24
Finished May 19 01:33:05 PM PDT 24
Peak memory 200684 kb
Host smart-1f795def-1b29-41b1-85d4-bd47c29e219b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852242201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.852242201
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1398985969
Short name T197
Test name
Test status
Simulation time 3575439460 ps
CPU time 15.8 seconds
Started May 19 01:33:05 PM PDT 24
Finished May 19 01:33:24 PM PDT 24
Peak memory 200788 kb
Host smart-fbe3ec37-2b06-4e87-847c-8f297c44edbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398985969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1398985969
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.758631503
Short name T355
Test name
Test status
Simulation time 361541912 ps
CPU time 2.37 seconds
Started May 19 01:33:01 PM PDT 24
Finished May 19 01:33:06 PM PDT 24
Peak memory 200452 kb
Host smart-e37a70da-98c3-4905-8af6-fcf3b88edcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758631503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.758631503
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2323687070
Short name T6
Test name
Test status
Simulation time 188869656 ps
CPU time 1.33 seconds
Started May 19 01:33:02 PM PDT 24
Finished May 19 01:33:05 PM PDT 24
Peak memory 200664 kb
Host smart-450371a1-5564-4f99-be1b-47e460d185d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323687070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2323687070
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.3159399422
Short name T420
Test name
Test status
Simulation time 72408158 ps
CPU time 0.74 seconds
Started May 19 01:33:06 PM PDT 24
Finished May 19 01:33:10 PM PDT 24
Peak memory 200256 kb
Host smart-6069d716-1bc1-4a80-8cd7-9c60a3288057
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159399422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.3159399422
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.4099503692
Short name T347
Test name
Test status
Simulation time 1225615635 ps
CPU time 6.19 seconds
Started May 19 01:33:04 PM PDT 24
Finished May 19 01:33:13 PM PDT 24
Peak memory 218316 kb
Host smart-c264e8a8-a7fa-435a-b14c-1d1f22028b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099503692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.4099503692
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2286823386
Short name T396
Test name
Test status
Simulation time 243777843 ps
CPU time 1.1 seconds
Started May 19 01:33:06 PM PDT 24
Finished May 19 01:33:10 PM PDT 24
Peak memory 217604 kb
Host smart-addd92c6-c49b-4000-b6ca-ecc00942d349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286823386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2286823386
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2736360246
Short name T507
Test name
Test status
Simulation time 190916647 ps
CPU time 0.95 seconds
Started May 19 01:33:09 PM PDT 24
Finished May 19 01:33:12 PM PDT 24
Peak memory 200248 kb
Host smart-e4831715-9c0e-4813-b0a1-4347e40fdb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736360246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2736360246
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.2155726479
Short name T477
Test name
Test status
Simulation time 944950251 ps
CPU time 4.97 seconds
Started May 19 01:33:02 PM PDT 24
Finished May 19 01:33:10 PM PDT 24
Peak memory 200696 kb
Host smart-d43ea810-65db-4268-8f39-8b466d8d0f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155726479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.2155726479
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2781120133
Short name T442
Test name
Test status
Simulation time 115273760 ps
CPU time 1.03 seconds
Started May 19 01:33:21 PM PDT 24
Finished May 19 01:33:24 PM PDT 24
Peak memory 200496 kb
Host smart-fa2ddee4-a2ab-4cbb-a467-0a71a60591a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781120133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2781120133
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.1541986375
Short name T140
Test name
Test status
Simulation time 247365380 ps
CPU time 1.48 seconds
Started May 19 01:33:05 PM PDT 24
Finished May 19 01:33:09 PM PDT 24
Peak memory 200660 kb
Host smart-3801373c-bcf1-4b01-863e-73b8551526dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541986375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1541986375
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.596598586
Short name T292
Test name
Test status
Simulation time 4528729061 ps
CPU time 19.6 seconds
Started May 19 01:33:09 PM PDT 24
Finished May 19 01:33:31 PM PDT 24
Peak memory 200804 kb
Host smart-8a47c2f9-b8f0-494a-85bb-fc53691b1319
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596598586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.596598586
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2258791825
Short name T263
Test name
Test status
Simulation time 132165969 ps
CPU time 1.69 seconds
Started May 19 01:33:06 PM PDT 24
Finished May 19 01:33:10 PM PDT 24
Peak memory 208644 kb
Host smart-ff112931-7ca8-4982-9939-16e05f4a4262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258791825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2258791825
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2849568339
Short name T279
Test name
Test status
Simulation time 219578979 ps
CPU time 1.42 seconds
Started May 19 01:33:02 PM PDT 24
Finished May 19 01:33:06 PM PDT 24
Peak memory 200476 kb
Host smart-789919ad-737f-492f-a3fd-9248a6c9178b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849568339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2849568339
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.429119263
Short name T201
Test name
Test status
Simulation time 74821270 ps
CPU time 0.84 seconds
Started May 19 01:33:02 PM PDT 24
Finished May 19 01:33:06 PM PDT 24
Peak memory 200516 kb
Host smart-62a883f9-086e-4475-ba69-c94b59ae4660
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429119263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.429119263
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.2720157134
Short name T73
Test name
Test status
Simulation time 1226671356 ps
CPU time 6.01 seconds
Started May 19 01:33:07 PM PDT 24
Finished May 19 01:33:15 PM PDT 24
Peak memory 221940 kb
Host smart-e8e4b3da-9fbc-437f-9253-3edf701b6e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720157134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2720157134
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.358164935
Short name T384
Test name
Test status
Simulation time 243827334 ps
CPU time 1.07 seconds
Started May 19 01:33:04 PM PDT 24
Finished May 19 01:33:08 PM PDT 24
Peak memory 217524 kb
Host smart-6ae1d933-5cce-455d-b3e5-721189aaa482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358164935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.358164935
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1966136833
Short name T246
Test name
Test status
Simulation time 189939146 ps
CPU time 0.88 seconds
Started May 19 01:33:06 PM PDT 24
Finished May 19 01:33:09 PM PDT 24
Peak memory 200236 kb
Host smart-cfa66ba5-d22c-43d6-bcb6-f83f7afc30db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966136833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1966136833
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.1439342541
Short name T377
Test name
Test status
Simulation time 1969924463 ps
CPU time 7.26 seconds
Started May 19 01:33:05 PM PDT 24
Finished May 19 01:33:15 PM PDT 24
Peak memory 200664 kb
Host smart-e6f8d853-817b-408f-b00a-46155a0ab2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439342541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1439342541
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.2299508396
Short name T428
Test name
Test status
Simulation time 155788766 ps
CPU time 1.17 seconds
Started May 19 01:33:03 PM PDT 24
Finished May 19 01:33:06 PM PDT 24
Peak memory 200696 kb
Host smart-cb7d10ad-02d0-48d9-9678-37dddd9adc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299508396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.2299508396
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.747294419
Short name T490
Test name
Test status
Simulation time 253573258 ps
CPU time 1.55 seconds
Started May 19 01:33:12 PM PDT 24
Finished May 19 01:33:15 PM PDT 24
Peak memory 200636 kb
Host smart-63b97361-0d03-40ff-a08b-ab4498e1fe1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747294419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.747294419
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1804338520
Short name T109
Test name
Test status
Simulation time 7523417391 ps
CPU time 27.71 seconds
Started May 19 01:33:10 PM PDT 24
Finished May 19 01:33:39 PM PDT 24
Peak memory 210384 kb
Host smart-74e6dd11-f564-4a44-b39b-d2f098475641
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804338520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1804338520
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.528898066
Short name T144
Test name
Test status
Simulation time 399668912 ps
CPU time 2.6 seconds
Started May 19 01:33:09 PM PDT 24
Finished May 19 01:33:14 PM PDT 24
Peak memory 200392 kb
Host smart-a1898000-fbc3-4285-aeec-60016483238f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528898066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.528898066
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.2573103525
Short name T304
Test name
Test status
Simulation time 133982929 ps
CPU time 1.03 seconds
Started May 19 01:33:03 PM PDT 24
Finished May 19 01:33:07 PM PDT 24
Peak memory 200452 kb
Host smart-be581771-b98b-44dc-b107-293f704dde6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573103525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2573103525
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3728430892
Short name T244
Test name
Test status
Simulation time 71814425 ps
CPU time 0.77 seconds
Started May 19 01:33:26 PM PDT 24
Finished May 19 01:33:31 PM PDT 24
Peak memory 200292 kb
Host smart-9edd358d-c532-45dc-91e5-ee5d356c3529
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728430892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3728430892
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.7817749
Short name T54
Test name
Test status
Simulation time 1900453215 ps
CPU time 6.96 seconds
Started May 19 01:33:07 PM PDT 24
Finished May 19 01:33:16 PM PDT 24
Peak memory 217584 kb
Host smart-b9df30ec-8b6f-406b-acde-8ad1a01dfa3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7817749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.7817749
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2602019175
Short name T223
Test name
Test status
Simulation time 245416021 ps
CPU time 1.06 seconds
Started May 19 01:33:08 PM PDT 24
Finished May 19 01:33:11 PM PDT 24
Peak memory 217744 kb
Host smart-c55daccb-0d81-4cbe-aa5a-a1c3f01d2353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602019175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2602019175
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3603736959
Short name T528
Test name
Test status
Simulation time 194287195 ps
CPU time 1.02 seconds
Started May 19 01:33:10 PM PDT 24
Finished May 19 01:33:13 PM PDT 24
Peak memory 200244 kb
Host smart-1c35b07a-4e6b-45f3-a8ec-d7ae57ad6344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603736959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3603736959
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.102077063
Short name T473
Test name
Test status
Simulation time 1364335702 ps
CPU time 5.53 seconds
Started May 19 01:33:10 PM PDT 24
Finished May 19 01:33:17 PM PDT 24
Peak memory 200644 kb
Host smart-281e7402-23ca-4dde-9db1-b020cd4e725c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102077063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.102077063
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.321664975
Short name T367
Test name
Test status
Simulation time 161943524 ps
CPU time 1.22 seconds
Started May 19 01:33:08 PM PDT 24
Finished May 19 01:33:11 PM PDT 24
Peak memory 200500 kb
Host smart-921682e3-c2ba-49e8-abc6-b91b788e9683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321664975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.321664975
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2811197570
Short name T449
Test name
Test status
Simulation time 121188994 ps
CPU time 1.19 seconds
Started May 19 01:33:06 PM PDT 24
Finished May 19 01:33:10 PM PDT 24
Peak memory 200660 kb
Host smart-5f80c1a4-d7be-4e3e-a0e3-8450fa37a368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811197570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2811197570
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.97356312
Short name T458
Test name
Test status
Simulation time 2329846832 ps
CPU time 8.59 seconds
Started May 19 01:33:24 PM PDT 24
Finished May 19 01:33:37 PM PDT 24
Peak memory 208956 kb
Host smart-90e1a2ab-766e-4a77-9453-46311d048b40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97356312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.97356312
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3727254161
Short name T343
Test name
Test status
Simulation time 123652225 ps
CPU time 1.69 seconds
Started May 19 01:33:09 PM PDT 24
Finished May 19 01:33:13 PM PDT 24
Peak memory 208596 kb
Host smart-10082651-284b-4b64-bbbf-15189d800305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727254161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3727254161
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2600071398
Short name T271
Test name
Test status
Simulation time 89995618 ps
CPU time 0.95 seconds
Started May 19 01:33:06 PM PDT 24
Finished May 19 01:33:10 PM PDT 24
Peak memory 200420 kb
Host smart-f0c61962-1ddb-4369-8ea2-1df84172343b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600071398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2600071398
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2586448400
Short name T479
Test name
Test status
Simulation time 61280578 ps
CPU time 0.79 seconds
Started May 19 01:33:17 PM PDT 24
Finished May 19 01:33:19 PM PDT 24
Peak memory 200288 kb
Host smart-e107ab05-59f2-4d27-ba6b-6d9ba9730067
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586448400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2586448400
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1518647516
Short name T387
Test name
Test status
Simulation time 1913505125 ps
CPU time 7.41 seconds
Started May 19 01:33:25 PM PDT 24
Finished May 19 01:33:37 PM PDT 24
Peak memory 222020 kb
Host smart-a525d608-6aa7-4c2f-8423-4577d45672e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518647516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1518647516
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2115153370
Short name T403
Test name
Test status
Simulation time 244456092 ps
CPU time 1.2 seconds
Started May 19 01:33:11 PM PDT 24
Finished May 19 01:33:14 PM PDT 24
Peak memory 217564 kb
Host smart-8092f9f7-53c2-4c9b-8e9e-6044fe330b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115153370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2115153370
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1948656046
Short name T351
Test name
Test status
Simulation time 136605960 ps
CPU time 0.82 seconds
Started May 19 01:33:14 PM PDT 24
Finished May 19 01:33:15 PM PDT 24
Peak memory 200224 kb
Host smart-1fc8450a-f3f7-4b83-891e-aa179f2125ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948656046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1948656046
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.392225843
Short name T360
Test name
Test status
Simulation time 1223831183 ps
CPU time 5.29 seconds
Started May 19 01:33:23 PM PDT 24
Finished May 19 01:33:32 PM PDT 24
Peak memory 200656 kb
Host smart-989f83a5-f784-415e-bebb-bb5e2ad446fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392225843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.392225843
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2021795046
Short name T165
Test name
Test status
Simulation time 154582774 ps
CPU time 1.16 seconds
Started May 19 01:33:21 PM PDT 24
Finished May 19 01:33:25 PM PDT 24
Peak memory 200436 kb
Host smart-a602009f-1593-4f34-ab68-1004c3c035c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021795046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2021795046
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.1245370485
Short name T397
Test name
Test status
Simulation time 121577537 ps
CPU time 1.2 seconds
Started May 19 01:33:07 PM PDT 24
Finished May 19 01:33:11 PM PDT 24
Peak memory 200616 kb
Host smart-cec47f60-137b-4448-8af7-5118f7ccd157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245370485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1245370485
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3823909169
Short name T283
Test name
Test status
Simulation time 4458034661 ps
CPU time 20.65 seconds
Started May 19 01:33:23 PM PDT 24
Finished May 19 01:33:48 PM PDT 24
Peak memory 209024 kb
Host smart-7db6f3a8-1fc7-4f41-bd90-ab3e86f9bc1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823909169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3823909169
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3076971045
Short name T480
Test name
Test status
Simulation time 115863557 ps
CPU time 1.51 seconds
Started May 19 01:33:07 PM PDT 24
Finished May 19 01:33:11 PM PDT 24
Peak memory 200496 kb
Host smart-b497cf0d-6d50-41be-94bd-abf26cfb6be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076971045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3076971045
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2735642575
Short name T64
Test name
Test status
Simulation time 119205628 ps
CPU time 1.08 seconds
Started May 19 01:33:10 PM PDT 24
Finished May 19 01:33:13 PM PDT 24
Peak memory 200432 kb
Host smart-1fc5aea7-a8e9-4b3f-b198-3ffa1f96d859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735642575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2735642575
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3346865087
Short name T153
Test name
Test status
Simulation time 115818617 ps
CPU time 0.9 seconds
Started May 19 01:33:10 PM PDT 24
Finished May 19 01:33:13 PM PDT 24
Peak memory 200260 kb
Host smart-609e1f2e-ae93-43c1-a2a6-de4eed76e2f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346865087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3346865087
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3149449811
Short name T69
Test name
Test status
Simulation time 1894837030 ps
CPU time 6.92 seconds
Started May 19 01:33:20 PM PDT 24
Finished May 19 01:33:29 PM PDT 24
Peak memory 218060 kb
Host smart-f1079c0b-59f8-42eb-baf1-6bfd5f863881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149449811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3149449811
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1715735992
Short name T230
Test name
Test status
Simulation time 243733434 ps
CPU time 1.09 seconds
Started May 19 01:33:20 PM PDT 24
Finished May 19 01:33:23 PM PDT 24
Peak memory 217536 kb
Host smart-3af3cdcd-84d5-4c47-ac4c-5bd7083bbed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715735992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1715735992
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.4212276603
Short name T513
Test name
Test status
Simulation time 213235722 ps
CPU time 1 seconds
Started May 19 01:33:10 PM PDT 24
Finished May 19 01:33:13 PM PDT 24
Peak memory 200256 kb
Host smart-6fc5040d-c1bc-4798-aaef-63d2eebf8219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212276603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.4212276603
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1267032982
Short name T68
Test name
Test status
Simulation time 1671838263 ps
CPU time 6.83 seconds
Started May 19 01:33:15 PM PDT 24
Finished May 19 01:33:23 PM PDT 24
Peak memory 200636 kb
Host smart-25e7e587-0980-4c6e-bbac-e61c8d860e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267032982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1267032982
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2071548384
Short name T65
Test name
Test status
Simulation time 102188783 ps
CPU time 0.96 seconds
Started May 19 01:33:25 PM PDT 24
Finished May 19 01:33:30 PM PDT 24
Peak memory 200476 kb
Host smart-4c915d53-1ee7-4e06-9b75-7c4c85b809b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071548384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2071548384
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.3919404247
Short name T326
Test name
Test status
Simulation time 121789121 ps
CPU time 1.23 seconds
Started May 19 01:33:22 PM PDT 24
Finished May 19 01:33:26 PM PDT 24
Peak memory 200640 kb
Host smart-0bbd9e5d-146c-48f7-b416-bb73c53f2a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919404247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.3919404247
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2273135813
Short name T314
Test name
Test status
Simulation time 7249875152 ps
CPU time 25.01 seconds
Started May 19 01:33:23 PM PDT 24
Finished May 19 01:33:52 PM PDT 24
Peak memory 200804 kb
Host smart-81cca017-6a74-454c-8173-b48f9a4d2317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273135813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2273135813
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.4134769063
Short name T509
Test name
Test status
Simulation time 482452549 ps
CPU time 2.7 seconds
Started May 19 01:33:11 PM PDT 24
Finished May 19 01:33:15 PM PDT 24
Peak memory 200404 kb
Host smart-268cadd8-3e10-467c-a1a4-2fbc377a788a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134769063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.4134769063
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2159375958
Short name T228
Test name
Test status
Simulation time 65371143 ps
CPU time 0.78 seconds
Started May 19 01:33:21 PM PDT 24
Finished May 19 01:33:24 PM PDT 24
Peak memory 200524 kb
Host smart-94ef2f47-4ffa-405b-8246-f1ea1b8c6ec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159375958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2159375958
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.275771915
Short name T306
Test name
Test status
Simulation time 2349377844 ps
CPU time 8.43 seconds
Started May 19 01:33:23 PM PDT 24
Finished May 19 01:33:35 PM PDT 24
Peak memory 218168 kb
Host smart-19da810a-4afa-463d-83fb-dfadd9eb564d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275771915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.275771915
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2250039135
Short name T31
Test name
Test status
Simulation time 243699930 ps
CPU time 1.06 seconds
Started May 19 01:33:21 PM PDT 24
Finished May 19 01:33:24 PM PDT 24
Peak memory 217568 kb
Host smart-c8c2b419-9567-406a-a35c-6b0ac5e87036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250039135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2250039135
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.1077186952
Short name T193
Test name
Test status
Simulation time 123526019 ps
CPU time 0.83 seconds
Started May 19 01:33:14 PM PDT 24
Finished May 19 01:33:16 PM PDT 24
Peak memory 200308 kb
Host smart-f5565efa-3def-4e6f-a6f1-2f66a7b2a68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077186952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1077186952
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2109678211
Short name T286
Test name
Test status
Simulation time 1429624813 ps
CPU time 5.47 seconds
Started May 19 01:33:11 PM PDT 24
Finished May 19 01:33:18 PM PDT 24
Peak memory 200600 kb
Host smart-7365b1a5-5a90-4886-ac02-b17c21eb2aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109678211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2109678211
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1927463383
Short name T152
Test name
Test status
Simulation time 142860927 ps
CPU time 1.22 seconds
Started May 19 01:33:18 PM PDT 24
Finished May 19 01:33:20 PM PDT 24
Peak memory 200436 kb
Host smart-a93b1356-cf93-4bd9-9c69-3f7c21e77100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927463383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1927463383
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.1878897744
Short name T362
Test name
Test status
Simulation time 118041428 ps
CPU time 1.22 seconds
Started May 19 01:33:17 PM PDT 24
Finished May 19 01:33:19 PM PDT 24
Peak memory 200656 kb
Host smart-3d75570d-f866-4d45-ad68-6841cab7ba75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878897744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1878897744
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1881686313
Short name T179
Test name
Test status
Simulation time 843335169 ps
CPU time 3.87 seconds
Started May 19 01:33:10 PM PDT 24
Finished May 19 01:33:15 PM PDT 24
Peak memory 200700 kb
Host smart-821283a6-659c-4112-be0c-fdee5ae35670
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881686313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1881686313
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1248449879
Short name T10
Test name
Test status
Simulation time 355157275 ps
CPU time 2.31 seconds
Started May 19 01:33:09 PM PDT 24
Finished May 19 01:33:13 PM PDT 24
Peak memory 200408 kb
Host smart-2c4892a2-0788-450f-99e2-fa96fc2a2ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248449879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1248449879
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3351471547
Short name T90
Test name
Test status
Simulation time 148735487 ps
CPU time 1.19 seconds
Started May 19 01:33:10 PM PDT 24
Finished May 19 01:33:13 PM PDT 24
Peak memory 200700 kb
Host smart-977fefb4-5a67-42c3-9e56-2463227c68f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351471547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3351471547
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.168589257
Short name T305
Test name
Test status
Simulation time 78749496 ps
CPU time 0.8 seconds
Started May 19 01:33:18 PM PDT 24
Finished May 19 01:33:20 PM PDT 24
Peak memory 200312 kb
Host smart-e22576cf-2207-4088-be74-1b90cf87b794
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168589257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.168589257
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2123844582
Short name T276
Test name
Test status
Simulation time 1226089532 ps
CPU time 5.44 seconds
Started May 19 01:33:21 PM PDT 24
Finished May 19 01:33:29 PM PDT 24
Peak memory 217016 kb
Host smart-12efb424-eae5-4281-8e80-373a51830b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123844582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2123844582
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.200741001
Short name T136
Test name
Test status
Simulation time 250413608 ps
CPU time 1.08 seconds
Started May 19 01:33:25 PM PDT 24
Finished May 19 01:33:31 PM PDT 24
Peak memory 217580 kb
Host smart-b7f82f29-1dd8-4a20-898f-691763ae76fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200741001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.200741001
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2309221380
Short name T238
Test name
Test status
Simulation time 102286446 ps
CPU time 0.78 seconds
Started May 19 01:33:12 PM PDT 24
Finished May 19 01:33:14 PM PDT 24
Peak memory 200268 kb
Host smart-d96bdcb6-474e-4542-9092-a20193c6b671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309221380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2309221380
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2787695401
Short name T414
Test name
Test status
Simulation time 752409215 ps
CPU time 3.79 seconds
Started May 19 01:33:07 PM PDT 24
Finished May 19 01:33:13 PM PDT 24
Peak memory 200568 kb
Host smart-f3b0123a-7c55-4003-8cb7-f67fb13419b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787695401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2787695401
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.623356738
Short name T431
Test name
Test status
Simulation time 189167230 ps
CPU time 1.26 seconds
Started May 19 01:33:22 PM PDT 24
Finished May 19 01:33:26 PM PDT 24
Peak memory 200504 kb
Host smart-429787d7-8f2d-402b-89d0-6dc1980974fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623356738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.623356738
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1116730940
Short name T251
Test name
Test status
Simulation time 125416437 ps
CPU time 1.13 seconds
Started May 19 01:33:10 PM PDT 24
Finished May 19 01:33:13 PM PDT 24
Peak memory 200528 kb
Host smart-46fc29fd-aed8-4b3a-9ac1-9f7766e14d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116730940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1116730940
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1555998182
Short name T344
Test name
Test status
Simulation time 9760100675 ps
CPU time 35.16 seconds
Started May 19 01:33:08 PM PDT 24
Finished May 19 01:33:46 PM PDT 24
Peak memory 200852 kb
Host smart-268a0539-5e32-422e-b619-d2645e66add9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555998182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1555998182
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3552447614
Short name T268
Test name
Test status
Simulation time 216161607 ps
CPU time 1.46 seconds
Started May 19 01:33:07 PM PDT 24
Finished May 19 01:33:11 PM PDT 24
Peak memory 200404 kb
Host smart-6788e34d-3c4d-41d6-8934-b2226af310a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552447614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3552447614
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2958765628
Short name T472
Test name
Test status
Simulation time 76069430 ps
CPU time 0.83 seconds
Started May 19 01:32:22 PM PDT 24
Finished May 19 01:32:24 PM PDT 24
Peak memory 200180 kb
Host smart-52b051f2-b2a3-4e76-9094-ebfffb6a2b0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958765628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2958765628
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.370008101
Short name T88
Test name
Test status
Simulation time 1228165212 ps
CPU time 5.77 seconds
Started May 19 01:32:28 PM PDT 24
Finished May 19 01:32:36 PM PDT 24
Peak memory 217808 kb
Host smart-0b8f97ef-93b4-45e8-8619-da232d28824e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370008101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.370008101
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3828359535
Short name T534
Test name
Test status
Simulation time 244375770 ps
CPU time 1.09 seconds
Started May 19 01:32:30 PM PDT 24
Finished May 19 01:32:33 PM PDT 24
Peak memory 217508 kb
Host smart-84deb272-c8ae-4085-9b89-8c9f83dcc10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828359535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3828359535
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.4177648210
Short name T494
Test name
Test status
Simulation time 235491731 ps
CPU time 0.95 seconds
Started May 19 01:32:28 PM PDT 24
Finished May 19 01:32:31 PM PDT 24
Peak memory 200288 kb
Host smart-5591eb3b-6f28-4bc7-83cf-dd652133aa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177648210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.4177648210
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.3807210045
Short name T331
Test name
Test status
Simulation time 1586915862 ps
CPU time 6.26 seconds
Started May 19 01:32:20 PM PDT 24
Finished May 19 01:32:27 PM PDT 24
Peak memory 200688 kb
Host smart-228d1fb3-a894-4f7b-a6fd-a5a94d6e95d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807210045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3807210045
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.907786170
Short name T198
Test name
Test status
Simulation time 145404234 ps
CPU time 1.21 seconds
Started May 19 01:32:18 PM PDT 24
Finished May 19 01:32:20 PM PDT 24
Peak memory 200440 kb
Host smart-f5927adc-f38d-471b-97e8-99d5e3a534b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907786170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.907786170
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3185017008
Short name T212
Test name
Test status
Simulation time 203657014 ps
CPU time 1.33 seconds
Started May 19 01:32:23 PM PDT 24
Finished May 19 01:32:26 PM PDT 24
Peak memory 200880 kb
Host smart-04512926-f8e5-4c66-96cb-40e6b63b02ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185017008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3185017008
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3234510822
Short name T196
Test name
Test status
Simulation time 479195323 ps
CPU time 2.38 seconds
Started May 19 01:32:22 PM PDT 24
Finished May 19 01:32:26 PM PDT 24
Peak memory 200652 kb
Host smart-1704acbc-4d8f-4f18-9258-a772161a1770
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234510822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3234510822
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1744488309
Short name T499
Test name
Test status
Simulation time 537583442 ps
CPU time 2.83 seconds
Started May 19 01:32:22 PM PDT 24
Finished May 19 01:32:27 PM PDT 24
Peak memory 200688 kb
Host smart-7a7c534e-7f15-4eb3-a6e5-fee8912cba34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744488309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1744488309
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1477279044
Short name T285
Test name
Test status
Simulation time 138070162 ps
CPU time 1.15 seconds
Started May 19 01:32:29 PM PDT 24
Finished May 19 01:32:32 PM PDT 24
Peak memory 200700 kb
Host smart-2fab5183-62ef-441d-a099-0188a5d03651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477279044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1477279044
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2461757455
Short name T293
Test name
Test status
Simulation time 67994177 ps
CPU time 0.74 seconds
Started May 19 01:33:17 PM PDT 24
Finished May 19 01:33:19 PM PDT 24
Peak memory 200284 kb
Host smart-ccbde5b9-dab9-4732-b23c-531679ee9ab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461757455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2461757455
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2337448299
Short name T37
Test name
Test status
Simulation time 2364838555 ps
CPU time 8.28 seconds
Started May 19 01:33:24 PM PDT 24
Finished May 19 01:33:36 PM PDT 24
Peak memory 218276 kb
Host smart-10c5f5d1-8861-4566-ab9c-b560dcb86e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337448299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2337448299
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2239841566
Short name T447
Test name
Test status
Simulation time 244992715 ps
CPU time 1.14 seconds
Started May 19 01:33:17 PM PDT 24
Finished May 19 01:33:19 PM PDT 24
Peak memory 217712 kb
Host smart-ed13fa48-2505-4f3b-8ec7-db43fb2b01d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239841566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2239841566
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3288268944
Short name T21
Test name
Test status
Simulation time 195359889 ps
CPU time 0.94 seconds
Started May 19 01:33:21 PM PDT 24
Finished May 19 01:33:25 PM PDT 24
Peak memory 200268 kb
Host smart-71ead156-d384-484a-bb99-4bca686d4a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288268944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3288268944
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.415167886
Short name T1
Test name
Test status
Simulation time 1680552054 ps
CPU time 6.59 seconds
Started May 19 01:33:08 PM PDT 24
Finished May 19 01:33:17 PM PDT 24
Peak memory 200696 kb
Host smart-446e80f6-be31-4dfa-8919-fab51995e2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415167886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.415167886
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2922410741
Short name T158
Test name
Test status
Simulation time 183858335 ps
CPU time 1.19 seconds
Started May 19 01:33:13 PM PDT 24
Finished May 19 01:33:15 PM PDT 24
Peak memory 200384 kb
Host smart-1ad9798f-79cd-4373-b66f-efd68a134fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922410741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2922410741
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2950366608
Short name T141
Test name
Test status
Simulation time 222706358 ps
CPU time 1.46 seconds
Started May 19 01:33:09 PM PDT 24
Finished May 19 01:33:13 PM PDT 24
Peak memory 200692 kb
Host smart-6984edf8-4470-4449-8f09-80eb2ea0abe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950366608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2950366608
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2777616555
Short name T105
Test name
Test status
Simulation time 2447304226 ps
CPU time 11.55 seconds
Started May 19 01:33:27 PM PDT 24
Finished May 19 01:33:42 PM PDT 24
Peak memory 200744 kb
Host smart-3eb4c3f4-8904-4b8e-8711-2c9d66557db2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777616555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2777616555
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.3161685960
Short name T142
Test name
Test status
Simulation time 484208824 ps
CPU time 2.56 seconds
Started May 19 01:33:23 PM PDT 24
Finished May 19 01:33:29 PM PDT 24
Peak memory 208620 kb
Host smart-35c73a64-b019-4a43-9471-2f925f4d2eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161685960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3161685960
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3528815668
Short name T455
Test name
Test status
Simulation time 169939749 ps
CPU time 1.09 seconds
Started May 19 01:33:23 PM PDT 24
Finished May 19 01:33:27 PM PDT 24
Peak memory 200412 kb
Host smart-fd4114dd-c624-4eda-969b-9bd182341e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528815668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3528815668
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1793739155
Short name T315
Test name
Test status
Simulation time 74981608 ps
CPU time 0.78 seconds
Started May 19 01:33:26 PM PDT 24
Finished May 19 01:33:31 PM PDT 24
Peak memory 200304 kb
Host smart-bd58388d-4434-4ef8-9bef-e79d34ba90fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793739155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1793739155
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.146385440
Short name T361
Test name
Test status
Simulation time 244324317 ps
CPU time 1.07 seconds
Started May 19 01:33:25 PM PDT 24
Finished May 19 01:33:30 PM PDT 24
Peak memory 217496 kb
Host smart-0368f3fc-5cf4-4f8a-bbfe-2b35ce5f6d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146385440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.146385440
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1133372163
Short name T368
Test name
Test status
Simulation time 76696688 ps
CPU time 0.75 seconds
Started May 19 01:33:24 PM PDT 24
Finished May 19 01:33:29 PM PDT 24
Peak memory 200280 kb
Host smart-78e6ec26-ab18-4b57-99e3-0c65d8f03e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133372163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1133372163
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.101993497
Short name T521
Test name
Test status
Simulation time 1292367397 ps
CPU time 5.28 seconds
Started May 19 01:33:25 PM PDT 24
Finished May 19 01:33:34 PM PDT 24
Peak memory 200628 kb
Host smart-6a70cce5-a89c-49d9-9ced-b29e6a623475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101993497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.101993497
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2371052905
Short name T537
Test name
Test status
Simulation time 105373707 ps
CPU time 1.01 seconds
Started May 19 01:33:11 PM PDT 24
Finished May 19 01:33:14 PM PDT 24
Peak memory 200464 kb
Host smart-03a9cb90-cf79-419b-9211-9f84c4f6f14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371052905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2371052905
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1612706268
Short name T67
Test name
Test status
Simulation time 243273280 ps
CPU time 1.65 seconds
Started May 19 01:33:25 PM PDT 24
Finished May 19 01:33:31 PM PDT 24
Peak memory 200684 kb
Host smart-61e1de38-e2d7-45e4-b6ba-86fe1fce4ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612706268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1612706268
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.41084843
Short name T132
Test name
Test status
Simulation time 12700750877 ps
CPU time 45.78 seconds
Started May 19 01:33:13 PM PDT 24
Finished May 19 01:34:00 PM PDT 24
Peak memory 209000 kb
Host smart-cccda52c-1f69-4f5a-8c9f-8eb315fe08ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41084843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.41084843
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.534148752
Short name T169
Test name
Test status
Simulation time 381202969 ps
CPU time 2.36 seconds
Started May 19 01:33:18 PM PDT 24
Finished May 19 01:33:22 PM PDT 24
Peak memory 200444 kb
Host smart-1e585cb3-af97-436a-8c2c-98aefa588c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534148752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.534148752
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.855817646
Short name T29
Test name
Test status
Simulation time 77366566 ps
CPU time 0.79 seconds
Started May 19 01:33:11 PM PDT 24
Finished May 19 01:33:14 PM PDT 24
Peak memory 200408 kb
Host smart-a3d2a29c-3237-4f31-a628-9bc05bd4101f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855817646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.855817646
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3686781557
Short name T178
Test name
Test status
Simulation time 63538770 ps
CPU time 0.71 seconds
Started May 19 01:33:17 PM PDT 24
Finished May 19 01:33:19 PM PDT 24
Peak memory 200284 kb
Host smart-a92e0eef-0517-4c51-a54b-957d9c46417d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686781557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3686781557
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2589380101
Short name T43
Test name
Test status
Simulation time 1220157685 ps
CPU time 6.25 seconds
Started May 19 01:33:17 PM PDT 24
Finished May 19 01:33:24 PM PDT 24
Peak memory 218084 kb
Host smart-4605b546-402c-42d8-a2a2-49d3b0054d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589380101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2589380101
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.3586992357
Short name T319
Test name
Test status
Simulation time 246113618 ps
CPU time 1.09 seconds
Started May 19 01:33:20 PM PDT 24
Finished May 19 01:33:22 PM PDT 24
Peak memory 217488 kb
Host smart-343072f5-7e61-45f9-b350-d7a350702523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586992357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.3586992357
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.438053953
Short name T26
Test name
Test status
Simulation time 131868408 ps
CPU time 0.81 seconds
Started May 19 01:33:23 PM PDT 24
Finished May 19 01:33:28 PM PDT 24
Peak memory 200284 kb
Host smart-20bfa4eb-9539-44a4-ad18-48da2d95fcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438053953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.438053953
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.2844246764
Short name T156
Test name
Test status
Simulation time 667993701 ps
CPU time 3.95 seconds
Started May 19 01:33:15 PM PDT 24
Finished May 19 01:33:19 PM PDT 24
Peak memory 200676 kb
Host smart-c7e073ab-7a03-4f58-bcfe-4677a771d5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844246764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2844246764
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1665846644
Short name T402
Test name
Test status
Simulation time 184192918 ps
CPU time 1.18 seconds
Started May 19 01:33:19 PM PDT 24
Finished May 19 01:33:21 PM PDT 24
Peak memory 200424 kb
Host smart-c5d752eb-9a92-4187-8671-82c8e442205f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665846644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1665846644
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3004661795
Short name T371
Test name
Test status
Simulation time 253577632 ps
CPU time 1.42 seconds
Started May 19 01:33:26 PM PDT 24
Finished May 19 01:33:31 PM PDT 24
Peak memory 200628 kb
Host smart-3160f607-40f7-4341-a284-a90b32258be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004661795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3004661795
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1309438055
Short name T243
Test name
Test status
Simulation time 6944544658 ps
CPU time 29.71 seconds
Started May 19 01:33:21 PM PDT 24
Finished May 19 01:33:52 PM PDT 24
Peak memory 200776 kb
Host smart-1ad03b1a-10dc-46ea-a3c1-d1f7af3da9d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309438055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1309438055
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3148041205
Short name T342
Test name
Test status
Simulation time 127579400 ps
CPU time 1.68 seconds
Started May 19 01:33:20 PM PDT 24
Finished May 19 01:33:23 PM PDT 24
Peak memory 208612 kb
Host smart-bf6b4b53-3a10-459d-94b2-96099f2594b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148041205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3148041205
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1314986941
Short name T353
Test name
Test status
Simulation time 260070844 ps
CPU time 1.5 seconds
Started May 19 01:33:19 PM PDT 24
Finished May 19 01:33:22 PM PDT 24
Peak memory 200448 kb
Host smart-7fa3b3c9-cec7-4082-b424-2733201d3ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314986941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1314986941
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2387064590
Short name T266
Test name
Test status
Simulation time 90248951 ps
CPU time 0.83 seconds
Started May 19 01:33:17 PM PDT 24
Finished May 19 01:33:19 PM PDT 24
Peak memory 200300 kb
Host smart-056fbb09-30b2-47ce-a801-3e0589332e73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387064590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2387064590
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2544366153
Short name T52
Test name
Test status
Simulation time 1228378810 ps
CPU time 6.11 seconds
Started May 19 01:33:13 PM PDT 24
Finished May 19 01:33:20 PM PDT 24
Peak memory 218068 kb
Host smart-134044d2-a17c-46d4-a23a-0e6e0d782b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544366153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2544366153
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.578284829
Short name T194
Test name
Test status
Simulation time 244573995 ps
CPU time 1.19 seconds
Started May 19 01:33:12 PM PDT 24
Finished May 19 01:33:15 PM PDT 24
Peak memory 217560 kb
Host smart-323fd3bb-5d14-4eac-9f91-ca070b8d53e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578284829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.578284829
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2684158216
Short name T23
Test name
Test status
Simulation time 138865845 ps
CPU time 0.8 seconds
Started May 19 01:33:25 PM PDT 24
Finished May 19 01:33:30 PM PDT 24
Peak memory 200264 kb
Host smart-5b4d1cc1-c248-4f95-9c02-f6fcd8431946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684158216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2684158216
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1550513553
Short name T496
Test name
Test status
Simulation time 948667102 ps
CPU time 5.35 seconds
Started May 19 01:33:14 PM PDT 24
Finished May 19 01:33:21 PM PDT 24
Peak memory 200620 kb
Host smart-75ec4104-dd5f-46a3-82a0-d08d03ce7427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550513553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1550513553
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3283129934
Short name T274
Test name
Test status
Simulation time 182831655 ps
CPU time 1.29 seconds
Started May 19 01:33:23 PM PDT 24
Finished May 19 01:33:28 PM PDT 24
Peak memory 200728 kb
Host smart-198b2c4d-a413-4a58-b436-4d2289442cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283129934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3283129934
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2390028042
Short name T250
Test name
Test status
Simulation time 239954601 ps
CPU time 1.58 seconds
Started May 19 01:33:19 PM PDT 24
Finished May 19 01:33:22 PM PDT 24
Peak memory 200652 kb
Host smart-93e443c6-c933-4831-a5f3-a041bbde1b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390028042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2390028042
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.2463508163
Short name T417
Test name
Test status
Simulation time 6203748204 ps
CPU time 21.29 seconds
Started May 19 01:33:15 PM PDT 24
Finished May 19 01:33:37 PM PDT 24
Peak memory 208992 kb
Host smart-e2453107-2a49-4d96-bc2f-9b2264dba617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463508163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2463508163
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3624290020
Short name T350
Test name
Test status
Simulation time 151873487 ps
CPU time 1.97 seconds
Started May 19 01:33:17 PM PDT 24
Finished May 19 01:33:20 PM PDT 24
Peak memory 200456 kb
Host smart-92253402-b4bf-45d4-ae74-0dad40d1261d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624290020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3624290020
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.4291563742
Short name T191
Test name
Test status
Simulation time 247286242 ps
CPU time 1.45 seconds
Started May 19 01:33:16 PM PDT 24
Finished May 19 01:33:18 PM PDT 24
Peak memory 200580 kb
Host smart-b8a47013-df2e-4aa5-9033-b84913cc320b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291563742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.4291563742
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3789600758
Short name T381
Test name
Test status
Simulation time 86742016 ps
CPU time 0.83 seconds
Started May 19 01:33:18 PM PDT 24
Finished May 19 01:33:20 PM PDT 24
Peak memory 200264 kb
Host smart-6501f826-7728-4097-846f-ae3ce857a053
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789600758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3789600758
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2233988283
Short name T391
Test name
Test status
Simulation time 2353850006 ps
CPU time 8.2 seconds
Started May 19 01:33:18 PM PDT 24
Finished May 19 01:33:27 PM PDT 24
Peak memory 222036 kb
Host smart-0382462f-e42c-422d-ab59-db13282f8437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233988283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2233988283
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.415373327
Short name T187
Test name
Test status
Simulation time 244909621 ps
CPU time 1.05 seconds
Started May 19 01:33:16 PM PDT 24
Finished May 19 01:33:18 PM PDT 24
Peak memory 217640 kb
Host smart-8bb313d4-ce40-4619-b3df-989b684808f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415373327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.415373327
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2445365783
Short name T300
Test name
Test status
Simulation time 183983828 ps
CPU time 0.88 seconds
Started May 19 01:33:23 PM PDT 24
Finished May 19 01:33:27 PM PDT 24
Peak memory 200276 kb
Host smart-d0698635-266d-4fbb-bd85-669dc8f3c99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445365783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2445365783
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3197605733
Short name T110
Test name
Test status
Simulation time 970504545 ps
CPU time 4.66 seconds
Started May 19 01:33:25 PM PDT 24
Finished May 19 01:33:34 PM PDT 24
Peak memory 200652 kb
Host smart-535e1c8f-806d-486f-836a-d66b3f364f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197605733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3197605733
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.387293558
Short name T486
Test name
Test status
Simulation time 104614631 ps
CPU time 0.99 seconds
Started May 19 01:33:22 PM PDT 24
Finished May 19 01:33:35 PM PDT 24
Peak memory 200724 kb
Host smart-26e34e4e-1862-4dfe-87e1-0b30475fd79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387293558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.387293558
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1683675583
Short name T284
Test name
Test status
Simulation time 260196294 ps
CPU time 1.5 seconds
Started May 19 01:33:24 PM PDT 24
Finished May 19 01:33:29 PM PDT 24
Peak memory 200632 kb
Host smart-03eba60b-3256-472e-8f84-f49ac400ddc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683675583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1683675583
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.2256296665
Short name T502
Test name
Test status
Simulation time 448625048 ps
CPU time 2.42 seconds
Started May 19 01:33:22 PM PDT 24
Finished May 19 01:33:28 PM PDT 24
Peak memory 200432 kb
Host smart-7d900a5e-c6e6-4db1-a9ba-81a92aca4920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256296665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2256296665
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1185056281
Short name T320
Test name
Test status
Simulation time 169941407 ps
CPU time 1.32 seconds
Started May 19 01:33:15 PM PDT 24
Finished May 19 01:33:17 PM PDT 24
Peak memory 200596 kb
Host smart-c7ebfdb2-8c28-4c22-89ab-04a3df0511a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185056281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1185056281
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.2091857976
Short name T222
Test name
Test status
Simulation time 69023710 ps
CPU time 0.79 seconds
Started May 19 01:33:25 PM PDT 24
Finished May 19 01:33:30 PM PDT 24
Peak memory 200292 kb
Host smart-1d369b22-011f-4c60-bbd6-52061d0f07db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091857976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2091857976
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.399826273
Short name T55
Test name
Test status
Simulation time 2357792329 ps
CPU time 8.41 seconds
Started May 19 01:33:20 PM PDT 24
Finished May 19 01:33:30 PM PDT 24
Peak memory 230532 kb
Host smart-a5564bab-316f-40b1-8578-fe37aad86a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399826273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.399826273
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3130288337
Short name T356
Test name
Test status
Simulation time 245123745 ps
CPU time 1.05 seconds
Started May 19 01:33:19 PM PDT 24
Finished May 19 01:33:22 PM PDT 24
Peak memory 217700 kb
Host smart-700b9f98-8dca-4974-8079-a990d902653c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130288337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3130288337
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.2362428253
Short name T205
Test name
Test status
Simulation time 139525266 ps
CPU time 0.8 seconds
Started May 19 01:33:21 PM PDT 24
Finished May 19 01:33:24 PM PDT 24
Peak memory 200300 kb
Host smart-35910bdc-6e8c-44e3-a8ca-ea08a4f72902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362428253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2362428253
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.221050175
Short name T231
Test name
Test status
Simulation time 992496331 ps
CPU time 4.6 seconds
Started May 19 01:33:16 PM PDT 24
Finished May 19 01:33:22 PM PDT 24
Peak memory 200716 kb
Host smart-b1383cdb-1e23-45e0-a815-aa80735f7044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221050175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.221050175
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.4069263891
Short name T4
Test name
Test status
Simulation time 149691195 ps
CPU time 1.14 seconds
Started May 19 01:33:22 PM PDT 24
Finished May 19 01:33:27 PM PDT 24
Peak memory 200480 kb
Host smart-aa030733-2615-4b7d-a176-fe22215c579f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069263891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.4069263891
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1902198002
Short name T202
Test name
Test status
Simulation time 231375501 ps
CPU time 1.47 seconds
Started May 19 01:33:26 PM PDT 24
Finished May 19 01:33:32 PM PDT 24
Peak memory 200620 kb
Host smart-79d3104c-7b9c-4563-9e65-d716ca522ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902198002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1902198002
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1096716760
Short name T330
Test name
Test status
Simulation time 4043106478 ps
CPU time 15.46 seconds
Started May 19 01:33:21 PM PDT 24
Finished May 19 01:33:38 PM PDT 24
Peak memory 209000 kb
Host smart-52d7bc60-9d30-4006-9704-1eb7d8fd1d02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096716760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1096716760
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1105555706
Short name T425
Test name
Test status
Simulation time 337283535 ps
CPU time 2.22 seconds
Started May 19 01:33:23 PM PDT 24
Finished May 19 01:33:29 PM PDT 24
Peak memory 200444 kb
Host smart-8ead3d73-8693-4165-a1d7-8dad37888722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105555706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1105555706
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1220095221
Short name T219
Test name
Test status
Simulation time 181662559 ps
CPU time 1.37 seconds
Started May 19 01:33:25 PM PDT 24
Finished May 19 01:33:30 PM PDT 24
Peak memory 200644 kb
Host smart-6edf0ca6-b055-4a5f-b487-f4590168f58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220095221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1220095221
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2075167997
Short name T495
Test name
Test status
Simulation time 69363341 ps
CPU time 0.77 seconds
Started May 19 01:33:23 PM PDT 24
Finished May 19 01:33:27 PM PDT 24
Peak memory 200264 kb
Host smart-120ec5e1-f14f-45d2-98e5-ae318c8a6447
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075167997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2075167997
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3151660544
Short name T427
Test name
Test status
Simulation time 1918430820 ps
CPU time 7.09 seconds
Started May 19 01:33:23 PM PDT 24
Finished May 19 01:33:33 PM PDT 24
Peak memory 218080 kb
Host smart-533b3b8b-7455-49ac-9f3f-a92dbac5717d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151660544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3151660544
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1426077451
Short name T5
Test name
Test status
Simulation time 244241476 ps
CPU time 1.05 seconds
Started May 19 01:33:19 PM PDT 24
Finished May 19 01:33:21 PM PDT 24
Peak memory 217620 kb
Host smart-afdca8da-f85d-4273-83aa-c21c193f1972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426077451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1426077451
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.4183628719
Short name T18
Test name
Test status
Simulation time 79818837 ps
CPU time 0.74 seconds
Started May 19 01:33:17 PM PDT 24
Finished May 19 01:33:18 PM PDT 24
Peak memory 200296 kb
Host smart-1d696854-541f-4aca-8129-94de178c1580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183628719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.4183628719
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2446655760
Short name T12
Test name
Test status
Simulation time 913045642 ps
CPU time 4.54 seconds
Started May 19 01:33:24 PM PDT 24
Finished May 19 01:33:33 PM PDT 24
Peak memory 200632 kb
Host smart-75fa5a0b-06c3-4117-b303-a260f4545544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446655760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2446655760
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.99850571
Short name T216
Test name
Test status
Simulation time 147120997 ps
CPU time 1.14 seconds
Started May 19 01:33:27 PM PDT 24
Finished May 19 01:33:32 PM PDT 24
Peak memory 200444 kb
Host smart-0d7ab8c2-27d1-413e-979c-7a0cc036eb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99850571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.99850571
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1947618044
Short name T245
Test name
Test status
Simulation time 116064027 ps
CPU time 1.18 seconds
Started May 19 01:33:27 PM PDT 24
Finished May 19 01:33:32 PM PDT 24
Peak memory 200640 kb
Host smart-892af769-c6cd-4cd7-aaac-fb2e6c951549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947618044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1947618044
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.4174437454
Short name T322
Test name
Test status
Simulation time 160874049 ps
CPU time 1.19 seconds
Started May 19 01:33:23 PM PDT 24
Finished May 19 01:33:28 PM PDT 24
Peak memory 200476 kb
Host smart-75d48ce1-92e3-4f6c-a319-a61f09bfaf81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174437454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.4174437454
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.566843431
Short name T264
Test name
Test status
Simulation time 367323309 ps
CPU time 2.06 seconds
Started May 19 01:33:20 PM PDT 24
Finished May 19 01:33:24 PM PDT 24
Peak memory 200496 kb
Host smart-6c245570-7be9-42f3-bde8-474338748ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566843431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.566843431
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.1931016967
Short name T176
Test name
Test status
Simulation time 87278860 ps
CPU time 0.84 seconds
Started May 19 01:33:24 PM PDT 24
Finished May 19 01:33:29 PM PDT 24
Peak memory 200476 kb
Host smart-e6bb1f82-ce0d-4d46-a586-12a404981dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931016967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1931016967
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3696914528
Short name T34
Test name
Test status
Simulation time 70119437 ps
CPU time 0.77 seconds
Started May 19 01:33:25 PM PDT 24
Finished May 19 01:33:30 PM PDT 24
Peak memory 200252 kb
Host smart-293aff94-dd5b-4858-9239-404e69517abf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696914528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3696914528
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2129652624
Short name T446
Test name
Test status
Simulation time 1883469043 ps
CPU time 7.46 seconds
Started May 19 01:33:25 PM PDT 24
Finished May 19 01:33:36 PM PDT 24
Peak memory 218124 kb
Host smart-ebd50337-5289-4089-ba66-9a7c014e4394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129652624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2129652624
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.4011449391
Short name T491
Test name
Test status
Simulation time 244617384 ps
CPU time 1.14 seconds
Started May 19 01:33:19 PM PDT 24
Finished May 19 01:33:21 PM PDT 24
Peak memory 217572 kb
Host smart-0d1bcedb-e8a2-452c-b18f-76e9660f00e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011449391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.4011449391
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.732396156
Short name T206
Test name
Test status
Simulation time 160747396 ps
CPU time 0.84 seconds
Started May 19 01:33:23 PM PDT 24
Finished May 19 01:33:27 PM PDT 24
Peak memory 200264 kb
Host smart-4616321d-1795-44f0-bc4d-ed31a77d43c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732396156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.732396156
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2787436276
Short name T497
Test name
Test status
Simulation time 1112089180 ps
CPU time 5.03 seconds
Started May 19 01:33:24 PM PDT 24
Finished May 19 01:33:33 PM PDT 24
Peak memory 200656 kb
Host smart-4ddafc4d-f9bc-42fb-9b14-96799da735c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787436276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2787436276
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1289177514
Short name T255
Test name
Test status
Simulation time 154942186 ps
CPU time 1.11 seconds
Started May 19 01:33:24 PM PDT 24
Finished May 19 01:33:29 PM PDT 24
Peak memory 200436 kb
Host smart-dd30a9a3-e5a4-4dee-9310-1741dcca1d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289177514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1289177514
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.515341492
Short name T213
Test name
Test status
Simulation time 117332892 ps
CPU time 1.16 seconds
Started May 19 01:33:19 PM PDT 24
Finished May 19 01:33:21 PM PDT 24
Peak memory 200564 kb
Host smart-2fde12d5-83b9-4e6b-9158-504c80abaf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515341492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.515341492
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1265265142
Short name T340
Test name
Test status
Simulation time 5525026305 ps
CPU time 27.27 seconds
Started May 19 01:33:28 PM PDT 24
Finished May 19 01:33:58 PM PDT 24
Peak memory 200720 kb
Host smart-f0ab3663-f1e3-47c2-871e-aafa289697d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265265142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1265265142
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.621887261
Short name T46
Test name
Test status
Simulation time 279699053 ps
CPU time 2.05 seconds
Started May 19 01:33:23 PM PDT 24
Finished May 19 01:33:29 PM PDT 24
Peak memory 200424 kb
Host smart-85cf6ba3-cb29-47df-8e4a-77eb3ef6385a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621887261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.621887261
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1327330403
Short name T413
Test name
Test status
Simulation time 161820644 ps
CPU time 1.29 seconds
Started May 19 01:33:21 PM PDT 24
Finished May 19 01:33:25 PM PDT 24
Peak memory 200608 kb
Host smart-15e67836-18f2-4418-a297-5237fdd8d66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327330403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1327330403
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.566558147
Short name T470
Test name
Test status
Simulation time 66771983 ps
CPU time 0.74 seconds
Started May 19 01:33:24 PM PDT 24
Finished May 19 01:33:29 PM PDT 24
Peak memory 200280 kb
Host smart-a0192258-8be8-46a5-8ae7-843c2d0c47f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566558147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.566558147
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1962727650
Short name T42
Test name
Test status
Simulation time 2386213689 ps
CPU time 8.07 seconds
Started May 19 01:33:27 PM PDT 24
Finished May 19 01:33:39 PM PDT 24
Peak memory 218208 kb
Host smart-4d7c1a57-ee6b-4947-94d2-c553561c4805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962727650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1962727650
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3198815092
Short name T466
Test name
Test status
Simulation time 244333372 ps
CPU time 1.14 seconds
Started May 19 01:33:26 PM PDT 24
Finished May 19 01:33:31 PM PDT 24
Peak memory 217656 kb
Host smart-7af1ac03-4c89-4fd7-856d-8fe087e944f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198815092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3198815092
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.366769824
Short name T379
Test name
Test status
Simulation time 184789074 ps
CPU time 0.85 seconds
Started May 19 01:33:19 PM PDT 24
Finished May 19 01:33:21 PM PDT 24
Peak memory 200232 kb
Host smart-83141d4a-5c65-43dc-8fdf-74dfccf3d6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366769824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.366769824
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.2634957333
Short name T373
Test name
Test status
Simulation time 776742474 ps
CPU time 4.17 seconds
Started May 19 01:33:25 PM PDT 24
Finished May 19 01:33:33 PM PDT 24
Peak memory 200660 kb
Host smart-2d4a6b77-adcd-473e-be2b-a7b77377ecbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634957333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2634957333
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.425823282
Short name T185
Test name
Test status
Simulation time 149441067 ps
CPU time 1.1 seconds
Started May 19 01:33:22 PM PDT 24
Finished May 19 01:33:25 PM PDT 24
Peak memory 200516 kb
Host smart-283e9d33-3c69-42e9-9c7a-df801bbe371d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425823282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.425823282
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3743474406
Short name T229
Test name
Test status
Simulation time 124791441 ps
CPU time 1.23 seconds
Started May 19 01:33:21 PM PDT 24
Finished May 19 01:33:24 PM PDT 24
Peak memory 200672 kb
Host smart-e7d22692-2a01-4a5a-850c-6e941fb268a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743474406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3743474406
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2079501054
Short name T364
Test name
Test status
Simulation time 5760544247 ps
CPU time 28.31 seconds
Started May 19 01:33:19 PM PDT 24
Finished May 19 01:33:48 PM PDT 24
Peak memory 200704 kb
Host smart-2c37f407-8d32-49a4-b29b-cdd3abf6fa15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079501054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2079501054
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.309560113
Short name T500
Test name
Test status
Simulation time 523749545 ps
CPU time 2.79 seconds
Started May 19 01:33:32 PM PDT 24
Finished May 19 01:33:38 PM PDT 24
Peak memory 200420 kb
Host smart-480c14eb-f5d1-4c6c-b366-ae61be4f14a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309560113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.309560113
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.632667067
Short name T380
Test name
Test status
Simulation time 144275724 ps
CPU time 0.99 seconds
Started May 19 01:33:26 PM PDT 24
Finished May 19 01:33:31 PM PDT 24
Peak memory 200412 kb
Host smart-c1d00be2-f3f0-4391-8652-2e0f45af7463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632667067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.632667067
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.537448004
Short name T48
Test name
Test status
Simulation time 84703696 ps
CPU time 0.91 seconds
Started May 19 01:33:28 PM PDT 24
Finished May 19 01:33:33 PM PDT 24
Peak memory 200316 kb
Host smart-0caea67b-d8e1-4d9c-a151-dd5fce569841
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537448004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.537448004
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1677278535
Short name T516
Test name
Test status
Simulation time 2364427957 ps
CPU time 8.09 seconds
Started May 19 01:33:54 PM PDT 24
Finished May 19 01:34:03 PM PDT 24
Peak memory 217848 kb
Host smart-72b88507-cf0d-45f5-9a37-65fb2f5a5737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677278535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1677278535
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1333536099
Short name T237
Test name
Test status
Simulation time 244833786 ps
CPU time 1.03 seconds
Started May 19 01:33:26 PM PDT 24
Finished May 19 01:33:31 PM PDT 24
Peak memory 217536 kb
Host smart-bfc5c78b-2b33-4420-9aff-7883fa2fcd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333536099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1333536099
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.3847046652
Short name T25
Test name
Test status
Simulation time 198374017 ps
CPU time 0.87 seconds
Started May 19 01:33:21 PM PDT 24
Finished May 19 01:33:23 PM PDT 24
Peak memory 200460 kb
Host smart-44a7e53e-387a-47b6-a5e2-b5056c1b0818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847046652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3847046652
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.4063332863
Short name T487
Test name
Test status
Simulation time 1687053106 ps
CPU time 6.78 seconds
Started May 19 01:33:23 PM PDT 24
Finished May 19 01:33:34 PM PDT 24
Peak memory 200600 kb
Host smart-1f883f83-3782-47b6-87f3-a18e4cd08b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063332863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.4063332863
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2655824419
Short name T324
Test name
Test status
Simulation time 142356936 ps
CPU time 1.2 seconds
Started May 19 01:33:27 PM PDT 24
Finished May 19 01:33:32 PM PDT 24
Peak memory 200480 kb
Host smart-f02c4428-4285-42ab-a4c4-865a5a4ad701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655824419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2655824419
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2036845089
Short name T298
Test name
Test status
Simulation time 193666543 ps
CPU time 1.44 seconds
Started May 19 01:33:20 PM PDT 24
Finished May 19 01:33:23 PM PDT 24
Peak memory 200692 kb
Host smart-69c53139-a284-4bf8-9fca-9f879eb6f3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036845089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2036845089
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3718021033
Short name T325
Test name
Test status
Simulation time 9626779499 ps
CPU time 36.39 seconds
Started May 19 01:33:26 PM PDT 24
Finished May 19 01:34:06 PM PDT 24
Peak memory 200964 kb
Host smart-fbbfa45a-254c-4258-b8ed-e403007ec058
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718021033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3718021033
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.1765130843
Short name T510
Test name
Test status
Simulation time 146980669 ps
CPU time 1.86 seconds
Started May 19 01:33:28 PM PDT 24
Finished May 19 01:33:33 PM PDT 24
Peak memory 200444 kb
Host smart-e096de9c-5f00-432a-93e1-51d3ed6ebd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765130843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1765130843
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.304266101
Short name T531
Test name
Test status
Simulation time 98373438 ps
CPU time 0.93 seconds
Started May 19 01:33:21 PM PDT 24
Finished May 19 01:33:24 PM PDT 24
Peak memory 200484 kb
Host smart-3637d5cc-c457-4bf2-afe3-0d285c73460c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304266101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.304266101
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2712506098
Short name T433
Test name
Test status
Simulation time 58700466 ps
CPU time 0.73 seconds
Started May 19 01:32:25 PM PDT 24
Finished May 19 01:32:28 PM PDT 24
Peak memory 200296 kb
Host smart-4c98cb94-c653-4a58-9b44-2f3413a8d1f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712506098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2712506098
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.109665873
Short name T58
Test name
Test status
Simulation time 1881079640 ps
CPU time 7.38 seconds
Started May 19 01:32:21 PM PDT 24
Finished May 19 01:32:29 PM PDT 24
Peak memory 218068 kb
Host smart-0b26685e-906f-4349-9afb-cff3f67adeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109665873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.109665873
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2614907141
Short name T299
Test name
Test status
Simulation time 244330934 ps
CPU time 1.1 seconds
Started May 19 01:32:29 PM PDT 24
Finished May 19 01:32:33 PM PDT 24
Peak memory 217504 kb
Host smart-91b3a65e-c464-481d-beba-f983a8fa73a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614907141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2614907141
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.2677321487
Short name T523
Test name
Test status
Simulation time 188031687 ps
CPU time 0.88 seconds
Started May 19 01:32:30 PM PDT 24
Finished May 19 01:32:33 PM PDT 24
Peak memory 200280 kb
Host smart-4695321c-a1f4-41cc-91df-dabbae308e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677321487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2677321487
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1766102556
Short name T47
Test name
Test status
Simulation time 879962086 ps
CPU time 4.61 seconds
Started May 19 01:32:40 PM PDT 24
Finished May 19 01:32:46 PM PDT 24
Peak memory 200524 kb
Host smart-449670a8-6ad5-4dee-9b43-bd04eba8b033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766102556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1766102556
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.589727734
Short name T514
Test name
Test status
Simulation time 106110961 ps
CPU time 1.15 seconds
Started May 19 01:32:30 PM PDT 24
Finished May 19 01:32:33 PM PDT 24
Peak memory 200436 kb
Host smart-c4082138-ceee-45bd-963f-ede74a03a8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589727734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.589727734
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3568841394
Short name T192
Test name
Test status
Simulation time 204663119 ps
CPU time 1.49 seconds
Started May 19 01:32:27 PM PDT 24
Finished May 19 01:32:31 PM PDT 24
Peak memory 200652 kb
Host smart-a52d2fe6-0605-4d26-8014-a756186caba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568841394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3568841394
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.4040854022
Short name T226
Test name
Test status
Simulation time 485701437 ps
CPU time 2.56 seconds
Started May 19 01:32:32 PM PDT 24
Finished May 19 01:32:37 PM PDT 24
Peak memory 200440 kb
Host smart-18037e81-d127-46fd-90b0-1d39104b370d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040854022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.4040854022
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2191606070
Short name T177
Test name
Test status
Simulation time 62696407 ps
CPU time 0.77 seconds
Started May 19 01:32:25 PM PDT 24
Finished May 19 01:32:28 PM PDT 24
Peak memory 200476 kb
Host smart-30f774b8-bff6-407b-a8ba-a87235986265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191606070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2191606070
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.478856243
Short name T233
Test name
Test status
Simulation time 71563965 ps
CPU time 0.78 seconds
Started May 19 01:32:35 PM PDT 24
Finished May 19 01:32:38 PM PDT 24
Peak memory 200212 kb
Host smart-c623a1d9-7ea4-476e-ac6f-2a9542560dc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478856243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.478856243
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2099556020
Short name T445
Test name
Test status
Simulation time 1238123545 ps
CPU time 5.48 seconds
Started May 19 01:32:29 PM PDT 24
Finished May 19 01:32:37 PM PDT 24
Peak memory 218076 kb
Host smart-57360726-c0fd-4b4d-b441-4af21a233589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099556020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2099556020
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.531619192
Short name T137
Test name
Test status
Simulation time 244741195 ps
CPU time 1.06 seconds
Started May 19 01:32:31 PM PDT 24
Finished May 19 01:32:35 PM PDT 24
Peak memory 217720 kb
Host smart-da6ef3bb-29d2-41d4-ad69-eade26f12641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531619192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.531619192
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1755948265
Short name T220
Test name
Test status
Simulation time 118701321 ps
CPU time 0.84 seconds
Started May 19 01:32:28 PM PDT 24
Finished May 19 01:32:30 PM PDT 24
Peak memory 200264 kb
Host smart-904b9b27-0985-4a43-bc26-878685c1849b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755948265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1755948265
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3952865022
Short name T345
Test name
Test status
Simulation time 1076822762 ps
CPU time 5.69 seconds
Started May 19 01:32:30 PM PDT 24
Finished May 19 01:32:38 PM PDT 24
Peak memory 200636 kb
Host smart-6637d6f8-1256-4b84-afb8-19b2ce096ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952865022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3952865022
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.4151153368
Short name T272
Test name
Test status
Simulation time 98578914 ps
CPU time 0.99 seconds
Started May 19 01:32:32 PM PDT 24
Finished May 19 01:32:36 PM PDT 24
Peak memory 200344 kb
Host smart-cfb80c8b-3b91-4370-a6aa-814f752ef447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151153368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.4151153368
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2296300539
Short name T62
Test name
Test status
Simulation time 113741260 ps
CPU time 1.22 seconds
Started May 19 01:32:28 PM PDT 24
Finished May 19 01:32:32 PM PDT 24
Peak memory 200652 kb
Host smart-c3fbaf93-6f40-4062-9cbb-860e407500a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296300539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2296300539
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.191168400
Short name T249
Test name
Test status
Simulation time 5785326386 ps
CPU time 27.55 seconds
Started May 19 01:32:28 PM PDT 24
Finished May 19 01:32:57 PM PDT 24
Peak memory 210812 kb
Host smart-d0f7dd0b-122c-46c4-a972-dbd1a67e74f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191168400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.191168400
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.2666144939
Short name T538
Test name
Test status
Simulation time 510697207 ps
CPU time 3.05 seconds
Started May 19 01:32:19 PM PDT 24
Finished May 19 01:32:23 PM PDT 24
Peak memory 200416 kb
Host smart-cc780d84-527a-4dd4-b30b-5a7fbefdf3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666144939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2666144939
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.4070681913
Short name T532
Test name
Test status
Simulation time 105119865 ps
CPU time 0.9 seconds
Started May 19 01:32:31 PM PDT 24
Finished May 19 01:32:35 PM PDT 24
Peak memory 200124 kb
Host smart-1c315461-9b3a-4463-844a-ac2a99b850e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070681913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.4070681913
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1773144665
Short name T349
Test name
Test status
Simulation time 67326221 ps
CPU time 0.74 seconds
Started May 19 01:32:37 PM PDT 24
Finished May 19 01:32:40 PM PDT 24
Peak memory 200168 kb
Host smart-9b3faf15-9d46-4a58-9363-747f602e96fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773144665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1773144665
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.525333465
Short name T419
Test name
Test status
Simulation time 1228922806 ps
CPU time 6.18 seconds
Started May 19 01:32:26 PM PDT 24
Finished May 19 01:32:34 PM PDT 24
Peak memory 218108 kb
Host smart-463d99b0-6845-4186-9e11-48b6a0dc0d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525333465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.525333465
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1665691210
Short name T280
Test name
Test status
Simulation time 244242559 ps
CPU time 1.08 seconds
Started May 19 01:32:24 PM PDT 24
Finished May 19 01:32:27 PM PDT 24
Peak memory 217728 kb
Host smart-42571dc9-c0c8-44a1-9614-5792ac9d94b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665691210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1665691210
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1704178481
Short name T512
Test name
Test status
Simulation time 109362248 ps
CPU time 0.81 seconds
Started May 19 01:32:32 PM PDT 24
Finished May 19 01:32:35 PM PDT 24
Peak memory 200276 kb
Host smart-c1bfce08-0717-4f8d-864d-86e801a0e50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704178481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1704178481
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.344793638
Short name T423
Test name
Test status
Simulation time 1146836687 ps
CPU time 4.62 seconds
Started May 19 01:32:22 PM PDT 24
Finished May 19 01:32:28 PM PDT 24
Peak memory 200636 kb
Host smart-e4b44d22-8b80-4a83-abe7-a3b933298140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344793638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.344793638
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1206298844
Short name T296
Test name
Test status
Simulation time 182370195 ps
CPU time 1.26 seconds
Started May 19 01:32:30 PM PDT 24
Finished May 19 01:32:34 PM PDT 24
Peak memory 200504 kb
Host smart-823f0485-eba2-497d-b479-9f670089a517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206298844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1206298844
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2993619409
Short name T346
Test name
Test status
Simulation time 126582332 ps
CPU time 1.2 seconds
Started May 19 01:32:24 PM PDT 24
Finished May 19 01:32:28 PM PDT 24
Peak memory 200652 kb
Host smart-8fc1f6c2-35fd-470e-b79f-2208964193b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993619409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2993619409
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3964434627
Short name T267
Test name
Test status
Simulation time 1676958535 ps
CPU time 7.93 seconds
Started May 19 01:32:31 PM PDT 24
Finished May 19 01:32:41 PM PDT 24
Peak memory 208712 kb
Host smart-21991c0f-12a9-44ed-83a5-ff721a188a16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964434627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3964434627
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.2470391037
Short name T236
Test name
Test status
Simulation time 111314227 ps
CPU time 1.41 seconds
Started May 19 01:32:37 PM PDT 24
Finished May 19 01:32:40 PM PDT 24
Peak memory 200328 kb
Host smart-0905341f-0e10-4094-a83e-965ce26a90c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470391037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2470391037
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3796916065
Short name T258
Test name
Test status
Simulation time 151149056 ps
CPU time 1.15 seconds
Started May 19 01:32:23 PM PDT 24
Finished May 19 01:32:26 PM PDT 24
Peak memory 200692 kb
Host smart-c2fc92ef-f2a7-446e-9f87-e7ea64979b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796916065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3796916065
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.547089158
Short name T416
Test name
Test status
Simulation time 53866006 ps
CPU time 0.73 seconds
Started May 19 01:32:29 PM PDT 24
Finished May 19 01:32:32 PM PDT 24
Peak memory 200272 kb
Host smart-6e05c779-46af-44fe-99d4-14d18698af7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547089158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.547089158
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2259100026
Short name T520
Test name
Test status
Simulation time 2166720391 ps
CPU time 7.81 seconds
Started May 19 01:32:26 PM PDT 24
Finished May 19 01:32:36 PM PDT 24
Peak memory 218232 kb
Host smart-26977e19-ac63-4b70-b3b0-3cca4f7e44fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259100026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2259100026
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.965036093
Short name T332
Test name
Test status
Simulation time 244291789 ps
CPU time 1.09 seconds
Started May 19 01:32:24 PM PDT 24
Finished May 19 01:32:27 PM PDT 24
Peak memory 217868 kb
Host smart-18ea6d8c-c1d3-467d-9936-5ded7baab5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965036093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.965036093
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1159260739
Short name T463
Test name
Test status
Simulation time 150522179 ps
CPU time 0.91 seconds
Started May 19 01:32:31 PM PDT 24
Finished May 19 01:32:34 PM PDT 24
Peak memory 200228 kb
Host smart-614346b2-3346-4c37-b12a-81781c1a73b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159260739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1159260739
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2961379890
Short name T303
Test name
Test status
Simulation time 770040262 ps
CPU time 3.95 seconds
Started May 19 01:32:28 PM PDT 24
Finished May 19 01:32:34 PM PDT 24
Peak memory 200616 kb
Host smart-584e18ee-6dad-4c22-9c0f-1a2a2e64f2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961379890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2961379890
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1673655678
Short name T476
Test name
Test status
Simulation time 153106992 ps
CPU time 1.11 seconds
Started May 19 01:32:24 PM PDT 24
Finished May 19 01:32:27 PM PDT 24
Peak memory 200520 kb
Host smart-7ce62e5e-89da-4ac8-a207-86cdaa831ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673655678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1673655678
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2343327599
Short name T289
Test name
Test status
Simulation time 238239498 ps
CPU time 1.47 seconds
Started May 19 01:32:40 PM PDT 24
Finished May 19 01:32:43 PM PDT 24
Peak memory 200520 kb
Host smart-c388e4e9-9bd9-4248-88b0-2cbadf8f1972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343327599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2343327599
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.3718511969
Short name T415
Test name
Test status
Simulation time 4154645993 ps
CPU time 15.83 seconds
Started May 19 01:32:40 PM PDT 24
Finished May 19 01:32:58 PM PDT 24
Peak memory 200820 kb
Host smart-be657982-5e30-4095-8961-891a4d4afd8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718511969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3718511969
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3948601727
Short name T50
Test name
Test status
Simulation time 345444445 ps
CPU time 1.98 seconds
Started May 19 01:32:34 PM PDT 24
Finished May 19 01:32:39 PM PDT 24
Peak memory 200452 kb
Host smart-cf6344d9-e3f6-4814-9066-862b93e362de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948601727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3948601727
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2874990345
Short name T32
Test name
Test status
Simulation time 195538393 ps
CPU time 1.21 seconds
Started May 19 01:32:25 PM PDT 24
Finished May 19 01:32:28 PM PDT 24
Peak memory 200436 kb
Host smart-9409f57f-7cde-432a-ac0a-92615ef4e599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874990345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2874990345
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.461814636
Short name T45
Test name
Test status
Simulation time 67953192 ps
CPU time 0.78 seconds
Started May 19 01:32:31 PM PDT 24
Finished May 19 01:32:34 PM PDT 24
Peak memory 200268 kb
Host smart-ecfefc3a-945a-4816-85dc-e4fb47ffef62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461814636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.461814636
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1450386143
Short name T434
Test name
Test status
Simulation time 2369723376 ps
CPU time 9.21 seconds
Started May 19 01:32:30 PM PDT 24
Finished May 19 01:32:41 PM PDT 24
Peak memory 217476 kb
Host smart-b7b443d7-b579-4bef-8201-195a03434b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450386143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1450386143
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.4102036613
Short name T49
Test name
Test status
Simulation time 244735392 ps
CPU time 1.1 seconds
Started May 19 01:32:26 PM PDT 24
Finished May 19 01:32:28 PM PDT 24
Peak memory 217572 kb
Host smart-4ad91b3d-35c2-4584-b508-55dd7ea8523e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102036613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.4102036613
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3963373027
Short name T254
Test name
Test status
Simulation time 103690742 ps
CPU time 0.81 seconds
Started May 19 01:32:30 PM PDT 24
Finished May 19 01:32:33 PM PDT 24
Peak memory 200264 kb
Host smart-f5762b14-dbae-494a-9bb7-dd6f48152424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963373027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3963373027
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.4143941863
Short name T483
Test name
Test status
Simulation time 1624092400 ps
CPU time 5.85 seconds
Started May 19 01:32:33 PM PDT 24
Finished May 19 01:32:42 PM PDT 24
Peak memory 200652 kb
Host smart-614c4538-3903-45d0-8335-fb0c99c63c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143941863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.4143941863
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2107510263
Short name T369
Test name
Test status
Simulation time 109527330 ps
CPU time 1.04 seconds
Started May 19 01:32:33 PM PDT 24
Finished May 19 01:32:37 PM PDT 24
Peak memory 200336 kb
Host smart-c7b96a64-4199-4df9-ac65-b4d350730f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107510263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2107510263
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2030038958
Short name T524
Test name
Test status
Simulation time 122452546 ps
CPU time 1.35 seconds
Started May 19 01:32:24 PM PDT 24
Finished May 19 01:32:27 PM PDT 24
Peak memory 200616 kb
Host smart-7d0d9d1d-13ae-4742-82d4-29f89a3755cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030038958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2030038958
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.971118017
Short name T316
Test name
Test status
Simulation time 8011338897 ps
CPU time 29.04 seconds
Started May 19 01:32:35 PM PDT 24
Finished May 19 01:33:07 PM PDT 24
Peak memory 209928 kb
Host smart-ef5407df-55e5-4eb4-99dd-4e78ad688f09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971118017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.971118017
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3065713306
Short name T336
Test name
Test status
Simulation time 126957500 ps
CPU time 1.81 seconds
Started May 19 01:32:27 PM PDT 24
Finished May 19 01:32:31 PM PDT 24
Peak memory 200368 kb
Host smart-ce8ad915-e6db-4f74-b55a-f567a8308ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065713306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3065713306
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3747609941
Short name T341
Test name
Test status
Simulation time 159983202 ps
CPU time 1.14 seconds
Started May 19 01:32:35 PM PDT 24
Finished May 19 01:32:38 PM PDT 24
Peak memory 200740 kb
Host smart-99f87451-0f6d-46a8-a527-3898ceadfc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747609941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3747609941
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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