Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8438

1

T1

113

T2

200

T3

173

auto[1]

11363

1

T1

132

T2

187

T3

187

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6103	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6639	1			T1	91		T2	123		T3	113
reset_info_cp[2]	3024	1			T1	38		T2	50		T3	63
reset_info_cp[4]	4047	1			T1	51		T2	90		T3	72
reset_info_cp[8]	134	1			T2	1		T3	1		T10	1
reset_info_cp[16]	97	1			T1	1		T2	1		T3	2
reset_info_cp[32]	112	1			T1	1		T2	3		T3	2
reset_info_cp[64]	119	1			T1	2		T2	2		T3	3
reset_info_cp[128]	146	1			T2	3		T3	2		T4	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3180	1			T1	42		T2	67		T3	48
reset_info_cp[1]	auto[1]	2839	1			T1	48		T2	55		T3	64
reset_info_cp[2]	auto[0]	976	1			T1	18		T2	23		T3	29
reset_info_cp[2]	auto[1]	2048	1			T1	20		T2	27		T3	34
reset_info_cp[4]	auto[0]	1454	1			T1	22		T2	40		T3	33
reset_info_cp[4]	auto[1]	2593	1			T1	29		T2	50		T3	39
reset_info_cp[8]	auto[0]	55	1			T3	1		T43	2		T28	2
reset_info_cp[8]	auto[1]	79	1			T2	1		T10	1		T27	2
reset_info_cp[16]	auto[0]	40	1			T3	1		T43	1		T28	2
reset_info_cp[16]	auto[1]	57	1			T1	1		T2	1		T3	1
reset_info_cp[32]	auto[0]	42	1			T3	1		T6	1		T28	1
reset_info_cp[32]	auto[1]	70	1			T1	1		T2	3		T3	1
reset_info_cp[64]	auto[0]	44	1			T3	1		T43	1		T28	1
reset_info_cp[64]	auto[1]	75	1			T1	2		T2	2		T3	2
reset_info_cp[128]	auto[0]	59	1			T3	2		T4	1		T28	1
reset_info_cp[128]	auto[1]	87	1			T2	3		T10	1		T15	1