Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8393

1

T1

122

T2

207

T3

175

auto[1]

11408

1

T1

123

T2

180

T3

185

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6103	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6639	1			T1	91		T2	123		T3	113
reset_info_cp[2]	3024	1			T1	38		T2	50		T3	63
reset_info_cp[4]	4047	1			T1	51		T2	90		T3	72
reset_info_cp[8]	134	1			T2	1		T3	1		T10	1
reset_info_cp[16]	97	1			T1	1		T2	1		T3	2
reset_info_cp[32]	112	1			T1	1		T2	3		T3	2
reset_info_cp[64]	119	1			T1	2		T2	2		T3	3
reset_info_cp[128]	146	1			T2	3		T3	2		T4	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3175	1			T1	39		T2	59		T3	54
reset_info_cp[1]	auto[1]	2844	1			T1	51		T2	63		T3	58
reset_info_cp[2]	auto[0]	955	1			T1	18		T2	22		T3	26
reset_info_cp[2]	auto[1]	2069	1			T1	20		T2	28		T3	37
reset_info_cp[4]	auto[0]	1459	1			T1	28		T2	44		T3	24
reset_info_cp[4]	auto[1]	2588	1			T1	23		T2	46		T3	48
reset_info_cp[8]	auto[0]	52	1			T2	1		T3	1		T43	2
reset_info_cp[8]	auto[1]	82	1			T10	1		T27	2		T28	1
reset_info_cp[16]	auto[0]	35	1			T2	1		T43	1		T28	2
reset_info_cp[16]	auto[1]	62	1			T1	1		T3	2		T10	1
reset_info_cp[32]	auto[0]	36	1			T2	1		T12	1		T28	3
reset_info_cp[32]	auto[1]	76	1			T1	1		T2	2		T3	2
reset_info_cp[64]	auto[0]	45	1			T2	1		T3	1		T12	1
reset_info_cp[64]	auto[1]	74	1			T1	2		T2	1		T3	2
reset_info_cp[128]	auto[0]	52	1			T2	2		T3	1		T4	1
reset_info_cp[128]	auto[1]	94	1			T2	1		T3	1		T10	1