Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
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T67 /workspace/coverage/default/3.rstmgr_sec_cm.2556880258 May 21 02:12:23 PM PDT 24 May 21 02:12:51 PM PDT 24 17322761303 ps
T538 /workspace/coverage/default/27.rstmgr_por_stretcher.2570704410 May 21 02:13:18 PM PDT 24 May 21 02:13:25 PM PDT 24 195569773 ps
T539 /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.3602915844 May 21 02:13:56 PM PDT 24 May 21 02:14:10 PM PDT 24 1895002400 ps
T540 /workspace/coverage/default/7.rstmgr_sw_rst.592480675 May 21 02:12:32 PM PDT 24 May 21 02:12:38 PM PDT 24 355113910 ps
T541 /workspace/coverage/default/9.rstmgr_stress_all.3398000716 May 21 02:12:29 PM PDT 24 May 21 02:13:06 PM PDT 24 9584781092 ps
T53 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1055408202 May 21 02:11:57 PM PDT 24 May 21 02:12:01 PM PDT 24 69576811 ps
T54 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1739201585 May 21 02:12:00 PM PDT 24 May 21 02:12:04 PM PDT 24 166541822 ps
T55 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.910908786 May 21 02:12:05 PM PDT 24 May 21 02:12:10 PM PDT 24 208208328 ps
T56 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1474190506 May 21 02:12:03 PM PDT 24 May 21 02:12:09 PM PDT 24 947408840 ps
T542 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3764359561 May 21 02:11:57 PM PDT 24 May 21 02:12:00 PM PDT 24 91863467 ps
T57 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1342624791 May 21 02:11:56 PM PDT 24 May 21 02:12:00 PM PDT 24 421501576 ps
T58 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.804969863 May 21 02:11:59 PM PDT 24 May 21 02:12:02 PM PDT 24 131030639 ps
T99 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.173898786 May 21 02:12:12 PM PDT 24 May 21 02:12:15 PM PDT 24 124578896 ps
T100 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2041703055 May 21 02:12:03 PM PDT 24 May 21 02:12:07 PM PDT 24 124233420 ps
T59 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2942262626 May 21 02:11:56 PM PDT 24 May 21 02:12:00 PM PDT 24 125077784 ps
T83 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2751190074 May 21 02:11:54 PM PDT 24 May 21 02:11:57 PM PDT 24 177995418 ps
T60 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.242039635 May 21 02:12:06 PM PDT 24 May 21 02:12:13 PM PDT 24 904293761 ps
T101 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1570181750 May 21 02:12:15 PM PDT 24 May 21 02:12:18 PM PDT 24 72690691 ps
T102 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3922409912 May 21 02:12:12 PM PDT 24 May 21 02:12:16 PM PDT 24 193074736 ps
T61 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1955716091 May 21 02:12:04 PM PDT 24 May 21 02:12:09 PM PDT 24 904540110 ps
T84 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3854931703 May 21 02:12:12 PM PDT 24 May 21 02:12:16 PM PDT 24 180531830 ps
T85 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1053200113 May 21 02:12:02 PM PDT 24 May 21 02:12:07 PM PDT 24 131905126 ps
T543 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2687921310 May 21 02:11:55 PM PDT 24 May 21 02:11:59 PM PDT 24 161701943 ps
T86 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1792846760 May 21 02:12:17 PM PDT 24 May 21 02:12:24 PM PDT 24 662863418 ps
T544 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.351520905 May 21 02:12:07 PM PDT 24 May 21 02:12:11 PM PDT 24 62951115 ps
T87 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2848449550 May 21 02:12:07 PM PDT 24 May 21 02:12:13 PM PDT 24 290117533 ps
T111 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1534439606 May 21 02:12:15 PM PDT 24 May 21 02:12:20 PM PDT 24 155522590 ps
T545 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2986268468 May 21 02:11:59 PM PDT 24 May 21 02:12:02 PM PDT 24 67527602 ps
T546 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3361630103 May 21 02:12:13 PM PDT 24 May 21 02:12:16 PM PDT 24 121991341 ps
T103 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4052758046 May 21 02:12:09 PM PDT 24 May 21 02:12:14 PM PDT 24 263910261 ps
T104 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2613538706 May 21 02:12:13 PM PDT 24 May 21 02:12:16 PM PDT 24 57491195 ps
T109 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1098774109 May 21 02:11:55 PM PDT 24 May 21 02:11:59 PM PDT 24 117238418 ps
T89 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3128988927 May 21 02:12:05 PM PDT 24 May 21 02:12:10 PM PDT 24 97524959 ps
T547 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3017237330 May 21 02:12:15 PM PDT 24 May 21 02:12:19 PM PDT 24 148364275 ps
T548 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.546847929 May 21 02:12:01 PM PDT 24 May 21 02:12:14 PM PDT 24 2299003915 ps
T549 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.618486942 May 21 02:12:14 PM PDT 24 May 21 02:12:18 PM PDT 24 412774698 ps
T550 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1708725896 May 21 02:12:01 PM PDT 24 May 21 02:12:06 PM PDT 24 401494478 ps
T110 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.306607816 May 21 02:12:04 PM PDT 24 May 21 02:12:11 PM PDT 24 541403914 ps
T105 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2478929497 May 21 02:11:59 PM PDT 24 May 21 02:12:03 PM PDT 24 88440357 ps
T106 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.977094655 May 21 02:12:12 PM PDT 24 May 21 02:12:15 PM PDT 24 67607366 ps
T116 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2082073246 May 21 02:12:01 PM PDT 24 May 21 02:12:06 PM PDT 24 797989691 ps
T551 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.972875548 May 21 02:11:57 PM PDT 24 May 21 02:12:00 PM PDT 24 122399646 ps
T107 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1303180617 May 21 02:12:02 PM PDT 24 May 21 02:12:06 PM PDT 24 240993836 ps
T552 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1050971107 May 21 02:11:57 PM PDT 24 May 21 02:12:05 PM PDT 24 1168202170 ps
T108 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1996082441 May 21 02:12:01 PM PDT 24 May 21 02:12:04 PM PDT 24 62278285 ps
T553 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3925339316 May 21 02:12:04 PM PDT 24 May 21 02:12:10 PM PDT 24 179208141 ps
T117 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.482929862 May 21 02:12:16 PM PDT 24 May 21 02:12:22 PM PDT 24 937287465 ps
T554 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.710308045 May 21 02:12:06 PM PDT 24 May 21 02:12:11 PM PDT 24 114368026 ps
T555 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3949557752 May 21 02:12:00 PM PDT 24 May 21 02:12:04 PM PDT 24 79106597 ps
T556 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2494512968 May 21 02:11:55 PM PDT 24 May 21 02:12:01 PM PDT 24 647484395 ps
T557 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.459181107 May 21 02:12:08 PM PDT 24 May 21 02:12:12 PM PDT 24 62367720 ps
T558 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1979244745 May 21 02:12:10 PM PDT 24 May 21 02:12:14 PM PDT 24 80149687 ps
T559 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3922340081 May 21 02:12:05 PM PDT 24 May 21 02:12:12 PM PDT 24 537661182 ps
T129 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4144836220 May 21 02:12:16 PM PDT 24 May 21 02:12:22 PM PDT 24 827280318 ps
T560 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.317617056 May 21 02:12:05 PM PDT 24 May 21 02:12:09 PM PDT 24 68243634 ps
T561 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.272233482 May 21 02:12:01 PM PDT 24 May 21 02:12:07 PM PDT 24 510128145 ps
T562 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.4091082800 May 21 02:12:05 PM PDT 24 May 21 02:12:09 PM PDT 24 64452568 ps
T563 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.58247103 May 21 02:12:02 PM PDT 24 May 21 02:12:08 PM PDT 24 264075517 ps
T564 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.4284357455 May 21 02:12:13 PM PDT 24 May 21 02:12:16 PM PDT 24 122188519 ps
T565 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3461983132 May 21 02:12:06 PM PDT 24 May 21 02:12:10 PM PDT 24 84620354 ps
T566 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.941888925 May 21 02:12:02 PM PDT 24 May 21 02:12:05 PM PDT 24 181993573 ps
T114 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1348836104 May 21 02:11:55 PM PDT 24 May 21 02:12:01 PM PDT 24 901657827 ps
T567 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2123969244 May 21 02:12:01 PM PDT 24 May 21 02:12:04 PM PDT 24 93982476 ps
T568 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2235607640 May 21 02:12:10 PM PDT 24 May 21 02:12:14 PM PDT 24 198831713 ps
T569 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1867020991 May 21 02:12:12 PM PDT 24 May 21 02:12:16 PM PDT 24 468733574 ps
T112 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.85829247 May 21 02:12:06 PM PDT 24 May 21 02:12:11 PM PDT 24 493241298 ps
T570 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.542843442 May 21 02:12:15 PM PDT 24 May 21 02:12:18 PM PDT 24 85409058 ps
T571 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1273523497 May 21 02:12:09 PM PDT 24 May 21 02:12:13 PM PDT 24 104318217 ps
T572 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.767638266 May 21 02:12:01 PM PDT 24 May 21 02:12:05 PM PDT 24 126790074 ps
T573 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2029040958 May 21 02:12:02 PM PDT 24 May 21 02:12:06 PM PDT 24 128439233 ps
T574 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2058926844 May 21 02:12:15 PM PDT 24 May 21 02:12:19 PM PDT 24 67446193 ps
T575 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1414157237 May 21 02:11:57 PM PDT 24 May 21 02:12:00 PM PDT 24 72276782 ps
T118 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.315346358 May 21 02:11:57 PM PDT 24 May 21 02:12:01 PM PDT 24 419831097 ps
T576 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3245337563 May 21 02:12:06 PM PDT 24 May 21 02:12:13 PM PDT 24 798959093 ps
T577 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3779817842 May 21 02:12:05 PM PDT 24 May 21 02:12:13 PM PDT 24 585710231 ps
T578 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3498461729 May 21 02:11:59 PM PDT 24 May 21 02:12:04 PM PDT 24 170579825 ps
T579 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2611620534 May 21 02:12:01 PM PDT 24 May 21 02:12:05 PM PDT 24 179660054 ps
T580 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3040266003 May 21 02:12:06 PM PDT 24 May 21 02:12:12 PM PDT 24 166283260 ps
T581 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2200392899 May 21 02:12:10 PM PDT 24 May 21 02:12:14 PM PDT 24 210038560 ps
T582 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2214057913 May 21 02:12:02 PM PDT 24 May 21 02:12:07 PM PDT 24 137623741 ps
T583 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3911499219 May 21 02:12:05 PM PDT 24 May 21 02:12:11 PM PDT 24 252373325 ps
T584 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3257092329 May 21 02:12:07 PM PDT 24 May 21 02:12:12 PM PDT 24 270413979 ps
T585 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2479274728 May 21 02:12:05 PM PDT 24 May 21 02:12:09 PM PDT 24 63900614 ps
T586 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.665317808 May 21 02:11:54 PM PDT 24 May 21 02:11:58 PM PDT 24 443031243 ps
T587 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2762986969 May 21 02:11:59 PM PDT 24 May 21 02:12:05 PM PDT 24 272825534 ps
T588 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.4101043317 May 21 02:12:06 PM PDT 24 May 21 02:12:12 PM PDT 24 436413366 ps
T589 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.4280013031 May 21 02:12:07 PM PDT 24 May 21 02:12:12 PM PDT 24 149830675 ps
T590 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.858145998 May 21 02:12:12 PM PDT 24 May 21 02:12:16 PM PDT 24 166739701 ps
T591 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2457517675 May 21 02:11:55 PM PDT 24 May 21 02:11:58 PM PDT 24 131452001 ps
T592 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.477976039 May 21 02:12:05 PM PDT 24 May 21 02:12:09 PM PDT 24 224166058 ps
T593 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2889640025 May 21 02:12:02 PM PDT 24 May 21 02:12:05 PM PDT 24 111274262 ps
T594 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2475371942 May 21 02:11:56 PM PDT 24 May 21 02:12:02 PM PDT 24 265736550 ps
T595 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2257911410 May 21 02:12:14 PM PDT 24 May 21 02:12:19 PM PDT 24 409828719 ps
T596 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.89394484 May 21 02:12:03 PM PDT 24 May 21 02:12:07 PM PDT 24 69749425 ps
T597 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3080844009 May 21 02:12:01 PM PDT 24 May 21 02:12:06 PM PDT 24 434204151 ps
T598 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3149759603 May 21 02:12:15 PM PDT 24 May 21 02:12:18 PM PDT 24 83989060 ps
T599 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1794738906 May 21 02:12:05 PM PDT 24 May 21 02:12:10 PM PDT 24 138363146 ps
T600 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.932775965 May 21 02:11:55 PM PDT 24 May 21 02:11:59 PM PDT 24 147569114 ps
T601 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3531693557 May 21 02:11:57 PM PDT 24 May 21 02:12:02 PM PDT 24 353447221 ps
T602 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3395092471 May 21 02:11:56 PM PDT 24 May 21 02:11:59 PM PDT 24 119814106 ps
T603 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1232898739 May 21 02:12:00 PM PDT 24 May 21 02:12:04 PM PDT 24 78948563 ps
T604 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.31414136 May 21 02:12:06 PM PDT 24 May 21 02:12:11 PM PDT 24 122828081 ps
T605 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1705590971 May 21 02:12:06 PM PDT 24 May 21 02:12:12 PM PDT 24 205233216 ps
T606 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3444133605 May 21 02:11:59 PM PDT 24 May 21 02:12:03 PM PDT 24 145524802 ps
T115 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3037043009 May 21 02:12:16 PM PDT 24 May 21 02:12:21 PM PDT 24 422861845 ps
T607 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3691673901 May 21 02:12:14 PM PDT 24 May 21 02:12:17 PM PDT 24 119324337 ps
T608 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2958681737 May 21 02:12:02 PM PDT 24 May 21 02:12:05 PM PDT 24 107575947 ps
T113 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3363443974 May 21 02:12:05 PM PDT 24 May 21 02:12:12 PM PDT 24 880918595 ps
T609 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2439123606 May 21 02:12:14 PM PDT 24 May 21 02:12:18 PM PDT 24 68123410 ps
T610 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3258831168 May 21 02:12:07 PM PDT 24 May 21 02:12:12 PM PDT 24 162274822 ps
T611 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1703264913 May 21 02:11:54 PM PDT 24 May 21 02:11:56 PM PDT 24 62655236 ps
T612 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.285374165 May 21 02:11:55 PM PDT 24 May 21 02:11:58 PM PDT 24 113777986 ps
T613 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3723313666 May 21 02:12:15 PM PDT 24 May 21 02:12:18 PM PDT 24 65912137 ps
T614 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4019073035 May 21 02:12:14 PM PDT 24 May 21 02:12:18 PM PDT 24 117484053 ps
T615 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2053026119 May 21 02:12:05 PM PDT 24 May 21 02:12:09 PM PDT 24 88912739 ps
T616 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3512852041 May 21 02:12:05 PM PDT 24 May 21 02:12:11 PM PDT 24 197533843 ps
T617 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2695361032 May 21 02:12:15 PM PDT 24 May 21 02:12:20 PM PDT 24 477875615 ps
T618 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2177212636 May 21 02:12:08 PM PDT 24 May 21 02:12:12 PM PDT 24 89031959 ps
T619 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.368302136 May 21 02:12:02 PM PDT 24 May 21 02:12:07 PM PDT 24 496291480 ps
T620 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3216262867 May 21 02:12:00 PM PDT 24 May 21 02:12:04 PM PDT 24 473153950 ps

Test location /workspace/coverage/default/7.rstmgr_stress_all.3467395346
Short name T3
Test name
Test status
Simulation time 9522647778 ps
CPU time 35.13 seconds
Started May 21 02:12:30 PM PDT 24
Finished May 21 02:13:08 PM PDT 24
Peak memory 209004 kb
Host smart-3080b8a3-32b1-4b3e-8dd9-e473759dbc81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467395346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3467395346
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.2066009416
Short name T52
Test name
Test status
Simulation time 139454469 ps
CPU time 1.76 seconds
Started May 21 02:12:31 PM PDT 24
Finished May 21 02:12:35 PM PDT 24
Peak memory 200496 kb
Host smart-ca1338a7-138a-496d-a866-7db21cd7aaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066009416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2066009416
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.910908786
Short name T55
Test name
Test status
Simulation time 208208328 ps
CPU time 1.96 seconds
Started May 21 02:12:05 PM PDT 24
Finished May 21 02:12:10 PM PDT 24
Peak memory 208844 kb
Host smart-49a112df-6710-43bd-9704-b6982557826b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910908786 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.910908786
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.444763020
Short name T62
Test name
Test status
Simulation time 16536745677 ps
CPU time 27.34 seconds
Started May 21 02:12:18 PM PDT 24
Finished May 21 02:12:48 PM PDT 24
Peak memory 217512 kb
Host smart-bf1b6c5f-f72f-496f-8fe0-28a1471184e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444763020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.444763020
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.614156794
Short name T10
Test name
Test status
Simulation time 1224531740 ps
CPU time 6.23 seconds
Started May 21 02:12:34 PM PDT 24
Finished May 21 02:12:45 PM PDT 24
Peak memory 217612 kb
Host smart-320a5d9c-98b7-4ea8-a0ff-1ed3af515a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614156794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.614156794
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1474190506
Short name T56
Test name
Test status
Simulation time 947408840 ps
CPU time 3.2 seconds
Started May 21 02:12:03 PM PDT 24
Finished May 21 02:12:09 PM PDT 24
Peak memory 200560 kb
Host smart-fa5350d0-c752-4493-8049-cdaba0789495
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474190506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1474190506
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/34.rstmgr_reset.1944461637
Short name T12
Test name
Test status
Simulation time 2186967330 ps
CPU time 8.72 seconds
Started May 21 02:13:28 PM PDT 24
Finished May 21 02:13:48 PM PDT 24
Peak memory 200784 kb
Host smart-d7161c40-db69-4b95-98d7-137990f49349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944461637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1944461637
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2064112882
Short name T5
Test name
Test status
Simulation time 73081193 ps
CPU time 0.77 seconds
Started May 21 02:12:36 PM PDT 24
Finished May 21 02:12:41 PM PDT 24
Peak memory 200240 kb
Host smart-73ea28bd-303e-4f91-89f0-d52d3eed43d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064112882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2064112882
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3314157880
Short name T160
Test name
Test status
Simulation time 179240704 ps
CPU time 1.19 seconds
Started May 21 02:12:38 PM PDT 24
Finished May 21 02:12:44 PM PDT 24
Peak memory 200496 kb
Host smart-bd036593-7406-49af-8dd3-4ab8af6101cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314157880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3314157880
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2494512968
Short name T556
Test name
Test status
Simulation time 647484395 ps
CPU time 3.96 seconds
Started May 21 02:11:55 PM PDT 24
Finished May 21 02:12:01 PM PDT 24
Peak memory 208836 kb
Host smart-f7442529-83fc-49da-bceb-bc3cd549db0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494512968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2494512968
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.4101043317
Short name T588
Test name
Test status
Simulation time 436413366 ps
CPU time 1.97 seconds
Started May 21 02:12:06 PM PDT 24
Finished May 21 02:12:12 PM PDT 24
Peak memory 200688 kb
Host smart-b89537ee-67f7-4149-9ca0-0698ecf617aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101043317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.4101043317
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2825253109
Short name T148
Test name
Test status
Simulation time 224776617 ps
CPU time 1.37 seconds
Started May 21 02:12:14 PM PDT 24
Finished May 21 02:12:18 PM PDT 24
Peak memory 200504 kb
Host smart-46dd0ffc-fff0-4c38-b47a-26b33a20de6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825253109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2825253109
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3096141081
Short name T38
Test name
Test status
Simulation time 1232497753 ps
CPU time 5.66 seconds
Started May 21 02:12:17 PM PDT 24
Finished May 21 02:12:25 PM PDT 24
Peak memory 218116 kb
Host smart-923310f3-ab93-40d2-9b65-aee5400312a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096141081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3096141081
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.895454058
Short name T44
Test name
Test status
Simulation time 2156922225 ps
CPU time 8.73 seconds
Started May 21 02:13:24 PM PDT 24
Finished May 21 02:13:40 PM PDT 24
Peak memory 222204 kb
Host smart-b5211bba-5797-4b0b-88f3-bdf3ce3cc13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895454058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.895454058
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.977094655
Short name T106
Test name
Test status
Simulation time 67607366 ps
CPU time 0.9 seconds
Started May 21 02:12:12 PM PDT 24
Finished May 21 02:12:15 PM PDT 24
Peak memory 200204 kb
Host smart-d6d342ea-aba2-458e-ab31-bad9baead0d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977094655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.977094655
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3086034402
Short name T17
Test name
Test status
Simulation time 185954950 ps
CPU time 0.9 seconds
Started May 21 02:12:21 PM PDT 24
Finished May 21 02:12:25 PM PDT 24
Peak memory 200484 kb
Host smart-ca48c409-2f33-4beb-a6cb-2c4276f447ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086034402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3086034402
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2942262626
Short name T59
Test name
Test status
Simulation time 125077784 ps
CPU time 1.84 seconds
Started May 21 02:11:56 PM PDT 24
Finished May 21 02:12:00 PM PDT 24
Peak memory 208840 kb
Host smart-21e4f840-6865-4846-837e-2b1fe1b5d80e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942262626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2942262626
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.85829247
Short name T112
Test name
Test status
Simulation time 493241298 ps
CPU time 1.88 seconds
Started May 21 02:12:06 PM PDT 24
Finished May 21 02:12:11 PM PDT 24
Peak memory 200704 kb
Host smart-d3feed41-ecb1-4b3c-beeb-4b0542b1fecb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85829247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.85829247
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2687921310
Short name T543
Test name
Test status
Simulation time 161701943 ps
CPU time 2.04 seconds
Started May 21 02:11:55 PM PDT 24
Finished May 21 02:11:59 PM PDT 24
Peak memory 208764 kb
Host smart-3fae3ed1-f11d-4dfd-9004-31c8b658f9fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687921310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
687921310
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1050971107
Short name T552
Test name
Test status
Simulation time 1168202170 ps
CPU time 5.62 seconds
Started May 21 02:11:57 PM PDT 24
Finished May 21 02:12:05 PM PDT 24
Peak memory 200532 kb
Host smart-f93992f7-4d04-4c21-ba84-12f15adde8ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050971107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
050971107
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3764359561
Short name T542
Test name
Test status
Simulation time 91863467 ps
CPU time 0.81 seconds
Started May 21 02:11:57 PM PDT 24
Finished May 21 02:12:00 PM PDT 24
Peak memory 200268 kb
Host smart-27e1e44e-0ab6-4407-9e9f-320506e5cec5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764359561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
764359561
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2751190074
Short name T83
Test name
Test status
Simulation time 177995418 ps
CPU time 1.2 seconds
Started May 21 02:11:54 PM PDT 24
Finished May 21 02:11:57 PM PDT 24
Peak memory 200480 kb
Host smart-f0f6479f-c041-4399-8294-9cd2bddc0b01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751190074 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2751190074
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1703264913
Short name T611
Test name
Test status
Simulation time 62655236 ps
CPU time 0.76 seconds
Started May 21 02:11:54 PM PDT 24
Finished May 21 02:11:56 PM PDT 24
Peak memory 200356 kb
Host smart-b5c70cc7-d5f0-4390-b9e9-f4cb58d37e03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703264913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1703264913
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3949557752
Short name T555
Test name
Test status
Simulation time 79106597 ps
CPU time 0.9 seconds
Started May 21 02:12:00 PM PDT 24
Finished May 21 02:12:04 PM PDT 24
Peak memory 200364 kb
Host smart-cb216f4f-ce31-4a34-8996-a9d671b52f2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949557752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3949557752
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.315346358
Short name T118
Test name
Test status
Simulation time 419831097 ps
CPU time 1.86 seconds
Started May 21 02:11:57 PM PDT 24
Finished May 21 02:12:01 PM PDT 24
Peak memory 200592 kb
Host smart-3218b1ed-0d59-4a34-9793-f9c6079b0aac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315346358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.
315346358
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.665317808
Short name T586
Test name
Test status
Simulation time 443031243 ps
CPU time 2.56 seconds
Started May 21 02:11:54 PM PDT 24
Finished May 21 02:11:58 PM PDT 24
Peak memory 200616 kb
Host smart-fdb88418-1670-4ad2-9765-298fa745c3f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665317808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.665317808
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2475371942
Short name T594
Test name
Test status
Simulation time 265736550 ps
CPU time 3.28 seconds
Started May 21 02:11:56 PM PDT 24
Finished May 21 02:12:02 PM PDT 24
Peak memory 200568 kb
Host smart-74d8d62f-066f-4f5d-883b-8c160458c1c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475371942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
475371942
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3395092471
Short name T602
Test name
Test status
Simulation time 119814106 ps
CPU time 0.86 seconds
Started May 21 02:11:56 PM PDT 24
Finished May 21 02:11:59 PM PDT 24
Peak memory 200296 kb
Host smart-4c20fbdd-b48b-459c-a9bf-6f2abe89f423
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395092471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.3
395092471
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1098774109
Short name T109
Test name
Test status
Simulation time 117238418 ps
CPU time 1.17 seconds
Started May 21 02:11:55 PM PDT 24
Finished May 21 02:11:59 PM PDT 24
Peak memory 208676 kb
Host smart-616b5ccb-99c6-45c1-a716-4bad61f5b829
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098774109 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1098774109
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1414157237
Short name T575
Test name
Test status
Simulation time 72276782 ps
CPU time 0.78 seconds
Started May 21 02:11:57 PM PDT 24
Finished May 21 02:12:00 PM PDT 24
Peak memory 200140 kb
Host smart-834ab7c8-a8d0-4078-aa3f-4989ecc08573
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414157237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1414157237
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.285374165
Short name T612
Test name
Test status
Simulation time 113777986 ps
CPU time 1.39 seconds
Started May 21 02:11:55 PM PDT 24
Finished May 21 02:11:58 PM PDT 24
Peak memory 200680 kb
Host smart-c3d8eeb4-1011-493a-8191-401703b1ca18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285374165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.285374165
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1342624791
Short name T57
Test name
Test status
Simulation time 421501576 ps
CPU time 1.87 seconds
Started May 21 02:11:56 PM PDT 24
Finished May 21 02:12:00 PM PDT 24
Peak memory 208740 kb
Host smart-c2f604ba-2b6a-41d8-a473-5d3aa4856079
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342624791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1342624791
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2177212636
Short name T618
Test name
Test status
Simulation time 89031959 ps
CPU time 0.87 seconds
Started May 21 02:12:08 PM PDT 24
Finished May 21 02:12:12 PM PDT 24
Peak memory 200328 kb
Host smart-53e75dff-6580-44a5-9f4d-f2d88ca19d83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177212636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2177212636
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3461983132
Short name T565
Test name
Test status
Simulation time 84620354 ps
CPU time 0.97 seconds
Started May 21 02:12:06 PM PDT 24
Finished May 21 02:12:10 PM PDT 24
Peak memory 200428 kb
Host smart-ae47f80b-59b9-4b45-a9e7-fc48630cfc57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461983132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3461983132
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3257092329
Short name T584
Test name
Test status
Simulation time 270413979 ps
CPU time 1.9 seconds
Started May 21 02:12:07 PM PDT 24
Finished May 21 02:12:12 PM PDT 24
Peak memory 208832 kb
Host smart-cc98dc0d-dc7f-41d8-a162-2663a1aa9e4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257092329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3257092329
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2235607640
Short name T568
Test name
Test status
Simulation time 198831713 ps
CPU time 1.31 seconds
Started May 21 02:12:10 PM PDT 24
Finished May 21 02:12:14 PM PDT 24
Peak memory 209544 kb
Host smart-d4497159-9caf-4138-b539-c3f24f75c0ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235607640 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2235607640
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.317617056
Short name T560
Test name
Test status
Simulation time 68243634 ps
CPU time 0.82 seconds
Started May 21 02:12:05 PM PDT 24
Finished May 21 02:12:09 PM PDT 24
Peak memory 200316 kb
Host smart-c7219f51-eb2a-4e0e-bb76-3e53166b0eda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317617056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.317617056
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1273523497
Short name T571
Test name
Test status
Simulation time 104318217 ps
CPU time 1.25 seconds
Started May 21 02:12:09 PM PDT 24
Finished May 21 02:12:13 PM PDT 24
Peak memory 199896 kb
Host smart-9754935d-ebb9-472e-b5ed-1074f9650925
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273523497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1273523497
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3040266003
Short name T580
Test name
Test status
Simulation time 166283260 ps
CPU time 2.83 seconds
Started May 21 02:12:06 PM PDT 24
Finished May 21 02:12:12 PM PDT 24
Peak memory 208816 kb
Host smart-495b2ef2-f627-4766-a018-139c189adf52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040266003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3040266003
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1867020991
Short name T569
Test name
Test status
Simulation time 468733574 ps
CPU time 1.89 seconds
Started May 21 02:12:12 PM PDT 24
Finished May 21 02:12:16 PM PDT 24
Peak memory 200572 kb
Host smart-bbb32a51-357e-42d6-8929-67c45479d068
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867020991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1867020991
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2200392899
Short name T581
Test name
Test status
Simulation time 210038560 ps
CPU time 1.44 seconds
Started May 21 02:12:10 PM PDT 24
Finished May 21 02:12:14 PM PDT 24
Peak memory 208668 kb
Host smart-bf6d3557-cb20-420d-b755-9886fc920c05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200392899 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2200392899
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4052758046
Short name T103
Test name
Test status
Simulation time 263910261 ps
CPU time 1.73 seconds
Started May 21 02:12:09 PM PDT 24
Finished May 21 02:12:14 PM PDT 24
Peak memory 199896 kb
Host smart-b8b08656-02f0-4194-989e-caad4d6bcbca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052758046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.4052758046
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3925339316
Short name T553
Test name
Test status
Simulation time 179208141 ps
CPU time 2.31 seconds
Started May 21 02:12:04 PM PDT 24
Finished May 21 02:12:10 PM PDT 24
Peak memory 208760 kb
Host smart-6dc94df8-50ec-40df-8489-f06226fc8ee6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925339316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3925339316
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4144836220
Short name T129
Test name
Test status
Simulation time 827280318 ps
CPU time 3 seconds
Started May 21 02:12:16 PM PDT 24
Finished May 21 02:12:22 PM PDT 24
Peak memory 200524 kb
Host smart-04896d76-5f70-4458-b0f0-9d5a6d1af756
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144836220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.4144836220
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1705590971
Short name T605
Test name
Test status
Simulation time 205233216 ps
CPU time 1.45 seconds
Started May 21 02:12:06 PM PDT 24
Finished May 21 02:12:12 PM PDT 24
Peak memory 208672 kb
Host smart-addc0f1f-16a4-4a56-87e5-bbbaeb7a6f1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705590971 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.1705590971
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.4091082800
Short name T562
Test name
Test status
Simulation time 64452568 ps
CPU time 0.81 seconds
Started May 21 02:12:05 PM PDT 24
Finished May 21 02:12:09 PM PDT 24
Peak memory 200336 kb
Host smart-69010d0f-65bb-4299-b758-0e85a6629aa7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091082800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.4091082800
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1979244745
Short name T558
Test name
Test status
Simulation time 80149687 ps
CPU time 1.02 seconds
Started May 21 02:12:10 PM PDT 24
Finished May 21 02:12:14 PM PDT 24
Peak memory 200404 kb
Host smart-84efc20b-28d7-4965-b79a-6022b10a6bf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979244745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1979244745
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1534439606
Short name T111
Test name
Test status
Simulation time 155522590 ps
CPU time 1.44 seconds
Started May 21 02:12:15 PM PDT 24
Finished May 21 02:12:20 PM PDT 24
Peak memory 200432 kb
Host smart-dd49bfb9-d402-454b-a9b5-70a2ba9a04b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534439606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1534439606
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3245337563
Short name T576
Test name
Test status
Simulation time 798959093 ps
CPU time 2.88 seconds
Started May 21 02:12:06 PM PDT 24
Finished May 21 02:12:13 PM PDT 24
Peak memory 200624 kb
Host smart-d0b6fa70-3612-43c3-8a65-d4973ba3095c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245337563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3245337563
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3854931703
Short name T84
Test name
Test status
Simulation time 180531830 ps
CPU time 1.87 seconds
Started May 21 02:12:12 PM PDT 24
Finished May 21 02:12:16 PM PDT 24
Peak memory 209012 kb
Host smart-0c707890-508a-4e0f-83c6-d33d34b8d353
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854931703 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3854931703
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2613538706
Short name T104
Test name
Test status
Simulation time 57491195 ps
CPU time 0.74 seconds
Started May 21 02:12:13 PM PDT 24
Finished May 21 02:12:16 PM PDT 24
Peak memory 200344 kb
Host smart-6f78a94d-5432-435f-872a-cea66f29247e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613538706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2613538706
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1794738906
Short name T599
Test name
Test status
Simulation time 138363146 ps
CPU time 1.21 seconds
Started May 21 02:12:05 PM PDT 24
Finished May 21 02:12:10 PM PDT 24
Peak memory 200400 kb
Host smart-c825ac48-e9a2-40af-803d-369a1d256f42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794738906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1794738906
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3922340081
Short name T559
Test name
Test status
Simulation time 537661182 ps
CPU time 3.16 seconds
Started May 21 02:12:05 PM PDT 24
Finished May 21 02:12:12 PM PDT 24
Peak memory 216864 kb
Host smart-7e8eec7c-439e-430a-8301-7b67415169e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922340081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3922340081
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.242039635
Short name T60
Test name
Test status
Simulation time 904293761 ps
CPU time 2.99 seconds
Started May 21 02:12:06 PM PDT 24
Finished May 21 02:12:13 PM PDT 24
Peak memory 200668 kb
Host smart-dfaa72b8-b61e-4194-b291-ccea83a62645
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242039635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.242039635
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3512852041
Short name T616
Test name
Test status
Simulation time 197533843 ps
CPU time 1.89 seconds
Started May 21 02:12:05 PM PDT 24
Finished May 21 02:12:11 PM PDT 24
Peak memory 208952 kb
Host smart-ce7767c1-6cad-4c98-8759-8b234b9401e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512852041 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3512852041
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.351520905
Short name T544
Test name
Test status
Simulation time 62951115 ps
CPU time 0.79 seconds
Started May 21 02:12:07 PM PDT 24
Finished May 21 02:12:11 PM PDT 24
Peak memory 200300 kb
Host smart-15eb15b0-030c-4399-891a-5c5850965d72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351520905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.351520905
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.4280013031
Short name T589
Test name
Test status
Simulation time 149830675 ps
CPU time 1.19 seconds
Started May 21 02:12:07 PM PDT 24
Finished May 21 02:12:12 PM PDT 24
Peak memory 200428 kb
Host smart-2ee9c7ad-e46c-4d20-97cb-80b4d255be96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280013031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.4280013031
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2848449550
Short name T87
Test name
Test status
Simulation time 290117533 ps
CPU time 1.96 seconds
Started May 21 02:12:07 PM PDT 24
Finished May 21 02:12:13 PM PDT 24
Peak memory 208688 kb
Host smart-fb968b71-2c5b-4aa7-a9db-2e2685990543
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848449550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2848449550
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3691673901
Short name T607
Test name
Test status
Simulation time 119324337 ps
CPU time 0.94 seconds
Started May 21 02:12:14 PM PDT 24
Finished May 21 02:12:17 PM PDT 24
Peak memory 200472 kb
Host smart-dfe2f2f1-67db-4678-9dee-b7be36b3b330
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691673901 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3691673901
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1570181750
Short name T101
Test name
Test status
Simulation time 72690691 ps
CPU time 0.83 seconds
Started May 21 02:12:15 PM PDT 24
Finished May 21 02:12:18 PM PDT 24
Peak memory 200356 kb
Host smart-24cbc46d-72e0-4d17-89fc-ff8ba92f3b36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570181750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1570181750
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3149759603
Short name T598
Test name
Test status
Simulation time 83989060 ps
CPU time 1.01 seconds
Started May 21 02:12:15 PM PDT 24
Finished May 21 02:12:18 PM PDT 24
Peak memory 200316 kb
Host smart-8f1d7337-59de-4f45-9701-721dbcfc3f63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149759603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3149759603
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3258831168
Short name T610
Test name
Test status
Simulation time 162274822 ps
CPU time 2.34 seconds
Started May 21 02:12:07 PM PDT 24
Finished May 21 02:12:12 PM PDT 24
Peak memory 208708 kb
Host smart-9916e701-0895-4c65-bccb-ec61bb7091fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258831168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3258831168
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.618486942
Short name T549
Test name
Test status
Simulation time 412774698 ps
CPU time 1.83 seconds
Started May 21 02:12:14 PM PDT 24
Finished May 21 02:12:18 PM PDT 24
Peak memory 200672 kb
Host smart-dccc37ac-21ae-4551-a560-898010408caa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618486942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err
.618486942
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3361630103
Short name T546
Test name
Test status
Simulation time 121991341 ps
CPU time 1.32 seconds
Started May 21 02:12:13 PM PDT 24
Finished May 21 02:12:16 PM PDT 24
Peak memory 208668 kb
Host smart-c5fe5b34-be55-4790-b37f-37bb306bd7e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361630103 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3361630103
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3723313666
Short name T613
Test name
Test status
Simulation time 65912137 ps
CPU time 0.81 seconds
Started May 21 02:12:15 PM PDT 24
Finished May 21 02:12:18 PM PDT 24
Peak memory 200368 kb
Host smart-1c19525e-45ac-45d3-91eb-33c3fed6cfa2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723313666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3723313666
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.542843442
Short name T570
Test name
Test status
Simulation time 85409058 ps
CPU time 1.03 seconds
Started May 21 02:12:15 PM PDT 24
Finished May 21 02:12:18 PM PDT 24
Peak memory 200424 kb
Host smart-fd8be09d-bcb9-49e2-b6f2-28dfd4c10b62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542843442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.542843442
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1792846760
Short name T86
Test name
Test status
Simulation time 662863418 ps
CPU time 4.19 seconds
Started May 21 02:12:17 PM PDT 24
Finished May 21 02:12:24 PM PDT 24
Peak memory 208836 kb
Host smart-43da4482-4936-4daf-b2e2-1e2afa4c5050
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792846760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1792846760
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2695361032
Short name T617
Test name
Test status
Simulation time 477875615 ps
CPU time 2.01 seconds
Started May 21 02:12:15 PM PDT 24
Finished May 21 02:12:20 PM PDT 24
Peak memory 200520 kb
Host smart-8449260a-b35c-4731-890b-8d6c2e612e6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695361032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2695361032
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3017237330
Short name T547
Test name
Test status
Simulation time 148364275 ps
CPU time 1.11 seconds
Started May 21 02:12:15 PM PDT 24
Finished May 21 02:12:19 PM PDT 24
Peak memory 208716 kb
Host smart-7f98074d-c63c-4f68-9567-4db3ee218ebd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017237330 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3017237330
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2439123606
Short name T609
Test name
Test status
Simulation time 68123410 ps
CPU time 0.81 seconds
Started May 21 02:12:14 PM PDT 24
Finished May 21 02:12:18 PM PDT 24
Peak memory 200384 kb
Host smart-07d01f6e-f105-49f4-824a-1869300ebcb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439123606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2439123606
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3922409912
Short name T102
Test name
Test status
Simulation time 193074736 ps
CPU time 1.45 seconds
Started May 21 02:12:12 PM PDT 24
Finished May 21 02:12:16 PM PDT 24
Peak memory 200596 kb
Host smart-acd3b678-28b5-4543-a068-6c94b7d8e4ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922409912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3922409912
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2257911410
Short name T595
Test name
Test status
Simulation time 409828719 ps
CPU time 3.42 seconds
Started May 21 02:12:14 PM PDT 24
Finished May 21 02:12:19 PM PDT 24
Peak memory 208772 kb
Host smart-7fa99c1a-a2ad-4a21-9478-360095de40da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257911410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2257911410
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3037043009
Short name T115
Test name
Test status
Simulation time 422861845 ps
CPU time 1.77 seconds
Started May 21 02:12:16 PM PDT 24
Finished May 21 02:12:21 PM PDT 24
Peak memory 200592 kb
Host smart-da628df8-7c49-4351-b656-90a6f181e389
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037043009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3037043009
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4019073035
Short name T614
Test name
Test status
Simulation time 117484053 ps
CPU time 0.99 seconds
Started May 21 02:12:14 PM PDT 24
Finished May 21 02:12:18 PM PDT 24
Peak memory 200516 kb
Host smart-92797ad7-34be-4288-a6eb-d252835187b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019073035 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.4019073035
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2058926844
Short name T574
Test name
Test status
Simulation time 67446193 ps
CPU time 0.82 seconds
Started May 21 02:12:15 PM PDT 24
Finished May 21 02:12:19 PM PDT 24
Peak memory 200300 kb
Host smart-5b7175de-6c6d-4869-8cc9-a85e6c454554
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058926844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2058926844
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.4284357455
Short name T564
Test name
Test status
Simulation time 122188519 ps
CPU time 1.05 seconds
Started May 21 02:12:13 PM PDT 24
Finished May 21 02:12:16 PM PDT 24
Peak memory 200396 kb
Host smart-ba7953d5-4c50-451a-8f45-da8646a53daa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284357455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.4284357455
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.858145998
Short name T590
Test name
Test status
Simulation time 166739701 ps
CPU time 2.35 seconds
Started May 21 02:12:12 PM PDT 24
Finished May 21 02:12:16 PM PDT 24
Peak memory 208800 kb
Host smart-ce9d9d4f-a804-41e8-9714-775dad45b6e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858145998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.858145998
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.482929862
Short name T117
Test name
Test status
Simulation time 937287465 ps
CPU time 3.35 seconds
Started May 21 02:12:16 PM PDT 24
Finished May 21 02:12:22 PM PDT 24
Peak memory 200656 kb
Host smart-676a4fd1-dc56-4400-92f7-227a34dd3e4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482929862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.482929862
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3531693557
Short name T601
Test name
Test status
Simulation time 353447221 ps
CPU time 2.5 seconds
Started May 21 02:11:57 PM PDT 24
Finished May 21 02:12:02 PM PDT 24
Peak memory 200388 kb
Host smart-8196f5f5-bc9d-464e-80c8-260269f46824
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531693557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
531693557
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.546847929
Short name T548
Test name
Test status
Simulation time 2299003915 ps
CPU time 10.37 seconds
Started May 21 02:12:01 PM PDT 24
Finished May 21 02:12:14 PM PDT 24
Peak memory 200612 kb
Host smart-fd883a2e-d8c1-4bb4-b123-76cae28f6782
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546847929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.546847929
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.972875548
Short name T551
Test name
Test status
Simulation time 122399646 ps
CPU time 0.89 seconds
Started May 21 02:11:57 PM PDT 24
Finished May 21 02:12:00 PM PDT 24
Peak memory 200336 kb
Host smart-c326ee0c-c0fa-496c-9db6-cbadd05e3750
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972875548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.972875548
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.941888925
Short name T566
Test name
Test status
Simulation time 181993573 ps
CPU time 1.25 seconds
Started May 21 02:12:02 PM PDT 24
Finished May 21 02:12:05 PM PDT 24
Peak memory 208608 kb
Host smart-50e5961f-a9fc-44cb-9fa9-465ae099367a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941888925 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.941888925
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1055408202
Short name T53
Test name
Test status
Simulation time 69576811 ps
CPU time 0.8 seconds
Started May 21 02:11:57 PM PDT 24
Finished May 21 02:12:01 PM PDT 24
Peak memory 200388 kb
Host smart-c6aac406-2e36-447c-80db-423c47391132
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055408202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1055408202
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2457517675
Short name T591
Test name
Test status
Simulation time 131452001 ps
CPU time 1.08 seconds
Started May 21 02:11:55 PM PDT 24
Finished May 21 02:11:58 PM PDT 24
Peak memory 200412 kb
Host smart-0559643e-5724-4f73-846f-6ddcbe4c490f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457517675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2457517675
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.932775965
Short name T600
Test name
Test status
Simulation time 147569114 ps
CPU time 2.24 seconds
Started May 21 02:11:55 PM PDT 24
Finished May 21 02:11:59 PM PDT 24
Peak memory 208780 kb
Host smart-11b3ac38-0776-459b-ab53-8f7d4fce772a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932775965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.932775965
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1348836104
Short name T114
Test name
Test status
Simulation time 901657827 ps
CPU time 3.4 seconds
Started May 21 02:11:55 PM PDT 24
Finished May 21 02:12:01 PM PDT 24
Peak memory 200616 kb
Host smart-b3da699c-2916-413c-bff7-aa79aab4828a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348836104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1348836104
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3128988927
Short name T89
Test name
Test status
Simulation time 97524959 ps
CPU time 1.27 seconds
Started May 21 02:12:05 PM PDT 24
Finished May 21 02:12:10 PM PDT 24
Peak memory 200452 kb
Host smart-d821fb6e-01f0-439e-83cf-124449872b98
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128988927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
128988927
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2762986969
Short name T587
Test name
Test status
Simulation time 272825534 ps
CPU time 3.29 seconds
Started May 21 02:11:59 PM PDT 24
Finished May 21 02:12:05 PM PDT 24
Peak memory 200584 kb
Host smart-00bf3b45-51d1-4062-b995-d09d7d48607a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762986969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
762986969
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3444133605
Short name T606
Test name
Test status
Simulation time 145524802 ps
CPU time 1.06 seconds
Started May 21 02:11:59 PM PDT 24
Finished May 21 02:12:03 PM PDT 24
Peak memory 200320 kb
Host smart-9e6cc9cf-8d7e-4f70-9490-4c72e1126cff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444133605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
444133605
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.804969863
Short name T58
Test name
Test status
Simulation time 131030639 ps
CPU time 1.08 seconds
Started May 21 02:11:59 PM PDT 24
Finished May 21 02:12:02 PM PDT 24
Peak memory 208632 kb
Host smart-4d2afa79-902e-4d2e-b0d0-e79e67b30f21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804969863 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.804969863
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1996082441
Short name T108
Test name
Test status
Simulation time 62278285 ps
CPU time 0.84 seconds
Started May 21 02:12:01 PM PDT 24
Finished May 21 02:12:04 PM PDT 24
Peak memory 200348 kb
Host smart-303a6bfa-f79c-40ca-ac37-13f621e32a31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996082441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1996082441
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.767638266
Short name T572
Test name
Test status
Simulation time 126790074 ps
CPU time 1.13 seconds
Started May 21 02:12:01 PM PDT 24
Finished May 21 02:12:05 PM PDT 24
Peak memory 200420 kb
Host smart-1bd78883-ec2d-4cd1-909d-6c0306fb3cb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767638266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam
e_csr_outstanding.767638266
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.272233482
Short name T561
Test name
Test status
Simulation time 510128145 ps
CPU time 3.71 seconds
Started May 21 02:12:01 PM PDT 24
Finished May 21 02:12:07 PM PDT 24
Peak memory 208756 kb
Host smart-780351dd-c5e4-411e-8e29-1eab0e71e8fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272233482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.272233482
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3080844009
Short name T597
Test name
Test status
Simulation time 434204151 ps
CPU time 1.81 seconds
Started May 21 02:12:01 PM PDT 24
Finished May 21 02:12:06 PM PDT 24
Peak memory 200672 kb
Host smart-333cf4df-28e2-4d16-8a48-b52541bfdca1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080844009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3080844009
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1708725896
Short name T550
Test name
Test status
Simulation time 401494478 ps
CPU time 2.63 seconds
Started May 21 02:12:01 PM PDT 24
Finished May 21 02:12:06 PM PDT 24
Peak memory 200556 kb
Host smart-7ebaaa00-4d46-4f35-9315-7cb9ba6fa4a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708725896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
708725896
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.58247103
Short name T563
Test name
Test status
Simulation time 264075517 ps
CPU time 3.31 seconds
Started May 21 02:12:02 PM PDT 24
Finished May 21 02:12:08 PM PDT 24
Peak memory 216848 kb
Host smart-6ecd3648-bba5-4e7a-b518-48d30e69a294
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58247103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.58247103
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2123969244
Short name T567
Test name
Test status
Simulation time 93982476 ps
CPU time 0.91 seconds
Started May 21 02:12:01 PM PDT 24
Finished May 21 02:12:04 PM PDT 24
Peak memory 200372 kb
Host smart-394cdba6-ed82-4742-9c70-b5ce22c679c7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123969244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
123969244
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1739201585
Short name T54
Test name
Test status
Simulation time 166541822 ps
CPU time 1.57 seconds
Started May 21 02:12:00 PM PDT 24
Finished May 21 02:12:04 PM PDT 24
Peak memory 208904 kb
Host smart-51297ed8-7bf5-442e-8a8a-8db26fedd53c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739201585 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1739201585
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2986268468
Short name T545
Test name
Test status
Simulation time 67527602 ps
CPU time 0.78 seconds
Started May 21 02:11:59 PM PDT 24
Finished May 21 02:12:02 PM PDT 24
Peak memory 200276 kb
Host smart-e0fffd78-be16-49dc-ac4e-a8749e97b6c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986268468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2986268468
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2889640025
Short name T593
Test name
Test status
Simulation time 111274262 ps
CPU time 1.02 seconds
Started May 21 02:12:02 PM PDT 24
Finished May 21 02:12:05 PM PDT 24
Peak memory 200372 kb
Host smart-557e8470-0249-442c-9ae9-7dbf6dda48b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889640025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.2889640025
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.306607816
Short name T110
Test name
Test status
Simulation time 541403914 ps
CPU time 3.98 seconds
Started May 21 02:12:04 PM PDT 24
Finished May 21 02:12:11 PM PDT 24
Peak memory 208744 kb
Host smart-649243a8-f370-4d1a-8c6a-1a153dc521b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306607816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.306607816
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2082073246
Short name T116
Test name
Test status
Simulation time 797989691 ps
CPU time 2.81 seconds
Started May 21 02:12:01 PM PDT 24
Finished May 21 02:12:06 PM PDT 24
Peak memory 200704 kb
Host smart-a89e7097-a6b5-4450-9e5d-bdf9ae2d7f0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082073246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2082073246
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2029040958
Short name T573
Test name
Test status
Simulation time 128439233 ps
CPU time 1.47 seconds
Started May 21 02:12:02 PM PDT 24
Finished May 21 02:12:06 PM PDT 24
Peak memory 208752 kb
Host smart-6b166674-a351-43d8-b995-611b2a886109
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029040958 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2029040958
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.89394484
Short name T596
Test name
Test status
Simulation time 69749425 ps
CPU time 0.87 seconds
Started May 21 02:12:03 PM PDT 24
Finished May 21 02:12:07 PM PDT 24
Peak memory 200296 kb
Host smart-362e5bde-72a9-4991-a723-aa3aec756e52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89394484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.89394484
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1303180617
Short name T107
Test name
Test status
Simulation time 240993836 ps
CPU time 1.54 seconds
Started May 21 02:12:02 PM PDT 24
Finished May 21 02:12:06 PM PDT 24
Peak memory 200548 kb
Host smart-1ffcea35-3bd8-48f9-970d-c3d5452af6be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303180617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1303180617
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3498461729
Short name T578
Test name
Test status
Simulation time 170579825 ps
CPU time 2.59 seconds
Started May 21 02:11:59 PM PDT 24
Finished May 21 02:12:04 PM PDT 24
Peak memory 211352 kb
Host smart-73a147a3-3eed-4175-89db-fbc1e189c4c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498461729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3498461729
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2958681737
Short name T608
Test name
Test status
Simulation time 107575947 ps
CPU time 1.08 seconds
Started May 21 02:12:02 PM PDT 24
Finished May 21 02:12:05 PM PDT 24
Peak memory 209856 kb
Host smart-dfce9628-a86c-4fdb-af8e-8e0fc9dd441b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958681737 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2958681737
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2478929497
Short name T105
Test name
Test status
Simulation time 88440357 ps
CPU time 0.97 seconds
Started May 21 02:11:59 PM PDT 24
Finished May 21 02:12:03 PM PDT 24
Peak memory 200348 kb
Host smart-ad75d9e3-df74-4863-be1d-e8e5002f0f36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478929497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2478929497
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2041703055
Short name T100
Test name
Test status
Simulation time 124233420 ps
CPU time 1.11 seconds
Started May 21 02:12:03 PM PDT 24
Finished May 21 02:12:07 PM PDT 24
Peak memory 200376 kb
Host smart-fd3d7967-3053-4d5e-89f4-f7449147974b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041703055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.2041703055
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1053200113
Short name T85
Test name
Test status
Simulation time 131905126 ps
CPU time 1.83 seconds
Started May 21 02:12:02 PM PDT 24
Finished May 21 02:12:07 PM PDT 24
Peak memory 208744 kb
Host smart-afa23977-56c8-41aa-a300-ed05087d6667
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053200113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1053200113
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.368302136
Short name T619
Test name
Test status
Simulation time 496291480 ps
CPU time 1.88 seconds
Started May 21 02:12:02 PM PDT 24
Finished May 21 02:12:07 PM PDT 24
Peak memory 200576 kb
Host smart-1d1be2d8-2f47-47aa-859e-1d18ae77d094
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368302136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
368302136
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2611620534
Short name T579
Test name
Test status
Simulation time 179660054 ps
CPU time 1.74 seconds
Started May 21 02:12:01 PM PDT 24
Finished May 21 02:12:05 PM PDT 24
Peak memory 208860 kb
Host smart-d673e7e1-1534-48d6-a94e-c213872e5e6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611620534 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2611620534
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1232898739
Short name T603
Test name
Test status
Simulation time 78948563 ps
CPU time 0.85 seconds
Started May 21 02:12:00 PM PDT 24
Finished May 21 02:12:04 PM PDT 24
Peak memory 200336 kb
Host smart-54c70fc1-b8bd-4312-97e4-4f5c49bc4473
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232898739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1232898739
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2053026119
Short name T615
Test name
Test status
Simulation time 88912739 ps
CPU time 1.02 seconds
Started May 21 02:12:05 PM PDT 24
Finished May 21 02:12:09 PM PDT 24
Peak memory 200456 kb
Host smart-c6d80cb4-6cdd-4028-bc31-4b7e84829b07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053026119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.2053026119
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.477976039
Short name T592
Test name
Test status
Simulation time 224166058 ps
CPU time 1.6 seconds
Started May 21 02:12:05 PM PDT 24
Finished May 21 02:12:09 PM PDT 24
Peak memory 208892 kb
Host smart-b729e17b-7013-4310-9936-a6f463ba540b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477976039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.477976039
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3216262867
Short name T620
Test name
Test status
Simulation time 473153950 ps
CPU time 2.04 seconds
Started May 21 02:12:00 PM PDT 24
Finished May 21 02:12:04 PM PDT 24
Peak memory 200612 kb
Host smart-ad53812e-a06c-4e9e-a3fa-ece0b038af36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216262867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3216262867
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.31414136
Short name T604
Test name
Test status
Simulation time 122828081 ps
CPU time 1.38 seconds
Started May 21 02:12:06 PM PDT 24
Finished May 21 02:12:11 PM PDT 24
Peak memory 208828 kb
Host smart-45a1b18b-3099-4be8-9557-54a255641fdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31414136 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.31414136
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2479274728
Short name T585
Test name
Test status
Simulation time 63900614 ps
CPU time 0.85 seconds
Started May 21 02:12:05 PM PDT 24
Finished May 21 02:12:09 PM PDT 24
Peak memory 200332 kb
Host smart-672a70c4-bf68-48a5-8dd1-85123195f35a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479274728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.2479274728
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.173898786
Short name T99
Test name
Test status
Simulation time 124578896 ps
CPU time 1.16 seconds
Started May 21 02:12:12 PM PDT 24
Finished May 21 02:12:15 PM PDT 24
Peak memory 200248 kb
Host smart-76f99835-1fa4-4f0c-a68a-801051d758be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173898786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.173898786
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2214057913
Short name T582
Test name
Test status
Simulation time 137623741 ps
CPU time 1.92 seconds
Started May 21 02:12:02 PM PDT 24
Finished May 21 02:12:07 PM PDT 24
Peak memory 216856 kb
Host smart-e725af5b-4b65-40ca-8fcd-41d48abd1cde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214057913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2214057913
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1955716091
Short name T61
Test name
Test status
Simulation time 904540110 ps
CPU time 3.12 seconds
Started May 21 02:12:04 PM PDT 24
Finished May 21 02:12:09 PM PDT 24
Peak memory 200560 kb
Host smart-f0555b6b-7238-4584-996f-4bf9568b22d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955716091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1955716091
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.710308045
Short name T554
Test name
Test status
Simulation time 114368026 ps
CPU time 1.12 seconds
Started May 21 02:12:06 PM PDT 24
Finished May 21 02:12:11 PM PDT 24
Peak memory 208656 kb
Host smart-64f97998-0d5c-47d4-883d-751c10662bc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710308045 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.710308045
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.459181107
Short name T557
Test name
Test status
Simulation time 62367720 ps
CPU time 0.81 seconds
Started May 21 02:12:08 PM PDT 24
Finished May 21 02:12:12 PM PDT 24
Peak memory 200352 kb
Host smart-56259e47-0496-4a2d-9b09-2108c3ae3582
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459181107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.459181107
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3911499219
Short name T583
Test name
Test status
Simulation time 252373325 ps
CPU time 1.62 seconds
Started May 21 02:12:05 PM PDT 24
Finished May 21 02:12:11 PM PDT 24
Peak memory 200592 kb
Host smart-40cea668-dcac-4b98-808d-7f48829cf787
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911499219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3911499219
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3779817842
Short name T577
Test name
Test status
Simulation time 585710231 ps
CPU time 3.74 seconds
Started May 21 02:12:05 PM PDT 24
Finished May 21 02:12:13 PM PDT 24
Peak memory 208792 kb
Host smart-8dd83609-0603-4a23-945a-a07b67808f63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779817842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3779817842
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3363443974
Short name T113
Test name
Test status
Simulation time 880918595 ps
CPU time 3.12 seconds
Started May 21 02:12:05 PM PDT 24
Finished May 21 02:12:12 PM PDT 24
Peak memory 200668 kb
Host smart-eeff7dda-1985-4c3a-8220-f02c41b6b071
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363443974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.3363443974
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3214103995
Short name T405
Test name
Test status
Simulation time 73362812 ps
CPU time 0.77 seconds
Started May 21 02:12:21 PM PDT 24
Finished May 21 02:12:25 PM PDT 24
Peak memory 200348 kb
Host smart-db57fbdf-c2f8-4910-8d14-0cd132b9f16a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214103995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3214103995
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1515829751
Short name T274
Test name
Test status
Simulation time 2164507347 ps
CPU time 8.05 seconds
Started May 21 02:12:20 PM PDT 24
Finished May 21 02:12:32 PM PDT 24
Peak memory 217624 kb
Host smart-d06e7d4f-abca-454c-bcc4-56fcbb9025d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515829751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1515829751
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2441305712
Short name T331
Test name
Test status
Simulation time 244947594 ps
CPU time 1.09 seconds
Started May 21 02:12:20 PM PDT 24
Finished May 21 02:12:24 PM PDT 24
Peak memory 217668 kb
Host smart-8ca3744c-9260-4996-b5d6-5429fb4fd811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441305712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2441305712
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3072659517
Short name T398
Test name
Test status
Simulation time 141032265 ps
CPU time 0.85 seconds
Started May 21 02:12:16 PM PDT 24
Finished May 21 02:12:20 PM PDT 24
Peak memory 200300 kb
Host smart-667836a0-7225-4e78-b4aa-f338410a3bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072659517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3072659517
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3302316779
Short name T271
Test name
Test status
Simulation time 1484034716 ps
CPU time 6.19 seconds
Started May 21 02:12:15 PM PDT 24
Finished May 21 02:12:24 PM PDT 24
Peak memory 200700 kb
Host smart-63c4eeb5-84b0-4be1-ae00-8ab1a8340fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302316779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3302316779
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1218845990
Short name T503
Test name
Test status
Simulation time 157495896 ps
CPU time 1.14 seconds
Started May 21 02:12:22 PM PDT 24
Finished May 21 02:12:26 PM PDT 24
Peak memory 200452 kb
Host smart-802c8efd-4c09-498a-8b03-695b61c381ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218845990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1218845990
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1615766081
Short name T149
Test name
Test status
Simulation time 190823000 ps
CPU time 1.36 seconds
Started May 21 02:12:13 PM PDT 24
Finished May 21 02:12:16 PM PDT 24
Peak memory 200664 kb
Host smart-32262fc2-29e3-4fcb-900c-06cc18387718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615766081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1615766081
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.806786707
Short name T463
Test name
Test status
Simulation time 6178460398 ps
CPU time 19.94 seconds
Started May 21 02:12:19 PM PDT 24
Finished May 21 02:12:42 PM PDT 24
Peak memory 208980 kb
Host smart-e3fa2f37-87c1-4edc-a529-ac0ae3f3a7e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806786707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.806786707
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1316732582
Short name T240
Test name
Test status
Simulation time 135448311 ps
CPU time 1.7 seconds
Started May 21 02:12:18 PM PDT 24
Finished May 21 02:12:22 PM PDT 24
Peak memory 208732 kb
Host smart-9dab8cc8-ee5e-497f-9912-9933ac2e769d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316732582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1316732582
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3156398780
Short name T506
Test name
Test status
Simulation time 77821111 ps
CPU time 0.8 seconds
Started May 21 02:12:19 PM PDT 24
Finished May 21 02:12:23 PM PDT 24
Peak memory 200336 kb
Host smart-92c96d04-76a9-49bd-879f-43ccaf718d77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156398780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3156398780
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3950005043
Short name T517
Test name
Test status
Simulation time 245362902 ps
CPU time 1.12 seconds
Started May 21 02:12:20 PM PDT 24
Finished May 21 02:12:24 PM PDT 24
Peak memory 217560 kb
Host smart-d0ea33f9-8afd-4240-972c-f52fc2e316b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950005043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3950005043
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2818722077
Short name T511
Test name
Test status
Simulation time 1517161986 ps
CPU time 6.02 seconds
Started May 21 02:12:19 PM PDT 24
Finished May 21 02:12:28 PM PDT 24
Peak memory 200688 kb
Host smart-31fec234-fa2c-40a2-96d9-006f70366dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818722077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2818722077
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3987864121
Short name T66
Test name
Test status
Simulation time 8330129352 ps
CPU time 13.73 seconds
Started May 21 02:12:17 PM PDT 24
Finished May 21 02:12:34 PM PDT 24
Peak memory 217440 kb
Host smart-89df47c6-ed2c-4ae5-8c30-0cc2ec4b6273
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987864121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3987864121
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3182996203
Short name T410
Test name
Test status
Simulation time 111148230 ps
CPU time 1.06 seconds
Started May 21 02:12:22 PM PDT 24
Finished May 21 02:12:25 PM PDT 24
Peak memory 200520 kb
Host smart-b2359e4d-596e-44c9-9544-0492a2fded00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182996203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3182996203
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.664895327
Short name T293
Test name
Test status
Simulation time 188038550 ps
CPU time 1.39 seconds
Started May 21 02:12:18 PM PDT 24
Finished May 21 02:12:22 PM PDT 24
Peak memory 200648 kb
Host smart-5a4163ce-2add-4c9a-bd00-4d4b1b035269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664895327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.664895327
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3461465783
Short name T392
Test name
Test status
Simulation time 14517609005 ps
CPU time 55.69 seconds
Started May 21 02:12:18 PM PDT 24
Finished May 21 02:13:17 PM PDT 24
Peak memory 200864 kb
Host smart-a3039828-8e6e-451c-ae96-eb1ad314b722
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461465783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3461465783
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3589626247
Short name T74
Test name
Test status
Simulation time 463367988 ps
CPU time 2.46 seconds
Started May 21 02:12:18 PM PDT 24
Finished May 21 02:12:23 PM PDT 24
Peak memory 200524 kb
Host smart-ae8ae5ca-b3b5-4eb4-804d-6124f13a2e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589626247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3589626247
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3757844395
Short name T278
Test name
Test status
Simulation time 169081324 ps
CPU time 1.14 seconds
Started May 21 02:12:18 PM PDT 24
Finished May 21 02:12:23 PM PDT 24
Peak memory 200484 kb
Host smart-e12b1568-b6c1-4b10-98ac-9afc744b82d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757844395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3757844395
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3316186086
Short name T284
Test name
Test status
Simulation time 77872530 ps
CPU time 0.79 seconds
Started May 21 02:12:35 PM PDT 24
Finished May 21 02:12:40 PM PDT 24
Peak memory 200328 kb
Host smart-01ad70cd-efd9-4c8f-8b4e-572ae4f910fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316186086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3316186086
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.2804647874
Short name T323
Test name
Test status
Simulation time 1239740872 ps
CPU time 5.48 seconds
Started May 21 02:12:34 PM PDT 24
Finished May 21 02:12:42 PM PDT 24
Peak memory 221324 kb
Host smart-9c617534-1644-4f5a-8f12-0202845c16d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804647874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.2804647874
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3569641223
Short name T241
Test name
Test status
Simulation time 243452470 ps
CPU time 1.18 seconds
Started May 21 02:12:37 PM PDT 24
Finished May 21 02:12:42 PM PDT 24
Peak memory 217604 kb
Host smart-a3d2c273-3106-4e7f-9194-12de38ddab9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569641223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3569641223
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.1481908440
Short name T238
Test name
Test status
Simulation time 96820110 ps
CPU time 0.77 seconds
Started May 21 02:12:28 PM PDT 24
Finished May 21 02:12:31 PM PDT 24
Peak memory 200304 kb
Host smart-83fe61df-e820-4834-b16b-60b5c8ae14ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481908440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.1481908440
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2387667445
Short name T326
Test name
Test status
Simulation time 1750554092 ps
CPU time 6.44 seconds
Started May 21 02:12:36 PM PDT 24
Finished May 21 02:12:47 PM PDT 24
Peak memory 200620 kb
Host smart-baad4273-eb4b-49a5-97a1-71def576f08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387667445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2387667445
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2936339954
Short name T356
Test name
Test status
Simulation time 100956492 ps
CPU time 1.04 seconds
Started May 21 02:12:36 PM PDT 24
Finished May 21 02:12:41 PM PDT 24
Peak memory 200512 kb
Host smart-f250e7d3-ccfb-4a38-814c-9d27b4bd6aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936339954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2936339954
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.3029254087
Short name T375
Test name
Test status
Simulation time 242615040 ps
CPU time 1.52 seconds
Started May 21 02:12:32 PM PDT 24
Finished May 21 02:12:37 PM PDT 24
Peak memory 200672 kb
Host smart-b96a01fe-3ec1-400c-8f4b-5c1919c8766f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029254087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3029254087
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2684733634
Short name T525
Test name
Test status
Simulation time 1565964454 ps
CPU time 8.38 seconds
Started May 21 02:12:36 PM PDT 24
Finished May 21 02:12:49 PM PDT 24
Peak memory 216960 kb
Host smart-fe8fa212-b29d-4aae-bf16-66d481c8d86e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684733634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2684733634
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2432621783
Short name T126
Test name
Test status
Simulation time 342830500 ps
CPU time 2.06 seconds
Started May 21 02:12:34 PM PDT 24
Finished May 21 02:12:39 PM PDT 24
Peak memory 200512 kb
Host smart-246fc233-c9d1-45bf-bf8d-fc8f72e5ac85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432621783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2432621783
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2214231486
Short name T124
Test name
Test status
Simulation time 171412558 ps
CPU time 1.17 seconds
Started May 21 02:12:35 PM PDT 24
Finished May 21 02:12:41 PM PDT 24
Peak memory 200496 kb
Host smart-3a01fe5a-63f9-4f68-8acb-d560c2f19ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214231486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2214231486
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.427223212
Short name T359
Test name
Test status
Simulation time 90579927 ps
CPU time 0.79 seconds
Started May 21 02:12:34 PM PDT 24
Finished May 21 02:12:39 PM PDT 24
Peak memory 200304 kb
Host smart-9e652c7c-251b-45c2-a1bc-84e26bc820e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427223212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.427223212
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2803444489
Short name T46
Test name
Test status
Simulation time 1213580013 ps
CPU time 5.48 seconds
Started May 21 02:12:35 PM PDT 24
Finished May 21 02:12:45 PM PDT 24
Peak memory 217576 kb
Host smart-1b455ad6-ec0b-47ae-9f1e-006006380fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803444489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2803444489
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1824024417
Short name T273
Test name
Test status
Simulation time 244235513 ps
CPU time 1.08 seconds
Started May 21 02:12:38 PM PDT 24
Finished May 21 02:12:44 PM PDT 24
Peak memory 217588 kb
Host smart-b2b895ad-930e-46f1-9f6b-908fe567ba0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824024417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1824024417
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.3723324966
Short name T309
Test name
Test status
Simulation time 189818171 ps
CPU time 0.85 seconds
Started May 21 02:12:37 PM PDT 24
Finished May 21 02:12:42 PM PDT 24
Peak memory 200324 kb
Host smart-fbaf8bf8-87e4-4dc7-a08c-653393ab172e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723324966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3723324966
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.3597555712
Short name T258
Test name
Test status
Simulation time 1790166420 ps
CPU time 7.16 seconds
Started May 21 02:12:34 PM PDT 24
Finished May 21 02:12:45 PM PDT 24
Peak memory 200708 kb
Host smart-b870daa1-5eb6-4e67-9e0f-446c66577efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597555712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3597555712
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3404057948
Short name T535
Test name
Test status
Simulation time 106747586 ps
CPU time 1.01 seconds
Started May 21 02:12:37 PM PDT 24
Finished May 21 02:12:42 PM PDT 24
Peak memory 200520 kb
Host smart-025fcbf6-69ef-42a6-b4ab-2501f8af8bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404057948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3404057948
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3622736399
Short name T466
Test name
Test status
Simulation time 114314063 ps
CPU time 1.18 seconds
Started May 21 02:12:36 PM PDT 24
Finished May 21 02:12:42 PM PDT 24
Peak memory 200672 kb
Host smart-996b8314-4e0d-4d7d-bcb9-c2d81e636b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622736399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3622736399
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.4042003198
Short name T217
Test name
Test status
Simulation time 1249296256 ps
CPU time 7.22 seconds
Started May 21 02:12:36 PM PDT 24
Finished May 21 02:12:47 PM PDT 24
Peak memory 208892 kb
Host smart-154c5c6d-d049-484d-a38b-bbb748f653c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042003198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.4042003198
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.4161151933
Short name T222
Test name
Test status
Simulation time 142063642 ps
CPU time 1.64 seconds
Started May 21 02:12:36 PM PDT 24
Finished May 21 02:12:42 PM PDT 24
Peak memory 208676 kb
Host smart-1734b6cc-1664-4752-8347-86563dcb6dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161151933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.4161151933
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3157771125
Short name T249
Test name
Test status
Simulation time 122698426 ps
CPU time 1.11 seconds
Started May 21 02:12:36 PM PDT 24
Finished May 21 02:12:41 PM PDT 24
Peak memory 200536 kb
Host smart-393e65f7-3b3a-44d0-82a4-ece06f1cad2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157771125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3157771125
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.1687788008
Short name T51
Test name
Test status
Simulation time 1885704622 ps
CPU time 7.47 seconds
Started May 21 02:12:34 PM PDT 24
Finished May 21 02:12:45 PM PDT 24
Peak memory 217600 kb
Host smart-a8d8c170-6e2e-4184-bf69-e18289a68138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687788008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1687788008
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3645505447
Short name T216
Test name
Test status
Simulation time 245194010 ps
CPU time 1.02 seconds
Started May 21 02:12:35 PM PDT 24
Finished May 21 02:12:41 PM PDT 24
Peak memory 217588 kb
Host smart-6bb3119f-3e24-4c16-9fee-e8cb74fab406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645505447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3645505447
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.4216250126
Short name T415
Test name
Test status
Simulation time 202273905 ps
CPU time 0.86 seconds
Started May 21 02:12:40 PM PDT 24
Finished May 21 02:12:47 PM PDT 24
Peak memory 200316 kb
Host smart-5ff45e49-1518-4501-a337-0ca06fb5450b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216250126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.4216250126
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2523910956
Short name T121
Test name
Test status
Simulation time 2176997529 ps
CPU time 7.97 seconds
Started May 21 02:12:36 PM PDT 24
Finished May 21 02:12:48 PM PDT 24
Peak memory 200772 kb
Host smart-385b66ba-dcc3-4f36-83f8-2bee23eb0ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523910956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2523910956
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3464480110
Short name T246
Test name
Test status
Simulation time 118743356 ps
CPU time 1.26 seconds
Started May 21 02:12:37 PM PDT 24
Finished May 21 02:12:42 PM PDT 24
Peak memory 200696 kb
Host smart-7a7e08da-bdda-4364-8f63-8307bb54bdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464480110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3464480110
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3101494816
Short name T91
Test name
Test status
Simulation time 4162104222 ps
CPU time 16.11 seconds
Started May 21 02:12:35 PM PDT 24
Finished May 21 02:12:56 PM PDT 24
Peak memory 200752 kb
Host smart-c226cda0-f90a-4430-8aa1-9d9797880df3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101494816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3101494816
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1514808683
Short name T198
Test name
Test status
Simulation time 154195682 ps
CPU time 2.04 seconds
Started May 21 02:12:36 PM PDT 24
Finished May 21 02:12:42 PM PDT 24
Peak memory 200400 kb
Host smart-f14be0aa-78fb-4ebb-acbe-eef0c7d6e720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514808683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1514808683
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3509263943
Short name T453
Test name
Test status
Simulation time 151612605 ps
CPU time 1.06 seconds
Started May 21 02:12:40 PM PDT 24
Finished May 21 02:12:47 PM PDT 24
Peak memory 200508 kb
Host smart-5b306afa-c179-4d0f-a41e-c3bbeeea0115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509263943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3509263943
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1942873795
Short name T377
Test name
Test status
Simulation time 83286708 ps
CPU time 0.78 seconds
Started May 21 02:12:33 PM PDT 24
Finished May 21 02:12:37 PM PDT 24
Peak memory 200280 kb
Host smart-24eaced8-7345-46ca-ab70-b7b54d901a5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942873795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1942873795
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3968714225
Short name T498
Test name
Test status
Simulation time 2347975590 ps
CPU time 8.11 seconds
Started May 21 02:12:36 PM PDT 24
Finished May 21 02:12:49 PM PDT 24
Peak memory 218248 kb
Host smart-7f255cbc-7114-4102-8c1d-efcba635960b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968714225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3968714225
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1954851111
Short name T265
Test name
Test status
Simulation time 244664701 ps
CPU time 1.11 seconds
Started May 21 02:12:37 PM PDT 24
Finished May 21 02:12:42 PM PDT 24
Peak memory 217572 kb
Host smart-5a738b4e-e335-4845-94d2-97058fcb238d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954851111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1954851111
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.557957279
Short name T268
Test name
Test status
Simulation time 224233994 ps
CPU time 0.97 seconds
Started May 21 02:12:36 PM PDT 24
Finished May 21 02:12:41 PM PDT 24
Peak memory 200208 kb
Host smart-3b8ac16c-d059-46c5-96d8-ee09129f666f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557957279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.557957279
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.1841515076
Short name T341
Test name
Test status
Simulation time 662379199 ps
CPU time 3.86 seconds
Started May 21 02:12:36 PM PDT 24
Finished May 21 02:12:45 PM PDT 24
Peak memory 200724 kb
Host smart-1ad23c57-8dba-4a9d-8c5b-d025c3066f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841515076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1841515076
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2518387222
Short name T363
Test name
Test status
Simulation time 180485005 ps
CPU time 1.26 seconds
Started May 21 02:12:36 PM PDT 24
Finished May 21 02:12:42 PM PDT 24
Peak memory 200432 kb
Host smart-5e2eec9f-7ac2-4645-8cce-80b9b4438dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518387222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2518387222
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1290510191
Short name T26
Test name
Test status
Simulation time 265370694 ps
CPU time 1.53 seconds
Started May 21 02:12:37 PM PDT 24
Finished May 21 02:12:43 PM PDT 24
Peak memory 200704 kb
Host smart-fe260dee-8202-46d1-bcbc-09eabc15e7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290510191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1290510191
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2958464003
Short name T285
Test name
Test status
Simulation time 5554707175 ps
CPU time 23.56 seconds
Started May 21 02:12:35 PM PDT 24
Finished May 21 02:13:03 PM PDT 24
Peak memory 200736 kb
Host smart-a9322a76-a351-4dc6-a1a6-a937ee0461df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958464003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2958464003
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3631140703
Short name T332
Test name
Test status
Simulation time 143529125 ps
CPU time 1.89 seconds
Started May 21 02:12:35 PM PDT 24
Finished May 21 02:12:41 PM PDT 24
Peak memory 200428 kb
Host smart-49683887-808b-4623-b1e9-165b88b5ef6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631140703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3631140703
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3180772050
Short name T155
Test name
Test status
Simulation time 73451384 ps
CPU time 0.85 seconds
Started May 21 02:12:33 PM PDT 24
Finished May 21 02:12:36 PM PDT 24
Peak memory 200476 kb
Host smart-c433a2f9-5507-4681-be9f-3741c15c7c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180772050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3180772050
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.1491995660
Short name T424
Test name
Test status
Simulation time 64816532 ps
CPU time 0.78 seconds
Started May 21 02:12:41 PM PDT 24
Finished May 21 02:12:47 PM PDT 24
Peak memory 200308 kb
Host smart-90f9bcc2-0f75-4628-a7a7-e6c2a6514fd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491995660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1491995660
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3497437530
Short name T348
Test name
Test status
Simulation time 2350087548 ps
CPU time 8.06 seconds
Started May 21 02:12:42 PM PDT 24
Finished May 21 02:12:55 PM PDT 24
Peak memory 217624 kb
Host smart-097f3601-e60b-4ad3-9b61-66e242a53588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497437530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3497437530
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.335126155
Short name T158
Test name
Test status
Simulation time 244706343 ps
CPU time 1.08 seconds
Started May 21 02:12:41 PM PDT 24
Finished May 21 02:12:48 PM PDT 24
Peak memory 217560 kb
Host smart-07cce8c9-cbcc-4dfc-9398-b50440a6adf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335126155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.335126155
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.4146306283
Short name T531
Test name
Test status
Simulation time 109400431 ps
CPU time 0.8 seconds
Started May 21 02:12:40 PM PDT 24
Finished May 21 02:12:46 PM PDT 24
Peak memory 200316 kb
Host smart-83acd097-3786-46e4-82cc-e9d51764696c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146306283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.4146306283
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2605949582
Short name T367
Test name
Test status
Simulation time 790908951 ps
CPU time 4.29 seconds
Started May 21 02:12:37 PM PDT 24
Finished May 21 02:12:46 PM PDT 24
Peak memory 200656 kb
Host smart-8602aa0f-d907-4faa-9137-ff0825d357ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605949582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2605949582
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2852652496
Short name T401
Test name
Test status
Simulation time 169816553 ps
CPU time 1.18 seconds
Started May 21 02:12:42 PM PDT 24
Finished May 21 02:12:48 PM PDT 24
Peak memory 200452 kb
Host smart-ab88082f-cd05-4942-8e4e-ac2ef4f1690a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852652496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2852652496
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.4172921429
Short name T296
Test name
Test status
Simulation time 120863693 ps
CPU time 1.15 seconds
Started May 21 02:12:36 PM PDT 24
Finished May 21 02:12:41 PM PDT 24
Peak memory 200620 kb
Host smart-ffe131e4-f9ac-4f4a-8ddf-34c4ebcb3b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172921429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.4172921429
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1916093924
Short name T94
Test name
Test status
Simulation time 8504189897 ps
CPU time 32.74 seconds
Started May 21 02:12:42 PM PDT 24
Finished May 21 02:13:20 PM PDT 24
Peak memory 200740 kb
Host smart-72567766-83c2-4c03-91c6-5df1bd0ed4fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916093924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1916093924
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3854388985
Short name T29
Test name
Test status
Simulation time 369292458 ps
CPU time 2.38 seconds
Started May 21 02:12:40 PM PDT 24
Finished May 21 02:12:48 PM PDT 24
Peak memory 200460 kb
Host smart-53d76e7e-d3f2-4a19-bdcc-65c3b28b2d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854388985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3854388985
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1464916670
Short name T435
Test name
Test status
Simulation time 153610581 ps
CPU time 1.21 seconds
Started May 21 02:12:42 PM PDT 24
Finished May 21 02:12:48 PM PDT 24
Peak memory 200520 kb
Host smart-acc4cb64-e48a-4c07-bde3-65e632a486f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464916670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1464916670
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.940043881
Short name T502
Test name
Test status
Simulation time 62288146 ps
CPU time 0.82 seconds
Started May 21 02:12:40 PM PDT 24
Finished May 21 02:12:46 PM PDT 24
Peak memory 200328 kb
Host smart-59880ae1-347c-4c00-b576-bcf52103bf8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940043881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.940043881
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1171648909
Short name T447
Test name
Test status
Simulation time 2369336390 ps
CPU time 8.05 seconds
Started May 21 02:12:43 PM PDT 24
Finished May 21 02:12:56 PM PDT 24
Peak memory 222208 kb
Host smart-42791c07-6c70-42ba-af6f-ce3c8a3c0ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171648909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1171648909
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1218099785
Short name T371
Test name
Test status
Simulation time 244451734 ps
CPU time 1.07 seconds
Started May 21 02:12:40 PM PDT 24
Finished May 21 02:12:47 PM PDT 24
Peak memory 217696 kb
Host smart-16f5dc70-dbbf-471d-9dc3-353dcd9e2fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218099785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1218099785
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.645966402
Short name T372
Test name
Test status
Simulation time 164823560 ps
CPU time 0.89 seconds
Started May 21 02:12:42 PM PDT 24
Finished May 21 02:12:48 PM PDT 24
Peak memory 200300 kb
Host smart-ddb2af43-7e4a-4715-9708-724710d31222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645966402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.645966402
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1442927363
Short name T478
Test name
Test status
Simulation time 1035336095 ps
CPU time 5.03 seconds
Started May 21 02:12:43 PM PDT 24
Finished May 21 02:12:52 PM PDT 24
Peak memory 200724 kb
Host smart-028e3778-1fa1-44d4-b3bf-74eede90dbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442927363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1442927363
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3329666727
Short name T481
Test name
Test status
Simulation time 103314555 ps
CPU time 1.03 seconds
Started May 21 02:12:41 PM PDT 24
Finished May 21 02:12:47 PM PDT 24
Peak memory 200444 kb
Host smart-2087382a-e36d-4cb6-8562-9b2799f9812f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329666727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3329666727
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.4047335940
Short name T537
Test name
Test status
Simulation time 200660592 ps
CPU time 1.4 seconds
Started May 21 02:12:42 PM PDT 24
Finished May 21 02:12:49 PM PDT 24
Peak memory 200760 kb
Host smart-9194c344-c47e-4013-aa5d-31733822d627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047335940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.4047335940
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2673407425
Short name T215
Test name
Test status
Simulation time 1028119312 ps
CPU time 5.27 seconds
Started May 21 02:12:43 PM PDT 24
Finished May 21 02:12:53 PM PDT 24
Peak memory 200716 kb
Host smart-fde8224f-ddac-4576-9e71-d591af961ea0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673407425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2673407425
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.1778862445
Short name T279
Test name
Test status
Simulation time 364610528 ps
CPU time 2.47 seconds
Started May 21 02:12:41 PM PDT 24
Finished May 21 02:12:49 PM PDT 24
Peak memory 200484 kb
Host smart-e349ef85-2056-4b9e-99a3-e009dcf34b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778862445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1778862445
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3739731556
Short name T482
Test name
Test status
Simulation time 60497977 ps
CPU time 0.75 seconds
Started May 21 02:12:40 PM PDT 24
Finished May 21 02:12:46 PM PDT 24
Peak memory 200436 kb
Host smart-3ed66f02-df13-45c6-9e6f-7a3088d2cc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739731556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3739731556
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2165427699
Short name T297
Test name
Test status
Simulation time 66193859 ps
CPU time 0.79 seconds
Started May 21 02:12:50 PM PDT 24
Finished May 21 02:12:54 PM PDT 24
Peak memory 200308 kb
Host smart-b40384ca-c2ab-407c-ae08-2715c51b996f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165427699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2165427699
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2320548535
Short name T364
Test name
Test status
Simulation time 1216962390 ps
CPU time 5.25 seconds
Started May 21 02:12:41 PM PDT 24
Finished May 21 02:12:51 PM PDT 24
Peak memory 230436 kb
Host smart-97edc422-0d12-4235-bd64-1cacf4a97358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320548535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2320548535
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2754638421
Short name T340
Test name
Test status
Simulation time 244531755 ps
CPU time 1.14 seconds
Started May 21 02:12:51 PM PDT 24
Finished May 21 02:12:55 PM PDT 24
Peak memory 217736 kb
Host smart-bc61b258-afad-430d-ab6a-a06d101ab9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754638421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2754638421
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3696395915
Short name T21
Test name
Test status
Simulation time 98949307 ps
CPU time 0.73 seconds
Started May 21 02:12:40 PM PDT 24
Finished May 21 02:12:46 PM PDT 24
Peak memory 200248 kb
Host smart-8d00c6be-57fa-46e7-86d9-b5545ed00709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696395915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3696395915
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.843438923
Short name T499
Test name
Test status
Simulation time 887029023 ps
CPU time 4.64 seconds
Started May 21 02:12:42 PM PDT 24
Finished May 21 02:12:51 PM PDT 24
Peak memory 200604 kb
Host smart-1d613c1e-1761-46cd-a254-12ea3e4446e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843438923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.843438923
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3794433649
Short name T350
Test name
Test status
Simulation time 103246311 ps
CPU time 1.02 seconds
Started May 21 02:12:42 PM PDT 24
Finished May 21 02:12:48 PM PDT 24
Peak memory 200492 kb
Host smart-224421ef-e673-4f28-b449-05010c145295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794433649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3794433649
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.940199285
Short name T333
Test name
Test status
Simulation time 115664236 ps
CPU time 1.19 seconds
Started May 21 02:12:40 PM PDT 24
Finished May 21 02:12:47 PM PDT 24
Peak memory 200668 kb
Host smart-1be8451a-9455-419b-ae90-1a8a5eb4b1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940199285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.940199285
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2611898646
Short name T1
Test name
Test status
Simulation time 6829886837 ps
CPU time 24.07 seconds
Started May 21 02:12:49 PM PDT 24
Finished May 21 02:13:16 PM PDT 24
Peak memory 200832 kb
Host smart-f49c35d0-6032-4d78-9d0b-06c389633728
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611898646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2611898646
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3504147382
Short name T455
Test name
Test status
Simulation time 495237558 ps
CPU time 2.54 seconds
Started May 21 02:12:41 PM PDT 24
Finished May 21 02:12:49 PM PDT 24
Peak memory 200480 kb
Host smart-a1d351df-fb68-4b62-90f0-e105f3a87a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504147382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3504147382
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2297929615
Short name T224
Test name
Test status
Simulation time 132453906 ps
CPU time 1.04 seconds
Started May 21 02:12:42 PM PDT 24
Finished May 21 02:12:48 PM PDT 24
Peak memory 200532 kb
Host smart-8462b55b-5cb9-4a36-afd4-fde0c5383d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297929615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2297929615
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3943743585
Short name T431
Test name
Test status
Simulation time 79952818 ps
CPU time 0.8 seconds
Started May 21 02:12:50 PM PDT 24
Finished May 21 02:12:54 PM PDT 24
Peak memory 200336 kb
Host smart-a220df4e-c891-4e08-b4b1-17e5c554d841
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943743585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3943743585
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.996218054
Short name T322
Test name
Test status
Simulation time 1897011550 ps
CPU time 7.26 seconds
Started May 21 02:12:51 PM PDT 24
Finished May 21 02:13:02 PM PDT 24
Peak memory 217620 kb
Host smart-af6a0d05-47c1-4f42-b7b1-fc8f893c69c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996218054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.996218054
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2425066873
Short name T228
Test name
Test status
Simulation time 244067467 ps
CPU time 1.13 seconds
Started May 21 02:12:48 PM PDT 24
Finished May 21 02:12:52 PM PDT 24
Peak memory 217604 kb
Host smart-9dc06e38-45cb-48fd-ba5c-036e8e7002cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425066873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2425066873
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2537798364
Short name T386
Test name
Test status
Simulation time 150648158 ps
CPU time 0.86 seconds
Started May 21 02:12:47 PM PDT 24
Finished May 21 02:12:51 PM PDT 24
Peak memory 200284 kb
Host smart-13fabf42-05c5-454d-846c-aff1d910a126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537798364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2537798364
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3104558627
Short name T422
Test name
Test status
Simulation time 821447730 ps
CPU time 4.07 seconds
Started May 21 02:12:46 PM PDT 24
Finished May 21 02:12:54 PM PDT 24
Peak memory 200720 kb
Host smart-8d15bbe1-47f2-4d89-bb14-a73dba995312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104558627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3104558627
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.569373239
Short name T354
Test name
Test status
Simulation time 107326891 ps
CPU time 1.02 seconds
Started May 21 02:12:52 PM PDT 24
Finished May 21 02:12:56 PM PDT 24
Peak memory 200504 kb
Host smart-43abd62d-5c8f-494a-bbf9-24b2d7a784e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569373239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.569373239
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.826009075
Short name T187
Test name
Test status
Simulation time 241608772 ps
CPU time 1.46 seconds
Started May 21 02:12:47 PM PDT 24
Finished May 21 02:12:52 PM PDT 24
Peak memory 200716 kb
Host smart-42ffe882-7603-4567-99dd-ea63e1da3e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826009075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.826009075
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.2346564732
Short name T28
Test name
Test status
Simulation time 6277909833 ps
CPU time 28.69 seconds
Started May 21 02:12:49 PM PDT 24
Finished May 21 02:13:21 PM PDT 24
Peak memory 209060 kb
Host smart-d09cf5cf-c4a8-4fbd-afa6-3ced21a58591
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346564732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2346564732
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.3478906733
Short name T152
Test name
Test status
Simulation time 337543407 ps
CPU time 2.27 seconds
Started May 21 02:12:52 PM PDT 24
Finished May 21 02:12:57 PM PDT 24
Peak memory 200472 kb
Host smart-b2291fcd-73ae-44aa-8176-c8f855f0baf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478906733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3478906733
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.881719645
Short name T177
Test name
Test status
Simulation time 198781342 ps
CPU time 1.38 seconds
Started May 21 02:12:50 PM PDT 24
Finished May 21 02:12:55 PM PDT 24
Peak memory 200540 kb
Host smart-aa492cef-fe6f-43c3-84a5-680a6b6708ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881719645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.881719645
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2023969792
Short name T475
Test name
Test status
Simulation time 83984634 ps
CPU time 0.83 seconds
Started May 21 02:12:49 PM PDT 24
Finished May 21 02:12:53 PM PDT 24
Peak memory 200336 kb
Host smart-63692144-e0ab-4c13-a623-0c005e8865e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023969792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2023969792
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.378761531
Short name T40
Test name
Test status
Simulation time 1872217866 ps
CPU time 7.02 seconds
Started May 21 02:12:50 PM PDT 24
Finished May 21 02:13:00 PM PDT 24
Peak memory 222140 kb
Host smart-2bbf45b9-2d08-46b0-b057-d21c6c702282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378761531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.378761531
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.671990987
Short name T349
Test name
Test status
Simulation time 244576780 ps
CPU time 1.13 seconds
Started May 21 02:12:50 PM PDT 24
Finished May 21 02:12:54 PM PDT 24
Peak memory 217680 kb
Host smart-81034704-dbe0-4ecb-918f-5471ad4150a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671990987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.671990987
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.955049221
Short name T19
Test name
Test status
Simulation time 115000033 ps
CPU time 0.78 seconds
Started May 21 02:12:51 PM PDT 24
Finished May 21 02:12:55 PM PDT 24
Peak memory 200328 kb
Host smart-62374316-1c0e-46e8-b428-8cd72fbf1e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955049221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.955049221
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1400532152
Short name T70
Test name
Test status
Simulation time 1784504111 ps
CPU time 7.32 seconds
Started May 21 02:12:51 PM PDT 24
Finished May 21 02:13:02 PM PDT 24
Peak memory 200680 kb
Host smart-b8a8b1d6-5d21-410c-a4e6-b3c8b593de1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400532152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1400532152
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3749888163
Short name T168
Test name
Test status
Simulation time 147071003 ps
CPU time 1.08 seconds
Started May 21 02:12:47 PM PDT 24
Finished May 21 02:12:51 PM PDT 24
Peak memory 200476 kb
Host smart-8b04e90a-8eb1-4eb1-8628-dc1b9b0a26b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749888163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3749888163
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.2460792926
Short name T81
Test name
Test status
Simulation time 230743166 ps
CPU time 1.49 seconds
Started May 21 02:12:49 PM PDT 24
Finished May 21 02:12:54 PM PDT 24
Peak memory 200704 kb
Host smart-7a4703e9-7656-44b3-9a4d-4d99e710247b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460792926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2460792926
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2239684538
Short name T150
Test name
Test status
Simulation time 1747036432 ps
CPU time 8.67 seconds
Started May 21 02:12:50 PM PDT 24
Finished May 21 02:13:02 PM PDT 24
Peak memory 200700 kb
Host smart-9b5f1ec1-462a-4b40-ac25-6f8e4299ca7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239684538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2239684538
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.175313063
Short name T362
Test name
Test status
Simulation time 455116837 ps
CPU time 2.44 seconds
Started May 21 02:12:48 PM PDT 24
Finished May 21 02:12:54 PM PDT 24
Peak memory 200432 kb
Host smart-d9d792a0-e544-4bd0-bdbd-07589aedfd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175313063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.175313063
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1520441076
Short name T34
Test name
Test status
Simulation time 126190558 ps
CPU time 1.03 seconds
Started May 21 02:12:47 PM PDT 24
Finished May 21 02:12:51 PM PDT 24
Peak memory 200436 kb
Host smart-6cb95f38-c0f8-4ef2-ba2e-5b96142f26ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520441076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1520441076
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2314688578
Short name T518
Test name
Test status
Simulation time 79285404 ps
CPU time 0.79 seconds
Started May 21 02:12:54 PM PDT 24
Finished May 21 02:12:58 PM PDT 24
Peak memory 200352 kb
Host smart-490640b4-838b-4434-94e0-b30d50cd94bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314688578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2314688578
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2135650647
Short name T330
Test name
Test status
Simulation time 1889627218 ps
CPU time 7.28 seconds
Started May 21 02:12:56 PM PDT 24
Finished May 21 02:13:06 PM PDT 24
Peak memory 217120 kb
Host smart-db08ff1c-bfb4-4947-b769-a9664f8cbbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135650647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2135650647
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1578147343
Short name T77
Test name
Test status
Simulation time 244205324 ps
CPU time 1.18 seconds
Started May 21 02:12:56 PM PDT 24
Finished May 21 02:13:00 PM PDT 24
Peak memory 217736 kb
Host smart-b20b4a96-87e2-4820-9172-a889c5032778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578147343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1578147343
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3472059411
Short name T183
Test name
Test status
Simulation time 108730080 ps
CPU time 0.86 seconds
Started May 21 02:12:48 PM PDT 24
Finished May 21 02:12:53 PM PDT 24
Peak memory 200284 kb
Host smart-70d7cc6b-49cf-45eb-9c53-2862a6d3d86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472059411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3472059411
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2702207308
Short name T462
Test name
Test status
Simulation time 1343296740 ps
CPU time 5.53 seconds
Started May 21 02:12:48 PM PDT 24
Finished May 21 02:12:57 PM PDT 24
Peak memory 200660 kb
Host smart-12c1cb9d-04ec-448c-a4a9-eb526fdaea76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702207308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2702207308
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.290119136
Short name T484
Test name
Test status
Simulation time 172523273 ps
CPU time 1.23 seconds
Started May 21 02:12:48 PM PDT 24
Finished May 21 02:12:53 PM PDT 24
Peak memory 200504 kb
Host smart-cb87eef6-8dad-4dfe-96d0-8c05dacc3f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290119136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.290119136
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.394385586
Short name T396
Test name
Test status
Simulation time 202457935 ps
CPU time 1.45 seconds
Started May 21 02:12:49 PM PDT 24
Finished May 21 02:12:53 PM PDT 24
Peak memory 200708 kb
Host smart-e35305ef-72a2-49bc-ab9c-fc90726ff7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394385586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.394385586
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3595277140
Short name T248
Test name
Test status
Simulation time 4856235000 ps
CPU time 20.35 seconds
Started May 21 02:12:53 PM PDT 24
Finished May 21 02:13:16 PM PDT 24
Peak memory 209048 kb
Host smart-b9319210-0c5c-48ab-9cca-04716e321cab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595277140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3595277140
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.124043578
Short name T402
Test name
Test status
Simulation time 368902077 ps
CPU time 2.44 seconds
Started May 21 02:12:50 PM PDT 24
Finished May 21 02:12:56 PM PDT 24
Peak memory 200456 kb
Host smart-d65faf2b-bf12-4c3a-92f2-03185221da82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124043578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.124043578
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3079366214
Short name T143
Test name
Test status
Simulation time 235944265 ps
CPU time 1.38 seconds
Started May 21 02:12:48 PM PDT 24
Finished May 21 02:12:52 PM PDT 24
Peak memory 200416 kb
Host smart-78bec4ee-9fd9-45e0-984f-214f6175902c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079366214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3079366214
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2576130038
Short name T449
Test name
Test status
Simulation time 60654537 ps
CPU time 0.81 seconds
Started May 21 02:12:18 PM PDT 24
Finished May 21 02:12:22 PM PDT 24
Peak memory 200264 kb
Host smart-5203a8eb-48c2-4764-8f0e-b1d4e79bcdb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576130038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2576130038
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.1064813331
Short name T387
Test name
Test status
Simulation time 1903496732 ps
CPU time 7.25 seconds
Started May 21 02:12:19 PM PDT 24
Finished May 21 02:12:30 PM PDT 24
Peak memory 217196 kb
Host smart-493844dc-7d06-4862-bb46-489462c65b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064813331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.1064813331
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1444883678
Short name T471
Test name
Test status
Simulation time 247914169 ps
CPU time 1.06 seconds
Started May 21 02:12:17 PM PDT 24
Finished May 21 02:12:21 PM PDT 24
Peak memory 217672 kb
Host smart-0ac257af-0695-4866-963f-19da07701e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444883678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1444883678
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.4163273809
Short name T185
Test name
Test status
Simulation time 116199758 ps
CPU time 0.88 seconds
Started May 21 02:12:21 PM PDT 24
Finished May 21 02:12:25 PM PDT 24
Peak memory 200340 kb
Host smart-0966fdc4-273c-4122-8cf7-db31e9327c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163273809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.4163273809
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.23290814
Short name T319
Test name
Test status
Simulation time 786696069 ps
CPU time 4.75 seconds
Started May 21 02:12:17 PM PDT 24
Finished May 21 02:12:25 PM PDT 24
Peak memory 200752 kb
Host smart-ee2f5322-928b-40d9-891e-2ba77b962538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23290814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.23290814
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.3144251544
Short name T63
Test name
Test status
Simulation time 17574539622 ps
CPU time 26.15 seconds
Started May 21 02:12:19 PM PDT 24
Finished May 21 02:12:48 PM PDT 24
Peak memory 217492 kb
Host smart-fb8438ef-7158-48e3-b25b-7254f82b5625
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144251544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3144251544
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1527419875
Short name T72
Test name
Test status
Simulation time 101321403 ps
CPU time 1 seconds
Started May 21 02:12:18 PM PDT 24
Finished May 21 02:12:23 PM PDT 24
Peak memory 200428 kb
Host smart-0bafd321-89ac-4cf8-8763-a96cfabb7b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527419875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1527419875
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.2306597512
Short name T414
Test name
Test status
Simulation time 256125251 ps
CPU time 1.54 seconds
Started May 21 02:12:18 PM PDT 24
Finished May 21 02:12:23 PM PDT 24
Peak memory 200596 kb
Host smart-03782aa6-aa1c-4b42-b695-ac6826f24310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306597512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2306597512
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1018969901
Short name T516
Test name
Test status
Simulation time 4915909838 ps
CPU time 22.53 seconds
Started May 21 02:12:17 PM PDT 24
Finished May 21 02:12:43 PM PDT 24
Peak memory 209004 kb
Host smart-f68a95c4-c3c1-4845-9f26-1e96819330da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018969901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1018969901
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.209634824
Short name T181
Test name
Test status
Simulation time 448740873 ps
CPU time 2.51 seconds
Started May 21 02:12:19 PM PDT 24
Finished May 21 02:12:25 PM PDT 24
Peak memory 200516 kb
Host smart-bc49cbca-2598-48ad-961a-af440936aff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209634824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.209634824
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1804780842
Short name T528
Test name
Test status
Simulation time 111982483 ps
CPU time 0.91 seconds
Started May 21 02:12:20 PM PDT 24
Finished May 21 02:12:24 PM PDT 24
Peak memory 200676 kb
Host smart-926490aa-521e-46eb-83f7-020de6f0d811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804780842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1804780842
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1656153326
Short name T487
Test name
Test status
Simulation time 72695201 ps
CPU time 0.83 seconds
Started May 21 02:12:55 PM PDT 24
Finished May 21 02:12:59 PM PDT 24
Peak memory 200308 kb
Host smart-63b7be30-2c7b-46f5-8ceb-857118425f2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656153326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1656153326
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2963372118
Short name T45
Test name
Test status
Simulation time 2361056498 ps
CPU time 8.5 seconds
Started May 21 02:12:59 PM PDT 24
Finished May 21 02:13:11 PM PDT 24
Peak memory 218264 kb
Host smart-5d4c7790-3b99-42df-aa9c-02fe3108d5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963372118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2963372118
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.961708394
Short name T519
Test name
Test status
Simulation time 243986276 ps
CPU time 1.05 seconds
Started May 21 02:12:57 PM PDT 24
Finished May 21 02:13:01 PM PDT 24
Peak memory 217500 kb
Host smart-f3251500-e382-47d9-ad48-71149839cdcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961708394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.961708394
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3920734813
Short name T446
Test name
Test status
Simulation time 205416856 ps
CPU time 0.9 seconds
Started May 21 02:12:53 PM PDT 24
Finished May 21 02:12:56 PM PDT 24
Peak memory 200280 kb
Host smart-52c92d50-c2bc-44db-9aa3-893f98302d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920734813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3920734813
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.172456596
Short name T261
Test name
Test status
Simulation time 1450300015 ps
CPU time 5.55 seconds
Started May 21 02:12:59 PM PDT 24
Finished May 21 02:13:08 PM PDT 24
Peak memory 200688 kb
Host smart-a70321f0-faa2-40a4-a36e-492b7c8339f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172456596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.172456596
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3233766813
Short name T154
Test name
Test status
Simulation time 179232181 ps
CPU time 1.19 seconds
Started May 21 02:13:00 PM PDT 24
Finished May 21 02:13:04 PM PDT 24
Peak memory 200416 kb
Host smart-2dfcf36b-ec03-4656-87e3-47323cd206ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233766813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3233766813
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.113910562
Short name T259
Test name
Test status
Simulation time 118816482 ps
CPU time 1.28 seconds
Started May 21 02:13:00 PM PDT 24
Finished May 21 02:13:04 PM PDT 24
Peak memory 200652 kb
Host smart-ea12b4c3-8c81-4ed8-8de6-f9b96a422ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113910562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.113910562
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3265490274
Short name T90
Test name
Test status
Simulation time 4839269693 ps
CPU time 21.74 seconds
Started May 21 02:12:57 PM PDT 24
Finished May 21 02:13:21 PM PDT 24
Peak memory 208936 kb
Host smart-e5ffcf0e-bab7-4b15-8db0-32fab902e9e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265490274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3265490274
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2405721748
Short name T141
Test name
Test status
Simulation time 153526928 ps
CPU time 1.86 seconds
Started May 21 02:12:57 PM PDT 24
Finished May 21 02:13:02 PM PDT 24
Peak memory 200452 kb
Host smart-45545ce2-4efc-4e0c-86ad-0c6437c915c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405721748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2405721748
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1981401031
Short name T378
Test name
Test status
Simulation time 79984937 ps
CPU time 0.78 seconds
Started May 21 02:12:59 PM PDT 24
Finished May 21 02:13:03 PM PDT 24
Peak memory 200416 kb
Host smart-8991e91e-f329-4b1c-b621-c944a06c76ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981401031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1981401031
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2589258608
Short name T133
Test name
Test status
Simulation time 60488907 ps
CPU time 0.76 seconds
Started May 21 02:12:54 PM PDT 24
Finished May 21 02:12:58 PM PDT 24
Peak memory 200332 kb
Host smart-dda61cd4-4173-45a8-9d3c-4ee243c64486
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589258608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2589258608
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.165555034
Short name T30
Test name
Test status
Simulation time 1228536598 ps
CPU time 5.77 seconds
Started May 21 02:12:55 PM PDT 24
Finished May 21 02:13:04 PM PDT 24
Peak memory 218152 kb
Host smart-4bbde2f1-f426-48f2-9e3f-2be9e2498f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165555034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.165555034
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2843274535
Short name T361
Test name
Test status
Simulation time 244606764 ps
CPU time 1.08 seconds
Started May 21 02:12:57 PM PDT 24
Finished May 21 02:13:01 PM PDT 24
Peak memory 217764 kb
Host smart-8e1e40ac-43d2-43fd-bfb7-467670e9a310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843274535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2843274535
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1311999428
Short name T311
Test name
Test status
Simulation time 213452571 ps
CPU time 0.93 seconds
Started May 21 02:12:54 PM PDT 24
Finished May 21 02:12:58 PM PDT 24
Peak memory 200288 kb
Host smart-0b9db8fb-8647-4ace-b1a3-d45cd3fb8aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311999428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1311999428
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3831936339
Short name T522
Test name
Test status
Simulation time 1933708123 ps
CPU time 7.71 seconds
Started May 21 02:12:54 PM PDT 24
Finished May 21 02:13:05 PM PDT 24
Peak memory 200648 kb
Host smart-9f50c8fa-12cf-4de4-987b-407707fa7e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831936339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3831936339
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.189307832
Short name T509
Test name
Test status
Simulation time 171201878 ps
CPU time 1.19 seconds
Started May 21 02:12:57 PM PDT 24
Finished May 21 02:13:01 PM PDT 24
Peak memory 200480 kb
Host smart-c5d253b4-8f63-4d7f-a3b3-45342d4e07eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189307832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.189307832
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.285716431
Short name T459
Test name
Test status
Simulation time 105939554 ps
CPU time 1.17 seconds
Started May 21 02:12:57 PM PDT 24
Finished May 21 02:13:01 PM PDT 24
Peak memory 200656 kb
Host smart-12e41f24-fb32-4ca2-ba86-290eab384f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285716431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.285716431
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1158053976
Short name T286
Test name
Test status
Simulation time 3032106242 ps
CPU time 10.84 seconds
Started May 21 02:12:55 PM PDT 24
Finished May 21 02:13:09 PM PDT 24
Peak memory 209064 kb
Host smart-2d47841c-2a93-4941-aa90-9e3e4acb9cff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158053976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1158053976
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2833816519
Short name T205
Test name
Test status
Simulation time 148858527 ps
CPU time 1.9 seconds
Started May 21 02:12:55 PM PDT 24
Finished May 21 02:13:00 PM PDT 24
Peak memory 200476 kb
Host smart-6784e5e7-613a-49d2-8972-20bb31adc7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833816519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2833816519
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.163502560
Short name T161
Test name
Test status
Simulation time 241439716 ps
CPU time 1.37 seconds
Started May 21 02:13:00 PM PDT 24
Finished May 21 02:13:04 PM PDT 24
Peak memory 200412 kb
Host smart-ea3d371e-52ea-4294-bd87-4c505aeadb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163502560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.163502560
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1260235139
Short name T473
Test name
Test status
Simulation time 76158332 ps
CPU time 0.81 seconds
Started May 21 02:12:59 PM PDT 24
Finished May 21 02:13:02 PM PDT 24
Peak memory 200336 kb
Host smart-b9c5993f-7e3b-4a34-a8ae-15ac4681092e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260235139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1260235139
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2542326636
Short name T39
Test name
Test status
Simulation time 1222795150 ps
CPU time 5.97 seconds
Started May 21 02:13:01 PM PDT 24
Finished May 21 02:13:11 PM PDT 24
Peak memory 217608 kb
Host smart-af6adf18-b09f-4071-b00d-dad20dc1b060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542326636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2542326636
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2282149781
Short name T257
Test name
Test status
Simulation time 244232740 ps
CPU time 1.24 seconds
Started May 21 02:12:59 PM PDT 24
Finished May 21 02:13:03 PM PDT 24
Peak memory 217604 kb
Host smart-7365a886-ad42-4f60-982c-1cbb1caf9a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282149781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2282149781
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2764411840
Short name T267
Test name
Test status
Simulation time 81403221 ps
CPU time 0.78 seconds
Started May 21 02:13:03 PM PDT 24
Finished May 21 02:13:08 PM PDT 24
Peak memory 200304 kb
Host smart-e0e4203d-a866-487b-825f-41a8458ca1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764411840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2764411840
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3154600242
Short name T302
Test name
Test status
Simulation time 661326926 ps
CPU time 3.87 seconds
Started May 21 02:12:53 PM PDT 24
Finished May 21 02:13:00 PM PDT 24
Peak memory 200684 kb
Host smart-2a12ad15-744b-4ba8-9b48-702323d89d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154600242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3154600242
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2409986095
Short name T247
Test name
Test status
Simulation time 147904152 ps
CPU time 1.15 seconds
Started May 21 02:13:00 PM PDT 24
Finished May 21 02:13:05 PM PDT 24
Peak memory 200444 kb
Host smart-70694faa-e3c4-49ed-8a2b-b5c1df69a036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409986095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2409986095
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.262144281
Short name T266
Test name
Test status
Simulation time 118328394 ps
CPU time 1.22 seconds
Started May 21 02:12:57 PM PDT 24
Finished May 21 02:13:01 PM PDT 24
Peak memory 200696 kb
Host smart-286b1c85-15ad-4685-86fc-074b8baa15b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262144281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.262144281
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2361383345
Short name T164
Test name
Test status
Simulation time 5203494284 ps
CPU time 21 seconds
Started May 21 02:13:03 PM PDT 24
Finished May 21 02:13:28 PM PDT 24
Peak memory 209032 kb
Host smart-8a75388d-0ff2-4c10-8a89-1ad238cdb5c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361383345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2361383345
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.1048438402
Short name T254
Test name
Test status
Simulation time 130234744 ps
CPU time 1.68 seconds
Started May 21 02:12:59 PM PDT 24
Finished May 21 02:13:04 PM PDT 24
Peak memory 208680 kb
Host smart-849af431-2de8-4911-bbae-92141cb2a4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048438402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1048438402
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2109896733
Short name T299
Test name
Test status
Simulation time 142025108 ps
CPU time 1.16 seconds
Started May 21 02:13:01 PM PDT 24
Finished May 21 02:13:07 PM PDT 24
Peak memory 200436 kb
Host smart-0e7fb229-40ac-42f2-9265-4a1841c1f9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109896733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2109896733
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1533405605
Short name T306
Test name
Test status
Simulation time 74439847 ps
CPU time 0.85 seconds
Started May 21 02:13:06 PM PDT 24
Finished May 21 02:13:12 PM PDT 24
Peak memory 200340 kb
Host smart-46a62bc0-70a2-4d37-bff3-e5445d4b22fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533405605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1533405605
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3315823654
Short name T321
Test name
Test status
Simulation time 2361917067 ps
CPU time 8.07 seconds
Started May 21 02:13:03 PM PDT 24
Finished May 21 02:13:16 PM PDT 24
Peak memory 218300 kb
Host smart-b2820b3f-a784-48d3-968f-f9ccbef41500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315823654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3315823654
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3482929421
Short name T275
Test name
Test status
Simulation time 244659477 ps
CPU time 1.14 seconds
Started May 21 02:13:03 PM PDT 24
Finished May 21 02:13:09 PM PDT 24
Peak memory 217836 kb
Host smart-fd9f1006-d28d-45ba-af2c-7e75427d6493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482929421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3482929421
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2342755425
Short name T218
Test name
Test status
Simulation time 179367170 ps
CPU time 0.89 seconds
Started May 21 02:13:01 PM PDT 24
Finished May 21 02:13:06 PM PDT 24
Peak memory 200252 kb
Host smart-7f1b0e83-ddd9-4b90-b9f0-2e89d7a8261f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342755425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2342755425
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1900215323
Short name T342
Test name
Test status
Simulation time 1500452999 ps
CPU time 5.64 seconds
Started May 21 02:13:01 PM PDT 24
Finished May 21 02:13:11 PM PDT 24
Peak memory 200600 kb
Host smart-37699739-54f1-4746-89d9-85ba1cb4b4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900215323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1900215323
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1469538666
Short name T524
Test name
Test status
Simulation time 170997319 ps
CPU time 1.19 seconds
Started May 21 02:13:03 PM PDT 24
Finished May 21 02:13:08 PM PDT 24
Peak memory 200416 kb
Host smart-384ec00c-f967-4038-864b-421d666859df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469538666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1469538666
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.3195294234
Short name T425
Test name
Test status
Simulation time 109158177 ps
CPU time 1.15 seconds
Started May 21 02:13:06 PM PDT 24
Finished May 21 02:13:13 PM PDT 24
Peak memory 200708 kb
Host smart-808e3fe1-7e02-4486-805f-09df70d8e479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195294234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3195294234
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.247988515
Short name T75
Test name
Test status
Simulation time 1969258368 ps
CPU time 8.2 seconds
Started May 21 02:13:04 PM PDT 24
Finished May 21 02:13:17 PM PDT 24
Peak memory 216948 kb
Host smart-346c58e1-c55f-4631-99d0-48889f302682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247988515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.247988515
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2556501234
Short name T184
Test name
Test status
Simulation time 121063742 ps
CPU time 1.57 seconds
Started May 21 02:13:03 PM PDT 24
Finished May 21 02:13:09 PM PDT 24
Peak memory 200544 kb
Host smart-73301862-a2bd-49e9-a07b-f19b09a55694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556501234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2556501234
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1815848287
Short name T159
Test name
Test status
Simulation time 117521986 ps
CPU time 1.06 seconds
Started May 21 02:13:00 PM PDT 24
Finished May 21 02:13:04 PM PDT 24
Peak memory 200532 kb
Host smart-36b37493-e312-4d1d-b9b1-e00a13eb9113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815848287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1815848287
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1188178703
Short name T208
Test name
Test status
Simulation time 74702944 ps
CPU time 0.78 seconds
Started May 21 02:13:07 PM PDT 24
Finished May 21 02:13:13 PM PDT 24
Peak memory 200336 kb
Host smart-c9d0c1f0-af43-43be-9c66-9af1c22291cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188178703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1188178703
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3747756929
Short name T50
Test name
Test status
Simulation time 1911882074 ps
CPU time 7.43 seconds
Started May 21 02:13:06 PM PDT 24
Finished May 21 02:13:18 PM PDT 24
Peak memory 222212 kb
Host smart-f1b39477-6c5f-4e50-ac81-1b0e65a92263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747756929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3747756929
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.944003926
Short name T441
Test name
Test status
Simulation time 244112863 ps
CPU time 1.14 seconds
Started May 21 02:13:08 PM PDT 24
Finished May 21 02:13:13 PM PDT 24
Peak memory 217592 kb
Host smart-f0f66066-b4b2-4170-ad17-7bc3dd291772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944003926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.944003926
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.463808899
Short name T329
Test name
Test status
Simulation time 191070007 ps
CPU time 0.95 seconds
Started May 21 02:13:01 PM PDT 24
Finished May 21 02:13:06 PM PDT 24
Peak memory 200220 kb
Host smart-927e143a-372d-4341-af87-f33728861357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463808899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.463808899
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.847169795
Short name T186
Test name
Test status
Simulation time 966911361 ps
CPU time 5.17 seconds
Started May 21 02:13:02 PM PDT 24
Finished May 21 02:13:11 PM PDT 24
Peak memory 200696 kb
Host smart-f94340f4-45d5-496f-ba31-d1674d811319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847169795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.847169795
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.469055813
Short name T132
Test name
Test status
Simulation time 162065110 ps
CPU time 1.22 seconds
Started May 21 02:13:08 PM PDT 24
Finished May 21 02:13:14 PM PDT 24
Peak memory 200524 kb
Host smart-d7565830-4694-45b1-9667-432f601e1a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469055813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.469055813
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2855771376
Short name T448
Test name
Test status
Simulation time 118315621 ps
CPU time 1.24 seconds
Started May 21 02:13:06 PM PDT 24
Finished May 21 02:13:13 PM PDT 24
Peak memory 200708 kb
Host smart-0db97bac-6291-411e-9939-fc5bde49d33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855771376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2855771376
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3866494699
Short name T430
Test name
Test status
Simulation time 9741694140 ps
CPU time 34.74 seconds
Started May 21 02:13:07 PM PDT 24
Finished May 21 02:13:47 PM PDT 24
Peak memory 209036 kb
Host smart-2a4ab427-10fe-4fdc-857e-afbb6ab066e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866494699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3866494699
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.3848573400
Short name T270
Test name
Test status
Simulation time 133029613 ps
CPU time 1.97 seconds
Started May 21 02:13:06 PM PDT 24
Finished May 21 02:13:13 PM PDT 24
Peak memory 208660 kb
Host smart-da8ba8dd-6a94-4c47-aeb7-87c3292e3fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848573400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.3848573400
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3084081718
Short name T353
Test name
Test status
Simulation time 113446095 ps
CPU time 1.04 seconds
Started May 21 02:13:11 PM PDT 24
Finished May 21 02:13:18 PM PDT 24
Peak memory 200472 kb
Host smart-31f56c50-7414-4fbc-92ad-3abbdd5df0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084081718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3084081718
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3685108044
Short name T472
Test name
Test status
Simulation time 79021562 ps
CPU time 0.8 seconds
Started May 21 02:13:08 PM PDT 24
Finished May 21 02:13:13 PM PDT 24
Peak memory 200256 kb
Host smart-dc6fe7b0-e6a7-4d4d-8137-5b69809a17be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685108044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3685108044
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.130862748
Short name T42
Test name
Test status
Simulation time 2152595558 ps
CPU time 7.71 seconds
Started May 21 02:13:09 PM PDT 24
Finished May 21 02:13:22 PM PDT 24
Peak memory 217752 kb
Host smart-b9d95ffb-802e-4695-944e-59a38d66bfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130862748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.130862748
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3853869126
Short name T281
Test name
Test status
Simulation time 244402908 ps
CPU time 1.09 seconds
Started May 21 02:13:08 PM PDT 24
Finished May 21 02:13:13 PM PDT 24
Peak memory 217592 kb
Host smart-8871c5db-5d9c-42b6-8648-f76aec7464f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853869126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3853869126
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1685052902
Short name T346
Test name
Test status
Simulation time 129288111 ps
CPU time 0.87 seconds
Started May 21 02:13:12 PM PDT 24
Finished May 21 02:13:18 PM PDT 24
Peak memory 200300 kb
Host smart-645cc7c8-9bf8-4cf7-af3b-028791ae208a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685052902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1685052902
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.734235809
Short name T390
Test name
Test status
Simulation time 967497739 ps
CPU time 5.02 seconds
Started May 21 02:13:06 PM PDT 24
Finished May 21 02:13:16 PM PDT 24
Peak memory 200696 kb
Host smart-ef754fec-1513-4760-b08c-c819bff0d4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734235809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.734235809
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2802830311
Short name T433
Test name
Test status
Simulation time 107239308 ps
CPU time 1 seconds
Started May 21 02:13:13 PM PDT 24
Finished May 21 02:13:19 PM PDT 24
Peak memory 200492 kb
Host smart-62bcee1d-967e-40e2-9b88-1dc569317ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802830311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2802830311
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2428448122
Short name T225
Test name
Test status
Simulation time 120123941 ps
CPU time 1.26 seconds
Started May 21 02:13:06 PM PDT 24
Finished May 21 02:13:13 PM PDT 24
Peak memory 200716 kb
Host smart-f3c83320-f4ab-47a8-a033-a5fe2faf9cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428448122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2428448122
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.4179497166
Short name T288
Test name
Test status
Simulation time 11358654774 ps
CPU time 40.47 seconds
Started May 21 02:13:09 PM PDT 24
Finished May 21 02:13:55 PM PDT 24
Peak memory 209024 kb
Host smart-ab00f41b-bc87-4653-a06d-90857176b034
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179497166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.4179497166
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3088442412
Short name T508
Test name
Test status
Simulation time 378955366 ps
CPU time 2.57 seconds
Started May 21 02:13:06 PM PDT 24
Finished May 21 02:13:14 PM PDT 24
Peak memory 200404 kb
Host smart-57244236-9929-459f-b4a2-5f8c3b263a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088442412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3088442412
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1430877798
Short name T491
Test name
Test status
Simulation time 109166411 ps
CPU time 0.96 seconds
Started May 21 02:13:13 PM PDT 24
Finished May 21 02:13:19 PM PDT 24
Peak memory 200492 kb
Host smart-5c63ccb1-4f6a-4197-96ec-0854e4a60145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430877798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1430877798
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2096181579
Short name T490
Test name
Test status
Simulation time 66118664 ps
CPU time 0.81 seconds
Started May 21 02:13:17 PM PDT 24
Finished May 21 02:13:22 PM PDT 24
Peak memory 200332 kb
Host smart-a18e61f0-c740-428b-8c7c-e78a8ee3a580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096181579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2096181579
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.3457073362
Short name T379
Test name
Test status
Simulation time 1239999986 ps
CPU time 5.56 seconds
Started May 21 02:13:06 PM PDT 24
Finished May 21 02:13:17 PM PDT 24
Peak memory 222220 kb
Host smart-112266f2-6496-4a0b-8bad-a5ea06f82942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457073362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3457073362
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3376261876
Short name T494
Test name
Test status
Simulation time 243489695 ps
CPU time 1.2 seconds
Started May 21 02:13:07 PM PDT 24
Finished May 21 02:13:14 PM PDT 24
Peak memory 217764 kb
Host smart-ddb5e98d-80a4-4b4a-8364-551a77bd8433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376261876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3376261876
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.724659624
Short name T292
Test name
Test status
Simulation time 196816995 ps
CPU time 0.9 seconds
Started May 21 02:13:13 PM PDT 24
Finished May 21 02:13:20 PM PDT 24
Peak memory 200316 kb
Host smart-b5403ac0-85e6-4ec3-841f-b4d86f0687ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724659624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.724659624
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3833179779
Short name T6
Test name
Test status
Simulation time 1298698390 ps
CPU time 5.27 seconds
Started May 21 02:13:08 PM PDT 24
Finished May 21 02:13:17 PM PDT 24
Peak memory 200712 kb
Host smart-e8f38305-2bb4-4f6f-9d70-8a867a84741a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833179779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3833179779
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2089766094
Short name T276
Test name
Test status
Simulation time 170784739 ps
CPU time 1.19 seconds
Started May 21 02:13:13 PM PDT 24
Finished May 21 02:13:19 PM PDT 24
Peak memory 200512 kb
Host smart-aed4424a-9875-4246-9450-70efbbaede27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089766094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2089766094
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.487111163
Short name T204
Test name
Test status
Simulation time 234488230 ps
CPU time 1.51 seconds
Started May 21 02:13:08 PM PDT 24
Finished May 21 02:13:14 PM PDT 24
Peak memory 200748 kb
Host smart-51beeb12-b7e8-491c-a5f4-8b96c544c09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487111163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.487111163
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.996047716
Short name T368
Test name
Test status
Simulation time 1363495107 ps
CPU time 6.86 seconds
Started May 21 02:13:17 PM PDT 24
Finished May 21 02:13:29 PM PDT 24
Peak memory 200652 kb
Host smart-6235b276-4a01-4d7d-abb2-38663e6db275
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996047716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.996047716
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.1614971488
Short name T157
Test name
Test status
Simulation time 119107805 ps
CPU time 1.43 seconds
Started May 21 02:13:08 PM PDT 24
Finished May 21 02:13:14 PM PDT 24
Peak memory 200496 kb
Host smart-c380f752-db27-4c8e-969b-be47738ddbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614971488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.1614971488
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.1970957022
Short name T413
Test name
Test status
Simulation time 164945314 ps
CPU time 1.28 seconds
Started May 21 02:13:07 PM PDT 24
Finished May 21 02:13:13 PM PDT 24
Peak memory 200616 kb
Host smart-12ead601-6d4f-4896-bf6d-9ae3c47bc742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970957022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1970957022
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2610275972
Short name T201
Test name
Test status
Simulation time 73688118 ps
CPU time 0.88 seconds
Started May 21 02:13:20 PM PDT 24
Finished May 21 02:13:26 PM PDT 24
Peak memory 200276 kb
Host smart-5ab9cb03-3336-43d0-8607-b076ba5bbd53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610275972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2610275972
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3568940880
Short name T47
Test name
Test status
Simulation time 1227422948 ps
CPU time 5.41 seconds
Started May 21 02:13:17 PM PDT 24
Finished May 21 02:13:28 PM PDT 24
Peak memory 222220 kb
Host smart-63d6e5e2-4cf6-4b41-aa50-084d98f5ddce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568940880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3568940880
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1084360156
Short name T393
Test name
Test status
Simulation time 244815099 ps
CPU time 1.12 seconds
Started May 21 02:13:18 PM PDT 24
Finished May 21 02:13:24 PM PDT 24
Peak memory 217580 kb
Host smart-16f221b1-f365-456d-b029-3fc27c2f3172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084360156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1084360156
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2570704410
Short name T538
Test name
Test status
Simulation time 195569773 ps
CPU time 0.93 seconds
Started May 21 02:13:18 PM PDT 24
Finished May 21 02:13:25 PM PDT 24
Peak memory 200284 kb
Host smart-6c2d7df7-cb77-4de1-b4b0-cc7ced3d045b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570704410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2570704410
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2133971807
Short name T146
Test name
Test status
Simulation time 1309368543 ps
CPU time 5.34 seconds
Started May 21 02:13:18 PM PDT 24
Finished May 21 02:13:28 PM PDT 24
Peak memory 200676 kb
Host smart-371ab3a0-3902-4df4-a2d3-aad016b20f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133971807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2133971807
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1344788306
Short name T504
Test name
Test status
Simulation time 182987882 ps
CPU time 1.18 seconds
Started May 21 02:13:17 PM PDT 24
Finished May 21 02:13:24 PM PDT 24
Peak memory 200520 kb
Host smart-c09db479-ac4e-4878-b1c5-a0ab7b14b8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344788306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1344788306
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.553019891
Short name T360
Test name
Test status
Simulation time 115081414 ps
CPU time 1.16 seconds
Started May 21 02:13:14 PM PDT 24
Finished May 21 02:13:21 PM PDT 24
Peak memory 200648 kb
Host smart-2d8d688f-a9b6-4724-9e5f-b565abec7bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553019891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.553019891
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.537502085
Short name T485
Test name
Test status
Simulation time 8369188942 ps
CPU time 31.82 seconds
Started May 21 02:13:17 PM PDT 24
Finished May 21 02:13:54 PM PDT 24
Peak memory 210624 kb
Host smart-bcc8eb66-8211-454c-a25a-5ffe2dc85388
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537502085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.537502085
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2636394002
Short name T234
Test name
Test status
Simulation time 118706738 ps
CPU time 1.52 seconds
Started May 21 02:13:17 PM PDT 24
Finished May 21 02:13:23 PM PDT 24
Peak memory 200524 kb
Host smart-5d878734-e0e9-4d93-a206-73264a2a6bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636394002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2636394002
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.889005789
Short name T32
Test name
Test status
Simulation time 148415518 ps
CPU time 1.18 seconds
Started May 21 02:13:14 PM PDT 24
Finished May 21 02:13:21 PM PDT 24
Peak memory 200476 kb
Host smart-35c518d3-e733-4c2c-b075-3da902f04be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889005789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.889005789
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.189740957
Short name T500
Test name
Test status
Simulation time 78232947 ps
CPU time 0.88 seconds
Started May 21 02:13:14 PM PDT 24
Finished May 21 02:13:20 PM PDT 24
Peak memory 200328 kb
Host smart-66579d47-cf9a-4149-97d0-3dbecdbb1361
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189740957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.189740957
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3756369408
Short name T510
Test name
Test status
Simulation time 1888845867 ps
CPU time 7.85 seconds
Started May 21 02:13:17 PM PDT 24
Finished May 21 02:13:30 PM PDT 24
Peak memory 217772 kb
Host smart-7e6660b1-44c1-4140-8159-9c3c1caed438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756369408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3756369408
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2726052364
Short name T203
Test name
Test status
Simulation time 244369250 ps
CPU time 1.18 seconds
Started May 21 02:13:18 PM PDT 24
Finished May 21 02:13:24 PM PDT 24
Peak memory 217584 kb
Host smart-c2f13c37-04dc-4fac-b13c-23357f2a5745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726052364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2726052364
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2737669217
Short name T202
Test name
Test status
Simulation time 87314279 ps
CPU time 0.81 seconds
Started May 21 02:13:18 PM PDT 24
Finished May 21 02:13:23 PM PDT 24
Peak memory 200324 kb
Host smart-808540d1-510d-4f75-ba86-0e1121b9bc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737669217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2737669217
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1869945387
Short name T180
Test name
Test status
Simulation time 1030204254 ps
CPU time 4.74 seconds
Started May 21 02:13:15 PM PDT 24
Finished May 21 02:13:25 PM PDT 24
Peak memory 200660 kb
Host smart-082dc3ba-4a3d-48f1-841c-c6ef0e3516e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869945387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1869945387
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1043584409
Short name T347
Test name
Test status
Simulation time 104947876 ps
CPU time 0.96 seconds
Started May 21 02:13:20 PM PDT 24
Finished May 21 02:13:26 PM PDT 24
Peak memory 200492 kb
Host smart-42ad637e-7f64-48c5-9694-952d40ed46ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043584409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1043584409
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.56848071
Short name T476
Test name
Test status
Simulation time 190232840 ps
CPU time 1.38 seconds
Started May 21 02:13:15 PM PDT 24
Finished May 21 02:13:22 PM PDT 24
Peak memory 200624 kb
Host smart-e474b774-d109-48db-aa71-e3a42d926201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56848071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.56848071
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3289952544
Short name T80
Test name
Test status
Simulation time 2933517633 ps
CPU time 10.5 seconds
Started May 21 02:13:17 PM PDT 24
Finished May 21 02:13:32 PM PDT 24
Peak memory 216500 kb
Host smart-ebc29539-6f13-418c-a011-d2e88af95bf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289952544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3289952544
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3138594150
Short name T439
Test name
Test status
Simulation time 123783449 ps
CPU time 1.61 seconds
Started May 21 02:13:19 PM PDT 24
Finished May 21 02:13:25 PM PDT 24
Peak memory 200400 kb
Host smart-f2516419-2f86-4ce1-bdb0-a6205ed6a274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138594150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3138594150
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.207069123
Short name T385
Test name
Test status
Simulation time 149535559 ps
CPU time 1.29 seconds
Started May 21 02:13:17 PM PDT 24
Finished May 21 02:13:23 PM PDT 24
Peak memory 200676 kb
Host smart-42af17b7-8c14-4729-a73e-4ae4cf29bcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207069123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.207069123
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.782120989
Short name T229
Test name
Test status
Simulation time 71446119 ps
CPU time 0.77 seconds
Started May 21 02:13:23 PM PDT 24
Finished May 21 02:13:30 PM PDT 24
Peak memory 200300 kb
Host smart-0c734c38-21cd-47ac-8d78-e36ab2d7cd90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782120989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.782120989
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3287748960
Short name T438
Test name
Test status
Simulation time 2357050498 ps
CPU time 8.34 seconds
Started May 21 02:13:27 PM PDT 24
Finished May 21 02:13:45 PM PDT 24
Peak memory 222376 kb
Host smart-8ff8c95b-ac08-4630-bfc3-8974781f0e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287748960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3287748960
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.141495441
Short name T153
Test name
Test status
Simulation time 244328470 ps
CPU time 1.15 seconds
Started May 21 02:13:22 PM PDT 24
Finished May 21 02:13:29 PM PDT 24
Peak memory 217572 kb
Host smart-097eb1b2-d8c6-4007-81ef-be252c9c6e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141495441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.141495441
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.4046563382
Short name T263
Test name
Test status
Simulation time 148160342 ps
CPU time 0.89 seconds
Started May 21 02:13:16 PM PDT 24
Finished May 21 02:13:22 PM PDT 24
Peak memory 200300 kb
Host smart-79b0fcf6-8289-4bcb-86bc-249aa292297e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046563382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.4046563382
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.583545753
Short name T440
Test name
Test status
Simulation time 932743375 ps
CPU time 4.44 seconds
Started May 21 02:13:14 PM PDT 24
Finished May 21 02:13:24 PM PDT 24
Peak memory 200664 kb
Host smart-6e2af4e3-7697-4c99-9439-453f67f804ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583545753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.583545753
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.422010420
Short name T176
Test name
Test status
Simulation time 103272526 ps
CPU time 1.05 seconds
Started May 21 02:13:15 PM PDT 24
Finished May 21 02:13:21 PM PDT 24
Peak memory 200520 kb
Host smart-2bcad9a1-23d3-4c72-8d18-37a904aecd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422010420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.422010420
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1812469542
Short name T79
Test name
Test status
Simulation time 118956315 ps
CPU time 1.23 seconds
Started May 21 02:13:20 PM PDT 24
Finished May 21 02:13:26 PM PDT 24
Peak memory 200708 kb
Host smart-ee613547-c56f-451b-a2a6-a2db4bd3145f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812469542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1812469542
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.189394934
Short name T460
Test name
Test status
Simulation time 1087489071 ps
CPU time 5.8 seconds
Started May 21 02:13:20 PM PDT 24
Finished May 21 02:13:31 PM PDT 24
Peak memory 200724 kb
Host smart-e42977a0-33d7-4c72-aa14-2d41b284ef7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189394934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.189394934
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.360465597
Short name T280
Test name
Test status
Simulation time 524498048 ps
CPU time 2.96 seconds
Started May 21 02:13:16 PM PDT 24
Finished May 21 02:13:24 PM PDT 24
Peak memory 200492 kb
Host smart-2ffffc1e-7be7-406b-a3f4-24943ba7b114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360465597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.360465597
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3705107284
Short name T76
Test name
Test status
Simulation time 140622647 ps
CPU time 1.17 seconds
Started May 21 02:13:19 PM PDT 24
Finished May 21 02:13:25 PM PDT 24
Peak memory 200468 kb
Host smart-fa9becf4-4a53-4241-b7bf-7df0d7471da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705107284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3705107284
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3665640693
Short name T464
Test name
Test status
Simulation time 70289914 ps
CPU time 0.77 seconds
Started May 21 02:12:26 PM PDT 24
Finished May 21 02:12:29 PM PDT 24
Peak memory 200328 kb
Host smart-4cbd8170-dfe1-4588-9010-9c089266acc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665640693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3665640693
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.427674257
Short name T366
Test name
Test status
Simulation time 1220837543 ps
CPU time 5.75 seconds
Started May 21 02:12:23 PM PDT 24
Finished May 21 02:12:31 PM PDT 24
Peak memory 222136 kb
Host smart-a4ccb149-3a84-4bdf-b424-79b9eb4d2737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427674257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.427674257
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3663259397
Short name T237
Test name
Test status
Simulation time 243652729 ps
CPU time 1.08 seconds
Started May 21 02:12:26 PM PDT 24
Finished May 21 02:12:29 PM PDT 24
Peak memory 217584 kb
Host smart-b6cca887-1558-460c-9cd6-16092dc39f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663259397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3663259397
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3290111595
Short name T358
Test name
Test status
Simulation time 85951721 ps
CPU time 0.72 seconds
Started May 21 02:12:20 PM PDT 24
Finished May 21 02:12:24 PM PDT 24
Peak memory 200300 kb
Host smart-d9ff5082-27d7-4ab4-9083-d7cea7320eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290111595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3290111595
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3818066643
Short name T324
Test name
Test status
Simulation time 1342999798 ps
CPU time 5.47 seconds
Started May 21 02:12:22 PM PDT 24
Finished May 21 02:12:30 PM PDT 24
Peak memory 200708 kb
Host smart-1cbea2a3-cc36-407a-96bd-ae515c546e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818066643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3818066643
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2556880258
Short name T67
Test name
Test status
Simulation time 17322761303 ps
CPU time 24.74 seconds
Started May 21 02:12:23 PM PDT 24
Finished May 21 02:12:51 PM PDT 24
Peak memory 218584 kb
Host smart-f7a555e0-bce1-4dce-9c79-10f758cb4129
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556880258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2556880258
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2474054235
Short name T131
Test name
Test status
Simulation time 102361480 ps
CPU time 0.98 seconds
Started May 21 02:12:20 PM PDT 24
Finished May 21 02:12:24 PM PDT 24
Peak memory 200532 kb
Host smart-e75811f7-d003-4aa4-acc6-685357bfaa25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474054235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2474054235
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2090371269
Short name T13
Test name
Test status
Simulation time 119196701 ps
CPU time 1.18 seconds
Started May 21 02:12:18 PM PDT 24
Finished May 21 02:12:23 PM PDT 24
Peak memory 200632 kb
Host smart-b5e67fa4-fbb6-41ea-8eba-ea4b6ece88cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090371269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2090371269
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.388651205
Short name T128
Test name
Test status
Simulation time 1581050242 ps
CPU time 6.28 seconds
Started May 21 02:12:23 PM PDT 24
Finished May 21 02:12:32 PM PDT 24
Peak memory 200672 kb
Host smart-5df6cde0-1ce9-4553-87a1-072a08979533
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388651205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.388651205
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.903686166
Short name T252
Test name
Test status
Simulation time 331203816 ps
CPU time 2.23 seconds
Started May 21 02:12:20 PM PDT 24
Finished May 21 02:12:25 PM PDT 24
Peak memory 200668 kb
Host smart-ba70d1a8-d6ef-4ea9-bee5-299b0be0e6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903686166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.903686166
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.1831810965
Short name T199
Test name
Test status
Simulation time 82271967 ps
CPU time 0.93 seconds
Started May 21 02:12:23 PM PDT 24
Finished May 21 02:12:26 PM PDT 24
Peak memory 200500 kb
Host smart-24797c25-2c7a-45d7-abca-34b345adcd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831810965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1831810965
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3799265521
Short name T188
Test name
Test status
Simulation time 69901922 ps
CPU time 0.79 seconds
Started May 21 02:13:24 PM PDT 24
Finished May 21 02:13:32 PM PDT 24
Peak memory 200272 kb
Host smart-1cd4504c-a64a-4a0c-bf09-3cf041038ab0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799265521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3799265521
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3878632313
Short name T355
Test name
Test status
Simulation time 2189914183 ps
CPU time 8.35 seconds
Started May 21 02:13:26 PM PDT 24
Finished May 21 02:13:43 PM PDT 24
Peak memory 217792 kb
Host smart-0aec7ae2-2e75-41e5-8804-6526eedaac6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878632313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3878632313
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1413132863
Short name T532
Test name
Test status
Simulation time 243739167 ps
CPU time 1.08 seconds
Started May 21 02:13:23 PM PDT 24
Finished May 21 02:13:31 PM PDT 24
Peak memory 217652 kb
Host smart-789822eb-b661-48d5-8905-f856b5005d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413132863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1413132863
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1370893928
Short name T469
Test name
Test status
Simulation time 149786957 ps
CPU time 0.85 seconds
Started May 21 02:13:21 PM PDT 24
Finished May 21 02:13:27 PM PDT 24
Peak memory 200304 kb
Host smart-29f28994-96c4-4184-9624-3eb148260c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370893928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1370893928
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.4086662171
Short name T260
Test name
Test status
Simulation time 954544152 ps
CPU time 5.07 seconds
Started May 21 02:13:27 PM PDT 24
Finished May 21 02:13:42 PM PDT 24
Peak memory 200764 kb
Host smart-52859a36-87ca-4838-b86b-f926a43100df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086662171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.4086662171
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2517764600
Short name T428
Test name
Test status
Simulation time 94485968 ps
CPU time 0.99 seconds
Started May 21 02:13:21 PM PDT 24
Finished May 21 02:13:28 PM PDT 24
Peak memory 200452 kb
Host smart-54c7e7a4-f6ff-4080-923c-b507ee0c746c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517764600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2517764600
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.165766993
Short name T304
Test name
Test status
Simulation time 257818486 ps
CPU time 1.61 seconds
Started May 21 02:13:22 PM PDT 24
Finished May 21 02:13:30 PM PDT 24
Peak memory 200676 kb
Host smart-0b0f5b0b-19a1-4bd8-9d6f-c36486ad5d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165766993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.165766993
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.113132005
Short name T305
Test name
Test status
Simulation time 8296975603 ps
CPU time 28.91 seconds
Started May 21 02:13:28 PM PDT 24
Finished May 21 02:14:07 PM PDT 24
Peak memory 200852 kb
Host smart-e2255cc9-5391-411a-b36f-ad293ea79d4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113132005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.113132005
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.318792708
Short name T231
Test name
Test status
Simulation time 369987105 ps
CPU time 2.2 seconds
Started May 21 02:13:22 PM PDT 24
Finished May 21 02:13:31 PM PDT 24
Peak memory 208716 kb
Host smart-26723c99-3276-4294-8fb3-294ad0556df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318792708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.318792708
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2149191523
Short name T144
Test name
Test status
Simulation time 156153692 ps
CPU time 1.12 seconds
Started May 21 02:13:23 PM PDT 24
Finished May 21 02:13:31 PM PDT 24
Peak memory 200488 kb
Host smart-707f26ac-fbe8-4413-b2a5-c05e12024878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149191523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2149191523
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2668828575
Short name T170
Test name
Test status
Simulation time 60944736 ps
CPU time 0.73 seconds
Started May 21 02:13:26 PM PDT 24
Finished May 21 02:13:36 PM PDT 24
Peak memory 200308 kb
Host smart-18ca97f1-2548-477a-9f9a-f4c7a9a06bba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668828575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2668828575
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2925566462
Short name T357
Test name
Test status
Simulation time 245292716 ps
CPU time 1.04 seconds
Started May 21 02:13:23 PM PDT 24
Finished May 21 02:13:31 PM PDT 24
Peak memory 217592 kb
Host smart-8ebc0f74-1e99-4420-9237-a92722c39945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925566462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2925566462
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1791730800
Short name T73
Test name
Test status
Simulation time 156113574 ps
CPU time 0.85 seconds
Started May 21 02:13:26 PM PDT 24
Finished May 21 02:13:36 PM PDT 24
Peak memory 200344 kb
Host smart-cfe3378d-eb6f-400e-8b9a-68f1746c97b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791730800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1791730800
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3961001564
Short name T31
Test name
Test status
Simulation time 1712918253 ps
CPU time 6.21 seconds
Started May 21 02:13:24 PM PDT 24
Finished May 21 02:13:38 PM PDT 24
Peak memory 200668 kb
Host smart-937f41bb-aaf8-4d51-923a-a4cf0ce3693c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961001564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3961001564
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2186456544
Short name T147
Test name
Test status
Simulation time 165625115 ps
CPU time 1.12 seconds
Started May 21 02:13:21 PM PDT 24
Finished May 21 02:13:28 PM PDT 24
Peak memory 200516 kb
Host smart-a22dc335-9f6a-466e-8af6-6192a33d07bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186456544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2186456544
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.329630215
Short name T376
Test name
Test status
Simulation time 122233029 ps
CPU time 1.26 seconds
Started May 21 02:13:22 PM PDT 24
Finished May 21 02:13:29 PM PDT 24
Peak memory 200720 kb
Host smart-98ec2c37-5831-427d-a5e2-38137f847be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329630215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.329630215
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.179337503
Short name T483
Test name
Test status
Simulation time 5143353973 ps
CPU time 21.91 seconds
Started May 21 02:13:28 PM PDT 24
Finished May 21 02:14:00 PM PDT 24
Peak memory 209044 kb
Host smart-bd8eb8d7-a65d-4881-89e6-f946ad7d78c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179337503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.179337503
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.151633364
Short name T480
Test name
Test status
Simulation time 300414251 ps
CPU time 2.03 seconds
Started May 21 02:13:26 PM PDT 24
Finished May 21 02:13:36 PM PDT 24
Peak memory 208712 kb
Host smart-5a7e831d-9e18-4dca-ba72-ee4c7a58d2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151633364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.151633364
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.4248244835
Short name T403
Test name
Test status
Simulation time 84316970 ps
CPU time 0.89 seconds
Started May 21 02:13:25 PM PDT 24
Finished May 21 02:13:34 PM PDT 24
Peak memory 200520 kb
Host smart-d6241692-5eb1-4127-9701-416d648f467f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248244835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.4248244835
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1609579534
Short name T169
Test name
Test status
Simulation time 72697118 ps
CPU time 0.8 seconds
Started May 21 02:13:25 PM PDT 24
Finished May 21 02:13:34 PM PDT 24
Peak memory 200348 kb
Host smart-60dd3759-4744-4d1a-bb14-3375d31516ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609579534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1609579534
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2928006318
Short name T391
Test name
Test status
Simulation time 1889956030 ps
CPU time 6.82 seconds
Started May 21 02:13:29 PM PDT 24
Finished May 21 02:13:46 PM PDT 24
Peak memory 222204 kb
Host smart-d6b210bd-af97-4b18-9641-e8054a325efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928006318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2928006318
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1474914509
Short name T370
Test name
Test status
Simulation time 245283378 ps
CPU time 1.13 seconds
Started May 21 02:13:26 PM PDT 24
Finished May 21 02:13:36 PM PDT 24
Peak memory 217556 kb
Host smart-887f496f-a04f-4b73-957d-3746fd0a2b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474914509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1474914509
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3564755986
Short name T24
Test name
Test status
Simulation time 222785295 ps
CPU time 1.01 seconds
Started May 21 02:13:23 PM PDT 24
Finished May 21 02:13:32 PM PDT 24
Peak memory 200264 kb
Host smart-3c417700-a418-4957-99ff-a66781a98390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564755986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3564755986
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1187751945
Short name T220
Test name
Test status
Simulation time 1300173260 ps
CPU time 5.65 seconds
Started May 21 02:13:25 PM PDT 24
Finished May 21 02:13:39 PM PDT 24
Peak memory 200680 kb
Host smart-45b95595-5356-499a-bcc5-fbbcd69a3f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187751945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1187751945
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3727295932
Short name T336
Test name
Test status
Simulation time 110660076 ps
CPU time 1.11 seconds
Started May 21 02:13:25 PM PDT 24
Finished May 21 02:13:34 PM PDT 24
Peak memory 200516 kb
Host smart-fe874582-f912-4857-b19c-d89896da88df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727295932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3727295932
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.431368997
Short name T207
Test name
Test status
Simulation time 112406231 ps
CPU time 1.16 seconds
Started May 21 02:13:29 PM PDT 24
Finished May 21 02:13:41 PM PDT 24
Peak memory 200680 kb
Host smart-d5827aaf-44b1-4c9c-b60e-63e90bdf16f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431368997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.431368997
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.4112979921
Short name T343
Test name
Test status
Simulation time 1835633625 ps
CPU time 6.5 seconds
Started May 21 02:13:25 PM PDT 24
Finished May 21 02:13:40 PM PDT 24
Peak memory 208908 kb
Host smart-74569df6-efbf-41ab-846d-c8eca3584334
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112979921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.4112979921
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.2548341178
Short name T407
Test name
Test status
Simulation time 359323955 ps
CPU time 2.45 seconds
Started May 21 02:13:25 PM PDT 24
Finished May 21 02:13:36 PM PDT 24
Peak memory 200496 kb
Host smart-bddd7dfe-2e21-4560-b4ba-9788634d401a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548341178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.2548341178
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2353980913
Short name T195
Test name
Test status
Simulation time 133275306 ps
CPU time 1.08 seconds
Started May 21 02:13:25 PM PDT 24
Finished May 21 02:13:35 PM PDT 24
Peak memory 200532 kb
Host smart-6e385580-0f54-48f8-93c4-321d942268bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353980913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2353980913
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.3553012973
Short name T526
Test name
Test status
Simulation time 64024423 ps
CPU time 0.79 seconds
Started May 21 02:13:28 PM PDT 24
Finished May 21 02:13:38 PM PDT 24
Peak memory 200348 kb
Host smart-bcd0a92a-380f-4128-9342-07c3622b8f4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553012973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.3553012973
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3096603747
Short name T37
Test name
Test status
Simulation time 1879260933 ps
CPU time 7.26 seconds
Started May 21 02:13:27 PM PDT 24
Finished May 21 02:13:44 PM PDT 24
Peak memory 217656 kb
Host smart-2ac39652-fd0c-4fcf-a4aa-9320a98d59e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096603747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3096603747
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3257266120
Short name T191
Test name
Test status
Simulation time 244075620 ps
CPU time 1.09 seconds
Started May 21 02:13:29 PM PDT 24
Finished May 21 02:13:41 PM PDT 24
Peak memory 217580 kb
Host smart-93f985ba-bc4b-4f8e-8f21-237bf4ac06b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257266120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3257266120
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.3271605467
Short name T394
Test name
Test status
Simulation time 138829955 ps
CPU time 0.86 seconds
Started May 21 02:13:26 PM PDT 24
Finished May 21 02:13:36 PM PDT 24
Peak memory 200320 kb
Host smart-e6179083-9932-47f1-b730-2cd340ee60ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271605467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3271605467
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3833332169
Short name T119
Test name
Test status
Simulation time 1407627921 ps
CPU time 6.02 seconds
Started May 21 02:13:26 PM PDT 24
Finished May 21 02:13:41 PM PDT 24
Peak memory 200664 kb
Host smart-a1281cc3-4d05-415d-b342-a9a57cffc318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833332169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3833332169
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1717506821
Short name T175
Test name
Test status
Simulation time 102402466 ps
CPU time 1.05 seconds
Started May 21 02:13:29 PM PDT 24
Finished May 21 02:13:41 PM PDT 24
Peak memory 200532 kb
Host smart-d15b102c-91f9-4fcd-a7f4-9b2762f9707b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717506821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1717506821
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.1735484717
Short name T474
Test name
Test status
Simulation time 190331769 ps
CPU time 1.28 seconds
Started May 21 02:13:29 PM PDT 24
Finished May 21 02:13:41 PM PDT 24
Peak memory 200676 kb
Host smart-0577543e-32d9-46b1-9dc0-3ebb8aeb173d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735484717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1735484717
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2262927780
Short name T317
Test name
Test status
Simulation time 5145980500 ps
CPU time 18.78 seconds
Started May 21 02:13:28 PM PDT 24
Finished May 21 02:13:56 PM PDT 24
Peak memory 200924 kb
Host smart-3d55927a-db14-4999-b668-566fb28ad760
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262927780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2262927780
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3417259933
Short name T182
Test name
Test status
Simulation time 145068370 ps
CPU time 1.71 seconds
Started May 21 02:13:25 PM PDT 24
Finished May 21 02:13:35 PM PDT 24
Peak memory 200564 kb
Host smart-d2370d57-be53-4e12-9f9b-5eac649ae326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417259933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3417259933
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3624996456
Short name T314
Test name
Test status
Simulation time 77279065 ps
CPU time 0.87 seconds
Started May 21 02:13:24 PM PDT 24
Finished May 21 02:13:32 PM PDT 24
Peak memory 200468 kb
Host smart-744bf879-ea9d-4d45-9cf9-e6df918434fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624996456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3624996456
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.1671457734
Short name T174
Test name
Test status
Simulation time 71066801 ps
CPU time 0.76 seconds
Started May 21 02:13:30 PM PDT 24
Finished May 21 02:13:41 PM PDT 24
Peak memory 200352 kb
Host smart-1e1bd4b5-c5cf-4c0d-ad55-aca04d8a6c95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671457734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1671457734
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.870106162
Short name T383
Test name
Test status
Simulation time 1898207571 ps
CPU time 7.13 seconds
Started May 21 02:13:33 PM PDT 24
Finished May 21 02:13:50 PM PDT 24
Peak memory 217616 kb
Host smart-7ec658e3-4e4a-4388-ab7d-75873695793c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870106162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.870106162
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.90843009
Short name T163
Test name
Test status
Simulation time 243776302 ps
CPU time 1.06 seconds
Started May 21 02:13:26 PM PDT 24
Finished May 21 02:13:36 PM PDT 24
Peak memory 217704 kb
Host smart-9e76e2e7-ca1f-476a-86b2-fad462897476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90843009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.90843009
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.428029917
Short name T337
Test name
Test status
Simulation time 119451584 ps
CPU time 0.81 seconds
Started May 21 02:13:31 PM PDT 24
Finished May 21 02:13:43 PM PDT 24
Peak memory 200284 kb
Host smart-d408ead7-336e-49d0-aa2b-81a2616f3172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428029917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.428029917
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1422153835
Short name T373
Test name
Test status
Simulation time 145106006 ps
CPU time 1.1 seconds
Started May 21 02:13:31 PM PDT 24
Finished May 21 02:13:43 PM PDT 24
Peak memory 200356 kb
Host smart-db4e9839-18c2-4c23-b991-d96053dc1093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422153835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1422153835
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3361625775
Short name T282
Test name
Test status
Simulation time 249455955 ps
CPU time 1.48 seconds
Started May 21 02:13:27 PM PDT 24
Finished May 21 02:13:38 PM PDT 24
Peak memory 200712 kb
Host smart-cd442dfd-bac9-4381-aa0e-62d291cf3742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361625775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3361625775
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3179568200
Short name T507
Test name
Test status
Simulation time 12727414938 ps
CPU time 43.35 seconds
Started May 21 02:13:29 PM PDT 24
Finished May 21 02:14:22 PM PDT 24
Peak memory 209064 kb
Host smart-1a7b13b8-c8e6-42da-838c-26a0baf99567
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179568200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3179568200
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1121167647
Short name T127
Test name
Test status
Simulation time 458032666 ps
CPU time 2.4 seconds
Started May 21 02:13:32 PM PDT 24
Finished May 21 02:13:45 PM PDT 24
Peak memory 200524 kb
Host smart-b09e1ce7-edfb-4711-b4e2-ee959b96ddcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121167647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1121167647
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1239570147
Short name T303
Test name
Test status
Simulation time 182151361 ps
CPU time 1.16 seconds
Started May 21 02:13:31 PM PDT 24
Finished May 21 02:13:43 PM PDT 24
Peak memory 200492 kb
Host smart-03fc7216-9001-4360-8a22-5b1b06ce034c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239570147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1239570147
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3949976761
Short name T8
Test name
Test status
Simulation time 78832355 ps
CPU time 0.79 seconds
Started May 21 02:13:33 PM PDT 24
Finished May 21 02:13:44 PM PDT 24
Peak memory 200272 kb
Host smart-85bfd4d5-30c7-483f-826b-900ea439f3b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949976761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3949976761
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3961725945
Short name T41
Test name
Test status
Simulation time 2349797642 ps
CPU time 8.52 seconds
Started May 21 02:13:29 PM PDT 24
Finished May 21 02:13:48 PM PDT 24
Peak memory 230352 kb
Host smart-e2c6e79a-ca89-4b28-a772-1d7df0c28c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961725945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3961725945
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2079086184
Short name T7
Test name
Test status
Simulation time 244868247 ps
CPU time 1.06 seconds
Started May 21 02:13:29 PM PDT 24
Finished May 21 02:13:41 PM PDT 24
Peak memory 217600 kb
Host smart-d2e77707-9c22-4ff7-af3f-dfcb50c5874e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079086184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2079086184
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3240587573
Short name T520
Test name
Test status
Simulation time 165040690 ps
CPU time 0.9 seconds
Started May 21 02:13:27 PM PDT 24
Finished May 21 02:13:37 PM PDT 24
Peak memory 200300 kb
Host smart-76fbf7b4-85f2-48b2-a710-d010759474a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240587573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3240587573
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3916569142
Short name T214
Test name
Test status
Simulation time 776795389 ps
CPU time 4.34 seconds
Started May 21 02:13:29 PM PDT 24
Finished May 21 02:13:45 PM PDT 24
Peak memory 200600 kb
Host smart-ed11ace9-ce2d-4785-ac9f-40e890279bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916569142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3916569142
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.4092734809
Short name T137
Test name
Test status
Simulation time 169737290 ps
CPU time 1.17 seconds
Started May 21 02:13:28 PM PDT 24
Finished May 21 02:13:40 PM PDT 24
Peak memory 200512 kb
Host smart-54b976a0-1d1c-4869-923e-32c84d6272f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092734809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.4092734809
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.3997278918
Short name T125
Test name
Test status
Simulation time 239401887 ps
CPU time 1.44 seconds
Started May 21 02:13:29 PM PDT 24
Finished May 21 02:13:41 PM PDT 24
Peak memory 200628 kb
Host smart-28284ba5-50eb-4d9b-9fa2-27345a41fd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997278918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.3997278918
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.668685999
Short name T120
Test name
Test status
Simulation time 5722908862 ps
CPU time 18.92 seconds
Started May 21 02:13:30 PM PDT 24
Finished May 21 02:13:59 PM PDT 24
Peak memory 200808 kb
Host smart-168285b2-7542-4581-823c-effb38f5082e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668685999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.668685999
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.2910900258
Short name T411
Test name
Test status
Simulation time 139946748 ps
CPU time 1.79 seconds
Started May 21 02:13:32 PM PDT 24
Finished May 21 02:13:45 PM PDT 24
Peak memory 208708 kb
Host smart-9d4fafe1-8a9b-40a0-87bf-1307a51fea3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910900258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2910900258
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1639938142
Short name T69
Test name
Test status
Simulation time 312993380 ps
CPU time 1.63 seconds
Started May 21 02:13:28 PM PDT 24
Finished May 21 02:13:40 PM PDT 24
Peak memory 200600 kb
Host smart-8a932d6a-818a-4761-82b7-e3d724748c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639938142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1639938142
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.722529302
Short name T427
Test name
Test status
Simulation time 62038230 ps
CPU time 0.74 seconds
Started May 21 02:13:31 PM PDT 24
Finished May 21 02:13:43 PM PDT 24
Peak memory 200332 kb
Host smart-ebdbf146-1b92-47ac-84b2-3d909a7e7036
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722529302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.722529302
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3994180666
Short name T327
Test name
Test status
Simulation time 2357709884 ps
CPU time 7.94 seconds
Started May 21 02:13:31 PM PDT 24
Finished May 21 02:13:50 PM PDT 24
Peak memory 218028 kb
Host smart-bcf24bd8-60e3-4d28-bf57-0caf2812418f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994180666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3994180666
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2861398864
Short name T9
Test name
Test status
Simulation time 244075020 ps
CPU time 1.11 seconds
Started May 21 02:13:34 PM PDT 24
Finished May 21 02:13:46 PM PDT 24
Peak memory 217584 kb
Host smart-5d200753-2803-4564-a373-ceaf575174a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861398864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2861398864
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.24305741
Short name T400
Test name
Test status
Simulation time 225245684 ps
CPU time 0.91 seconds
Started May 21 02:13:31 PM PDT 24
Finished May 21 02:13:43 PM PDT 24
Peak memory 200172 kb
Host smart-c6873df0-c558-40cf-9526-25fd5595a5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24305741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.24305741
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1459618476
Short name T339
Test name
Test status
Simulation time 1691881251 ps
CPU time 6.25 seconds
Started May 21 02:13:30 PM PDT 24
Finished May 21 02:13:46 PM PDT 24
Peak memory 200704 kb
Host smart-dc7f7648-0e32-48b7-9a67-d0b76effc623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459618476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1459618476
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.215774067
Short name T172
Test name
Test status
Simulation time 103819646 ps
CPU time 1.02 seconds
Started May 21 02:13:30 PM PDT 24
Finished May 21 02:13:41 PM PDT 24
Peak memory 200444 kb
Host smart-cc325343-b91d-47cc-8e93-397a73eb337c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215774067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.215774067
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.1431721763
Short name T82
Test name
Test status
Simulation time 248523021 ps
CPU time 1.56 seconds
Started May 21 02:13:28 PM PDT 24
Finished May 21 02:13:41 PM PDT 24
Peak memory 200728 kb
Host smart-82ea7950-6a57-45c1-9d6e-54b5e6555258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431721763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1431721763
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2841832101
Short name T95
Test name
Test status
Simulation time 17063920490 ps
CPU time 57.77 seconds
Started May 21 02:13:27 PM PDT 24
Finished May 21 02:14:34 PM PDT 24
Peak memory 200816 kb
Host smart-b03df5ec-4f2c-487e-8560-90a3dcce1c85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841832101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2841832101
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1917923403
Short name T173
Test name
Test status
Simulation time 279626287 ps
CPU time 1.92 seconds
Started May 21 02:13:28 PM PDT 24
Finished May 21 02:13:41 PM PDT 24
Peak memory 200436 kb
Host smart-b92655f6-31f5-4cd9-869b-79d80abd4b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917923403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1917923403
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2876059332
Short name T419
Test name
Test status
Simulation time 166651477 ps
CPU time 1.47 seconds
Started May 21 02:13:27 PM PDT 24
Finished May 21 02:13:38 PM PDT 24
Peak memory 200732 kb
Host smart-d0791d74-717b-4477-8765-3007620d6638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876059332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2876059332
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3400145631
Short name T68
Test name
Test status
Simulation time 66331933 ps
CPU time 0.75 seconds
Started May 21 02:13:37 PM PDT 24
Finished May 21 02:13:49 PM PDT 24
Peak memory 200324 kb
Host smart-6e02dad9-8d52-49c5-99fa-405766fa0803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400145631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3400145631
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.970729014
Short name T35
Test name
Test status
Simulation time 1227907100 ps
CPU time 5.84 seconds
Started May 21 02:13:37 PM PDT 24
Finished May 21 02:13:54 PM PDT 24
Peak memory 217120 kb
Host smart-4ddff9ad-e3a0-4f2c-b6ba-4196745660b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970729014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.970729014
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3227009101
Short name T421
Test name
Test status
Simulation time 244612885 ps
CPU time 1.05 seconds
Started May 21 02:13:38 PM PDT 24
Finished May 21 02:13:50 PM PDT 24
Peak memory 217572 kb
Host smart-0777714a-4d1f-417b-b1e4-e273a93e45a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227009101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3227009101
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.3595124136
Short name T488
Test name
Test status
Simulation time 79900092 ps
CPU time 0.74 seconds
Started May 21 02:13:35 PM PDT 24
Finished May 21 02:13:46 PM PDT 24
Peak memory 200292 kb
Host smart-4da8037f-6172-40ca-b8b6-943f30d7d609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595124136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3595124136
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.3454935726
Short name T307
Test name
Test status
Simulation time 844492704 ps
CPU time 4.38 seconds
Started May 21 02:13:34 PM PDT 24
Finished May 21 02:13:49 PM PDT 24
Peak memory 200704 kb
Host smart-8737f919-2dd4-421c-9704-0dcf0a52881b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454935726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3454935726
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.1714747917
Short name T277
Test name
Test status
Simulation time 185000078 ps
CPU time 1.2 seconds
Started May 21 02:13:39 PM PDT 24
Finished May 21 02:13:50 PM PDT 24
Peak memory 200524 kb
Host smart-c1aa519a-ebd8-469a-a60a-2a4b098a335f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714747917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.1714747917
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.4001171755
Short name T291
Test name
Test status
Simulation time 207192127 ps
CPU time 1.53 seconds
Started May 21 02:13:35 PM PDT 24
Finished May 21 02:13:47 PM PDT 24
Peak memory 200676 kb
Host smart-724f5915-c32e-40ec-b265-2e332ab9ae6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001171755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.4001171755
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3914876209
Short name T300
Test name
Test status
Simulation time 5208742982 ps
CPU time 21.43 seconds
Started May 21 02:13:36 PM PDT 24
Finished May 21 02:14:09 PM PDT 24
Peak memory 200860 kb
Host smart-541ae878-2c52-44da-8d46-8162eaa82a6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914876209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3914876209
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.425533897
Short name T200
Test name
Test status
Simulation time 140281519 ps
CPU time 1.7 seconds
Started May 21 02:13:38 PM PDT 24
Finished May 21 02:13:50 PM PDT 24
Peak memory 200520 kb
Host smart-1f6bf024-9591-4dd1-a248-dd5581635b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425533897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.425533897
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.3159325219
Short name T167
Test name
Test status
Simulation time 148321136 ps
CPU time 1.12 seconds
Started May 21 02:13:35 PM PDT 24
Finished May 21 02:13:48 PM PDT 24
Peak memory 200696 kb
Host smart-f2316588-3a7d-4431-991a-606ad96c1f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159325219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3159325219
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2078987251
Short name T444
Test name
Test status
Simulation time 74910688 ps
CPU time 0.81 seconds
Started May 21 02:13:34 PM PDT 24
Finished May 21 02:13:46 PM PDT 24
Peak memory 200324 kb
Host smart-d710c105-01fc-418f-bb0f-5639f487ca77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078987251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2078987251
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3840425314
Short name T36
Test name
Test status
Simulation time 2347462873 ps
CPU time 8.28 seconds
Started May 21 02:13:37 PM PDT 24
Finished May 21 02:13:56 PM PDT 24
Peak memory 218244 kb
Host smart-4d1c5176-59e2-46f2-8f0a-8ddc23e4f114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840425314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3840425314
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1993584378
Short name T384
Test name
Test status
Simulation time 244655064 ps
CPU time 1.04 seconds
Started May 21 02:13:49 PM PDT 24
Finished May 21 02:13:57 PM PDT 24
Peak memory 217576 kb
Host smart-7b0a6807-947d-4259-b849-0de52d0aab57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993584378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1993584378
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2459157630
Short name T251
Test name
Test status
Simulation time 198616149 ps
CPU time 0.88 seconds
Started May 21 02:13:35 PM PDT 24
Finished May 21 02:13:47 PM PDT 24
Peak memory 200344 kb
Host smart-9a14b1e0-b5b2-4e57-9406-ab4175ca1a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459157630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2459157630
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3828089868
Short name T88
Test name
Test status
Simulation time 2094124940 ps
CPU time 7.45 seconds
Started May 21 02:13:35 PM PDT 24
Finished May 21 02:13:53 PM PDT 24
Peak memory 200724 kb
Host smart-69fc76a3-91a5-45ad-a9a8-d57320be0bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828089868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3828089868
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.458679552
Short name T493
Test name
Test status
Simulation time 180160634 ps
CPU time 1.23 seconds
Started May 21 02:13:37 PM PDT 24
Finished May 21 02:13:49 PM PDT 24
Peak memory 200524 kb
Host smart-ac01e3be-e19b-4786-80f3-f71c7da20891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458679552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.458679552
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.1689388819
Short name T369
Test name
Test status
Simulation time 112326515 ps
CPU time 1.21 seconds
Started May 21 02:13:40 PM PDT 24
Finished May 21 02:13:51 PM PDT 24
Peak memory 200676 kb
Host smart-d8506b49-b3f0-492b-94a7-5a9ef1a73b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689388819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1689388819
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1170823840
Short name T527
Test name
Test status
Simulation time 4339065211 ps
CPU time 21.37 seconds
Started May 21 02:13:34 PM PDT 24
Finished May 21 02:14:07 PM PDT 24
Peak memory 200828 kb
Host smart-26f7695e-c176-42b1-b9a9-9746671d0e74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170823840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1170823840
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1854529539
Short name T78
Test name
Test status
Simulation time 120275648 ps
CPU time 1.44 seconds
Started May 21 02:13:36 PM PDT 24
Finished May 21 02:13:48 PM PDT 24
Peak memory 200460 kb
Host smart-44a116a1-2f92-471e-a7cb-e47a1a0f35ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854529539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1854529539
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3130820256
Short name T497
Test name
Test status
Simulation time 156905236 ps
CPU time 1.15 seconds
Started May 21 02:13:35 PM PDT 24
Finished May 21 02:13:47 PM PDT 24
Peak memory 200492 kb
Host smart-205304df-d8f9-4c99-8544-1927e778ed8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130820256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3130820256
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.2172653778
Short name T138
Test name
Test status
Simulation time 81248352 ps
CPU time 0.88 seconds
Started May 21 02:13:35 PM PDT 24
Finished May 21 02:13:47 PM PDT 24
Peak memory 200328 kb
Host smart-2531f6eb-55ca-40c4-bc28-cb1bcd014fe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172653778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2172653778
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3729952562
Short name T49
Test name
Test status
Simulation time 1873041436 ps
CPU time 7.54 seconds
Started May 21 02:13:35 PM PDT 24
Finished May 21 02:13:54 PM PDT 24
Peak memory 218140 kb
Host smart-2a4ab549-a30c-4414-ac37-7c1e2558bee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729952562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3729952562
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1703333134
Short name T512
Test name
Test status
Simulation time 244533265 ps
CPU time 1.08 seconds
Started May 21 02:13:36 PM PDT 24
Finished May 21 02:13:48 PM PDT 24
Peak memory 217728 kb
Host smart-f5fd9d2c-42fd-4989-92bb-69c00d669253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703333134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1703333134
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2990645752
Short name T289
Test name
Test status
Simulation time 120322014 ps
CPU time 0.84 seconds
Started May 21 02:13:33 PM PDT 24
Finished May 21 02:13:44 PM PDT 24
Peak memory 200232 kb
Host smart-d439ab3d-dae3-414d-a572-fd7c4e46b12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990645752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2990645752
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2836047092
Short name T194
Test name
Test status
Simulation time 1505793549 ps
CPU time 5.92 seconds
Started May 21 02:13:40 PM PDT 24
Finished May 21 02:13:56 PM PDT 24
Peak memory 200676 kb
Host smart-42d50c08-6d65-4b5b-b061-557c06869f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836047092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2836047092
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2094765200
Short name T529
Test name
Test status
Simulation time 107235794 ps
CPU time 1 seconds
Started May 21 02:13:35 PM PDT 24
Finished May 21 02:13:47 PM PDT 24
Peak memory 200464 kb
Host smart-66e27773-f423-4f11-838f-8860f968284e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094765200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2094765200
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3579769341
Short name T14
Test name
Test status
Simulation time 114324586 ps
CPU time 1.25 seconds
Started May 21 02:13:34 PM PDT 24
Finished May 21 02:13:47 PM PDT 24
Peak memory 200668 kb
Host smart-d68a2050-b143-4b9d-b349-3b95257b093a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579769341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3579769341
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1244085043
Short name T467
Test name
Test status
Simulation time 5638081869 ps
CPU time 24.72 seconds
Started May 21 02:13:35 PM PDT 24
Finished May 21 02:14:11 PM PDT 24
Peak memory 200840 kb
Host smart-d54053ad-bbf8-4c15-8cc3-bdc6c3e4b3ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244085043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1244085043
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.4070165458
Short name T226
Test name
Test status
Simulation time 311412068 ps
CPU time 2.05 seconds
Started May 21 02:13:35 PM PDT 24
Finished May 21 02:13:48 PM PDT 24
Peak memory 208712 kb
Host smart-b37f5837-740e-44c8-b5a3-cf121d8bf342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070165458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.4070165458
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3094407583
Short name T335
Test name
Test status
Simulation time 164108887 ps
CPU time 1.36 seconds
Started May 21 02:13:32 PM PDT 24
Finished May 21 02:13:44 PM PDT 24
Peak memory 200660 kb
Host smart-627ef8df-6e04-4127-b772-f1d4404c4722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094407583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3094407583
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.201442402
Short name T264
Test name
Test status
Simulation time 66446857 ps
CPU time 0.8 seconds
Started May 21 02:12:28 PM PDT 24
Finished May 21 02:12:31 PM PDT 24
Peak memory 200328 kb
Host smart-d8163841-5672-40e0-aba9-2a2a4cca83cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201442402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.201442402
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.884670893
Short name T513
Test name
Test status
Simulation time 2376348473 ps
CPU time 8.65 seconds
Started May 21 02:12:30 PM PDT 24
Finished May 21 02:12:41 PM PDT 24
Peak memory 218184 kb
Host smart-fb1c7bc5-7f7d-4c0f-b220-6a773ef11c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884670893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.884670893
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.4144471301
Short name T192
Test name
Test status
Simulation time 244706858 ps
CPU time 1.07 seconds
Started May 21 02:12:24 PM PDT 24
Finished May 21 02:12:27 PM PDT 24
Peak memory 217592 kb
Host smart-6eddf2d3-5501-471b-9601-27e66a4e1932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144471301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.4144471301
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3399993364
Short name T221
Test name
Test status
Simulation time 140829298 ps
CPU time 0.82 seconds
Started May 21 02:12:27 PM PDT 24
Finished May 21 02:12:30 PM PDT 24
Peak memory 200284 kb
Host smart-01a82c65-8100-47be-9d34-8aa79688adba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399993364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3399993364
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1732154883
Short name T235
Test name
Test status
Simulation time 1571963912 ps
CPU time 5.84 seconds
Started May 21 02:12:24 PM PDT 24
Finished May 21 02:12:32 PM PDT 24
Peak memory 200676 kb
Host smart-336bb6c7-1515-4d15-bb64-28baff7d90db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732154883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1732154883
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.518597299
Short name T64
Test name
Test status
Simulation time 16934538183 ps
CPU time 25.71 seconds
Started May 21 02:12:23 PM PDT 24
Finished May 21 02:12:52 PM PDT 24
Peak memory 217620 kb
Host smart-fd567e33-fe57-4205-886d-2afb78010b63
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518597299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.518597299
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.135713981
Short name T470
Test name
Test status
Simulation time 179316328 ps
CPU time 1.2 seconds
Started May 21 02:12:27 PM PDT 24
Finished May 21 02:12:29 PM PDT 24
Peak memory 200524 kb
Host smart-4af3f0fb-ec23-43b9-b6bb-a979eafceb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135713981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.135713981
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.4160344596
Short name T381
Test name
Test status
Simulation time 250784150 ps
CPU time 1.58 seconds
Started May 21 02:12:26 PM PDT 24
Finished May 21 02:12:29 PM PDT 24
Peak memory 200680 kb
Host smart-347edfe9-0c70-4348-8820-e8f27617c5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160344596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.4160344596
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3694712788
Short name T328
Test name
Test status
Simulation time 2790299277 ps
CPU time 13.34 seconds
Started May 21 02:12:26 PM PDT 24
Finished May 21 02:12:41 PM PDT 24
Peak memory 200808 kb
Host smart-11f35484-2753-468b-a007-edceb4b2ba30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694712788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3694712788
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3182352439
Short name T151
Test name
Test status
Simulation time 259113203 ps
CPU time 1.76 seconds
Started May 21 02:12:30 PM PDT 24
Finished May 21 02:12:35 PM PDT 24
Peak memory 200432 kb
Host smart-93d8af39-ea4a-4ee9-bdd1-f3e95523ee67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182352439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3182352439
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2653434206
Short name T492
Test name
Test status
Simulation time 116944083 ps
CPU time 1.16 seconds
Started May 21 02:12:23 PM PDT 24
Finished May 21 02:12:27 PM PDT 24
Peak memory 200488 kb
Host smart-7bf35632-fc66-4613-91fe-a1d6b942fe37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653434206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2653434206
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2232948589
Short name T223
Test name
Test status
Simulation time 77444888 ps
CPU time 0.78 seconds
Started May 21 02:13:45 PM PDT 24
Finished May 21 02:13:54 PM PDT 24
Peak memory 200312 kb
Host smart-0b2d95a6-2415-4a03-a7b7-0316ea7b14d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232948589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2232948589
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2902720095
Short name T15
Test name
Test status
Simulation time 1235665898 ps
CPU time 5.31 seconds
Started May 21 02:13:40 PM PDT 24
Finished May 21 02:13:55 PM PDT 24
Peak memory 222220 kb
Host smart-854ed265-760f-44e6-9e21-f68764469faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902720095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2902720095
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.296637842
Short name T315
Test name
Test status
Simulation time 243077312 ps
CPU time 1.08 seconds
Started May 21 02:13:44 PM PDT 24
Finished May 21 02:13:53 PM PDT 24
Peak memory 217588 kb
Host smart-5ef62830-aaa3-4837-9bf3-1dfd2eeb0d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296637842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.296637842
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3151341002
Short name T404
Test name
Test status
Simulation time 200656158 ps
CPU time 0.88 seconds
Started May 21 02:13:40 PM PDT 24
Finished May 21 02:13:50 PM PDT 24
Peak memory 200296 kb
Host smart-b39c24a9-c01d-4b46-b939-76c55532faa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151341002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3151341002
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.633486601
Short name T287
Test name
Test status
Simulation time 946125303 ps
CPU time 5.6 seconds
Started May 21 02:13:46 PM PDT 24
Finished May 21 02:13:59 PM PDT 24
Peak memory 200752 kb
Host smart-8ef3d73c-62aa-4a8e-8a65-6cacdf16ae75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633486601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.633486601
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2014877642
Short name T533
Test name
Test status
Simulation time 144908663 ps
CPU time 1.12 seconds
Started May 21 02:13:44 PM PDT 24
Finished May 21 02:13:53 PM PDT 24
Peak memory 200492 kb
Host smart-1d83e75f-568c-4674-a743-1af158b8b98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014877642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2014877642
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.540270395
Short name T298
Test name
Test status
Simulation time 119579443 ps
CPU time 1.23 seconds
Started May 21 02:13:34 PM PDT 24
Finished May 21 02:13:46 PM PDT 24
Peak memory 200600 kb
Host smart-98913cd8-5b95-4bfd-94e3-5e7c7358fda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540270395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.540270395
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2185851956
Short name T344
Test name
Test status
Simulation time 3428018830 ps
CPU time 12.31 seconds
Started May 21 02:13:48 PM PDT 24
Finished May 21 02:14:07 PM PDT 24
Peak memory 210596 kb
Host smart-96a1a7f0-3799-4566-90be-1a62ecfa4a29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185851956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2185851956
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.3449771503
Short name T156
Test name
Test status
Simulation time 371335392 ps
CPU time 2.63 seconds
Started May 21 02:13:41 PM PDT 24
Finished May 21 02:13:53 PM PDT 24
Peak memory 200484 kb
Host smart-ed54510c-f591-48e7-92c4-1a53c486efbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449771503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3449771503
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2556992756
Short name T318
Test name
Test status
Simulation time 206997304 ps
CPU time 1.3 seconds
Started May 21 02:13:39 PM PDT 24
Finished May 21 02:13:50 PM PDT 24
Peak memory 200532 kb
Host smart-418c0c5d-c2b2-4a15-a1b1-bc3a81916221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556992756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2556992756
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1413212107
Short name T316
Test name
Test status
Simulation time 80163224 ps
CPU time 0.87 seconds
Started May 21 02:13:41 PM PDT 24
Finished May 21 02:13:51 PM PDT 24
Peak memory 200264 kb
Host smart-7a935fd4-5a8f-49a3-8df6-ae6b201aa9d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413212107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1413212107
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1090309459
Short name T295
Test name
Test status
Simulation time 1225455376 ps
CPU time 5.58 seconds
Started May 21 02:13:40 PM PDT 24
Finished May 21 02:13:56 PM PDT 24
Peak memory 221680 kb
Host smart-fb109232-1a31-48f0-a58b-bb1acac2b590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090309459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1090309459
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2890728365
Short name T443
Test name
Test status
Simulation time 244485804 ps
CPU time 1.15 seconds
Started May 21 02:13:43 PM PDT 24
Finished May 21 02:13:53 PM PDT 24
Peak memory 217540 kb
Host smart-41771a6d-f374-4b2f-bd20-387f85db82a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890728365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2890728365
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.3033132596
Short name T213
Test name
Test status
Simulation time 101158039 ps
CPU time 0.78 seconds
Started May 21 02:13:48 PM PDT 24
Finished May 21 02:13:56 PM PDT 24
Peak memory 200220 kb
Host smart-2e8901d4-90a9-4bcd-8be7-7741e6040273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033132596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3033132596
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3651388774
Short name T190
Test name
Test status
Simulation time 795071982 ps
CPU time 3.84 seconds
Started May 21 02:13:38 PM PDT 24
Finished May 21 02:13:53 PM PDT 24
Peak memory 200704 kb
Host smart-90a32992-22da-4e65-bbab-5fdca815bfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651388774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3651388774
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.734015548
Short name T450
Test name
Test status
Simulation time 167940821 ps
CPU time 1.2 seconds
Started May 21 02:13:46 PM PDT 24
Finished May 21 02:13:55 PM PDT 24
Peak memory 200536 kb
Host smart-b7c18f1b-edb9-45b0-b3f4-284a3969b60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734015548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.734015548
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1331341217
Short name T206
Test name
Test status
Simulation time 253903981 ps
CPU time 1.53 seconds
Started May 21 02:13:46 PM PDT 24
Finished May 21 02:13:55 PM PDT 24
Peak memory 200696 kb
Host smart-0dcc9654-aa1b-4b87-b617-44a39f666f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331341217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1331341217
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1782477226
Short name T2
Test name
Test status
Simulation time 10520579973 ps
CPU time 39.86 seconds
Started May 21 02:13:40 PM PDT 24
Finished May 21 02:14:29 PM PDT 24
Peak memory 200828 kb
Host smart-7524f321-d793-45ba-85ce-166317441996
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782477226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1782477226
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.571406360
Short name T486
Test name
Test status
Simulation time 356040196 ps
CPU time 2.24 seconds
Started May 21 02:13:48 PM PDT 24
Finished May 21 02:13:57 PM PDT 24
Peak memory 200476 kb
Host smart-7bf93e43-7982-40cb-8b0f-9a0b6590c043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571406360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.571406360
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2210246582
Short name T406
Test name
Test status
Simulation time 216911276 ps
CPU time 1.33 seconds
Started May 21 02:13:44 PM PDT 24
Finished May 21 02:13:53 PM PDT 24
Peak memory 200488 kb
Host smart-7921cd42-81bd-4690-bd15-00c805079564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210246582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2210246582
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3508091627
Short name T412
Test name
Test status
Simulation time 66906022 ps
CPU time 0.75 seconds
Started May 21 02:13:53 PM PDT 24
Finished May 21 02:14:00 PM PDT 24
Peak memory 200328 kb
Host smart-c0b9c0bc-11e4-4180-9d10-ae45d23ceabe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508091627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3508091627
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.714251804
Short name T479
Test name
Test status
Simulation time 1891387447 ps
CPU time 7.48 seconds
Started May 21 02:13:48 PM PDT 24
Finished May 21 02:14:02 PM PDT 24
Peak memory 218156 kb
Host smart-e5f7c90d-2049-457b-8297-57f8e789dd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714251804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.714251804
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1822609593
Short name T136
Test name
Test status
Simulation time 244190297 ps
CPU time 1.15 seconds
Started May 21 02:13:48 PM PDT 24
Finished May 21 02:13:56 PM PDT 24
Peak memory 217724 kb
Host smart-9d24e140-808a-4dcb-9509-f75ef98d4369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822609593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1822609593
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.565932033
Short name T242
Test name
Test status
Simulation time 188693667 ps
CPU time 0.92 seconds
Started May 21 02:13:42 PM PDT 24
Finished May 21 02:13:52 PM PDT 24
Peak memory 200344 kb
Host smart-6eb119b9-ba66-43aa-a2f0-3ec163844645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565932033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.565932033
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3605177679
Short name T98
Test name
Test status
Simulation time 1370494514 ps
CPU time 5.32 seconds
Started May 21 02:13:43 PM PDT 24
Finished May 21 02:13:57 PM PDT 24
Peak memory 200696 kb
Host smart-c1932b33-c8b4-42fa-9a30-608bcc77d976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605177679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3605177679
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1821463181
Short name T365
Test name
Test status
Simulation time 103526802 ps
CPU time 1.01 seconds
Started May 21 02:14:18 PM PDT 24
Finished May 21 02:14:23 PM PDT 24
Peak memory 200536 kb
Host smart-4ab63d3c-1bee-4184-87c9-205bda1f2934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821463181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1821463181
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.141510072
Short name T408
Test name
Test status
Simulation time 186243016 ps
CPU time 1.43 seconds
Started May 21 02:13:40 PM PDT 24
Finished May 21 02:13:52 PM PDT 24
Peak memory 200724 kb
Host smart-e6bb20c8-c48e-43da-86f0-a332ac892f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141510072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.141510072
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.3250427185
Short name T233
Test name
Test status
Simulation time 2215126738 ps
CPU time 8.91 seconds
Started May 21 02:13:50 PM PDT 24
Finished May 21 02:14:05 PM PDT 24
Peak memory 200852 kb
Host smart-1c426bf6-6321-4a26-b003-e3a51ab8d1fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250427185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3250427185
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3370002765
Short name T465
Test name
Test status
Simulation time 126330250 ps
CPU time 1.66 seconds
Started May 21 02:13:54 PM PDT 24
Finished May 21 02:14:01 PM PDT 24
Peak memory 208716 kb
Host smart-0d3806b2-4614-4077-9287-fc21e7573d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370002765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3370002765
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.2174326730
Short name T461
Test name
Test status
Simulation time 193368370 ps
CPU time 1.37 seconds
Started May 21 02:13:40 PM PDT 24
Finished May 21 02:13:51 PM PDT 24
Peak memory 200492 kb
Host smart-a731ef60-93e8-4bab-94a7-e4f3c02f1fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174326730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2174326730
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.1799777505
Short name T135
Test name
Test status
Simulation time 59071212 ps
CPU time 0.72 seconds
Started May 21 02:13:54 PM PDT 24
Finished May 21 02:14:00 PM PDT 24
Peak memory 200332 kb
Host smart-cd442426-293a-4a13-9be5-8072573a1276
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799777505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1799777505
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3840633841
Short name T429
Test name
Test status
Simulation time 2358762168 ps
CPU time 8.28 seconds
Started May 21 02:13:54 PM PDT 24
Finished May 21 02:14:08 PM PDT 24
Peak memory 218284 kb
Host smart-8e45072c-23ac-4998-80b0-06e0b0b1de6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840633841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3840633841
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.943541288
Short name T530
Test name
Test status
Simulation time 244458655 ps
CPU time 1.04 seconds
Started May 21 02:13:48 PM PDT 24
Finished May 21 02:13:55 PM PDT 24
Peak memory 217568 kb
Host smart-052dbc27-e805-4f28-bf10-1dcf2725e780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943541288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.943541288
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3035363089
Short name T25
Test name
Test status
Simulation time 115148200 ps
CPU time 0.79 seconds
Started May 21 02:13:55 PM PDT 24
Finished May 21 02:14:02 PM PDT 24
Peak memory 200316 kb
Host smart-da76dbaf-25e6-4916-baed-c4a5ad4f2846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035363089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3035363089
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2852619273
Short name T294
Test name
Test status
Simulation time 951254134 ps
CPU time 4.54 seconds
Started May 21 02:13:50 PM PDT 24
Finished May 21 02:14:01 PM PDT 24
Peak memory 200864 kb
Host smart-755a289d-21c6-47ab-a3d2-fd67a3035f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852619273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2852619273
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2464065491
Short name T140
Test name
Test status
Simulation time 144525846 ps
CPU time 1.13 seconds
Started May 21 02:13:47 PM PDT 24
Finished May 21 02:13:55 PM PDT 24
Peak memory 200516 kb
Host smart-2a7d14ce-6277-4a88-a5cb-d4cbd31aee86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464065491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2464065491
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2247581697
Short name T139
Test name
Test status
Simulation time 113200856 ps
CPU time 1.18 seconds
Started May 21 02:13:56 PM PDT 24
Finished May 21 02:14:03 PM PDT 24
Peak memory 200688 kb
Host smart-f2cd3590-fb2c-48be-b459-99176cdef33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247581697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2247581697
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3969621292
Short name T489
Test name
Test status
Simulation time 9951481535 ps
CPU time 33.73 seconds
Started May 21 02:13:55 PM PDT 24
Finished May 21 02:14:35 PM PDT 24
Peak memory 200736 kb
Host smart-35669344-896c-4493-bab3-01785088cbdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969621292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3969621292
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1620963455
Short name T452
Test name
Test status
Simulation time 112618376 ps
CPU time 1.44 seconds
Started May 21 02:13:50 PM PDT 24
Finished May 21 02:13:58 PM PDT 24
Peak memory 200464 kb
Host smart-e05136da-030e-4410-8811-258700427f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620963455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1620963455
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1768044350
Short name T71
Test name
Test status
Simulation time 76788272 ps
CPU time 0.84 seconds
Started May 21 02:13:50 PM PDT 24
Finished May 21 02:13:57 PM PDT 24
Peak memory 200680 kb
Host smart-14180fb6-b21a-4473-af64-d0adc3406985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768044350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1768044350
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.989964706
Short name T209
Test name
Test status
Simulation time 60915182 ps
CPU time 0.76 seconds
Started May 21 02:14:01 PM PDT 24
Finished May 21 02:14:08 PM PDT 24
Peak memory 200332 kb
Host smart-4b6e5d54-658c-49f6-b72d-5a5ac4f19d80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989964706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.989964706
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2100145173
Short name T243
Test name
Test status
Simulation time 1223532060 ps
CPU time 6.22 seconds
Started May 21 02:13:51 PM PDT 24
Finished May 21 02:14:04 PM PDT 24
Peak memory 218076 kb
Host smart-3f9a6b67-0ee9-4fc3-a05b-36bc6331b8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100145173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2100145173
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.834743762
Short name T457
Test name
Test status
Simulation time 245665653 ps
CPU time 1.06 seconds
Started May 21 02:13:51 PM PDT 24
Finished May 21 02:13:59 PM PDT 24
Peak memory 217592 kb
Host smart-aeeb2ca5-0090-4eba-9e36-dc4931bd38d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834743762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.834743762
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2457981333
Short name T197
Test name
Test status
Simulation time 136573958 ps
CPU time 0.82 seconds
Started May 21 02:13:53 PM PDT 24
Finished May 21 02:14:00 PM PDT 24
Peak memory 200332 kb
Host smart-4ab1f757-1e23-47ee-85f0-063e90f2dff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457981333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2457981333
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.4109879482
Short name T338
Test name
Test status
Simulation time 842296989 ps
CPU time 4.19 seconds
Started May 21 02:13:47 PM PDT 24
Finished May 21 02:13:58 PM PDT 24
Peak memory 200724 kb
Host smart-71969a39-cf9b-42a5-89b4-6821e9a157f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109879482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.4109879482
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3250216472
Short name T395
Test name
Test status
Simulation time 141831136 ps
CPU time 1.16 seconds
Started May 21 02:13:53 PM PDT 24
Finished May 21 02:14:00 PM PDT 24
Peak memory 200488 kb
Host smart-06f22bf7-dfd7-4f22-82c1-a8213b851655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250216472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3250216472
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.4097746005
Short name T269
Test name
Test status
Simulation time 188279538 ps
CPU time 1.34 seconds
Started May 21 02:13:49 PM PDT 24
Finished May 21 02:13:57 PM PDT 24
Peak memory 200620 kb
Host smart-47073eb1-5662-417b-abf3-e075d4dbe0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097746005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.4097746005
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3838375011
Short name T477
Test name
Test status
Simulation time 138244189 ps
CPU time 1.18 seconds
Started May 21 02:13:52 PM PDT 24
Finished May 21 02:13:59 PM PDT 24
Peak memory 200292 kb
Host smart-3e1a7d4d-24ea-457d-bcb0-1b2b8e08686c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838375011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3838375011
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.4105653143
Short name T432
Test name
Test status
Simulation time 138453382 ps
CPU time 1.76 seconds
Started May 21 02:13:51 PM PDT 24
Finished May 21 02:13:59 PM PDT 24
Peak memory 200472 kb
Host smart-0d676ad3-1679-4cce-be3a-6e47397fb3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105653143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.4105653143
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.232557654
Short name T4
Test name
Test status
Simulation time 239406035 ps
CPU time 1.43 seconds
Started May 21 02:13:55 PM PDT 24
Finished May 21 02:14:02 PM PDT 24
Peak memory 200412 kb
Host smart-5710d7b3-77a0-490c-bfd6-1569807c1c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232557654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.232557654
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3656532576
Short name T244
Test name
Test status
Simulation time 76401009 ps
CPU time 0.85 seconds
Started May 21 02:13:53 PM PDT 24
Finished May 21 02:14:00 PM PDT 24
Peak memory 200324 kb
Host smart-d18cc353-45d1-4e9b-8021-7078ea818d1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656532576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3656532576
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.3602915844
Short name T539
Test name
Test status
Simulation time 1895002400 ps
CPU time 7.5 seconds
Started May 21 02:13:56 PM PDT 24
Finished May 21 02:14:10 PM PDT 24
Peak memory 218076 kb
Host smart-78ab5238-4a4e-4de5-96fe-cb606cad6901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602915844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.3602915844
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3076256751
Short name T505
Test name
Test status
Simulation time 245566166 ps
CPU time 1.04 seconds
Started May 21 02:14:01 PM PDT 24
Finished May 21 02:14:08 PM PDT 24
Peak memory 217748 kb
Host smart-2416c188-4cd3-4c4c-9bf3-a04174c7c895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076256751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3076256751
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.4095653171
Short name T18
Test name
Test status
Simulation time 189026354 ps
CPU time 1 seconds
Started May 21 02:13:57 PM PDT 24
Finished May 21 02:14:04 PM PDT 24
Peak memory 200352 kb
Host smart-e95b8782-4933-40df-b639-ca8e891e775d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095653171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.4095653171
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.3376863306
Short name T310
Test name
Test status
Simulation time 1380417692 ps
CPU time 5.67 seconds
Started May 21 02:13:54 PM PDT 24
Finished May 21 02:14:05 PM PDT 24
Peak memory 200724 kb
Host smart-868211c5-331f-4656-89dd-aaaeb2bdbeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376863306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3376863306
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1586820879
Short name T130
Test name
Test status
Simulation time 101242977 ps
CPU time 1.01 seconds
Started May 21 02:13:53 PM PDT 24
Finished May 21 02:14:00 PM PDT 24
Peak memory 200476 kb
Host smart-0fbe99cf-d6b1-47c7-bf6a-48df1c4a5250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586820879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1586820879
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2173933328
Short name T351
Test name
Test status
Simulation time 124915488 ps
CPU time 1.2 seconds
Started May 21 02:13:54 PM PDT 24
Finished May 21 02:14:01 PM PDT 24
Peak memory 200636 kb
Host smart-9917f003-7ea9-43a3-ade1-82f38a30a14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173933328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2173933328
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.2202780432
Short name T43
Test name
Test status
Simulation time 5494703809 ps
CPU time 25.18 seconds
Started May 21 02:13:52 PM PDT 24
Finished May 21 02:14:23 PM PDT 24
Peak memory 200828 kb
Host smart-70f82f31-cc01-4cfd-aa8c-ab0c9b3bd3d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202780432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2202780432
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1192103602
Short name T11
Test name
Test status
Simulation time 136953657 ps
CPU time 1.76 seconds
Started May 21 02:13:54 PM PDT 24
Finished May 21 02:14:02 PM PDT 24
Peak memory 200484 kb
Host smart-d9999e1d-ea8a-4862-967f-0f68c22d09ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192103602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1192103602
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3679894766
Short name T123
Test name
Test status
Simulation time 260444002 ps
CPU time 1.47 seconds
Started May 21 02:13:54 PM PDT 24
Finished May 21 02:14:01 PM PDT 24
Peak memory 200680 kb
Host smart-03e6ae05-0616-4abb-ac6b-1397df1cc5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679894766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3679894766
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.1343235199
Short name T162
Test name
Test status
Simulation time 70415900 ps
CPU time 0.78 seconds
Started May 21 02:13:58 PM PDT 24
Finished May 21 02:14:05 PM PDT 24
Peak memory 200308 kb
Host smart-5fd8ba95-43bc-4d2e-bd02-36505208a379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343235199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1343235199
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3835392251
Short name T458
Test name
Test status
Simulation time 2180966337 ps
CPU time 8.11 seconds
Started May 21 02:13:59 PM PDT 24
Finished May 21 02:14:13 PM PDT 24
Peak memory 222168 kb
Host smart-43200088-7088-455c-a65a-3a9ce650143f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835392251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3835392251
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.131747721
Short name T230
Test name
Test status
Simulation time 243695357 ps
CPU time 1.07 seconds
Started May 21 02:13:53 PM PDT 24
Finished May 21 02:14:00 PM PDT 24
Peak memory 217624 kb
Host smart-1f3d402e-c41e-4ab6-a982-87038d837bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131747721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.131747721
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.913895107
Short name T312
Test name
Test status
Simulation time 116198155 ps
CPU time 0.74 seconds
Started May 21 02:14:01 PM PDT 24
Finished May 21 02:14:08 PM PDT 24
Peak memory 200304 kb
Host smart-ef99cec1-f7c0-44de-b3a1-fcd190b497cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913895107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.913895107
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2021264084
Short name T97
Test name
Test status
Simulation time 1505300807 ps
CPU time 5.85 seconds
Started May 21 02:13:57 PM PDT 24
Finished May 21 02:14:08 PM PDT 24
Peak memory 200740 kb
Host smart-e2f32425-9333-4655-b918-31542b225377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021264084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2021264084
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.365667775
Short name T313
Test name
Test status
Simulation time 113233115 ps
CPU time 1.03 seconds
Started May 21 02:13:52 PM PDT 24
Finished May 21 02:13:59 PM PDT 24
Peak memory 200440 kb
Host smart-87b3007c-9afd-4dd9-8f0a-5b86ca7f5bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365667775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.365667775
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1604808556
Short name T227
Test name
Test status
Simulation time 121582403 ps
CPU time 1.21 seconds
Started May 21 02:13:53 PM PDT 24
Finished May 21 02:14:00 PM PDT 24
Peak memory 200676 kb
Host smart-1a26c2e5-76e2-4485-a411-3ae6b270b7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604808556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1604808556
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2091954801
Short name T397
Test name
Test status
Simulation time 6778701524 ps
CPU time 31.47 seconds
Started May 21 02:14:01 PM PDT 24
Finished May 21 02:14:38 PM PDT 24
Peak memory 209028 kb
Host smart-a237b201-a1fd-4d90-bd63-90c5ef8b2465
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091954801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2091954801
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.1120119680
Short name T374
Test name
Test status
Simulation time 139828871 ps
CPU time 1.81 seconds
Started May 21 02:13:56 PM PDT 24
Finished May 21 02:14:03 PM PDT 24
Peak memory 208712 kb
Host smart-c8811588-fbd9-4cd1-a0de-f222988db945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120119680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1120119680
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2781664116
Short name T325
Test name
Test status
Simulation time 122664667 ps
CPU time 1.16 seconds
Started May 21 02:13:56 PM PDT 24
Finished May 21 02:14:03 PM PDT 24
Peak memory 200524 kb
Host smart-14ac510b-dccd-4649-9eeb-deaeba67a584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781664116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2781664116
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.158792049
Short name T134
Test name
Test status
Simulation time 66898392 ps
CPU time 0.76 seconds
Started May 21 02:14:05 PM PDT 24
Finished May 21 02:14:10 PM PDT 24
Peak memory 200324 kb
Host smart-f081f3b1-42f0-4e5b-ae06-62ba05a5d679
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158792049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.158792049
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2971105514
Short name T456
Test name
Test status
Simulation time 1887340689 ps
CPU time 6.94 seconds
Started May 21 02:14:02 PM PDT 24
Finished May 21 02:14:14 PM PDT 24
Peak memory 218204 kb
Host smart-c425f6bf-aec6-424a-8b09-0ed719fc1147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971105514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2971105514
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.4017180797
Short name T232
Test name
Test status
Simulation time 244109100 ps
CPU time 1.18 seconds
Started May 21 02:14:02 PM PDT 24
Finished May 21 02:14:09 PM PDT 24
Peak memory 217532 kb
Host smart-00d1b2a0-2768-40df-958f-8ee48e8d319c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017180797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.4017180797
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2794794735
Short name T20
Test name
Test status
Simulation time 85830381 ps
CPU time 0.8 seconds
Started May 21 02:13:58 PM PDT 24
Finished May 21 02:14:05 PM PDT 24
Peak memory 200312 kb
Host smart-ee9708c7-f58e-4f6e-b0a0-bc735ca72f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794794735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2794794735
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1817123114
Short name T308
Test name
Test status
Simulation time 2044379973 ps
CPU time 7.89 seconds
Started May 21 02:13:58 PM PDT 24
Finished May 21 02:14:11 PM PDT 24
Peak memory 200652 kb
Host smart-66e3339f-fc3c-4416-ab54-97e473cb5d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817123114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1817123114
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3295146799
Short name T179
Test name
Test status
Simulation time 140363446 ps
CPU time 1.07 seconds
Started May 21 02:14:00 PM PDT 24
Finished May 21 02:14:08 PM PDT 24
Peak memory 200472 kb
Host smart-86a4f197-45ec-449a-ae83-d9326d1f597a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295146799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3295146799
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.4279316715
Short name T256
Test name
Test status
Simulation time 228245387 ps
CPU time 1.54 seconds
Started May 21 02:13:59 PM PDT 24
Finished May 21 02:14:07 PM PDT 24
Peak memory 200728 kb
Host smart-bb25661d-ce4b-40bd-8f1d-07bac841a322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279316715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.4279316715
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.3969514030
Short name T96
Test name
Test status
Simulation time 2105091565 ps
CPU time 8.07 seconds
Started May 21 02:13:59 PM PDT 24
Finished May 21 02:14:13 PM PDT 24
Peak memory 200724 kb
Host smart-8a079271-a99d-431f-b1e7-e4ec105d057d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969514030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3969514030
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.227345097
Short name T496
Test name
Test status
Simulation time 128740858 ps
CPU time 1.71 seconds
Started May 21 02:14:03 PM PDT 24
Finished May 21 02:14:10 PM PDT 24
Peak memory 200504 kb
Host smart-ed2c77c7-2459-47b8-8fb2-7d7bff7fb245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227345097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.227345097
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2505098763
Short name T178
Test name
Test status
Simulation time 166648102 ps
CPU time 1.21 seconds
Started May 21 02:14:02 PM PDT 24
Finished May 21 02:14:08 PM PDT 24
Peak memory 200672 kb
Host smart-b2e32d45-67ba-4bd7-ac2d-21226df608c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505098763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2505098763
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.2434884033
Short name T262
Test name
Test status
Simulation time 77903446 ps
CPU time 0.87 seconds
Started May 21 02:13:59 PM PDT 24
Finished May 21 02:14:06 PM PDT 24
Peak memory 200304 kb
Host smart-cbb4db06-017f-4b27-b91a-bee0a03ae902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434884033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2434884033
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.53203839
Short name T534
Test name
Test status
Simulation time 2357458051 ps
CPU time 8.31 seconds
Started May 21 02:14:00 PM PDT 24
Finished May 21 02:14:14 PM PDT 24
Peak memory 222380 kb
Host smart-1ea6c4d0-bdbf-46f3-89c7-f10bacf4c22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53203839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.53203839
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.294153346
Short name T239
Test name
Test status
Simulation time 244194332 ps
CPU time 1.11 seconds
Started May 21 02:14:00 PM PDT 24
Finished May 21 02:14:07 PM PDT 24
Peak memory 217596 kb
Host smart-ceee6d4e-da34-44f1-b722-0e71472a8431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294153346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.294153346
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3739639323
Short name T16
Test name
Test status
Simulation time 99324820 ps
CPU time 0.89 seconds
Started May 21 02:14:00 PM PDT 24
Finished May 21 02:14:07 PM PDT 24
Peak memory 200308 kb
Host smart-1020ca0b-1f7a-4ed1-a40a-6db07c6793b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739639323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3739639323
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.757541459
Short name T253
Test name
Test status
Simulation time 1485751644 ps
CPU time 5.59 seconds
Started May 21 02:14:05 PM PDT 24
Finished May 21 02:14:15 PM PDT 24
Peak memory 200640 kb
Host smart-596fe482-2a53-4ce8-8be9-f9458c1c6ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757541459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.757541459
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2678523980
Short name T250
Test name
Test status
Simulation time 182069874 ps
CPU time 1.19 seconds
Started May 21 02:14:01 PM PDT 24
Finished May 21 02:14:08 PM PDT 24
Peak memory 200484 kb
Host smart-22dd7e9b-2134-43a1-9788-b337b960ec74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678523980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2678523980
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.4055455232
Short name T501
Test name
Test status
Simulation time 248739820 ps
CPU time 1.51 seconds
Started May 21 02:14:05 PM PDT 24
Finished May 21 02:14:11 PM PDT 24
Peak memory 200600 kb
Host smart-e47ab2fa-5b56-460a-84d9-4f14bbbe532b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055455232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.4055455232
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1974970035
Short name T442
Test name
Test status
Simulation time 3247672870 ps
CPU time 12.32 seconds
Started May 21 02:14:03 PM PDT 24
Finished May 21 02:14:21 PM PDT 24
Peak memory 209024 kb
Host smart-126c8329-33f3-40f1-9054-c4b817422a85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974970035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1974970035
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2161111605
Short name T515
Test name
Test status
Simulation time 546567680 ps
CPU time 2.98 seconds
Started May 21 02:14:00 PM PDT 24
Finished May 21 02:14:08 PM PDT 24
Peak memory 200472 kb
Host smart-afd4dbff-f723-4155-b3a2-5c6cbfcc0fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161111605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2161111605
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2080591004
Short name T283
Test name
Test status
Simulation time 103397776 ps
CPU time 1.04 seconds
Started May 21 02:14:00 PM PDT 24
Finished May 21 02:14:08 PM PDT 24
Peak memory 200488 kb
Host smart-3e2b8731-bca4-40d5-94b2-a726511e168a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080591004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2080591004
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2644539502
Short name T536
Test name
Test status
Simulation time 72410014 ps
CPU time 0.74 seconds
Started May 21 02:14:06 PM PDT 24
Finished May 21 02:14:12 PM PDT 24
Peak memory 200324 kb
Host smart-59c3aad5-2408-40ce-abbf-698d99bc5d40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644539502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2644539502
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2492463862
Short name T514
Test name
Test status
Simulation time 1884337723 ps
CPU time 7.3 seconds
Started May 21 02:14:08 PM PDT 24
Finished May 21 02:14:20 PM PDT 24
Peak memory 217140 kb
Host smart-dfe104b8-980a-4c71-a03a-1adba7a717b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492463862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2492463862
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.458780900
Short name T245
Test name
Test status
Simulation time 244665990 ps
CPU time 1.07 seconds
Started May 21 02:14:08 PM PDT 24
Finished May 21 02:14:14 PM PDT 24
Peak memory 217608 kb
Host smart-7e65abab-4c7e-424f-83f9-d7d984743536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458780900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.458780900
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.941461619
Short name T320
Test name
Test status
Simulation time 95492639 ps
CPU time 0.75 seconds
Started May 21 02:14:02 PM PDT 24
Finished May 21 02:14:09 PM PDT 24
Peak memory 200280 kb
Host smart-0dda990e-31b0-49f7-a127-7d5ca16683e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941461619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.941461619
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.1826126001
Short name T468
Test name
Test status
Simulation time 1877174194 ps
CPU time 6.6 seconds
Started May 21 02:14:07 PM PDT 24
Finished May 21 02:14:19 PM PDT 24
Peak memory 200600 kb
Host smart-4e73642d-5049-4cd6-8d38-cc7ac5709c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826126001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1826126001
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.598773898
Short name T436
Test name
Test status
Simulation time 180373801 ps
CPU time 1.26 seconds
Started May 21 02:14:00 PM PDT 24
Finished May 21 02:14:07 PM PDT 24
Peak memory 200524 kb
Host smart-85fdeeba-fd98-4d12-9f38-083eaba51fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598773898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.598773898
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2608455309
Short name T454
Test name
Test status
Simulation time 189956790 ps
CPU time 1.3 seconds
Started May 21 02:14:04 PM PDT 24
Finished May 21 02:14:11 PM PDT 24
Peak memory 200600 kb
Host smart-54ef15d4-4cf5-4b66-a147-20c31d5b3cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608455309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2608455309
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2434166839
Short name T437
Test name
Test status
Simulation time 4880899504 ps
CPU time 23.52 seconds
Started May 21 02:14:04 PM PDT 24
Finished May 21 02:14:33 PM PDT 24
Peak memory 200828 kb
Host smart-09c481af-24f5-4503-9439-5e912ea694d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434166839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2434166839
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3966586677
Short name T334
Test name
Test status
Simulation time 295149447 ps
CPU time 2.04 seconds
Started May 21 02:13:59 PM PDT 24
Finished May 21 02:14:07 PM PDT 24
Peak memory 208608 kb
Host smart-26b33487-4fc8-4780-8a17-80a4b335616e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966586677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3966586677
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3425936419
Short name T345
Test name
Test status
Simulation time 172873309 ps
CPU time 1.2 seconds
Started May 21 02:14:03 PM PDT 24
Finished May 21 02:14:10 PM PDT 24
Peak memory 200680 kb
Host smart-a45d8e8f-d9a4-4b92-9e51-4a0cf1d9d1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425936419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3425936419
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3424110037
Short name T219
Test name
Test status
Simulation time 80563897 ps
CPU time 0.79 seconds
Started May 21 02:12:25 PM PDT 24
Finished May 21 02:12:28 PM PDT 24
Peak memory 200304 kb
Host smart-ad67f951-1dbf-4f2a-9577-73e39b89d071
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424110037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3424110037
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.4044578046
Short name T48
Test name
Test status
Simulation time 2353708593 ps
CPU time 8.98 seconds
Started May 21 02:12:26 PM PDT 24
Finished May 21 02:12:37 PM PDT 24
Peak memory 222364 kb
Host smart-61b1ff21-e682-402f-abde-9aeee9ae8bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044578046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.4044578046
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3014284900
Short name T290
Test name
Test status
Simulation time 244083271 ps
CPU time 1.09 seconds
Started May 21 02:12:26 PM PDT 24
Finished May 21 02:12:29 PM PDT 24
Peak memory 217576 kb
Host smart-b77f47a7-d995-48e3-a1c8-1d5f8774b7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014284900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3014284900
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3981733553
Short name T389
Test name
Test status
Simulation time 131364423 ps
CPU time 0.81 seconds
Started May 21 02:12:25 PM PDT 24
Finished May 21 02:12:28 PM PDT 24
Peak memory 200288 kb
Host smart-708dcb7d-044f-43d4-b1b4-be5579de9c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981733553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3981733553
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1827518506
Short name T122
Test name
Test status
Simulation time 1487216230 ps
CPU time 5.55 seconds
Started May 21 02:12:26 PM PDT 24
Finished May 21 02:12:33 PM PDT 24
Peak memory 200752 kb
Host smart-53fe898b-2904-4a75-9ce3-871770312725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827518506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1827518506
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1589612210
Short name T409
Test name
Test status
Simulation time 182071109 ps
CPU time 1.23 seconds
Started May 21 02:12:28 PM PDT 24
Finished May 21 02:12:31 PM PDT 24
Peak memory 200504 kb
Host smart-e9fd4342-09c1-4ddb-b750-80a40477f93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589612210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1589612210
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2601777948
Short name T189
Test name
Test status
Simulation time 235369461 ps
CPU time 1.51 seconds
Started May 21 02:12:24 PM PDT 24
Finished May 21 02:12:28 PM PDT 24
Peak memory 200616 kb
Host smart-81c9e8a6-e348-40e9-9659-f66e501f770a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601777948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2601777948
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2861980201
Short name T93
Test name
Test status
Simulation time 4035980299 ps
CPU time 19.59 seconds
Started May 21 02:12:25 PM PDT 24
Finished May 21 02:12:46 PM PDT 24
Peak memory 210600 kb
Host smart-6e6323c2-e32a-42c2-8933-48278fd9695f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861980201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2861980201
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.2047033451
Short name T417
Test name
Test status
Simulation time 140452978 ps
CPU time 1.94 seconds
Started May 21 02:12:22 PM PDT 24
Finished May 21 02:12:27 PM PDT 24
Peak memory 200452 kb
Host smart-9b703afb-a998-4980-adc5-b5cbd210983d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047033451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.2047033451
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.4249236
Short name T521
Test name
Test status
Simulation time 116071921 ps
CPU time 1.03 seconds
Started May 21 02:12:30 PM PDT 24
Finished May 21 02:12:33 PM PDT 24
Peak memory 200440 kb
Host smart-b9d22799-0908-4c48-accf-059259c50e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.4249236
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2310115332
Short name T166
Test name
Test status
Simulation time 60954600 ps
CPU time 0.73 seconds
Started May 21 02:12:30 PM PDT 24
Finished May 21 02:12:34 PM PDT 24
Peak memory 200320 kb
Host smart-bdfc9a3c-6a25-41f7-a1c9-dd831101a8d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310115332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2310115332
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1235575724
Short name T418
Test name
Test status
Simulation time 1233156420 ps
CPU time 5.95 seconds
Started May 21 02:12:30 PM PDT 24
Finished May 21 02:12:38 PM PDT 24
Peak memory 222208 kb
Host smart-a4bdcac0-b150-4647-bc98-49dcc864aa81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235575724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1235575724
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2900402024
Short name T380
Test name
Test status
Simulation time 245023932 ps
CPU time 1.1 seconds
Started May 21 02:12:32 PM PDT 24
Finished May 21 02:12:36 PM PDT 24
Peak memory 217736 kb
Host smart-bd6a9ea2-69e7-49ac-bd95-9c579d7523f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900402024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2900402024
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.4287175227
Short name T193
Test name
Test status
Simulation time 106772257 ps
CPU time 0.76 seconds
Started May 21 02:12:29 PM PDT 24
Finished May 21 02:12:33 PM PDT 24
Peak memory 200232 kb
Host smart-c80ee586-c05f-4028-ae7d-84c9291ef39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287175227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.4287175227
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.732719901
Short name T445
Test name
Test status
Simulation time 1124249293 ps
CPU time 4.92 seconds
Started May 21 02:12:32 PM PDT 24
Finished May 21 02:12:39 PM PDT 24
Peak memory 200704 kb
Host smart-958b9613-6c79-4460-b45d-3d3f21a77ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732719901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.732719901
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.683560173
Short name T523
Test name
Test status
Simulation time 144033561 ps
CPU time 1.19 seconds
Started May 21 02:12:28 PM PDT 24
Finished May 21 02:12:31 PM PDT 24
Peak memory 200536 kb
Host smart-a7b106b8-7ab1-46f7-9500-e76414323ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683560173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.683560173
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.131088962
Short name T495
Test name
Test status
Simulation time 122999183 ps
CPU time 1.13 seconds
Started May 21 02:12:28 PM PDT 24
Finished May 21 02:12:31 PM PDT 24
Peak memory 200700 kb
Host smart-2b81ec62-58a2-4e6d-851a-2baf21594490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131088962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.131088962
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1739215810
Short name T255
Test name
Test status
Simulation time 6023657860 ps
CPU time 19.38 seconds
Started May 21 02:12:31 PM PDT 24
Finished May 21 02:12:53 PM PDT 24
Peak memory 200824 kb
Host smart-64b76a20-d98e-49fb-9a10-55b95be27022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739215810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1739215810
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.2754640391
Short name T423
Test name
Test status
Simulation time 68702608 ps
CPU time 0.8 seconds
Started May 21 02:12:38 PM PDT 24
Finished May 21 02:12:43 PM PDT 24
Peak memory 200504 kb
Host smart-15c3dc5a-6e59-4e33-a658-9a4c3846431e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754640391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2754640391
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3671929129
Short name T416
Test name
Test status
Simulation time 83281818 ps
CPU time 0.8 seconds
Started May 21 02:12:31 PM PDT 24
Finished May 21 02:12:35 PM PDT 24
Peak memory 200280 kb
Host smart-712a824c-8a73-48c0-b8eb-b4051bfe2891
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671929129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3671929129
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1307842765
Short name T27
Test name
Test status
Simulation time 1217743791 ps
CPU time 6.09 seconds
Started May 21 02:12:34 PM PDT 24
Finished May 21 02:12:45 PM PDT 24
Peak memory 218160 kb
Host smart-4077c1d6-8a1a-4cfe-afa3-5ba84af5549b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307842765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1307842765
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3400416987
Short name T210
Test name
Test status
Simulation time 244412601 ps
CPU time 1.09 seconds
Started May 21 02:12:35 PM PDT 24
Finished May 21 02:12:41 PM PDT 24
Peak memory 217580 kb
Host smart-b9eb15a6-c05a-4508-b6a1-cdc15773ed0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400416987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3400416987
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.3432136567
Short name T352
Test name
Test status
Simulation time 95153597 ps
CPU time 0.79 seconds
Started May 21 02:12:33 PM PDT 24
Finished May 21 02:12:36 PM PDT 24
Peak memory 200484 kb
Host smart-36b8e233-7a27-417e-8ec7-5e8c2e37be9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432136567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3432136567
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.60397544
Short name T165
Test name
Test status
Simulation time 1190286043 ps
CPU time 4.78 seconds
Started May 21 02:12:30 PM PDT 24
Finished May 21 02:12:37 PM PDT 24
Peak memory 200684 kb
Host smart-a836f1f4-c6cd-457b-b2d2-2a055b69d4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60397544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.60397544
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.4003719936
Short name T426
Test name
Test status
Simulation time 181736261 ps
CPU time 1.19 seconds
Started May 21 02:12:30 PM PDT 24
Finished May 21 02:12:33 PM PDT 24
Peak memory 200520 kb
Host smart-7812f3bd-6db2-4bfb-869f-2aac79d3b1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003719936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.4003719936
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3277324199
Short name T211
Test name
Test status
Simulation time 201699267 ps
CPU time 1.41 seconds
Started May 21 02:12:30 PM PDT 24
Finished May 21 02:12:34 PM PDT 24
Peak memory 200672 kb
Host smart-92209599-90b3-4579-a626-36db432f487f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277324199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3277324199
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.592480675
Short name T540
Test name
Test status
Simulation time 355113910 ps
CPU time 2.12 seconds
Started May 21 02:12:32 PM PDT 24
Finished May 21 02:12:38 PM PDT 24
Peak memory 200668 kb
Host smart-869f3e23-ad30-40a0-a6b6-8214a1309d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592480675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.592480675
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1106361099
Short name T451
Test name
Test status
Simulation time 128445263 ps
CPU time 1.03 seconds
Started May 21 02:12:33 PM PDT 24
Finished May 21 02:12:37 PM PDT 24
Peak memory 200476 kb
Host smart-0ef0ad28-9be9-4434-9b69-81c54125ef03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106361099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1106361099
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.480282401
Short name T65
Test name
Test status
Simulation time 72453351 ps
CPU time 0.86 seconds
Started May 21 02:12:29 PM PDT 24
Finished May 21 02:12:33 PM PDT 24
Peak memory 200304 kb
Host smart-aa5966c7-83a2-41f9-a7c4-147114b119c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480282401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.480282401
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.398910499
Short name T399
Test name
Test status
Simulation time 1219338873 ps
CPU time 5.5 seconds
Started May 21 02:12:30 PM PDT 24
Finished May 21 02:12:39 PM PDT 24
Peak memory 217120 kb
Host smart-b3acf596-2975-4649-9013-77e18d55676c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398910499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.398910499
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1772849396
Short name T142
Test name
Test status
Simulation time 244525473 ps
CPU time 1.13 seconds
Started May 21 02:12:27 PM PDT 24
Finished May 21 02:12:30 PM PDT 24
Peak memory 217580 kb
Host smart-4c452703-3d13-4a43-945c-997f61bd26c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772849396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1772849396
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2991968501
Short name T23
Test name
Test status
Simulation time 177915877 ps
CPU time 0.87 seconds
Started May 21 02:12:31 PM PDT 24
Finished May 21 02:12:34 PM PDT 24
Peak memory 200308 kb
Host smart-b17be5bc-f65f-464a-b229-c4339eccdf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991968501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2991968501
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3095409584
Short name T420
Test name
Test status
Simulation time 1034420215 ps
CPU time 6.06 seconds
Started May 21 02:12:28 PM PDT 24
Finished May 21 02:12:36 PM PDT 24
Peak memory 200664 kb
Host smart-7f1579f7-6827-42cd-bf02-5f5ec810651d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095409584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3095409584
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2192367039
Short name T382
Test name
Test status
Simulation time 154332763 ps
CPU time 1.11 seconds
Started May 21 02:12:29 PM PDT 24
Finished May 21 02:12:33 PM PDT 24
Peak memory 200488 kb
Host smart-14039bde-fac0-4b4c-8461-27b085c86baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192367039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2192367039
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.1315693870
Short name T301
Test name
Test status
Simulation time 120616133 ps
CPU time 1.16 seconds
Started May 21 02:12:31 PM PDT 24
Finished May 21 02:12:35 PM PDT 24
Peak memory 200620 kb
Host smart-adbbfca0-b6eb-4590-9c94-66222c5dbdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315693870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1315693870
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.3139490866
Short name T92
Test name
Test status
Simulation time 9734355250 ps
CPU time 31.83 seconds
Started May 21 02:12:34 PM PDT 24
Finished May 21 02:13:10 PM PDT 24
Peak memory 209076 kb
Host smart-098944eb-dfa9-4785-8d86-b3010cfdfe50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139490866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3139490866
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.241434377
Short name T236
Test name
Test status
Simulation time 328333843 ps
CPU time 2.21 seconds
Started May 21 02:12:29 PM PDT 24
Finished May 21 02:12:34 PM PDT 24
Peak memory 200464 kb
Host smart-f97817f8-16c4-4a7d-863c-7956b0e0f77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241434377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.241434377
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2577309759
Short name T434
Test name
Test status
Simulation time 130574138 ps
CPU time 1.02 seconds
Started May 21 02:12:29 PM PDT 24
Finished May 21 02:12:33 PM PDT 24
Peak memory 200508 kb
Host smart-e704c115-b7bd-4922-b3ba-66b3dac0299b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577309759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2577309759
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.1180694934
Short name T212
Test name
Test status
Simulation time 82326741 ps
CPU time 0.81 seconds
Started May 21 02:12:34 PM PDT 24
Finished May 21 02:12:38 PM PDT 24
Peak memory 200336 kb
Host smart-89e45f02-d927-4c4d-aa48-0a7432d5248e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180694934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1180694934
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3479628745
Short name T171
Test name
Test status
Simulation time 245694689 ps
CPU time 1.1 seconds
Started May 21 02:12:28 PM PDT 24
Finished May 21 02:12:31 PM PDT 24
Peak memory 217584 kb
Host smart-d02d44c2-f364-467e-ade3-03e522c9084f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479628745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3479628745
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2050160311
Short name T22
Test name
Test status
Simulation time 152288600 ps
CPU time 0.95 seconds
Started May 21 02:12:28 PM PDT 24
Finished May 21 02:12:30 PM PDT 24
Peak memory 200228 kb
Host smart-d10d8589-d9f3-46e8-9df5-887375a54dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050160311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2050160311
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3612325326
Short name T388
Test name
Test status
Simulation time 1805540607 ps
CPU time 6.6 seconds
Started May 21 02:12:30 PM PDT 24
Finished May 21 02:12:39 PM PDT 24
Peak memory 200676 kb
Host smart-7e0d876d-c2aa-4b44-904e-0232a452e3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612325326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3612325326
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1568626791
Short name T196
Test name
Test status
Simulation time 105284170 ps
CPU time 1 seconds
Started May 21 02:12:29 PM PDT 24
Finished May 21 02:12:32 PM PDT 24
Peak memory 200520 kb
Host smart-71d858f9-e847-49a1-aba9-a31aa4ea1c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568626791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1568626791
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.3499847701
Short name T33
Test name
Test status
Simulation time 118566143 ps
CPU time 1.26 seconds
Started May 21 02:12:32 PM PDT 24
Finished May 21 02:12:36 PM PDT 24
Peak memory 200716 kb
Host smart-2e2c463e-c2e1-4a31-8f64-ed3b17816ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499847701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3499847701
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3398000716
Short name T541
Test name
Test status
Simulation time 9584781092 ps
CPU time 33.98 seconds
Started May 21 02:12:29 PM PDT 24
Finished May 21 02:13:06 PM PDT 24
Peak memory 210764 kb
Host smart-121617d2-9839-4b94-85ee-cf225dbf51e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398000716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3398000716
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2800143360
Short name T145
Test name
Test status
Simulation time 143117691 ps
CPU time 1.73 seconds
Started May 21 02:12:34 PM PDT 24
Finished May 21 02:12:40 PM PDT 24
Peak memory 200508 kb
Host smart-1b5029d4-867d-4610-91df-b35f73d5cb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800143360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2800143360
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.323443284
Short name T272
Test name
Test status
Simulation time 105617164 ps
CPU time 0.88 seconds
Started May 21 02:12:32 PM PDT 24
Finished May 21 02:12:36 PM PDT 24
Peak memory 200492 kb
Host smart-c8f8212e-e586-4997-83dc-80e210ecfab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323443284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.323443284
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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