Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7634

1

T3

65

T5

18

T6

26

auto[1]

10521

1

T1

4

T3

79

T5

1

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5662	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6159	1			T1	2		T2	1		T3	50
reset_info_cp[2]	2795	1			T1	1		T3	22		T6	5
reset_info_cp[4]	3620	1			T1	1		T3	33		T6	12
reset_info_cp[8]	104	1			T3	2		T5	1		T6	1
reset_info_cp[16]	112	1			T6	1		T13	1		T21	1
reset_info_cp[32]	107	1			T3	1		T13	1		T35	1
reset_info_cp[64]	113	1			T5	4		T6	1		T10	1
reset_info_cp[128]	103	1			T5	1		T6	1		T13	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2976	1			T3	23		T6	12		T10	12
reset_info_cp[1]	auto[1]	2563	1			T1	1		T3	26		T6	9
reset_info_cp[2]	auto[0]	846	1			T3	6		T6	3		T10	4
reset_info_cp[2]	auto[1]	1949	1			T1	1		T3	16		T6	2
reset_info_cp[4]	auto[0]	1256	1			T3	16		T6	5		T10	5
reset_info_cp[4]	auto[1]	2364	1			T1	1		T3	17		T6	7
reset_info_cp[8]	auto[0]	47	1			T3	1		T5	1		T6	1
reset_info_cp[8]	auto[1]	57	1			T3	1		T13	1		T35	2
reset_info_cp[16]	auto[0]	47	1			T6	1		T23	1		T37	1
reset_info_cp[16]	auto[1]	65	1			T13	1		T21	1		T35	2
reset_info_cp[32]	auto[0]	49	1			T13	1		T47	1		T96	1
reset_info_cp[32]	auto[1]	58	1			T3	1		T35	1		T36	1
reset_info_cp[64]	auto[0]	43	1			T5	4		T6	1		T10	1
reset_info_cp[64]	auto[1]	70	1			T21	3		T35	2		T36	1
reset_info_cp[128]	auto[0]	42	1			T5	1		T13	1		T22	1
reset_info_cp[128]	auto[1]	61	1			T6	1		T21	2		T89	2