Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T536 /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.4204253436 May 23 02:56:54 PM PDT 24 May 23 02:56:57 PM PDT 24 311660214 ps
T537 /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.4000690243 May 23 02:55:37 PM PDT 24 May 23 02:55:40 PM PDT 24 244203518 ps
T538 /workspace/coverage/default/0.rstmgr_sw_rst.1080318449 May 23 02:54:32 PM PDT 24 May 23 02:54:37 PM PDT 24 510290271 ps
T539 /workspace/coverage/default/12.rstmgr_reset.2703878760 May 23 02:55:07 PM PDT 24 May 23 02:55:15 PM PDT 24 1220250777 ps
T540 /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3674097530 May 23 02:55:58 PM PDT 24 May 23 02:56:03 PM PDT 24 134730363 ps
T62 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.61925856 May 23 03:35:14 PM PDT 24 May 23 03:35:23 PM PDT 24 878917550 ps
T66 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2584137959 May 23 03:35:10 PM PDT 24 May 23 03:35:17 PM PDT 24 112860858 ps
T67 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.274726721 May 23 03:34:56 PM PDT 24 May 23 03:35:01 PM PDT 24 330166812 ps
T63 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.283105461 May 23 03:35:09 PM PDT 24 May 23 03:35:15 PM PDT 24 207277706 ps
T64 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.828508170 May 23 03:34:52 PM PDT 24 May 23 03:34:55 PM PDT 24 98610884 ps
T65 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2558539949 May 23 03:35:09 PM PDT 24 May 23 03:35:16 PM PDT 24 467361678 ps
T98 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.129903986 May 23 03:35:10 PM PDT 24 May 23 03:35:16 PM PDT 24 151791504 ps
T68 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2724107346 May 23 03:35:14 PM PDT 24 May 23 03:35:21 PM PDT 24 124278126 ps
T69 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.33274155 May 23 03:35:08 PM PDT 24 May 23 03:35:14 PM PDT 24 188903838 ps
T99 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3541281252 May 23 03:34:51 PM PDT 24 May 23 03:34:53 PM PDT 24 125108942 ps
T78 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2256305652 May 23 03:35:13 PM PDT 24 May 23 03:35:19 PM PDT 24 105533350 ps
T84 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1372407273 May 23 03:34:54 PM PDT 24 May 23 03:34:58 PM PDT 24 414655691 ps
T100 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3456363000 May 23 03:35:08 PM PDT 24 May 23 03:35:14 PM PDT 24 126525114 ps
T79 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2100911742 May 23 03:34:54 PM PDT 24 May 23 03:35:00 PM PDT 24 892462406 ps
T80 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1484121576 May 23 03:35:12 PM PDT 24 May 23 03:35:19 PM PDT 24 101356488 ps
T81 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3400530237 May 23 03:35:11 PM PDT 24 May 23 03:35:22 PM PDT 24 658999913 ps
T82 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2161423170 May 23 03:35:08 PM PDT 24 May 23 03:35:15 PM PDT 24 365115784 ps
T83 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2034742824 May 23 03:35:06 PM PDT 24 May 23 03:35:11 PM PDT 24 443943743 ps
T85 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2644146338 May 23 03:35:09 PM PDT 24 May 23 03:35:17 PM PDT 24 179314948 ps
T125 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2829298922 May 23 03:34:56 PM PDT 24 May 23 03:35:02 PM PDT 24 272956005 ps
T101 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.555855027 May 23 03:35:07 PM PDT 24 May 23 03:35:11 PM PDT 24 143023719 ps
T102 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.405425456 May 23 03:34:55 PM PDT 24 May 23 03:35:00 PM PDT 24 198774107 ps
T541 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1261063353 May 23 03:35:10 PM PDT 24 May 23 03:35:17 PM PDT 24 199162574 ps
T542 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1402051404 May 23 03:35:10 PM PDT 24 May 23 03:35:16 PM PDT 24 114538231 ps
T543 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3445711729 May 23 03:35:07 PM PDT 24 May 23 03:35:11 PM PDT 24 78115791 ps
T544 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1253352541 May 23 03:35:08 PM PDT 24 May 23 03:35:14 PM PDT 24 200120264 ps
T545 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2752011752 May 23 03:35:06 PM PDT 24 May 23 03:35:10 PM PDT 24 192605727 ps
T546 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.358749205 May 23 03:35:12 PM PDT 24 May 23 03:35:22 PM PDT 24 508527895 ps
T547 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3215968456 May 23 03:35:10 PM PDT 24 May 23 03:35:17 PM PDT 24 422109381 ps
T103 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3550506738 May 23 03:35:11 PM PDT 24 May 23 03:35:18 PM PDT 24 146858630 ps
T548 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.580930455 May 23 03:34:51 PM PDT 24 May 23 03:34:53 PM PDT 24 150777307 ps
T549 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3897234608 May 23 03:34:54 PM PDT 24 May 23 03:35:01 PM PDT 24 928369092 ps
T114 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.35044584 May 23 03:35:06 PM PDT 24 May 23 03:35:11 PM PDT 24 485527578 ps
T550 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3777939411 May 23 03:35:09 PM PDT 24 May 23 03:35:15 PM PDT 24 138777771 ps
T551 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.908865844 May 23 03:34:57 PM PDT 24 May 23 03:35:00 PM PDT 24 128274534 ps
T104 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.651802082 May 23 03:35:08 PM PDT 24 May 23 03:35:12 PM PDT 24 81457128 ps
T552 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.44569248 May 23 03:35:09 PM PDT 24 May 23 03:35:15 PM PDT 24 500157470 ps
T553 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.472933055 May 23 03:34:55 PM PDT 24 May 23 03:35:00 PM PDT 24 333577310 ps
T108 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1004112743 May 23 03:35:10 PM PDT 24 May 23 03:35:18 PM PDT 24 778832690 ps
T554 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2607867566 May 23 03:35:06 PM PDT 24 May 23 03:35:10 PM PDT 24 104233678 ps
T555 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1210074273 May 23 03:35:07 PM PDT 24 May 23 03:35:12 PM PDT 24 494537076 ps
T556 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1687056386 May 23 03:34:56 PM PDT 24 May 23 03:35:00 PM PDT 24 205958913 ps
T105 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.259355875 May 23 03:35:08 PM PDT 24 May 23 03:35:13 PM PDT 24 82771891 ps
T557 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2761468964 May 23 03:35:06 PM PDT 24 May 23 03:35:09 PM PDT 24 132118142 ps
T106 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3338105097 May 23 03:35:12 PM PDT 24 May 23 03:35:19 PM PDT 24 101155778 ps
T558 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.603572105 May 23 03:35:09 PM PDT 24 May 23 03:35:14 PM PDT 24 71915976 ps
T559 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2033538753 May 23 03:35:14 PM PDT 24 May 23 03:35:21 PM PDT 24 225940628 ps
T560 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1321375899 May 23 03:35:07 PM PDT 24 May 23 03:35:11 PM PDT 24 132241301 ps
T561 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3597955472 May 23 03:34:53 PM PDT 24 May 23 03:34:56 PM PDT 24 99151564 ps
T562 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3294172690 May 23 03:34:53 PM PDT 24 May 23 03:34:56 PM PDT 24 179777654 ps
T563 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.126744881 May 23 03:35:06 PM PDT 24 May 23 03:35:10 PM PDT 24 126406243 ps
T564 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3681599058 May 23 03:35:08 PM PDT 24 May 23 03:35:13 PM PDT 24 60149552 ps
T565 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.683881679 May 23 03:35:08 PM PDT 24 May 23 03:35:13 PM PDT 24 227363867 ps
T566 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.331863357 May 23 03:35:08 PM PDT 24 May 23 03:35:14 PM PDT 24 114068266 ps
T567 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3117862813 May 23 03:34:54 PM PDT 24 May 23 03:35:00 PM PDT 24 438742876 ps
T568 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.924697706 May 23 03:35:06 PM PDT 24 May 23 03:35:09 PM PDT 24 74153604 ps
T569 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4069483061 May 23 03:34:56 PM PDT 24 May 23 03:35:01 PM PDT 24 365034628 ps
T570 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1878874991 May 23 03:35:10 PM PDT 24 May 23 03:35:16 PM PDT 24 67403332 ps
T571 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1974294087 May 23 03:35:06 PM PDT 24 May 23 03:35:13 PM PDT 24 479237133 ps
T572 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1240429012 May 23 03:35:08 PM PDT 24 May 23 03:35:12 PM PDT 24 69031636 ps
T113 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.561231550 May 23 03:35:14 PM PDT 24 May 23 03:35:22 PM PDT 24 772379505 ps
T573 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3553981126 May 23 03:34:53 PM PDT 24 May 23 03:34:57 PM PDT 24 138997062 ps
T574 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3125621751 May 23 03:34:52 PM PDT 24 May 23 03:34:56 PM PDT 24 155075178 ps
T575 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.381138457 May 23 03:34:53 PM PDT 24 May 23 03:34:57 PM PDT 24 128827155 ps
T576 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2664597814 May 23 03:35:13 PM PDT 24 May 23 03:35:21 PM PDT 24 147568146 ps
T577 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2903718778 May 23 03:35:12 PM PDT 24 May 23 03:35:19 PM PDT 24 191829101 ps
T578 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1459540815 May 23 03:35:06 PM PDT 24 May 23 03:35:12 PM PDT 24 353656400 ps
T110 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.75283570 May 23 03:34:53 PM PDT 24 May 23 03:34:58 PM PDT 24 796664870 ps
T579 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1521301619 May 23 03:35:09 PM PDT 24 May 23 03:35:15 PM PDT 24 436583738 ps
T580 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1299333811 May 23 03:34:53 PM PDT 24 May 23 03:34:55 PM PDT 24 91524835 ps
T581 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1597814403 May 23 03:34:52 PM PDT 24 May 23 03:34:58 PM PDT 24 781791298 ps
T582 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3274042259 May 23 03:34:53 PM PDT 24 May 23 03:34:56 PM PDT 24 85649951 ps
T583 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3995162118 May 23 03:35:09 PM PDT 24 May 23 03:35:13 PM PDT 24 72572162 ps
T111 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2554006139 May 23 03:35:11 PM PDT 24 May 23 03:35:19 PM PDT 24 401450988 ps
T584 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1254968719 May 23 03:35:10 PM PDT 24 May 23 03:35:17 PM PDT 24 133707538 ps
T585 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.545234524 May 23 03:34:55 PM PDT 24 May 23 03:34:59 PM PDT 24 179691574 ps
T586 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1275012676 May 23 03:35:11 PM PDT 24 May 23 03:35:18 PM PDT 24 182527994 ps
T587 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2978372390 May 23 03:35:08 PM PDT 24 May 23 03:35:12 PM PDT 24 118230290 ps
T588 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.194757808 May 23 03:35:08 PM PDT 24 May 23 03:35:13 PM PDT 24 137409811 ps
T589 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1311042564 May 23 03:34:55 PM PDT 24 May 23 03:34:59 PM PDT 24 78526668 ps
T112 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3834115760 May 23 03:35:08 PM PDT 24 May 23 03:35:16 PM PDT 24 870538967 ps
T590 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2953062349 May 23 03:34:51 PM PDT 24 May 23 03:34:54 PM PDT 24 192821419 ps
T591 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2985760090 May 23 03:34:57 PM PDT 24 May 23 03:35:00 PM PDT 24 65067663 ps
T592 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3634551519 May 23 03:34:55 PM PDT 24 May 23 03:34:59 PM PDT 24 61773699 ps
T593 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3651789357 May 23 03:35:08 PM PDT 24 May 23 03:35:14 PM PDT 24 465941732 ps
T594 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3964100940 May 23 03:35:12 PM PDT 24 May 23 03:35:19 PM PDT 24 65105786 ps
T595 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3280065733 May 23 03:35:07 PM PDT 24 May 23 03:35:11 PM PDT 24 69952340 ps
T596 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.47266399 May 23 03:35:08 PM PDT 24 May 23 03:35:14 PM PDT 24 170623653 ps
T597 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3114517098 May 23 03:35:12 PM PDT 24 May 23 03:35:19 PM PDT 24 59860433 ps
T598 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.55220892 May 23 03:34:54 PM PDT 24 May 23 03:34:57 PM PDT 24 72166124 ps
T599 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3600712686 May 23 03:34:54 PM PDT 24 May 23 03:34:59 PM PDT 24 307704793 ps
T600 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3997084968 May 23 03:34:52 PM PDT 24 May 23 03:34:56 PM PDT 24 785913032 ps
T601 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1387712553 May 23 03:35:06 PM PDT 24 May 23 03:35:10 PM PDT 24 93737323 ps
T602 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1323637077 May 23 03:34:51 PM PDT 24 May 23 03:34:54 PM PDT 24 193105740 ps
T603 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.396989532 May 23 03:35:10 PM PDT 24 May 23 03:35:17 PM PDT 24 61032606 ps
T604 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1736165208 May 23 03:35:10 PM PDT 24 May 23 03:35:19 PM PDT 24 779904424 ps
T123 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3597254910 May 23 03:35:10 PM PDT 24 May 23 03:35:18 PM PDT 24 923706149 ps
T605 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2465863111 May 23 03:35:12 PM PDT 24 May 23 03:35:19 PM PDT 24 99992387 ps
T606 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3627244884 May 23 03:34:54 PM PDT 24 May 23 03:35:06 PM PDT 24 1551131597 ps
T124 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1181853249 May 23 03:35:06 PM PDT 24 May 23 03:35:11 PM PDT 24 1075463506 ps
T607 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.526676500 May 23 03:35:14 PM PDT 24 May 23 03:35:24 PM PDT 24 519457566 ps
T608 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1398655464 May 23 03:35:08 PM PDT 24 May 23 03:35:15 PM PDT 24 354443333 ps
T609 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3137068053 May 23 03:35:12 PM PDT 24 May 23 03:35:19 PM PDT 24 66241960 ps
T109 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1242306678 May 23 03:35:08 PM PDT 24 May 23 03:35:15 PM PDT 24 869791188 ps
T610 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.113637619 May 23 03:34:51 PM PDT 24 May 23 03:34:55 PM PDT 24 154772688 ps
T611 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2169877247 May 23 03:35:06 PM PDT 24 May 23 03:35:10 PM PDT 24 116731188 ps
T612 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2649351997 May 23 03:34:55 PM PDT 24 May 23 03:34:59 PM PDT 24 147741946 ps
T613 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3026372417 May 23 03:35:06 PM PDT 24 May 23 03:35:09 PM PDT 24 77281792 ps
T614 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.4023391484 May 23 03:35:07 PM PDT 24 May 23 03:35:12 PM PDT 24 230076850 ps
T615 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3345469717 May 23 03:35:07 PM PDT 24 May 23 03:35:10 PM PDT 24 64788727 ps
T616 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2331352086 May 23 03:35:05 PM PDT 24 May 23 03:35:10 PM PDT 24 489038339 ps
T617 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.555883528 May 23 03:35:08 PM PDT 24 May 23 03:35:12 PM PDT 24 60740514 ps
T618 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3065823104 May 23 03:34:52 PM PDT 24 May 23 03:35:03 PM PDT 24 1539215137 ps
T619 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2872197513 May 23 03:35:06 PM PDT 24 May 23 03:35:10 PM PDT 24 133789408 ps
T620 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1676492587 May 23 03:35:06 PM PDT 24 May 23 03:35:09 PM PDT 24 76873144 ps

Test location /workspace/coverage/default/17.rstmgr_stress_all.1739661317
Short name T3
Test name
Test status
Simulation time 5527326980 ps
CPU time 21.02 seconds
Started May 23 02:55:36 PM PDT 24
Finished May 23 02:55:59 PM PDT 24
Peak memory 201032 kb
Host smart-8ce488ff-aaf7-4432-8a7f-14d82669d65b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739661317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1739661317
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3154891941
Short name T55
Test name
Test status
Simulation time 154906644 ps
CPU time 1.87 seconds
Started May 23 02:55:41 PM PDT 24
Finished May 23 02:55:46 PM PDT 24
Peak memory 200472 kb
Host smart-00e403dc-ae9d-4084-b550-9788ee51e298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154891941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3154891941
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.33274155
Short name T69
Test name
Test status
Simulation time 188903838 ps
CPU time 1.8 seconds
Started May 23 03:35:08 PM PDT 24
Finished May 23 03:35:14 PM PDT 24
Peak memory 208948 kb
Host smart-db6f5d84-a63d-45ae-8ac8-7e212923a05b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33274155 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.33274155
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2792802750
Short name T33
Test name
Test status
Simulation time 17221415618 ps
CPU time 26.17 seconds
Started May 23 02:54:30 PM PDT 24
Finished May 23 02:54:58 PM PDT 24
Peak memory 217668 kb
Host smart-a5b0bb9c-9f94-416a-a199-b4f2fb8c7eea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792802750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2792802750
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1982958763
Short name T21
Test name
Test status
Simulation time 1219073337 ps
CPU time 5.93 seconds
Started May 23 02:56:20 PM PDT 24
Finished May 23 02:56:28 PM PDT 24
Peak memory 222140 kb
Host smart-2bb85944-c1e7-465f-80c3-e09966e9f8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982958763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1982958763
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2100911742
Short name T79
Test name
Test status
Simulation time 892462406 ps
CPU time 3.08 seconds
Started May 23 03:34:54 PM PDT 24
Finished May 23 03:35:00 PM PDT 24
Peak memory 200784 kb
Host smart-1ec9d998-4456-46af-80de-8cfa9573c43a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100911742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2100911742
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2311194105
Short name T121
Test name
Test status
Simulation time 258828956 ps
CPU time 1.58 seconds
Started May 23 02:55:10 PM PDT 24
Finished May 23 02:55:14 PM PDT 24
Peak memory 200420 kb
Host smart-149a3325-e55b-4b0a-99e5-eb5ebcaff1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311194105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2311194105
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.1422835623
Short name T72
Test name
Test status
Simulation time 104862703 ps
CPU time 0.85 seconds
Started May 23 02:56:13 PM PDT 24
Finished May 23 02:56:16 PM PDT 24
Peak memory 200312 kb
Host smart-2bc2e7ec-47e1-452f-a0d7-2a6587f80b48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422835623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.1422835623
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1706800437
Short name T152
Test name
Test status
Simulation time 154371169 ps
CPU time 1.16 seconds
Started May 23 02:54:31 PM PDT 24
Finished May 23 02:54:33 PM PDT 24
Peak memory 200444 kb
Host smart-69019ffc-c82d-4785-8048-97dee6d18137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706800437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1706800437
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.458079325
Short name T39
Test name
Test status
Simulation time 2353634735 ps
CPU time 8.51 seconds
Started May 23 02:54:42 PM PDT 24
Finished May 23 02:54:52 PM PDT 24
Peak memory 218104 kb
Host smart-20ece615-4063-4bc8-9b82-4633d8c62dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458079325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.458079325
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2967944460
Short name T13
Test name
Test status
Simulation time 4305389095 ps
CPU time 19.04 seconds
Started May 23 02:54:31 PM PDT 24
Finished May 23 02:54:52 PM PDT 24
Peak memory 209004 kb
Host smart-9950cbab-1079-4867-a96f-eb46aae13749
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967944460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2967944460
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2607867566
Short name T554
Test name
Test status
Simulation time 104233678 ps
CPU time 1.41 seconds
Started May 23 03:35:06 PM PDT 24
Finished May 23 03:35:10 PM PDT 24
Peak memory 200528 kb
Host smart-74666919-438b-4b4b-898f-3ba3f3cada46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607867566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2607867566
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2706221576
Short name T28
Test name
Test status
Simulation time 1220216339 ps
CPU time 5.9 seconds
Started May 23 02:55:38 PM PDT 24
Finished May 23 02:55:47 PM PDT 24
Peak memory 218124 kb
Host smart-66fb85e6-bfb0-4b99-a5de-47f353bda51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706221576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2706221576
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1242306678
Short name T109
Test name
Test status
Simulation time 869791188 ps
CPU time 3.39 seconds
Started May 23 03:35:08 PM PDT 24
Finished May 23 03:35:15 PM PDT 24
Peak memory 200732 kb
Host smart-a3fd4d0d-59a1-4910-a78c-5bbfd0486b88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242306678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1242306678
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.75283570
Short name T110
Test name
Test status
Simulation time 796664870 ps
CPU time 2.66 seconds
Started May 23 03:34:53 PM PDT 24
Finished May 23 03:34:58 PM PDT 24
Peak memory 200692 kb
Host smart-ab330ec9-3488-4879-abc7-cc24cc410a82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75283570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.75283570
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3541281252
Short name T99
Test name
Test status
Simulation time 125108942 ps
CPU time 1.06 seconds
Started May 23 03:34:51 PM PDT 24
Finished May 23 03:34:53 PM PDT 24
Peak memory 200408 kb
Host smart-48e099ba-1958-403e-a3f1-ba8a6a49ba90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541281252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3541281252
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2591157731
Short name T2
Test name
Test status
Simulation time 121817392 ps
CPU time 0.86 seconds
Started May 23 02:55:12 PM PDT 24
Finished May 23 02:55:15 PM PDT 24
Peak memory 200320 kb
Host smart-0c10c68a-92f3-46f8-8fb1-28d86d3feeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591157731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2591157731
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2475225065
Short name T178
Test name
Test status
Simulation time 244737928 ps
CPU time 1.15 seconds
Started May 23 02:54:30 PM PDT 24
Finished May 23 02:54:33 PM PDT 24
Peak memory 217556 kb
Host smart-9e0ff137-267d-4286-ae5a-fd203b88e1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475225065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2475225065
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1372407273
Short name T84
Test name
Test status
Simulation time 414655691 ps
CPU time 1.73 seconds
Started May 23 03:34:54 PM PDT 24
Finished May 23 03:34:58 PM PDT 24
Peak memory 200604 kb
Host smart-645c8fb1-ba99-4995-996d-ed68ef2a126f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372407273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1372407273
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4069483061
Short name T569
Test name
Test status
Simulation time 365034628 ps
CPU time 2.55 seconds
Started May 23 03:34:56 PM PDT 24
Finished May 23 03:35:01 PM PDT 24
Peak memory 200560 kb
Host smart-5282b9af-a678-44bc-9fe0-9bc77eb9a68e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069483061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.4
069483061
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3065823104
Short name T618
Test name
Test status
Simulation time 1539215137 ps
CPU time 8.46 seconds
Started May 23 03:34:52 PM PDT 24
Finished May 23 03:35:03 PM PDT 24
Peak memory 200528 kb
Host smart-0cc46c5c-b943-4180-802a-05dbb590ddd5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065823104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
065823104
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.381138457
Short name T575
Test name
Test status
Simulation time 128827155 ps
CPU time 0.9 seconds
Started May 23 03:34:53 PM PDT 24
Finished May 23 03:34:57 PM PDT 24
Peak memory 200340 kb
Host smart-938e17bb-a6fa-45a5-8ba7-d4a8a839da57
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381138457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.381138457
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3294172690
Short name T562
Test name
Test status
Simulation time 179777654 ps
CPU time 1.15 seconds
Started May 23 03:34:53 PM PDT 24
Finished May 23 03:34:56 PM PDT 24
Peak memory 208744 kb
Host smart-04d9cb37-0547-42cf-aaab-5892d21be15c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294172690 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.3294172690
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.55220892
Short name T598
Test name
Test status
Simulation time 72166124 ps
CPU time 0.86 seconds
Started May 23 03:34:54 PM PDT 24
Finished May 23 03:34:57 PM PDT 24
Peak memory 200368 kb
Host smart-4f1caf62-06b0-4251-b90b-1d7010b6af96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55220892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.55220892
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.472933055
Short name T553
Test name
Test status
Simulation time 333577310 ps
CPU time 2.32 seconds
Started May 23 03:34:55 PM PDT 24
Finished May 23 03:35:00 PM PDT 24
Peak memory 216832 kb
Host smart-a53690ff-e000-4aa5-984b-35f8c481cc38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472933055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.472933055
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3997084968
Short name T600
Test name
Test status
Simulation time 785913032 ps
CPU time 3.03 seconds
Started May 23 03:34:52 PM PDT 24
Finished May 23 03:34:56 PM PDT 24
Peak memory 200620 kb
Host smart-f70c9438-7786-4deb-b5ed-17778c2dec9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997084968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.3997084968
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3125621751
Short name T574
Test name
Test status
Simulation time 155075178 ps
CPU time 1.98 seconds
Started May 23 03:34:52 PM PDT 24
Finished May 23 03:34:56 PM PDT 24
Peak memory 200568 kb
Host smart-67254d20-3128-48dc-8f67-6c4bf77f748e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125621751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
125621751
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3627244884
Short name T606
Test name
Test status
Simulation time 1551131597 ps
CPU time 8.07 seconds
Started May 23 03:34:54 PM PDT 24
Finished May 23 03:35:06 PM PDT 24
Peak memory 200604 kb
Host smart-6204945a-16a9-443a-abf6-240462d14f2c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627244884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
627244884
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.580930455
Short name T548
Test name
Test status
Simulation time 150777307 ps
CPU time 0.97 seconds
Started May 23 03:34:51 PM PDT 24
Finished May 23 03:34:53 PM PDT 24
Peak memory 200348 kb
Host smart-21a096bd-9830-481d-8d9a-ac49cb247e05
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580930455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.580930455
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.908865844
Short name T551
Test name
Test status
Simulation time 128274534 ps
CPU time 0.99 seconds
Started May 23 03:34:57 PM PDT 24
Finished May 23 03:35:00 PM PDT 24
Peak memory 200476 kb
Host smart-4fb93ce8-5885-4597-b02c-e8af345c38c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908865844 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.908865844
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2985760090
Short name T591
Test name
Test status
Simulation time 65067663 ps
CPU time 0.81 seconds
Started May 23 03:34:57 PM PDT 24
Finished May 23 03:35:00 PM PDT 24
Peak memory 200360 kb
Host smart-d8c41132-381e-4b2c-a8db-b0fb1074b80d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985760090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2985760090
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3553981126
Short name T573
Test name
Test status
Simulation time 138997062 ps
CPU time 1.11 seconds
Started May 23 03:34:53 PM PDT 24
Finished May 23 03:34:57 PM PDT 24
Peak memory 200400 kb
Host smart-677d4a79-b8cc-4720-973a-5562e2c71875
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553981126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3553981126
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1323637077
Short name T602
Test name
Test status
Simulation time 193105740 ps
CPU time 1.5 seconds
Started May 23 03:34:51 PM PDT 24
Finished May 23 03:34:54 PM PDT 24
Peak memory 200604 kb
Host smart-41e1e6d1-66cb-4f7b-9d41-9bb385b6aa2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323637077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1323637077
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1402051404
Short name T542
Test name
Test status
Simulation time 114538231 ps
CPU time 1.11 seconds
Started May 23 03:35:10 PM PDT 24
Finished May 23 03:35:16 PM PDT 24
Peak memory 210872 kb
Host smart-9ab31ea5-16c5-4f0b-b1e4-5c5d33afc599
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402051404 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1402051404
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1240429012
Short name T572
Test name
Test status
Simulation time 69031636 ps
CPU time 0.77 seconds
Started May 23 03:35:08 PM PDT 24
Finished May 23 03:35:12 PM PDT 24
Peak memory 200296 kb
Host smart-37d444c3-16e9-49b9-9ff2-0139cfee2ee5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240429012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1240429012
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1676492587
Short name T620
Test name
Test status
Simulation time 76873144 ps
CPU time 0.91 seconds
Started May 23 03:35:06 PM PDT 24
Finished May 23 03:35:09 PM PDT 24
Peak memory 200424 kb
Host smart-2a93cae5-1aaa-4f62-bc94-20eb7247164a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676492587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1676492587
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2161423170
Short name T82
Test name
Test status
Simulation time 365115784 ps
CPU time 2.74 seconds
Started May 23 03:35:08 PM PDT 24
Finished May 23 03:35:15 PM PDT 24
Peak memory 216856 kb
Host smart-1cb45c5d-4ee7-4b19-80fa-77bb6cdfc108
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161423170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2161423170
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.44569248
Short name T552
Test name
Test status
Simulation time 500157470 ps
CPU time 1.9 seconds
Started May 23 03:35:09 PM PDT 24
Finished May 23 03:35:15 PM PDT 24
Peak memory 200588 kb
Host smart-6a67c9dc-8444-496f-a514-d02c84530cc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44569248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err.44569248
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2978372390
Short name T587
Test name
Test status
Simulation time 118230290 ps
CPU time 1.07 seconds
Started May 23 03:35:08 PM PDT 24
Finished May 23 03:35:12 PM PDT 24
Peak memory 200448 kb
Host smart-a454a0ae-8244-4bde-9318-c6170bbcf9c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978372390 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2978372390
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.924697706
Short name T568
Test name
Test status
Simulation time 74153604 ps
CPU time 0.86 seconds
Started May 23 03:35:06 PM PDT 24
Finished May 23 03:35:09 PM PDT 24
Peak memory 200344 kb
Host smart-b824ff28-0ce3-41c1-a7e3-09e7fd1e0b41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924697706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.924697706
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.651802082
Short name T104
Test name
Test status
Simulation time 81457128 ps
CPU time 1.04 seconds
Started May 23 03:35:08 PM PDT 24
Finished May 23 03:35:12 PM PDT 24
Peak memory 200436 kb
Host smart-115ee4be-5be2-4ae8-b09c-7493ad741e9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651802082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sa
me_csr_outstanding.651802082
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.331863357
Short name T566
Test name
Test status
Simulation time 114068266 ps
CPU time 1.62 seconds
Started May 23 03:35:08 PM PDT 24
Finished May 23 03:35:14 PM PDT 24
Peak memory 208772 kb
Host smart-70c3383e-1048-4f16-ac5c-24e03fb8c0bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331863357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.331863357
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1321375899
Short name T560
Test name
Test status
Simulation time 132241301 ps
CPU time 1 seconds
Started May 23 03:35:07 PM PDT 24
Finished May 23 03:35:11 PM PDT 24
Peak memory 200404 kb
Host smart-a429c359-c692-46ef-a1ee-352edc2b680e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321375899 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1321375899
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.555883528
Short name T617
Test name
Test status
Simulation time 60740514 ps
CPU time 0.79 seconds
Started May 23 03:35:08 PM PDT 24
Finished May 23 03:35:12 PM PDT 24
Peak memory 200380 kb
Host smart-2365f736-91b8-4941-bede-90103d3e580c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555883528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.555883528
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.194757808
Short name T588
Test name
Test status
Simulation time 137409811 ps
CPU time 1.2 seconds
Started May 23 03:35:08 PM PDT 24
Finished May 23 03:35:13 PM PDT 24
Peak memory 200428 kb
Host smart-14d28418-03ea-4531-a565-4577ba36e4f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194757808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.194757808
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.35044584
Short name T114
Test name
Test status
Simulation time 485527578 ps
CPU time 1.95 seconds
Started May 23 03:35:06 PM PDT 24
Finished May 23 03:35:11 PM PDT 24
Peak memory 200752 kb
Host smart-b70d7618-9fe1-40b2-8eda-97355a2b1627
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35044584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err.35044584
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3280065733
Short name T595
Test name
Test status
Simulation time 69952340 ps
CPU time 0.8 seconds
Started May 23 03:35:07 PM PDT 24
Finished May 23 03:35:11 PM PDT 24
Peak memory 200372 kb
Host smart-6d203b5e-b51b-4eda-b2cb-5dd7df090f9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280065733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3280065733
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2872197513
Short name T619
Test name
Test status
Simulation time 133789408 ps
CPU time 1.25 seconds
Started May 23 03:35:06 PM PDT 24
Finished May 23 03:35:10 PM PDT 24
Peak memory 200612 kb
Host smart-7b8a70e5-8ac2-46dc-a334-4aaf15ecd416
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872197513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2872197513
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.358749205
Short name T546
Test name
Test status
Simulation time 508527895 ps
CPU time 3.85 seconds
Started May 23 03:35:12 PM PDT 24
Finished May 23 03:35:22 PM PDT 24
Peak memory 212376 kb
Host smart-d5c08533-9ae6-45b9-be27-ebbf08be89da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358749205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.358749205
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1210074273
Short name T555
Test name
Test status
Simulation time 494537076 ps
CPU time 1.97 seconds
Started May 23 03:35:07 PM PDT 24
Finished May 23 03:35:12 PM PDT 24
Peak memory 200652 kb
Host smart-95d6ae86-1ae0-49ca-aa9c-88c33facb2eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210074273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1210074273
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1387712553
Short name T601
Test name
Test status
Simulation time 93737323 ps
CPU time 0.92 seconds
Started May 23 03:35:06 PM PDT 24
Finished May 23 03:35:10 PM PDT 24
Peak memory 200412 kb
Host smart-bd0bced6-b3a7-41da-8afb-2d36a99e0b14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387712553 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.1387712553
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1878874991
Short name T570
Test name
Test status
Simulation time 67403332 ps
CPU time 0.76 seconds
Started May 23 03:35:10 PM PDT 24
Finished May 23 03:35:16 PM PDT 24
Peak memory 200304 kb
Host smart-2497642e-b5e4-4dbc-9a44-7f7611d33b54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878874991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1878874991
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.4023391484
Short name T614
Test name
Test status
Simulation time 230076850 ps
CPU time 1.52 seconds
Started May 23 03:35:07 PM PDT 24
Finished May 23 03:35:12 PM PDT 24
Peak memory 200604 kb
Host smart-462bc7cc-bf26-4a0e-aadc-e66fdc9e8bcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023391484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.4023391484
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2169877247
Short name T611
Test name
Test status
Simulation time 116731188 ps
CPU time 1.57 seconds
Started May 23 03:35:06 PM PDT 24
Finished May 23 03:35:10 PM PDT 24
Peak memory 210756 kb
Host smart-7b4d5f58-fc93-4f64-a21f-bb9eebb8ef5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169877247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2169877247
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1181853249
Short name T124
Test name
Test status
Simulation time 1075463506 ps
CPU time 3.22 seconds
Started May 23 03:35:06 PM PDT 24
Finished May 23 03:35:11 PM PDT 24
Peak memory 200640 kb
Host smart-912db6ec-649c-4826-b2d6-21d5d18c2ac8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181853249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1181853249
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1261063353
Short name T541
Test name
Test status
Simulation time 199162574 ps
CPU time 1.34 seconds
Started May 23 03:35:10 PM PDT 24
Finished May 23 03:35:17 PM PDT 24
Peak memory 211656 kb
Host smart-7742f8cb-db8b-41f5-ba4d-83c9d7703cd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261063353 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1261063353
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3681599058
Short name T564
Test name
Test status
Simulation time 60149552 ps
CPU time 0.79 seconds
Started May 23 03:35:08 PM PDT 24
Finished May 23 03:35:13 PM PDT 24
Peak memory 200324 kb
Host smart-b84407e5-454c-4322-922c-8416b8b67c03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681599058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3681599058
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.129903986
Short name T98
Test name
Test status
Simulation time 151791504 ps
CPU time 1.14 seconds
Started May 23 03:35:10 PM PDT 24
Finished May 23 03:35:16 PM PDT 24
Peak memory 200396 kb
Host smart-d7ae63f3-e181-46ae-8fad-43648f9b4fe3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129903986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.129903986
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.47266399
Short name T596
Test name
Test status
Simulation time 170623653 ps
CPU time 1.44 seconds
Started May 23 03:35:08 PM PDT 24
Finished May 23 03:35:14 PM PDT 24
Peak memory 208632 kb
Host smart-6426bd4e-8c04-486b-9f8c-8ce30ac16518
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47266399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.47266399
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1521301619
Short name T579
Test name
Test status
Simulation time 436583738 ps
CPU time 1.76 seconds
Started May 23 03:35:09 PM PDT 24
Finished May 23 03:35:15 PM PDT 24
Peak memory 200712 kb
Host smart-4cb2bf28-3cbf-44dd-b85e-99f18dab456a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521301619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1521301619
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1275012676
Short name T586
Test name
Test status
Simulation time 182527994 ps
CPU time 1.19 seconds
Started May 23 03:35:11 PM PDT 24
Finished May 23 03:35:18 PM PDT 24
Peak memory 208732 kb
Host smart-a0fd01aa-3f05-40ea-8971-11306a160c26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275012676 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.1275012676
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.603572105
Short name T558
Test name
Test status
Simulation time 71915976 ps
CPU time 0.82 seconds
Started May 23 03:35:09 PM PDT 24
Finished May 23 03:35:14 PM PDT 24
Peak memory 200320 kb
Host smart-8ae9abbb-8939-4f9d-a925-956580e85a18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603572105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.603572105
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3338105097
Short name T106
Test name
Test status
Simulation time 101155778 ps
CPU time 1.21 seconds
Started May 23 03:35:12 PM PDT 24
Finished May 23 03:35:19 PM PDT 24
Peak memory 200608 kb
Host smart-45f3aa98-1bff-40f8-b108-7bb3bf463857
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338105097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3338105097
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3400530237
Short name T81
Test name
Test status
Simulation time 658999913 ps
CPU time 4.37 seconds
Started May 23 03:35:11 PM PDT 24
Finished May 23 03:35:22 PM PDT 24
Peak memory 216784 kb
Host smart-21567cf3-a106-4b41-8d72-a7dafd637937
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400530237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3400530237
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3215968456
Short name T547
Test name
Test status
Simulation time 422109381 ps
CPU time 1.85 seconds
Started May 23 03:35:10 PM PDT 24
Finished May 23 03:35:17 PM PDT 24
Peak memory 200724 kb
Host smart-cbe43660-409a-4f3e-87b9-16dc2ef81a3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215968456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3215968456
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2724107346
Short name T68
Test name
Test status
Simulation time 124278126 ps
CPU time 1.45 seconds
Started May 23 03:35:14 PM PDT 24
Finished May 23 03:35:21 PM PDT 24
Peak memory 212820 kb
Host smart-0b448211-5374-474b-ba02-913cfe631bb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724107346 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2724107346
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3114517098
Short name T597
Test name
Test status
Simulation time 59860433 ps
CPU time 0.76 seconds
Started May 23 03:35:12 PM PDT 24
Finished May 23 03:35:19 PM PDT 24
Peak memory 200296 kb
Host smart-60b52351-4ee4-4e2d-9880-8d14399797d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114517098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3114517098
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.283105461
Short name T63
Test name
Test status
Simulation time 207277706 ps
CPU time 1.63 seconds
Started May 23 03:35:09 PM PDT 24
Finished May 23 03:35:15 PM PDT 24
Peak memory 200684 kb
Host smart-fe784f72-cbee-47e5-82d4-c1e70c9571bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283105461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.283105461
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2664597814
Short name T576
Test name
Test status
Simulation time 147568146 ps
CPU time 2.29 seconds
Started May 23 03:35:13 PM PDT 24
Finished May 23 03:35:21 PM PDT 24
Peak memory 208816 kb
Host smart-1870e5fe-146e-42c4-9189-78f6025adcbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664597814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2664597814
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2554006139
Short name T111
Test name
Test status
Simulation time 401450988 ps
CPU time 1.75 seconds
Started May 23 03:35:11 PM PDT 24
Finished May 23 03:35:19 PM PDT 24
Peak memory 200708 kb
Host smart-29f0fef4-c921-4edc-a9c5-96871b14eb74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554006139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2554006139
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2256305652
Short name T78
Test name
Test status
Simulation time 105533350 ps
CPU time 0.97 seconds
Started May 23 03:35:13 PM PDT 24
Finished May 23 03:35:19 PM PDT 24
Peak memory 200496 kb
Host smart-4ca3b809-42b5-4862-961e-fbc1e3a32480
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256305652 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2256305652
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3964100940
Short name T594
Test name
Test status
Simulation time 65105786 ps
CPU time 0.81 seconds
Started May 23 03:35:12 PM PDT 24
Finished May 23 03:35:19 PM PDT 24
Peak memory 200364 kb
Host smart-1a467fe7-f6aa-42d3-9de6-d22955239d44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964100940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3964100940
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2033538753
Short name T559
Test name
Test status
Simulation time 225940628 ps
CPU time 1.56 seconds
Started May 23 03:35:14 PM PDT 24
Finished May 23 03:35:21 PM PDT 24
Peak memory 200660 kb
Host smart-8c42dab7-a1ef-48d1-abca-c4b82953e850
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033538753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2033538753
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.526676500
Short name T607
Test name
Test status
Simulation time 519457566 ps
CPU time 3.83 seconds
Started May 23 03:35:14 PM PDT 24
Finished May 23 03:35:24 PM PDT 24
Peak memory 208816 kb
Host smart-16f8b55c-d84e-4dc9-b039-0c4014238eb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526676500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.526676500
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.561231550
Short name T113
Test name
Test status
Simulation time 772379505 ps
CPU time 2.7 seconds
Started May 23 03:35:14 PM PDT 24
Finished May 23 03:35:22 PM PDT 24
Peak memory 200652 kb
Host smart-4679e417-6da3-40bb-9a16-ee7ec4e31942
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561231550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err
.561231550
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2465863111
Short name T605
Test name
Test status
Simulation time 99992387 ps
CPU time 0.91 seconds
Started May 23 03:35:12 PM PDT 24
Finished May 23 03:35:19 PM PDT 24
Peak memory 200476 kb
Host smart-d79d7026-12a0-46d0-949f-bc6e9a53bd76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465863111 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2465863111
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3137068053
Short name T609
Test name
Test status
Simulation time 66241960 ps
CPU time 0.79 seconds
Started May 23 03:35:12 PM PDT 24
Finished May 23 03:35:19 PM PDT 24
Peak memory 200364 kb
Host smart-5b0936ec-58a9-45e8-a6f5-cfb2ba5042d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137068053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3137068053
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.259355875
Short name T105
Test name
Test status
Simulation time 82771891 ps
CPU time 1.04 seconds
Started May 23 03:35:08 PM PDT 24
Finished May 23 03:35:13 PM PDT 24
Peak memory 200388 kb
Host smart-91b2682b-a942-4b1e-9083-2309f16cd70d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259355875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.259355875
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1398655464
Short name T608
Test name
Test status
Simulation time 354443333 ps
CPU time 2.63 seconds
Started May 23 03:35:08 PM PDT 24
Finished May 23 03:35:15 PM PDT 24
Peak memory 208848 kb
Host smart-b210ea6b-3e53-48bd-94ad-28a4b3571153
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398655464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1398655464
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.61925856
Short name T62
Test name
Test status
Simulation time 878917550 ps
CPU time 3.67 seconds
Started May 23 03:35:14 PM PDT 24
Finished May 23 03:35:23 PM PDT 24
Peak memory 200696 kb
Host smart-aae606e3-98cc-49b0-8aa0-5308c72603ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61925856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err.61925856
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1687056386
Short name T556
Test name
Test status
Simulation time 205958913 ps
CPU time 1.55 seconds
Started May 23 03:34:56 PM PDT 24
Finished May 23 03:35:00 PM PDT 24
Peak memory 200604 kb
Host smart-967188a3-055e-4266-8951-c3f14589b78d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687056386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1
687056386
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2829298922
Short name T125
Test name
Test status
Simulation time 272956005 ps
CPU time 3.28 seconds
Started May 23 03:34:56 PM PDT 24
Finished May 23 03:35:02 PM PDT 24
Peak memory 200544 kb
Host smart-2c48f454-9403-4ad6-b770-447759b4eb17
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829298922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
829298922
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3597955472
Short name T561
Test name
Test status
Simulation time 99151564 ps
CPU time 0.82 seconds
Started May 23 03:34:53 PM PDT 24
Finished May 23 03:34:56 PM PDT 24
Peak memory 200268 kb
Host smart-09577b58-09ea-4157-ac83-86b584c9d933
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597955472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
597955472
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.545234524
Short name T585
Test name
Test status
Simulation time 179691574 ps
CPU time 1.15 seconds
Started May 23 03:34:55 PM PDT 24
Finished May 23 03:34:59 PM PDT 24
Peak memory 200492 kb
Host smart-e04ae949-2c19-46be-85af-4cb89a85f5ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545234524 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.545234524
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3274042259
Short name T582
Test name
Test status
Simulation time 85649951 ps
CPU time 0.9 seconds
Started May 23 03:34:53 PM PDT 24
Finished May 23 03:34:56 PM PDT 24
Peak memory 200420 kb
Host smart-9de6bc7c-3fc4-42e6-a066-90681b53f53b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274042259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3274042259
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.405425456
Short name T102
Test name
Test status
Simulation time 198774107 ps
CPU time 1.53 seconds
Started May 23 03:34:55 PM PDT 24
Finished May 23 03:35:00 PM PDT 24
Peak memory 200700 kb
Host smart-3eef8e3c-e386-4e5a-8df4-67a240493a53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405425456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.405425456
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.274726721
Short name T67
Test name
Test status
Simulation time 330166812 ps
CPU time 2.27 seconds
Started May 23 03:34:56 PM PDT 24
Finished May 23 03:35:01 PM PDT 24
Peak memory 208804 kb
Host smart-4252b999-7c57-401b-adfe-d27569c82473
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274726721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.274726721
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.113637619
Short name T610
Test name
Test status
Simulation time 154772688 ps
CPU time 1.95 seconds
Started May 23 03:34:51 PM PDT 24
Finished May 23 03:34:55 PM PDT 24
Peak memory 200552 kb
Host smart-59fb0420-477a-42a5-8f1c-9b2f3b11cda9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113637619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.113637619
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1597814403
Short name T581
Test name
Test status
Simulation time 781791298 ps
CPU time 4.25 seconds
Started May 23 03:34:52 PM PDT 24
Finished May 23 03:34:58 PM PDT 24
Peak memory 200548 kb
Host smart-8c8eccf0-6601-4f28-b98b-81cbecaea114
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597814403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
597814403
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1299333811
Short name T580
Test name
Test status
Simulation time 91524835 ps
CPU time 0.81 seconds
Started May 23 03:34:53 PM PDT 24
Finished May 23 03:34:55 PM PDT 24
Peak memory 200356 kb
Host smart-71482538-a24a-4048-ac39-aad30abcbd6e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299333811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
299333811
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2953062349
Short name T590
Test name
Test status
Simulation time 192821419 ps
CPU time 1.28 seconds
Started May 23 03:34:51 PM PDT 24
Finished May 23 03:34:54 PM PDT 24
Peak memory 200476 kb
Host smart-a745df9e-3670-47f6-a0c3-58830eae2224
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953062349 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2953062349
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3634551519
Short name T592
Test name
Test status
Simulation time 61773699 ps
CPU time 0.82 seconds
Started May 23 03:34:55 PM PDT 24
Finished May 23 03:34:59 PM PDT 24
Peak memory 200344 kb
Host smart-065634da-4dca-48c5-9a46-ccdad08d6a3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634551519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3634551519
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2649351997
Short name T612
Test name
Test status
Simulation time 147741946 ps
CPU time 1.15 seconds
Started May 23 03:34:55 PM PDT 24
Finished May 23 03:34:59 PM PDT 24
Peak memory 200448 kb
Host smart-93814b67-fe0f-4565-be97-111e8ec9bcd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649351997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2649351997
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3600712686
Short name T599
Test name
Test status
Simulation time 307704793 ps
CPU time 2.35 seconds
Started May 23 03:34:54 PM PDT 24
Finished May 23 03:34:59 PM PDT 24
Peak memory 208720 kb
Host smart-69d36809-91bc-4c8f-8900-a975ea8c4a6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600712686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3600712686
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3897234608
Short name T549
Test name
Test status
Simulation time 928369092 ps
CPU time 3.05 seconds
Started May 23 03:34:54 PM PDT 24
Finished May 23 03:35:01 PM PDT 24
Peak memory 200732 kb
Host smart-5f862fbb-4fd1-436e-9ae9-c69cda5d9ba7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897234608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3897234608
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1459540815
Short name T578
Test name
Test status
Simulation time 353656400 ps
CPU time 2.44 seconds
Started May 23 03:35:06 PM PDT 24
Finished May 23 03:35:12 PM PDT 24
Peak memory 200532 kb
Host smart-a6bb70e1-97b6-4daa-bbf0-9f074a787026
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459540815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
459540815
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1974294087
Short name T571
Test name
Test status
Simulation time 479237133 ps
CPU time 5.38 seconds
Started May 23 03:35:06 PM PDT 24
Finished May 23 03:35:13 PM PDT 24
Peak memory 200544 kb
Host smart-a08c8b74-bd3b-44e9-b9b7-75cefca41e2d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974294087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
974294087
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.828508170
Short name T64
Test name
Test status
Simulation time 98610884 ps
CPU time 0.81 seconds
Started May 23 03:34:52 PM PDT 24
Finished May 23 03:34:55 PM PDT 24
Peak memory 200352 kb
Host smart-6d9a493a-3d8d-44c7-8489-25dfd44fecd8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828508170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.828508170
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2752011752
Short name T545
Test name
Test status
Simulation time 192605727 ps
CPU time 1.21 seconds
Started May 23 03:35:06 PM PDT 24
Finished May 23 03:35:10 PM PDT 24
Peak memory 208680 kb
Host smart-07bfc053-43e6-463e-b387-638bbe99d770
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752011752 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2752011752
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1311042564
Short name T589
Test name
Test status
Simulation time 78526668 ps
CPU time 0.87 seconds
Started May 23 03:34:55 PM PDT 24
Finished May 23 03:34:59 PM PDT 24
Peak memory 200360 kb
Host smart-4ee89d85-94b6-436a-9c0f-ca1f1976b5fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311042564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1311042564
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3550506738
Short name T103
Test name
Test status
Simulation time 146858630 ps
CPU time 1.17 seconds
Started May 23 03:35:11 PM PDT 24
Finished May 23 03:35:18 PM PDT 24
Peak memory 200440 kb
Host smart-76302b26-0389-4b45-818f-28b00e4526d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550506738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3550506738
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3117862813
Short name T567
Test name
Test status
Simulation time 438742876 ps
CPU time 3.39 seconds
Started May 23 03:34:54 PM PDT 24
Finished May 23 03:35:00 PM PDT 24
Peak memory 208760 kb
Host smart-7f9a841d-685d-41b2-9022-ded3c9a7da1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117862813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3117862813
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2761468964
Short name T557
Test name
Test status
Simulation time 132118142 ps
CPU time 1.13 seconds
Started May 23 03:35:06 PM PDT 24
Finished May 23 03:35:09 PM PDT 24
Peak memory 200436 kb
Host smart-94258030-fd05-4a7e-80a2-036bacff796b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761468964 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2761468964
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3995162118
Short name T583
Test name
Test status
Simulation time 72572162 ps
CPU time 0.85 seconds
Started May 23 03:35:09 PM PDT 24
Finished May 23 03:35:13 PM PDT 24
Peak memory 200360 kb
Host smart-bf1fc6e2-78e5-4521-b7db-d02fd865a75e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995162118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3995162118
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.126744881
Short name T563
Test name
Test status
Simulation time 126406243 ps
CPU time 1.02 seconds
Started May 23 03:35:06 PM PDT 24
Finished May 23 03:35:10 PM PDT 24
Peak memory 200408 kb
Host smart-699b31d9-0147-4690-b8ff-ac33b1d08fed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126744881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sam
e_csr_outstanding.126744881
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3651789357
Short name T593
Test name
Test status
Simulation time 465941732 ps
CPU time 3 seconds
Started May 23 03:35:08 PM PDT 24
Finished May 23 03:35:14 PM PDT 24
Peak memory 208868 kb
Host smart-9e5702b3-d8d9-447b-852b-8d667fb7f6ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651789357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3651789357
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2558539949
Short name T65
Test name
Test status
Simulation time 467361678 ps
CPU time 1.94 seconds
Started May 23 03:35:09 PM PDT 24
Finished May 23 03:35:16 PM PDT 24
Peak memory 200596 kb
Host smart-574df7cd-e277-47de-a026-a7521443ca62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558539949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2558539949
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2903718778
Short name T577
Test name
Test status
Simulation time 191829101 ps
CPU time 1.3 seconds
Started May 23 03:35:12 PM PDT 24
Finished May 23 03:35:19 PM PDT 24
Peak memory 208680 kb
Host smart-8299129f-2b78-4484-807b-120030299eba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903718778 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2903718778
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.396989532
Short name T603
Test name
Test status
Simulation time 61032606 ps
CPU time 0.81 seconds
Started May 23 03:35:10 PM PDT 24
Finished May 23 03:35:17 PM PDT 24
Peak memory 200324 kb
Host smart-652ce86b-5615-4a81-831c-182a44047842
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396989532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.396989532
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.683881679
Short name T565
Test name
Test status
Simulation time 227363867 ps
CPU time 1.56 seconds
Started May 23 03:35:08 PM PDT 24
Finished May 23 03:35:13 PM PDT 24
Peak memory 200616 kb
Host smart-70212edd-3cbe-4c79-ad29-3d51a8a76589
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683881679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.683881679
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2584137959
Short name T66
Test name
Test status
Simulation time 112860858 ps
CPU time 1.72 seconds
Started May 23 03:35:10 PM PDT 24
Finished May 23 03:35:17 PM PDT 24
Peak memory 208816 kb
Host smart-cfd94dc8-54f7-4403-b239-6f7fde90d949
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584137959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2584137959
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1736165208
Short name T604
Test name
Test status
Simulation time 779904424 ps
CPU time 3.19 seconds
Started May 23 03:35:10 PM PDT 24
Finished May 23 03:35:19 PM PDT 24
Peak memory 200696 kb
Host smart-5b19e2f7-5efa-42b7-97ff-e54a5acf768f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736165208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.1736165208
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3777939411
Short name T550
Test name
Test status
Simulation time 138777771 ps
CPU time 1.5 seconds
Started May 23 03:35:09 PM PDT 24
Finished May 23 03:35:15 PM PDT 24
Peak memory 208916 kb
Host smart-bea8238f-1c94-4fb0-9cf9-cf41e808b7de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777939411 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3777939411
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3026372417
Short name T613
Test name
Test status
Simulation time 77281792 ps
CPU time 0.77 seconds
Started May 23 03:35:06 PM PDT 24
Finished May 23 03:35:09 PM PDT 24
Peak memory 200308 kb
Host smart-0c2e46dc-33f8-4051-86b7-c9d52e496169
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026372417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.3026372417
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3456363000
Short name T100
Test name
Test status
Simulation time 126525114 ps
CPU time 1.24 seconds
Started May 23 03:35:08 PM PDT 24
Finished May 23 03:35:14 PM PDT 24
Peak memory 200568 kb
Host smart-65a5f81d-96c5-4b61-8a73-af03cfff9f98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456363000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3456363000
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2331352086
Short name T616
Test name
Test status
Simulation time 489038339 ps
CPU time 3.36 seconds
Started May 23 03:35:05 PM PDT 24
Finished May 23 03:35:10 PM PDT 24
Peak memory 208788 kb
Host smart-3c7f116a-8dca-47fa-9f4c-17fc1ee3305e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331352086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2331352086
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3834115760
Short name T112
Test name
Test status
Simulation time 870538967 ps
CPU time 3.51 seconds
Started May 23 03:35:08 PM PDT 24
Finished May 23 03:35:16 PM PDT 24
Peak memory 200580 kb
Host smart-cc70794b-4ea5-4286-9e3d-625ed0d00fde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834115760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3834115760
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1253352541
Short name T544
Test name
Test status
Simulation time 200120264 ps
CPU time 1.39 seconds
Started May 23 03:35:08 PM PDT 24
Finished May 23 03:35:14 PM PDT 24
Peak memory 208744 kb
Host smart-2c0dc431-267f-43f2-a211-3adff47a37eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253352541 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1253352541
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3445711729
Short name T543
Test name
Test status
Simulation time 78115791 ps
CPU time 0.79 seconds
Started May 23 03:35:07 PM PDT 24
Finished May 23 03:35:11 PM PDT 24
Peak memory 200304 kb
Host smart-2ea5ca8c-190f-4985-aef5-7c3bd475af35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445711729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3445711729
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1254968719
Short name T584
Test name
Test status
Simulation time 133707538 ps
CPU time 1.07 seconds
Started May 23 03:35:10 PM PDT 24
Finished May 23 03:35:17 PM PDT 24
Peak memory 200448 kb
Host smart-7afa4e8f-16c9-471a-9662-fc4519ebd75b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254968719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.1254968719
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2034742824
Short name T83
Test name
Test status
Simulation time 443943743 ps
CPU time 3.15 seconds
Started May 23 03:35:06 PM PDT 24
Finished May 23 03:35:11 PM PDT 24
Peak memory 216864 kb
Host smart-c2bab2ba-6f35-42db-b198-3ef0c70a92ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034742824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2034742824
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3597254910
Short name T123
Test name
Test status
Simulation time 923706149 ps
CPU time 3.07 seconds
Started May 23 03:35:10 PM PDT 24
Finished May 23 03:35:18 PM PDT 24
Peak memory 200596 kb
Host smart-15a9bb50-bc7b-4c89-9bcd-43875c113462
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597254910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3597254910
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1484121576
Short name T80
Test name
Test status
Simulation time 101356488 ps
CPU time 1.09 seconds
Started May 23 03:35:12 PM PDT 24
Finished May 23 03:35:19 PM PDT 24
Peak memory 216832 kb
Host smart-6607cee5-d8c1-4968-bedc-a9173d5c2d4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484121576 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1484121576
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3345469717
Short name T615
Test name
Test status
Simulation time 64788727 ps
CPU time 0.74 seconds
Started May 23 03:35:07 PM PDT 24
Finished May 23 03:35:10 PM PDT 24
Peak memory 200224 kb
Host smart-bfe94ead-5a16-4eac-b4e0-f0f2e26fe5d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345469717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.3345469717
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.555855027
Short name T101
Test name
Test status
Simulation time 143023719 ps
CPU time 1.28 seconds
Started May 23 03:35:07 PM PDT 24
Finished May 23 03:35:11 PM PDT 24
Peak memory 200648 kb
Host smart-3dd79f4c-116d-4891-b298-eeb1810af67a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555855027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.555855027
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2644146338
Short name T85
Test name
Test status
Simulation time 179314948 ps
CPU time 2.52 seconds
Started May 23 03:35:09 PM PDT 24
Finished May 23 03:35:17 PM PDT 24
Peak memory 208816 kb
Host smart-822a42e3-f6a8-4a19-8573-b3e8206b5ce9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644146338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2644146338
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1004112743
Short name T108
Test name
Test status
Simulation time 778832690 ps
CPU time 2.77 seconds
Started May 23 03:35:10 PM PDT 24
Finished May 23 03:35:18 PM PDT 24
Peak memory 200632 kb
Host smart-0a8faa75-5ad3-4886-98f0-81815e182ce7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004112743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1004112743
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2145568896
Short name T268
Test name
Test status
Simulation time 67150139 ps
CPU time 0.73 seconds
Started May 23 02:54:34 PM PDT 24
Finished May 23 02:54:36 PM PDT 24
Peak memory 200332 kb
Host smart-b5546861-8b82-478f-b7d9-7b66a5678107
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145568896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2145568896
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3261387577
Short name T357
Test name
Test status
Simulation time 1887928558 ps
CPU time 7.84 seconds
Started May 23 02:54:30 PM PDT 24
Finished May 23 02:54:39 PM PDT 24
Peak memory 222264 kb
Host smart-189157a0-7996-44b2-99d3-f9d4dc1dc539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261387577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3261387577
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1233576547
Short name T512
Test name
Test status
Simulation time 244401387 ps
CPU time 1.08 seconds
Started May 23 02:54:30 PM PDT 24
Finished May 23 02:54:33 PM PDT 24
Peak memory 217736 kb
Host smart-9540ca45-3e3e-41af-924c-b56e5aa71db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233576547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1233576547
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.2683251783
Short name T335
Test name
Test status
Simulation time 121322001 ps
CPU time 0.76 seconds
Started May 23 02:54:23 PM PDT 24
Finished May 23 02:54:27 PM PDT 24
Peak memory 200280 kb
Host smart-616f5de8-6306-4585-8d23-b37227c8d31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683251783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2683251783
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1567222398
Short name T488
Test name
Test status
Simulation time 990298549 ps
CPU time 4.97 seconds
Started May 23 02:54:32 PM PDT 24
Finished May 23 02:54:39 PM PDT 24
Peak memory 200652 kb
Host smart-fa229f05-efd2-44d5-9c34-bcdffdcea8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567222398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1567222398
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2605972097
Short name T70
Test name
Test status
Simulation time 16617032701 ps
CPU time 25.91 seconds
Started May 23 02:54:31 PM PDT 24
Finished May 23 02:54:58 PM PDT 24
Peak memory 217548 kb
Host smart-969aca32-9242-4fa8-b81a-3de78ad14755
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605972097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2605972097
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1164477718
Short name T218
Test name
Test status
Simulation time 143655985 ps
CPU time 1.15 seconds
Started May 23 02:54:30 PM PDT 24
Finished May 23 02:54:32 PM PDT 24
Peak memory 200500 kb
Host smart-f8d01ea5-63bb-4414-9c64-1058fb008b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164477718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1164477718
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1065790736
Short name T459
Test name
Test status
Simulation time 112991959 ps
CPU time 1.12 seconds
Started May 23 02:54:23 PM PDT 24
Finished May 23 02:54:27 PM PDT 24
Peak memory 200648 kb
Host smart-b39b9c73-5f89-4b4e-b714-170e31ba2488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065790736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1065790736
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.485499624
Short name T362
Test name
Test status
Simulation time 6665827083 ps
CPU time 24.43 seconds
Started May 23 02:54:30 PM PDT 24
Finished May 23 02:54:56 PM PDT 24
Peak memory 209052 kb
Host smart-552a37d5-a713-4f36-b4da-31a889600cd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485499624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.485499624
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1080318449
Short name T538
Test name
Test status
Simulation time 510290271 ps
CPU time 2.62 seconds
Started May 23 02:54:32 PM PDT 24
Finished May 23 02:54:37 PM PDT 24
Peak memory 200420 kb
Host smart-a5c32251-c477-4c66-a037-cdf8516b098f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080318449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1080318449
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.970388994
Short name T352
Test name
Test status
Simulation time 76774138 ps
CPU time 0.85 seconds
Started May 23 02:54:30 PM PDT 24
Finished May 23 02:54:33 PM PDT 24
Peak memory 200496 kb
Host smart-d7b0d0b0-ef11-42eb-b286-de1ed7e6c32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970388994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.970388994
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.919926031
Short name T389
Test name
Test status
Simulation time 131481115 ps
CPU time 0.88 seconds
Started May 23 02:54:34 PM PDT 24
Finished May 23 02:54:36 PM PDT 24
Peak memory 200332 kb
Host smart-47b96235-5bb9-483a-b88d-55e8b62b98a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919926031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.919926031
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2256056960
Short name T472
Test name
Test status
Simulation time 2171344651 ps
CPU time 8.21 seconds
Started May 23 02:54:27 PM PDT 24
Finished May 23 02:54:37 PM PDT 24
Peak memory 218264 kb
Host smart-acf84b61-9f80-495b-897a-44dee4a49f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256056960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2256056960
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.1687000572
Short name T329
Test name
Test status
Simulation time 83161084 ps
CPU time 0.75 seconds
Started May 23 02:54:29 PM PDT 24
Finished May 23 02:54:31 PM PDT 24
Peak memory 200284 kb
Host smart-28a32b34-e596-4ecc-8422-eec8f568eb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687000572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.1687000572
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3778726137
Short name T88
Test name
Test status
Simulation time 863251358 ps
CPU time 4.43 seconds
Started May 23 02:54:30 PM PDT 24
Finished May 23 02:54:36 PM PDT 24
Peak memory 200636 kb
Host smart-19f9abc0-d888-4f9f-b1f4-0ff47e1655f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778726137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3778726137
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.2000501152
Short name T379
Test name
Test status
Simulation time 113206026 ps
CPU time 1.18 seconds
Started May 23 02:54:30 PM PDT 24
Finished May 23 02:54:32 PM PDT 24
Peak memory 200668 kb
Host smart-dc2edaae-51d6-417e-8a44-0781af76509d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000501152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2000501152
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2030416185
Short name T454
Test name
Test status
Simulation time 402317825 ps
CPU time 2.24 seconds
Started May 23 02:54:30 PM PDT 24
Finished May 23 02:54:34 PM PDT 24
Peak memory 200508 kb
Host smart-26609cff-45b1-4bef-8e31-d57d3ab9f644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030416185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2030416185
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3717023347
Short name T227
Test name
Test status
Simulation time 144247231 ps
CPU time 1.06 seconds
Started May 23 02:54:27 PM PDT 24
Finished May 23 02:54:30 PM PDT 24
Peak memory 200492 kb
Host smart-3cca650b-ce4b-4e75-808a-8ffd1aa5406d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717023347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3717023347
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3382751767
Short name T194
Test name
Test status
Simulation time 109743452 ps
CPU time 0.85 seconds
Started May 23 02:55:07 PM PDT 24
Finished May 23 02:55:09 PM PDT 24
Peak memory 200320 kb
Host smart-8bf669e6-41f4-4244-8e8b-9626d04ae1f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382751767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3382751767
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.594811770
Short name T38
Test name
Test status
Simulation time 2373511760 ps
CPU time 9.1 seconds
Started May 23 02:55:07 PM PDT 24
Finished May 23 02:55:18 PM PDT 24
Peak memory 218236 kb
Host smart-1e650940-96e8-46af-9eeb-451315f116f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594811770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.594811770
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2539674396
Short name T130
Test name
Test status
Simulation time 244699003 ps
CPU time 1.12 seconds
Started May 23 02:55:08 PM PDT 24
Finished May 23 02:55:12 PM PDT 24
Peak memory 217636 kb
Host smart-f532949d-93e8-4699-aec0-266838aba6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539674396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2539674396
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.3730088049
Short name T164
Test name
Test status
Simulation time 180375051 ps
CPU time 0.88 seconds
Started May 23 02:55:09 PM PDT 24
Finished May 23 02:55:12 PM PDT 24
Peak memory 200308 kb
Host smart-b3174e00-42de-4a14-91ea-75ebdf03422f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730088049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3730088049
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3418897537
Short name T10
Test name
Test status
Simulation time 1804423900 ps
CPU time 6.85 seconds
Started May 23 02:55:10 PM PDT 24
Finished May 23 02:55:19 PM PDT 24
Peak memory 200688 kb
Host smart-38804c78-da4f-4588-a385-652206587466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418897537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3418897537
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.167848762
Short name T176
Test name
Test status
Simulation time 97981893 ps
CPU time 0.96 seconds
Started May 23 02:55:11 PM PDT 24
Finished May 23 02:55:14 PM PDT 24
Peak memory 200524 kb
Host smart-d7fba11b-357f-40f6-88b2-0afdd464881b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167848762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.167848762
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2226390832
Short name T521
Test name
Test status
Simulation time 114787604 ps
CPU time 1.35 seconds
Started May 23 02:55:09 PM PDT 24
Finished May 23 02:55:13 PM PDT 24
Peak memory 200664 kb
Host smart-072f18e3-d078-42bf-a8db-d4e5f1bb5939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226390832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2226390832
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2369754228
Short name T212
Test name
Test status
Simulation time 2508347630 ps
CPU time 10.62 seconds
Started May 23 02:55:09 PM PDT 24
Finished May 23 02:55:22 PM PDT 24
Peak memory 200844 kb
Host smart-8731e3f5-971a-4dc0-aec6-c2669883a725
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369754228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2369754228
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.4191529264
Short name T368
Test name
Test status
Simulation time 151705253 ps
CPU time 2.01 seconds
Started May 23 02:55:08 PM PDT 24
Finished May 23 02:55:12 PM PDT 24
Peak memory 200480 kb
Host smart-09f77f66-53c7-43e4-91a1-31ce61d59366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191529264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.4191529264
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2084930175
Short name T264
Test name
Test status
Simulation time 216823699 ps
CPU time 1.25 seconds
Started May 23 02:55:08 PM PDT 24
Finished May 23 02:55:12 PM PDT 24
Peak memory 200472 kb
Host smart-10ad35cc-690b-4bbd-85ad-5af459ca0a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084930175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2084930175
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2335067846
Short name T333
Test name
Test status
Simulation time 88980917 ps
CPU time 0.78 seconds
Started May 23 02:55:06 PM PDT 24
Finished May 23 02:55:08 PM PDT 24
Peak memory 200340 kb
Host smart-a95016e3-5d6b-456c-a2ff-052f229a7807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335067846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2335067846
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1628948172
Short name T51
Test name
Test status
Simulation time 1225081706 ps
CPU time 5.61 seconds
Started May 23 02:55:08 PM PDT 24
Finished May 23 02:55:16 PM PDT 24
Peak memory 217548 kb
Host smart-b5068deb-c2c4-4e8a-aee9-472a87d471db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628948172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1628948172
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2801886918
Short name T507
Test name
Test status
Simulation time 244372489 ps
CPU time 1.07 seconds
Started May 23 02:55:09 PM PDT 24
Finished May 23 02:55:12 PM PDT 24
Peak memory 217724 kb
Host smart-242336f6-692c-4424-b432-169c9da8bc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801886918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.2801886918
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1587325592
Short name T452
Test name
Test status
Simulation time 132166845 ps
CPU time 0.87 seconds
Started May 23 02:55:07 PM PDT 24
Finished May 23 02:55:10 PM PDT 24
Peak memory 200272 kb
Host smart-1b8e67dc-d42e-4a2e-8d91-641a912dd410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587325592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1587325592
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.335648846
Short name T117
Test name
Test status
Simulation time 1694660897 ps
CPU time 6.55 seconds
Started May 23 02:55:11 PM PDT 24
Finished May 23 02:55:20 PM PDT 24
Peak memory 200740 kb
Host smart-42305677-f5f9-452a-92ea-416e81afed93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335648846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.335648846
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.615052361
Short name T180
Test name
Test status
Simulation time 107693301 ps
CPU time 1 seconds
Started May 23 02:55:09 PM PDT 24
Finished May 23 02:55:12 PM PDT 24
Peak memory 200540 kb
Host smart-ef2b8727-1728-46d1-ae57-6a6d186fec1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615052361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.615052361
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3914132729
Short name T471
Test name
Test status
Simulation time 198991520 ps
CPU time 1.48 seconds
Started May 23 02:55:07 PM PDT 24
Finished May 23 02:55:11 PM PDT 24
Peak memory 200728 kb
Host smart-11f85891-0e1b-4b82-b527-a93e1c09db78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914132729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3914132729
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2754927604
Short name T166
Test name
Test status
Simulation time 127039820 ps
CPU time 1.04 seconds
Started May 23 02:55:12 PM PDT 24
Finished May 23 02:55:15 PM PDT 24
Peak memory 200332 kb
Host smart-a447b2d6-c704-49e3-acad-783d4db58471
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754927604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2754927604
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.849348472
Short name T155
Test name
Test status
Simulation time 286066925 ps
CPU time 1.93 seconds
Started May 23 02:55:08 PM PDT 24
Finished May 23 02:55:12 PM PDT 24
Peak memory 200480 kb
Host smart-b26e81e6-0244-4a99-97c3-1689421035ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849348472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.849348472
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.919608142
Short name T377
Test name
Test status
Simulation time 64371022 ps
CPU time 0.75 seconds
Started May 23 02:55:13 PM PDT 24
Finished May 23 02:55:15 PM PDT 24
Peak memory 200332 kb
Host smart-b955482f-dd61-4a86-90bb-e93a03378395
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919608142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.919608142
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3430579352
Short name T426
Test name
Test status
Simulation time 1884791804 ps
CPU time 6.92 seconds
Started May 23 02:55:10 PM PDT 24
Finished May 23 02:55:20 PM PDT 24
Peak memory 222224 kb
Host smart-3015e724-f54a-4044-8c7c-8c893a43b8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430579352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3430579352
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2367456843
Short name T500
Test name
Test status
Simulation time 244734326 ps
CPU time 1.14 seconds
Started May 23 02:55:12 PM PDT 24
Finished May 23 02:55:15 PM PDT 24
Peak memory 217584 kb
Host smart-6f3c6bb2-8ef2-4bab-8275-67324e424acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367456843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2367456843
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2318143291
Short name T313
Test name
Test status
Simulation time 145738114 ps
CPU time 0.89 seconds
Started May 23 02:55:06 PM PDT 24
Finished May 23 02:55:08 PM PDT 24
Peak memory 200328 kb
Host smart-e9de1e36-174c-4d6d-83c9-acbaa5f29638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318143291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2318143291
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2703878760
Short name T539
Test name
Test status
Simulation time 1220250777 ps
CPU time 5.49 seconds
Started May 23 02:55:07 PM PDT 24
Finished May 23 02:55:15 PM PDT 24
Peak memory 200664 kb
Host smart-61926ec3-acf8-4f31-8116-a25eeec7e2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703878760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2703878760
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1422874317
Short name T56
Test name
Test status
Simulation time 93791057 ps
CPU time 0.97 seconds
Started May 23 02:55:09 PM PDT 24
Finished May 23 02:55:12 PM PDT 24
Peak memory 200556 kb
Host smart-b3e4acd6-8d35-4f56-a955-a82af378b38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422874317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1422874317
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.344491098
Short name T484
Test name
Test status
Simulation time 123955552 ps
CPU time 1.21 seconds
Started May 23 02:55:10 PM PDT 24
Finished May 23 02:55:14 PM PDT 24
Peak memory 200604 kb
Host smart-d82deb29-252d-4aeb-b2d1-c300fbde07e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344491098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.344491098
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3218283592
Short name T499
Test name
Test status
Simulation time 4345775667 ps
CPU time 19.79 seconds
Started May 23 02:55:11 PM PDT 24
Finished May 23 02:55:33 PM PDT 24
Peak memory 210704 kb
Host smart-be537200-2476-4edc-944e-bd8afd3e61d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218283592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3218283592
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.966320542
Short name T292
Test name
Test status
Simulation time 351581379 ps
CPU time 2.14 seconds
Started May 23 02:55:08 PM PDT 24
Finished May 23 02:55:12 PM PDT 24
Peak memory 200484 kb
Host smart-7fce6a31-bc3e-4f74-9d4c-29fc33a9f041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966320542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.966320542
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.1426291160
Short name T422
Test name
Test status
Simulation time 112774116 ps
CPU time 1.03 seconds
Started May 23 02:55:12 PM PDT 24
Finished May 23 02:55:15 PM PDT 24
Peak memory 200500 kb
Host smart-fa721d64-cdff-4247-bd11-dfe5bff5d29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426291160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1426291160
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.639216523
Short name T325
Test name
Test status
Simulation time 76121712 ps
CPU time 0.85 seconds
Started May 23 02:55:12 PM PDT 24
Finished May 23 02:55:15 PM PDT 24
Peak memory 200308 kb
Host smart-cae2174d-f8bc-4275-9d57-a22a40b86e77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639216523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.639216523
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.4004541834
Short name T346
Test name
Test status
Simulation time 1224122373 ps
CPU time 5.86 seconds
Started May 23 02:55:13 PM PDT 24
Finished May 23 02:55:21 PM PDT 24
Peak memory 218196 kb
Host smart-78fc4eca-92bc-43c5-ab50-e1241b93ecda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004541834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.4004541834
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2957734082
Short name T511
Test name
Test status
Simulation time 244147792 ps
CPU time 1.14 seconds
Started May 23 02:55:13 PM PDT 24
Finished May 23 02:55:16 PM PDT 24
Peak memory 217600 kb
Host smart-f9264b2c-1047-4821-a02d-70e658d61588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957734082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2957734082
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_reset.1947133714
Short name T424
Test name
Test status
Simulation time 1405915060 ps
CPU time 6.17 seconds
Started May 23 02:55:11 PM PDT 24
Finished May 23 02:55:20 PM PDT 24
Peak memory 200692 kb
Host smart-aed9d916-ff17-4e24-bc48-7503d2dfb107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947133714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1947133714
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1064752111
Short name T259
Test name
Test status
Simulation time 104534481 ps
CPU time 1.01 seconds
Started May 23 02:55:11 PM PDT 24
Finished May 23 02:55:14 PM PDT 24
Peak memory 200500 kb
Host smart-814a82b5-6791-4ad7-b695-ea9de3353152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064752111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1064752111
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.944072114
Short name T349
Test name
Test status
Simulation time 246530606 ps
CPU time 1.54 seconds
Started May 23 02:55:10 PM PDT 24
Finished May 23 02:55:14 PM PDT 24
Peak memory 200656 kb
Host smart-1b1edc15-49da-4992-b524-22d0f3bb500a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944072114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.944072114
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2531929326
Short name T297
Test name
Test status
Simulation time 6630618355 ps
CPU time 28.54 seconds
Started May 23 02:55:11 PM PDT 24
Finished May 23 02:55:42 PM PDT 24
Peak memory 200844 kb
Host smart-f9dde770-5c9e-47d2-9fdf-0d135d17202e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531929326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2531929326
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.587227915
Short name T334
Test name
Test status
Simulation time 309653982 ps
CPU time 2.36 seconds
Started May 23 02:55:11 PM PDT 24
Finished May 23 02:55:16 PM PDT 24
Peak memory 208764 kb
Host smart-6a33ba54-6911-43d2-99e5-c1188a27868c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587227915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.587227915
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3511544327
Short name T307
Test name
Test status
Simulation time 194399433 ps
CPU time 1.37 seconds
Started May 23 02:55:10 PM PDT 24
Finished May 23 02:55:13 PM PDT 24
Peak memory 200556 kb
Host smart-b0c0b3b8-4e1c-4f79-8ad5-b364d86ecf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511544327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3511544327
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.21114486
Short name T168
Test name
Test status
Simulation time 57657812 ps
CPU time 0.77 seconds
Started May 23 02:55:33 PM PDT 24
Finished May 23 02:55:35 PM PDT 24
Peak memory 200304 kb
Host smart-16e289c3-5a82-420a-bf90-f7c9c90d3815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21114486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.21114486
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2531990182
Short name T295
Test name
Test status
Simulation time 1230954792 ps
CPU time 5.97 seconds
Started May 23 02:55:35 PM PDT 24
Finished May 23 02:55:43 PM PDT 24
Peak memory 218156 kb
Host smart-709117cd-457f-40c7-8235-c1e49aa43b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531990182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2531990182
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3421743414
Short name T347
Test name
Test status
Simulation time 244576982 ps
CPU time 1.08 seconds
Started May 23 02:55:33 PM PDT 24
Finished May 23 02:55:35 PM PDT 24
Peak memory 217764 kb
Host smart-f16ca311-a183-4088-a5f7-5c391e87c018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421743414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3421743414
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3783349489
Short name T320
Test name
Test status
Simulation time 166410209 ps
CPU time 0.87 seconds
Started May 23 02:55:12 PM PDT 24
Finished May 23 02:55:15 PM PDT 24
Peak memory 200296 kb
Host smart-39f3d506-a3e2-45a3-9304-55d36539ddc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783349489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3783349489
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2709539360
Short name T306
Test name
Test status
Simulation time 1086835167 ps
CPU time 5.69 seconds
Started May 23 02:55:13 PM PDT 24
Finished May 23 02:55:20 PM PDT 24
Peak memory 200688 kb
Host smart-f20a9e6b-7203-440c-ba06-a02fd583ddb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709539360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2709539360
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.656764562
Short name T252
Test name
Test status
Simulation time 152403494 ps
CPU time 1.12 seconds
Started May 23 02:55:38 PM PDT 24
Finished May 23 02:55:42 PM PDT 24
Peak memory 200508 kb
Host smart-06dd18f4-77a7-4624-a786-e512730ca925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656764562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.656764562
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2628163593
Short name T317
Test name
Test status
Simulation time 256448590 ps
CPU time 1.65 seconds
Started May 23 02:55:08 PM PDT 24
Finished May 23 02:55:12 PM PDT 24
Peak memory 200704 kb
Host smart-2348dccf-513e-47a0-900f-14084dcd1cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628163593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2628163593
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2146484549
Short name T90
Test name
Test status
Simulation time 5957535316 ps
CPU time 27.61 seconds
Started May 23 02:55:35 PM PDT 24
Finished May 23 02:56:05 PM PDT 24
Peak memory 200832 kb
Host smart-d56a39bf-6415-466a-ab26-1c96d39c6bcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146484549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2146484549
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2985959441
Short name T276
Test name
Test status
Simulation time 468329583 ps
CPU time 2.82 seconds
Started May 23 02:55:33 PM PDT 24
Finished May 23 02:55:37 PM PDT 24
Peak memory 200492 kb
Host smart-3a70f1e0-8ec4-4651-af67-bbf10bc23af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985959441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2985959441
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1674288574
Short name T242
Test name
Test status
Simulation time 91286499 ps
CPU time 0.91 seconds
Started May 23 02:55:12 PM PDT 24
Finished May 23 02:55:15 PM PDT 24
Peak memory 200468 kb
Host smart-5bc2ef94-ae82-483d-9e22-361c7611aa10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674288574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1674288574
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.894883191
Short name T461
Test name
Test status
Simulation time 67941071 ps
CPU time 0.79 seconds
Started May 23 02:55:34 PM PDT 24
Finished May 23 02:55:36 PM PDT 24
Peak memory 200260 kb
Host smart-f10fb4f0-ebf4-4718-a6b3-071fecf2e928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894883191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.894883191
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2201566475
Short name T138
Test name
Test status
Simulation time 243454988 ps
CPU time 1.08 seconds
Started May 23 02:55:34 PM PDT 24
Finished May 23 02:55:37 PM PDT 24
Peak memory 217568 kb
Host smart-923fb585-aa4b-4ab4-bd00-1a7be44dc85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201566475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2201566475
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.1408532545
Short name T318
Test name
Test status
Simulation time 94578917 ps
CPU time 0.81 seconds
Started May 23 02:55:34 PM PDT 24
Finished May 23 02:55:37 PM PDT 24
Peak memory 200316 kb
Host smart-ecf1fb2f-67ef-4fc0-bd76-48863a22b3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408532545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1408532545
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2333534607
Short name T490
Test name
Test status
Simulation time 1447460982 ps
CPU time 6.14 seconds
Started May 23 02:55:37 PM PDT 24
Finished May 23 02:55:45 PM PDT 24
Peak memory 200724 kb
Host smart-55738119-d5d5-44d5-aa0b-a803ef98833b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333534607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2333534607
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2833245362
Short name T200
Test name
Test status
Simulation time 162824308 ps
CPU time 1.27 seconds
Started May 23 02:55:35 PM PDT 24
Finished May 23 02:55:38 PM PDT 24
Peak memory 200488 kb
Host smart-a23e3f9b-c0f3-4ad9-9b7f-b719afb1959f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833245362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2833245362
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.573649167
Short name T118
Test name
Test status
Simulation time 228868667 ps
CPU time 1.64 seconds
Started May 23 02:55:33 PM PDT 24
Finished May 23 02:55:35 PM PDT 24
Peak memory 200696 kb
Host smart-69468509-94b0-427b-83e8-1c75d672503d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573649167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.573649167
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3368847169
Short name T485
Test name
Test status
Simulation time 1487702186 ps
CPU time 5.67 seconds
Started May 23 02:55:33 PM PDT 24
Finished May 23 02:55:40 PM PDT 24
Peak memory 200688 kb
Host smart-57b4cfdb-5955-4d37-bda1-772f2c8853da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368847169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3368847169
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.1308185373
Short name T213
Test name
Test status
Simulation time 117529290 ps
CPU time 1.5 seconds
Started May 23 02:55:34 PM PDT 24
Finished May 23 02:55:36 PM PDT 24
Peak memory 200472 kb
Host smart-0fb7a06c-f40e-40e1-b221-c7b89f5c5e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308185373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1308185373
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1552507454
Short name T475
Test name
Test status
Simulation time 219908974 ps
CPU time 1.3 seconds
Started May 23 02:55:34 PM PDT 24
Finished May 23 02:55:37 PM PDT 24
Peak memory 200492 kb
Host smart-a404da90-1501-4214-9d81-09a7fa510f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552507454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1552507454
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2528479973
Short name T479
Test name
Test status
Simulation time 59481445 ps
CPU time 0.8 seconds
Started May 23 02:55:33 PM PDT 24
Finished May 23 02:55:35 PM PDT 24
Peak memory 200348 kb
Host smart-bcf917be-e76a-4284-88db-dbbe633d0349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528479973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2528479973
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2926409977
Short name T42
Test name
Test status
Simulation time 1222080806 ps
CPU time 5.44 seconds
Started May 23 02:55:34 PM PDT 24
Finished May 23 02:55:40 PM PDT 24
Peak memory 222104 kb
Host smart-0fb4559e-1e2b-4cdb-8274-2bcee7e4f8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926409977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2926409977
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.77433527
Short name T492
Test name
Test status
Simulation time 245331758 ps
CPU time 1.07 seconds
Started May 23 02:55:32 PM PDT 24
Finished May 23 02:55:35 PM PDT 24
Peak memory 217748 kb
Host smart-05f5f1f2-f3bd-4c92-a792-447e1105c69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77433527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.77433527
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3130646314
Short name T270
Test name
Test status
Simulation time 157277149 ps
CPU time 0.92 seconds
Started May 23 02:55:33 PM PDT 24
Finished May 23 02:55:35 PM PDT 24
Peak memory 200316 kb
Host smart-76ca6601-709c-4828-b596-6c2ebdcca7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130646314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3130646314
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2245520045
Short name T527
Test name
Test status
Simulation time 957413557 ps
CPU time 4.87 seconds
Started May 23 02:55:36 PM PDT 24
Finished May 23 02:55:44 PM PDT 24
Peak memory 200628 kb
Host smart-fd0e273a-bb28-4395-a3ea-c2149f9c7619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245520045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2245520045
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1171577839
Short name T523
Test name
Test status
Simulation time 149487194 ps
CPU time 1.15 seconds
Started May 23 02:55:39 PM PDT 24
Finished May 23 02:55:44 PM PDT 24
Peak memory 200496 kb
Host smart-e23e31f8-32e0-402e-8df2-43c1c7c495ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171577839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1171577839
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3799770422
Short name T210
Test name
Test status
Simulation time 231069313 ps
CPU time 1.52 seconds
Started May 23 02:55:39 PM PDT 24
Finished May 23 02:55:43 PM PDT 24
Peak memory 200720 kb
Host smart-fdf2d508-5306-4ddf-b74f-fcb335811c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799770422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3799770422
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.3342901939
Short name T387
Test name
Test status
Simulation time 5984195659 ps
CPU time 21.45 seconds
Started May 23 02:55:38 PM PDT 24
Finished May 23 02:56:02 PM PDT 24
Peak memory 209016 kb
Host smart-c6a568ef-afb8-4e27-a1ae-15f5921b93e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342901939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3342901939
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.1673904562
Short name T391
Test name
Test status
Simulation time 342399304 ps
CPU time 2.2 seconds
Started May 23 02:55:32 PM PDT 24
Finished May 23 02:55:36 PM PDT 24
Peak memory 200504 kb
Host smart-c84e0a44-9762-4093-874d-1782f23f8f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673904562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1673904562
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1458830193
Short name T223
Test name
Test status
Simulation time 162704917 ps
CPU time 1.41 seconds
Started May 23 02:55:36 PM PDT 24
Finished May 23 02:55:40 PM PDT 24
Peak memory 200660 kb
Host smart-74142a26-382b-4fb8-9a31-8e002bbe53dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458830193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1458830193
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.969017518
Short name T392
Test name
Test status
Simulation time 74606570 ps
CPU time 0.87 seconds
Started May 23 02:55:37 PM PDT 24
Finished May 23 02:55:41 PM PDT 24
Peak memory 200372 kb
Host smart-06bb1c8d-8403-45a0-9f98-50918a969c58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969017518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.969017518
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1339054101
Short name T30
Test name
Test status
Simulation time 1886873766 ps
CPU time 7.74 seconds
Started May 23 02:55:34 PM PDT 24
Finished May 23 02:55:44 PM PDT 24
Peak memory 217032 kb
Host smart-931ba6db-a74b-462b-9297-c99ef842c87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339054101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1339054101
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1284678001
Short name T467
Test name
Test status
Simulation time 243948851 ps
CPU time 1.16 seconds
Started May 23 02:55:35 PM PDT 24
Finished May 23 02:55:39 PM PDT 24
Peak memory 217596 kb
Host smart-c5b4d973-9a9c-4161-8e98-66918decd59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284678001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1284678001
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3074559071
Short name T153
Test name
Test status
Simulation time 98153855 ps
CPU time 0.84 seconds
Started May 23 02:55:33 PM PDT 24
Finished May 23 02:55:36 PM PDT 24
Peak memory 200328 kb
Host smart-56a56dc4-68ce-4f95-9d45-58927adfde41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074559071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3074559071
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2489256193
Short name T156
Test name
Test status
Simulation time 1561330168 ps
CPU time 6.47 seconds
Started May 23 02:55:35 PM PDT 24
Finished May 23 02:55:43 PM PDT 24
Peak memory 200676 kb
Host smart-b706e320-8eb5-4fd2-8033-1da1d320a1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489256193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2489256193
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1963954532
Short name T432
Test name
Test status
Simulation time 152818321 ps
CPU time 1.18 seconds
Started May 23 02:55:35 PM PDT 24
Finished May 23 02:55:38 PM PDT 24
Peak memory 200484 kb
Host smart-41bb1833-de62-45df-8972-44ebdbd41716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963954532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1963954532
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2159189237
Short name T355
Test name
Test status
Simulation time 114289891 ps
CPU time 1.22 seconds
Started May 23 02:55:35 PM PDT 24
Finished May 23 02:55:39 PM PDT 24
Peak memory 200664 kb
Host smart-a330b128-d57e-4c1a-97b3-5350da47d613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159189237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2159189237
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.3385187193
Short name T456
Test name
Test status
Simulation time 360443784 ps
CPU time 2.28 seconds
Started May 23 02:55:39 PM PDT 24
Finished May 23 02:55:44 PM PDT 24
Peak memory 200492 kb
Host smart-d46ae9f0-d0d3-4c57-b153-251880ca4bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385187193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3385187193
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.396106248
Short name T275
Test name
Test status
Simulation time 154163183 ps
CPU time 1.26 seconds
Started May 23 02:55:38 PM PDT 24
Finished May 23 02:55:42 PM PDT 24
Peak memory 200480 kb
Host smart-8b7d4d57-6c5b-4034-936d-07551585c067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396106248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.396106248
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3118687807
Short name T428
Test name
Test status
Simulation time 75527175 ps
CPU time 0.85 seconds
Started May 23 02:55:41 PM PDT 24
Finished May 23 02:55:44 PM PDT 24
Peak memory 200308 kb
Host smart-f8e0b865-15fe-4a74-901d-5a82eb65071a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118687807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3118687807
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.254131768
Short name T26
Test name
Test status
Simulation time 1228383173 ps
CPU time 6.24 seconds
Started May 23 02:55:38 PM PDT 24
Finished May 23 02:55:47 PM PDT 24
Peak memory 221916 kb
Host smart-1f49c2c8-0c6b-4f48-b2fa-db6283157819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254131768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.254131768
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.421690515
Short name T244
Test name
Test status
Simulation time 244111320 ps
CPU time 1.17 seconds
Started May 23 02:55:37 PM PDT 24
Finished May 23 02:55:41 PM PDT 24
Peak memory 217588 kb
Host smart-59e07f46-af7c-4aca-9c1f-1c449bd15855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421690515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.421690515
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2081526322
Short name T524
Test name
Test status
Simulation time 142652235 ps
CPU time 0.85 seconds
Started May 23 02:55:38 PM PDT 24
Finished May 23 02:55:41 PM PDT 24
Peak memory 200288 kb
Host smart-42c1db87-f1f2-4cad-bc99-21694e1a424d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081526322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2081526322
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.2667585529
Short name T87
Test name
Test status
Simulation time 1646992417 ps
CPU time 6.8 seconds
Started May 23 02:55:37 PM PDT 24
Finished May 23 02:55:47 PM PDT 24
Peak memory 200796 kb
Host smart-16008263-ff44-4b6a-811b-4756f99835e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667585529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2667585529
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.4111995334
Short name T374
Test name
Test status
Simulation time 179569090 ps
CPU time 1.27 seconds
Started May 23 02:55:36 PM PDT 24
Finished May 23 02:55:40 PM PDT 24
Peak memory 200500 kb
Host smart-0014d7a7-efad-4d56-9b8c-ac2333dd7ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111995334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.4111995334
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.2810269161
Short name T191
Test name
Test status
Simulation time 251990947 ps
CPU time 1.49 seconds
Started May 23 02:55:38 PM PDT 24
Finished May 23 02:55:42 PM PDT 24
Peak memory 200592 kb
Host smart-fe00c2d0-fbc9-4bf6-a54f-2c716e15f053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810269161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2810269161
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3392946443
Short name T354
Test name
Test status
Simulation time 2829712383 ps
CPU time 10.18 seconds
Started May 23 02:55:40 PM PDT 24
Finished May 23 02:55:53 PM PDT 24
Peak memory 200808 kb
Host smart-2619e035-2e55-4fb5-ae0d-d55b1f8658f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392946443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3392946443
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2784613404
Short name T187
Test name
Test status
Simulation time 315194245 ps
CPU time 2.19 seconds
Started May 23 02:55:38 PM PDT 24
Finished May 23 02:55:43 PM PDT 24
Peak memory 200396 kb
Host smart-6aab2612-be62-4222-a7f9-d93205ed3ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784613404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2784613404
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1307596077
Short name T341
Test name
Test status
Simulation time 102612596 ps
CPU time 0.86 seconds
Started May 23 02:55:36 PM PDT 24
Finished May 23 02:55:40 PM PDT 24
Peak memory 200500 kb
Host smart-efbabca8-2951-44a3-b7c2-7e072897a477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307596077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1307596077
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2318410143
Short name T209
Test name
Test status
Simulation time 70695357 ps
CPU time 0.81 seconds
Started May 23 02:55:37 PM PDT 24
Finished May 23 02:55:41 PM PDT 24
Peak memory 200316 kb
Host smart-934f0c92-4a40-4db7-9630-bf19b17e4a9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318410143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2318410143
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.755059061
Short name T52
Test name
Test status
Simulation time 1894752891 ps
CPU time 7.3 seconds
Started May 23 02:55:37 PM PDT 24
Finished May 23 02:55:47 PM PDT 24
Peak memory 218096 kb
Host smart-11b9bbc6-e7f7-4be0-a863-50ab90c48417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755059061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.755059061
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.4000690243
Short name T537
Test name
Test status
Simulation time 244203518 ps
CPU time 1.15 seconds
Started May 23 02:55:37 PM PDT 24
Finished May 23 02:55:40 PM PDT 24
Peak memory 217584 kb
Host smart-a8f04922-f4c9-4d88-813e-9ff13b9b3199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000690243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.4000690243
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3706224086
Short name T372
Test name
Test status
Simulation time 175498026 ps
CPU time 0.97 seconds
Started May 23 02:55:40 PM PDT 24
Finished May 23 02:55:44 PM PDT 24
Peak memory 200296 kb
Host smart-02491569-c9d0-4537-8410-e5402ae2c9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706224086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3706224086
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2405983466
Short name T326
Test name
Test status
Simulation time 1752213422 ps
CPU time 6.95 seconds
Started May 23 02:55:37 PM PDT 24
Finished May 23 02:55:46 PM PDT 24
Peak memory 200688 kb
Host smart-bb7a8902-2f05-4c41-b5e1-91472a766652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405983466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2405983466
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1131356481
Short name T126
Test name
Test status
Simulation time 103022570 ps
CPU time 0.97 seconds
Started May 23 02:55:37 PM PDT 24
Finished May 23 02:55:41 PM PDT 24
Peak memory 200520 kb
Host smart-d9f03e59-b074-4070-85d9-499ea2512453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131356481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1131356481
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.621331134
Short name T480
Test name
Test status
Simulation time 244907441 ps
CPU time 1.47 seconds
Started May 23 02:55:37 PM PDT 24
Finished May 23 02:55:41 PM PDT 24
Peak memory 200676 kb
Host smart-85ffe515-07a8-4798-93b4-5e2c76cf4e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621331134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.621331134
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.4078219154
Short name T482
Test name
Test status
Simulation time 17648504670 ps
CPU time 64.78 seconds
Started May 23 02:55:37 PM PDT 24
Finished May 23 02:56:44 PM PDT 24
Peak memory 209020 kb
Host smart-9c1151e3-a0a4-4f3e-9f4d-59d8eaa2cbc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078219154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.4078219154
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3364587098
Short name T272
Test name
Test status
Simulation time 498076181 ps
CPU time 2.6 seconds
Started May 23 02:55:37 PM PDT 24
Finished May 23 02:55:42 PM PDT 24
Peak memory 200480 kb
Host smart-bc0987a7-7cdf-4c65-aa34-e6f1406c419e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364587098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3364587098
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1977740239
Short name T436
Test name
Test status
Simulation time 129499364 ps
CPU time 1.05 seconds
Started May 23 02:55:37 PM PDT 24
Finished May 23 02:55:40 PM PDT 24
Peak memory 200488 kb
Host smart-28e9201f-8bd9-430f-8f0b-b842dadcac62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977740239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1977740239
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1986724746
Short name T148
Test name
Test status
Simulation time 75159335 ps
CPU time 0.82 seconds
Started May 23 02:54:47 PM PDT 24
Finished May 23 02:54:52 PM PDT 24
Peak memory 200316 kb
Host smart-f3f8c75d-83f0-4775-8dbe-938bfe9757bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986724746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1986724746
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2713777729
Short name T353
Test name
Test status
Simulation time 245623392 ps
CPU time 1.12 seconds
Started May 23 02:54:43 PM PDT 24
Finished May 23 02:54:45 PM PDT 24
Peak memory 217708 kb
Host smart-3b181e9d-905c-4d8a-9f63-3d2a4b5a6749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713777729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2713777729
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2347909648
Short name T442
Test name
Test status
Simulation time 182616632 ps
CPU time 0.9 seconds
Started May 23 02:54:30 PM PDT 24
Finished May 23 02:54:32 PM PDT 24
Peak memory 200264 kb
Host smart-11aa4b1b-7e93-4108-a6d4-69c5a7c6466d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347909648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2347909648
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.880102907
Short name T95
Test name
Test status
Simulation time 1890042688 ps
CPU time 7.7 seconds
Started May 23 02:54:42 PM PDT 24
Finished May 23 02:54:51 PM PDT 24
Peak memory 200740 kb
Host smart-c0c416ae-8f83-474c-bd6f-4b43cf1a8747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880102907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.880102907
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.3250817673
Short name T74
Test name
Test status
Simulation time 8407015248 ps
CPU time 14.8 seconds
Started May 23 02:54:48 PM PDT 24
Finished May 23 02:55:06 PM PDT 24
Peak memory 218048 kb
Host smart-65cdc481-030c-4f3f-abdd-d7987bad93e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250817673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3250817673
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.4070177833
Short name T321
Test name
Test status
Simulation time 177703209 ps
CPU time 1.29 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:54:50 PM PDT 24
Peak memory 200464 kb
Host smart-770308b7-283a-4412-836f-053a37ea3d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070177833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.4070177833
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1204172979
Short name T59
Test name
Test status
Simulation time 113203371 ps
CPU time 1.15 seconds
Started May 23 02:54:29 PM PDT 24
Finished May 23 02:54:31 PM PDT 24
Peak memory 200668 kb
Host smart-74fc4b45-c479-4429-bc63-bcd0d8208471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204172979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1204172979
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.248044827
Short name T294
Test name
Test status
Simulation time 121980418 ps
CPU time 0.89 seconds
Started May 23 02:54:43 PM PDT 24
Finished May 23 02:54:46 PM PDT 24
Peak memory 200300 kb
Host smart-ac36c7a4-3abb-4bcc-bdaa-1ab38604dcbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248044827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.248044827
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2494939372
Short name T224
Test name
Test status
Simulation time 356120758 ps
CPU time 1.97 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:54:50 PM PDT 24
Peak memory 200492 kb
Host smart-9add5d71-de78-42d7-a073-1813531e326d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494939372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2494939372
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.516609450
Short name T404
Test name
Test status
Simulation time 160439352 ps
CPU time 1.25 seconds
Started May 23 02:54:43 PM PDT 24
Finished May 23 02:54:46 PM PDT 24
Peak memory 200664 kb
Host smart-6741aba7-0d17-40db-bc06-8c5de3697001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516609450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.516609450
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.715726459
Short name T427
Test name
Test status
Simulation time 60702158 ps
CPU time 0.75 seconds
Started May 23 02:55:38 PM PDT 24
Finished May 23 02:55:42 PM PDT 24
Peak memory 200236 kb
Host smart-86427d29-da06-456f-ad50-1e2a4a0c74c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715726459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.715726459
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3190853248
Short name T280
Test name
Test status
Simulation time 2348886220 ps
CPU time 9.29 seconds
Started May 23 02:55:39 PM PDT 24
Finished May 23 02:55:52 PM PDT 24
Peak memory 218188 kb
Host smart-6afb3a18-5368-4549-ae7b-71afbe506754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190853248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3190853248
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.37393869
Short name T301
Test name
Test status
Simulation time 244875989 ps
CPU time 1.03 seconds
Started May 23 02:55:41 PM PDT 24
Finished May 23 02:55:45 PM PDT 24
Peak memory 217740 kb
Host smart-3e08d21d-b3a9-404c-bd47-73dafa52d58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37393869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.37393869
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2892109460
Short name T145
Test name
Test status
Simulation time 137831202 ps
CPU time 0.9 seconds
Started May 23 02:55:41 PM PDT 24
Finished May 23 02:55:45 PM PDT 24
Peak memory 200312 kb
Host smart-effb1593-249d-495e-b0e0-5b97b446d757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892109460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2892109460
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3568991713
Short name T421
Test name
Test status
Simulation time 1805123797 ps
CPU time 8.15 seconds
Started May 23 02:55:37 PM PDT 24
Finished May 23 02:55:48 PM PDT 24
Peak memory 200708 kb
Host smart-a04fbaf6-f6e3-4d1c-bdd2-5a594c61a93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568991713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3568991713
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1577242544
Short name T50
Test name
Test status
Simulation time 108749958 ps
CPU time 1.04 seconds
Started May 23 02:55:39 PM PDT 24
Finished May 23 02:55:43 PM PDT 24
Peak memory 200400 kb
Host smart-34f39bdc-0893-4900-8d4d-bbcaf036e960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577242544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1577242544
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.711317048
Short name T398
Test name
Test status
Simulation time 226155738 ps
CPU time 1.45 seconds
Started May 23 02:55:38 PM PDT 24
Finished May 23 02:55:42 PM PDT 24
Peak memory 200724 kb
Host smart-5bf60517-1347-448c-a0d9-6612e2efcb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711317048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.711317048
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3935690973
Short name T262
Test name
Test status
Simulation time 5966287923 ps
CPU time 23.16 seconds
Started May 23 02:55:42 PM PDT 24
Finished May 23 02:56:07 PM PDT 24
Peak memory 200820 kb
Host smart-d7d33685-b0f8-41c5-b2ab-24e9bfdd1da1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935690973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3935690973
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.639315154
Short name T328
Test name
Test status
Simulation time 64858993 ps
CPU time 0.82 seconds
Started May 23 02:55:38 PM PDT 24
Finished May 23 02:55:42 PM PDT 24
Peak memory 200476 kb
Host smart-c24f47a9-63a8-45f4-8dc9-d9dc9d601d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639315154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.639315154
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1021665002
Short name T434
Test name
Test status
Simulation time 71735059 ps
CPU time 0.84 seconds
Started May 23 02:55:35 PM PDT 24
Finished May 23 02:55:38 PM PDT 24
Peak memory 200284 kb
Host smart-5067b07e-28fb-4461-a136-5145a8017369
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021665002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1021665002
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3887111289
Short name T412
Test name
Test status
Simulation time 1897513635 ps
CPU time 7.28 seconds
Started May 23 02:55:38 PM PDT 24
Finished May 23 02:55:48 PM PDT 24
Peak memory 218048 kb
Host smart-4ad79613-b294-4881-9a9b-f83b92edbb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887111289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3887111289
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3920267616
Short name T365
Test name
Test status
Simulation time 244985253 ps
CPU time 1.2 seconds
Started May 23 02:55:41 PM PDT 24
Finished May 23 02:55:45 PM PDT 24
Peak memory 217692 kb
Host smart-e44963ce-8842-4ac0-8920-91f99c562468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920267616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3920267616
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1645761850
Short name T366
Test name
Test status
Simulation time 199900795 ps
CPU time 0.91 seconds
Started May 23 02:55:42 PM PDT 24
Finished May 23 02:55:45 PM PDT 24
Peak memory 200312 kb
Host smart-042dc887-3b2e-406f-9b8d-c569f3457569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645761850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1645761850
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.776442233
Short name T115
Test name
Test status
Simulation time 1890007142 ps
CPU time 7.59 seconds
Started May 23 02:55:39 PM PDT 24
Finished May 23 02:55:49 PM PDT 24
Peak memory 200652 kb
Host smart-4a7f8b3c-5402-495c-a360-7ce6d4068358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776442233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.776442233
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2309317678
Short name T258
Test name
Test status
Simulation time 98033739 ps
CPU time 1.08 seconds
Started May 23 02:55:41 PM PDT 24
Finished May 23 02:55:44 PM PDT 24
Peak memory 200300 kb
Host smart-7afb8434-f8ae-498b-8407-3a2abeb05c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309317678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2309317678
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3262905267
Short name T473
Test name
Test status
Simulation time 209622733 ps
CPU time 1.4 seconds
Started May 23 02:55:38 PM PDT 24
Finished May 23 02:55:43 PM PDT 24
Peak memory 200636 kb
Host smart-ead7fec5-bc31-4300-bf04-3052f3814680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262905267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3262905267
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.4272901557
Short name T273
Test name
Test status
Simulation time 3778279129 ps
CPU time 17.01 seconds
Started May 23 02:55:35 PM PDT 24
Finished May 23 02:55:55 PM PDT 24
Peak memory 200864 kb
Host smart-20f21bec-f3c7-4e04-bf74-9aebdebf2425
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272901557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.4272901557
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3310160151
Short name T287
Test name
Test status
Simulation time 394245631 ps
CPU time 2.72 seconds
Started May 23 02:55:39 PM PDT 24
Finished May 23 02:55:45 PM PDT 24
Peak memory 200456 kb
Host smart-c5aa78a1-7c0d-4641-8ac4-43fef042ddf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310160151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3310160151
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.790547512
Short name T516
Test name
Test status
Simulation time 166953993 ps
CPU time 1.19 seconds
Started May 23 02:55:41 PM PDT 24
Finished May 23 02:55:44 PM PDT 24
Peak memory 200268 kb
Host smart-d9f6bfd6-d308-4abb-89a8-94c1d9ef96e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790547512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.790547512
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2172098893
Short name T450
Test name
Test status
Simulation time 76025336 ps
CPU time 0.78 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:02 PM PDT 24
Peak memory 200312 kb
Host smart-690f3f3b-83c3-4251-8f1c-08bfec6cd1f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172098893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2172098893
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.168958591
Short name T172
Test name
Test status
Simulation time 1883835221 ps
CPU time 7.09 seconds
Started May 23 02:55:37 PM PDT 24
Finished May 23 02:55:47 PM PDT 24
Peak memory 218136 kb
Host smart-bf3adfc2-b04c-40e5-aec7-3f4ac7c72a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168958591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.168958591
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.227390935
Short name T206
Test name
Test status
Simulation time 243362244 ps
CPU time 1.23 seconds
Started May 23 02:55:35 PM PDT 24
Finished May 23 02:55:38 PM PDT 24
Peak memory 217568 kb
Host smart-0c2ece98-2964-4b48-a49a-a09222054e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227390935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.227390935
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.524951612
Short name T18
Test name
Test status
Simulation time 149455001 ps
CPU time 0.84 seconds
Started May 23 02:55:35 PM PDT 24
Finished May 23 02:55:38 PM PDT 24
Peak memory 200256 kb
Host smart-1317146d-43a7-4be7-92a4-fe5c5f44c327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524951612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.524951612
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2119179221
Short name T286
Test name
Test status
Simulation time 1425790490 ps
CPU time 6.72 seconds
Started May 23 02:55:39 PM PDT 24
Finished May 23 02:55:49 PM PDT 24
Peak memory 200728 kb
Host smart-5fafb419-7213-47c0-8b53-2c7502b2ef6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119179221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2119179221
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3299171108
Short name T20
Test name
Test status
Simulation time 175530403 ps
CPU time 1.27 seconds
Started May 23 02:55:35 PM PDT 24
Finished May 23 02:55:39 PM PDT 24
Peak memory 200504 kb
Host smart-fc0a88e1-b237-4a7e-8a10-6a6bdffe7199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299171108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3299171108
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.486951765
Short name T134
Test name
Test status
Simulation time 116862294 ps
CPU time 1.21 seconds
Started May 23 02:55:36 PM PDT 24
Finished May 23 02:55:40 PM PDT 24
Peak memory 200624 kb
Host smart-b614cb21-0046-4f72-820b-54167869ebb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486951765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.486951765
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.31935046
Short name T202
Test name
Test status
Simulation time 10593912049 ps
CPU time 40.7 seconds
Started May 23 02:55:37 PM PDT 24
Finished May 23 02:56:20 PM PDT 24
Peak memory 208988 kb
Host smart-2db715de-6490-4a5d-ae63-52a40d58599c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31935046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.31935046
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3184455380
Short name T261
Test name
Test status
Simulation time 402290021 ps
CPU time 2.45 seconds
Started May 23 02:55:35 PM PDT 24
Finished May 23 02:55:39 PM PDT 24
Peak memory 200492 kb
Host smart-bfd750e6-c3b2-49e7-bf35-a97f79963a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184455380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3184455380
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.976369505
Short name T465
Test name
Test status
Simulation time 140903956 ps
CPU time 1.06 seconds
Started May 23 02:55:38 PM PDT 24
Finished May 23 02:55:43 PM PDT 24
Peak memory 200496 kb
Host smart-94861d0e-94bb-451e-b13d-87e7c5502be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976369505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.976369505
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.2706815542
Short name T414
Test name
Test status
Simulation time 57914029 ps
CPU time 0.73 seconds
Started May 23 02:55:59 PM PDT 24
Finished May 23 02:56:04 PM PDT 24
Peak memory 200300 kb
Host smart-3b947b23-6275-4e0d-8e7f-b93d11b5cf5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706815542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.2706815542
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3290207374
Short name T43
Test name
Test status
Simulation time 2353761390 ps
CPU time 10.24 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:12 PM PDT 24
Peak memory 218288 kb
Host smart-aa97bd9a-9998-4f1d-b43c-45ef2be35d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290207374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3290207374
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.2663989034
Short name T400
Test name
Test status
Simulation time 243773406 ps
CPU time 1.17 seconds
Started May 23 02:55:56 PM PDT 24
Finished May 23 02:56:00 PM PDT 24
Peak memory 217568 kb
Host smart-ce3dba4e-7d26-4bb2-9658-d66549c9f5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663989034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.2663989034
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2301135688
Short name T14
Test name
Test status
Simulation time 205914007 ps
CPU time 0.92 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:01 PM PDT 24
Peak memory 200304 kb
Host smart-19937cf6-6a5f-4af5-856c-5a4bf1ec6b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301135688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2301135688
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.420118729
Short name T173
Test name
Test status
Simulation time 1678501579 ps
CPU time 7.13 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:09 PM PDT 24
Peak memory 200640 kb
Host smart-4192ff55-cc77-4c29-8461-157e1dd59121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420118729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.420118729
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.835072030
Short name T201
Test name
Test status
Simulation time 139650257 ps
CPU time 1.15 seconds
Started May 23 02:55:58 PM PDT 24
Finished May 23 02:56:03 PM PDT 24
Peak memory 200448 kb
Host smart-98c9c4af-8f51-422f-ba57-6318d0d1391c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835072030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.835072030
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2086283541
Short name T351
Test name
Test status
Simulation time 195147455 ps
CPU time 1.48 seconds
Started May 23 02:55:53 PM PDT 24
Finished May 23 02:55:55 PM PDT 24
Peak memory 200660 kb
Host smart-9a4cfc93-4206-41b5-a4cd-c3cd8bef2b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086283541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2086283541
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3364393165
Short name T247
Test name
Test status
Simulation time 7199095713 ps
CPU time 33.44 seconds
Started May 23 02:55:55 PM PDT 24
Finished May 23 02:56:30 PM PDT 24
Peak memory 200832 kb
Host smart-57ced0f3-01a7-43f6-92eb-f78f2bccd6d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364393165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3364393165
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.672245286
Short name T188
Test name
Test status
Simulation time 139313801 ps
CPU time 1.81 seconds
Started May 23 02:55:58 PM PDT 24
Finished May 23 02:56:04 PM PDT 24
Peak memory 200448 kb
Host smart-5aa21cff-5a72-4b4b-aa24-0daacc464a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672245286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.672245286
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.312774615
Short name T127
Test name
Test status
Simulation time 170403040 ps
CPU time 1.31 seconds
Started May 23 02:55:56 PM PDT 24
Finished May 23 02:56:01 PM PDT 24
Peak memory 200500 kb
Host smart-49d9f931-197e-40f8-87d3-de242c1d7569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312774615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.312774615
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.187731656
Short name T220
Test name
Test status
Simulation time 76031933 ps
CPU time 0.85 seconds
Started May 23 02:55:56 PM PDT 24
Finished May 23 02:55:59 PM PDT 24
Peak memory 200316 kb
Host smart-73fc4d9d-4948-49b1-809f-e81a359e912a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187731656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.187731656
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.832184560
Short name T157
Test name
Test status
Simulation time 1888417324 ps
CPU time 8.38 seconds
Started May 23 02:55:54 PM PDT 24
Finished May 23 02:56:04 PM PDT 24
Peak memory 217136 kb
Host smart-245b2dd6-ac82-4944-b334-85c93d83222f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832184560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.832184560
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3670590662
Short name T504
Test name
Test status
Simulation time 244773526 ps
CPU time 1.15 seconds
Started May 23 02:55:55 PM PDT 24
Finished May 23 02:55:58 PM PDT 24
Peak memory 217496 kb
Host smart-37fb207e-cb36-4a50-b0d0-d0847a8fee61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670590662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3670590662
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.747404709
Short name T12
Test name
Test status
Simulation time 162445879 ps
CPU time 0.86 seconds
Started May 23 02:55:56 PM PDT 24
Finished May 23 02:56:00 PM PDT 24
Peak memory 200316 kb
Host smart-270a79e6-0801-44d6-916a-4874ad49de5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747404709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.747404709
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2244345281
Short name T107
Test name
Test status
Simulation time 1398457341 ps
CPU time 5.47 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:07 PM PDT 24
Peak memory 200668 kb
Host smart-8e039437-6a96-4153-bc45-2631555929c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244345281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2244345281
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1027776397
Short name T382
Test name
Test status
Simulation time 111823054 ps
CPU time 1.02 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:01 PM PDT 24
Peak memory 200512 kb
Host smart-795510ee-6762-4320-906b-4c107e933bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027776397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1027776397
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2038853449
Short name T381
Test name
Test status
Simulation time 192953523 ps
CPU time 1.36 seconds
Started May 23 02:55:54 PM PDT 24
Finished May 23 02:55:57 PM PDT 24
Peak memory 200664 kb
Host smart-0a7ef094-a849-40e8-8cb3-1dcb504447cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038853449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2038853449
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2103326747
Short name T89
Test name
Test status
Simulation time 4642727704 ps
CPU time 20.33 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:22 PM PDT 24
Peak memory 210452 kb
Host smart-2e652120-2229-4d24-ba64-37aaae19b2cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103326747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2103326747
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1845350259
Short name T464
Test name
Test status
Simulation time 148148731 ps
CPU time 1.84 seconds
Started May 23 02:55:54 PM PDT 24
Finished May 23 02:55:56 PM PDT 24
Peak memory 200532 kb
Host smart-2b7bd909-00ec-43f5-b8e4-c12472e44315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845350259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1845350259
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1346541943
Short name T323
Test name
Test status
Simulation time 204946913 ps
CPU time 1.33 seconds
Started May 23 02:55:59 PM PDT 24
Finished May 23 02:56:05 PM PDT 24
Peak memory 200500 kb
Host smart-4b110c19-0900-42d2-92c1-681067c27936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346541943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1346541943
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2374223474
Short name T502
Test name
Test status
Simulation time 69159458 ps
CPU time 0.76 seconds
Started May 23 02:55:54 PM PDT 24
Finished May 23 02:55:56 PM PDT 24
Peak memory 200324 kb
Host smart-2fbc6589-0737-4e19-ac36-78b6d3092987
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374223474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2374223474
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.312823893
Short name T32
Test name
Test status
Simulation time 2172884300 ps
CPU time 9.13 seconds
Started May 23 02:55:55 PM PDT 24
Finished May 23 02:56:07 PM PDT 24
Peak memory 218252 kb
Host smart-3301261e-11a0-4db5-9a35-37dbb968fdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312823893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.312823893
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1922035610
Short name T532
Test name
Test status
Simulation time 245912360 ps
CPU time 1.08 seconds
Started May 23 02:55:55 PM PDT 24
Finished May 23 02:55:58 PM PDT 24
Peak memory 217604 kb
Host smart-c32de8d3-618f-4423-a1f8-9a39b112bd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922035610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1922035610
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.413538271
Short name T364
Test name
Test status
Simulation time 95365891 ps
CPU time 0.74 seconds
Started May 23 02:55:58 PM PDT 24
Finished May 23 02:56:03 PM PDT 24
Peak memory 200276 kb
Host smart-13273ed6-4d04-4107-b395-1bec663d450b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413538271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.413538271
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.3585308831
Short name T393
Test name
Test status
Simulation time 1040038937 ps
CPU time 4.75 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:05 PM PDT 24
Peak memory 200680 kb
Host smart-c89416ce-519a-4fc4-8df9-644d1d3b2e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585308831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3585308831
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1770715187
Short name T515
Test name
Test status
Simulation time 152403347 ps
CPU time 1.25 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:03 PM PDT 24
Peak memory 200488 kb
Host smart-2a6d7861-2741-4a79-bd50-0704e2e40171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770715187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1770715187
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2110923397
Short name T526
Test name
Test status
Simulation time 204541271 ps
CPU time 1.47 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:01 PM PDT 24
Peak memory 200668 kb
Host smart-d3f255f3-ea9b-4dcb-863c-58640225f78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110923397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2110923397
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2382425288
Short name T281
Test name
Test status
Simulation time 11969827484 ps
CPU time 41.34 seconds
Started May 23 02:55:55 PM PDT 24
Finished May 23 02:56:39 PM PDT 24
Peak memory 200816 kb
Host smart-272452dd-455d-478c-949f-ed5e53f6b43b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382425288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2382425288
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1084673598
Short name T338
Test name
Test status
Simulation time 269581609 ps
CPU time 2.02 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:03 PM PDT 24
Peak memory 200544 kb
Host smart-8a8dfe57-cdcf-4733-9b0d-cd6e94c001be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084673598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1084673598
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1343108216
Short name T235
Test name
Test status
Simulation time 113563449 ps
CPU time 0.98 seconds
Started May 23 02:55:56 PM PDT 24
Finished May 23 02:55:59 PM PDT 24
Peak memory 200564 kb
Host smart-915dc91e-d738-4849-ad64-038aca0b591b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343108216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1343108216
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2863315139
Short name T443
Test name
Test status
Simulation time 66947750 ps
CPU time 0.74 seconds
Started May 23 02:55:59 PM PDT 24
Finished May 23 02:56:04 PM PDT 24
Peak memory 200304 kb
Host smart-d16fc461-1c49-4ccd-a6a2-c3decfa74eb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863315139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2863315139
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1787863148
Short name T204
Test name
Test status
Simulation time 2344083234 ps
CPU time 9.41 seconds
Started May 23 02:56:00 PM PDT 24
Finished May 23 02:56:13 PM PDT 24
Peak memory 222352 kb
Host smart-d5da850a-4ec5-40d4-aa28-418384fe120c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787863148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1787863148
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2003578091
Short name T468
Test name
Test status
Simulation time 244907395 ps
CPU time 1.08 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:01 PM PDT 24
Peak memory 217608 kb
Host smart-0ae62da6-d5ac-4959-9b1d-6b5aeeedb123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003578091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2003578091
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.4276564368
Short name T17
Test name
Test status
Simulation time 102898492 ps
CPU time 0.77 seconds
Started May 23 02:55:55 PM PDT 24
Finished May 23 02:55:57 PM PDT 24
Peak memory 200344 kb
Host smart-b3e6f837-286d-45c7-8267-e4ce8398212e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276564368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.4276564368
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3814312542
Short name T378
Test name
Test status
Simulation time 1586508453 ps
CPU time 6.46 seconds
Started May 23 02:55:58 PM PDT 24
Finished May 23 02:56:09 PM PDT 24
Peak memory 200684 kb
Host smart-3b88a56d-63e1-4bc4-87e8-817704aee452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814312542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3814312542
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2022358138
Short name T430
Test name
Test status
Simulation time 110655360 ps
CPU time 1.02 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:02 PM PDT 24
Peak memory 200464 kb
Host smart-b6b2ffd0-4dec-4026-b968-84a7776f6cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022358138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2022358138
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.2464725683
Short name T343
Test name
Test status
Simulation time 227947908 ps
CPU time 1.53 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:02 PM PDT 24
Peak memory 200680 kb
Host smart-400362a7-324e-47e2-be3c-43a298754ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464725683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.2464725683
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3682170730
Short name T437
Test name
Test status
Simulation time 3265893221 ps
CPU time 12.41 seconds
Started May 23 02:55:58 PM PDT 24
Finished May 23 02:56:14 PM PDT 24
Peak memory 200932 kb
Host smart-3f0cf46a-1557-42a3-8dc4-14d9381b85e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682170730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3682170730
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.564710876
Short name T240
Test name
Test status
Simulation time 292872416 ps
CPU time 1.96 seconds
Started May 23 02:55:54 PM PDT 24
Finished May 23 02:55:57 PM PDT 24
Peak memory 200496 kb
Host smart-edaea8b6-517b-4b47-8ab3-c737bcb6eb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564710876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.564710876
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2448636808
Short name T120
Test name
Test status
Simulation time 154361940 ps
CPU time 1.06 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:01 PM PDT 24
Peak memory 200508 kb
Host smart-8da3cc2a-4d4a-4db8-88b1-afcb3edea6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448636808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2448636808
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.3676723899
Short name T167
Test name
Test status
Simulation time 74948024 ps
CPU time 0.8 seconds
Started May 23 02:55:58 PM PDT 24
Finished May 23 02:56:03 PM PDT 24
Peak memory 200324 kb
Host smart-5af15fce-ad73-42e6-886d-a7519e6cfbe0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676723899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.3676723899
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1183315698
Short name T45
Test name
Test status
Simulation time 1224250538 ps
CPU time 5.71 seconds
Started May 23 02:55:56 PM PDT 24
Finished May 23 02:56:05 PM PDT 24
Peak memory 222200 kb
Host smart-f0ac0c57-e44f-49aa-be1e-17cda666c7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183315698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1183315698
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3022056023
Short name T405
Test name
Test status
Simulation time 244191955 ps
CPU time 1.18 seconds
Started May 23 02:56:00 PM PDT 24
Finished May 23 02:56:05 PM PDT 24
Peak memory 217760 kb
Host smart-bffe1a89-f51c-4ee2-ba9f-93f7a242baea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022056023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3022056023
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1130012140
Short name T319
Test name
Test status
Simulation time 136749853 ps
CPU time 0.85 seconds
Started May 23 02:55:58 PM PDT 24
Finished May 23 02:56:03 PM PDT 24
Peak memory 200300 kb
Host smart-e6405399-af3a-4b1a-85aa-298eceb4654c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130012140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1130012140
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1158926359
Short name T47
Test name
Test status
Simulation time 1251088117 ps
CPU time 5.14 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:07 PM PDT 24
Peak memory 200676 kb
Host smart-9d9cea40-6e4c-4d61-8f1c-165f69da0237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158926359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1158926359
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1231625799
Short name T491
Test name
Test status
Simulation time 141656352 ps
CPU time 1.07 seconds
Started May 23 02:55:55 PM PDT 24
Finished May 23 02:55:57 PM PDT 24
Peak memory 200480 kb
Host smart-58185484-74bc-43c9-8235-19e140d0a7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231625799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1231625799
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.975325475
Short name T60
Test name
Test status
Simulation time 129831505 ps
CPU time 1.26 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:02 PM PDT 24
Peak memory 200600 kb
Host smart-b958f0fe-b9e3-412d-adb9-454eb8766072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975325475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.975325475
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3017343969
Short name T91
Test name
Test status
Simulation time 5254697879 ps
CPU time 23.32 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:23 PM PDT 24
Peak memory 209004 kb
Host smart-69128714-5123-4419-9028-664f1d3c6d03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017343969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3017343969
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1139405515
Short name T330
Test name
Test status
Simulation time 284315629 ps
CPU time 1.92 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:03 PM PDT 24
Peak memory 208708 kb
Host smart-927fba5d-ed7b-4cdf-b6fc-b49fc6f6b999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139405515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1139405515
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3674097530
Short name T540
Test name
Test status
Simulation time 134730363 ps
CPU time 1.09 seconds
Started May 23 02:55:58 PM PDT 24
Finished May 23 02:56:03 PM PDT 24
Peak memory 200488 kb
Host smart-81a9c30e-8ece-464a-bbe7-fe7f57891fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674097530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3674097530
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.2868827665
Short name T230
Test name
Test status
Simulation time 53072204 ps
CPU time 0.7 seconds
Started May 23 02:55:59 PM PDT 24
Finished May 23 02:56:04 PM PDT 24
Peak memory 200304 kb
Host smart-005f41c2-615a-4f36-b90e-ff7d30284ba7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868827665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2868827665
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2866618731
Short name T190
Test name
Test status
Simulation time 1216083998 ps
CPU time 6.15 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:07 PM PDT 24
Peak memory 222232 kb
Host smart-a4169111-9960-4154-81ac-27b09677c060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866618731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2866618731
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.4106858889
Short name T211
Test name
Test status
Simulation time 244239267 ps
CPU time 1.06 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:02 PM PDT 24
Peak memory 217608 kb
Host smart-d1967d4c-f151-4ba1-aeb9-45a92c777b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106858889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.4106858889
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2634945758
Short name T513
Test name
Test status
Simulation time 200995778 ps
CPU time 0.88 seconds
Started May 23 02:55:54 PM PDT 24
Finished May 23 02:55:57 PM PDT 24
Peak memory 200316 kb
Host smart-ac29f2cb-459b-4ca4-af38-510523d484af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634945758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2634945758
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1762835770
Short name T189
Test name
Test status
Simulation time 903780944 ps
CPU time 4.53 seconds
Started May 23 02:55:58 PM PDT 24
Finished May 23 02:56:07 PM PDT 24
Peak memory 200648 kb
Host smart-cf09c542-5a88-465b-8112-5bad5b8c73bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762835770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1762835770
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.486996963
Short name T274
Test name
Test status
Simulation time 154828405 ps
CPU time 1.13 seconds
Started May 23 02:55:56 PM PDT 24
Finished May 23 02:56:00 PM PDT 24
Peak memory 200540 kb
Host smart-68a3423b-e898-4e6a-a0e6-2dea718d64bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486996963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.486996963
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.916530912
Short name T278
Test name
Test status
Simulation time 200235930 ps
CPU time 1.37 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:03 PM PDT 24
Peak memory 200776 kb
Host smart-5330d659-453d-43d9-9b88-2248bec742e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916530912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.916530912
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1132545103
Short name T441
Test name
Test status
Simulation time 151066149 ps
CPU time 1.12 seconds
Started May 23 02:55:55 PM PDT 24
Finished May 23 02:55:58 PM PDT 24
Peak memory 200512 kb
Host smart-32a081e7-1868-48ac-b8b8-a4a093a5b3bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132545103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1132545103
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3609531433
Short name T136
Test name
Test status
Simulation time 368707459 ps
CPU time 2.66 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:04 PM PDT 24
Peak memory 200528 kb
Host smart-947d83ea-5eba-4156-8e6c-ec26bf32551c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609531433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3609531433
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3477752037
Short name T139
Test name
Test status
Simulation time 71744052 ps
CPU time 0.74 seconds
Started May 23 02:55:59 PM PDT 24
Finished May 23 02:56:04 PM PDT 24
Peak memory 200500 kb
Host smart-5b6875a1-4270-4d45-9fe1-3878d75c5486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477752037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3477752037
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.366265680
Short name T363
Test name
Test status
Simulation time 58400478 ps
CPU time 0.73 seconds
Started May 23 02:56:18 PM PDT 24
Finished May 23 02:56:21 PM PDT 24
Peak memory 200348 kb
Host smart-f159c859-f876-471d-b3cf-f14ce5e51939
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366265680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.366265680
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3539832107
Short name T36
Test name
Test status
Simulation time 1229800193 ps
CPU time 5.97 seconds
Started May 23 02:55:59 PM PDT 24
Finished May 23 02:56:09 PM PDT 24
Peak memory 218120 kb
Host smart-11e60312-bb2e-4210-8b9b-513d440cf7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539832107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3539832107
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.1038695574
Short name T534
Test name
Test status
Simulation time 244788400 ps
CPU time 1.06 seconds
Started May 23 02:56:13 PM PDT 24
Finished May 23 02:56:16 PM PDT 24
Peak memory 217600 kb
Host smart-31109dc9-0084-4283-bcdf-7e8e09610627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038695574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.1038695574
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.116339704
Short name T4
Test name
Test status
Simulation time 166416584 ps
CPU time 0.86 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:01 PM PDT 24
Peak memory 200360 kb
Host smart-deb38a0b-6065-4a8f-99e9-def01ef3b1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116339704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.116339704
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3386996544
Short name T6
Test name
Test status
Simulation time 1456339293 ps
CPU time 5.84 seconds
Started May 23 02:55:59 PM PDT 24
Finished May 23 02:56:08 PM PDT 24
Peak memory 200656 kb
Host smart-dc6115c8-1ae2-4259-af12-da8456c99077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386996544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3386996544
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1588133106
Short name T238
Test name
Test status
Simulation time 189163257 ps
CPU time 1.3 seconds
Started May 23 02:55:58 PM PDT 24
Finished May 23 02:56:04 PM PDT 24
Peak memory 200472 kb
Host smart-70044dbd-58f0-43cd-8236-7fdea77ab332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588133106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1588133106
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3984548007
Short name T496
Test name
Test status
Simulation time 113153163 ps
CPU time 1.19 seconds
Started May 23 02:55:58 PM PDT 24
Finished May 23 02:56:03 PM PDT 24
Peak memory 200640 kb
Host smart-b34ead38-be37-47fb-af0e-7ad27324ee85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984548007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3984548007
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2848864389
Short name T150
Test name
Test status
Simulation time 1955042510 ps
CPU time 8.86 seconds
Started May 23 02:56:14 PM PDT 24
Finished May 23 02:56:26 PM PDT 24
Peak memory 216704 kb
Host smart-08ec0abf-54c9-4e0f-9805-19fd0d912833
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848864389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2848864389
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1711996735
Short name T444
Test name
Test status
Simulation time 397027553 ps
CPU time 2.35 seconds
Started May 23 02:55:58 PM PDT 24
Finished May 23 02:56:05 PM PDT 24
Peak memory 200460 kb
Host smart-1589cb6e-85b3-4794-9895-1481d4be4fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711996735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1711996735
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2907762521
Short name T413
Test name
Test status
Simulation time 230579724 ps
CPU time 1.46 seconds
Started May 23 02:55:57 PM PDT 24
Finished May 23 02:56:01 PM PDT 24
Peak memory 200680 kb
Host smart-1826d5e3-a683-4a49-98f1-0f5ca853ce4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907762521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2907762521
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.2687847800
Short name T503
Test name
Test status
Simulation time 74948373 ps
CPU time 0.81 seconds
Started May 23 02:54:42 PM PDT 24
Finished May 23 02:54:44 PM PDT 24
Peak memory 200336 kb
Host smart-a395b717-e7d3-4d9c-a47b-4ccc5780a7bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687847800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.2687847800
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2468436171
Short name T308
Test name
Test status
Simulation time 1218005226 ps
CPU time 5.64 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:54:54 PM PDT 24
Peak memory 218088 kb
Host smart-3a4eb51b-4e5a-4848-b858-650731fad98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468436171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2468436171
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.187405237
Short name T466
Test name
Test status
Simulation time 244399864 ps
CPU time 1.09 seconds
Started May 23 02:54:43 PM PDT 24
Finished May 23 02:54:45 PM PDT 24
Peak memory 217732 kb
Host smart-25bf5b24-9c01-451d-ac25-db0d3beb6be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187405237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.187405237
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1674189059
Short name T129
Test name
Test status
Simulation time 141985878 ps
CPU time 0.88 seconds
Started May 23 02:54:45 PM PDT 24
Finished May 23 02:54:48 PM PDT 24
Peak memory 200284 kb
Host smart-a6735ac1-4815-4f55-a745-10316dc28688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674189059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1674189059
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2704238895
Short name T380
Test name
Test status
Simulation time 1727755829 ps
CPU time 6.32 seconds
Started May 23 02:54:43 PM PDT 24
Finished May 23 02:54:50 PM PDT 24
Peak memory 200656 kb
Host smart-ae116a59-3d8a-4c22-857a-652b297f1460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704238895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2704238895
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1512005977
Short name T71
Test name
Test status
Simulation time 8515473969 ps
CPU time 13.27 seconds
Started May 23 02:54:47 PM PDT 24
Finished May 23 02:55:04 PM PDT 24
Peak memory 217436 kb
Host smart-f9ad5d98-b4f3-4f15-a70d-ceb3bbf5178a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512005977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1512005977
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1370558879
Short name T217
Test name
Test status
Simulation time 107202995 ps
CPU time 1.03 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:54:51 PM PDT 24
Peak memory 200460 kb
Host smart-e613410c-c65c-4b53-b1a1-da37b6e4a255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370558879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1370558879
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.3884449620
Short name T311
Test name
Test status
Simulation time 194947137 ps
CPU time 1.37 seconds
Started May 23 02:54:48 PM PDT 24
Finished May 23 02:54:53 PM PDT 24
Peak memory 200572 kb
Host smart-defeb8e6-5f82-4fd8-ade8-dfa9cf9c0d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884449620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3884449620
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.4282246849
Short name T237
Test name
Test status
Simulation time 1148620492 ps
CPU time 5.9 seconds
Started May 23 02:54:45 PM PDT 24
Finished May 23 02:54:53 PM PDT 24
Peak memory 200696 kb
Host smart-ffcd60cb-ec82-4fe2-a0ae-9eb5dd7f3f4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282246849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.4282246849
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2594754972
Short name T146
Test name
Test status
Simulation time 114439463 ps
CPU time 1.48 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:54:50 PM PDT 24
Peak memory 200468 kb
Host smart-9e292455-8a5b-4ea2-81d4-f5a2474c9245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594754972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2594754972
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2745214657
Short name T140
Test name
Test status
Simulation time 121788614 ps
CPU time 1.07 seconds
Started May 23 02:54:43 PM PDT 24
Finished May 23 02:54:46 PM PDT 24
Peak memory 200516 kb
Host smart-225b8f13-ad6e-490e-9152-9b76f4762a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745214657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2745214657
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3112443592
Short name T256
Test name
Test status
Simulation time 66659910 ps
CPU time 0.79 seconds
Started May 23 02:56:19 PM PDT 24
Finished May 23 02:56:21 PM PDT 24
Peak memory 200344 kb
Host smart-15ae8a83-e653-4744-97c0-167ee0378715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112443592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3112443592
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3042616918
Short name T399
Test name
Test status
Simulation time 2179626262 ps
CPU time 7.95 seconds
Started May 23 02:56:08 PM PDT 24
Finished May 23 02:56:18 PM PDT 24
Peak memory 218256 kb
Host smart-3a260bed-42bc-491a-bd5e-3958e8089d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042616918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3042616918
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.687426842
Short name T350
Test name
Test status
Simulation time 244032833 ps
CPU time 1.16 seconds
Started May 23 02:56:21 PM PDT 24
Finished May 23 02:56:25 PM PDT 24
Peak memory 217560 kb
Host smart-206dc79f-7073-48c4-803e-8ed5308a1a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687426842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.687426842
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3486901627
Short name T260
Test name
Test status
Simulation time 95369747 ps
CPU time 0.73 seconds
Started May 23 02:56:13 PM PDT 24
Finished May 23 02:56:15 PM PDT 24
Peak memory 200332 kb
Host smart-61a7c7c1-ecb4-4b15-96ac-7c1b58bbb183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486901627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3486901627
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3862562708
Short name T514
Test name
Test status
Simulation time 1801160419 ps
CPU time 6.89 seconds
Started May 23 02:56:08 PM PDT 24
Finished May 23 02:56:16 PM PDT 24
Peak memory 200688 kb
Host smart-540b0162-8312-4571-9347-43bb484426e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862562708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3862562708
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1471988043
Short name T401
Test name
Test status
Simulation time 105146865 ps
CPU time 1.03 seconds
Started May 23 02:56:21 PM PDT 24
Finished May 23 02:56:25 PM PDT 24
Peak memory 200464 kb
Host smart-3633a624-934d-4a2b-a141-ca89f20847f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471988043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1471988043
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2413156658
Short name T119
Test name
Test status
Simulation time 222981792 ps
CPU time 1.46 seconds
Started May 23 02:56:16 PM PDT 24
Finished May 23 02:56:20 PM PDT 24
Peak memory 200636 kb
Host smart-06a0d982-2714-4f5e-91dc-6744b55ee84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413156658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2413156658
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.870843400
Short name T386
Test name
Test status
Simulation time 11642039767 ps
CPU time 47.16 seconds
Started May 23 02:56:14 PM PDT 24
Finished May 23 02:57:03 PM PDT 24
Peak memory 200840 kb
Host smart-d233d92a-ba51-46ac-b1f5-9ae89070d165
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870843400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.870843400
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.1706471012
Short name T77
Test name
Test status
Simulation time 120442040 ps
CPU time 1.49 seconds
Started May 23 02:56:13 PM PDT 24
Finished May 23 02:56:16 PM PDT 24
Peak memory 200496 kb
Host smart-b4f34659-2bd9-4402-99bc-6f0ba9d30f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706471012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1706471012
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.134660715
Short name T249
Test name
Test status
Simulation time 171206736 ps
CPU time 1.34 seconds
Started May 23 02:56:16 PM PDT 24
Finished May 23 02:56:20 PM PDT 24
Peak memory 200688 kb
Host smart-cb46f17d-74fa-4914-9a5b-aed4b6279316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134660715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.134660715
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.4078883934
Short name T53
Test name
Test status
Simulation time 1227545661 ps
CPU time 5.97 seconds
Started May 23 02:56:10 PM PDT 24
Finished May 23 02:56:17 PM PDT 24
Peak memory 222160 kb
Host smart-ca577216-0131-4d68-b757-b48ade8b997b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078883934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.4078883934
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1815778921
Short name T447
Test name
Test status
Simulation time 244160940 ps
CPU time 1.26 seconds
Started May 23 02:56:14 PM PDT 24
Finished May 23 02:56:18 PM PDT 24
Peak memory 217620 kb
Host smart-42ea7d05-cbe5-48aa-9562-0fcf7800a706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815778921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1815778921
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.3488090321
Short name T388
Test name
Test status
Simulation time 154249030 ps
CPU time 0.94 seconds
Started May 23 02:56:13 PM PDT 24
Finished May 23 02:56:16 PM PDT 24
Peak memory 200332 kb
Host smart-00206862-c89a-4ebf-b689-d00b8e2fad71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488090321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3488090321
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3048667266
Short name T215
Test name
Test status
Simulation time 1404544320 ps
CPU time 5.85 seconds
Started May 23 02:56:14 PM PDT 24
Finished May 23 02:56:23 PM PDT 24
Peak memory 200740 kb
Host smart-9f91a872-68b5-40f1-8711-f6a7c08e2014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048667266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3048667266
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3307377432
Short name T383
Test name
Test status
Simulation time 102772853 ps
CPU time 1.01 seconds
Started May 23 02:56:11 PM PDT 24
Finished May 23 02:56:13 PM PDT 24
Peak memory 200536 kb
Host smart-186096fe-255e-448b-93f8-1ddeff18001e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307377432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3307377432
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1590832029
Short name T254
Test name
Test status
Simulation time 189445960 ps
CPU time 1.38 seconds
Started May 23 02:56:11 PM PDT 24
Finished May 23 02:56:13 PM PDT 24
Peak memory 200684 kb
Host smart-10184967-4b5d-456e-a624-4eee32c47449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590832029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1590832029
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.646175637
Short name T418
Test name
Test status
Simulation time 11770995848 ps
CPU time 38.33 seconds
Started May 23 02:56:17 PM PDT 24
Finished May 23 02:56:58 PM PDT 24
Peak memory 209040 kb
Host smart-026c54cc-3a85-4def-bf38-9c3b4c4ab062
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646175637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.646175637
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1718396592
Short name T11
Test name
Test status
Simulation time 117329435 ps
CPU time 1.55 seconds
Started May 23 02:56:08 PM PDT 24
Finished May 23 02:56:11 PM PDT 24
Peak memory 200468 kb
Host smart-c4641939-912d-4f5a-9ceb-3389a203dba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718396592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1718396592
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2610338646
Short name T489
Test name
Test status
Simulation time 133071426 ps
CPU time 1.12 seconds
Started May 23 02:56:16 PM PDT 24
Finished May 23 02:56:20 PM PDT 24
Peak memory 200448 kb
Host smart-f12ae1ba-47ce-487c-bcdd-27483e5c644f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610338646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2610338646
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1815316115
Short name T309
Test name
Test status
Simulation time 62438467 ps
CPU time 0.76 seconds
Started May 23 02:56:15 PM PDT 24
Finished May 23 02:56:19 PM PDT 24
Peak memory 200316 kb
Host smart-90dc3608-db3f-4d71-aa0f-2030e87c79d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815316115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1815316115
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.4010467192
Short name T435
Test name
Test status
Simulation time 2353294722 ps
CPU time 8.55 seconds
Started May 23 02:56:11 PM PDT 24
Finished May 23 02:56:20 PM PDT 24
Peak memory 222296 kb
Host smart-931dff6b-0a8b-41cb-9091-ede57465ef2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010467192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.4010467192
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1865787374
Short name T462
Test name
Test status
Simulation time 244659492 ps
CPU time 1.08 seconds
Started May 23 02:56:12 PM PDT 24
Finished May 23 02:56:14 PM PDT 24
Peak memory 217760 kb
Host smart-cf233285-d941-44cf-bde7-0c0c22749b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865787374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1865787374
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2056630929
Short name T322
Test name
Test status
Simulation time 188575387 ps
CPU time 0.84 seconds
Started May 23 02:56:14 PM PDT 24
Finished May 23 02:56:18 PM PDT 24
Peak memory 200304 kb
Host smart-943ba127-cd71-473f-ad94-7d14fcdd5fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056630929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2056630929
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.3489899085
Short name T316
Test name
Test status
Simulation time 1336378854 ps
CPU time 5.2 seconds
Started May 23 02:56:16 PM PDT 24
Finished May 23 02:56:24 PM PDT 24
Peak memory 200656 kb
Host smart-1b51780e-976e-411d-a0ec-54da9ff34df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489899085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3489899085
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.648271653
Short name T142
Test name
Test status
Simulation time 183911435 ps
CPU time 1.14 seconds
Started May 23 02:56:07 PM PDT 24
Finished May 23 02:56:09 PM PDT 24
Peak memory 200508 kb
Host smart-62d26095-ef79-4923-8ebc-0bb5600ed3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648271653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.648271653
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1138370491
Short name T197
Test name
Test status
Simulation time 225825781 ps
CPU time 1.43 seconds
Started May 23 02:56:16 PM PDT 24
Finished May 23 02:56:20 PM PDT 24
Peak memory 200632 kb
Host smart-1ab860d6-0cda-4806-a68b-81aa757e7bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138370491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1138370491
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.879092546
Short name T304
Test name
Test status
Simulation time 2840637141 ps
CPU time 12.76 seconds
Started May 23 02:56:14 PM PDT 24
Finished May 23 02:56:29 PM PDT 24
Peak memory 200836 kb
Host smart-334e58f4-30a1-4c0d-bf74-6e604c3ddfbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879092546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.879092546
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.2680300095
Short name T214
Test name
Test status
Simulation time 419164426 ps
CPU time 2.35 seconds
Started May 23 02:56:12 PM PDT 24
Finished May 23 02:56:15 PM PDT 24
Peak memory 200488 kb
Host smart-d4111fcd-c922-493d-817d-31882672de47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680300095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.2680300095
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.411092184
Short name T162
Test name
Test status
Simulation time 144651584 ps
CPU time 1.17 seconds
Started May 23 02:56:16 PM PDT 24
Finished May 23 02:56:20 PM PDT 24
Peak memory 200464 kb
Host smart-fcadf7b2-84ec-4471-9647-2b94f77f1175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411092184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.411092184
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2449367904
Short name T161
Test name
Test status
Simulation time 62616127 ps
CPU time 0.82 seconds
Started May 23 02:56:16 PM PDT 24
Finished May 23 02:56:19 PM PDT 24
Peak memory 200308 kb
Host smart-80f7b193-3c6f-4c2a-8739-e4b928697d78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449367904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2449367904
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2954542553
Short name T24
Test name
Test status
Simulation time 1894422002 ps
CPU time 7.96 seconds
Started May 23 02:56:19 PM PDT 24
Finished May 23 02:56:29 PM PDT 24
Peak memory 217156 kb
Host smart-bfd826c3-d491-4321-ae58-76f98ae11830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954542553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2954542553
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1837579872
Short name T481
Test name
Test status
Simulation time 245038235 ps
CPU time 1.06 seconds
Started May 23 02:56:14 PM PDT 24
Finished May 23 02:56:18 PM PDT 24
Peak memory 217568 kb
Host smart-e079586b-6310-4197-bb37-9d9d97be21f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837579872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1837579872
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.3430406983
Short name T57
Test name
Test status
Simulation time 192287602 ps
CPU time 0.88 seconds
Started May 23 02:56:17 PM PDT 24
Finished May 23 02:56:20 PM PDT 24
Peak memory 200276 kb
Host smart-36644176-2641-40d4-8d77-950f0c0ff0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430406983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3430406983
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3312850854
Short name T417
Test name
Test status
Simulation time 1321823771 ps
CPU time 5.05 seconds
Started May 23 02:56:10 PM PDT 24
Finished May 23 02:56:17 PM PDT 24
Peak memory 200688 kb
Host smart-8862ad5c-94cb-41e8-834d-b26c56577831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312850854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3312850854
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1633411020
Short name T144
Test name
Test status
Simulation time 160207955 ps
CPU time 1.16 seconds
Started May 23 02:56:09 PM PDT 24
Finished May 23 02:56:11 PM PDT 24
Peak memory 200496 kb
Host smart-e036b025-4708-48fa-a68d-685d9fdf4e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633411020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1633411020
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.955002699
Short name T470
Test name
Test status
Simulation time 198152036 ps
CPU time 1.46 seconds
Started May 23 02:56:14 PM PDT 24
Finished May 23 02:56:19 PM PDT 24
Peak memory 200696 kb
Host smart-35b5e565-4947-42e3-b68b-60ee4ba46baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955002699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.955002699
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.423659700
Short name T518
Test name
Test status
Simulation time 2954520389 ps
CPU time 13.28 seconds
Started May 23 02:56:15 PM PDT 24
Finished May 23 02:56:31 PM PDT 24
Peak memory 209000 kb
Host smart-781c2446-c03e-4d3f-8874-5905b1069914
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423659700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.423659700
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1177020121
Short name T439
Test name
Test status
Simulation time 387486240 ps
CPU time 2.38 seconds
Started May 23 02:55:58 PM PDT 24
Finished May 23 02:56:05 PM PDT 24
Peak memory 200480 kb
Host smart-0756352d-dcc0-47a1-8d66-164f7e3e90cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177020121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1177020121
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.1853957687
Short name T177
Test name
Test status
Simulation time 86197153 ps
CPU time 0.82 seconds
Started May 23 02:56:21 PM PDT 24
Finished May 23 02:56:24 PM PDT 24
Peak memory 200464 kb
Host smart-4c93102a-64f0-4b4d-95a1-46b2bc771bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853957687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1853957687
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3106492415
Short name T284
Test name
Test status
Simulation time 70745128 ps
CPU time 0.75 seconds
Started May 23 02:56:17 PM PDT 24
Finished May 23 02:56:20 PM PDT 24
Peak memory 200284 kb
Host smart-09bc55a9-ee88-4917-aa4f-87201ddd582f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106492415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3106492415
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.399464841
Short name T409
Test name
Test status
Simulation time 1918056063 ps
CPU time 7.11 seconds
Started May 23 02:56:13 PM PDT 24
Finished May 23 02:56:23 PM PDT 24
Peak memory 218120 kb
Host smart-c37998ba-2c51-442a-9c67-221360e3c6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399464841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.399464841
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3568763824
Short name T58
Test name
Test status
Simulation time 244203981 ps
CPU time 1.11 seconds
Started May 23 02:56:19 PM PDT 24
Finished May 23 02:56:22 PM PDT 24
Peak memory 217768 kb
Host smart-e00f0df9-52fb-42af-aaf7-23087cc8c624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568763824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3568763824
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3416789438
Short name T267
Test name
Test status
Simulation time 163786434 ps
CPU time 0.86 seconds
Started May 23 02:56:21 PM PDT 24
Finished May 23 02:56:25 PM PDT 24
Peak memory 200288 kb
Host smart-fe6818f4-787a-4ec8-a4a0-43fbaff97d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416789438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3416789438
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.212265259
Short name T192
Test name
Test status
Simulation time 965614835 ps
CPU time 4.76 seconds
Started May 23 02:56:13 PM PDT 24
Finished May 23 02:56:19 PM PDT 24
Peak memory 200700 kb
Host smart-188c304d-267e-441e-abdb-0a94afade56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212265259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.212265259
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1462382820
Short name T160
Test name
Test status
Simulation time 105824234 ps
CPU time 0.97 seconds
Started May 23 02:56:09 PM PDT 24
Finished May 23 02:56:11 PM PDT 24
Peak memory 200508 kb
Host smart-b69aa09a-4047-4b59-8a0f-9d3a664b999c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462382820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1462382820
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2845245773
Short name T487
Test name
Test status
Simulation time 107291364 ps
CPU time 1.19 seconds
Started May 23 02:56:14 PM PDT 24
Finished May 23 02:56:18 PM PDT 24
Peak memory 200672 kb
Host smart-ca010e1c-a465-430c-ba95-c51980a7d9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845245773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2845245773
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1854335244
Short name T239
Test name
Test status
Simulation time 1393289911 ps
CPU time 6.64 seconds
Started May 23 02:56:08 PM PDT 24
Finished May 23 02:56:16 PM PDT 24
Peak memory 200688 kb
Host smart-e44adf25-c703-40c7-8b80-29414562b60d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854335244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1854335244
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3679342380
Short name T216
Test name
Test status
Simulation time 278117889 ps
CPU time 1.87 seconds
Started May 23 02:56:14 PM PDT 24
Finished May 23 02:56:18 PM PDT 24
Peak memory 200464 kb
Host smart-91fac4c6-04f7-47fa-8e04-91169e647fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679342380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3679342380
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1994482870
Short name T415
Test name
Test status
Simulation time 76705582 ps
CPU time 0.86 seconds
Started May 23 02:56:13 PM PDT 24
Finished May 23 02:56:15 PM PDT 24
Peak memory 200492 kb
Host smart-3a2fbfa3-91a8-49d6-a758-338ed2227f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994482870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1994482870
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3942448387
Short name T179
Test name
Test status
Simulation time 58650507 ps
CPU time 0.75 seconds
Started May 23 02:56:21 PM PDT 24
Finished May 23 02:56:25 PM PDT 24
Peak memory 200304 kb
Host smart-1b1fe7ab-c441-49e1-80ec-971b2c737dc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942448387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3942448387
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.2569513640
Short name T370
Test name
Test status
Simulation time 2360001878 ps
CPU time 8.04 seconds
Started May 23 02:56:13 PM PDT 24
Finished May 23 02:56:23 PM PDT 24
Peak memory 222312 kb
Host smart-f634d714-95aa-424b-a492-4a443a2e9b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569513640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2569513640
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1465748695
Short name T312
Test name
Test status
Simulation time 244649242 ps
CPU time 1.07 seconds
Started May 23 02:56:14 PM PDT 24
Finished May 23 02:56:17 PM PDT 24
Peak memory 217560 kb
Host smart-b877bcc3-0f02-4280-975e-12a88d3a0a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465748695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1465748695
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.715816127
Short name T147
Test name
Test status
Simulation time 124748148 ps
CPU time 0.78 seconds
Started May 23 02:56:21 PM PDT 24
Finished May 23 02:56:24 PM PDT 24
Peak memory 200276 kb
Host smart-a1e046ed-6e44-48f3-9058-3680069c1a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715816127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.715816127
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1779086944
Short name T509
Test name
Test status
Simulation time 821829313 ps
CPU time 4.33 seconds
Started May 23 02:56:16 PM PDT 24
Finished May 23 02:56:23 PM PDT 24
Peak memory 200672 kb
Host smart-a36a1847-b391-486c-8728-2073b60069fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779086944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1779086944
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1565506971
Short name T171
Test name
Test status
Simulation time 172161017 ps
CPU time 1.19 seconds
Started May 23 02:56:13 PM PDT 24
Finished May 23 02:56:16 PM PDT 24
Peak memory 200488 kb
Host smart-571c1236-37a4-40a3-8e51-6a96755bd290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565506971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1565506971
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1278757875
Short name T455
Test name
Test status
Simulation time 240494777 ps
CPU time 1.51 seconds
Started May 23 02:56:09 PM PDT 24
Finished May 23 02:56:12 PM PDT 24
Peak memory 200632 kb
Host smart-2e081db7-6a64-4d93-a69b-2151ce87dd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278757875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1278757875
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.5991603
Short name T530
Test name
Test status
Simulation time 314082497 ps
CPU time 1.68 seconds
Started May 23 02:56:19 PM PDT 24
Finished May 23 02:56:22 PM PDT 24
Peak memory 200756 kb
Host smart-922e8811-3494-418f-a4b7-21ab23959055
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5991603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.5991603
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.4055849254
Short name T75
Test name
Test status
Simulation time 149654605 ps
CPU time 1.87 seconds
Started May 23 02:56:13 PM PDT 24
Finished May 23 02:56:16 PM PDT 24
Peak memory 200484 kb
Host smart-dfd7707b-2655-461f-ba05-5b9dcaf4a3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055849254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.4055849254
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2696243582
Short name T122
Test name
Test status
Simulation time 285523979 ps
CPU time 1.62 seconds
Started May 23 02:56:11 PM PDT 24
Finished May 23 02:56:14 PM PDT 24
Peak memory 200636 kb
Host smart-861d0044-2cf6-4241-a886-ab1c5b3675ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696243582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2696243582
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3792314793
Short name T199
Test name
Test status
Simulation time 92539146 ps
CPU time 0.85 seconds
Started May 23 02:56:22 PM PDT 24
Finished May 23 02:56:25 PM PDT 24
Peak memory 200296 kb
Host smart-00349b2f-93d1-43ad-9b0d-f3b6dba83c3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792314793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3792314793
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1876145479
Short name T506
Test name
Test status
Simulation time 1894590499 ps
CPU time 7.96 seconds
Started May 23 02:56:23 PM PDT 24
Finished May 23 02:56:34 PM PDT 24
Peak memory 218068 kb
Host smart-58a668b5-8ad0-47a3-b841-64a097bbcb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876145479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1876145479
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2804235666
Short name T159
Test name
Test status
Simulation time 243209315 ps
CPU time 1.1 seconds
Started May 23 02:56:21 PM PDT 24
Finished May 23 02:56:25 PM PDT 24
Peak memory 217556 kb
Host smart-3d5d216d-e5de-4428-8d61-c1cd44dfaa1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804235666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2804235666
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1380657134
Short name T373
Test name
Test status
Simulation time 134203994 ps
CPU time 0.81 seconds
Started May 23 02:56:16 PM PDT 24
Finished May 23 02:56:19 PM PDT 24
Peak memory 200292 kb
Host smart-c4792d33-b2ed-4911-b88b-5f28c835cfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380657134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1380657134
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.4206503170
Short name T431
Test name
Test status
Simulation time 1390626657 ps
CPU time 5.07 seconds
Started May 23 02:56:12 PM PDT 24
Finished May 23 02:56:18 PM PDT 24
Peak memory 200732 kb
Host smart-9928451c-0c01-4ecc-9649-a816d7ad8f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206503170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.4206503170
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3031355341
Short name T299
Test name
Test status
Simulation time 112871049 ps
CPU time 1.02 seconds
Started May 23 02:56:14 PM PDT 24
Finished May 23 02:56:18 PM PDT 24
Peak memory 200508 kb
Host smart-863da562-1ec1-420a-b751-111cfb55391d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031355341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3031355341
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3543267926
Short name T478
Test name
Test status
Simulation time 255692192 ps
CPU time 1.46 seconds
Started May 23 02:56:21 PM PDT 24
Finished May 23 02:56:25 PM PDT 24
Peak memory 200688 kb
Host smart-2f45fc0b-5119-4ae7-867b-5a20c6006600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543267926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3543267926
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.626291091
Short name T93
Test name
Test status
Simulation time 2492346995 ps
CPU time 8.72 seconds
Started May 23 02:56:20 PM PDT 24
Finished May 23 02:56:31 PM PDT 24
Peak memory 200888 kb
Host smart-9481c0d3-972d-4052-bb9d-46d683a0a84e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626291091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.626291091
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.4030104876
Short name T457
Test name
Test status
Simulation time 145363533 ps
CPU time 1.91 seconds
Started May 23 02:56:14 PM PDT 24
Finished May 23 02:56:18 PM PDT 24
Peak memory 200480 kb
Host smart-4dd69dfa-dd8d-4f1f-b73b-f6dc26c10b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030104876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.4030104876
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3184950826
Short name T469
Test name
Test status
Simulation time 135569162 ps
CPU time 1.12 seconds
Started May 23 02:56:08 PM PDT 24
Finished May 23 02:56:11 PM PDT 24
Peak memory 200448 kb
Host smart-4c651c1b-5acb-4127-96e1-c513e8cb7ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184950826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3184950826
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.4198228067
Short name T34
Test name
Test status
Simulation time 87278960 ps
CPU time 0.85 seconds
Started May 23 02:56:22 PM PDT 24
Finished May 23 02:56:26 PM PDT 24
Peak memory 200372 kb
Host smart-c402a671-da3f-4f4c-8ac1-763792ecf98f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198228067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.4198228067
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.823091400
Short name T27
Test name
Test status
Simulation time 1226745522 ps
CPU time 5.62 seconds
Started May 23 02:56:20 PM PDT 24
Finished May 23 02:56:27 PM PDT 24
Peak memory 222216 kb
Host smart-5caae402-2bb2-4519-a3fc-4d3c8fe76d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823091400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.823091400
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.4192506914
Short name T531
Test name
Test status
Simulation time 245167350 ps
CPU time 1.18 seconds
Started May 23 02:56:23 PM PDT 24
Finished May 23 02:56:27 PM PDT 24
Peak memory 217572 kb
Host smart-8a2b61f3-5661-4c47-bb71-b410565bdf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192506914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.4192506914
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1821858697
Short name T16
Test name
Test status
Simulation time 160613747 ps
CPU time 0.86 seconds
Started May 23 02:56:21 PM PDT 24
Finished May 23 02:56:25 PM PDT 24
Peak memory 200312 kb
Host smart-9c0f61e9-f342-4712-9de2-074d7bd88d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821858697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1821858697
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.4012359168
Short name T359
Test name
Test status
Simulation time 1558582452 ps
CPU time 6.91 seconds
Started May 23 02:56:21 PM PDT 24
Finished May 23 02:56:30 PM PDT 24
Peak memory 200604 kb
Host smart-dcf01e77-3fed-4746-b83f-a71d1db6b9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012359168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.4012359168
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3457186460
Short name T438
Test name
Test status
Simulation time 106702868 ps
CPU time 1.02 seconds
Started May 23 02:56:21 PM PDT 24
Finished May 23 02:56:24 PM PDT 24
Peak memory 200500 kb
Host smart-77e70e98-276a-4987-9c6a-a61218ee01c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457186460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3457186460
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1527887490
Short name T495
Test name
Test status
Simulation time 205366208 ps
CPU time 1.38 seconds
Started May 23 02:56:20 PM PDT 24
Finished May 23 02:56:24 PM PDT 24
Peak memory 200700 kb
Host smart-fc6deeaf-15c4-47aa-9f8b-80ebd7ee8ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527887490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1527887490
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.34168809
Short name T86
Test name
Test status
Simulation time 2386836480 ps
CPU time 7.96 seconds
Started May 23 02:56:21 PM PDT 24
Finished May 23 02:56:31 PM PDT 24
Peak memory 209256 kb
Host smart-0d08be63-2774-4ec2-b8d4-baf160f4f3cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34168809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.34168809
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.956241235
Short name T257
Test name
Test status
Simulation time 143163981 ps
CPU time 1.83 seconds
Started May 23 02:56:19 PM PDT 24
Finished May 23 02:56:23 PM PDT 24
Peak memory 200508 kb
Host smart-0269278e-b118-41fa-a3bc-382e042fc084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956241235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.956241235
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2278837134
Short name T22
Test name
Test status
Simulation time 120495983 ps
CPU time 0.96 seconds
Started May 23 02:56:22 PM PDT 24
Finished May 23 02:56:26 PM PDT 24
Peak memory 200488 kb
Host smart-12ac403f-87d4-4479-9f20-ecafd9b3bfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278837134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2278837134
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.1771226351
Short name T222
Test name
Test status
Simulation time 61396334 ps
CPU time 0.77 seconds
Started May 23 02:56:41 PM PDT 24
Finished May 23 02:56:47 PM PDT 24
Peak memory 200344 kb
Host smart-8dcc06b9-89b2-4230-8aac-b7aebcc9079a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771226351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1771226351
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2223276097
Short name T298
Test name
Test status
Simulation time 244523874 ps
CPU time 1.22 seconds
Started May 23 02:56:21 PM PDT 24
Finished May 23 02:56:25 PM PDT 24
Peak memory 217764 kb
Host smart-475965fe-3440-4bb7-b76d-8297f1e7796d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223276097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2223276097
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3288438797
Short name T520
Test name
Test status
Simulation time 211576358 ps
CPU time 0.93 seconds
Started May 23 02:56:22 PM PDT 24
Finished May 23 02:56:26 PM PDT 24
Peak memory 200288 kb
Host smart-51286a28-43a7-42c5-953a-3e1b89637edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288438797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3288438797
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3697731326
Short name T501
Test name
Test status
Simulation time 1614620801 ps
CPU time 6.8 seconds
Started May 23 02:56:22 PM PDT 24
Finished May 23 02:56:31 PM PDT 24
Peak memory 200676 kb
Host smart-01db46c7-466e-48c3-860d-520edfdfecc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697731326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3697731326
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3631045570
Short name T344
Test name
Test status
Simulation time 113159312 ps
CPU time 1.06 seconds
Started May 23 02:56:22 PM PDT 24
Finished May 23 02:56:25 PM PDT 24
Peak memory 200476 kb
Host smart-72a5b8eb-616e-425b-a6db-47dcac75dbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631045570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3631045570
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.4169864639
Short name T535
Test name
Test status
Simulation time 121119390 ps
CPU time 1.18 seconds
Started May 23 02:56:21 PM PDT 24
Finished May 23 02:56:25 PM PDT 24
Peak memory 200668 kb
Host smart-28ce2c38-0b21-46bd-8e8a-3457cfbdac6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169864639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.4169864639
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.2498186951
Short name T269
Test name
Test status
Simulation time 5921240187 ps
CPU time 22.82 seconds
Started May 23 02:56:21 PM PDT 24
Finished May 23 02:56:47 PM PDT 24
Peak memory 210080 kb
Host smart-9bd16761-89d6-496e-9802-7f90ad8fada2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498186951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2498186951
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1271311630
Short name T76
Test name
Test status
Simulation time 146785542 ps
CPU time 1.98 seconds
Started May 23 02:56:21 PM PDT 24
Finished May 23 02:56:25 PM PDT 24
Peak memory 200496 kb
Host smart-cce15354-8cfb-4752-86ab-dc8a7aaddf96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271311630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1271311630
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.452969966
Short name T420
Test name
Test status
Simulation time 217737434 ps
CPU time 1.45 seconds
Started May 23 02:56:23 PM PDT 24
Finished May 23 02:56:27 PM PDT 24
Peak memory 200476 kb
Host smart-3d5a6a47-8dda-48c1-ade9-d089e560d938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452969966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.452969966
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1373194322
Short name T250
Test name
Test status
Simulation time 70692047 ps
CPU time 0.74 seconds
Started May 23 02:56:41 PM PDT 24
Finished May 23 02:56:46 PM PDT 24
Peak memory 200096 kb
Host smart-4301870d-46e6-467c-91f2-976a1c444d7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373194322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1373194322
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3190229303
Short name T29
Test name
Test status
Simulation time 1227500706 ps
CPU time 5.92 seconds
Started May 23 02:56:37 PM PDT 24
Finished May 23 02:56:44 PM PDT 24
Peak memory 217672 kb
Host smart-53379bf4-d5b0-4089-99f7-2c4ca7c48752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190229303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3190229303
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1056352819
Short name T477
Test name
Test status
Simulation time 244070383 ps
CPU time 1.11 seconds
Started May 23 02:56:39 PM PDT 24
Finished May 23 02:56:44 PM PDT 24
Peak memory 217600 kb
Host smart-60ac8e05-c0b8-48a6-aaa1-b3b1cbc8a74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056352819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1056352819
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.3413034641
Short name T183
Test name
Test status
Simulation time 214991532 ps
CPU time 0.89 seconds
Started May 23 02:56:40 PM PDT 24
Finished May 23 02:56:45 PM PDT 24
Peak memory 200304 kb
Host smart-a4acf87c-6c8b-4181-90b1-8b31e2438dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413034641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3413034641
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.4158539288
Short name T448
Test name
Test status
Simulation time 1085001310 ps
CPU time 5.79 seconds
Started May 23 02:56:38 PM PDT 24
Finished May 23 02:56:46 PM PDT 24
Peak memory 200716 kb
Host smart-e2ce2bd2-9e70-4e6d-a5b6-1a48013b151d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158539288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.4158539288
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1526826629
Short name T402
Test name
Test status
Simulation time 97482959 ps
CPU time 0.96 seconds
Started May 23 02:56:39 PM PDT 24
Finished May 23 02:56:44 PM PDT 24
Peak memory 200544 kb
Host smart-7f6218ce-224d-40d7-a1e1-61463dbe4a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526826629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1526826629
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3069979263
Short name T246
Test name
Test status
Simulation time 221817692 ps
CPU time 1.54 seconds
Started May 23 02:56:40 PM PDT 24
Finished May 23 02:56:46 PM PDT 24
Peak memory 200712 kb
Host smart-74e300e9-fe61-4aba-901d-3dfe2195e0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069979263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3069979263
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2384746708
Short name T310
Test name
Test status
Simulation time 3863390718 ps
CPU time 15.51 seconds
Started May 23 02:56:39 PM PDT 24
Finished May 23 02:56:59 PM PDT 24
Peak memory 200848 kb
Host smart-248eeab2-c7dc-4297-82bb-1f50492583b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384746708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2384746708
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1538084587
Short name T429
Test name
Test status
Simulation time 137024891 ps
CPU time 1.91 seconds
Started May 23 02:56:39 PM PDT 24
Finished May 23 02:56:45 PM PDT 24
Peak memory 208772 kb
Host smart-34b96235-4147-4c8c-bdd5-8a4afc459947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538084587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1538084587
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.4062637502
Short name T266
Test name
Test status
Simulation time 222860890 ps
CPU time 1.36 seconds
Started May 23 02:56:38 PM PDT 24
Finished May 23 02:56:43 PM PDT 24
Peak memory 200560 kb
Host smart-6bfce0a2-9a6d-4f41-83c6-902ed107d1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062637502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.4062637502
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3889389198
Short name T165
Test name
Test status
Simulation time 57366343 ps
CPU time 0.74 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:54:50 PM PDT 24
Peak memory 200336 kb
Host smart-f9f2626b-4c46-464b-8971-133428dbcd9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889389198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3889389198
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2610987334
Short name T285
Test name
Test status
Simulation time 2367210503 ps
CPU time 8.21 seconds
Started May 23 02:54:45 PM PDT 24
Finished May 23 02:54:56 PM PDT 24
Peak memory 218252 kb
Host smart-d283d2e5-507d-4be7-8b8d-ef772583d0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610987334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2610987334
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.999521364
Short name T390
Test name
Test status
Simulation time 244322591 ps
CPU time 1.17 seconds
Started May 23 02:54:44 PM PDT 24
Finished May 23 02:54:47 PM PDT 24
Peak memory 217748 kb
Host smart-b0c32902-83d9-435a-95f7-13997f26e7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999521364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.999521364
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.2794366922
Short name T9
Test name
Test status
Simulation time 221486616 ps
CPU time 0.92 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:54:51 PM PDT 24
Peak memory 200260 kb
Host smart-e83e3e53-91a9-4464-bc67-5e520fcd622f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794366922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2794366922
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.423541030
Short name T263
Test name
Test status
Simulation time 968086880 ps
CPU time 4.9 seconds
Started May 23 02:54:44 PM PDT 24
Finished May 23 02:54:51 PM PDT 24
Peak memory 200728 kb
Host smart-cab7847d-b943-43b9-9d7b-f74aeeee5b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423541030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.423541030
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.4226806560
Short name T73
Test name
Test status
Simulation time 17274843357 ps
CPU time 25.74 seconds
Started May 23 02:54:44 PM PDT 24
Finished May 23 02:55:11 PM PDT 24
Peak memory 217588 kb
Host smart-109fbaa5-2ff2-4a0e-941a-2bdab37b060e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226806560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.4226806560
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1819562654
Short name T403
Test name
Test status
Simulation time 165195668 ps
CPU time 1.13 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:54:50 PM PDT 24
Peak memory 200512 kb
Host smart-28e1103d-01b1-4d2f-816b-3e46926de773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819562654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1819562654
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1177450632
Short name T182
Test name
Test status
Simulation time 124201524 ps
CPU time 1.14 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:54:50 PM PDT 24
Peak memory 200580 kb
Host smart-ad2b5d09-e3ba-40e9-89f8-eb0cfd9b5551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177450632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1177450632
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2782261481
Short name T253
Test name
Test status
Simulation time 886961469 ps
CPU time 5.01 seconds
Started May 23 02:54:43 PM PDT 24
Finished May 23 02:54:50 PM PDT 24
Peak memory 200684 kb
Host smart-bac7d90c-2a5d-43b3-ae20-e85d146c0f11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782261481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2782261481
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3666834535
Short name T203
Test name
Test status
Simulation time 482154873 ps
CPU time 2.49 seconds
Started May 23 02:54:47 PM PDT 24
Finished May 23 02:54:53 PM PDT 24
Peak memory 208796 kb
Host smart-fe401853-1b31-4956-ac9a-e7775c88b46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666834535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3666834535
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.211335986
Short name T449
Test name
Test status
Simulation time 100651669 ps
CPU time 0.98 seconds
Started May 23 02:54:47 PM PDT 24
Finished May 23 02:54:51 PM PDT 24
Peak memory 200500 kb
Host smart-ed34ba5f-468b-441c-9298-a6fadeaaf1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211335986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.211335986
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3224947328
Short name T394
Test name
Test status
Simulation time 70563257 ps
CPU time 0.78 seconds
Started May 23 02:56:40 PM PDT 24
Finished May 23 02:56:44 PM PDT 24
Peak memory 200256 kb
Host smart-4f4e3587-07d5-497c-80c8-60dbe765b233
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224947328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3224947328
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2369963820
Short name T411
Test name
Test status
Simulation time 1896386225 ps
CPU time 7.54 seconds
Started May 23 02:56:38 PM PDT 24
Finished May 23 02:56:47 PM PDT 24
Peak memory 217648 kb
Host smart-8486d1ca-4a56-411e-ba86-bf854e2ba995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369963820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2369963820
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.214102562
Short name T8
Test name
Test status
Simulation time 248287416 ps
CPU time 1.09 seconds
Started May 23 02:56:44 PM PDT 24
Finished May 23 02:56:49 PM PDT 24
Peak memory 217576 kb
Host smart-a863c98e-bc34-4679-b74e-f9f7c7df9aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214102562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.214102562
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3013357865
Short name T185
Test name
Test status
Simulation time 148493911 ps
CPU time 0.85 seconds
Started May 23 02:56:41 PM PDT 24
Finished May 23 02:56:47 PM PDT 24
Peak memory 200332 kb
Host smart-236e7615-de29-4deb-99a1-e9c8b388cca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013357865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3013357865
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2186144257
Short name T196
Test name
Test status
Simulation time 867074517 ps
CPU time 4.97 seconds
Started May 23 02:56:38 PM PDT 24
Finished May 23 02:56:47 PM PDT 24
Peak memory 200748 kb
Host smart-007680f8-8cb5-463e-9d13-b84baa5623fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186144257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2186144257
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2533604121
Short name T141
Test name
Test status
Simulation time 173690741 ps
CPU time 1.19 seconds
Started May 23 02:56:44 PM PDT 24
Finished May 23 02:56:50 PM PDT 24
Peak memory 200476 kb
Host smart-4dc15907-4914-4802-b431-a5dbc2597c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533604121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2533604121
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2435576559
Short name T476
Test name
Test status
Simulation time 236112867 ps
CPU time 1.52 seconds
Started May 23 02:56:41 PM PDT 24
Finished May 23 02:56:47 PM PDT 24
Peak memory 200664 kb
Host smart-016e2b40-cade-4260-8a70-79778a9b40b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435576559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2435576559
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2077130621
Short name T205
Test name
Test status
Simulation time 1728493496 ps
CPU time 6.99 seconds
Started May 23 02:56:39 PM PDT 24
Finished May 23 02:56:50 PM PDT 24
Peak memory 208880 kb
Host smart-619671bc-6703-4b45-ac46-eb505c1a5346
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077130621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2077130621
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.3875356187
Short name T384
Test name
Test status
Simulation time 530874533 ps
CPU time 2.68 seconds
Started May 23 02:56:40 PM PDT 24
Finished May 23 02:56:46 PM PDT 24
Peak memory 200512 kb
Host smart-0f864492-c9f5-4b38-94d9-88add90123b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875356187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3875356187
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2077438685
Short name T277
Test name
Test status
Simulation time 186820163 ps
CPU time 1.23 seconds
Started May 23 02:56:40 PM PDT 24
Finished May 23 02:56:46 PM PDT 24
Peak memory 200504 kb
Host smart-3e672c6c-0c59-4d23-a307-430e2a7b6329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077438685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2077438685
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1703165095
Short name T219
Test name
Test status
Simulation time 70363897 ps
CPU time 0.8 seconds
Started May 23 02:56:40 PM PDT 24
Finished May 23 02:56:46 PM PDT 24
Peak memory 200328 kb
Host smart-62b20d41-daad-4828-85a6-87bb60e0f51d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703165095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1703165095
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.906117533
Short name T396
Test name
Test status
Simulation time 1231832439 ps
CPU time 6.09 seconds
Started May 23 02:56:42 PM PDT 24
Finished May 23 02:56:53 PM PDT 24
Peak memory 222084 kb
Host smart-724e463d-651e-4cc8-bd3c-ef2875642268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906117533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.906117533
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2595113360
Short name T193
Test name
Test status
Simulation time 244941370 ps
CPU time 1.05 seconds
Started May 23 02:56:39 PM PDT 24
Finished May 23 02:56:44 PM PDT 24
Peak memory 217600 kb
Host smart-33de3388-bfa7-4910-9a5a-ef55708328a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595113360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2595113360
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.2466507676
Short name T169
Test name
Test status
Simulation time 97956699 ps
CPU time 0.73 seconds
Started May 23 02:56:44 PM PDT 24
Finished May 23 02:56:49 PM PDT 24
Peak memory 200328 kb
Host smart-500da0fc-d484-437f-ac10-4480d4c03db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466507676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2466507676
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.40835575
Short name T245
Test name
Test status
Simulation time 1668253035 ps
CPU time 6.22 seconds
Started May 23 02:56:40 PM PDT 24
Finished May 23 02:56:50 PM PDT 24
Peak memory 200740 kb
Host smart-bc6800b6-10f6-4826-bcff-684ad6cd9437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40835575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.40835575
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1576116287
Short name T348
Test name
Test status
Simulation time 108991292 ps
CPU time 1.1 seconds
Started May 23 02:56:41 PM PDT 24
Finished May 23 02:56:47 PM PDT 24
Peak memory 200504 kb
Host smart-06cf3029-a5b5-457a-927d-684d3ebdc72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576116287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1576116287
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2562471758
Short name T175
Test name
Test status
Simulation time 128658790 ps
CPU time 1.19 seconds
Started May 23 02:56:38 PM PDT 24
Finished May 23 02:56:40 PM PDT 24
Peak memory 200684 kb
Host smart-ff7a4557-cec7-4a93-b0f9-22567da9f29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562471758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2562471758
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.446774537
Short name T255
Test name
Test status
Simulation time 413119551 ps
CPU time 2.31 seconds
Started May 23 02:56:41 PM PDT 24
Finished May 23 02:56:47 PM PDT 24
Peak memory 200688 kb
Host smart-7b088e56-4f1b-4b9a-a953-649d8b97f1dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446774537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.446774537
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1775923590
Short name T290
Test name
Test status
Simulation time 124068948 ps
CPU time 1.56 seconds
Started May 23 02:56:40 PM PDT 24
Finished May 23 02:56:45 PM PDT 24
Peak memory 208976 kb
Host smart-5c6f7ab4-9813-4eb6-9c79-400807b18613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775923590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1775923590
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3423605346
Short name T406
Test name
Test status
Simulation time 277281005 ps
CPU time 1.63 seconds
Started May 23 02:56:38 PM PDT 24
Finished May 23 02:56:43 PM PDT 24
Peak memory 200668 kb
Host smart-5c8569bb-6401-43ca-b941-bcbda493fbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423605346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3423605346
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1480778591
Short name T46
Test name
Test status
Simulation time 54774459 ps
CPU time 0.72 seconds
Started May 23 02:56:41 PM PDT 24
Finished May 23 02:56:46 PM PDT 24
Peak memory 200340 kb
Host smart-3cc71d4b-ccb3-468b-a43b-0169d9cb9dde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480778591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1480778591
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.3256255784
Short name T445
Test name
Test status
Simulation time 1898720915 ps
CPU time 7.05 seconds
Started May 23 02:56:39 PM PDT 24
Finished May 23 02:56:50 PM PDT 24
Peak memory 217628 kb
Host smart-5b550f26-7864-47cc-b6eb-0b09bd47738d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256255784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.3256255784
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.453041980
Short name T331
Test name
Test status
Simulation time 244536646 ps
CPU time 1.08 seconds
Started May 23 02:56:40 PM PDT 24
Finished May 23 02:56:46 PM PDT 24
Peak memory 217568 kb
Host smart-cb98a899-597f-469d-a11e-6dffac7b6c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453041980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.453041980
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2272297295
Short name T15
Test name
Test status
Simulation time 108374074 ps
CPU time 0.79 seconds
Started May 23 02:56:41 PM PDT 24
Finished May 23 02:56:47 PM PDT 24
Peak memory 200316 kb
Host smart-e4709941-1ce8-44c2-bd59-9b6ddbffecbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272297295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2272297295
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.937598427
Short name T195
Test name
Test status
Simulation time 885835982 ps
CPU time 4.79 seconds
Started May 23 02:56:40 PM PDT 24
Finished May 23 02:56:50 PM PDT 24
Peak memory 200668 kb
Host smart-8db756d6-19a0-4258-9938-7cceffa13c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937598427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.937598427
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2131333299
Short name T226
Test name
Test status
Simulation time 99914374 ps
CPU time 1.04 seconds
Started May 23 02:56:37 PM PDT 24
Finished May 23 02:56:39 PM PDT 24
Peak memory 200504 kb
Host smart-f268dcad-b06f-4b02-8186-86d44a0d2871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131333299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2131333299
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3599178574
Short name T302
Test name
Test status
Simulation time 204244043 ps
CPU time 1.34 seconds
Started May 23 02:56:36 PM PDT 24
Finished May 23 02:56:38 PM PDT 24
Peak memory 200680 kb
Host smart-cc0b933e-7502-4ea0-8b21-0af9a28d5c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599178574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3599178574
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.439511834
Short name T92
Test name
Test status
Simulation time 5224313005 ps
CPU time 25.33 seconds
Started May 23 02:56:37 PM PDT 24
Finished May 23 02:57:03 PM PDT 24
Peak memory 210780 kb
Host smart-4319b274-975f-4785-a7fd-4ad3bfbcbf6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439511834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.439511834
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1029291644
Short name T61
Test name
Test status
Simulation time 144779996 ps
CPU time 1.81 seconds
Started May 23 02:56:39 PM PDT 24
Finished May 23 02:56:44 PM PDT 24
Peak memory 200464 kb
Host smart-f8338f67-d33a-4d34-a79b-75156b7ce872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029291644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1029291644
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3112805977
Short name T425
Test name
Test status
Simulation time 153908582 ps
CPU time 1.06 seconds
Started May 23 02:56:41 PM PDT 24
Finished May 23 02:56:47 PM PDT 24
Peak memory 200480 kb
Host smart-5c22351b-b0db-4825-8aaa-f773d32c78d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112805977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3112805977
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.1570529534
Short name T229
Test name
Test status
Simulation time 70991660 ps
CPU time 0.77 seconds
Started May 23 02:56:43 PM PDT 24
Finished May 23 02:56:49 PM PDT 24
Peak memory 200316 kb
Host smart-5f07cd33-d452-4d1c-b710-bd9976cce089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570529534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1570529534
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3882194165
Short name T508
Test name
Test status
Simulation time 2376880579 ps
CPU time 7.98 seconds
Started May 23 02:56:44 PM PDT 24
Finished May 23 02:56:56 PM PDT 24
Peak memory 217960 kb
Host smart-d38d3984-be3d-4cc2-a7e5-6c57d3db5c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882194165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3882194165
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1743584733
Short name T324
Test name
Test status
Simulation time 244416793 ps
CPU time 1.13 seconds
Started May 23 02:56:41 PM PDT 24
Finished May 23 02:56:46 PM PDT 24
Peak memory 217372 kb
Host smart-05cbcc59-1652-4bd3-8b20-c83c0b2015de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743584733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1743584733
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3706113327
Short name T303
Test name
Test status
Simulation time 103773138 ps
CPU time 0.8 seconds
Started May 23 02:56:38 PM PDT 24
Finished May 23 02:56:40 PM PDT 24
Peak memory 200316 kb
Host smart-236d88b9-958d-4090-b01a-6dabd221ab3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706113327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3706113327
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2077108576
Short name T486
Test name
Test status
Simulation time 880036250 ps
CPU time 4.52 seconds
Started May 23 02:56:40 PM PDT 24
Finished May 23 02:56:49 PM PDT 24
Peak memory 200688 kb
Host smart-9cb2d5b6-1e32-416e-95a2-1c4d4eb7e769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077108576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2077108576
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.4252069651
Short name T433
Test name
Test status
Simulation time 173904106 ps
CPU time 1.14 seconds
Started May 23 02:56:39 PM PDT 24
Finished May 23 02:56:44 PM PDT 24
Peak memory 200544 kb
Host smart-5797e6d6-ce2e-499e-b631-d7f428de64c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252069651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.4252069651
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2087946784
Short name T231
Test name
Test status
Simulation time 121499868 ps
CPU time 1.17 seconds
Started May 23 02:56:39 PM PDT 24
Finished May 23 02:56:44 PM PDT 24
Peak memory 200700 kb
Host smart-46a2b728-ff93-4e35-904b-bd40ebcae8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087946784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2087946784
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1762254885
Short name T97
Test name
Test status
Simulation time 4738650928 ps
CPU time 17.81 seconds
Started May 23 02:56:40 PM PDT 24
Finished May 23 02:57:02 PM PDT 24
Peak memory 200892 kb
Host smart-7a57e715-330a-4ceb-9669-9f1fb57172b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762254885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1762254885
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1329874169
Short name T184
Test name
Test status
Simulation time 132372498 ps
CPU time 1.58 seconds
Started May 23 02:56:39 PM PDT 24
Finished May 23 02:56:45 PM PDT 24
Peak memory 208712 kb
Host smart-71a40bcc-2596-48db-a8c8-38cadddd19a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329874169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1329874169
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1460899161
Short name T225
Test name
Test status
Simulation time 62569035 ps
CPU time 0.77 seconds
Started May 23 02:56:36 PM PDT 24
Finished May 23 02:56:38 PM PDT 24
Peak memory 200504 kb
Host smart-586f428a-b70b-4f9c-b549-614a05bc1cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460899161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1460899161
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.250452776
Short name T208
Test name
Test status
Simulation time 76528283 ps
CPU time 0.82 seconds
Started May 23 02:56:40 PM PDT 24
Finished May 23 02:56:46 PM PDT 24
Peak memory 200244 kb
Host smart-0fe6d94a-669c-42e4-8599-54f120e0e7fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250452776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.250452776
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3832303593
Short name T44
Test name
Test status
Simulation time 1233124699 ps
CPU time 6.73 seconds
Started May 23 02:56:40 PM PDT 24
Finished May 23 02:56:51 PM PDT 24
Peak memory 221640 kb
Host smart-60f2dc6a-c03e-40bd-97ae-89cc1fb9ce9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832303593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3832303593
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1866547943
Short name T385
Test name
Test status
Simulation time 243236281 ps
CPU time 1.17 seconds
Started May 23 02:56:29 PM PDT 24
Finished May 23 02:56:31 PM PDT 24
Peak memory 217552 kb
Host smart-61399b0c-92ac-4254-a5cf-ffaf85ee91da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866547943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1866547943
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2025657630
Short name T163
Test name
Test status
Simulation time 121525734 ps
CPU time 0.8 seconds
Started May 23 02:56:43 PM PDT 24
Finished May 23 02:56:49 PM PDT 24
Peak memory 200300 kb
Host smart-6d3ea7e6-2697-42fd-ad70-e98fd4cfac23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025657630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2025657630
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3802210694
Short name T336
Test name
Test status
Simulation time 1389588727 ps
CPU time 5.47 seconds
Started May 23 02:56:44 PM PDT 24
Finished May 23 02:56:54 PM PDT 24
Peak memory 200692 kb
Host smart-66e562f9-1246-4430-ad5c-a26c13a12f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802210694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3802210694
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.143068186
Short name T143
Test name
Test status
Simulation time 174694092 ps
CPU time 1.15 seconds
Started May 23 02:56:42 PM PDT 24
Finished May 23 02:56:48 PM PDT 24
Peak memory 200508 kb
Host smart-d5d1a63a-b8cf-4b85-bea3-8dbc8221eeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143068186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.143068186
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1065375644
Short name T416
Test name
Test status
Simulation time 113665992 ps
CPU time 1.21 seconds
Started May 23 02:56:41 PM PDT 24
Finished May 23 02:56:47 PM PDT 24
Peak memory 200664 kb
Host smart-a851eed5-5c9a-424e-b17c-1c3ab697b48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065375644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1065375644
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1562084729
Short name T345
Test name
Test status
Simulation time 3778938354 ps
CPU time 18.6 seconds
Started May 23 02:56:40 PM PDT 24
Finished May 23 02:57:02 PM PDT 24
Peak memory 209032 kb
Host smart-966e82de-4d05-43bf-bf5d-dc2fe020980c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562084729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1562084729
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.597641859
Short name T236
Test name
Test status
Simulation time 124912480 ps
CPU time 1.59 seconds
Started May 23 02:56:40 PM PDT 24
Finished May 23 02:56:46 PM PDT 24
Peak memory 208708 kb
Host smart-438c0f6b-19af-49d0-a080-f1cca93eed42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597641859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.597641859
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.3728199048
Short name T137
Test name
Test status
Simulation time 93165468 ps
CPU time 0.94 seconds
Started May 23 02:56:38 PM PDT 24
Finished May 23 02:56:41 PM PDT 24
Peak memory 200516 kb
Host smart-43892f68-a695-4871-9c27-2b3ef7798355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728199048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3728199048
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.2994474223
Short name T151
Test name
Test status
Simulation time 75290293 ps
CPU time 0.81 seconds
Started May 23 02:56:54 PM PDT 24
Finished May 23 02:56:56 PM PDT 24
Peak memory 200332 kb
Host smart-6fe24a2f-6a6d-44c0-957c-534f0b433815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994474223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2994474223
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2887154575
Short name T528
Test name
Test status
Simulation time 1224910502 ps
CPU time 5.8 seconds
Started May 23 02:56:55 PM PDT 24
Finished May 23 02:57:02 PM PDT 24
Peak memory 230392 kb
Host smart-05e51b7f-854b-4524-9c9e-4c7e816f95a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887154575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2887154575
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3045188151
Short name T497
Test name
Test status
Simulation time 244208862 ps
CPU time 1.03 seconds
Started May 23 02:56:53 PM PDT 24
Finished May 23 02:56:56 PM PDT 24
Peak memory 217740 kb
Host smart-833e90b8-d6c4-4629-9c74-b76671a5bd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045188151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3045188151
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3775822341
Short name T19
Test name
Test status
Simulation time 92866729 ps
CPU time 0.77 seconds
Started May 23 02:56:38 PM PDT 24
Finished May 23 02:56:42 PM PDT 24
Peak memory 200328 kb
Host smart-04e5aa39-5d97-4233-a40a-4643137bb54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775822341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3775822341
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.614934222
Short name T271
Test name
Test status
Simulation time 1714501371 ps
CPU time 6.37 seconds
Started May 23 02:56:59 PM PDT 24
Finished May 23 02:57:08 PM PDT 24
Peak memory 200640 kb
Host smart-e32c1d93-bc38-417a-ab46-d077837b9a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614934222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.614934222
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2489364676
Short name T174
Test name
Test status
Simulation time 174624927 ps
CPU time 1.2 seconds
Started May 23 02:56:56 PM PDT 24
Finished May 23 02:57:00 PM PDT 24
Peak memory 200484 kb
Host smart-2b61c9f0-18b7-413b-a417-2136b1e18b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489364676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2489364676
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.127891431
Short name T49
Test name
Test status
Simulation time 233032576 ps
CPU time 1.38 seconds
Started May 23 02:56:42 PM PDT 24
Finished May 23 02:56:48 PM PDT 24
Peak memory 200668 kb
Host smart-34f7a359-4c53-4ebb-9ac3-56aac998bc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127891431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.127891431
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.4130679260
Short name T23
Test name
Test status
Simulation time 8724135056 ps
CPU time 28.99 seconds
Started May 23 02:56:54 PM PDT 24
Finished May 23 02:57:24 PM PDT 24
Peak memory 209036 kb
Host smart-ef5090ef-c3ed-4426-a99c-6cf194c3a4f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130679260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.4130679260
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3895823620
Short name T149
Test name
Test status
Simulation time 141416057 ps
CPU time 1.82 seconds
Started May 23 02:56:54 PM PDT 24
Finished May 23 02:56:57 PM PDT 24
Peak memory 200484 kb
Host smart-0221061b-42bb-40e8-9dbf-bc17ac556f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895823620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3895823620
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.280971885
Short name T453
Test name
Test status
Simulation time 174620590 ps
CPU time 1.29 seconds
Started May 23 02:56:57 PM PDT 24
Finished May 23 02:57:02 PM PDT 24
Peak memory 200684 kb
Host smart-e74169c9-488b-42ca-81b8-cf2c7679a56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280971885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.280971885
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2010541039
Short name T458
Test name
Test status
Simulation time 176166555 ps
CPU time 1.06 seconds
Started May 23 02:56:53 PM PDT 24
Finished May 23 02:56:56 PM PDT 24
Peak memory 200316 kb
Host smart-5015728a-5f28-45b4-afd7-01aa6c104407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010541039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2010541039
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.209222408
Short name T40
Test name
Test status
Simulation time 1224623966 ps
CPU time 5.95 seconds
Started May 23 02:56:58 PM PDT 24
Finished May 23 02:57:06 PM PDT 24
Peak memory 217412 kb
Host smart-76228792-804c-4167-a93e-fcf1ac151ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209222408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.209222408
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2666093647
Short name T339
Test name
Test status
Simulation time 243733961 ps
CPU time 1.17 seconds
Started May 23 02:56:56 PM PDT 24
Finished May 23 02:57:00 PM PDT 24
Peak memory 217708 kb
Host smart-c59712bf-ebb1-45a0-980c-0e726413fee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666093647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2666093647
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.1842780650
Short name T251
Test name
Test status
Simulation time 215749062 ps
CPU time 1.01 seconds
Started May 23 02:56:58 PM PDT 24
Finished May 23 02:57:02 PM PDT 24
Peak memory 200312 kb
Host smart-7241d541-4cc6-457a-9501-84ae3af379c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842780650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1842780650
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1929262159
Short name T232
Test name
Test status
Simulation time 1886718209 ps
CPU time 7.33 seconds
Started May 23 02:56:55 PM PDT 24
Finished May 23 02:57:03 PM PDT 24
Peak memory 200672 kb
Host smart-1cd5331b-fd50-485a-9a14-d1019a25d0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929262159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1929262159
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1282425066
Short name T282
Test name
Test status
Simulation time 171652445 ps
CPU time 1.25 seconds
Started May 23 02:56:58 PM PDT 24
Finished May 23 02:57:02 PM PDT 24
Peak memory 200516 kb
Host smart-89cf7826-0700-4bc5-b426-6fe8fb10423e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282425066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1282425066
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.575750023
Short name T291
Test name
Test status
Simulation time 109578491 ps
CPU time 1.24 seconds
Started May 23 02:56:57 PM PDT 24
Finished May 23 02:57:01 PM PDT 24
Peak memory 200684 kb
Host smart-845ecd55-c649-4996-9911-1c996aeb9a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575750023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.575750023
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.368303224
Short name T494
Test name
Test status
Simulation time 2084681297 ps
CPU time 9.46 seconds
Started May 23 02:56:59 PM PDT 24
Finished May 23 02:57:11 PM PDT 24
Peak memory 208948 kb
Host smart-91c2c464-f746-44b3-aeb4-e141be317d73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368303224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.368303224
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.682650700
Short name T170
Test name
Test status
Simulation time 114402431 ps
CPU time 1.53 seconds
Started May 23 02:56:54 PM PDT 24
Finished May 23 02:56:57 PM PDT 24
Peak memory 200464 kb
Host smart-d668c570-c041-4ff2-9510-5b6aa0bf3938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682650700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.682650700
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2731335450
Short name T54
Test name
Test status
Simulation time 84943798 ps
CPU time 0.85 seconds
Started May 23 02:56:55 PM PDT 24
Finished May 23 02:56:57 PM PDT 24
Peak memory 200472 kb
Host smart-2e03b510-18d9-48ed-bf37-1477a89f882e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731335450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2731335450
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3878605535
Short name T228
Test name
Test status
Simulation time 69579575 ps
CPU time 0.77 seconds
Started May 23 02:56:55 PM PDT 24
Finished May 23 02:56:57 PM PDT 24
Peak memory 200312 kb
Host smart-44337935-6af4-4218-9182-848ac3d12ff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878605535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3878605535
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2732535052
Short name T35
Test name
Test status
Simulation time 1227742957 ps
CPU time 5.67 seconds
Started May 23 02:57:01 PM PDT 24
Finished May 23 02:57:09 PM PDT 24
Peak memory 222136 kb
Host smart-aaf46ec8-112e-4d0f-a53f-7e81ef2b4705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732535052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2732535052
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.394576330
Short name T132
Test name
Test status
Simulation time 259661127 ps
CPU time 1.13 seconds
Started May 23 02:57:01 PM PDT 24
Finished May 23 02:57:05 PM PDT 24
Peak memory 217704 kb
Host smart-973f7450-c4c0-4014-8b4c-9d4b07e2208f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394576330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.394576330
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.1999646265
Short name T265
Test name
Test status
Simulation time 147154509 ps
CPU time 0.91 seconds
Started May 23 02:56:55 PM PDT 24
Finished May 23 02:56:58 PM PDT 24
Peak memory 200308 kb
Host smart-7ee251fc-d480-487e-92c9-04ff0fb9dd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999646265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1999646265
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.3216246836
Short name T288
Test name
Test status
Simulation time 1824926090 ps
CPU time 7.53 seconds
Started May 23 02:56:55 PM PDT 24
Finished May 23 02:57:04 PM PDT 24
Peak memory 200700 kb
Host smart-bf0eb77a-b7f2-4c31-ba16-f692bf70cb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216246836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3216246836
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1481933830
Short name T498
Test name
Test status
Simulation time 153900684 ps
CPU time 1.15 seconds
Started May 23 02:56:55 PM PDT 24
Finished May 23 02:56:57 PM PDT 24
Peak memory 200464 kb
Host smart-a3847624-e3b8-474e-877b-002fcbd22df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481933830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1481933830
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.3933981529
Short name T248
Test name
Test status
Simulation time 253500917 ps
CPU time 1.53 seconds
Started May 23 02:57:00 PM PDT 24
Finished May 23 02:57:05 PM PDT 24
Peak memory 200652 kb
Host smart-acc57630-4bec-4ad1-8acb-36d2032a25e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933981529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3933981529
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1823106056
Short name T340
Test name
Test status
Simulation time 5178112620 ps
CPU time 24.44 seconds
Started May 23 02:56:54 PM PDT 24
Finished May 23 02:57:20 PM PDT 24
Peak memory 209024 kb
Host smart-6e2448d9-c8eb-47f2-9391-3b609772eddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823106056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1823106056
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2964350574
Short name T300
Test name
Test status
Simulation time 283273693 ps
CPU time 1.94 seconds
Started May 23 02:56:53 PM PDT 24
Finished May 23 02:56:56 PM PDT 24
Peak memory 200508 kb
Host smart-12f2e51d-b35d-4e09-a5c4-8134a7da004a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964350574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2964350574
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3508801283
Short name T128
Test name
Test status
Simulation time 159605470 ps
CPU time 1.19 seconds
Started May 23 02:56:53 PM PDT 24
Finished May 23 02:56:56 PM PDT 24
Peak memory 200512 kb
Host smart-dee6b11b-33b5-495c-b6a5-f5c8685fc27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508801283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3508801283
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.1371790515
Short name T356
Test name
Test status
Simulation time 75360372 ps
CPU time 0.8 seconds
Started May 23 02:57:00 PM PDT 24
Finished May 23 02:57:04 PM PDT 24
Peak memory 200344 kb
Host smart-a1ce2adf-1497-4832-b8bb-d41d640f35db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371790515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1371790515
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2393593168
Short name T25
Test name
Test status
Simulation time 1894715223 ps
CPU time 8.18 seconds
Started May 23 02:56:56 PM PDT 24
Finished May 23 02:57:07 PM PDT 24
Peak memory 217504 kb
Host smart-def4cd28-6016-4ed9-bdbe-18ead188305a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393593168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2393593168
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.365920024
Short name T463
Test name
Test status
Simulation time 243905048 ps
CPU time 1.11 seconds
Started May 23 02:56:59 PM PDT 24
Finished May 23 02:57:03 PM PDT 24
Peak memory 217596 kb
Host smart-4fccfab1-ae26-4d7f-a692-8a1c897d84cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365920024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.365920024
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.974262384
Short name T376
Test name
Test status
Simulation time 113027939 ps
CPU time 0.78 seconds
Started May 23 02:56:55 PM PDT 24
Finished May 23 02:56:57 PM PDT 24
Peak memory 200356 kb
Host smart-bdbc8211-d392-4e07-8434-210cbf0eb6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974262384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.974262384
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.122997751
Short name T361
Test name
Test status
Simulation time 1857009760 ps
CPU time 7.06 seconds
Started May 23 02:56:59 PM PDT 24
Finished May 23 02:57:10 PM PDT 24
Peak memory 200676 kb
Host smart-4b2c50b1-88e7-46fd-8e98-c9a9043d5534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122997751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.122997751
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3037292313
Short name T289
Test name
Test status
Simulation time 182940478 ps
CPU time 1.18 seconds
Started May 23 02:56:53 PM PDT 24
Finished May 23 02:56:56 PM PDT 24
Peak memory 200492 kb
Host smart-b91f3087-d428-4a11-8a9f-cdcb4078512c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037292313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3037292313
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2905555290
Short name T440
Test name
Test status
Simulation time 257289921 ps
CPU time 1.57 seconds
Started May 23 02:56:55 PM PDT 24
Finished May 23 02:56:58 PM PDT 24
Peak memory 200600 kb
Host smart-ea271e1b-23cc-41e1-9906-a643cb892e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905555290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2905555290
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2038869295
Short name T483
Test name
Test status
Simulation time 3796765331 ps
CPU time 13.54 seconds
Started May 23 02:56:58 PM PDT 24
Finished May 23 02:57:15 PM PDT 24
Peak memory 200892 kb
Host smart-9e42e740-673d-4173-89d9-a5c1ea659a99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038869295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2038869295
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3969386667
Short name T358
Test name
Test status
Simulation time 133205468 ps
CPU time 1.56 seconds
Started May 23 02:56:57 PM PDT 24
Finished May 23 02:57:01 PM PDT 24
Peak memory 208692 kb
Host smart-e0bdc88e-0e90-48bf-8198-dcefef9fe36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969386667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3969386667
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2897007761
Short name T342
Test name
Test status
Simulation time 195112017 ps
CPU time 1.27 seconds
Started May 23 02:56:53 PM PDT 24
Finished May 23 02:56:56 PM PDT 24
Peak memory 200508 kb
Host smart-c9d26118-7b87-49de-9fe4-384d2ffc68ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897007761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2897007761
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1913281976
Short name T533
Test name
Test status
Simulation time 79405989 ps
CPU time 0.8 seconds
Started May 23 02:57:01 PM PDT 24
Finished May 23 02:57:04 PM PDT 24
Peak memory 200348 kb
Host smart-8de9ddd4-f657-493b-ba68-de00b1481608
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913281976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1913281976
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3905619030
Short name T493
Test name
Test status
Simulation time 1230580384 ps
CPU time 5.62 seconds
Started May 23 02:56:58 PM PDT 24
Finished May 23 02:57:07 PM PDT 24
Peak memory 221644 kb
Host smart-824bb98b-618f-4df3-9061-99f24b0ef4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905619030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3905619030
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.764132374
Short name T7
Test name
Test status
Simulation time 251122656 ps
CPU time 1.09 seconds
Started May 23 02:56:57 PM PDT 24
Finished May 23 02:57:01 PM PDT 24
Peak memory 217540 kb
Host smart-b1185c29-6511-4203-a479-6da16fe0056c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764132374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.764132374
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.17535299
Short name T133
Test name
Test status
Simulation time 100982783 ps
CPU time 0.78 seconds
Started May 23 02:56:54 PM PDT 24
Finished May 23 02:56:57 PM PDT 24
Peak memory 200284 kb
Host smart-9a0b682f-c052-4ab1-ad11-486651842920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17535299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.17535299
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2737428125
Short name T410
Test name
Test status
Simulation time 1737509608 ps
CPU time 6.62 seconds
Started May 23 02:56:57 PM PDT 24
Finished May 23 02:57:06 PM PDT 24
Peak memory 200692 kb
Host smart-76932551-7937-4a8d-9b75-45406edf21b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737428125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2737428125
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3433082487
Short name T221
Test name
Test status
Simulation time 97698127 ps
CPU time 1.05 seconds
Started May 23 02:56:58 PM PDT 24
Finished May 23 02:57:01 PM PDT 24
Peak memory 200536 kb
Host smart-6000959a-8153-46b7-9647-906f088a97c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433082487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3433082487
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2042502518
Short name T1
Test name
Test status
Simulation time 117327642 ps
CPU time 1.25 seconds
Started May 23 02:57:00 PM PDT 24
Finished May 23 02:57:05 PM PDT 24
Peak memory 200692 kb
Host smart-9c0b2ba7-f94b-4a83-b026-5adc99ae2662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042502518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2042502518
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3380296503
Short name T94
Test name
Test status
Simulation time 4319766479 ps
CPU time 15.56 seconds
Started May 23 02:56:59 PM PDT 24
Finished May 23 02:57:18 PM PDT 24
Peak memory 200876 kb
Host smart-ba097bf9-66a5-4dc2-8112-1ca5d6188450
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380296503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3380296503
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.125264549
Short name T48
Test name
Test status
Simulation time 439237294 ps
CPU time 2.46 seconds
Started May 23 02:56:57 PM PDT 24
Finished May 23 02:57:02 PM PDT 24
Peak memory 200532 kb
Host smart-ee0d212d-6a39-44ce-a323-339c590d6579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125264549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.125264549
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.4204253436
Short name T536
Test name
Test status
Simulation time 311660214 ps
CPU time 1.82 seconds
Started May 23 02:56:54 PM PDT 24
Finished May 23 02:56:57 PM PDT 24
Peak memory 200696 kb
Host smart-e22e3b58-7c67-4b49-b6d7-17b772fae133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204253436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.4204253436
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1247941413
Short name T407
Test name
Test status
Simulation time 77024072 ps
CPU time 0.75 seconds
Started May 23 02:54:45 PM PDT 24
Finished May 23 02:54:48 PM PDT 24
Peak memory 200340 kb
Host smart-f23ef95f-f986-4ad7-8bf8-d7b6826f2f62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247941413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1247941413
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.800026885
Short name T41
Test name
Test status
Simulation time 1896125011 ps
CPU time 7.09 seconds
Started May 23 02:54:47 PM PDT 24
Finished May 23 02:54:58 PM PDT 24
Peak memory 221700 kb
Host smart-929178a8-6adf-4113-acb7-df28dbe91457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800026885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.800026885
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3032125386
Short name T397
Test name
Test status
Simulation time 244443593 ps
CPU time 1.1 seconds
Started May 23 02:54:44 PM PDT 24
Finished May 23 02:54:47 PM PDT 24
Peak memory 217792 kb
Host smart-4206ca88-82e9-4c45-b99b-9fec7a4d491e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032125386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3032125386
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3947760664
Short name T314
Test name
Test status
Simulation time 179234297 ps
CPU time 0.92 seconds
Started May 23 02:54:45 PM PDT 24
Finished May 23 02:54:47 PM PDT 24
Peak memory 200364 kb
Host smart-b178d9d8-5f55-472c-a6d5-4b41c43e4a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947760664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3947760664
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2538637923
Short name T519
Test name
Test status
Simulation time 853872845 ps
CPU time 4.76 seconds
Started May 23 02:54:44 PM PDT 24
Finished May 23 02:54:50 PM PDT 24
Peak memory 200700 kb
Host smart-fe1e556a-86cf-4ddd-bc38-62dc5cd1b7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538637923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2538637923
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.4091847405
Short name T505
Test name
Test status
Simulation time 108239524 ps
CPU time 1.04 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:54:50 PM PDT 24
Peak memory 200472 kb
Host smart-6ffc1d1d-ef8b-41f0-ad5f-42a85fd78e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091847405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.4091847405
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3225648326
Short name T293
Test name
Test status
Simulation time 203234443 ps
CPU time 1.45 seconds
Started May 23 02:54:44 PM PDT 24
Finished May 23 02:54:47 PM PDT 24
Peak memory 200740 kb
Host smart-e4a52af9-ea64-43d8-96da-7de0e4b03105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225648326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3225648326
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3231196083
Short name T529
Test name
Test status
Simulation time 2645139848 ps
CPU time 12.42 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:55:02 PM PDT 24
Peak memory 209008 kb
Host smart-de822892-0afe-423e-a4b3-01991b21a705
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231196083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3231196083
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.4015944490
Short name T305
Test name
Test status
Simulation time 385199933 ps
CPU time 2.85 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:54:52 PM PDT 24
Peak memory 200384 kb
Host smart-416d4c97-5ca0-49b8-90c3-bbaf512273c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015944490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.4015944490
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2879975506
Short name T233
Test name
Test status
Simulation time 63247040 ps
CPU time 0.75 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:54:50 PM PDT 24
Peak memory 200444 kb
Host smart-446fba45-033c-41ad-a970-004fc5c2a1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879975506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2879975506
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.1362336000
Short name T510
Test name
Test status
Simulation time 75413043 ps
CPU time 0.8 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:54:50 PM PDT 24
Peak memory 200312 kb
Host smart-aed2c29f-a9af-4103-a387-efcca0431500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362336000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1362336000
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.941861620
Short name T375
Test name
Test status
Simulation time 1220742629 ps
CPU time 5.61 seconds
Started May 23 02:54:48 PM PDT 24
Finished May 23 02:54:57 PM PDT 24
Peak memory 218120 kb
Host smart-08211e01-4efb-464b-9353-d39219f8ea7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941861620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.941861620
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2493971366
Short name T419
Test name
Test status
Simulation time 243991409 ps
CPU time 1.06 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:54:50 PM PDT 24
Peak memory 217580 kb
Host smart-5af047e1-bdbf-4a5e-9f72-9c56a84e257d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493971366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2493971366
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1636393959
Short name T158
Test name
Test status
Simulation time 187529977 ps
CPU time 0.89 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:54:49 PM PDT 24
Peak memory 200272 kb
Host smart-b839be25-495e-4977-b1d8-f9042c8f5e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636393959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1636393959
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3111058996
Short name T446
Test name
Test status
Simulation time 760661598 ps
CPU time 3.99 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:54:53 PM PDT 24
Peak memory 200668 kb
Host smart-4ca69299-5df1-4e26-b592-814598e44dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111058996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3111058996
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3710000400
Short name T241
Test name
Test status
Simulation time 98651402 ps
CPU time 0.99 seconds
Started May 23 02:54:45 PM PDT 24
Finished May 23 02:54:49 PM PDT 24
Peak memory 200504 kb
Host smart-6aff7fc7-b46b-4994-a82e-47a376d9777e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710000400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3710000400
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1229653037
Short name T131
Test name
Test status
Simulation time 113029145 ps
CPU time 1.25 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:54:51 PM PDT 24
Peak memory 200580 kb
Host smart-f2c0de56-ccb4-4c1a-a755-7a3c7732ad9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229653037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1229653037
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3974163528
Short name T327
Test name
Test status
Simulation time 2187473641 ps
CPU time 8.33 seconds
Started May 23 02:54:42 PM PDT 24
Finished May 23 02:54:51 PM PDT 24
Peak memory 200816 kb
Host smart-68277211-74d1-4f34-9b42-26e51c3b69af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974163528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3974163528
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1276855164
Short name T283
Test name
Test status
Simulation time 373532359 ps
CPU time 2.35 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:54:52 PM PDT 24
Peak memory 200504 kb
Host smart-7bcd8f6f-a033-4ffc-99ee-5d373a3b5306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276855164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1276855164
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3738528702
Short name T37
Test name
Test status
Simulation time 155660250 ps
CPU time 1.14 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:54:51 PM PDT 24
Peak memory 200512 kb
Host smart-dc09f47b-9427-46cc-80d1-4d2a6a077c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738528702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3738528702
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.991060714
Short name T522
Test name
Test status
Simulation time 76611417 ps
CPU time 0.85 seconds
Started May 23 02:54:48 PM PDT 24
Finished May 23 02:54:52 PM PDT 24
Peak memory 200332 kb
Host smart-cd1d0e98-a7f4-432b-ac59-5b8e278c4cd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991060714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.991060714
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1100745808
Short name T474
Test name
Test status
Simulation time 1224996618 ps
CPU time 5.9 seconds
Started May 23 02:54:47 PM PDT 24
Finished May 23 02:54:57 PM PDT 24
Peak memory 217136 kb
Host smart-8e55e944-d2ce-46d6-a5b0-56348d9cce19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100745808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1100745808
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1794755616
Short name T408
Test name
Test status
Simulation time 244444671 ps
CPU time 1.19 seconds
Started May 23 02:54:47 PM PDT 24
Finished May 23 02:54:52 PM PDT 24
Peak memory 217652 kb
Host smart-b6a9da89-e040-48f9-85ae-02360f0fb1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794755616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1794755616
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.2615710986
Short name T337
Test name
Test status
Simulation time 119575992 ps
CPU time 0.81 seconds
Started May 23 02:54:50 PM PDT 24
Finished May 23 02:54:53 PM PDT 24
Peak memory 200356 kb
Host smart-45d31364-9bc9-46f0-8bcb-7bc2ca55f051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615710986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2615710986
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.1035817065
Short name T369
Test name
Test status
Simulation time 1364797833 ps
CPU time 5.68 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:54:55 PM PDT 24
Peak memory 200700 kb
Host smart-5f46b03d-a39d-4580-a123-20b3d65a81d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035817065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1035817065
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.942157307
Short name T181
Test name
Test status
Simulation time 145647875 ps
CPU time 1.2 seconds
Started May 23 02:54:47 PM PDT 24
Finished May 23 02:54:52 PM PDT 24
Peak memory 200528 kb
Host smart-aefd5e1a-d528-4aa7-995f-231e28681f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942157307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.942157307
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2188903902
Short name T154
Test name
Test status
Simulation time 122733561 ps
CPU time 1.23 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:54:50 PM PDT 24
Peak memory 200656 kb
Host smart-cc3e7f23-5ac6-40b6-883d-7dfa05446917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188903902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2188903902
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3981693941
Short name T96
Test name
Test status
Simulation time 7561470870 ps
CPU time 32.54 seconds
Started May 23 02:54:44 PM PDT 24
Finished May 23 02:55:18 PM PDT 24
Peak memory 200844 kb
Host smart-f6570f1d-72a6-4a60-8507-cc400813ea7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981693941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3981693941
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1036285709
Short name T296
Test name
Test status
Simulation time 133040678 ps
CPU time 1.62 seconds
Started May 23 02:54:43 PM PDT 24
Finished May 23 02:54:46 PM PDT 24
Peak memory 200500 kb
Host smart-6468db0d-3c20-4575-b23a-c0b411d8e76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036285709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1036285709
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3924097669
Short name T5
Test name
Test status
Simulation time 247824326 ps
CPU time 1.45 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:54:50 PM PDT 24
Peak memory 200700 kb
Host smart-b9008dc9-016f-4328-9005-293317df3329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924097669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3924097669
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.3003972215
Short name T367
Test name
Test status
Simulation time 68039776 ps
CPU time 0.75 seconds
Started May 23 02:55:06 PM PDT 24
Finished May 23 02:55:08 PM PDT 24
Peak memory 200264 kb
Host smart-38df7fc2-1268-4798-ab41-9abb91fd7e1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003972215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3003972215
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3556529439
Short name T31
Test name
Test status
Simulation time 2362376144 ps
CPU time 9.22 seconds
Started May 23 02:55:07 PM PDT 24
Finished May 23 02:55:18 PM PDT 24
Peak memory 218000 kb
Host smart-11d4caf9-34e1-48b0-b1ed-572e92cc124c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556529439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3556529439
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3077530590
Short name T460
Test name
Test status
Simulation time 245001018 ps
CPU time 1.03 seconds
Started May 23 02:55:08 PM PDT 24
Finished May 23 02:55:11 PM PDT 24
Peak memory 217716 kb
Host smart-4798bbd4-54eb-4b4d-8182-f1a94000d5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077530590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3077530590
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3719994380
Short name T198
Test name
Test status
Simulation time 115362975 ps
CPU time 0.81 seconds
Started May 23 02:54:46 PM PDT 24
Finished May 23 02:54:50 PM PDT 24
Peak memory 200312 kb
Host smart-38457867-fdd0-4462-a622-15b96a683f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719994380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3719994380
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3993182818
Short name T371
Test name
Test status
Simulation time 1653909435 ps
CPU time 6.4 seconds
Started May 23 02:55:09 PM PDT 24
Finished May 23 02:55:17 PM PDT 24
Peak memory 200672 kb
Host smart-b945a9ee-b38f-4e7a-9464-f95a02714cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993182818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3993182818
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1388566438
Short name T525
Test name
Test status
Simulation time 103749875 ps
CPU time 1.01 seconds
Started May 23 02:55:05 PM PDT 24
Finished May 23 02:55:08 PM PDT 24
Peak memory 200492 kb
Host smart-02dc431d-c65b-4abc-8541-576264d5ac4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388566438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1388566438
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.676731815
Short name T315
Test name
Test status
Simulation time 258820436 ps
CPU time 1.6 seconds
Started May 23 02:54:47 PM PDT 24
Finished May 23 02:54:52 PM PDT 24
Peak memory 200684 kb
Host smart-7594a84e-b6c6-454e-a382-0b4dac7458ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676731815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.676731815
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2878570102
Short name T423
Test name
Test status
Simulation time 5507953114 ps
CPU time 25.39 seconds
Started May 23 02:55:07 PM PDT 24
Finished May 23 02:55:34 PM PDT 24
Peak memory 208980 kb
Host smart-b3a716eb-658d-47ae-af53-6654eae96925
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878570102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2878570102
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3953895892
Short name T135
Test name
Test status
Simulation time 262650182 ps
CPU time 1.79 seconds
Started May 23 02:55:08 PM PDT 24
Finished May 23 02:55:12 PM PDT 24
Peak memory 200472 kb
Host smart-f38983dc-7892-4db3-bcf0-60b8aeb75601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953895892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3953895892
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2138672790
Short name T395
Test name
Test status
Simulation time 68480077 ps
CPU time 0.82 seconds
Started May 23 02:55:07 PM PDT 24
Finished May 23 02:55:10 PM PDT 24
Peak memory 200512 kb
Host smart-a30f8dd2-bf67-465f-bbc1-dc53096c0495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138672790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2138672790
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2568356580
Short name T186
Test name
Test status
Simulation time 60706781 ps
CPU time 0.79 seconds
Started May 23 02:55:09 PM PDT 24
Finished May 23 02:55:12 PM PDT 24
Peak memory 200352 kb
Host smart-d8ad7a95-8b29-4231-a0fb-5b9cbcbb86d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568356580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2568356580
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1179489109
Short name T360
Test name
Test status
Simulation time 1223368726 ps
CPU time 5.18 seconds
Started May 23 02:55:09 PM PDT 24
Finished May 23 02:55:16 PM PDT 24
Peak memory 221672 kb
Host smart-92e694d8-e42d-46d2-81fa-8e819f61662e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179489109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1179489109
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.4165737999
Short name T243
Test name
Test status
Simulation time 244525583 ps
CPU time 1.06 seconds
Started May 23 02:55:09 PM PDT 24
Finished May 23 02:55:12 PM PDT 24
Peak memory 217568 kb
Host smart-59ddbf85-e153-461d-98b7-23030ce339e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165737999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.4165737999
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1255455722
Short name T234
Test name
Test status
Simulation time 93707129 ps
CPU time 0.74 seconds
Started May 23 02:55:12 PM PDT 24
Finished May 23 02:55:15 PM PDT 24
Peak memory 200312 kb
Host smart-85c333a9-054c-4d01-99d2-efea81121c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255455722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1255455722
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.2070700340
Short name T207
Test name
Test status
Simulation time 1278034523 ps
CPU time 5.22 seconds
Started May 23 02:55:06 PM PDT 24
Finished May 23 02:55:13 PM PDT 24
Peak memory 200752 kb
Host smart-cd0dfd68-b465-4500-90c9-4bbc1c6d4559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070700340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2070700340
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2110794803
Short name T332
Test name
Test status
Simulation time 177195548 ps
CPU time 1.23 seconds
Started May 23 02:55:06 PM PDT 24
Finished May 23 02:55:08 PM PDT 24
Peak memory 200512 kb
Host smart-117aa995-e2ed-4a0a-bd84-cd194bae614d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110794803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2110794803
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.4210436513
Short name T517
Test name
Test status
Simulation time 122996917 ps
CPU time 1.23 seconds
Started May 23 02:55:11 PM PDT 24
Finished May 23 02:55:14 PM PDT 24
Peak memory 200740 kb
Host smart-08b17e97-627d-49b6-8d49-e489edde54fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210436513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.4210436513
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.2182422965
Short name T116
Test name
Test status
Simulation time 7384885060 ps
CPU time 27.17 seconds
Started May 23 02:55:08 PM PDT 24
Finished May 23 02:55:37 PM PDT 24
Peak memory 209020 kb
Host smart-f785a9aa-94e4-4d31-b152-93c96e916f8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182422965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2182422965
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.382515367
Short name T451
Test name
Test status
Simulation time 134034068 ps
CPU time 1.55 seconds
Started May 23 02:55:08 PM PDT 24
Finished May 23 02:55:12 PM PDT 24
Peak memory 208700 kb
Host smart-cd241900-b79f-4581-a4ba-c5a2175c718e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382515367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.382515367
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3609611079
Short name T279
Test name
Test status
Simulation time 72442855 ps
CPU time 0.79 seconds
Started May 23 02:55:06 PM PDT 24
Finished May 23 02:55:08 PM PDT 24
Peak memory 200504 kb
Host smart-b3f5b0c5-064f-4ab5-8e81-7c47ea26b87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609611079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3609611079
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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