Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8010

1

T2

18

T3

7

T6

27

auto[1]

10999

1

T2

83

T3

1

T6

31

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5819	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6412	1			T1	1		T2	27		T3	1
reset_info_cp[2]	3009	1			T2	16		T6	11		T7	1
reset_info_cp[4]	3837	1			T2	17		T6	12		T7	1
reset_info_cp[8]	122	1			T3	1		T6	1		T14	1
reset_info_cp[16]	109	1			T6	2		T41	1		T49	1
reset_info_cp[32]	122	1			T3	1		T8	2		T13	1
reset_info_cp[64]	92	1			T2	1		T48	1		T49	1
reset_info_cp[128]	107	1			T8	2		T13	1		T14	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3093	1			T2	18		T6	6		T13	6
reset_info_cp[1]	auto[1]	2699	1			T2	8		T6	8		T7	1
reset_info_cp[2]	auto[0]	940	1			T6	5		T13	6		T14	9
reset_info_cp[2]	auto[1]	2069	1			T2	16		T6	6		T7	1
reset_info_cp[4]	auto[0]	1358	1			T6	4		T13	4		T14	5
reset_info_cp[4]	auto[1]	2479	1			T2	17		T6	8		T7	1
reset_info_cp[8]	auto[0]	39	1			T3	1		T65	1		T95	2
reset_info_cp[8]	auto[1]	83	1			T6	1		T14	1		T47	1
reset_info_cp[16]	auto[0]	42	1			T87	1		T132	1		T37	1
reset_info_cp[16]	auto[1]	67	1			T6	2		T41	1		T49	1
reset_info_cp[32]	auto[0]	52	1			T3	1		T8	2		T48	1
reset_info_cp[32]	auto[1]	70	1			T13	1		T14	1		T41	1
reset_info_cp[64]	auto[0]	39	1			T48	1		T87	1		T95	1
reset_info_cp[64]	auto[1]	53	1			T2	1		T49	1		T87	1
reset_info_cp[128]	auto[0]	40	1			T8	2		T13	1		T14	1
reset_info_cp[128]	auto[1]	67	1			T48	1		T65	1		T87	1