Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
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T536 /workspace/coverage/default/25.rstmgr_sw_rst.4046469942 May 26 01:56:39 PM PDT 24 May 26 01:56:52 PM PDT 24 154787122 ps
T537 /workspace/coverage/default/48.rstmgr_por_stretcher.3204241455 May 26 01:57:21 PM PDT 24 May 26 01:57:23 PM PDT 24 184736396 ps
T538 /workspace/coverage/default/33.rstmgr_sw_rst.600279062 May 26 01:56:59 PM PDT 24 May 26 01:57:02 PM PDT 24 140109693 ps
T539 /workspace/coverage/default/5.rstmgr_alert_test.1056516622 May 26 01:56:14 PM PDT 24 May 26 01:56:27 PM PDT 24 61190891 ps
T540 /workspace/coverage/default/31.rstmgr_por_stretcher.3639782473 May 26 01:56:49 PM PDT 24 May 26 01:56:54 PM PDT 24 129233687 ps
T66 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3674046461 May 26 02:31:18 PM PDT 24 May 26 02:31:21 PM PDT 24 169322473 ps
T67 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2720427854 May 26 02:31:16 PM PDT 24 May 26 02:31:19 PM PDT 24 140943417 ps
T68 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.4069315634 May 26 02:31:16 PM PDT 24 May 26 02:31:19 PM PDT 24 71944053 ps
T69 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.131657662 May 26 02:31:17 PM PDT 24 May 26 02:31:20 PM PDT 24 212161458 ps
T70 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3324044300 May 26 02:31:04 PM PDT 24 May 26 02:31:08 PM PDT 24 184864837 ps
T103 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.4019905059 May 26 02:30:56 PM PDT 24 May 26 02:30:57 PM PDT 24 60581458 ps
T71 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2976140202 May 26 02:31:24 PM PDT 24 May 26 02:31:28 PM PDT 24 881870785 ps
T88 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1241905047 May 26 02:31:06 PM PDT 24 May 26 02:31:07 PM PDT 24 117323613 ps
T72 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3401807460 May 26 02:31:14 PM PDT 24 May 26 02:31:19 PM PDT 24 944209714 ps
T89 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3838263971 May 26 02:31:15 PM PDT 24 May 26 02:31:17 PM PDT 24 163321618 ps
T93 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2647722362 May 26 02:31:19 PM PDT 24 May 26 02:31:21 PM PDT 24 124080522 ps
T90 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1886715096 May 26 02:31:05 PM PDT 24 May 26 02:31:07 PM PDT 24 108654523 ps
T91 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3200497613 May 26 02:31:24 PM PDT 24 May 26 02:31:26 PM PDT 24 133954929 ps
T104 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.292740005 May 26 02:31:17 PM PDT 24 May 26 02:31:20 PM PDT 24 192610497 ps
T111 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2198460958 May 26 02:31:26 PM PDT 24 May 26 02:31:29 PM PDT 24 513249845 ps
T92 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2445495624 May 26 02:31:25 PM PDT 24 May 26 02:31:27 PM PDT 24 122871358 ps
T541 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.28277291 May 26 02:30:57 PM PDT 24 May 26 02:30:59 PM PDT 24 106413897 ps
T105 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2390954960 May 26 02:31:23 PM PDT 24 May 26 02:31:25 PM PDT 24 125700682 ps
T94 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1474566612 May 26 02:30:58 PM PDT 24 May 26 02:31:00 PM PDT 24 198196209 ps
T106 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2665814506 May 26 02:31:14 PM PDT 24 May 26 02:31:16 PM PDT 24 79826475 ps
T107 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1094247207 May 26 02:31:06 PM PDT 24 May 26 02:31:08 PM PDT 24 65984589 ps
T114 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.729890452 May 26 02:31:19 PM PDT 24 May 26 02:31:23 PM PDT 24 464579365 ps
T112 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.4068401503 May 26 02:31:15 PM PDT 24 May 26 02:31:19 PM PDT 24 204907479 ps
T119 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3796061641 May 26 02:30:58 PM PDT 24 May 26 02:31:02 PM PDT 24 888998393 ps
T117 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2862040889 May 26 02:30:57 PM PDT 24 May 26 02:31:02 PM PDT 24 1025204185 ps
T121 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3127557530 May 26 02:31:04 PM PDT 24 May 26 02:31:07 PM PDT 24 489995417 ps
T108 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1476194936 May 26 02:31:07 PM PDT 24 May 26 02:31:09 PM PDT 24 142540235 ps
T113 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3859113527 May 26 02:30:58 PM PDT 24 May 26 02:31:01 PM PDT 24 139527833 ps
T542 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2944994749 May 26 02:30:58 PM PDT 24 May 26 02:31:01 PM PDT 24 279941688 ps
T543 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1212255551 May 26 02:31:23 PM PDT 24 May 26 02:31:25 PM PDT 24 99898053 ps
T544 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.873321004 May 26 02:30:58 PM PDT 24 May 26 02:31:02 PM PDT 24 265706350 ps
T545 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2566710163 May 26 02:31:07 PM PDT 24 May 26 02:31:08 PM PDT 24 75038996 ps
T115 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1377112510 May 26 02:31:25 PM PDT 24 May 26 02:31:29 PM PDT 24 476319961 ps
T122 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2402369232 May 26 02:31:15 PM PDT 24 May 26 02:31:18 PM PDT 24 148319163 ps
T546 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3879045079 May 26 02:30:59 PM PDT 24 May 26 02:31:03 PM PDT 24 863779750 ps
T118 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1181692725 May 26 02:30:49 PM PDT 24 May 26 02:30:54 PM PDT 24 1101670051 ps
T109 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3308355081 May 26 02:30:56 PM PDT 24 May 26 02:30:58 PM PDT 24 60109018 ps
T547 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.928564430 May 26 02:31:07 PM PDT 24 May 26 02:31:09 PM PDT 24 203404243 ps
T548 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.684055585 May 26 02:31:16 PM PDT 24 May 26 02:31:21 PM PDT 24 797629133 ps
T549 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4079080563 May 26 02:31:16 PM PDT 24 May 26 02:31:19 PM PDT 24 121874554 ps
T550 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.574025792 May 26 02:30:56 PM PDT 24 May 26 02:30:59 PM PDT 24 353498406 ps
T551 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2350159123 May 26 02:31:06 PM PDT 24 May 26 02:31:10 PM PDT 24 800453596 ps
T552 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.107803234 May 26 02:30:49 PM PDT 24 May 26 02:30:53 PM PDT 24 193291684 ps
T110 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.242287801 May 26 02:30:56 PM PDT 24 May 26 02:30:58 PM PDT 24 111022382 ps
T553 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2326919293 May 26 02:31:25 PM PDT 24 May 26 02:31:27 PM PDT 24 66189469 ps
T554 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1961498588 May 26 02:31:04 PM PDT 24 May 26 02:31:05 PM PDT 24 60438109 ps
T555 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3375176591 May 26 02:30:57 PM PDT 24 May 26 02:31:00 PM PDT 24 445501960 ps
T556 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3099672722 May 26 02:31:16 PM PDT 24 May 26 02:31:18 PM PDT 24 121905855 ps
T557 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2782780954 May 26 02:31:14 PM PDT 24 May 26 02:31:17 PM PDT 24 88821713 ps
T558 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.834691650 May 26 02:31:25 PM PDT 24 May 26 02:31:28 PM PDT 24 131914054 ps
T559 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2786873164 May 26 02:31:16 PM PDT 24 May 26 02:31:18 PM PDT 24 66576318 ps
T560 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1587614325 May 26 02:31:06 PM PDT 24 May 26 02:31:08 PM PDT 24 153314720 ps
T561 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2240803366 May 26 02:30:58 PM PDT 24 May 26 02:31:00 PM PDT 24 178362497 ps
T562 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3659680375 May 26 02:31:05 PM PDT 24 May 26 02:31:07 PM PDT 24 154741023 ps
T120 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3050440092 May 26 02:31:22 PM PDT 24 May 26 02:31:25 PM PDT 24 885627238 ps
T563 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.254037954 May 26 02:31:24 PM PDT 24 May 26 02:31:26 PM PDT 24 138947378 ps
T564 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1531615440 May 26 02:30:58 PM PDT 24 May 26 02:31:00 PM PDT 24 100657437 ps
T565 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3020397672 May 26 02:30:55 PM PDT 24 May 26 02:31:02 PM PDT 24 480533040 ps
T566 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1321913691 May 26 02:31:10 PM PDT 24 May 26 02:31:13 PM PDT 24 408157039 ps
T567 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2482052973 May 26 02:31:15 PM PDT 24 May 26 02:31:20 PM PDT 24 632954787 ps
T568 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4016628961 May 26 02:31:04 PM PDT 24 May 26 02:31:07 PM PDT 24 240577117 ps
T569 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.317740669 May 26 02:31:17 PM PDT 24 May 26 02:31:19 PM PDT 24 76040267 ps
T570 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2100797430 May 26 02:31:05 PM PDT 24 May 26 02:31:09 PM PDT 24 874876901 ps
T571 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.323112873 May 26 02:31:16 PM PDT 24 May 26 02:31:20 PM PDT 24 489706530 ps
T572 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1510693163 May 26 02:31:07 PM PDT 24 May 26 02:31:09 PM PDT 24 120027985 ps
T573 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3005084997 May 26 02:31:15 PM PDT 24 May 26 02:31:18 PM PDT 24 363450815 ps
T116 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3593361500 May 26 02:31:14 PM PDT 24 May 26 02:31:19 PM PDT 24 929834847 ps
T574 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3429332985 May 26 02:31:06 PM PDT 24 May 26 02:31:10 PM PDT 24 481490028 ps
T575 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2884307919 May 26 02:30:57 PM PDT 24 May 26 02:31:01 PM PDT 24 414834303 ps
T576 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3112998037 May 26 02:30:58 PM PDT 24 May 26 02:31:05 PM PDT 24 483164014 ps
T577 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2951153587 May 26 02:31:25 PM PDT 24 May 26 02:31:28 PM PDT 24 170703092 ps
T578 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1040091288 May 26 02:31:20 PM PDT 24 May 26 02:31:23 PM PDT 24 425904742 ps
T579 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1229363978 May 26 02:31:05 PM PDT 24 May 26 02:31:07 PM PDT 24 138825933 ps
T580 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3543950765 May 26 02:31:26 PM PDT 24 May 26 02:31:28 PM PDT 24 61995080 ps
T581 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3486761134 May 26 02:30:58 PM PDT 24 May 26 02:31:02 PM PDT 24 420454466 ps
T582 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3209932026 May 26 02:31:23 PM PDT 24 May 26 02:31:24 PM PDT 24 83034319 ps
T583 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3075698890 May 26 02:31:14 PM PDT 24 May 26 02:31:18 PM PDT 24 789128497 ps
T584 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.4181793543 May 26 02:30:57 PM PDT 24 May 26 02:30:58 PM PDT 24 61369291 ps
T585 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.235061788 May 26 02:30:58 PM PDT 24 May 26 02:31:00 PM PDT 24 129237387 ps
T586 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2593485482 May 26 02:31:14 PM PDT 24 May 26 02:31:16 PM PDT 24 125940003 ps
T587 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.821211509 May 26 02:31:16 PM PDT 24 May 26 02:31:19 PM PDT 24 271481623 ps
T588 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1392110475 May 26 02:31:18 PM PDT 24 May 26 02:31:28 PM PDT 24 1984301685 ps
T589 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.160871940 May 26 02:31:16 PM PDT 24 May 26 02:31:19 PM PDT 24 130653470 ps
T590 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.187886595 May 26 02:31:04 PM PDT 24 May 26 02:31:06 PM PDT 24 206108181 ps
T591 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2368990996 May 26 02:31:23 PM PDT 24 May 26 02:31:27 PM PDT 24 792159416 ps
T592 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2564583628 May 26 02:31:14 PM PDT 24 May 26 02:31:16 PM PDT 24 135323337 ps
T593 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3892909616 May 26 02:30:58 PM PDT 24 May 26 02:31:00 PM PDT 24 92442358 ps
T594 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.539374499 May 26 02:31:16 PM PDT 24 May 26 02:31:18 PM PDT 24 89165789 ps
T595 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1569693777 May 26 02:31:17 PM PDT 24 May 26 02:31:21 PM PDT 24 889875635 ps
T596 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1533147745 May 26 02:31:07 PM PDT 24 May 26 02:31:09 PM PDT 24 86622156 ps
T597 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1227866003 May 26 02:31:03 PM PDT 24 May 26 02:31:04 PM PDT 24 55773221 ps
T598 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.989520174 May 26 02:31:26 PM PDT 24 May 26 02:31:29 PM PDT 24 123622986 ps
T599 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2076125155 May 26 02:31:16 PM PDT 24 May 26 02:31:20 PM PDT 24 402082446 ps
T600 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.938506930 May 26 02:31:14 PM PDT 24 May 26 02:31:16 PM PDT 24 75540120 ps
T601 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2573004452 May 26 02:30:56 PM PDT 24 May 26 02:30:58 PM PDT 24 84362963 ps
T602 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2649306983 May 26 02:31:25 PM PDT 24 May 26 02:31:28 PM PDT 24 493367817 ps
T603 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3138439970 May 26 02:31:06 PM PDT 24 May 26 02:31:08 PM PDT 24 114791644 ps
T604 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.72213446 May 26 02:30:57 PM PDT 24 May 26 02:30:58 PM PDT 24 66528893 ps
T605 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1423041028 May 26 02:30:58 PM PDT 24 May 26 02:31:00 PM PDT 24 196907827 ps
T96 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.4115710184 May 26 02:31:26 PM PDT 24 May 26 02:31:28 PM PDT 24 59665527 ps
T606 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3021408247 May 26 02:31:24 PM PDT 24 May 26 02:31:26 PM PDT 24 147277547 ps
T607 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1411235483 May 26 02:31:03 PM PDT 24 May 26 02:31:06 PM PDT 24 364321772 ps
T608 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.78217414 May 26 02:31:16 PM PDT 24 May 26 02:31:21 PM PDT 24 797165121 ps
T609 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.71329004 May 26 02:31:04 PM PDT 24 May 26 02:31:07 PM PDT 24 116159970 ps
T610 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.805665658 May 26 02:30:56 PM PDT 24 May 26 02:30:58 PM PDT 24 216534617 ps
T611 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3389373388 May 26 02:31:16 PM PDT 24 May 26 02:31:19 PM PDT 24 134488852 ps
T612 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2982851404 May 26 02:31:14 PM PDT 24 May 26 02:31:17 PM PDT 24 183332919 ps
T613 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1713386047 May 26 02:31:25 PM PDT 24 May 26 02:31:30 PM PDT 24 647624115 ps
T614 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.362481965 May 26 02:31:19 PM PDT 24 May 26 02:31:21 PM PDT 24 69079749 ps
T615 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1815615505 May 26 02:31:15 PM PDT 24 May 26 02:31:18 PM PDT 24 62116313 ps
T616 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2335629578 May 26 02:30:58 PM PDT 24 May 26 02:31:05 PM PDT 24 483865075 ps
T617 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1444682904 May 26 02:31:27 PM PDT 24 May 26 02:31:29 PM PDT 24 80815368 ps
T618 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2887085099 May 26 02:31:14 PM PDT 24 May 26 02:31:17 PM PDT 24 146774646 ps
T619 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3817976746 May 26 02:31:04 PM PDT 24 May 26 02:31:06 PM PDT 24 110022893 ps
T620 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1595358922 May 26 02:31:25 PM PDT 24 May 26 02:31:28 PM PDT 24 227190946 ps

Test location /workspace/coverage/default/18.rstmgr_smoke.192245682
Short name T7
Test name
Test status
Simulation time 125068929 ps
CPU time 1.28 seconds
Started May 26 01:56:26 PM PDT 24
Finished May 26 01:56:45 PM PDT 24
Peak memory 200664 kb
Host smart-22e69b8e-f727-4fcb-aed9-54235d272858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192245682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.192245682
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.767746547
Short name T48
Test name
Test status
Simulation time 5685449922 ps
CPU time 26.62 seconds
Started May 26 01:56:34 PM PDT 24
Finished May 26 01:57:14 PM PDT 24
Peak memory 208980 kb
Host smart-640b3c27-1c9b-4736-82ff-042928cb30fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767746547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.767746547
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2976140202
Short name T71
Test name
Test status
Simulation time 881870785 ps
CPU time 3.35 seconds
Started May 26 02:31:24 PM PDT 24
Finished May 26 02:31:28 PM PDT 24
Peak memory 200616 kb
Host smart-e4617150-d435-471f-bd60-428f18acbeeb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976140202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2976140202
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3208547823
Short name T86
Test name
Test status
Simulation time 443702105 ps
CPU time 2.36 seconds
Started May 26 01:56:33 PM PDT 24
Finished May 26 01:56:49 PM PDT 24
Peak memory 200492 kb
Host smart-52eef1fa-4485-45c9-a318-3fe8933707cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208547823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3208547823
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.1592010646
Short name T39
Test name
Test status
Simulation time 17765799309 ps
CPU time 26.56 seconds
Started May 26 01:56:09 PM PDT 24
Finished May 26 01:56:39 PM PDT 24
Peak memory 217756 kb
Host smart-af72507b-3589-4fb6-a66a-a4a866717e81
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592010646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1592010646
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2982673096
Short name T41
Test name
Test status
Simulation time 2361886610 ps
CPU time 7.78 seconds
Started May 26 01:57:29 PM PDT 24
Finished May 26 01:57:39 PM PDT 24
Peak memory 217740 kb
Host smart-2c80aead-40ac-4397-bd7f-447b6274cc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982673096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2982673096
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3324044300
Short name T70
Test name
Test status
Simulation time 184864837 ps
CPU time 2.53 seconds
Started May 26 02:31:04 PM PDT 24
Finished May 26 02:31:08 PM PDT 24
Peak memory 208832 kb
Host smart-885eddaa-ad55-4cb4-ae03-ff0cfebc4c9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324044300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3324044300
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2040741986
Short name T43
Test name
Test status
Simulation time 1236989964 ps
CPU time 6.29 seconds
Started May 26 01:57:29 PM PDT 24
Finished May 26 01:57:38 PM PDT 24
Peak memory 218140 kb
Host smart-014c8189-57d0-476f-bac8-00c9523003dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040741986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2040741986
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1520449618
Short name T63
Test name
Test status
Simulation time 110415988 ps
CPU time 1.02 seconds
Started May 26 01:57:24 PM PDT 24
Finished May 26 01:57:26 PM PDT 24
Peak memory 200504 kb
Host smart-1202053d-20bf-4efe-b144-b4431ecb37df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520449618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1520449618
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1534130391
Short name T132
Test name
Test status
Simulation time 107954662 ps
CPU time 1 seconds
Started May 26 01:57:23 PM PDT 24
Finished May 26 01:57:26 PM PDT 24
Peak memory 200392 kb
Host smart-cdfcfaf8-ca66-4ae4-9335-dfda4d00d57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534130391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1534130391
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.978934067
Short name T145
Test name
Test status
Simulation time 63365705 ps
CPU time 0.75 seconds
Started May 26 01:56:21 PM PDT 24
Finished May 26 01:56:39 PM PDT 24
Peak memory 200348 kb
Host smart-8bf7ea49-3a9b-4fb6-9bdb-90e6da703e5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978934067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.978934067
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1000554025
Short name T32
Test name
Test status
Simulation time 2349587730 ps
CPU time 8.03 seconds
Started May 26 01:56:24 PM PDT 24
Finished May 26 01:56:50 PM PDT 24
Peak memory 218272 kb
Host smart-da3aa4ce-0d6b-4599-9322-03e4133b2453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000554025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1000554025
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_reset.16624091
Short name T123
Test name
Test status
Simulation time 1842300044 ps
CPU time 6.79 seconds
Started May 26 01:55:48 PM PDT 24
Finished May 26 01:55:56 PM PDT 24
Peak memory 200700 kb
Host smart-e1f1f2f6-1de9-410f-9df0-29377939670d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16624091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.16624091
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2799563794
Short name T95
Test name
Test status
Simulation time 5354200503 ps
CPU time 27.67 seconds
Started May 26 01:56:17 PM PDT 24
Finished May 26 01:57:01 PM PDT 24
Peak memory 200796 kb
Host smart-1f4a4058-caf5-40b6-8d95-d3d7b9816bf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799563794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2799563794
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.4068401503
Short name T112
Test name
Test status
Simulation time 204907479 ps
CPU time 3.1 seconds
Started May 26 02:31:15 PM PDT 24
Finished May 26 02:31:19 PM PDT 24
Peak memory 216776 kb
Host smart-a1d86d13-efb8-46bf-8ad5-a52b24cc5017
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068401503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.4068401503
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3401807460
Short name T72
Test name
Test status
Simulation time 944209714 ps
CPU time 3.1 seconds
Started May 26 02:31:14 PM PDT 24
Finished May 26 02:31:19 PM PDT 24
Peak memory 200536 kb
Host smart-a566a550-0b47-468b-8a9d-ff1a063ca374
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401807460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3401807460
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.4019905059
Short name T103
Test name
Test status
Simulation time 60581458 ps
CPU time 0.75 seconds
Started May 26 02:30:56 PM PDT 24
Finished May 26 02:30:57 PM PDT 24
Peak memory 200352 kb
Host smart-2c395b0d-ad96-453a-975e-89c0a367b44e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019905059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.4019905059
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2659214390
Short name T15
Test name
Test status
Simulation time 119862434 ps
CPU time 0.82 seconds
Started May 26 01:56:26 PM PDT 24
Finished May 26 01:56:44 PM PDT 24
Peak memory 199804 kb
Host smart-14107e94-e624-45f5-b5db-dc85acdbdbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659214390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2659214390
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1181692725
Short name T118
Test name
Test status
Simulation time 1101670051 ps
CPU time 3.25 seconds
Started May 26 02:30:49 PM PDT 24
Finished May 26 02:30:54 PM PDT 24
Peak memory 200572 kb
Host smart-26fc576e-aa41-4962-b892-eece98d63ca6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181692725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1181692725
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.574025792
Short name T550
Test name
Test status
Simulation time 353498406 ps
CPU time 2.33 seconds
Started May 26 02:30:56 PM PDT 24
Finished May 26 02:30:59 PM PDT 24
Peak memory 200520 kb
Host smart-2ce04af9-a199-4b59-87ed-0c9593c8e735
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574025792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.574025792
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.873321004
Short name T544
Test name
Test status
Simulation time 265706350 ps
CPU time 3.21 seconds
Started May 26 02:30:58 PM PDT 24
Finished May 26 02:31:02 PM PDT 24
Peak memory 200516 kb
Host smart-c47b9367-7099-4c7c-baf9-3c428bdd93d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873321004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.873321004
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1531615440
Short name T564
Test name
Test status
Simulation time 100657437 ps
CPU time 0.89 seconds
Started May 26 02:30:58 PM PDT 24
Finished May 26 02:31:00 PM PDT 24
Peak memory 200352 kb
Host smart-f2f4378f-56dc-4cd8-ba5e-ec024a167c7b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531615440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
531615440
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2240803366
Short name T561
Test name
Test status
Simulation time 178362497 ps
CPU time 1.24 seconds
Started May 26 02:30:58 PM PDT 24
Finished May 26 02:31:00 PM PDT 24
Peak memory 208876 kb
Host smart-dd0ed548-a69d-4497-a75c-d95e06c710b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240803366 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2240803366
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.805665658
Short name T610
Test name
Test status
Simulation time 216534617 ps
CPU time 1.42 seconds
Started May 26 02:30:56 PM PDT 24
Finished May 26 02:30:58 PM PDT 24
Peak memory 200712 kb
Host smart-0e694840-6c50-4cbb-b752-8f7d9c71cf1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805665658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sam
e_csr_outstanding.805665658
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.107803234
Short name T552
Test name
Test status
Simulation time 193291684 ps
CPU time 2.78 seconds
Started May 26 02:30:49 PM PDT 24
Finished May 26 02:30:53 PM PDT 24
Peak memory 208824 kb
Host smart-42fa3415-2cbd-4156-b9ee-04b28a9e0392
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107803234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.107803234
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3486761134
Short name T581
Test name
Test status
Simulation time 420454466 ps
CPU time 2.63 seconds
Started May 26 02:30:58 PM PDT 24
Finished May 26 02:31:02 PM PDT 24
Peak memory 200564 kb
Host smart-93314c1b-bf35-4a25-9a1d-d02ab8f0cf66
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486761134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
486761134
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3112998037
Short name T576
Test name
Test status
Simulation time 483164014 ps
CPU time 5.7 seconds
Started May 26 02:30:58 PM PDT 24
Finished May 26 02:31:05 PM PDT 24
Peak memory 200532 kb
Host smart-dc75c5a5-577b-4396-803c-caf53c67ef82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112998037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
112998037
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.235061788
Short name T585
Test name
Test status
Simulation time 129237387 ps
CPU time 0.91 seconds
Started May 26 02:30:58 PM PDT 24
Finished May 26 02:31:00 PM PDT 24
Peak memory 200364 kb
Host smart-118b6370-a3d6-45bc-ac05-1d2618b83863
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235061788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.235061788
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1474566612
Short name T94
Test name
Test status
Simulation time 198196209 ps
CPU time 1.27 seconds
Started May 26 02:30:58 PM PDT 24
Finished May 26 02:31:00 PM PDT 24
Peak memory 208660 kb
Host smart-2bc9015b-2f04-4320-b162-2326e639bda3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474566612 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1474566612
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.72213446
Short name T604
Test name
Test status
Simulation time 66528893 ps
CPU time 0.81 seconds
Started May 26 02:30:57 PM PDT 24
Finished May 26 02:30:58 PM PDT 24
Peak memory 200348 kb
Host smart-1a91f52f-6642-4f36-bc3f-aaf7418c3f59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72213446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.72213446
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.242287801
Short name T110
Test name
Test status
Simulation time 111022382 ps
CPU time 1.24 seconds
Started May 26 02:30:56 PM PDT 24
Finished May 26 02:30:58 PM PDT 24
Peak memory 200604 kb
Host smart-f5ffca33-2063-406d-ab8e-4a84731e40c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242287801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.242287801
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2944994749
Short name T542
Test name
Test status
Simulation time 279941688 ps
CPU time 2.44 seconds
Started May 26 02:30:58 PM PDT 24
Finished May 26 02:31:01 PM PDT 24
Peak memory 208832 kb
Host smart-c107f1e7-edea-46c7-8daf-268ee6484259
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944994749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2944994749
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3796061641
Short name T119
Test name
Test status
Simulation time 888998393 ps
CPU time 3.31 seconds
Started May 26 02:30:58 PM PDT 24
Finished May 26 02:31:02 PM PDT 24
Peak memory 200644 kb
Host smart-da12230a-f3aa-4d91-9ab7-76412ddb0366
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796061641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3796061641
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3674046461
Short name T66
Test name
Test status
Simulation time 169322473 ps
CPU time 1.56 seconds
Started May 26 02:31:18 PM PDT 24
Finished May 26 02:31:21 PM PDT 24
Peak memory 208856 kb
Host smart-7f77123c-7fb8-4802-821c-13817b27b649
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674046461 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3674046461
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.938506930
Short name T600
Test name
Test status
Simulation time 75540120 ps
CPU time 0.78 seconds
Started May 26 02:31:14 PM PDT 24
Finished May 26 02:31:16 PM PDT 24
Peak memory 200360 kb
Host smart-d0ac9e05-ec84-4399-bce3-28de2faec1a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938506930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.938506930
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2782780954
Short name T557
Test name
Test status
Simulation time 88821713 ps
CPU time 1.02 seconds
Started May 26 02:31:14 PM PDT 24
Finished May 26 02:31:17 PM PDT 24
Peak memory 200404 kb
Host smart-00c083d2-ca85-4284-b8c8-d70aa342972a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782780954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.2782780954
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2076125155
Short name T599
Test name
Test status
Simulation time 402082446 ps
CPU time 2.78 seconds
Started May 26 02:31:16 PM PDT 24
Finished May 26 02:31:20 PM PDT 24
Peak memory 208864 kb
Host smart-c6844249-af13-4a03-9bd4-fdcac47ae240
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076125155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2076125155
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2647722362
Short name T93
Test name
Test status
Simulation time 124080522 ps
CPU time 1.26 seconds
Started May 26 02:31:19 PM PDT 24
Finished May 26 02:31:21 PM PDT 24
Peak memory 208664 kb
Host smart-16ae4047-13ba-404b-9233-7a1852660ec7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647722362 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2647722362
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.362481965
Short name T614
Test name
Test status
Simulation time 69079749 ps
CPU time 0.84 seconds
Started May 26 02:31:19 PM PDT 24
Finished May 26 02:31:21 PM PDT 24
Peak memory 200240 kb
Host smart-dfa2b201-a63a-493f-b022-0a97998a3520
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362481965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.362481965
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2564583628
Short name T592
Test name
Test status
Simulation time 135323337 ps
CPU time 1.18 seconds
Started May 26 02:31:14 PM PDT 24
Finished May 26 02:31:16 PM PDT 24
Peak memory 200496 kb
Host smart-b452ebfc-1e7b-4ac2-9ba5-a117c82da9cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564583628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2564583628
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.729890452
Short name T114
Test name
Test status
Simulation time 464579365 ps
CPU time 3.52 seconds
Started May 26 02:31:19 PM PDT 24
Finished May 26 02:31:23 PM PDT 24
Peak memory 200576 kb
Host smart-56a2ff53-afbf-497c-b993-8cfbeda18fa5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729890452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.729890452
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.684055585
Short name T548
Test name
Test status
Simulation time 797629133 ps
CPU time 2.85 seconds
Started May 26 02:31:16 PM PDT 24
Finished May 26 02:31:21 PM PDT 24
Peak memory 200516 kb
Host smart-09f5a624-a582-4200-a647-fd469bd05a59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684055585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.684055585
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3099672722
Short name T556
Test name
Test status
Simulation time 121905855 ps
CPU time 1.01 seconds
Started May 26 02:31:16 PM PDT 24
Finished May 26 02:31:18 PM PDT 24
Peak memory 200480 kb
Host smart-04a3c91f-4fcb-49ab-8d40-e56f86453c91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099672722 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3099672722
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1815615505
Short name T615
Test name
Test status
Simulation time 62116313 ps
CPU time 0.8 seconds
Started May 26 02:31:15 PM PDT 24
Finished May 26 02:31:18 PM PDT 24
Peak memory 200560 kb
Host smart-7c2e2c06-53e8-4edd-85b9-fd3f644202ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815615505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1815615505
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.160871940
Short name T589
Test name
Test status
Simulation time 130653470 ps
CPU time 1.43 seconds
Started May 26 02:31:16 PM PDT 24
Finished May 26 02:31:19 PM PDT 24
Peak memory 200588 kb
Host smart-0604e739-73a8-4e9b-968d-0670fec574bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160871940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.160871940
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2402369232
Short name T122
Test name
Test status
Simulation time 148319163 ps
CPU time 1.99 seconds
Started May 26 02:31:15 PM PDT 24
Finished May 26 02:31:18 PM PDT 24
Peak memory 208816 kb
Host smart-8bb36b83-2a61-42e5-a4cc-00a56c17565f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402369232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2402369232
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1040091288
Short name T578
Test name
Test status
Simulation time 425904742 ps
CPU time 1.77 seconds
Started May 26 02:31:20 PM PDT 24
Finished May 26 02:31:23 PM PDT 24
Peak memory 200668 kb
Host smart-b505ff5a-4e59-4c81-be04-045afba3f460
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040091288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1040091288
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2720427854
Short name T67
Test name
Test status
Simulation time 140943417 ps
CPU time 1.07 seconds
Started May 26 02:31:16 PM PDT 24
Finished May 26 02:31:19 PM PDT 24
Peak memory 200464 kb
Host smart-10290c8b-bd1a-4cda-8341-7f45a8b42ddc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720427854 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2720427854
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2665814506
Short name T106
Test name
Test status
Simulation time 79826475 ps
CPU time 0.81 seconds
Started May 26 02:31:14 PM PDT 24
Finished May 26 02:31:16 PM PDT 24
Peak memory 200376 kb
Host smart-37d45f04-0e68-4fd9-8322-4b5dcf91dea9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665814506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2665814506
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2887085099
Short name T618
Test name
Test status
Simulation time 146774646 ps
CPU time 1.12 seconds
Started May 26 02:31:14 PM PDT 24
Finished May 26 02:31:17 PM PDT 24
Peak memory 200448 kb
Host smart-dc244f31-9f33-4a72-819a-583b1046cc19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887085099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2887085099
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2482052973
Short name T567
Test name
Test status
Simulation time 632954787 ps
CPU time 3.76 seconds
Started May 26 02:31:15 PM PDT 24
Finished May 26 02:31:20 PM PDT 24
Peak memory 208796 kb
Host smart-332777de-042e-45ee-b231-2d896ca709e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482052973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2482052973
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.323112873
Short name T571
Test name
Test status
Simulation time 489706530 ps
CPU time 2.23 seconds
Started May 26 02:31:16 PM PDT 24
Finished May 26 02:31:20 PM PDT 24
Peak memory 200624 kb
Host smart-d4d9780e-98a6-4d74-bfa4-dfa96ec3b80c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323112873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.323112873
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3389373388
Short name T611
Test name
Test status
Simulation time 134488852 ps
CPU time 1.59 seconds
Started May 26 02:31:16 PM PDT 24
Finished May 26 02:31:19 PM PDT 24
Peak memory 208876 kb
Host smart-4bdb1f24-4f49-4ac7-8a5a-8b53bf8f0fcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389373388 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3389373388
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.4069315634
Short name T68
Test name
Test status
Simulation time 71944053 ps
CPU time 0.78 seconds
Started May 26 02:31:16 PM PDT 24
Finished May 26 02:31:19 PM PDT 24
Peak memory 200312 kb
Host smart-7626ccc5-7ac3-4a43-ac1d-533887b34b7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069315634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.4069315634
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2593485482
Short name T586
Test name
Test status
Simulation time 125940003 ps
CPU time 1.05 seconds
Started May 26 02:31:14 PM PDT 24
Finished May 26 02:31:16 PM PDT 24
Peak memory 200412 kb
Host smart-9dda9b82-6e40-46c3-ae37-d99c517cbd1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593485482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2593485482
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3050440092
Short name T120
Test name
Test status
Simulation time 885627238 ps
CPU time 3.3 seconds
Started May 26 02:31:22 PM PDT 24
Finished May 26 02:31:25 PM PDT 24
Peak memory 200656 kb
Host smart-a9c4fd2c-d1c9-45ec-89c4-2da59251ee1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050440092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3050440092
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2445495624
Short name T92
Test name
Test status
Simulation time 122871358 ps
CPU time 1 seconds
Started May 26 02:31:25 PM PDT 24
Finished May 26 02:31:27 PM PDT 24
Peak memory 200492 kb
Host smart-cd1f0b5d-c954-4216-b635-c78e0975697c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445495624 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2445495624
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2786873164
Short name T559
Test name
Test status
Simulation time 66576318 ps
CPU time 0.94 seconds
Started May 26 02:31:16 PM PDT 24
Finished May 26 02:31:18 PM PDT 24
Peak memory 200292 kb
Host smart-d17677de-b742-4dc5-8b40-bdb9141c730b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786873164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2786873164
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.821211509
Short name T587
Test name
Test status
Simulation time 271481623 ps
CPU time 1.58 seconds
Started May 26 02:31:16 PM PDT 24
Finished May 26 02:31:19 PM PDT 24
Peak memory 200564 kb
Host smart-91631241-babf-46e9-844c-7128b50d04be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821211509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.821211509
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4079080563
Short name T549
Test name
Test status
Simulation time 121874554 ps
CPU time 1.46 seconds
Started May 26 02:31:16 PM PDT 24
Finished May 26 02:31:19 PM PDT 24
Peak memory 200636 kb
Host smart-e020ee03-52a6-4830-b291-dfd8273acc48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079080563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.4079080563
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.78217414
Short name T608
Test name
Test status
Simulation time 797165121 ps
CPU time 2.88 seconds
Started May 26 02:31:16 PM PDT 24
Finished May 26 02:31:21 PM PDT 24
Peak memory 200704 kb
Host smart-1e92084d-f9d8-4fc5-92a2-60efff84527e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78217414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.78217414
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.834691650
Short name T558
Test name
Test status
Simulation time 131914054 ps
CPU time 1.07 seconds
Started May 26 02:31:25 PM PDT 24
Finished May 26 02:31:28 PM PDT 24
Peak memory 200496 kb
Host smart-2ca2cfdc-3dee-4e4c-bed6-1aa1b2aa3819
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834691650 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.834691650
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3543950765
Short name T580
Test name
Test status
Simulation time 61995080 ps
CPU time 0.83 seconds
Started May 26 02:31:26 PM PDT 24
Finished May 26 02:31:28 PM PDT 24
Peak memory 200364 kb
Host smart-a67f362f-80d5-41ae-9ef6-bafe6e19521a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543950765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3543950765
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3021408247
Short name T606
Test name
Test status
Simulation time 147277547 ps
CPU time 1.15 seconds
Started May 26 02:31:24 PM PDT 24
Finished May 26 02:31:26 PM PDT 24
Peak memory 200412 kb
Host smart-657befc9-2cb2-488f-bfd2-ad21ecdf02d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021408247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3021408247
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1713386047
Short name T613
Test name
Test status
Simulation time 647624115 ps
CPU time 4 seconds
Started May 26 02:31:25 PM PDT 24
Finished May 26 02:31:30 PM PDT 24
Peak memory 216884 kb
Host smart-6ede421f-edec-4c35-9c5a-33e8336c1960
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713386047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1713386047
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2198460958
Short name T111
Test name
Test status
Simulation time 513249845 ps
CPU time 2.03 seconds
Started May 26 02:31:26 PM PDT 24
Finished May 26 02:31:29 PM PDT 24
Peak memory 200632 kb
Host smart-6141d2d6-4d09-42e1-953b-54f1709c29cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198460958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2198460958
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2951153587
Short name T577
Test name
Test status
Simulation time 170703092 ps
CPU time 1.49 seconds
Started May 26 02:31:25 PM PDT 24
Finished May 26 02:31:28 PM PDT 24
Peak memory 208868 kb
Host smart-ab2452eb-8cf5-4f0a-b88c-08a00e24511f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951153587 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2951153587
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2326919293
Short name T553
Test name
Test status
Simulation time 66189469 ps
CPU time 0.8 seconds
Started May 26 02:31:25 PM PDT 24
Finished May 26 02:31:27 PM PDT 24
Peak memory 200312 kb
Host smart-c6224019-a977-4a0c-b752-ef6e03b31844
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326919293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2326919293
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.254037954
Short name T563
Test name
Test status
Simulation time 138947378 ps
CPU time 1.31 seconds
Started May 26 02:31:24 PM PDT 24
Finished May 26 02:31:26 PM PDT 24
Peak memory 200660 kb
Host smart-e531b4af-98a5-414b-9076-9940af7653be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254037954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.254037954
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.989520174
Short name T598
Test name
Test status
Simulation time 123622986 ps
CPU time 1.59 seconds
Started May 26 02:31:26 PM PDT 24
Finished May 26 02:31:29 PM PDT 24
Peak memory 200576 kb
Host smart-73a578db-8ba3-4363-aa16-ad83b88e052d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989520174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.989520174
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1212255551
Short name T543
Test name
Test status
Simulation time 99898053 ps
CPU time 0.88 seconds
Started May 26 02:31:23 PM PDT 24
Finished May 26 02:31:25 PM PDT 24
Peak memory 200476 kb
Host smart-7ee35205-25f7-40d8-94b6-a9a71bf35838
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212255551 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1212255551
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.4115710184
Short name T96
Test name
Test status
Simulation time 59665527 ps
CPU time 0.8 seconds
Started May 26 02:31:26 PM PDT 24
Finished May 26 02:31:28 PM PDT 24
Peak memory 200356 kb
Host smart-2f14008c-15ca-4fdf-b979-0f894271284b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115710184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.4115710184
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2390954960
Short name T105
Test name
Test status
Simulation time 125700682 ps
CPU time 1.32 seconds
Started May 26 02:31:23 PM PDT 24
Finished May 26 02:31:25 PM PDT 24
Peak memory 200656 kb
Host smart-a69e8273-0abe-4de8-bbe0-4bee0d40c283
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390954960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2390954960
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1595358922
Short name T620
Test name
Test status
Simulation time 227190946 ps
CPU time 1.88 seconds
Started May 26 02:31:25 PM PDT 24
Finished May 26 02:31:28 PM PDT 24
Peak memory 200576 kb
Host smart-6a484f8a-86e0-4b67-a47d-be01d67136a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595358922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1595358922
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2368990996
Short name T591
Test name
Test status
Simulation time 792159416 ps
CPU time 3.01 seconds
Started May 26 02:31:23 PM PDT 24
Finished May 26 02:31:27 PM PDT 24
Peak memory 200644 kb
Host smart-090aefc7-d3ea-4f21-9179-fa8d5b06ff7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368990996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2368990996
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3200497613
Short name T91
Test name
Test status
Simulation time 133954929 ps
CPU time 1.11 seconds
Started May 26 02:31:24 PM PDT 24
Finished May 26 02:31:26 PM PDT 24
Peak memory 209704 kb
Host smart-045fd8bb-e466-4198-886b-bf879c270ee4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200497613 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3200497613
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1444682904
Short name T617
Test name
Test status
Simulation time 80815368 ps
CPU time 0.79 seconds
Started May 26 02:31:27 PM PDT 24
Finished May 26 02:31:29 PM PDT 24
Peak memory 200272 kb
Host smart-a5a0f618-2d29-461d-84c8-147b73125b29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444682904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1444682904
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3209932026
Short name T582
Test name
Test status
Simulation time 83034319 ps
CPU time 0.99 seconds
Started May 26 02:31:23 PM PDT 24
Finished May 26 02:31:24 PM PDT 24
Peak memory 200344 kb
Host smart-5d14192e-ba76-4359-8692-9e09d761881d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209932026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3209932026
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1377112510
Short name T115
Test name
Test status
Simulation time 476319961 ps
CPU time 3.76 seconds
Started May 26 02:31:25 PM PDT 24
Finished May 26 02:31:29 PM PDT 24
Peak memory 208784 kb
Host smart-45f17fc6-17aa-4311-9d92-f6bc7b7eb30a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377112510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1377112510
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2649306983
Short name T602
Test name
Test status
Simulation time 493367817 ps
CPU time 1.98 seconds
Started May 26 02:31:25 PM PDT 24
Finished May 26 02:31:28 PM PDT 24
Peak memory 200680 kb
Host smart-ec04792b-00f3-406c-a660-c9d8f87f79f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649306983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2649306983
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3375176591
Short name T555
Test name
Test status
Simulation time 445501960 ps
CPU time 2.66 seconds
Started May 26 02:30:57 PM PDT 24
Finished May 26 02:31:00 PM PDT 24
Peak memory 200452 kb
Host smart-83e70a9b-4747-4da3-acfc-2da7c9e23c94
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375176591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
375176591
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3020397672
Short name T565
Test name
Test status
Simulation time 480533040 ps
CPU time 6.27 seconds
Started May 26 02:30:55 PM PDT 24
Finished May 26 02:31:02 PM PDT 24
Peak memory 200632 kb
Host smart-7273e4e4-38fd-4d48-be26-b5f009963cc2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020397672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
020397672
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3892909616
Short name T593
Test name
Test status
Simulation time 92442358 ps
CPU time 0.8 seconds
Started May 26 02:30:58 PM PDT 24
Finished May 26 02:31:00 PM PDT 24
Peak memory 200236 kb
Host smart-3dc45407-343d-49df-9445-d01e551c02d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892909616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
892909616
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1423041028
Short name T605
Test name
Test status
Simulation time 196907827 ps
CPU time 1.27 seconds
Started May 26 02:30:58 PM PDT 24
Finished May 26 02:31:00 PM PDT 24
Peak memory 200620 kb
Host smart-bca84d65-d5ff-4065-8c0e-cbbd3a66fa09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423041028 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1423041028
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.4181793543
Short name T584
Test name
Test status
Simulation time 61369291 ps
CPU time 0.83 seconds
Started May 26 02:30:57 PM PDT 24
Finished May 26 02:30:58 PM PDT 24
Peak memory 200340 kb
Host smart-78203241-fa7e-41ea-91ba-d163ed126279
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181793543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.4181793543
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2573004452
Short name T601
Test name
Test status
Simulation time 84362963 ps
CPU time 0.94 seconds
Started May 26 02:30:56 PM PDT 24
Finished May 26 02:30:58 PM PDT 24
Peak memory 200420 kb
Host smart-69ff3235-524d-473e-8b5b-d0947b782f7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573004452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2573004452
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3859113527
Short name T113
Test name
Test status
Simulation time 139527833 ps
CPU time 2.12 seconds
Started May 26 02:30:58 PM PDT 24
Finished May 26 02:31:01 PM PDT 24
Peak memory 208824 kb
Host smart-abf0e0be-c338-428d-aff6-3f408ed8d925
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859113527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3859113527
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3879045079
Short name T546
Test name
Test status
Simulation time 863779750 ps
CPU time 3.05 seconds
Started May 26 02:30:59 PM PDT 24
Finished May 26 02:31:03 PM PDT 24
Peak memory 200620 kb
Host smart-48f31d8f-bd10-46b2-a238-27a5f68b5f93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879045079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3879045079
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1411235483
Short name T607
Test name
Test status
Simulation time 364321772 ps
CPU time 2.52 seconds
Started May 26 02:31:03 PM PDT 24
Finished May 26 02:31:06 PM PDT 24
Peak memory 200616 kb
Host smart-f2a76410-de8b-4f4c-aa88-84a919813a47
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411235483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
411235483
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2335629578
Short name T616
Test name
Test status
Simulation time 483865075 ps
CPU time 6.1 seconds
Started May 26 02:30:58 PM PDT 24
Finished May 26 02:31:05 PM PDT 24
Peak memory 200516 kb
Host smart-d003c32f-431c-43ac-b2ba-f6112c6b74fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335629578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
335629578
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.28277291
Short name T541
Test name
Test status
Simulation time 106413897 ps
CPU time 0.84 seconds
Started May 26 02:30:57 PM PDT 24
Finished May 26 02:30:59 PM PDT 24
Peak memory 200380 kb
Host smart-75e99ff9-eaf8-4323-908b-07912e90721d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28277291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.28277291
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1510693163
Short name T572
Test name
Test status
Simulation time 120027985 ps
CPU time 0.9 seconds
Started May 26 02:31:07 PM PDT 24
Finished May 26 02:31:09 PM PDT 24
Peak memory 200496 kb
Host smart-642b2ad7-b650-4b71-80a0-95323a418356
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510693163 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1510693163
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3308355081
Short name T109
Test name
Test status
Simulation time 60109018 ps
CPU time 0.77 seconds
Started May 26 02:30:56 PM PDT 24
Finished May 26 02:30:58 PM PDT 24
Peak memory 200380 kb
Host smart-76e887b9-ae86-4098-8d1d-5a8ac7a91fd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308355081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3308355081
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4016628961
Short name T568
Test name
Test status
Simulation time 240577117 ps
CPU time 1.55 seconds
Started May 26 02:31:04 PM PDT 24
Finished May 26 02:31:07 PM PDT 24
Peak memory 200556 kb
Host smart-8c28b5b0-a1db-41e2-abb4-5b45f90bb80e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016628961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.4016628961
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2884307919
Short name T575
Test name
Test status
Simulation time 414834303 ps
CPU time 2.96 seconds
Started May 26 02:30:57 PM PDT 24
Finished May 26 02:31:01 PM PDT 24
Peak memory 200600 kb
Host smart-fcdbadee-114a-4501-bea4-61bfa1066101
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884307919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2884307919
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2862040889
Short name T117
Test name
Test status
Simulation time 1025204185 ps
CPU time 3.19 seconds
Started May 26 02:30:57 PM PDT 24
Finished May 26 02:31:02 PM PDT 24
Peak memory 200692 kb
Host smart-60650cb6-2db7-4482-8b78-f9e80bc0a4a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862040889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2862040889
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3817976746
Short name T619
Test name
Test status
Simulation time 110022893 ps
CPU time 1.37 seconds
Started May 26 02:31:04 PM PDT 24
Finished May 26 02:31:06 PM PDT 24
Peak memory 200720 kb
Host smart-8a0aed37-9401-426b-8684-be620bbbfc71
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817976746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
817976746
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1392110475
Short name T588
Test name
Test status
Simulation time 1984301685 ps
CPU time 9.21 seconds
Started May 26 02:31:18 PM PDT 24
Finished May 26 02:31:28 PM PDT 24
Peak memory 200516 kb
Host smart-11c7ab8e-7b96-4199-bf78-beb50acaf435
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392110475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
392110475
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1229363978
Short name T579
Test name
Test status
Simulation time 138825933 ps
CPU time 0.91 seconds
Started May 26 02:31:05 PM PDT 24
Finished May 26 02:31:07 PM PDT 24
Peak memory 200400 kb
Host smart-995579f5-f36a-49ae-b3e7-0a93838a6fdb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229363978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
229363978
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1587614325
Short name T560
Test name
Test status
Simulation time 153314720 ps
CPU time 1.32 seconds
Started May 26 02:31:06 PM PDT 24
Finished May 26 02:31:08 PM PDT 24
Peak memory 208648 kb
Host smart-8c51fab7-553d-4c0d-ae58-597286e4a5ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587614325 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1587614325
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1227866003
Short name T597
Test name
Test status
Simulation time 55773221 ps
CPU time 0.81 seconds
Started May 26 02:31:03 PM PDT 24
Finished May 26 02:31:04 PM PDT 24
Peak memory 200340 kb
Host smart-acf681fe-5ad6-417c-a34a-a19b296313ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227866003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1227866003
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1476194936
Short name T108
Test name
Test status
Simulation time 142540235 ps
CPU time 1.32 seconds
Started May 26 02:31:07 PM PDT 24
Finished May 26 02:31:09 PM PDT 24
Peak memory 200628 kb
Host smart-3ca7003c-0717-40f5-82fd-66c5710dacdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476194936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1476194936
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2100797430
Short name T570
Test name
Test status
Simulation time 874876901 ps
CPU time 3.05 seconds
Started May 26 02:31:05 PM PDT 24
Finished May 26 02:31:09 PM PDT 24
Peak memory 200640 kb
Host smart-7305356c-b96b-4031-83af-83fff6e5e5be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100797430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2100797430
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1241905047
Short name T88
Test name
Test status
Simulation time 117323613 ps
CPU time 0.95 seconds
Started May 26 02:31:06 PM PDT 24
Finished May 26 02:31:07 PM PDT 24
Peak memory 200468 kb
Host smart-84b8e086-2bad-4201-94d0-b542d03e903f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241905047 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1241905047
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2566710163
Short name T545
Test name
Test status
Simulation time 75038996 ps
CPU time 0.78 seconds
Started May 26 02:31:07 PM PDT 24
Finished May 26 02:31:08 PM PDT 24
Peak memory 200324 kb
Host smart-b4e7c514-1f0e-45b5-86ac-ea1bc26adb76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566710163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2566710163
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3659680375
Short name T562
Test name
Test status
Simulation time 154741023 ps
CPU time 1.11 seconds
Started May 26 02:31:05 PM PDT 24
Finished May 26 02:31:07 PM PDT 24
Peak memory 200416 kb
Host smart-617e4674-80e7-4392-81ff-1e4e9697dfeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659680375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3659680375
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.187886595
Short name T590
Test name
Test status
Simulation time 206108181 ps
CPU time 1.72 seconds
Started May 26 02:31:04 PM PDT 24
Finished May 26 02:31:06 PM PDT 24
Peak memory 208792 kb
Host smart-49b6d7c5-8e0a-47b0-a90a-8f888b670f75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187886595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.187886595
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3127557530
Short name T121
Test name
Test status
Simulation time 489995417 ps
CPU time 1.99 seconds
Started May 26 02:31:04 PM PDT 24
Finished May 26 02:31:07 PM PDT 24
Peak memory 200668 kb
Host smart-af2bde38-6cf7-41c5-b869-6b3b8b4b2e66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127557530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.3127557530
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1886715096
Short name T90
Test name
Test status
Simulation time 108654523 ps
CPU time 1.09 seconds
Started May 26 02:31:05 PM PDT 24
Finished May 26 02:31:07 PM PDT 24
Peak memory 208824 kb
Host smart-a1137aa3-bb70-4a09-b53b-4b641222227b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886715096 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1886715096
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1094247207
Short name T107
Test name
Test status
Simulation time 65984589 ps
CPU time 0.78 seconds
Started May 26 02:31:06 PM PDT 24
Finished May 26 02:31:08 PM PDT 24
Peak memory 200376 kb
Host smart-89d6c344-c79d-4d1c-91df-92671792cd9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094247207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1094247207
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1533147745
Short name T596
Test name
Test status
Simulation time 86622156 ps
CPU time 0.97 seconds
Started May 26 02:31:07 PM PDT 24
Finished May 26 02:31:09 PM PDT 24
Peak memory 200444 kb
Host smart-8af0f9ea-33bf-4444-89b0-b67742abce57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533147745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1533147745
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.71329004
Short name T609
Test name
Test status
Simulation time 116159970 ps
CPU time 1.68 seconds
Started May 26 02:31:04 PM PDT 24
Finished May 26 02:31:07 PM PDT 24
Peak memory 208860 kb
Host smart-1ccd64f1-13e4-4d13-8bd3-f3b3a5be8bdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71329004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.71329004
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2350159123
Short name T551
Test name
Test status
Simulation time 800453596 ps
CPU time 2.83 seconds
Started May 26 02:31:06 PM PDT 24
Finished May 26 02:31:10 PM PDT 24
Peak memory 200600 kb
Host smart-bd32c675-8b16-49f4-8745-e18c103acb27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350159123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.2350159123
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.928564430
Short name T547
Test name
Test status
Simulation time 203404243 ps
CPU time 1.24 seconds
Started May 26 02:31:07 PM PDT 24
Finished May 26 02:31:09 PM PDT 24
Peak memory 200444 kb
Host smart-1eb0137e-8dad-402e-9942-bf7c686528ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928564430 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.928564430
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1961498588
Short name T554
Test name
Test status
Simulation time 60438109 ps
CPU time 0.83 seconds
Started May 26 02:31:04 PM PDT 24
Finished May 26 02:31:05 PM PDT 24
Peak memory 200368 kb
Host smart-3ce94adb-43b5-4d70-93a3-27e733067fe3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961498588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1961498588
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3138439970
Short name T603
Test name
Test status
Simulation time 114791644 ps
CPU time 1.08 seconds
Started May 26 02:31:06 PM PDT 24
Finished May 26 02:31:08 PM PDT 24
Peak memory 200436 kb
Host smart-09cbd364-799a-411b-9a2d-9cc86b78e160
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138439970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3138439970
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3429332985
Short name T574
Test name
Test status
Simulation time 481490028 ps
CPU time 3.34 seconds
Started May 26 02:31:06 PM PDT 24
Finished May 26 02:31:10 PM PDT 24
Peak memory 208796 kb
Host smart-e50ded3d-cdf9-43e4-8716-18c5dcf9e908
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429332985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3429332985
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3075698890
Short name T583
Test name
Test status
Simulation time 789128497 ps
CPU time 2.88 seconds
Started May 26 02:31:14 PM PDT 24
Finished May 26 02:31:18 PM PDT 24
Peak memory 200652 kb
Host smart-527a3e58-cba7-427c-8580-f22d676ac1bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075698890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3075698890
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3838263971
Short name T89
Test name
Test status
Simulation time 163321618 ps
CPU time 1.14 seconds
Started May 26 02:31:15 PM PDT 24
Finished May 26 02:31:17 PM PDT 24
Peak memory 200668 kb
Host smart-e094e300-9813-464e-bc53-4d84c5eecd37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838263971 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3838263971
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.539374499
Short name T594
Test name
Test status
Simulation time 89165789 ps
CPU time 0.85 seconds
Started May 26 02:31:16 PM PDT 24
Finished May 26 02:31:18 PM PDT 24
Peak memory 200352 kb
Host smart-427026a9-b709-4cbf-89bb-2d65d80b5876
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539374499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.539374499
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.292740005
Short name T104
Test name
Test status
Simulation time 192610497 ps
CPU time 1.66 seconds
Started May 26 02:31:17 PM PDT 24
Finished May 26 02:31:20 PM PDT 24
Peak memory 200600 kb
Host smart-1542833f-e57f-4589-b516-b01fda13c75e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292740005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.292740005
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1321913691
Short name T566
Test name
Test status
Simulation time 408157039 ps
CPU time 2.59 seconds
Started May 26 02:31:10 PM PDT 24
Finished May 26 02:31:13 PM PDT 24
Peak memory 208780 kb
Host smart-2837434b-d2fd-4279-b242-be45d706b72a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321913691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1321913691
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1569693777
Short name T595
Test name
Test status
Simulation time 889875635 ps
CPU time 2.99 seconds
Started May 26 02:31:17 PM PDT 24
Finished May 26 02:31:21 PM PDT 24
Peak memory 200656 kb
Host smart-a41b1c9e-25da-473e-abf0-b46c3d4e61d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569693777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1569693777
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2982851404
Short name T612
Test name
Test status
Simulation time 183332919 ps
CPU time 1.2 seconds
Started May 26 02:31:14 PM PDT 24
Finished May 26 02:31:17 PM PDT 24
Peak memory 210004 kb
Host smart-f3ca5968-03ff-4489-b421-38d608d91641
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982851404 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2982851404
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.317740669
Short name T569
Test name
Test status
Simulation time 76040267 ps
CPU time 0.81 seconds
Started May 26 02:31:17 PM PDT 24
Finished May 26 02:31:19 PM PDT 24
Peak memory 200320 kb
Host smart-9bd7c792-7093-4593-93c5-d0e119ec07ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317740669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.317740669
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.131657662
Short name T69
Test name
Test status
Simulation time 212161458 ps
CPU time 1.57 seconds
Started May 26 02:31:17 PM PDT 24
Finished May 26 02:31:20 PM PDT 24
Peak memory 200608 kb
Host smart-38992a8e-635c-4eb1-8f30-9b62db9ae37f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131657662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.131657662
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3005084997
Short name T573
Test name
Test status
Simulation time 363450815 ps
CPU time 2.65 seconds
Started May 26 02:31:15 PM PDT 24
Finished May 26 02:31:18 PM PDT 24
Peak memory 208836 kb
Host smart-5c4667cd-84c9-48a2-980d-541249296302
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005084997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3005084997
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3593361500
Short name T116
Test name
Test status
Simulation time 929834847 ps
CPU time 3.49 seconds
Started May 26 02:31:14 PM PDT 24
Finished May 26 02:31:19 PM PDT 24
Peak memory 200680 kb
Host smart-8bafc531-bd2e-41d6-893b-a3d8c7109a93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593361500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.3593361500
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.1305172569
Short name T260
Test name
Test status
Simulation time 108657375 ps
CPU time 0.85 seconds
Started May 26 01:55:46 PM PDT 24
Finished May 26 01:55:48 PM PDT 24
Peak memory 200352 kb
Host smart-3e894b26-5503-429a-b445-f14e40bc9d8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305172569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1305172569
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3649562175
Short name T129
Test name
Test status
Simulation time 2172962922 ps
CPU time 8.95 seconds
Started May 26 01:55:46 PM PDT 24
Finished May 26 01:55:56 PM PDT 24
Peak memory 217012 kb
Host smart-0d5c4c2c-df9b-490f-af5f-d23f77bcfc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649562175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3649562175
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.196196367
Short name T422
Test name
Test status
Simulation time 244951911 ps
CPU time 1.02 seconds
Started May 26 01:55:50 PM PDT 24
Finished May 26 01:55:51 PM PDT 24
Peak memory 217584 kb
Host smart-444e77c9-4a46-4cc3-8ce7-ffc4e704a41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196196367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.196196367
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3958845529
Short name T140
Test name
Test status
Simulation time 132248195 ps
CPU time 0.83 seconds
Started May 26 01:55:49 PM PDT 24
Finished May 26 01:55:51 PM PDT 24
Peak memory 200288 kb
Host smart-507c225c-2c30-47af-a706-0212409eb8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958845529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3958845529
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.375521996
Short name T77
Test name
Test status
Simulation time 16640200064 ps
CPU time 26.34 seconds
Started May 26 01:55:46 PM PDT 24
Finished May 26 01:56:14 PM PDT 24
Peak memory 217488 kb
Host smart-c1cf11cc-67e6-400a-a82e-c3f85f24c07b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375521996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.375521996
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.196493715
Short name T142
Test name
Test status
Simulation time 108116986 ps
CPU time 1 seconds
Started May 26 01:55:45 PM PDT 24
Finished May 26 01:55:47 PM PDT 24
Peak memory 200540 kb
Host smart-1541f429-896f-4820-b69c-e61929470ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196493715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.196493715
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.502896414
Short name T210
Test name
Test status
Simulation time 115622838 ps
CPU time 1.2 seconds
Started May 26 01:55:46 PM PDT 24
Finished May 26 01:55:48 PM PDT 24
Peak memory 200668 kb
Host smart-f7f28dd0-71d2-4603-b08f-802aca50449a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502896414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.502896414
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1903080259
Short name T436
Test name
Test status
Simulation time 6158116883 ps
CPU time 26.78 seconds
Started May 26 01:55:47 PM PDT 24
Finished May 26 01:56:15 PM PDT 24
Peak memory 200832 kb
Host smart-5418cb98-40c1-4776-a27e-142e17fed8c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903080259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1903080259
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1402728804
Short name T281
Test name
Test status
Simulation time 268454679 ps
CPU time 1.92 seconds
Started May 26 01:55:47 PM PDT 24
Finished May 26 01:55:50 PM PDT 24
Peak memory 200500 kb
Host smart-2b9ec91d-7889-4199-80d8-93cb46e362d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402728804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1402728804
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3986942275
Short name T185
Test name
Test status
Simulation time 205745286 ps
CPU time 1.36 seconds
Started May 26 01:55:45 PM PDT 24
Finished May 26 01:55:47 PM PDT 24
Peak memory 200536 kb
Host smart-afbb6fc8-e1bd-45fb-91dd-2af527b3d2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986942275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3986942275
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.351202789
Short name T430
Test name
Test status
Simulation time 70442020 ps
CPU time 0.81 seconds
Started May 26 01:56:04 PM PDT 24
Finished May 26 01:56:07 PM PDT 24
Peak memory 200276 kb
Host smart-b6076578-1202-435e-b749-e0cd6c4d3329
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351202789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.351202789
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2739242378
Short name T225
Test name
Test status
Simulation time 1891661777 ps
CPU time 7.24 seconds
Started May 26 01:55:49 PM PDT 24
Finished May 26 01:55:57 PM PDT 24
Peak memory 217088 kb
Host smart-d12e649d-1602-46c2-81a3-d7daa4eec1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739242378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2739242378
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1056963287
Short name T254
Test name
Test status
Simulation time 244323530 ps
CPU time 1.18 seconds
Started May 26 01:55:45 PM PDT 24
Finished May 26 01:55:47 PM PDT 24
Peak memory 217608 kb
Host smart-2d538d54-263c-4be9-8fb1-69c07866e1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056963287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1056963287
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2690123752
Short name T258
Test name
Test status
Simulation time 90397618 ps
CPU time 0.77 seconds
Started May 26 01:55:49 PM PDT 24
Finished May 26 01:55:51 PM PDT 24
Peak memory 200504 kb
Host smart-e02d7edb-52b3-4167-8103-431e57090734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690123752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2690123752
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1900317974
Short name T451
Test name
Test status
Simulation time 1100955628 ps
CPU time 4.74 seconds
Started May 26 01:55:47 PM PDT 24
Finished May 26 01:55:53 PM PDT 24
Peak memory 200592 kb
Host smart-d832a9c7-0750-45e1-87ad-5bac8f79a579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900317974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1900317974
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1069616384
Short name T74
Test name
Test status
Simulation time 16753702931 ps
CPU time 24.93 seconds
Started May 26 01:56:06 PM PDT 24
Finished May 26 01:56:33 PM PDT 24
Peak memory 217572 kb
Host smart-11632d01-c2bb-4857-852e-fe16e1a768a1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069616384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1069616384
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.4155967017
Short name T411
Test name
Test status
Simulation time 180074059 ps
CPU time 1.19 seconds
Started May 26 01:55:47 PM PDT 24
Finished May 26 01:55:50 PM PDT 24
Peak memory 200464 kb
Host smart-6595c9cd-28fb-4e18-bc72-e3ccfa964935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155967017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.4155967017
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1904167431
Short name T237
Test name
Test status
Simulation time 110413187 ps
CPU time 1.2 seconds
Started May 26 01:55:49 PM PDT 24
Finished May 26 01:55:51 PM PDT 24
Peak memory 200628 kb
Host smart-e3f57fea-6ca1-4394-a010-35ccda7bba20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904167431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1904167431
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3142929289
Short name T378
Test name
Test status
Simulation time 7081555158 ps
CPU time 31.11 seconds
Started May 26 01:56:05 PM PDT 24
Finished May 26 01:56:39 PM PDT 24
Peak memory 209040 kb
Host smart-7b3dffaa-3a0b-4db0-bd5e-723beb053fd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142929289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3142929289
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.4206632687
Short name T241
Test name
Test status
Simulation time 136866710 ps
CPU time 1.8 seconds
Started May 26 01:55:47 PM PDT 24
Finished May 26 01:55:50 PM PDT 24
Peak memory 200504 kb
Host smart-f5e15200-6b20-4038-9239-731c36c0d6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206632687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.4206632687
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.838738343
Short name T338
Test name
Test status
Simulation time 78041082 ps
CPU time 0.88 seconds
Started May 26 01:55:47 PM PDT 24
Finished May 26 01:55:49 PM PDT 24
Peak memory 200420 kb
Host smart-a4455d3a-c974-4400-9686-7cddee13df16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838738343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.838738343
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3907628322
Short name T435
Test name
Test status
Simulation time 57702076 ps
CPU time 0.79 seconds
Started May 26 01:56:11 PM PDT 24
Finished May 26 01:56:19 PM PDT 24
Peak memory 200332 kb
Host smart-0b30e545-79da-4365-b3aa-c436d82712f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907628322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3907628322
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1756832972
Short name T329
Test name
Test status
Simulation time 1225365876 ps
CPU time 5.7 seconds
Started May 26 01:56:13 PM PDT 24
Finished May 26 01:56:31 PM PDT 24
Peak memory 222152 kb
Host smart-207b0d0b-3818-49ad-b56c-d97e58feafe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756832972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1756832972
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3190273200
Short name T280
Test name
Test status
Simulation time 244496824 ps
CPU time 1.05 seconds
Started May 26 01:56:13 PM PDT 24
Finished May 26 01:56:27 PM PDT 24
Peak memory 217720 kb
Host smart-2ba2826d-d6b5-4d2e-aba2-bb2e0a01ef40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190273200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3190273200
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.906347549
Short name T522
Test name
Test status
Simulation time 143777811 ps
CPU time 0.83 seconds
Started May 26 01:56:16 PM PDT 24
Finished May 26 01:56:33 PM PDT 24
Peak memory 200480 kb
Host smart-8177a32b-3959-407e-b8af-3576d0313681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906347549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.906347549
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2852424589
Short name T442
Test name
Test status
Simulation time 2017260845 ps
CPU time 7.09 seconds
Started May 26 01:56:19 PM PDT 24
Finished May 26 01:56:44 PM PDT 24
Peak memory 200700 kb
Host smart-3f4dc74c-caa7-40e5-ba3d-3349132775e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852424589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2852424589
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2523969689
Short name T244
Test name
Test status
Simulation time 138525986 ps
CPU time 1.12 seconds
Started May 26 01:56:12 PM PDT 24
Finished May 26 01:56:21 PM PDT 24
Peak memory 200488 kb
Host smart-cc2e3543-9cde-4162-801f-ce5cb381299d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523969689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2523969689
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1772716625
Short name T456
Test name
Test status
Simulation time 254317191 ps
CPU time 1.5 seconds
Started May 26 01:56:19 PM PDT 24
Finished May 26 01:56:38 PM PDT 24
Peak memory 200696 kb
Host smart-5db16a7f-ad2d-4468-b43a-139123fd6980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772716625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1772716625
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.780943690
Short name T401
Test name
Test status
Simulation time 2459257169 ps
CPU time 12.48 seconds
Started May 26 01:56:10 PM PDT 24
Finished May 26 01:56:29 PM PDT 24
Peak memory 217116 kb
Host smart-48f76998-19ec-4aae-a64a-fe53ea55114e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780943690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.780943690
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2180380326
Short name T479
Test name
Test status
Simulation time 117981215 ps
CPU time 1.69 seconds
Started May 26 01:56:13 PM PDT 24
Finished May 26 01:56:26 PM PDT 24
Peak memory 208588 kb
Host smart-2a16b0ea-5bc7-4eee-bd82-eb265cc7977c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180380326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2180380326
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2126085691
Short name T344
Test name
Test status
Simulation time 69031679 ps
CPU time 0.76 seconds
Started May 26 01:56:16 PM PDT 24
Finished May 26 01:56:32 PM PDT 24
Peak memory 200492 kb
Host smart-0d0ccf0f-6f1b-430a-b65a-a3199c78a450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126085691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2126085691
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.837109656
Short name T309
Test name
Test status
Simulation time 75148365 ps
CPU time 0.83 seconds
Started May 26 01:56:14 PM PDT 24
Finished May 26 01:56:28 PM PDT 24
Peak memory 200288 kb
Host smart-27f5e2c8-37b5-4b17-bf89-0e839fbc4a01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837109656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.837109656
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3225166664
Short name T45
Test name
Test status
Simulation time 1897053444 ps
CPU time 7.25 seconds
Started May 26 01:56:15 PM PDT 24
Finished May 26 01:56:35 PM PDT 24
Peak memory 218040 kb
Host smart-30acb086-9b23-4568-b5ed-2272cc2c9c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225166664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3225166664
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.699439116
Short name T266
Test name
Test status
Simulation time 244490541 ps
CPU time 1.05 seconds
Started May 26 01:56:16 PM PDT 24
Finished May 26 01:56:33 PM PDT 24
Peak memory 217548 kb
Host smart-366b11ef-ce06-4951-8833-4057e895545b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699439116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.699439116
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.3968719945
Short name T264
Test name
Test status
Simulation time 86831658 ps
CPU time 0.75 seconds
Started May 26 01:56:14 PM PDT 24
Finished May 26 01:56:29 PM PDT 24
Peak memory 200264 kb
Host smart-3887256a-cfd4-4d7e-9397-ccff00e1f197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968719945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3968719945
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2170253738
Short name T125
Test name
Test status
Simulation time 1762418593 ps
CPU time 6.38 seconds
Started May 26 01:56:13 PM PDT 24
Finished May 26 01:56:29 PM PDT 24
Peak memory 200712 kb
Host smart-0cb1fc7d-3781-42d5-8178-20119cc13e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170253738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2170253738
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3419763398
Short name T315
Test name
Test status
Simulation time 106823544 ps
CPU time 1.01 seconds
Started May 26 01:56:14 PM PDT 24
Finished May 26 01:56:28 PM PDT 24
Peak memory 200504 kb
Host smart-9766a6f4-ade9-4e54-bc92-27a3bd92bb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419763398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3419763398
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3248739642
Short name T36
Test name
Test status
Simulation time 198953442 ps
CPU time 1.43 seconds
Started May 26 01:56:14 PM PDT 24
Finished May 26 01:56:30 PM PDT 24
Peak memory 200672 kb
Host smart-6fc64e55-507d-481f-8a1c-ce568dfcb86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248739642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3248739642
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.3946037937
Short name T128
Test name
Test status
Simulation time 474240056 ps
CPU time 2.73 seconds
Started May 26 01:56:13 PM PDT 24
Finished May 26 01:56:26 PM PDT 24
Peak memory 200500 kb
Host smart-0db6bb20-83c1-48c6-9a14-6d4b701a149b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946037937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3946037937
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2032644055
Short name T432
Test name
Test status
Simulation time 88820321 ps
CPU time 0.94 seconds
Started May 26 01:56:12 PM PDT 24
Finished May 26 01:56:21 PM PDT 24
Peak memory 200476 kb
Host smart-2576379e-06de-40fc-b3f7-bbba74527743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032644055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2032644055
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1918833747
Short name T242
Test name
Test status
Simulation time 85521485 ps
CPU time 0.85 seconds
Started May 26 01:56:19 PM PDT 24
Finished May 26 01:56:36 PM PDT 24
Peak memory 200324 kb
Host smart-cb2990c7-ac2c-4a15-9fc0-34c8c089fbc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918833747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1918833747
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.983964478
Short name T33
Test name
Test status
Simulation time 2350922153 ps
CPU time 7.86 seconds
Started May 26 01:56:19 PM PDT 24
Finished May 26 01:56:43 PM PDT 24
Peak memory 217504 kb
Host smart-2e52da42-f776-45ac-b008-1d3a45965cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983964478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.983964478
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3604876783
Short name T255
Test name
Test status
Simulation time 244690743 ps
CPU time 1.04 seconds
Started May 26 01:56:19 PM PDT 24
Finished May 26 01:56:37 PM PDT 24
Peak memory 217600 kb
Host smart-17b5c5f4-4d33-4c2e-92e1-ffc7e851f2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604876783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3604876783
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3125550369
Short name T486
Test name
Test status
Simulation time 149444169 ps
CPU time 0.86 seconds
Started May 26 01:56:16 PM PDT 24
Finished May 26 01:56:33 PM PDT 24
Peak memory 200276 kb
Host smart-03bd77ee-4d17-4e58-9fd5-cbbe412b2f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125550369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3125550369
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.225683293
Short name T102
Test name
Test status
Simulation time 1485789356 ps
CPU time 5.98 seconds
Started May 26 01:56:16 PM PDT 24
Finished May 26 01:56:38 PM PDT 24
Peak memory 200648 kb
Host smart-a653895c-61f1-4999-ae7b-db7374db72f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225683293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.225683293
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1464900043
Short name T52
Test name
Test status
Simulation time 98272851 ps
CPU time 1.02 seconds
Started May 26 01:56:15 PM PDT 24
Finished May 26 01:56:32 PM PDT 24
Peak memory 200516 kb
Host smart-90a1719c-da4d-4f84-bd2b-f310c8f1221d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464900043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1464900043
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.607492139
Short name T47
Test name
Test status
Simulation time 197910827 ps
CPU time 1.49 seconds
Started May 26 01:56:15 PM PDT 24
Finished May 26 01:56:32 PM PDT 24
Peak memory 200632 kb
Host smart-883494ee-bc1f-4a4e-bc53-4e9e3766cdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607492139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.607492139
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2016270643
Short name T87
Test name
Test status
Simulation time 9345977825 ps
CPU time 34.95 seconds
Started May 26 01:56:17 PM PDT 24
Finished May 26 01:57:08 PM PDT 24
Peak memory 208992 kb
Host smart-570bd513-f07c-4b5f-8811-5df0b0e215ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016270643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2016270643
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2571774302
Short name T464
Test name
Test status
Simulation time 115904921 ps
CPU time 1.59 seconds
Started May 26 01:56:15 PM PDT 24
Finished May 26 01:56:32 PM PDT 24
Peak memory 200504 kb
Host smart-4146eaf3-e5fb-44cc-87a9-208389981ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571774302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2571774302
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2146479215
Short name T274
Test name
Test status
Simulation time 137785357 ps
CPU time 1.12 seconds
Started May 26 01:56:15 PM PDT 24
Finished May 26 01:56:32 PM PDT 24
Peak memory 200504 kb
Host smart-cd536eeb-1d09-40e7-95c5-b70f293680d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146479215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2146479215
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2522154315
Short name T341
Test name
Test status
Simulation time 72449406 ps
CPU time 0.83 seconds
Started May 26 01:56:11 PM PDT 24
Finished May 26 01:56:19 PM PDT 24
Peak memory 200264 kb
Host smart-27e0a0a4-8ab2-4898-bc1c-0a30e4339ffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522154315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2522154315
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2175480097
Short name T279
Test name
Test status
Simulation time 2378097572 ps
CPU time 8.81 seconds
Started May 26 01:56:14 PM PDT 24
Finished May 26 01:56:36 PM PDT 24
Peak memory 218156 kb
Host smart-620d51c0-4b9e-4118-9606-e9b208b55c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175480097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2175480097
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.848121747
Short name T521
Test name
Test status
Simulation time 244249527 ps
CPU time 1.12 seconds
Started May 26 01:56:18 PM PDT 24
Finished May 26 01:56:36 PM PDT 24
Peak memory 217628 kb
Host smart-dd696656-65bf-40b6-b529-07ba8b9ebf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848121747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.848121747
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1602458941
Short name T458
Test name
Test status
Simulation time 178818325 ps
CPU time 0.99 seconds
Started May 26 01:56:19 PM PDT 24
Finished May 26 01:56:36 PM PDT 24
Peak memory 200276 kb
Host smart-27870fa7-b2a2-432b-b8cf-9244a7b3bda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602458941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1602458941
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.288502043
Short name T332
Test name
Test status
Simulation time 1382468228 ps
CPU time 5.96 seconds
Started May 26 01:56:22 PM PDT 24
Finished May 26 01:56:46 PM PDT 24
Peak memory 199924 kb
Host smart-c5d770d3-af75-4bb9-bc17-275f094e17e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288502043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.288502043
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2795299888
Short name T404
Test name
Test status
Simulation time 159374972 ps
CPU time 1.18 seconds
Started May 26 01:56:14 PM PDT 24
Finished May 26 01:56:28 PM PDT 24
Peak memory 200448 kb
Host smart-768fb834-f1d5-431a-8d15-6f04cfe3fa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795299888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2795299888
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3398642370
Short name T154
Test name
Test status
Simulation time 114944410 ps
CPU time 1.24 seconds
Started May 26 01:56:22 PM PDT 24
Finished May 26 01:56:41 PM PDT 24
Peak memory 199916 kb
Host smart-e1f076ff-98cc-45b0-85f9-c2f65362d5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398642370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3398642370
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2742599142
Short name T252
Test name
Test status
Simulation time 3936720718 ps
CPU time 14.72 seconds
Started May 26 01:56:17 PM PDT 24
Finished May 26 01:56:48 PM PDT 24
Peak memory 200836 kb
Host smart-6857e5ed-7fe5-4e5e-adc5-878ee95f33e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742599142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2742599142
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3535763119
Short name T9
Test name
Test status
Simulation time 110196765 ps
CPU time 1.42 seconds
Started May 26 01:56:18 PM PDT 24
Finished May 26 01:56:37 PM PDT 24
Peak memory 200452 kb
Host smart-b6d24adf-887c-4845-a916-189c665ca8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535763119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3535763119
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3367093241
Short name T312
Test name
Test status
Simulation time 124166168 ps
CPU time 1.12 seconds
Started May 26 01:56:15 PM PDT 24
Finished May 26 01:56:32 PM PDT 24
Peak memory 200480 kb
Host smart-c4a6a71f-680d-4e28-ba89-476af165fb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367093241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3367093241
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.64509085
Short name T398
Test name
Test status
Simulation time 67412586 ps
CPU time 0.82 seconds
Started May 26 01:56:19 PM PDT 24
Finished May 26 01:56:37 PM PDT 24
Peak memory 200332 kb
Host smart-36ff3f5c-77c1-4c83-8f53-79855b78fe84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64509085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.64509085
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1402869928
Short name T304
Test name
Test status
Simulation time 1224116483 ps
CPU time 5.73 seconds
Started May 26 01:56:19 PM PDT 24
Finished May 26 01:56:42 PM PDT 24
Peak memory 217104 kb
Host smart-815b971c-360c-4010-b04f-263b0a51c27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402869928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1402869928
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.504480686
Short name T189
Test name
Test status
Simulation time 244331278 ps
CPU time 1.06 seconds
Started May 26 01:56:20 PM PDT 24
Finished May 26 01:56:38 PM PDT 24
Peak memory 217752 kb
Host smart-a0ae0dd0-5c10-43f6-92b0-b54261016d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504480686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.504480686
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3512174210
Short name T169
Test name
Test status
Simulation time 146361398 ps
CPU time 0.85 seconds
Started May 26 01:56:17 PM PDT 24
Finished May 26 01:56:35 PM PDT 24
Peak memory 200312 kb
Host smart-39334ab9-0a90-4f59-b39f-bd477a301058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512174210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3512174210
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.1389154452
Short name T466
Test name
Test status
Simulation time 2226849227 ps
CPU time 8.08 seconds
Started May 26 01:56:21 PM PDT 24
Finished May 26 01:56:46 PM PDT 24
Peak memory 200640 kb
Host smart-14263fb7-f886-48f3-a723-ce5d18038c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389154452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1389154452
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2347165863
Short name T198
Test name
Test status
Simulation time 146997622 ps
CPU time 1.09 seconds
Started May 26 01:56:20 PM PDT 24
Finished May 26 01:56:38 PM PDT 24
Peak memory 200504 kb
Host smart-124044c0-7132-4128-829f-f1b396aaaf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347165863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2347165863
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3399930701
Short name T134
Test name
Test status
Simulation time 121416721 ps
CPU time 1.21 seconds
Started May 26 01:56:16 PM PDT 24
Finished May 26 01:56:33 PM PDT 24
Peak memory 200696 kb
Host smart-4655b0b7-3ffe-48a5-bffe-91116464e063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399930701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3399930701
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3204951290
Short name T334
Test name
Test status
Simulation time 2738973109 ps
CPU time 9.26 seconds
Started May 26 01:56:20 PM PDT 24
Finished May 26 01:56:47 PM PDT 24
Peak memory 209116 kb
Host smart-7e197900-03fc-44d8-af08-818b3ef437ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204951290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3204951290
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3809168950
Short name T214
Test name
Test status
Simulation time 361533832 ps
CPU time 2.02 seconds
Started May 26 01:56:21 PM PDT 24
Finished May 26 01:56:40 PM PDT 24
Peak memory 200380 kb
Host smart-36ad0fab-e4a4-4972-9bbd-87481d9f6763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809168950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3809168950
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3153476109
Short name T171
Test name
Test status
Simulation time 119440991 ps
CPU time 1.11 seconds
Started May 26 01:56:21 PM PDT 24
Finished May 26 01:56:39 PM PDT 24
Peak memory 200404 kb
Host smart-a15f52ec-0ded-4ddb-a03e-ce345fdb947c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153476109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3153476109
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.1078868760
Short name T357
Test name
Test status
Simulation time 152861692 ps
CPU time 0.94 seconds
Started May 26 01:56:25 PM PDT 24
Finished May 26 01:56:44 PM PDT 24
Peak memory 200312 kb
Host smart-974623fd-d10d-480a-b4b9-43d61d8c9a3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078868760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.1078868760
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2944014770
Short name T447
Test name
Test status
Simulation time 2374725696 ps
CPU time 9.44 seconds
Started May 26 01:56:14 PM PDT 24
Finished May 26 01:56:37 PM PDT 24
Peak memory 218268 kb
Host smart-ff142f4e-0163-4ab0-9be7-e8f32c91b4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944014770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2944014770
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.359129383
Short name T393
Test name
Test status
Simulation time 243816296 ps
CPU time 1.08 seconds
Started May 26 01:56:22 PM PDT 24
Finished May 26 01:56:41 PM PDT 24
Peak memory 217572 kb
Host smart-f38998fa-46ee-4d5d-b5dd-4ab21a5578f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359129383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.359129383
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.33440742
Short name T234
Test name
Test status
Simulation time 143657609 ps
CPU time 0.83 seconds
Started May 26 01:56:20 PM PDT 24
Finished May 26 01:56:37 PM PDT 24
Peak memory 200316 kb
Host smart-5d06985f-d5c5-4074-9794-d9bccc9403d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33440742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.33440742
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3741368274
Short name T475
Test name
Test status
Simulation time 830955340 ps
CPU time 4.33 seconds
Started May 26 01:56:20 PM PDT 24
Finished May 26 01:56:41 PM PDT 24
Peak memory 200608 kb
Host smart-4670e21f-4078-40b8-aca2-2d30be280ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741368274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3741368274
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.4290099068
Short name T186
Test name
Test status
Simulation time 108450433 ps
CPU time 1.02 seconds
Started May 26 01:56:11 PM PDT 24
Finished May 26 01:56:21 PM PDT 24
Peak memory 200512 kb
Host smart-668595e2-bca8-400d-b4cd-a7b6545ec7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290099068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.4290099068
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.2530215621
Short name T135
Test name
Test status
Simulation time 112816147 ps
CPU time 1.2 seconds
Started May 26 01:56:19 PM PDT 24
Finished May 26 01:56:38 PM PDT 24
Peak memory 200676 kb
Host smart-eca527a7-79de-4722-a997-39bae725c606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530215621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.2530215621
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3660920436
Short name T278
Test name
Test status
Simulation time 5521039505 ps
CPU time 20.18 seconds
Started May 26 01:56:21 PM PDT 24
Finished May 26 01:56:58 PM PDT 24
Peak memory 209016 kb
Host smart-727cb96e-c3e2-40cd-af9a-ba280aa8dc22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660920436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3660920436
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.3726660410
Short name T495
Test name
Test status
Simulation time 141619411 ps
CPU time 1.8 seconds
Started May 26 01:56:14 PM PDT 24
Finished May 26 01:56:28 PM PDT 24
Peak memory 200508 kb
Host smart-cbc6e6cd-3a56-47b7-8cfd-2e161f7bfe56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726660410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.3726660410
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.943653361
Short name T431
Test name
Test status
Simulation time 203154980 ps
CPU time 1.31 seconds
Started May 26 01:56:19 PM PDT 24
Finished May 26 01:56:38 PM PDT 24
Peak memory 200496 kb
Host smart-531e1134-3145-4c7b-9c8a-4f6a88cb319c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943653361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.943653361
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.258141231
Short name T311
Test name
Test status
Simulation time 69564483 ps
CPU time 0.78 seconds
Started May 26 01:56:27 PM PDT 24
Finished May 26 01:56:45 PM PDT 24
Peak memory 200204 kb
Host smart-68003b39-f330-4124-a37a-e205981ae23f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258141231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.258141231
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.311384916
Short name T28
Test name
Test status
Simulation time 1893092975 ps
CPU time 6.87 seconds
Started May 26 01:56:21 PM PDT 24
Finished May 26 01:56:45 PM PDT 24
Peak memory 222192 kb
Host smart-ac135d53-4e3d-4f5b-8fd7-6c5cfa9307af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311384916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.311384916
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3409088050
Short name T314
Test name
Test status
Simulation time 243567244 ps
CPU time 1.12 seconds
Started May 26 01:56:27 PM PDT 24
Finished May 26 01:56:45 PM PDT 24
Peak memory 217608 kb
Host smart-32d08c36-07ba-4021-af7b-0c935cd77787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409088050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3409088050
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2920981323
Short name T209
Test name
Test status
Simulation time 92188466 ps
CPU time 0.8 seconds
Started May 26 01:56:23 PM PDT 24
Finished May 26 01:56:41 PM PDT 24
Peak memory 200312 kb
Host smart-35916155-b160-48ed-ad46-241f14adfb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920981323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2920981323
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.704314924
Short name T413
Test name
Test status
Simulation time 1559624205 ps
CPU time 6.61 seconds
Started May 26 01:56:27 PM PDT 24
Finished May 26 01:56:50 PM PDT 24
Peak memory 200724 kb
Host smart-3ff552bc-0d7a-4169-9fa3-b4e636fdb5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704314924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.704314924
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3593660198
Short name T164
Test name
Test status
Simulation time 155156590 ps
CPU time 1.17 seconds
Started May 26 01:56:26 PM PDT 24
Finished May 26 01:56:44 PM PDT 24
Peak memory 200368 kb
Host smart-e2a4217f-9322-42b6-b3d1-b9b51e6420b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593660198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3593660198
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2838969195
Short name T345
Test name
Test status
Simulation time 247959206 ps
CPU time 1.51 seconds
Started May 26 01:56:26 PM PDT 24
Finished May 26 01:56:45 PM PDT 24
Peak memory 200664 kb
Host smart-54c0a417-a8bf-4333-b508-9403e07371f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838969195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2838969195
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.600233689
Short name T215
Test name
Test status
Simulation time 8978853441 ps
CPU time 33.22 seconds
Started May 26 01:56:26 PM PDT 24
Finished May 26 01:57:16 PM PDT 24
Peak memory 208896 kb
Host smart-4ececbf6-6307-48c6-861a-b4c0c2148554
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600233689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.600233689
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.1044045957
Short name T523
Test name
Test status
Simulation time 448247154 ps
CPU time 2.36 seconds
Started May 26 01:56:20 PM PDT 24
Finished May 26 01:56:40 PM PDT 24
Peak memory 200488 kb
Host smart-1d03daf0-5516-46a6-9761-6e59dcde197b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044045957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1044045957
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1692057912
Short name T163
Test name
Test status
Simulation time 241615007 ps
CPU time 1.48 seconds
Started May 26 01:56:22 PM PDT 24
Finished May 26 01:56:41 PM PDT 24
Peak memory 200588 kb
Host smart-569d8e0c-38b1-474b-8182-4001b9b67797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692057912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1692057912
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2268067323
Short name T506
Test name
Test status
Simulation time 2172470337 ps
CPU time 8.38 seconds
Started May 26 01:56:21 PM PDT 24
Finished May 26 01:56:47 PM PDT 24
Peak memory 222308 kb
Host smart-95462d41-d7d7-47e5-85aa-1c873d80175f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268067323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2268067323
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2185032482
Short name T454
Test name
Test status
Simulation time 244650977 ps
CPU time 1.06 seconds
Started May 26 01:56:21 PM PDT 24
Finished May 26 01:56:39 PM PDT 24
Peak memory 217556 kb
Host smart-d6d0ec6b-ef38-4cb3-a34f-91d49ebd5fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185032482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2185032482
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_reset.91653431
Short name T233
Test name
Test status
Simulation time 2269885732 ps
CPU time 8.51 seconds
Started May 26 01:56:22 PM PDT 24
Finished May 26 01:56:48 PM PDT 24
Peak memory 200876 kb
Host smart-0d2f8399-e100-4ce8-a270-2a3be4fd32b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91653431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.91653431
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.4124523344
Short name T289
Test name
Test status
Simulation time 146528335 ps
CPU time 1.22 seconds
Started May 26 01:56:20 PM PDT 24
Finished May 26 01:56:39 PM PDT 24
Peak memory 200448 kb
Host smart-a6707774-31a5-4fbe-9003-ec3daa2b7423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124523344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.4124523344
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.171726403
Short name T180
Test name
Test status
Simulation time 124733911 ps
CPU time 1.38 seconds
Started May 26 01:56:23 PM PDT 24
Finished May 26 01:56:42 PM PDT 24
Peak memory 200684 kb
Host smart-9f897061-6b16-4b52-91d3-2510e21674c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171726403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.171726403
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.2308265739
Short name T335
Test name
Test status
Simulation time 2045122012 ps
CPU time 10.64 seconds
Started May 26 01:56:26 PM PDT 24
Finished May 26 01:56:54 PM PDT 24
Peak memory 200696 kb
Host smart-5703dbfb-92ee-481d-81b1-2ce74608688c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308265739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2308265739
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.301311837
Short name T230
Test name
Test status
Simulation time 129280573 ps
CPU time 1.57 seconds
Started May 26 01:56:21 PM PDT 24
Finished May 26 01:56:40 PM PDT 24
Peak memory 200484 kb
Host smart-7184c241-f1b3-46a5-8477-e3b977b39550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301311837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.301311837
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.1260467427
Short name T228
Test name
Test status
Simulation time 252568623 ps
CPU time 1.48 seconds
Started May 26 01:56:26 PM PDT 24
Finished May 26 01:56:44 PM PDT 24
Peak memory 200696 kb
Host smart-82aad7c8-bf44-4157-9220-c9f9088596c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260467427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1260467427
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.4076269993
Short name T490
Test name
Test status
Simulation time 67077078 ps
CPU time 0.77 seconds
Started May 26 01:56:23 PM PDT 24
Finished May 26 01:56:41 PM PDT 24
Peak memory 200340 kb
Host smart-fc747bdc-cffd-47d0-864f-9fd84e08d395
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076269993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.4076269993
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.4225857287
Short name T34
Test name
Test status
Simulation time 1887424867 ps
CPU time 7.96 seconds
Started May 26 01:56:25 PM PDT 24
Finished May 26 01:56:51 PM PDT 24
Peak memory 217116 kb
Host smart-b552a4e0-0aae-490e-b805-10a3e6129f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225857287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.4225857287
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1115397628
Short name T468
Test name
Test status
Simulation time 244446062 ps
CPU time 1.11 seconds
Started May 26 01:56:22 PM PDT 24
Finished May 26 01:56:41 PM PDT 24
Peak memory 217708 kb
Host smart-bb50e0c9-b7d5-4205-99ac-c78e1f45c2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115397628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1115397628
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.523132420
Short name T196
Test name
Test status
Simulation time 129494196 ps
CPU time 0.8 seconds
Started May 26 01:56:23 PM PDT 24
Finished May 26 01:56:42 PM PDT 24
Peak memory 200316 kb
Host smart-bf977c69-9c2d-4bf3-bcd7-0cd7a73b848e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523132420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.523132420
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.792732438
Short name T250
Test name
Test status
Simulation time 1804716080 ps
CPU time 7.58 seconds
Started May 26 01:56:20 PM PDT 24
Finished May 26 01:56:45 PM PDT 24
Peak memory 200672 kb
Host smart-13bd232f-e4f5-4a3a-9cce-c1fe4cea2a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792732438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.792732438
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3944219255
Short name T240
Test name
Test status
Simulation time 147529734 ps
CPU time 1.15 seconds
Started May 26 01:56:20 PM PDT 24
Finished May 26 01:56:38 PM PDT 24
Peak memory 200496 kb
Host smart-af0e0c0a-8d28-4979-aeef-7fb2644d1a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944219255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3944219255
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3808086097
Short name T383
Test name
Test status
Simulation time 2820514472 ps
CPU time 12.37 seconds
Started May 26 01:56:22 PM PDT 24
Finished May 26 01:56:52 PM PDT 24
Peak memory 200792 kb
Host smart-8b1ebec8-7c7a-47ed-99f8-e9d46d3afcb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808086097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3808086097
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2652825303
Short name T519
Test name
Test status
Simulation time 145958198 ps
CPU time 1.79 seconds
Started May 26 01:56:20 PM PDT 24
Finished May 26 01:56:38 PM PDT 24
Peak memory 200484 kb
Host smart-07bf39e0-6a97-4ad3-87e0-cc42a5834318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652825303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2652825303
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1369743188
Short name T269
Test name
Test status
Simulation time 198356968 ps
CPU time 1.32 seconds
Started May 26 01:56:24 PM PDT 24
Finished May 26 01:56:43 PM PDT 24
Peak memory 200504 kb
Host smart-15e12ecb-d7ce-4309-a899-423f22312a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369743188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1369743188
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2695793580
Short name T277
Test name
Test status
Simulation time 67033025 ps
CPU time 0.77 seconds
Started May 26 01:56:27 PM PDT 24
Finished May 26 01:56:45 PM PDT 24
Peak memory 200232 kb
Host smart-fd81f5b8-cf56-400e-861a-ff58110ec873
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695793580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2695793580
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3116044616
Short name T327
Test name
Test status
Simulation time 1890703863 ps
CPU time 7.2 seconds
Started May 26 01:56:25 PM PDT 24
Finished May 26 01:56:49 PM PDT 24
Peak memory 222180 kb
Host smart-df77bc94-084b-4331-af8d-0df7f65cbb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116044616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3116044616
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1712564619
Short name T147
Test name
Test status
Simulation time 244416159 ps
CPU time 1.13 seconds
Started May 26 01:56:26 PM PDT 24
Finished May 26 01:56:44 PM PDT 24
Peak memory 217588 kb
Host smart-217ae01f-3e9d-4d4d-ae75-b0707fec55ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712564619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1712564619
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3982666817
Short name T340
Test name
Test status
Simulation time 132080860 ps
CPU time 0.84 seconds
Started May 26 01:56:21 PM PDT 24
Finished May 26 01:56:39 PM PDT 24
Peak memory 200304 kb
Host smart-a1a7f73d-9353-474f-86b5-f0eb7bec5e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982666817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3982666817
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3667114354
Short name T283
Test name
Test status
Simulation time 767705293 ps
CPU time 4.39 seconds
Started May 26 01:56:25 PM PDT 24
Finished May 26 01:56:47 PM PDT 24
Peak memory 200668 kb
Host smart-11c2c60e-20f0-4ef1-ac12-7e1e1ee70e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667114354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3667114354
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2462240143
Short name T449
Test name
Test status
Simulation time 181158771 ps
CPU time 1.23 seconds
Started May 26 01:56:26 PM PDT 24
Finished May 26 01:56:44 PM PDT 24
Peak memory 200520 kb
Host smart-441a3544-9f16-4f02-80f7-63fba9f10aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462240143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2462240143
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2344325037
Short name T201
Test name
Test status
Simulation time 221734030 ps
CPU time 1.48 seconds
Started May 26 01:56:27 PM PDT 24
Finished May 26 01:56:46 PM PDT 24
Peak memory 200552 kb
Host smart-4263f173-0e90-4a07-b6dd-f96cc95a01ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344325037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2344325037
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1966967176
Short name T249
Test name
Test status
Simulation time 3406433116 ps
CPU time 15.95 seconds
Started May 26 01:56:27 PM PDT 24
Finished May 26 01:57:00 PM PDT 24
Peak memory 200888 kb
Host smart-23beeeac-abc2-4835-a843-851bba36a129
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966967176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1966967176
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.2755245025
Short name T221
Test name
Test status
Simulation time 361083119 ps
CPU time 2.33 seconds
Started May 26 01:56:27 PM PDT 24
Finished May 26 01:56:46 PM PDT 24
Peak memory 200508 kb
Host smart-a4ceb0eb-65c8-4772-ae16-2456acb28541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755245025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.2755245025
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2649281388
Short name T319
Test name
Test status
Simulation time 168539546 ps
CPU time 1.35 seconds
Started May 26 01:56:27 PM PDT 24
Finished May 26 01:56:46 PM PDT 24
Peak memory 200700 kb
Host smart-2f951556-ddd4-4f94-acc3-a9743afb122f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649281388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2649281388
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1595429718
Short name T313
Test name
Test status
Simulation time 71911199 ps
CPU time 0.83 seconds
Started May 26 01:56:06 PM PDT 24
Finished May 26 01:56:09 PM PDT 24
Peak memory 200300 kb
Host smart-19e95c1f-993c-4b1d-842c-20000ee1569e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595429718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1595429718
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3086989875
Short name T438
Test name
Test status
Simulation time 1229630814 ps
CPU time 6.1 seconds
Started May 26 01:56:04 PM PDT 24
Finished May 26 01:56:11 PM PDT 24
Peak memory 218148 kb
Host smart-d54705bf-c2a1-47af-82d4-aad571cbd428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086989875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3086989875
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2949327646
Short name T461
Test name
Test status
Simulation time 244242825 ps
CPU time 1.17 seconds
Started May 26 01:56:07 PM PDT 24
Finished May 26 01:56:12 PM PDT 24
Peak memory 217756 kb
Host smart-51deadbd-08e9-46fe-a6dc-d751a1b4eb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949327646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2949327646
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3660565323
Short name T16
Test name
Test status
Simulation time 176859947 ps
CPU time 0.87 seconds
Started May 26 01:56:05 PM PDT 24
Finished May 26 01:56:08 PM PDT 24
Peak memory 200256 kb
Host smart-ea217222-579a-4d15-991d-7bd73161f402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660565323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3660565323
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.4080944913
Short name T384
Test name
Test status
Simulation time 742543698 ps
CPU time 4.26 seconds
Started May 26 01:56:08 PM PDT 24
Finished May 26 01:56:15 PM PDT 24
Peak memory 200668 kb
Host smart-aaf2f668-39ed-4ebe-a477-207da6e799c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080944913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.4080944913
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.892132519
Short name T73
Test name
Test status
Simulation time 8739190029 ps
CPU time 13.36 seconds
Started May 26 01:56:04 PM PDT 24
Finished May 26 01:56:19 PM PDT 24
Peak memory 217576 kb
Host smart-75734d90-86a4-45af-88d6-265fe644ca85
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892132519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.892132519
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1282334044
Short name T497
Test name
Test status
Simulation time 112026063 ps
CPU time 1.06 seconds
Started May 26 01:56:04 PM PDT 24
Finished May 26 01:56:06 PM PDT 24
Peak memory 200504 kb
Host smart-fbba3eea-8ffb-47e9-aa69-826c8f20a0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282334044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1282334044
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.2588468524
Short name T482
Test name
Test status
Simulation time 113605173 ps
CPU time 1.22 seconds
Started May 26 01:56:07 PM PDT 24
Finished May 26 01:56:11 PM PDT 24
Peak memory 200612 kb
Host smart-1a74b759-2a33-4d69-9baa-089ce696bc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588468524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2588468524
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.3589551325
Short name T408
Test name
Test status
Simulation time 2497680980 ps
CPU time 8.84 seconds
Started May 26 01:56:05 PM PDT 24
Finished May 26 01:56:16 PM PDT 24
Peak memory 200760 kb
Host smart-f56bfb28-d2dd-4514-a052-8523f210cb8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589551325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3589551325
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2553741620
Short name T426
Test name
Test status
Simulation time 428579384 ps
CPU time 2.68 seconds
Started May 26 01:56:05 PM PDT 24
Finished May 26 01:56:09 PM PDT 24
Peak memory 200472 kb
Host smart-838b45f0-8013-4261-855d-b8b71fdc226a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553741620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2553741620
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2657048454
Short name T380
Test name
Test status
Simulation time 83036353 ps
CPU time 0.81 seconds
Started May 26 01:56:04 PM PDT 24
Finished May 26 01:56:06 PM PDT 24
Peak memory 200420 kb
Host smart-82c791ec-d3a5-4f18-bea8-2628fb4db363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657048454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2657048454
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2622095640
Short name T212
Test name
Test status
Simulation time 73996244 ps
CPU time 0.79 seconds
Started May 26 01:56:21 PM PDT 24
Finished May 26 01:56:39 PM PDT 24
Peak memory 200364 kb
Host smart-35847593-6a53-458f-9a59-ae23c186baed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622095640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2622095640
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2500514002
Short name T2
Test name
Test status
Simulation time 1901178301 ps
CPU time 6.91 seconds
Started May 26 01:56:27 PM PDT 24
Finished May 26 01:56:51 PM PDT 24
Peak memory 221628 kb
Host smart-a30c20d0-367c-4de5-8244-441de11c6e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500514002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2500514002
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.776866193
Short name T296
Test name
Test status
Simulation time 244068941 ps
CPU time 1.11 seconds
Started May 26 01:56:19 PM PDT 24
Finished May 26 01:56:37 PM PDT 24
Peak memory 217556 kb
Host smart-3651f14f-b7cd-44d5-ace8-01aa2f56bbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776866193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.776866193
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.373833174
Short name T399
Test name
Test status
Simulation time 114910324 ps
CPU time 0.8 seconds
Started May 26 01:56:22 PM PDT 24
Finished May 26 01:56:41 PM PDT 24
Peak memory 200296 kb
Host smart-859aae5f-b638-4f95-9f25-4b4efd585d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373833174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.373833174
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2968080634
Short name T238
Test name
Test status
Simulation time 1555216585 ps
CPU time 5.94 seconds
Started May 26 01:56:20 PM PDT 24
Finished May 26 01:56:42 PM PDT 24
Peak memory 200684 kb
Host smart-3343a69f-a15f-4853-bb69-c4e6686dd36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968080634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2968080634
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2453582898
Short name T321
Test name
Test status
Simulation time 139952863 ps
CPU time 1.14 seconds
Started May 26 01:56:26 PM PDT 24
Finished May 26 01:56:44 PM PDT 24
Peak memory 200512 kb
Host smart-4e31d4cb-6a69-4c8a-ae46-ee1b6c900628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453582898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2453582898
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1925135838
Short name T227
Test name
Test status
Simulation time 118993626 ps
CPU time 1.18 seconds
Started May 26 01:56:26 PM PDT 24
Finished May 26 01:56:45 PM PDT 24
Peak memory 200664 kb
Host smart-14a21bc0-d081-45bd-8e0b-e5dd13800d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925135838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1925135838
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2318187553
Short name T527
Test name
Test status
Simulation time 8639142721 ps
CPU time 31.39 seconds
Started May 26 01:56:22 PM PDT 24
Finished May 26 01:57:11 PM PDT 24
Peak memory 200792 kb
Host smart-9820e742-9b8d-4fb5-a3c1-f765982af76c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318187553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2318187553
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3072372503
Short name T474
Test name
Test status
Simulation time 481750469 ps
CPU time 2.5 seconds
Started May 26 01:56:26 PM PDT 24
Finished May 26 01:56:46 PM PDT 24
Peak memory 208196 kb
Host smart-e235e27e-6ecb-423a-8fbd-cc73e977b72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072372503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3072372503
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2220495072
Short name T462
Test name
Test status
Simulation time 222315616 ps
CPU time 1.35 seconds
Started May 26 01:56:27 PM PDT 24
Finished May 26 01:56:45 PM PDT 24
Peak memory 200512 kb
Host smart-ed4588d4-ffe4-41f3-b88a-af9cebc5d866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220495072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2220495072
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.317537763
Short name T211
Test name
Test status
Simulation time 66659914 ps
CPU time 0.79 seconds
Started May 26 01:56:32 PM PDT 24
Finished May 26 01:56:47 PM PDT 24
Peak memory 200280 kb
Host smart-b6bcc289-5931-4dc1-ba24-423b9edcb002
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317537763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.317537763
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1996713856
Short name T157
Test name
Test status
Simulation time 244783657 ps
CPU time 1.04 seconds
Started May 26 01:56:26 PM PDT 24
Finished May 26 01:56:44 PM PDT 24
Peak memory 217680 kb
Host smart-b1dcc431-6107-4ac7-86c1-b43705da2d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996713856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1996713856
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1061208782
Short name T272
Test name
Test status
Simulation time 204665334 ps
CPU time 0.9 seconds
Started May 26 01:56:24 PM PDT 24
Finished May 26 01:56:43 PM PDT 24
Peak memory 200300 kb
Host smart-c2a10fbb-ffa1-4408-a044-ca8e48faaa52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061208782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1061208782
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3009965298
Short name T370
Test name
Test status
Simulation time 831123258 ps
CPU time 4.18 seconds
Started May 26 01:56:23 PM PDT 24
Finished May 26 01:56:44 PM PDT 24
Peak memory 200684 kb
Host smart-31b84a5d-4be3-4db8-b6ae-41131cb28379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009965298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3009965298
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.723566654
Short name T11
Test name
Test status
Simulation time 109579029 ps
CPU time 1.09 seconds
Started May 26 01:56:23 PM PDT 24
Finished May 26 01:56:42 PM PDT 24
Peak memory 200508 kb
Host smart-0ac6fc86-3e46-4d2f-95b1-67c4057b6981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723566654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.723566654
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3569603364
Short name T389
Test name
Test status
Simulation time 123074227 ps
CPU time 1.19 seconds
Started May 26 01:56:26 PM PDT 24
Finished May 26 01:56:44 PM PDT 24
Peak memory 200700 kb
Host smart-1b18c686-916a-4db1-892b-498916d4dad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569603364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3569603364
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2556327768
Short name T256
Test name
Test status
Simulation time 1006875531 ps
CPU time 4.91 seconds
Started May 26 01:56:27 PM PDT 24
Finished May 26 01:56:49 PM PDT 24
Peak memory 200732 kb
Host smart-111eef7c-2bec-4805-810e-bfc33782cb9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556327768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2556327768
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3475538631
Short name T226
Test name
Test status
Simulation time 347024299 ps
CPU time 1.96 seconds
Started May 26 01:56:22 PM PDT 24
Finished May 26 01:56:42 PM PDT 24
Peak memory 200452 kb
Host smart-0d586798-2ac8-4acd-b6f8-e99f4c966c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475538631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3475538631
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1233943488
Short name T229
Test name
Test status
Simulation time 90371763 ps
CPU time 0.87 seconds
Started May 26 01:56:27 PM PDT 24
Finished May 26 01:56:45 PM PDT 24
Peak memory 200484 kb
Host smart-ea731bb8-4df6-48b8-a304-e627092c188b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233943488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1233943488
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.4069314403
Short name T159
Test name
Test status
Simulation time 71738888 ps
CPU time 0.82 seconds
Started May 26 01:56:31 PM PDT 24
Finished May 26 01:56:47 PM PDT 24
Peak memory 200348 kb
Host smart-1971c32b-a718-41f2-963e-c10f8adc596b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069314403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.4069314403
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3274945936
Short name T27
Test name
Test status
Simulation time 2365550513 ps
CPU time 8.92 seconds
Started May 26 01:56:32 PM PDT 24
Finished May 26 01:56:55 PM PDT 24
Peak memory 217916 kb
Host smart-0cac50d4-9c97-4fad-8bfe-abce860e88cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274945936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3274945936
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3790666108
Short name T326
Test name
Test status
Simulation time 244373722 ps
CPU time 1.09 seconds
Started May 26 01:56:34 PM PDT 24
Finished May 26 01:56:48 PM PDT 24
Peak memory 217740 kb
Host smart-7cb48fac-2866-42ca-b5e1-eae57fcc6c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790666108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3790666108
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.4035879922
Short name T22
Test name
Test status
Simulation time 95032212 ps
CPU time 0.84 seconds
Started May 26 01:56:32 PM PDT 24
Finished May 26 01:56:47 PM PDT 24
Peak memory 200196 kb
Host smart-4ad749ca-69aa-4e0f-81c3-64ae1d9270b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035879922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.4035879922
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.859116669
Short name T270
Test name
Test status
Simulation time 911115563 ps
CPU time 4.45 seconds
Started May 26 01:56:33 PM PDT 24
Finished May 26 01:56:52 PM PDT 24
Peak memory 200592 kb
Host smart-00707130-3edb-4a54-900a-e1dbd6fc73c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859116669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.859116669
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2196721063
Short name T511
Test name
Test status
Simulation time 107580389 ps
CPU time 1.04 seconds
Started May 26 01:56:34 PM PDT 24
Finished May 26 01:56:49 PM PDT 24
Peak memory 200480 kb
Host smart-9ba6cbd9-8c4c-4bb6-b5c5-7fb0e76521e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196721063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2196721063
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3645081573
Short name T168
Test name
Test status
Simulation time 201329892 ps
CPU time 1.29 seconds
Started May 26 01:56:32 PM PDT 24
Finished May 26 01:56:48 PM PDT 24
Peak memory 200688 kb
Host smart-8f761ddf-5158-4c8d-a9a5-5d717a3650da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645081573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3645081573
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1637499234
Short name T306
Test name
Test status
Simulation time 2336506020 ps
CPU time 10.5 seconds
Started May 26 01:56:33 PM PDT 24
Finished May 26 01:56:58 PM PDT 24
Peak memory 200772 kb
Host smart-fe94a06f-a7ab-417c-bb76-fb8fe3d69965
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637499234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1637499234
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2026073071
Short name T292
Test name
Test status
Simulation time 140540760 ps
CPU time 1.16 seconds
Started May 26 01:56:32 PM PDT 24
Finished May 26 01:56:48 PM PDT 24
Peak memory 200440 kb
Host smart-547387bc-1658-4e06-99c5-d76bad1259c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026073071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2026073071
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3878556335
Short name T406
Test name
Test status
Simulation time 83165282 ps
CPU time 0.86 seconds
Started May 26 01:56:34 PM PDT 24
Finished May 26 01:56:48 PM PDT 24
Peak memory 200284 kb
Host smart-1defdefb-0e8b-4e65-a8d8-ad9308e2b1f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878556335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3878556335
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1191378630
Short name T513
Test name
Test status
Simulation time 1225322944 ps
CPU time 6.09 seconds
Started May 26 01:56:33 PM PDT 24
Finished May 26 01:56:53 PM PDT 24
Peak memory 222140 kb
Host smart-fc8b165b-a807-4be4-9edd-ff3977b89a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191378630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1191378630
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.4149507434
Short name T299
Test name
Test status
Simulation time 244452497 ps
CPU time 1.04 seconds
Started May 26 01:56:33 PM PDT 24
Finished May 26 01:56:48 PM PDT 24
Peak memory 217624 kb
Host smart-6d56797e-8435-4c34-acfb-f2bce8647a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149507434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.4149507434
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.436324359
Short name T21
Test name
Test status
Simulation time 184374469 ps
CPU time 0.86 seconds
Started May 26 01:56:33 PM PDT 24
Finished May 26 01:56:48 PM PDT 24
Peak memory 200288 kb
Host smart-aa2c6a1f-5a8d-4e4c-ad04-3780d804b5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436324359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.436324359
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.3872318973
Short name T158
Test name
Test status
Simulation time 933788756 ps
CPU time 4.51 seconds
Started May 26 01:56:31 PM PDT 24
Finished May 26 01:56:51 PM PDT 24
Peak memory 200680 kb
Host smart-0a4983e9-5d73-4f7c-8b37-0b846948e724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872318973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3872318973
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2170601178
Short name T78
Test name
Test status
Simulation time 158034441 ps
CPU time 1.19 seconds
Started May 26 01:56:32 PM PDT 24
Finished May 26 01:56:48 PM PDT 24
Peak memory 200520 kb
Host smart-bf52fc96-44f1-4ff8-89cf-f19e1a8bcb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170601178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2170601178
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2208118073
Short name T362
Test name
Test status
Simulation time 200870764 ps
CPU time 1.37 seconds
Started May 26 01:56:34 PM PDT 24
Finished May 26 01:56:49 PM PDT 24
Peak memory 200628 kb
Host smart-0ebf75ae-7c7f-4c3c-a24c-3f30e04508c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208118073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2208118073
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2769385218
Short name T10
Test name
Test status
Simulation time 139487065 ps
CPU time 1.75 seconds
Started May 26 01:56:32 PM PDT 24
Finished May 26 01:56:48 PM PDT 24
Peak memory 200488 kb
Host smart-6b81fbd9-4a74-4f6c-8c0d-994c9b3fe79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769385218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2769385218
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.971621367
Short name T83
Test name
Test status
Simulation time 78195025 ps
CPU time 0.81 seconds
Started May 26 01:56:33 PM PDT 24
Finished May 26 01:56:48 PM PDT 24
Peak memory 200508 kb
Host smart-38fd48a4-bf6c-48a9-a47d-325fcc2e8e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971621367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.971621367
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2179058851
Short name T170
Test name
Test status
Simulation time 77529714 ps
CPU time 0.83 seconds
Started May 26 01:56:39 PM PDT 24
Finished May 26 01:56:51 PM PDT 24
Peak memory 200324 kb
Host smart-80155c53-8ad6-45d2-9b97-b1e786410593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179058851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2179058851
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3174950470
Short name T42
Test name
Test status
Simulation time 2183715300 ps
CPU time 7.47 seconds
Started May 26 01:56:39 PM PDT 24
Finished May 26 01:56:57 PM PDT 24
Peak memory 217728 kb
Host smart-9ba87fd4-d481-4b63-be6d-04b89e2d5e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174950470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3174950470
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.188601492
Short name T379
Test name
Test status
Simulation time 245665886 ps
CPU time 1.07 seconds
Started May 26 01:56:39 PM PDT 24
Finished May 26 01:56:51 PM PDT 24
Peak memory 217572 kb
Host smart-33506471-d502-435d-a6f9-5a45a27cca8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188601492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.188601492
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1472399502
Short name T18
Test name
Test status
Simulation time 139109300 ps
CPU time 0.9 seconds
Started May 26 01:56:40 PM PDT 24
Finished May 26 01:56:51 PM PDT 24
Peak memory 200312 kb
Host smart-7c790654-4424-449b-ba1b-707ae85e1282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472399502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1472399502
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3959801744
Short name T6
Test name
Test status
Simulation time 1723000598 ps
CPU time 6.52 seconds
Started May 26 01:56:34 PM PDT 24
Finished May 26 01:56:54 PM PDT 24
Peak memory 200660 kb
Host smart-73cf9975-37dd-40e7-9e30-de4381f1f553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959801744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3959801744
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1493749544
Short name T219
Test name
Test status
Simulation time 102736771 ps
CPU time 1.01 seconds
Started May 26 01:56:34 PM PDT 24
Finished May 26 01:56:49 PM PDT 24
Peak memory 200496 kb
Host smart-786abd5f-55c7-47cf-b32a-91fab7e55921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493749544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1493749544
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2757603920
Short name T246
Test name
Test status
Simulation time 121245525 ps
CPU time 1.26 seconds
Started May 26 01:56:33 PM PDT 24
Finished May 26 01:56:48 PM PDT 24
Peak memory 200648 kb
Host smart-c6d47438-29d6-475f-a813-91cec0f535cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757603920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2757603920
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.4070050557
Short name T488
Test name
Test status
Simulation time 16418253098 ps
CPU time 56.92 seconds
Started May 26 01:56:34 PM PDT 24
Finished May 26 01:57:44 PM PDT 24
Peak memory 200848 kb
Host smart-176f6b4e-8051-4c1f-a9ff-6e78a734c0ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070050557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.4070050557
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1973117644
Short name T508
Test name
Test status
Simulation time 417042993 ps
CPU time 2.37 seconds
Started May 26 01:56:34 PM PDT 24
Finished May 26 01:56:50 PM PDT 24
Peak memory 200496 kb
Host smart-37de4e2e-8bf3-4321-b287-fd14f243ed0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973117644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1973117644
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1133470652
Short name T505
Test name
Test status
Simulation time 119498551 ps
CPU time 1.12 seconds
Started May 26 01:56:34 PM PDT 24
Finished May 26 01:56:49 PM PDT 24
Peak memory 200492 kb
Host smart-b2423ce4-c955-4c20-91c4-8bf7f4a3e8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133470652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1133470652
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.708418609
Short name T75
Test name
Test status
Simulation time 66737287 ps
CPU time 0.77 seconds
Started May 26 01:56:40 PM PDT 24
Finished May 26 01:56:51 PM PDT 24
Peak memory 200368 kb
Host smart-ee8bf124-3480-4c3d-8c0a-f3d5611891e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708418609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.708418609
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1193324827
Short name T531
Test name
Test status
Simulation time 2355009613 ps
CPU time 8.91 seconds
Started May 26 01:56:36 PM PDT 24
Finished May 26 01:56:57 PM PDT 24
Peak memory 218020 kb
Host smart-6165a2a6-3aa2-4f72-b1f9-4823c6a6cf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193324827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1193324827
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2011232901
Short name T346
Test name
Test status
Simulation time 244737720 ps
CPU time 1.11 seconds
Started May 26 01:56:37 PM PDT 24
Finished May 26 01:56:50 PM PDT 24
Peak memory 217648 kb
Host smart-929c5ed0-6d5b-4f10-9d5c-012deacb27ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011232901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2011232901
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.2250234307
Short name T518
Test name
Test status
Simulation time 196709034 ps
CPU time 0.9 seconds
Started May 26 01:56:39 PM PDT 24
Finished May 26 01:56:51 PM PDT 24
Peak memory 200364 kb
Host smart-0b9bf9cc-41da-40c4-93e4-473313ec8348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250234307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2250234307
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1644797140
Short name T247
Test name
Test status
Simulation time 1907746633 ps
CPU time 7.48 seconds
Started May 26 01:56:34 PM PDT 24
Finished May 26 01:56:55 PM PDT 24
Peak memory 200224 kb
Host smart-cce079ae-5f12-483d-bf4f-993fa4f31879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644797140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1644797140
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.627212945
Short name T160
Test name
Test status
Simulation time 107706795 ps
CPU time 1 seconds
Started May 26 01:56:36 PM PDT 24
Finished May 26 01:56:50 PM PDT 24
Peak memory 200496 kb
Host smart-5159fa2e-e4c9-49f5-97b8-0354f66e7cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627212945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.627212945
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3864394845
Short name T352
Test name
Test status
Simulation time 194864043 ps
CPU time 1.46 seconds
Started May 26 01:56:40 PM PDT 24
Finished May 26 01:56:52 PM PDT 24
Peak memory 200720 kb
Host smart-7e157611-379e-41de-924f-d6831a5af10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864394845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3864394845
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2867588445
Short name T400
Test name
Test status
Simulation time 1338535914 ps
CPU time 6.13 seconds
Started May 26 01:56:35 PM PDT 24
Finished May 26 01:56:55 PM PDT 24
Peak memory 200788 kb
Host smart-163cb6e0-4adb-4fe2-8c52-38e5f33d0134
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867588445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2867588445
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.4046469942
Short name T536
Test name
Test status
Simulation time 154787122 ps
CPU time 1.95 seconds
Started May 26 01:56:39 PM PDT 24
Finished May 26 01:56:52 PM PDT 24
Peak memory 200548 kb
Host smart-11219c9b-ec12-4564-96e2-47f4826c0ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046469942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.4046469942
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2588441823
Short name T257
Test name
Test status
Simulation time 170731826 ps
CPU time 1.26 seconds
Started May 26 01:56:34 PM PDT 24
Finished May 26 01:56:49 PM PDT 24
Peak memory 200180 kb
Host smart-ef4a4d3e-285a-492a-a209-2dc17d7a0ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588441823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2588441823
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.4224933283
Short name T216
Test name
Test status
Simulation time 86365950 ps
CPU time 0.86 seconds
Started May 26 01:56:32 PM PDT 24
Finished May 26 01:56:47 PM PDT 24
Peak memory 200324 kb
Host smart-79ad2803-b3d1-4fb4-8b13-2b8be2512921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224933283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.4224933283
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2911756560
Short name T507
Test name
Test status
Simulation time 2352640844 ps
CPU time 8.16 seconds
Started May 26 01:56:39 PM PDT 24
Finished May 26 01:56:58 PM PDT 24
Peak memory 222352 kb
Host smart-f810d0b1-7569-4949-88e8-ec754adc9323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911756560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2911756560
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1192606891
Short name T307
Test name
Test status
Simulation time 243496886 ps
CPU time 1.05 seconds
Started May 26 01:56:39 PM PDT 24
Finished May 26 01:56:51 PM PDT 24
Peak memory 217668 kb
Host smart-d2732dc9-1130-49eb-8f87-b2c3278d7057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192606891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1192606891
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3308512250
Short name T417
Test name
Test status
Simulation time 103078870 ps
CPU time 0.75 seconds
Started May 26 01:56:40 PM PDT 24
Finished May 26 01:56:51 PM PDT 24
Peak memory 200364 kb
Host smart-e911fcbf-162f-4c6b-a2c6-642de5287bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308512250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3308512250
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.223506399
Short name T101
Test name
Test status
Simulation time 1805128895 ps
CPU time 6.74 seconds
Started May 26 01:56:40 PM PDT 24
Finished May 26 01:56:57 PM PDT 24
Peak memory 200728 kb
Host smart-00e63476-cae4-4382-afe3-b3d63317b196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223506399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.223506399
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3993606367
Short name T188
Test name
Test status
Simulation time 152289993 ps
CPU time 1.12 seconds
Started May 26 01:56:37 PM PDT 24
Finished May 26 01:56:51 PM PDT 24
Peak memory 200672 kb
Host smart-b976a6dc-47f7-41ff-85d5-baadbc306501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993606367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3993606367
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.2796678619
Short name T184
Test name
Test status
Simulation time 187694858 ps
CPU time 1.4 seconds
Started May 26 01:56:35 PM PDT 24
Finished May 26 01:56:50 PM PDT 24
Peak memory 200724 kb
Host smart-5f9d3472-3a23-45af-a8eb-841aacca1cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796678619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.2796678619
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.1461909275
Short name T503
Test name
Test status
Simulation time 4232406446 ps
CPU time 15.98 seconds
Started May 26 01:56:37 PM PDT 24
Finished May 26 01:57:05 PM PDT 24
Peak memory 200968 kb
Host smart-c64d069e-7892-4bcb-8e4f-b39b336b2f60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461909275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1461909275
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.1607488296
Short name T423
Test name
Test status
Simulation time 445695336 ps
CPU time 2.3 seconds
Started May 26 01:56:36 PM PDT 24
Finished May 26 01:56:51 PM PDT 24
Peak memory 200396 kb
Host smart-5c5c2505-e0c8-4fb0-9043-dfe992fdbe7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607488296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.1607488296
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.1369729773
Short name T57
Test name
Test status
Simulation time 71865756 ps
CPU time 0.82 seconds
Started May 26 01:56:37 PM PDT 24
Finished May 26 01:56:50 PM PDT 24
Peak memory 200672 kb
Host smart-499ed932-e4b1-4f10-beed-1e7f24a482de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369729773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1369729773
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.4173282332
Short name T489
Test name
Test status
Simulation time 78272938 ps
CPU time 0.81 seconds
Started May 26 01:56:38 PM PDT 24
Finished May 26 01:56:50 PM PDT 24
Peak memory 200312 kb
Host smart-5e6dbfa5-23cb-4191-8067-109db53bf7b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173282332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.4173282332
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3525876334
Short name T316
Test name
Test status
Simulation time 1228575872 ps
CPU time 5.92 seconds
Started May 26 01:56:34 PM PDT 24
Finished May 26 01:56:53 PM PDT 24
Peak memory 218148 kb
Host smart-0dc026be-23ed-477d-b48b-d2892ec83b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525876334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3525876334
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3180386392
Short name T4
Test name
Test status
Simulation time 244320437 ps
CPU time 1.12 seconds
Started May 26 01:56:39 PM PDT 24
Finished May 26 01:56:51 PM PDT 24
Peak memory 217672 kb
Host smart-3f466037-5d87-4bad-82f9-d858ab07d549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180386392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3180386392
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.526147077
Short name T459
Test name
Test status
Simulation time 232942454 ps
CPU time 0.94 seconds
Started May 26 01:56:32 PM PDT 24
Finished May 26 01:56:48 PM PDT 24
Peak memory 200288 kb
Host smart-040de35a-b99e-4cce-a81a-e6819edf26b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526147077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.526147077
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2135638747
Short name T472
Test name
Test status
Simulation time 1067839504 ps
CPU time 5.55 seconds
Started May 26 01:56:32 PM PDT 24
Finished May 26 01:56:52 PM PDT 24
Peak memory 200696 kb
Host smart-009a985d-6cf0-42af-b1b2-cd379296e146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135638747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2135638747
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3680550076
Short name T259
Test name
Test status
Simulation time 150902091 ps
CPU time 1.19 seconds
Started May 26 01:56:32 PM PDT 24
Finished May 26 01:56:47 PM PDT 24
Peak memory 200432 kb
Host smart-d89415c1-fe33-446f-a2c2-990c666d2b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680550076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3680550076
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2579993750
Short name T81
Test name
Test status
Simulation time 227404595 ps
CPU time 1.53 seconds
Started May 26 01:56:32 PM PDT 24
Finished May 26 01:56:48 PM PDT 24
Peak memory 200724 kb
Host smart-9d0e6180-d328-4095-948b-17f586e08b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579993750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2579993750
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2924992661
Short name T385
Test name
Test status
Simulation time 1153049756 ps
CPU time 5.03 seconds
Started May 26 01:56:45 PM PDT 24
Finished May 26 01:56:57 PM PDT 24
Peak memory 200664 kb
Host smart-34049038-74e2-45db-89a5-9012022ba708
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924992661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2924992661
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2007280658
Short name T284
Test name
Test status
Simulation time 332702320 ps
CPU time 2.16 seconds
Started May 26 01:56:32 PM PDT 24
Finished May 26 01:56:49 PM PDT 24
Peak memory 200496 kb
Host smart-a027ac41-75b8-40c2-9dd2-5d990bda4bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007280658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2007280658
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.200485643
Short name T407
Test name
Test status
Simulation time 69229914 ps
CPU time 0.76 seconds
Started May 26 01:56:32 PM PDT 24
Finished May 26 01:56:47 PM PDT 24
Peak memory 200400 kb
Host smart-90111305-92fa-4968-a100-a650a3986715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200485643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.200485643
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.719535200
Short name T46
Test name
Test status
Simulation time 76615178 ps
CPU time 0.81 seconds
Started May 26 01:56:48 PM PDT 24
Finished May 26 01:56:54 PM PDT 24
Peak memory 200276 kb
Host smart-809e20b5-57d4-4e9a-b204-58e4285b476b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719535200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.719535200
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2783421968
Short name T26
Test name
Test status
Simulation time 1220949042 ps
CPU time 5.74 seconds
Started May 26 01:56:42 PM PDT 24
Finished May 26 01:56:57 PM PDT 24
Peak memory 218148 kb
Host smart-750e6ca6-c4c4-4cd1-9c8f-8cd01104b217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783421968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2783421968
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1141177821
Short name T470
Test name
Test status
Simulation time 245625345 ps
CPU time 1.02 seconds
Started May 26 01:56:39 PM PDT 24
Finished May 26 01:56:51 PM PDT 24
Peak memory 217480 kb
Host smart-30e03eba-4913-4b5d-b766-c57b7d898c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141177821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1141177821
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3494492801
Short name T364
Test name
Test status
Simulation time 77860497 ps
CPU time 0.73 seconds
Started May 26 01:56:46 PM PDT 24
Finished May 26 01:56:53 PM PDT 24
Peak memory 200264 kb
Host smart-1df0354e-9124-4f0c-a6bf-facf5453850b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494492801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3494492801
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3907462255
Short name T282
Test name
Test status
Simulation time 1490538003 ps
CPU time 5.84 seconds
Started May 26 01:56:37 PM PDT 24
Finished May 26 01:56:55 PM PDT 24
Peak memory 200660 kb
Host smart-a3bcc4d0-8997-404a-955a-72a8301d422a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907462255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3907462255
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3084238463
Short name T224
Test name
Test status
Simulation time 107901911 ps
CPU time 1 seconds
Started May 26 01:56:45 PM PDT 24
Finished May 26 01:56:53 PM PDT 24
Peak memory 200456 kb
Host smart-1b6e68cd-4780-440f-b7c8-63c63412d691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084238463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3084238463
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.3278850256
Short name T177
Test name
Test status
Simulation time 125657377 ps
CPU time 1.29 seconds
Started May 26 01:56:39 PM PDT 24
Finished May 26 01:56:51 PM PDT 24
Peak memory 200668 kb
Host smart-dd2be8cc-21cb-4b80-90f9-771c108be070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278850256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3278850256
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1196741310
Short name T323
Test name
Test status
Simulation time 2308916393 ps
CPU time 9.46 seconds
Started May 26 01:56:38 PM PDT 24
Finished May 26 01:56:59 PM PDT 24
Peak memory 200744 kb
Host smart-c5b23702-840a-4b21-8ab3-ff5d5afceb07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196741310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1196741310
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1489316971
Short name T328
Test name
Test status
Simulation time 157824958 ps
CPU time 2 seconds
Started May 26 01:56:42 PM PDT 24
Finished May 26 01:56:53 PM PDT 24
Peak memory 200500 kb
Host smart-a13e21b0-de5f-47ed-9d67-59d0f5c52385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489316971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1489316971
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1794373609
Short name T484
Test name
Test status
Simulation time 121287570 ps
CPU time 1.03 seconds
Started May 26 01:56:45 PM PDT 24
Finished May 26 01:56:53 PM PDT 24
Peak memory 200452 kb
Host smart-a2191fea-7b52-42d9-bbd4-1414854281ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794373609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1794373609
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.2889289279
Short name T148
Test name
Test status
Simulation time 64576767 ps
CPU time 0.76 seconds
Started May 26 01:56:48 PM PDT 24
Finished May 26 01:56:54 PM PDT 24
Peak memory 200324 kb
Host smart-e027099e-7a1d-4474-8f65-b52d416ed592
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889289279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2889289279
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2345379846
Short name T496
Test name
Test status
Simulation time 1891294061 ps
CPU time 6.54 seconds
Started May 26 01:56:46 PM PDT 24
Finished May 26 01:56:59 PM PDT 24
Peak memory 217112 kb
Host smart-3831ca65-7ef4-43c0-951e-cd23a20b87c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345379846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2345379846
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.4058399077
Short name T369
Test name
Test status
Simulation time 244999689 ps
CPU time 1.07 seconds
Started May 26 01:56:51 PM PDT 24
Finished May 26 01:56:55 PM PDT 24
Peak memory 217764 kb
Host smart-70a47659-4296-40dd-9883-716c71432381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058399077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.4058399077
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.377384258
Short name T217
Test name
Test status
Simulation time 82317355 ps
CPU time 0.82 seconds
Started May 26 01:56:47 PM PDT 24
Finished May 26 01:56:53 PM PDT 24
Peak memory 200320 kb
Host smart-2e1d1921-3f5e-4c41-8469-6ac73e62e29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377384258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.377384258
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2190832497
Short name T477
Test name
Test status
Simulation time 966664004 ps
CPU time 4.66 seconds
Started May 26 01:56:46 PM PDT 24
Finished May 26 01:56:57 PM PDT 24
Peak memory 200688 kb
Host smart-51fb77fc-211a-4730-a6d9-748fa93670fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190832497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2190832497
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2948107290
Short name T136
Test name
Test status
Simulation time 109791131 ps
CPU time 1.01 seconds
Started May 26 01:56:47 PM PDT 24
Finished May 26 01:56:53 PM PDT 24
Peak memory 200504 kb
Host smart-b0e89457-0469-4546-94e2-c5f5ea2151b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948107290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2948107290
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.158624786
Short name T165
Test name
Test status
Simulation time 194400518 ps
CPU time 1.44 seconds
Started May 26 01:56:47 PM PDT 24
Finished May 26 01:56:54 PM PDT 24
Peak memory 200676 kb
Host smart-26cca8e0-d2dc-4b43-8ab4-9c2017269ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158624786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.158624786
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.710738884
Short name T514
Test name
Test status
Simulation time 7280955333 ps
CPU time 34.25 seconds
Started May 26 01:56:47 PM PDT 24
Finished May 26 01:57:27 PM PDT 24
Peak memory 200836 kb
Host smart-fe0737e9-4a76-49d6-8719-ae52e6fbf098
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710738884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.710738884
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.677973087
Short name T530
Test name
Test status
Simulation time 318944661 ps
CPU time 2.09 seconds
Started May 26 01:56:46 PM PDT 24
Finished May 26 01:56:54 PM PDT 24
Peak memory 200392 kb
Host smart-1d2c0545-6c1f-4514-9d27-56336f663e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677973087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.677973087
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.192778755
Short name T232
Test name
Test status
Simulation time 63572792 ps
CPU time 0.76 seconds
Started May 26 01:56:50 PM PDT 24
Finished May 26 01:56:54 PM PDT 24
Peak memory 200480 kb
Host smart-64891b73-f58f-4917-849f-29b1d376ab15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192778755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.192778755
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.48373806
Short name T480
Test name
Test status
Simulation time 62245938 ps
CPU time 0.79 seconds
Started May 26 01:56:07 PM PDT 24
Finished May 26 01:56:11 PM PDT 24
Peak memory 200320 kb
Host smart-cda9ea34-ce0e-4c98-9a5f-118490638415
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48373806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.48373806
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2846187293
Short name T535
Test name
Test status
Simulation time 1894508807 ps
CPU time 6.95 seconds
Started May 26 01:56:09 PM PDT 24
Finished May 26 01:56:20 PM PDT 24
Peak memory 222212 kb
Host smart-05d98d1f-637d-4389-8ce6-1ce202536c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846187293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2846187293
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.4033702888
Short name T403
Test name
Test status
Simulation time 244372722 ps
CPU time 1.12 seconds
Started May 26 01:56:08 PM PDT 24
Finished May 26 01:56:12 PM PDT 24
Peak memory 217744 kb
Host smart-a4aa74f7-9808-41f8-a0f0-d648d5c3fe59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033702888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.4033702888
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1947931058
Short name T12
Test name
Test status
Simulation time 140368033 ps
CPU time 0.77 seconds
Started May 26 01:56:05 PM PDT 24
Finished May 26 01:56:08 PM PDT 24
Peak memory 200220 kb
Host smart-f14cc90b-c99f-4256-9c39-b9c186c54e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947931058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1947931058
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1645790705
Short name T208
Test name
Test status
Simulation time 1651625798 ps
CPU time 6.18 seconds
Started May 26 01:56:05 PM PDT 24
Finished May 26 01:56:14 PM PDT 24
Peak memory 200664 kb
Host smart-d439ddf2-73ea-4c23-be03-0cf0399facce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645790705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1645790705
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3217428605
Short name T76
Test name
Test status
Simulation time 18610894785 ps
CPU time 28.79 seconds
Started May 26 01:56:04 PM PDT 24
Finished May 26 01:56:34 PM PDT 24
Peak memory 218088 kb
Host smart-c5af7be6-56cc-4b92-93e3-00ec03d16814
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217428605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3217428605
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.224372091
Short name T133
Test name
Test status
Simulation time 110279059 ps
CPU time 1.05 seconds
Started May 26 01:56:07 PM PDT 24
Finished May 26 01:56:12 PM PDT 24
Peak memory 200460 kb
Host smart-60497507-592b-4d3e-89a6-03a79b5f0820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224372091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.224372091
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1617322299
Short name T175
Test name
Test status
Simulation time 224997952 ps
CPU time 1.47 seconds
Started May 26 01:56:08 PM PDT 24
Finished May 26 01:56:14 PM PDT 24
Peak memory 200684 kb
Host smart-a1745a39-f0f6-4212-89ee-97d740e471b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617322299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1617322299
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.2865774662
Short name T428
Test name
Test status
Simulation time 1978347285 ps
CPU time 9.29 seconds
Started May 26 01:56:08 PM PDT 24
Finished May 26 01:56:21 PM PDT 24
Peak memory 200712 kb
Host smart-79a3ec94-1dbf-46d7-9ba6-a84f4a2196c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865774662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2865774662
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.710039241
Short name T231
Test name
Test status
Simulation time 431072330 ps
CPU time 2.56 seconds
Started May 26 01:56:04 PM PDT 24
Finished May 26 01:56:07 PM PDT 24
Peak memory 200436 kb
Host smart-d7a8337f-3542-41c9-aa44-2bdb66e6208b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710039241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.710039241
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2649301773
Short name T23
Test name
Test status
Simulation time 159526456 ps
CPU time 1.24 seconds
Started May 26 01:56:04 PM PDT 24
Finished May 26 01:56:07 PM PDT 24
Peak memory 200528 kb
Host smart-4c13ae82-5949-48d3-94d7-97988b364dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649301773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2649301773
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.4030327751
Short name T358
Test name
Test status
Simulation time 67871161 ps
CPU time 0.81 seconds
Started May 26 01:56:48 PM PDT 24
Finished May 26 01:56:54 PM PDT 24
Peak memory 200324 kb
Host smart-319e7a99-6bec-4673-a628-1da5c6b7cfe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030327751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.4030327751
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.2229672963
Short name T60
Test name
Test status
Simulation time 1889543626 ps
CPU time 8.12 seconds
Started May 26 01:56:47 PM PDT 24
Finished May 26 01:57:01 PM PDT 24
Peak memory 218060 kb
Host smart-403efe75-bde7-4d91-9462-fba0ed97e02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229672963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2229672963
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2630653745
Short name T360
Test name
Test status
Simulation time 244622573 ps
CPU time 1.06 seconds
Started May 26 01:56:47 PM PDT 24
Finished May 26 01:56:53 PM PDT 24
Peak memory 217600 kb
Host smart-57580b5b-0f2f-46a6-a1d9-d80f60f82424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630653745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2630653745
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.894273749
Short name T5
Test name
Test status
Simulation time 161368789 ps
CPU time 0.91 seconds
Started May 26 01:56:47 PM PDT 24
Finished May 26 01:56:54 PM PDT 24
Peak memory 200260 kb
Host smart-554a8b27-4bbb-43f7-96ec-37ae030f0de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894273749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.894273749
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.1731628891
Short name T64
Test name
Test status
Simulation time 821037329 ps
CPU time 4.07 seconds
Started May 26 01:56:47 PM PDT 24
Finished May 26 01:56:57 PM PDT 24
Peak memory 200636 kb
Host smart-36113dfb-fce3-430a-b7d9-c5dc60c13496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731628891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1731628891
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.379158630
Short name T181
Test name
Test status
Simulation time 99736335 ps
CPU time 1 seconds
Started May 26 01:56:48 PM PDT 24
Finished May 26 01:56:54 PM PDT 24
Peak memory 200468 kb
Host smart-ed5f23e9-60e5-43b7-bb5f-2fcf6d46984f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379158630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.379158630
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.36159544
Short name T236
Test name
Test status
Simulation time 255279868 ps
CPU time 1.73 seconds
Started May 26 01:56:46 PM PDT 24
Finished May 26 01:56:54 PM PDT 24
Peak memory 200712 kb
Host smart-cd9be6af-25c6-40d4-9eac-1d831c100b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36159544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.36159544
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.258396545
Short name T318
Test name
Test status
Simulation time 3828277436 ps
CPU time 18.36 seconds
Started May 26 01:56:48 PM PDT 24
Finished May 26 01:57:11 PM PDT 24
Peak memory 208928 kb
Host smart-2ee7f5af-9042-414c-9280-620f76a4f3f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258396545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.258396545
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.1376721620
Short name T516
Test name
Test status
Simulation time 293942386 ps
CPU time 2.04 seconds
Started May 26 01:56:47 PM PDT 24
Finished May 26 01:56:54 PM PDT 24
Peak memory 208696 kb
Host smart-8ac4e376-9dfc-4933-bb19-bf542b3c23d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376721620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1376721620
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1416836534
Short name T268
Test name
Test status
Simulation time 92369536 ps
CPU time 0.84 seconds
Started May 26 01:56:47 PM PDT 24
Finished May 26 01:56:53 PM PDT 24
Peak memory 200500 kb
Host smart-9ccd8f5f-e2cf-40cf-a81c-451ce0ff9634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416836534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1416836534
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.3137984650
Short name T347
Test name
Test status
Simulation time 64526335 ps
CPU time 0.73 seconds
Started May 26 01:56:56 PM PDT 24
Finished May 26 01:56:58 PM PDT 24
Peak memory 200268 kb
Host smart-b6b0e2a7-a053-40eb-8bea-8103b04d6d81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137984650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3137984650
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1455844057
Short name T476
Test name
Test status
Simulation time 2361456662 ps
CPU time 9.34 seconds
Started May 26 01:56:55 PM PDT 24
Finished May 26 01:57:06 PM PDT 24
Peak memory 217388 kb
Host smart-2d619e54-e4f7-47f0-827b-111024432a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455844057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1455844057
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2803426580
Short name T138
Test name
Test status
Simulation time 245068458 ps
CPU time 1.12 seconds
Started May 26 01:56:55 PM PDT 24
Finished May 26 01:56:57 PM PDT 24
Peak memory 217592 kb
Host smart-a49ff56e-99fb-4288-be71-8d62577e5b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803426580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2803426580
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.3639782473
Short name T540
Test name
Test status
Simulation time 129233687 ps
CPU time 0.87 seconds
Started May 26 01:56:49 PM PDT 24
Finished May 26 01:56:54 PM PDT 24
Peak memory 200300 kb
Host smart-a1999cc3-61e3-49ad-9566-0f24414e7ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639782473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3639782473
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1222703
Short name T13
Test name
Test status
Simulation time 1624666030 ps
CPU time 6.25 seconds
Started May 26 01:56:50 PM PDT 24
Finished May 26 01:57:00 PM PDT 24
Peak memory 200872 kb
Host smart-9f03e63f-f8e6-4b43-9467-ddab5e46f8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1222703
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1881260
Short name T372
Test name
Test status
Simulation time 107230159 ps
CPU time 1.14 seconds
Started May 26 01:56:54 PM PDT 24
Finished May 26 01:56:56 PM PDT 24
Peak memory 200536 kb
Host smart-eb38a74f-4263-4132-9ab3-fdf8578d933b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1881260
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3022628890
Short name T143
Test name
Test status
Simulation time 207613354 ps
CPU time 1.33 seconds
Started May 26 01:56:47 PM PDT 24
Finished May 26 01:56:54 PM PDT 24
Peak memory 200640 kb
Host smart-5a02c495-39ac-4c3e-834b-16e26470e2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022628890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3022628890
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3405090877
Short name T59
Test name
Test status
Simulation time 216106246 ps
CPU time 1.46 seconds
Started May 26 01:56:59 PM PDT 24
Finished May 26 01:57:01 PM PDT 24
Peak memory 200316 kb
Host smart-8a891c9c-b85d-4c84-ba2a-96e2d6792686
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405090877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3405090877
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2880117303
Short name T58
Test name
Test status
Simulation time 126772206 ps
CPU time 1.54 seconds
Started May 26 01:56:47 PM PDT 24
Finished May 26 01:56:54 PM PDT 24
Peak memory 208832 kb
Host smart-51c86311-b2c7-4959-96fc-defb962699c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880117303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2880117303
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.4154495728
Short name T8
Test name
Test status
Simulation time 196035716 ps
CPU time 1.21 seconds
Started May 26 01:56:48 PM PDT 24
Finished May 26 01:56:54 PM PDT 24
Peak memory 200484 kb
Host smart-4c156899-bb35-4bae-8a07-b5da14752a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154495728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.4154495728
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2079858677
Short name T342
Test name
Test status
Simulation time 77696432 ps
CPU time 0.81 seconds
Started May 26 01:56:55 PM PDT 24
Finished May 26 01:56:57 PM PDT 24
Peak memory 200316 kb
Host smart-423a3ecf-f9ec-45e8-bcf8-58aaa0a17b36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079858677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2079858677
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1375902614
Short name T481
Test name
Test status
Simulation time 1893585932 ps
CPU time 7.53 seconds
Started May 26 01:56:54 PM PDT 24
Finished May 26 01:57:03 PM PDT 24
Peak memory 217716 kb
Host smart-2b33e6d0-f4d0-447e-b806-7492d8796952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375902614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1375902614
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1611845526
Short name T510
Test name
Test status
Simulation time 244199829 ps
CPU time 1.1 seconds
Started May 26 01:56:56 PM PDT 24
Finished May 26 01:56:58 PM PDT 24
Peak memory 217504 kb
Host smart-eebb2674-ebbe-48fa-877a-3bd0f9075f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611845526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1611845526
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3418780408
Short name T172
Test name
Test status
Simulation time 159581873 ps
CPU time 0.93 seconds
Started May 26 01:56:55 PM PDT 24
Finished May 26 01:56:57 PM PDT 24
Peak memory 200292 kb
Host smart-f8dc2114-d19b-41a5-956c-dd167e8fa8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418780408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3418780408
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.862935539
Short name T40
Test name
Test status
Simulation time 2093331856 ps
CPU time 7.24 seconds
Started May 26 01:56:55 PM PDT 24
Finished May 26 01:57:04 PM PDT 24
Peak memory 200680 kb
Host smart-4fcd47dc-63d9-44b6-a547-557c7849d260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862935539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.862935539
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1154788466
Short name T55
Test name
Test status
Simulation time 155737867 ps
CPU time 1.18 seconds
Started May 26 01:56:54 PM PDT 24
Finished May 26 01:56:57 PM PDT 24
Peak memory 200496 kb
Host smart-1e176624-43d3-4fac-a60a-1fb7a1ca68b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154788466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1154788466
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.3103227699
Short name T199
Test name
Test status
Simulation time 249489879 ps
CPU time 1.53 seconds
Started May 26 01:56:54 PM PDT 24
Finished May 26 01:56:57 PM PDT 24
Peak memory 200680 kb
Host smart-307be2e5-313f-4c00-89ad-6e24ca2c4890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103227699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.3103227699
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.3226882409
Short name T300
Test name
Test status
Simulation time 3254183558 ps
CPU time 14.29 seconds
Started May 26 01:56:55 PM PDT 24
Finished May 26 01:57:11 PM PDT 24
Peak memory 200788 kb
Host smart-7643da0e-3012-440f-9453-15759663752a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226882409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3226882409
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.4269098688
Short name T80
Test name
Test status
Simulation time 334373341 ps
CPU time 2.27 seconds
Started May 26 01:56:54 PM PDT 24
Finished May 26 01:56:57 PM PDT 24
Peak memory 200496 kb
Host smart-8fa73d35-8867-494a-be50-7e102ed73852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269098688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.4269098688
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1823000179
Short name T152
Test name
Test status
Simulation time 70579488 ps
CPU time 0.81 seconds
Started May 26 01:56:53 PM PDT 24
Finished May 26 01:56:56 PM PDT 24
Peak memory 200516 kb
Host smart-e72c7b24-77ba-419a-94dc-8f2709179662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823000179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1823000179
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1880078094
Short name T82
Test name
Test status
Simulation time 66777101 ps
CPU time 0.76 seconds
Started May 26 01:56:53 PM PDT 24
Finished May 26 01:56:56 PM PDT 24
Peak memory 200352 kb
Host smart-efb844e8-832e-4a17-9d65-6b46a1fc2594
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880078094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1880078094
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.1160224902
Short name T499
Test name
Test status
Simulation time 2363499594 ps
CPU time 8.87 seconds
Started May 26 01:56:54 PM PDT 24
Finished May 26 01:57:05 PM PDT 24
Peak memory 218268 kb
Host smart-dd9015c3-93b3-4df7-8d1b-b6c95d40fd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160224902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.1160224902
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2746536584
Short name T473
Test name
Test status
Simulation time 245957117 ps
CPU time 1.03 seconds
Started May 26 01:56:54 PM PDT 24
Finished May 26 01:56:56 PM PDT 24
Peak memory 217752 kb
Host smart-20a747c8-414d-4050-9e13-0c37a3d310bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746536584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2746536584
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2387287563
Short name T173
Test name
Test status
Simulation time 191819802 ps
CPU time 0.87 seconds
Started May 26 01:56:54 PM PDT 24
Finished May 26 01:56:57 PM PDT 24
Peak memory 200292 kb
Host smart-7f347a19-b310-4da5-809e-5c770dfb55b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387287563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2387287563
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.90184386
Short name T405
Test name
Test status
Simulation time 1277629683 ps
CPU time 5.96 seconds
Started May 26 01:56:55 PM PDT 24
Finished May 26 01:57:02 PM PDT 24
Peak memory 200580 kb
Host smart-52990b83-3221-4fee-8bf3-32e0dafb782b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90184386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.90184386
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.880282473
Short name T330
Test name
Test status
Simulation time 138652887 ps
CPU time 1.18 seconds
Started May 26 01:56:54 PM PDT 24
Finished May 26 01:56:56 PM PDT 24
Peak memory 200516 kb
Host smart-0eec323a-6cbc-4651-b231-f00c99c74dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880282473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.880282473
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2431894608
Short name T502
Test name
Test status
Simulation time 242405218 ps
CPU time 1.54 seconds
Started May 26 01:56:54 PM PDT 24
Finished May 26 01:56:57 PM PDT 24
Peak memory 200688 kb
Host smart-d59dd412-991d-46f8-83cd-53e2e100ca65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431894608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2431894608
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2695879008
Short name T446
Test name
Test status
Simulation time 3503521703 ps
CPU time 14.68 seconds
Started May 26 01:56:55 PM PDT 24
Finished May 26 01:57:11 PM PDT 24
Peak memory 209048 kb
Host smart-039b30c4-9fb5-440e-90a9-af51bd85ac28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695879008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2695879008
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.600279062
Short name T538
Test name
Test status
Simulation time 140109693 ps
CPU time 1.86 seconds
Started May 26 01:56:59 PM PDT 24
Finished May 26 01:57:02 PM PDT 24
Peak memory 208704 kb
Host smart-cb95a9a5-ff90-424a-b97d-4444b067509e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600279062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.600279062
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3157171235
Short name T324
Test name
Test status
Simulation time 79450520 ps
CPU time 0.79 seconds
Started May 26 01:56:54 PM PDT 24
Finished May 26 01:56:56 PM PDT 24
Peak memory 200516 kb
Host smart-5ec14875-5bae-45e3-b219-1da03303e5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157171235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3157171235
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.1141303619
Short name T365
Test name
Test status
Simulation time 74329555 ps
CPU time 0.79 seconds
Started May 26 01:57:06 PM PDT 24
Finished May 26 01:57:08 PM PDT 24
Peak memory 200336 kb
Host smart-6688b902-bed7-4eab-9c78-666ad3080224
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141303619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1141303619
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.4167314177
Short name T493
Test name
Test status
Simulation time 1898250082 ps
CPU time 7.11 seconds
Started May 26 01:57:05 PM PDT 24
Finished May 26 01:57:13 PM PDT 24
Peak memory 221652 kb
Host smart-954dfbee-47c3-4039-a3af-2ef726f3837b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167314177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.4167314177
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3262851310
Short name T359
Test name
Test status
Simulation time 245118795 ps
CPU time 1.11 seconds
Started May 26 01:57:06 PM PDT 24
Finished May 26 01:57:08 PM PDT 24
Peak memory 217736 kb
Host smart-530cba72-7e08-41e8-bb5b-d052828e5773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262851310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3262851310
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2492827241
Short name T191
Test name
Test status
Simulation time 203697490 ps
CPU time 1.02 seconds
Started May 26 01:56:54 PM PDT 24
Finished May 26 01:56:56 PM PDT 24
Peak memory 200292 kb
Host smart-85b1bdcc-bf0c-446e-983e-60db0d9da6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492827241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2492827241
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2597598912
Short name T333
Test name
Test status
Simulation time 1246256827 ps
CPU time 5.61 seconds
Started May 26 01:57:05 PM PDT 24
Finished May 26 01:57:11 PM PDT 24
Peak memory 200696 kb
Host smart-52e4f729-3388-487f-898e-402ed015293f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597598912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2597598912
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3781959123
Short name T533
Test name
Test status
Simulation time 153159458 ps
CPU time 1.22 seconds
Started May 26 01:57:05 PM PDT 24
Finished May 26 01:57:08 PM PDT 24
Peak memory 200504 kb
Host smart-26b031eb-a49d-4666-a81d-6a5b7d0cadab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781959123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3781959123
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.520047149
Short name T178
Test name
Test status
Simulation time 247575858 ps
CPU time 1.47 seconds
Started May 26 01:56:59 PM PDT 24
Finished May 26 01:57:01 PM PDT 24
Peak memory 200760 kb
Host smart-c48d6f62-d038-431d-983a-882aa336cf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520047149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.520047149
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3372548297
Short name T534
Test name
Test status
Simulation time 4053321180 ps
CPU time 18.43 seconds
Started May 26 01:57:05 PM PDT 24
Finished May 26 01:57:25 PM PDT 24
Peak memory 200736 kb
Host smart-3e00b8d5-30ed-4968-822a-3461b3e05a8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372548297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3372548297
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1908442861
Short name T361
Test name
Test status
Simulation time 339291909 ps
CPU time 2.25 seconds
Started May 26 01:57:05 PM PDT 24
Finished May 26 01:57:08 PM PDT 24
Peak memory 200504 kb
Host smart-58332aef-23d3-4d1e-a887-4ecb1e1f5481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908442861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1908442861
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3905519402
Short name T174
Test name
Test status
Simulation time 109356529 ps
CPU time 1.02 seconds
Started May 26 01:57:05 PM PDT 24
Finished May 26 01:57:06 PM PDT 24
Peak memory 200512 kb
Host smart-b316acea-5078-4155-9145-6f19cfa43b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905519402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3905519402
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3529770557
Short name T291
Test name
Test status
Simulation time 56608868 ps
CPU time 0.76 seconds
Started May 26 01:57:06 PM PDT 24
Finished May 26 01:57:08 PM PDT 24
Peak memory 200340 kb
Host smart-0909bf80-8d8b-446d-8267-229bb49c3bac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529770557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3529770557
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1994860740
Short name T29
Test name
Test status
Simulation time 2351474022 ps
CPU time 8.72 seconds
Started May 26 01:57:07 PM PDT 24
Finished May 26 01:57:17 PM PDT 24
Peak memory 222312 kb
Host smart-b1eca917-330a-46a7-9541-838c83c3d802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994860740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1994860740
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.4224325865
Short name T162
Test name
Test status
Simulation time 244996159 ps
CPU time 1.04 seconds
Started May 26 01:57:06 PM PDT 24
Finished May 26 01:57:08 PM PDT 24
Peak memory 217612 kb
Host smart-c92b30c9-d429-480c-a749-28c52ffc49d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224325865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.4224325865
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1745655531
Short name T248
Test name
Test status
Simulation time 185740425 ps
CPU time 1 seconds
Started May 26 01:57:08 PM PDT 24
Finished May 26 01:57:10 PM PDT 24
Peak memory 200320 kb
Host smart-48f4219c-77df-428c-9f17-d6dcec66599d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745655531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1745655531
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.2588524766
Short name T97
Test name
Test status
Simulation time 1892465750 ps
CPU time 7.22 seconds
Started May 26 01:57:05 PM PDT 24
Finished May 26 01:57:13 PM PDT 24
Peak memory 200664 kb
Host smart-f995c325-31a5-4dd7-8562-0237ea0b7173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588524766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2588524766
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2263452129
Short name T267
Test name
Test status
Simulation time 178360147 ps
CPU time 1.31 seconds
Started May 26 01:57:05 PM PDT 24
Finished May 26 01:57:07 PM PDT 24
Peak memory 200520 kb
Host smart-0bfa31ce-eba1-4575-af70-085178242ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263452129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2263452129
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.3836088156
Short name T469
Test name
Test status
Simulation time 261619255 ps
CPU time 1.58 seconds
Started May 26 01:57:06 PM PDT 24
Finished May 26 01:57:09 PM PDT 24
Peak memory 200628 kb
Host smart-958ff4ec-28a0-4ba8-bfb7-3319033eff4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836088156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.3836088156
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3373410812
Short name T285
Test name
Test status
Simulation time 1423046294 ps
CPU time 7.3 seconds
Started May 26 01:57:07 PM PDT 24
Finished May 26 01:57:15 PM PDT 24
Peak memory 208880 kb
Host smart-ffd6d18f-8150-4bcb-bfd0-e8687cf2c593
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373410812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3373410812
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3164576110
Short name T193
Test name
Test status
Simulation time 266152214 ps
CPU time 2.08 seconds
Started May 26 01:57:05 PM PDT 24
Finished May 26 01:57:08 PM PDT 24
Peak memory 200504 kb
Host smart-8394c92b-93a3-4a13-a8a7-e0d7b77c989f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164576110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3164576110
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2100331111
Short name T161
Test name
Test status
Simulation time 79165838 ps
CPU time 0.82 seconds
Started May 26 01:57:04 PM PDT 24
Finished May 26 01:57:05 PM PDT 24
Peak memory 200484 kb
Host smart-cf2416db-782f-476b-a073-54b74e721dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100331111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2100331111
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.4260925951
Short name T139
Test name
Test status
Simulation time 65119177 ps
CPU time 0.75 seconds
Started May 26 01:57:15 PM PDT 24
Finished May 26 01:57:16 PM PDT 24
Peak memory 200340 kb
Host smart-ed5622d9-801a-498c-94de-442ff9c29faa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260925951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.4260925951
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2296221819
Short name T44
Test name
Test status
Simulation time 1877120432 ps
CPU time 7.25 seconds
Started May 26 01:57:15 PM PDT 24
Finished May 26 01:57:23 PM PDT 24
Peak memory 218124 kb
Host smart-5de3bc08-e688-4309-86c4-6d81cac11d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296221819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2296221819
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3641161621
Short name T450
Test name
Test status
Simulation time 243870064 ps
CPU time 1.16 seconds
Started May 26 01:57:16 PM PDT 24
Finished May 26 01:57:18 PM PDT 24
Peak memory 217928 kb
Host smart-54d03b88-c7a6-419e-9dfd-fa968fa3b522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641161621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3641161621
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.4043190203
Short name T197
Test name
Test status
Simulation time 145915397 ps
CPU time 0.87 seconds
Started May 26 01:57:06 PM PDT 24
Finished May 26 01:57:08 PM PDT 24
Peak memory 200292 kb
Host smart-7ab42032-5263-4586-9cfd-e76f71a310d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043190203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.4043190203
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3887559507
Short name T392
Test name
Test status
Simulation time 828532722 ps
CPU time 4.56 seconds
Started May 26 01:57:15 PM PDT 24
Finished May 26 01:57:21 PM PDT 24
Peak memory 200696 kb
Host smart-1279aebf-7fc3-4f64-b864-83ff18aa6357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887559507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3887559507
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.4134789687
Short name T517
Test name
Test status
Simulation time 108031295 ps
CPU time 1.07 seconds
Started May 26 01:57:18 PM PDT 24
Finished May 26 01:57:20 PM PDT 24
Peak memory 200284 kb
Host smart-984b340b-7703-433c-9b81-d2e3e7b9f371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134789687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.4134789687
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.841996843
Short name T126
Test name
Test status
Simulation time 254234699 ps
CPU time 1.56 seconds
Started May 26 01:57:06 PM PDT 24
Finished May 26 01:57:08 PM PDT 24
Peak memory 200684 kb
Host smart-47ff6624-d86e-49df-ad33-09792f4312c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841996843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.841996843
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3911270151
Short name T485
Test name
Test status
Simulation time 2529306495 ps
CPU time 8.98 seconds
Started May 26 01:57:14 PM PDT 24
Finished May 26 01:57:23 PM PDT 24
Peak memory 209020 kb
Host smart-d43c667a-9f0c-40a6-a812-8be26d0d7a1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911270151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3911270151
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3277105528
Short name T287
Test name
Test status
Simulation time 117623456 ps
CPU time 1.55 seconds
Started May 26 01:57:20 PM PDT 24
Finished May 26 01:57:22 PM PDT 24
Peak memory 200468 kb
Host smart-8bd29706-cc75-4ede-b750-9eb87aebd1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277105528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3277105528
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2535496988
Short name T532
Test name
Test status
Simulation time 74832078 ps
CPU time 0.82 seconds
Started May 26 01:57:13 PM PDT 24
Finished May 26 01:57:15 PM PDT 24
Peak memory 200672 kb
Host smart-5b98289b-6d1a-425d-80c3-b0b9c76d7c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535496988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2535496988
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.368874761
Short name T235
Test name
Test status
Simulation time 67237632 ps
CPU time 0.78 seconds
Started May 26 01:57:17 PM PDT 24
Finished May 26 01:57:19 PM PDT 24
Peak memory 200344 kb
Host smart-e58a5d91-fe28-452b-b3f2-fa100606671e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368874761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.368874761
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2622659666
Short name T434
Test name
Test status
Simulation time 1224784389 ps
CPU time 6.04 seconds
Started May 26 01:57:17 PM PDT 24
Finished May 26 01:57:23 PM PDT 24
Peak memory 217336 kb
Host smart-b9884d41-fd5a-43a9-a137-7ea7a40791e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622659666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2622659666
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1206069606
Short name T492
Test name
Test status
Simulation time 244733612 ps
CPU time 1.09 seconds
Started May 26 01:57:18 PM PDT 24
Finished May 26 01:57:20 PM PDT 24
Peak memory 217408 kb
Host smart-1490bdba-6bf5-403e-a5d5-f8c83ff32683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206069606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1206069606
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2502342824
Short name T19
Test name
Test status
Simulation time 111288811 ps
CPU time 0.8 seconds
Started May 26 01:57:15 PM PDT 24
Finished May 26 01:57:17 PM PDT 24
Peak memory 200320 kb
Host smart-58f25605-1e4d-426f-9f5f-b0f7ab8ef7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502342824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2502342824
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.635351805
Short name T206
Test name
Test status
Simulation time 1175382435 ps
CPU time 4.51 seconds
Started May 26 01:57:18 PM PDT 24
Finished May 26 01:57:23 PM PDT 24
Peak memory 200744 kb
Host smart-e02b74ce-49d0-4cd0-8e42-44b2d20694be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635351805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.635351805
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3263181799
Short name T487
Test name
Test status
Simulation time 98488879 ps
CPU time 0.98 seconds
Started May 26 01:57:13 PM PDT 24
Finished May 26 01:57:14 PM PDT 24
Peak memory 200468 kb
Host smart-341975b2-f40a-46a8-86fa-fef7bc426a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263181799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3263181799
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2442592687
Short name T325
Test name
Test status
Simulation time 194325096 ps
CPU time 1.37 seconds
Started May 26 01:57:16 PM PDT 24
Finished May 26 01:57:19 PM PDT 24
Peak memory 200652 kb
Host smart-40bd34f4-e21d-4e2a-98ff-337062a000de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442592687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2442592687
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3154683586
Short name T391
Test name
Test status
Simulation time 11171703928 ps
CPU time 39.36 seconds
Started May 26 01:57:15 PM PDT 24
Finished May 26 01:57:56 PM PDT 24
Peak memory 200824 kb
Host smart-ac92d986-83b6-4853-8e9d-0c4d129d5dc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154683586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3154683586
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.784581158
Short name T416
Test name
Test status
Simulation time 462784618 ps
CPU time 2.65 seconds
Started May 26 01:57:15 PM PDT 24
Finished May 26 01:57:19 PM PDT 24
Peak memory 200468 kb
Host smart-e433825c-de46-4174-80eb-eb811afe297e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784581158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.784581158
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2204130651
Short name T295
Test name
Test status
Simulation time 225192526 ps
CPU time 1.42 seconds
Started May 26 01:57:17 PM PDT 24
Finished May 26 01:57:20 PM PDT 24
Peak memory 200684 kb
Host smart-ebabf253-996a-411d-937f-2cd0b1818437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204130651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2204130651
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2797937212
Short name T445
Test name
Test status
Simulation time 54452847 ps
CPU time 0.76 seconds
Started May 26 01:57:14 PM PDT 24
Finished May 26 01:57:16 PM PDT 24
Peak memory 200288 kb
Host smart-201d17d8-25df-4d62-ba03-051fec452515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797937212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2797937212
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.4163100961
Short name T301
Test name
Test status
Simulation time 1224576117 ps
CPU time 5.5 seconds
Started May 26 01:57:14 PM PDT 24
Finished May 26 01:57:21 PM PDT 24
Peak memory 222172 kb
Host smart-292c8571-a847-4445-ac73-c7acee8d5509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163100961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.4163100961
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.741953544
Short name T414
Test name
Test status
Simulation time 243950835 ps
CPU time 1.13 seconds
Started May 26 01:57:17 PM PDT 24
Finished May 26 01:57:19 PM PDT 24
Peak memory 217608 kb
Host smart-171645b8-fd75-49d9-b3f5-a6d6e39367f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741953544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.741953544
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.4234396742
Short name T425
Test name
Test status
Simulation time 103540046 ps
CPU time 0.81 seconds
Started May 26 01:57:14 PM PDT 24
Finished May 26 01:57:16 PM PDT 24
Peak memory 200328 kb
Host smart-aaf4bc9f-0c41-487c-80cc-284f3c5a9b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234396742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.4234396742
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1818573019
Short name T65
Test name
Test status
Simulation time 928457432 ps
CPU time 4.51 seconds
Started May 26 01:57:19 PM PDT 24
Finished May 26 01:57:25 PM PDT 24
Peak memory 200680 kb
Host smart-d2fa4ebe-2cf1-4a73-953e-ef3a56816554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818573019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1818573019
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.123437290
Short name T130
Test name
Test status
Simulation time 175744952 ps
CPU time 1.34 seconds
Started May 26 01:57:16 PM PDT 24
Finished May 26 01:57:18 PM PDT 24
Peak memory 200532 kb
Host smart-122af629-51c7-42db-8a99-45f16b260058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123437290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.123437290
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2940327067
Short name T194
Test name
Test status
Simulation time 129868698 ps
CPU time 1.25 seconds
Started May 26 01:57:14 PM PDT 24
Finished May 26 01:57:15 PM PDT 24
Peak memory 200664 kb
Host smart-6dd79a81-294a-4488-bf1a-f49c60b55c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940327067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2940327067
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3671450439
Short name T85
Test name
Test status
Simulation time 4816191127 ps
CPU time 19.1 seconds
Started May 26 01:57:15 PM PDT 24
Finished May 26 01:57:35 PM PDT 24
Peak memory 209044 kb
Host smart-4aae25af-71ae-46b8-92f0-a8672d7d7812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671450439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3671450439
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1546432581
Short name T427
Test name
Test status
Simulation time 139197191 ps
CPU time 1.89 seconds
Started May 26 01:57:14 PM PDT 24
Finished May 26 01:57:16 PM PDT 24
Peak memory 200476 kb
Host smart-cd7328e2-6dec-49e8-83ae-1981de36f045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546432581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1546432581
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3625204080
Short name T155
Test name
Test status
Simulation time 120581477 ps
CPU time 0.96 seconds
Started May 26 01:57:12 PM PDT 24
Finished May 26 01:57:14 PM PDT 24
Peak memory 200492 kb
Host smart-d4983340-005d-4f4c-8fbf-f963a2a27e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625204080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3625204080
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3104895917
Short name T515
Test name
Test status
Simulation time 59957394 ps
CPU time 0.76 seconds
Started May 26 01:57:18 PM PDT 24
Finished May 26 01:57:20 PM PDT 24
Peak memory 200328 kb
Host smart-b82c612b-92b9-4248-9a81-8ac22f7aee9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104895917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3104895917
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2647294592
Short name T207
Test name
Test status
Simulation time 1220619886 ps
CPU time 5.93 seconds
Started May 26 01:57:16 PM PDT 24
Finished May 26 01:57:23 PM PDT 24
Peak memory 218160 kb
Host smart-63e26ff9-fecf-4b86-a690-69c32795244e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647294592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2647294592
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3396400882
Short name T377
Test name
Test status
Simulation time 245399213 ps
CPU time 1.07 seconds
Started May 26 01:57:17 PM PDT 24
Finished May 26 01:57:19 PM PDT 24
Peak memory 217624 kb
Host smart-710a81bb-1dfe-409e-997b-1696f25252a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396400882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3396400882
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.123984751
Short name T509
Test name
Test status
Simulation time 138408945 ps
CPU time 0.87 seconds
Started May 26 01:57:15 PM PDT 24
Finished May 26 01:57:17 PM PDT 24
Peak memory 200320 kb
Host smart-0b9b9738-589e-42bc-804d-bcbbe97ed1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123984751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.123984751
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.3901806617
Short name T463
Test name
Test status
Simulation time 1359907681 ps
CPU time 5.45 seconds
Started May 26 01:57:15 PM PDT 24
Finished May 26 01:57:22 PM PDT 24
Peak memory 200648 kb
Host smart-be6d9d85-06af-4fe8-8451-21b7efff8ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901806617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3901806617
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.976132668
Short name T146
Test name
Test status
Simulation time 103112627 ps
CPU time 1.11 seconds
Started May 26 01:57:17 PM PDT 24
Finished May 26 01:57:20 PM PDT 24
Peak memory 200436 kb
Host smart-ce0c418c-496d-42f0-b867-d0e309695925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976132668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.976132668
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2981919793
Short name T204
Test name
Test status
Simulation time 112499757 ps
CPU time 1.24 seconds
Started May 26 01:57:16 PM PDT 24
Finished May 26 01:57:19 PM PDT 24
Peak memory 200652 kb
Host smart-aa1383b4-9287-4d36-a1c8-09d829060429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981919793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2981919793
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.3643271907
Short name T424
Test name
Test status
Simulation time 12517216652 ps
CPU time 45.51 seconds
Started May 26 01:57:19 PM PDT 24
Finished May 26 01:58:06 PM PDT 24
Peak memory 200872 kb
Host smart-4707d60e-5e03-4eac-80b1-29f8238f8c14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643271907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.3643271907
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2572088226
Short name T467
Test name
Test status
Simulation time 329369639 ps
CPU time 2.21 seconds
Started May 26 01:57:15 PM PDT 24
Finished May 26 01:57:18 PM PDT 24
Peak memory 200176 kb
Host smart-3d97a4a2-7da5-45df-94e7-aa7cf5ad6247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572088226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2572088226
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1946398614
Short name T367
Test name
Test status
Simulation time 160869725 ps
CPU time 1.15 seconds
Started May 26 01:57:15 PM PDT 24
Finished May 26 01:57:17 PM PDT 24
Peak memory 200132 kb
Host smart-468ff846-0f78-486b-b13d-85455ab7a225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946398614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1946398614
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2329876417
Short name T437
Test name
Test status
Simulation time 83614820 ps
CPU time 0.8 seconds
Started May 26 01:56:06 PM PDT 24
Finished May 26 01:56:09 PM PDT 24
Peak memory 200500 kb
Host smart-c88771cd-b639-4880-8b49-88e42b090840
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329876417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2329876417
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1748571732
Short name T526
Test name
Test status
Simulation time 1889336538 ps
CPU time 8.01 seconds
Started May 26 01:56:08 PM PDT 24
Finished May 26 01:56:19 PM PDT 24
Peak memory 217112 kb
Host smart-4c51018e-1c42-44ba-acbd-cf35ddd3ead0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748571732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1748571732
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3023868742
Short name T429
Test name
Test status
Simulation time 244277645 ps
CPU time 1.07 seconds
Started May 26 01:56:05 PM PDT 24
Finished May 26 01:56:08 PM PDT 24
Peak memory 217756 kb
Host smart-f02be736-c8c9-4c03-ad15-354fef77afb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023868742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3023868742
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1482112574
Short name T448
Test name
Test status
Simulation time 109653645 ps
CPU time 0.88 seconds
Started May 26 01:56:06 PM PDT 24
Finished May 26 01:56:09 PM PDT 24
Peak memory 200276 kb
Host smart-97176486-2cb7-4179-9aab-baa28693a310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482112574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1482112574
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1653547924
Short name T14
Test name
Test status
Simulation time 1442257780 ps
CPU time 5.67 seconds
Started May 26 01:56:06 PM PDT 24
Finished May 26 01:56:15 PM PDT 24
Peak memory 200640 kb
Host smart-2e2eb845-ea38-4737-92dc-cb33acf29aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653547924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1653547924
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1939493114
Short name T275
Test name
Test status
Simulation time 186947009 ps
CPU time 1.26 seconds
Started May 26 01:56:06 PM PDT 24
Finished May 26 01:56:11 PM PDT 24
Peak memory 200464 kb
Host smart-1a18ff8b-90b4-4798-9804-25391381197c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939493114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1939493114
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.38427065
Short name T251
Test name
Test status
Simulation time 264997239 ps
CPU time 1.6 seconds
Started May 26 01:56:07 PM PDT 24
Finished May 26 01:56:12 PM PDT 24
Peak memory 200676 kb
Host smart-e28e7df6-eeb6-48f6-b03c-4e52f97cc63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38427065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.38427065
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2881669651
Short name T261
Test name
Test status
Simulation time 1628172620 ps
CPU time 6.6 seconds
Started May 26 01:56:08 PM PDT 24
Finished May 26 01:56:18 PM PDT 24
Peak memory 200704 kb
Host smart-b091ffed-2155-440c-8023-d582045f4be0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881669651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2881669651
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3399218850
Short name T200
Test name
Test status
Simulation time 134161496 ps
CPU time 1.77 seconds
Started May 26 01:56:06 PM PDT 24
Finished May 26 01:56:10 PM PDT 24
Peak memory 208644 kb
Host smart-21e08768-029b-4356-a449-5c0498a59874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399218850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3399218850
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2184162294
Short name T491
Test name
Test status
Simulation time 141450735 ps
CPU time 1.06 seconds
Started May 26 01:56:09 PM PDT 24
Finished May 26 01:56:14 PM PDT 24
Peak memory 200516 kb
Host smart-5f08ce3d-4a0f-4385-aa75-58b8b0e6e83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184162294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2184162294
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3380984119
Short name T223
Test name
Test status
Simulation time 68533272 ps
CPU time 0.75 seconds
Started May 26 01:57:25 PM PDT 24
Finished May 26 01:57:27 PM PDT 24
Peak memory 200244 kb
Host smart-611ceffd-7aa8-43ce-a55a-172d31940edc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380984119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3380984119
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2950303569
Short name T354
Test name
Test status
Simulation time 2358094642 ps
CPU time 8.26 seconds
Started May 26 01:57:22 PM PDT 24
Finished May 26 01:57:32 PM PDT 24
Peak memory 218260 kb
Host smart-b262a579-3977-40b8-a204-62bb4571f291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950303569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2950303569
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3046479227
Short name T441
Test name
Test status
Simulation time 245653683 ps
CPU time 1.04 seconds
Started May 26 01:57:22 PM PDT 24
Finished May 26 01:57:24 PM PDT 24
Peak memory 217840 kb
Host smart-1f0d34ea-5cac-43b8-8cc5-ff09d9c18828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046479227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3046479227
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.767211600
Short name T368
Test name
Test status
Simulation time 229533329 ps
CPU time 0.94 seconds
Started May 26 01:57:17 PM PDT 24
Finished May 26 01:57:19 PM PDT 24
Peak memory 200220 kb
Host smart-d579b70c-9f57-4fe3-ad5c-547d7ede0430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767211600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.767211600
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.4147558137
Short name T79
Test name
Test status
Simulation time 1697554041 ps
CPU time 6.84 seconds
Started May 26 01:57:22 PM PDT 24
Finished May 26 01:57:30 PM PDT 24
Peak memory 200668 kb
Host smart-9427f923-d246-4522-8381-b29c968d7732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147558137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.4147558137
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2178398677
Short name T512
Test name
Test status
Simulation time 151694780 ps
CPU time 1.22 seconds
Started May 26 01:57:27 PM PDT 24
Finished May 26 01:57:30 PM PDT 24
Peak memory 200504 kb
Host smart-f31766eb-af03-4190-9b66-7f6b5374f98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178398677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2178398677
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2581324897
Short name T440
Test name
Test status
Simulation time 206818741 ps
CPU time 1.35 seconds
Started May 26 01:57:13 PM PDT 24
Finished May 26 01:57:15 PM PDT 24
Peak memory 200740 kb
Host smart-9ddc1756-4d13-4600-a4cc-dddfca8f6609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581324897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2581324897
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3628846761
Short name T366
Test name
Test status
Simulation time 2778426237 ps
CPU time 10.21 seconds
Started May 26 01:57:21 PM PDT 24
Finished May 26 01:57:33 PM PDT 24
Peak memory 200824 kb
Host smart-941a9fb7-ced2-4449-944d-fec23ad1ca10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628846761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3628846761
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.1379956411
Short name T203
Test name
Test status
Simulation time 381615507 ps
CPU time 2.47 seconds
Started May 26 01:57:25 PM PDT 24
Finished May 26 01:57:29 PM PDT 24
Peak memory 200496 kb
Host smart-bcf80007-ddba-4cc6-9f6a-a44ff211e24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379956411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.1379956411
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.4245486111
Short name T245
Test name
Test status
Simulation time 170327888 ps
CPU time 1.25 seconds
Started May 26 01:57:21 PM PDT 24
Finished May 26 01:57:24 PM PDT 24
Peak memory 200460 kb
Host smart-d3df5160-c143-41bd-abe4-4992e2c6e500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245486111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.4245486111
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3882900260
Short name T337
Test name
Test status
Simulation time 84238513 ps
CPU time 0.85 seconds
Started May 26 01:57:25 PM PDT 24
Finished May 26 01:57:28 PM PDT 24
Peak memory 200344 kb
Host smart-27b185b3-2933-4e71-aa0f-2e2b97db3574
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882900260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3882900260
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2338779277
Short name T195
Test name
Test status
Simulation time 244665659 ps
CPU time 1.05 seconds
Started May 26 01:57:23 PM PDT 24
Finished May 26 01:57:25 PM PDT 24
Peak memory 217688 kb
Host smart-6198d49d-864b-43cf-b16d-180d126edc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338779277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2338779277
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1917523975
Short name T433
Test name
Test status
Simulation time 139569993 ps
CPU time 0.89 seconds
Started May 26 01:57:26 PM PDT 24
Finished May 26 01:57:29 PM PDT 24
Peak memory 200324 kb
Host smart-00c03fe4-30ef-4200-afa5-e7f15ece9a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917523975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1917523975
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3160840512
Short name T494
Test name
Test status
Simulation time 2122008053 ps
CPU time 8.2 seconds
Started May 26 01:57:23 PM PDT 24
Finished May 26 01:57:33 PM PDT 24
Peak memory 200676 kb
Host smart-baf3c89f-119f-42ca-af67-c8df409f5741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160840512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3160840512
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3538387967
Short name T56
Test name
Test status
Simulation time 168083252 ps
CPU time 1.16 seconds
Started May 26 01:57:20 PM PDT 24
Finished May 26 01:57:22 PM PDT 24
Peak memory 200504 kb
Host smart-4aa54a1a-098e-4000-9c86-497ada9d1a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538387967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3538387967
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2717397820
Short name T271
Test name
Test status
Simulation time 249783807 ps
CPU time 1.59 seconds
Started May 26 01:57:25 PM PDT 24
Finished May 26 01:57:29 PM PDT 24
Peak memory 200588 kb
Host smart-ca95730e-be11-471a-bccd-b752baecad77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717397820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2717397820
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.329872748
Short name T156
Test name
Test status
Simulation time 2853684276 ps
CPU time 10.99 seconds
Started May 26 01:57:21 PM PDT 24
Finished May 26 01:57:34 PM PDT 24
Peak memory 200624 kb
Host smart-82c1d216-8bd2-4a50-bab6-d275e252f981
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329872748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.329872748
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2100221854
Short name T84
Test name
Test status
Simulation time 122496002 ps
CPU time 1.58 seconds
Started May 26 01:57:20 PM PDT 24
Finished May 26 01:57:22 PM PDT 24
Peak memory 200536 kb
Host smart-f4a3ac2f-6215-41f5-8caf-44513124b8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100221854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2100221854
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3786602050
Short name T3
Test name
Test status
Simulation time 127025047 ps
CPU time 1.01 seconds
Started May 26 01:57:23 PM PDT 24
Finished May 26 01:57:25 PM PDT 24
Peak memory 200500 kb
Host smart-156e502d-0cfe-4793-99fc-e9f94caae8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786602050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3786602050
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.74451347
Short name T38
Test name
Test status
Simulation time 80330889 ps
CPU time 0.85 seconds
Started May 26 01:57:21 PM PDT 24
Finished May 26 01:57:23 PM PDT 24
Peak memory 200328 kb
Host smart-ac45179d-0369-4a2c-956a-12e76c7d8192
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74451347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.74451347
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2430591078
Short name T49
Test name
Test status
Simulation time 2173706448 ps
CPU time 7.63 seconds
Started May 26 01:57:25 PM PDT 24
Finished May 26 01:57:35 PM PDT 24
Peak memory 222200 kb
Host smart-388afbee-bf5f-4d39-a0a5-2b2cfa3a6bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430591078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2430591078
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.3251768329
Short name T483
Test name
Test status
Simulation time 244364815 ps
CPU time 1.04 seconds
Started May 26 01:57:25 PM PDT 24
Finished May 26 01:57:28 PM PDT 24
Peak memory 217572 kb
Host smart-cd2b5dfe-c751-4aba-999c-af6f62e141d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251768329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.3251768329
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.478632463
Short name T412
Test name
Test status
Simulation time 103149460 ps
CPU time 0.77 seconds
Started May 26 01:57:24 PM PDT 24
Finished May 26 01:57:27 PM PDT 24
Peak memory 200336 kb
Host smart-c7329253-f226-4df3-a349-57a63ed0f937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478632463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.478632463
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1397448661
Short name T202
Test name
Test status
Simulation time 1111128029 ps
CPU time 5.54 seconds
Started May 26 01:57:24 PM PDT 24
Finished May 26 01:57:32 PM PDT 24
Peak memory 200676 kb
Host smart-126ebf9c-cba1-4839-b069-3f29b455baf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397448661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1397448661
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3140223683
Short name T331
Test name
Test status
Simulation time 94108778 ps
CPU time 1.03 seconds
Started May 26 01:57:28 PM PDT 24
Finished May 26 01:57:30 PM PDT 24
Peak memory 200500 kb
Host smart-70611449-9a13-4974-9fd4-7c1e30f9124d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140223683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3140223683
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2987462105
Short name T61
Test name
Test status
Simulation time 113701007 ps
CPU time 1.18 seconds
Started May 26 01:57:22 PM PDT 24
Finished May 26 01:57:25 PM PDT 24
Peak memory 200676 kb
Host smart-fdf5321b-6730-4901-a9e9-bf510b713835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987462105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2987462105
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1599123711
Short name T455
Test name
Test status
Simulation time 4740444019 ps
CPU time 17.07 seconds
Started May 26 01:57:23 PM PDT 24
Finished May 26 01:57:42 PM PDT 24
Peak memory 209000 kb
Host smart-c1bebe6b-ce52-463b-bd5f-4d4e040163eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599123711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1599123711
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3090680135
Short name T317
Test name
Test status
Simulation time 347780993 ps
CPU time 2.25 seconds
Started May 26 01:57:22 PM PDT 24
Finished May 26 01:57:26 PM PDT 24
Peak memory 200508 kb
Host smart-03449706-872d-4fe3-82c8-78ff5c5eb3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090680135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3090680135
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3480715825
Short name T51
Test name
Test status
Simulation time 54282266 ps
CPU time 0.73 seconds
Started May 26 01:57:23 PM PDT 24
Finished May 26 01:57:25 PM PDT 24
Peak memory 200328 kb
Host smart-2a042d08-43e7-4dc7-9525-d015b1709e51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480715825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3480715825
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.229417619
Short name T213
Test name
Test status
Simulation time 1222241449 ps
CPU time 6 seconds
Started May 26 01:57:23 PM PDT 24
Finished May 26 01:57:30 PM PDT 24
Peak memory 218144 kb
Host smart-a442dc0c-88c8-4767-8cde-cfb4b41646fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229417619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.229417619
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.548468531
Short name T302
Test name
Test status
Simulation time 244023981 ps
CPU time 1.11 seconds
Started May 26 01:57:22 PM PDT 24
Finished May 26 01:57:24 PM PDT 24
Peak memory 217648 kb
Host smart-7b53b00b-805e-44c8-b3bd-0007218a1c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548468531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.548468531
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2176074301
Short name T350
Test name
Test status
Simulation time 126531069 ps
CPU time 0.79 seconds
Started May 26 01:57:25 PM PDT 24
Finished May 26 01:57:28 PM PDT 24
Peak memory 200292 kb
Host smart-7446e1c1-e3e8-4ab4-9490-7ee036e6a2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176074301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2176074301
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2458085406
Short name T149
Test name
Test status
Simulation time 1560790681 ps
CPU time 6.74 seconds
Started May 26 01:57:26 PM PDT 24
Finished May 26 01:57:34 PM PDT 24
Peak memory 200700 kb
Host smart-781c0a2a-4d57-4991-bf57-725e07463567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458085406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2458085406
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3228812608
Short name T150
Test name
Test status
Simulation time 149398196 ps
CPU time 1.11 seconds
Started May 26 01:57:26 PM PDT 24
Finished May 26 01:57:29 PM PDT 24
Peak memory 200512 kb
Host smart-24bddb51-56d0-46cf-8908-07c63216237e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228812608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3228812608
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1170221488
Short name T471
Test name
Test status
Simulation time 115574352 ps
CPU time 1.23 seconds
Started May 26 01:57:29 PM PDT 24
Finished May 26 01:57:33 PM PDT 24
Peak memory 200700 kb
Host smart-5adaec8b-e3be-46d0-bdb7-e9c37c01871f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170221488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1170221488
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1797162253
Short name T239
Test name
Test status
Simulation time 6914215081 ps
CPU time 28.58 seconds
Started May 26 01:57:27 PM PDT 24
Finished May 26 01:57:58 PM PDT 24
Peak memory 200840 kb
Host smart-9db3dace-545f-4d0a-9fa6-1bd0c35a7742
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797162253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1797162253
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.2908761217
Short name T353
Test name
Test status
Simulation time 359076321 ps
CPU time 2.18 seconds
Started May 26 01:57:22 PM PDT 24
Finished May 26 01:57:25 PM PDT 24
Peak memory 200364 kb
Host smart-7065c00d-60d7-457b-a764-59dab0f187f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908761217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2908761217
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.4045320494
Short name T183
Test name
Test status
Simulation time 143664628 ps
CPU time 1.13 seconds
Started May 26 01:57:23 PM PDT 24
Finished May 26 01:57:26 PM PDT 24
Peak memory 200216 kb
Host smart-917416ef-38b6-467d-994f-770adcb684e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045320494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.4045320494
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1889746430
Short name T137
Test name
Test status
Simulation time 66915567 ps
CPU time 0.79 seconds
Started May 26 01:57:29 PM PDT 24
Finished May 26 01:57:32 PM PDT 24
Peak memory 200356 kb
Host smart-68ee1736-2e6e-4aef-8de8-2f7af885ad06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889746430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1889746430
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1782638343
Short name T25
Test name
Test status
Simulation time 2169623306 ps
CPU time 7.94 seconds
Started May 26 01:57:29 PM PDT 24
Finished May 26 01:57:40 PM PDT 24
Peak memory 218268 kb
Host smart-79450f52-bb68-4e56-834e-f7f9bd81b79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782638343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1782638343
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.498346694
Short name T151
Test name
Test status
Simulation time 245124838 ps
CPU time 1.08 seconds
Started May 26 01:57:25 PM PDT 24
Finished May 26 01:57:28 PM PDT 24
Peak memory 217848 kb
Host smart-e1a2f2e6-79cd-43a4-9911-6183ddd3a3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498346694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.498346694
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2066325076
Short name T17
Test name
Test status
Simulation time 193612168 ps
CPU time 0.93 seconds
Started May 26 01:57:23 PM PDT 24
Finished May 26 01:57:25 PM PDT 24
Peak memory 200304 kb
Host smart-78657dd9-ace8-4d9a-bca5-684b4fc97c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066325076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2066325076
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.4039129879
Short name T382
Test name
Test status
Simulation time 1969090611 ps
CPU time 7.62 seconds
Started May 26 01:57:24 PM PDT 24
Finished May 26 01:57:33 PM PDT 24
Peak memory 200668 kb
Host smart-eeed3eb5-cb6e-4702-8600-85881cee8719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039129879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.4039129879
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1585868804
Short name T355
Test name
Test status
Simulation time 126901930 ps
CPU time 1.24 seconds
Started May 26 01:57:29 PM PDT 24
Finished May 26 01:57:33 PM PDT 24
Peak memory 200700 kb
Host smart-2ae58846-f9f8-4b21-b788-cc9e44f8f0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585868804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1585868804
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.36491394
Short name T421
Test name
Test status
Simulation time 2518749655 ps
CPU time 11.66 seconds
Started May 26 01:57:29 PM PDT 24
Finished May 26 01:57:44 PM PDT 24
Peak memory 200840 kb
Host smart-3a2c5755-12ad-4bb3-ac9f-ef7bb8a7196d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36491394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.36491394
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3644987435
Short name T53
Test name
Test status
Simulation time 120658953 ps
CPU time 1.65 seconds
Started May 26 01:57:21 PM PDT 24
Finished May 26 01:57:23 PM PDT 24
Peak memory 208692 kb
Host smart-6ad030b1-9f21-4ca2-8350-c00c45977d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644987435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3644987435
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.155677989
Short name T349
Test name
Test status
Simulation time 172910950 ps
CPU time 1.29 seconds
Started May 26 01:57:26 PM PDT 24
Finished May 26 01:57:29 PM PDT 24
Peak memory 200720 kb
Host smart-1a1ae5de-0b05-447c-86cf-6ee3418742e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155677989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.155677989
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.1405416018
Short name T439
Test name
Test status
Simulation time 87609932 ps
CPU time 0.88 seconds
Started May 26 01:57:23 PM PDT 24
Finished May 26 01:57:25 PM PDT 24
Peak memory 200280 kb
Host smart-43cde95f-39ed-4c75-a942-f4df2c610488
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405416018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1405416018
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2898309647
Short name T187
Test name
Test status
Simulation time 243690914 ps
CPU time 1.11 seconds
Started May 26 01:57:27 PM PDT 24
Finished May 26 01:57:30 PM PDT 24
Peak memory 217572 kb
Host smart-fa059dcc-1893-4875-b09c-b0a9713516ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898309647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2898309647
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.307690695
Short name T20
Test name
Test status
Simulation time 192742605 ps
CPU time 0.9 seconds
Started May 26 01:57:23 PM PDT 24
Finished May 26 01:57:26 PM PDT 24
Peak memory 200240 kb
Host smart-7d5695dd-570a-4956-a811-6e722ab07901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307690695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.307690695
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.822247913
Short name T54
Test name
Test status
Simulation time 1331131917 ps
CPU time 5.53 seconds
Started May 26 01:57:25 PM PDT 24
Finished May 26 01:57:32 PM PDT 24
Peak memory 200696 kb
Host smart-369c1dc5-a00d-46a0-9db2-3205fb5b6bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822247913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.822247913
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2089129842
Short name T222
Test name
Test status
Simulation time 178397534 ps
CPU time 1.19 seconds
Started May 26 01:57:28 PM PDT 24
Finished May 26 01:57:31 PM PDT 24
Peak memory 200504 kb
Host smart-3df8a06d-2841-40a4-a5f8-b0e1a05fa26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089129842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2089129842
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2431398609
Short name T192
Test name
Test status
Simulation time 247742237 ps
CPU time 1.49 seconds
Started May 26 01:57:28 PM PDT 24
Finished May 26 01:57:32 PM PDT 24
Peak memory 200688 kb
Host smart-20447b7e-38d3-441b-97ff-c00f51dc9d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431398609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2431398609
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.2208017632
Short name T310
Test name
Test status
Simulation time 3598430084 ps
CPU time 14.59 seconds
Started May 26 01:57:26 PM PDT 24
Finished May 26 01:57:42 PM PDT 24
Peak memory 210064 kb
Host smart-1db55c3e-692f-48f0-b810-0526fcb2af4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208017632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2208017632
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1949805365
Short name T253
Test name
Test status
Simulation time 347068467 ps
CPU time 2.2 seconds
Started May 26 01:57:22 PM PDT 24
Finished May 26 01:57:25 PM PDT 24
Peak memory 200376 kb
Host smart-81ce1a7f-156d-4350-a0e1-ec3ce15dc67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949805365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1949805365
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3234727538
Short name T395
Test name
Test status
Simulation time 64442200 ps
CPU time 0.76 seconds
Started May 26 01:57:22 PM PDT 24
Finished May 26 01:57:24 PM PDT 24
Peak memory 200460 kb
Host smart-0a293c88-46b5-4ad7-83f9-506c2d1ab738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234727538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3234727538
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2330494359
Short name T273
Test name
Test status
Simulation time 78485802 ps
CPU time 0.8 seconds
Started May 26 01:57:27 PM PDT 24
Finished May 26 01:57:30 PM PDT 24
Peak memory 200340 kb
Host smart-ef1b2449-5f00-45d7-9449-ba74d5610e1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330494359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2330494359
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1519255817
Short name T387
Test name
Test status
Simulation time 1219587537 ps
CPU time 5.36 seconds
Started May 26 01:57:23 PM PDT 24
Finished May 26 01:57:30 PM PDT 24
Peak memory 221400 kb
Host smart-0eed246d-f1f6-4520-91d3-68563db73b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519255817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1519255817
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.480130807
Short name T351
Test name
Test status
Simulation time 244203120 ps
CPU time 1.16 seconds
Started May 26 01:57:25 PM PDT 24
Finished May 26 01:57:28 PM PDT 24
Peak memory 217748 kb
Host smart-d8544d6c-37e1-4d10-8882-6fe5b75c739b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480130807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.480130807
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.739622103
Short name T386
Test name
Test status
Simulation time 94952886 ps
CPU time 0.76 seconds
Started May 26 01:57:23 PM PDT 24
Finished May 26 01:57:25 PM PDT 24
Peak memory 200272 kb
Host smart-da6ba22d-3a9a-44b8-9a9a-7db72af03798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739622103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.739622103
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2001622545
Short name T286
Test name
Test status
Simulation time 1676999353 ps
CPU time 6.25 seconds
Started May 26 01:57:27 PM PDT 24
Finished May 26 01:57:35 PM PDT 24
Peak memory 200672 kb
Host smart-51c2e6d7-19cf-48d6-98a6-8b15c161faf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001622545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2001622545
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1179902298
Short name T263
Test name
Test status
Simulation time 98197332 ps
CPU time 0.98 seconds
Started May 26 01:57:29 PM PDT 24
Finished May 26 01:57:33 PM PDT 24
Peak memory 200516 kb
Host smart-e663f692-342e-43db-89cc-9ff65a538dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179902298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1179902298
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1214868257
Short name T35
Test name
Test status
Simulation time 195913852 ps
CPU time 1.48 seconds
Started May 26 01:57:29 PM PDT 24
Finished May 26 01:57:33 PM PDT 24
Peak memory 200740 kb
Host smart-24e31153-fd41-433e-a24e-39dbbc7e2431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214868257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1214868257
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.4038557783
Short name T190
Test name
Test status
Simulation time 5406316073 ps
CPU time 24.01 seconds
Started May 26 01:57:26 PM PDT 24
Finished May 26 01:57:52 PM PDT 24
Peak memory 200856 kb
Host smart-97a4722a-18f9-4186-9210-8abd10b2f306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038557783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.4038557783
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3000957017
Short name T396
Test name
Test status
Simulation time 148526281 ps
CPU time 1.83 seconds
Started May 26 01:57:24 PM PDT 24
Finished May 26 01:57:28 PM PDT 24
Peak memory 200448 kb
Host smart-9869a67b-a170-4a9d-86f6-eb97f9c372b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000957017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3000957017
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.3229047597
Short name T144
Test name
Test status
Simulation time 126578513 ps
CPU time 1.14 seconds
Started May 26 01:57:27 PM PDT 24
Finished May 26 01:57:30 PM PDT 24
Peak memory 200504 kb
Host smart-bb01c513-05bf-48df-8377-ba79af98b241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229047597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.3229047597
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1216536985
Short name T265
Test name
Test status
Simulation time 52818946 ps
CPU time 0.79 seconds
Started May 26 01:57:29 PM PDT 24
Finished May 26 01:57:32 PM PDT 24
Peak memory 200312 kb
Host smart-b9faa953-770f-4ddc-bb90-6aece9b8077c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216536985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1216536985
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.30106855
Short name T528
Test name
Test status
Simulation time 1224822685 ps
CPU time 5.53 seconds
Started May 26 01:57:28 PM PDT 24
Finished May 26 01:57:36 PM PDT 24
Peak memory 222184 kb
Host smart-2040f693-d05b-4ceb-b878-d1b64b9ca1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30106855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.30106855
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3028644536
Short name T410
Test name
Test status
Simulation time 243572433 ps
CPU time 1.14 seconds
Started May 26 01:57:28 PM PDT 24
Finished May 26 01:57:31 PM PDT 24
Peak memory 217532 kb
Host smart-ed70c30f-6ce4-420c-a74c-a5a3ecf6b0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028644536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3028644536
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2708208440
Short name T294
Test name
Test status
Simulation time 166457852 ps
CPU time 0.87 seconds
Started May 26 01:57:29 PM PDT 24
Finished May 26 01:57:33 PM PDT 24
Peak memory 200308 kb
Host smart-4acb859c-581b-4bd0-9a35-9a3f04622b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708208440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2708208440
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.283157318
Short name T501
Test name
Test status
Simulation time 1405839429 ps
CPU time 5.34 seconds
Started May 26 01:57:24 PM PDT 24
Finished May 26 01:57:31 PM PDT 24
Peak memory 200720 kb
Host smart-8d96e42e-4215-427d-aab9-8dfca1c01d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283157318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.283157318
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1225681647
Short name T131
Test name
Test status
Simulation time 170860996 ps
CPU time 1.13 seconds
Started May 26 01:57:27 PM PDT 24
Finished May 26 01:57:30 PM PDT 24
Peak memory 200472 kb
Host smart-a94ee1e2-3377-4fd9-a38e-82b0b1a706da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225681647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1225681647
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.446233108
Short name T179
Test name
Test status
Simulation time 114496744 ps
CPU time 1.21 seconds
Started May 26 01:57:26 PM PDT 24
Finished May 26 01:57:29 PM PDT 24
Peak memory 200696 kb
Host smart-feb5d46d-3fc4-4d3f-b846-f85b3a0e6d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446233108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.446233108
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2701866034
Short name T37
Test name
Test status
Simulation time 7959966488 ps
CPU time 31.9 seconds
Started May 26 01:57:29 PM PDT 24
Finished May 26 01:58:03 PM PDT 24
Peak memory 200816 kb
Host smart-69f87467-3c15-4d30-a65d-74d96d3003dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701866034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2701866034
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3929219882
Short name T176
Test name
Test status
Simulation time 148899764 ps
CPU time 1.97 seconds
Started May 26 01:57:29 PM PDT 24
Finished May 26 01:57:33 PM PDT 24
Peak memory 200072 kb
Host smart-3dba4a3e-909f-462b-b144-a89c19a84c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929219882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3929219882
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.4059535232
Short name T373
Test name
Test status
Simulation time 89956698 ps
CPU time 0.93 seconds
Started May 26 01:57:28 PM PDT 24
Finished May 26 01:57:32 PM PDT 24
Peak memory 200440 kb
Host smart-a2d680c8-d09c-4f4b-a1dd-88de3c942efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059535232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.4059535232
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3977230781
Short name T452
Test name
Test status
Simulation time 127451093 ps
CPU time 0.93 seconds
Started May 26 01:57:30 PM PDT 24
Finished May 26 01:57:34 PM PDT 24
Peak memory 200224 kb
Host smart-f7a1967a-80a9-4659-8f13-1984be6fd675
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977230781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3977230781
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2325462739
Short name T50
Test name
Test status
Simulation time 1231964178 ps
CPU time 6.48 seconds
Started May 26 01:57:24 PM PDT 24
Finished May 26 01:57:33 PM PDT 24
Peak memory 218144 kb
Host smart-0d692b57-fdcd-4ffc-a798-10ecc74133ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325462739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2325462739
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.949593231
Short name T348
Test name
Test status
Simulation time 244772778 ps
CPU time 1.06 seconds
Started May 26 01:57:28 PM PDT 24
Finished May 26 01:57:31 PM PDT 24
Peak memory 217736 kb
Host smart-f655ce37-7861-40be-bb39-7b11cab7d0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949593231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.949593231
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3204241455
Short name T537
Test name
Test status
Simulation time 184736396 ps
CPU time 0.92 seconds
Started May 26 01:57:21 PM PDT 24
Finished May 26 01:57:23 PM PDT 24
Peak memory 200296 kb
Host smart-f68a0156-1237-4fc5-929d-1dea1ab9c3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204241455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3204241455
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3638906518
Short name T388
Test name
Test status
Simulation time 1350498770 ps
CPU time 5.74 seconds
Started May 26 01:57:23 PM PDT 24
Finished May 26 01:57:30 PM PDT 24
Peak memory 200744 kb
Host smart-23d8a546-da47-46cf-8f6c-2365ceec96e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638906518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3638906518
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.165837494
Short name T218
Test name
Test status
Simulation time 108114847 ps
CPU time 1.02 seconds
Started May 26 01:57:26 PM PDT 24
Finished May 26 01:57:29 PM PDT 24
Peak memory 200488 kb
Host smart-3375d56e-773f-4bfb-8b12-df8b89210e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165837494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.165837494
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3781031278
Short name T205
Test name
Test status
Simulation time 199109443 ps
CPU time 1.37 seconds
Started May 26 01:57:28 PM PDT 24
Finished May 26 01:57:31 PM PDT 24
Peak memory 200644 kb
Host smart-18924904-2098-4866-9f71-23548b39cd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781031278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3781031278
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.4058932554
Short name T100
Test name
Test status
Simulation time 9910067489 ps
CPU time 39.8 seconds
Started May 26 01:57:30 PM PDT 24
Finished May 26 01:58:12 PM PDT 24
Peak memory 209052 kb
Host smart-75279e5e-c227-4641-aff5-8607d3b6a5f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058932554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.4058932554
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.354168360
Short name T457
Test name
Test status
Simulation time 475614496 ps
CPU time 2.55 seconds
Started May 26 01:57:28 PM PDT 24
Finished May 26 01:57:32 PM PDT 24
Peak memory 200456 kb
Host smart-0d98045c-2475-48c1-8033-db0303918292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354168360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.354168360
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2449677998
Short name T376
Test name
Test status
Simulation time 125611560 ps
CPU time 1.02 seconds
Started May 26 01:57:28 PM PDT 24
Finished May 26 01:57:31 PM PDT 24
Peak memory 200460 kb
Host smart-60b23243-834a-410f-9d59-07b792b105cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449677998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2449677998
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2236176041
Short name T418
Test name
Test status
Simulation time 75112481 ps
CPU time 0.85 seconds
Started May 26 01:57:30 PM PDT 24
Finished May 26 01:57:34 PM PDT 24
Peak memory 200340 kb
Host smart-fe907759-e0a5-41c9-8e66-4659d742dc1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236176041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2236176041
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.306442326
Short name T498
Test name
Test status
Simulation time 2352541098 ps
CPU time 8.3 seconds
Started May 26 01:57:32 PM PDT 24
Finished May 26 01:57:44 PM PDT 24
Peak memory 222288 kb
Host smart-e8814e73-0587-4e7a-adee-faaf7dd88a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306442326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.306442326
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.4281408816
Short name T1
Test name
Test status
Simulation time 244119071 ps
CPU time 1.04 seconds
Started May 26 01:57:29 PM PDT 24
Finished May 26 01:57:33 PM PDT 24
Peak memory 217604 kb
Host smart-548d604f-1c7d-4fd2-86e4-19f0ff6165a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281408816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.4281408816
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.332067933
Short name T381
Test name
Test status
Simulation time 133739362 ps
CPU time 0.81 seconds
Started May 26 01:57:30 PM PDT 24
Finished May 26 01:57:34 PM PDT 24
Peak memory 200316 kb
Host smart-9d3a0ac5-3119-465a-854c-45c795a33447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332067933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.332067933
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.1187399092
Short name T243
Test name
Test status
Simulation time 753488598 ps
CPU time 4.24 seconds
Started May 26 01:57:35 PM PDT 24
Finished May 26 01:57:41 PM PDT 24
Peak memory 200704 kb
Host smart-2ca07e2b-c711-48cb-a90b-8462ba9152cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187399092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1187399092
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1760914648
Short name T24
Test name
Test status
Simulation time 94329009 ps
CPU time 1 seconds
Started May 26 01:57:30 PM PDT 24
Finished May 26 01:57:34 PM PDT 24
Peak memory 200508 kb
Host smart-ccc75fa5-a6a1-4727-8735-a6b5da2ab447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760914648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1760914648
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3684924270
Short name T320
Test name
Test status
Simulation time 242284972 ps
CPU time 1.57 seconds
Started May 26 01:57:27 PM PDT 24
Finished May 26 01:57:31 PM PDT 24
Peak memory 200584 kb
Host smart-888cc59d-f383-49bc-addd-6451582e358f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684924270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3684924270
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.936019620
Short name T288
Test name
Test status
Simulation time 15628452685 ps
CPU time 53.72 seconds
Started May 26 01:57:32 PM PDT 24
Finished May 26 01:58:29 PM PDT 24
Peak memory 209040 kb
Host smart-12eb4688-8e37-4593-8252-eac459aee167
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936019620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.936019620
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.1069217682
Short name T305
Test name
Test status
Simulation time 129246557 ps
CPU time 1.74 seconds
Started May 26 01:57:31 PM PDT 24
Finished May 26 01:57:36 PM PDT 24
Peak memory 200504 kb
Host smart-a403eacd-48ee-43f6-b24d-c364ef81cd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069217682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1069217682
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.646260677
Short name T460
Test name
Test status
Simulation time 241609357 ps
CPU time 1.49 seconds
Started May 26 01:57:28 PM PDT 24
Finished May 26 01:57:32 PM PDT 24
Peak memory 200664 kb
Host smart-f3e9188e-0b8d-4d1e-bfc0-74ce0a0c17fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646260677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.646260677
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1056516622
Short name T539
Test name
Test status
Simulation time 61190891 ps
CPU time 0.79 seconds
Started May 26 01:56:14 PM PDT 24
Finished May 26 01:56:27 PM PDT 24
Peak memory 200312 kb
Host smart-1806c1d2-8d72-4087-b5cf-d4ab704e70f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056516622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1056516622
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2050935356
Short name T374
Test name
Test status
Simulation time 1897381088 ps
CPU time 7.12 seconds
Started May 26 01:56:16 PM PDT 24
Finished May 26 01:56:40 PM PDT 24
Peak memory 218040 kb
Host smart-3f74ca38-7f80-4598-b62e-86ff1bcf74ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050935356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2050935356
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1220189638
Short name T390
Test name
Test status
Simulation time 244951664 ps
CPU time 1.1 seconds
Started May 26 01:56:14 PM PDT 24
Finished May 26 01:56:28 PM PDT 24
Peak memory 217692 kb
Host smart-6b828416-e512-4b0a-92fe-d6cbccdf4a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220189638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1220189638
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.2098730739
Short name T308
Test name
Test status
Simulation time 219440297 ps
CPU time 0.9 seconds
Started May 26 01:56:10 PM PDT 24
Finished May 26 01:56:17 PM PDT 24
Peak memory 200180 kb
Host smart-7cabef33-f68d-426f-bae6-8c6706120520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098730739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2098730739
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.3165812711
Short name T394
Test name
Test status
Simulation time 851747151 ps
CPU time 4.52 seconds
Started May 26 01:56:08 PM PDT 24
Finished May 26 01:56:16 PM PDT 24
Peak memory 200648 kb
Host smart-7635e51f-f096-438a-8e8c-19cd5ca7290e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165812711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3165812711
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.287197970
Short name T166
Test name
Test status
Simulation time 97237265 ps
CPU time 0.96 seconds
Started May 26 01:56:11 PM PDT 24
Finished May 26 01:56:20 PM PDT 24
Peak memory 200504 kb
Host smart-8246cf34-61cf-4c18-9b37-2808d1ebf45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287197970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.287197970
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.373915500
Short name T375
Test name
Test status
Simulation time 257707651 ps
CPU time 1.57 seconds
Started May 26 01:56:10 PM PDT 24
Finished May 26 01:56:18 PM PDT 24
Peak memory 200616 kb
Host smart-cc8f0361-2f41-440a-bd56-fa94722b4317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373915500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.373915500
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2284523910
Short name T303
Test name
Test status
Simulation time 9673823653 ps
CPU time 33.57 seconds
Started May 26 01:56:15 PM PDT 24
Finished May 26 01:57:03 PM PDT 24
Peak memory 200764 kb
Host smart-8238e40f-948d-4113-a089-1398c4867f60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284523910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2284523910
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.960504107
Short name T453
Test name
Test status
Simulation time 141193802 ps
CPU time 1.75 seconds
Started May 26 01:56:13 PM PDT 24
Finished May 26 01:56:25 PM PDT 24
Peak memory 200480 kb
Host smart-e55992fe-8f47-450a-93e7-bef50bab5b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960504107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.960504107
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1049037638
Short name T478
Test name
Test status
Simulation time 173121035 ps
CPU time 1.12 seconds
Started May 26 01:56:08 PM PDT 24
Finished May 26 01:56:13 PM PDT 24
Peak memory 200448 kb
Host smart-23c1d639-9400-4947-b08c-b1db58c1c894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049037638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1049037638
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.112004354
Short name T262
Test name
Test status
Simulation time 67957222 ps
CPU time 0.78 seconds
Started May 26 01:56:17 PM PDT 24
Finished May 26 01:56:35 PM PDT 24
Peak memory 200300 kb
Host smart-fc829bb1-e9d0-4974-a310-bec4156759f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112004354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.112004354
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1945899332
Short name T31
Test name
Test status
Simulation time 1227281567 ps
CPU time 5.52 seconds
Started May 26 01:56:17 PM PDT 24
Finished May 26 01:56:39 PM PDT 24
Peak memory 218124 kb
Host smart-e9ba6f4f-ced6-467e-85f5-df6ccf5b6e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945899332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1945899332
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2818694901
Short name T419
Test name
Test status
Simulation time 244617488 ps
CPU time 1.11 seconds
Started May 26 01:56:18 PM PDT 24
Finished May 26 01:56:35 PM PDT 24
Peak memory 217556 kb
Host smart-2141c2ee-f40c-4413-bc99-8c736a92b84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818694901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2818694901
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1935058819
Short name T276
Test name
Test status
Simulation time 107027053 ps
CPU time 0.81 seconds
Started May 26 01:56:13 PM PDT 24
Finished May 26 01:56:25 PM PDT 24
Peak memory 200220 kb
Host smart-d1e504b9-d2c3-428d-820b-384437d0d51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935058819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1935058819
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1516468139
Short name T99
Test name
Test status
Simulation time 1088913299 ps
CPU time 4.91 seconds
Started May 26 01:56:14 PM PDT 24
Finished May 26 01:56:32 PM PDT 24
Peak memory 200688 kb
Host smart-513c2935-19b2-46fc-8335-c447f543447c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516468139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1516468139
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2436706040
Short name T298
Test name
Test status
Simulation time 96906753 ps
CPU time 1.02 seconds
Started May 26 01:56:14 PM PDT 24
Finished May 26 01:56:27 PM PDT 24
Peak memory 200528 kb
Host smart-7998d8e7-1866-4a8a-8550-7190d09bb9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436706040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2436706040
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.708171620
Short name T220
Test name
Test status
Simulation time 263573201 ps
CPU time 1.65 seconds
Started May 26 01:56:14 PM PDT 24
Finished May 26 01:56:29 PM PDT 24
Peak memory 200708 kb
Host smart-fee3ecb9-4a1b-428b-98e7-04b27af9780a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708171620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.708171620
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.2173591273
Short name T124
Test name
Test status
Simulation time 8895427437 ps
CPU time 31.37 seconds
Started May 26 01:56:14 PM PDT 24
Finished May 26 01:56:59 PM PDT 24
Peak memory 200784 kb
Host smart-f243f7b8-5de5-40b3-803e-c439d91375b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173591273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2173591273
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.3285899093
Short name T529
Test name
Test status
Simulation time 388617652 ps
CPU time 2.69 seconds
Started May 26 01:56:15 PM PDT 24
Finished May 26 01:56:33 PM PDT 24
Peak memory 200468 kb
Host smart-584d2612-f48d-47e1-a8b7-ca25ef0a1f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285899093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.3285899093
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.2769883573
Short name T290
Test name
Test status
Simulation time 197583162 ps
CPU time 1.23 seconds
Started May 26 01:56:13 PM PDT 24
Finished May 26 01:56:27 PM PDT 24
Peak memory 200500 kb
Host smart-e3a7854d-51fe-4a14-9e9f-8e4a7e5557ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769883573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2769883573
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3089369014
Short name T153
Test name
Test status
Simulation time 81654109 ps
CPU time 0.89 seconds
Started May 26 01:56:22 PM PDT 24
Finished May 26 01:56:41 PM PDT 24
Peak memory 200272 kb
Host smart-5f015f2d-37a1-4f1d-813d-37f3d4b62180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089369014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3089369014
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3491099430
Short name T339
Test name
Test status
Simulation time 2349721092 ps
CPU time 8.24 seconds
Started May 26 01:56:22 PM PDT 24
Finished May 26 01:56:48 PM PDT 24
Peak memory 217604 kb
Host smart-921dcd76-1b10-4d6b-8927-4e61cdf340ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491099430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3491099430
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.4016040285
Short name T524
Test name
Test status
Simulation time 244738054 ps
CPU time 1.15 seconds
Started May 26 01:56:18 PM PDT 24
Finished May 26 01:56:36 PM PDT 24
Peak memory 217540 kb
Host smart-6dce4eab-fe5f-4aa7-8656-5cb8ad688499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016040285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.4016040285
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.967501327
Short name T363
Test name
Test status
Simulation time 149695484 ps
CPU time 0.85 seconds
Started May 26 01:56:16 PM PDT 24
Finished May 26 01:56:32 PM PDT 24
Peak memory 200316 kb
Host smart-a31e9dac-09c1-4882-96db-5525a269a555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967501327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.967501327
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3683436051
Short name T322
Test name
Test status
Simulation time 2051495832 ps
CPU time 7.31 seconds
Started May 26 01:56:17 PM PDT 24
Finished May 26 01:56:40 PM PDT 24
Peak memory 200644 kb
Host smart-eb2bc0fe-a754-451d-a240-d9918ed676d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683436051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3683436051
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2896514123
Short name T397
Test name
Test status
Simulation time 99237177 ps
CPU time 0.98 seconds
Started May 26 01:56:15 PM PDT 24
Finished May 26 01:56:32 PM PDT 24
Peak memory 200528 kb
Host smart-222bd389-77ad-4391-acfc-08ae20341718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896514123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2896514123
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2155608440
Short name T182
Test name
Test status
Simulation time 206208147 ps
CPU time 1.41 seconds
Started May 26 01:56:19 PM PDT 24
Finished May 26 01:56:37 PM PDT 24
Peak memory 200652 kb
Host smart-f9a4a6e0-704f-4bb2-9a0c-c96d452f0d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155608440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2155608440
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.739814995
Short name T98
Test name
Test status
Simulation time 4241430872 ps
CPU time 20.26 seconds
Started May 26 01:56:22 PM PDT 24
Finished May 26 01:57:00 PM PDT 24
Peak memory 200080 kb
Host smart-63dd7c44-a8d4-4d31-b4c4-116ef68f7331
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739814995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.739814995
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3317251244
Short name T356
Test name
Test status
Simulation time 123363724 ps
CPU time 1.6 seconds
Started May 26 01:56:14 PM PDT 24
Finished May 26 01:56:28 PM PDT 24
Peak memory 208680 kb
Host smart-152066e7-c5a5-47fc-9ff7-dc7544a96c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317251244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3317251244
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1587346343
Short name T293
Test name
Test status
Simulation time 185915414 ps
CPU time 1.17 seconds
Started May 26 01:56:19 PM PDT 24
Finished May 26 01:56:36 PM PDT 24
Peak memory 200504 kb
Host smart-f2631830-22e4-456d-9bfc-330cd144dd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587346343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1587346343
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1083053691
Short name T167
Test name
Test status
Simulation time 80106106 ps
CPU time 0.82 seconds
Started May 26 01:56:18 PM PDT 24
Finished May 26 01:56:36 PM PDT 24
Peak memory 200340 kb
Host smart-42d82127-938e-4c84-94f9-1a30a8fb213a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083053691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1083053691
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3592047034
Short name T415
Test name
Test status
Simulation time 1232164546 ps
CPU time 5.93 seconds
Started May 26 01:56:18 PM PDT 24
Finished May 26 01:56:41 PM PDT 24
Peak memory 217988 kb
Host smart-8cf82d7e-32c2-4c87-8356-0fdaf846b6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592047034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3592047034
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2036442659
Short name T62
Test name
Test status
Simulation time 244493054 ps
CPU time 1.11 seconds
Started May 26 01:56:17 PM PDT 24
Finished May 26 01:56:35 PM PDT 24
Peak memory 217748 kb
Host smart-84aadb6a-afba-4dbb-a289-e91a9a3bf5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036442659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2036442659
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3836607558
Short name T465
Test name
Test status
Simulation time 121774984 ps
CPU time 0.79 seconds
Started May 26 01:56:16 PM PDT 24
Finished May 26 01:56:32 PM PDT 24
Peak memory 200296 kb
Host smart-c33ca95a-ecdb-4aa6-9aa3-ad0c8133728e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836607558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3836607558
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2470101650
Short name T520
Test name
Test status
Simulation time 860491586 ps
CPU time 4.17 seconds
Started May 26 01:56:15 PM PDT 24
Finished May 26 01:56:34 PM PDT 24
Peak memory 200668 kb
Host smart-aef45b92-0d61-492f-b784-8c2762c6d439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470101650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2470101650
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.4156548192
Short name T141
Test name
Test status
Simulation time 98522127 ps
CPU time 1.02 seconds
Started May 26 01:56:21 PM PDT 24
Finished May 26 01:56:39 PM PDT 24
Peak memory 200408 kb
Host smart-2f2f6a53-1762-4ea1-8d44-0d92a983ac4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156548192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.4156548192
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2058516457
Short name T127
Test name
Test status
Simulation time 225617316 ps
CPU time 1.52 seconds
Started May 26 01:56:19 PM PDT 24
Finished May 26 01:56:37 PM PDT 24
Peak memory 200688 kb
Host smart-4cd5ac52-2a25-4085-b22f-2e8b41d31ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058516457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2058516457
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.1337498021
Short name T409
Test name
Test status
Simulation time 165157532 ps
CPU time 1.26 seconds
Started May 26 01:56:17 PM PDT 24
Finished May 26 01:56:35 PM PDT 24
Peak memory 200704 kb
Host smart-74dd739a-c540-4f88-888f-6269f7f5318c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337498021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.1337498021
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.4146422158
Short name T297
Test name
Test status
Simulation time 305073255 ps
CPU time 2.01 seconds
Started May 26 01:56:18 PM PDT 24
Finished May 26 01:56:37 PM PDT 24
Peak memory 208732 kb
Host smart-44b466f9-ef4e-4fe7-918a-2ed78b37ac5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146422158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.4146422158
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.973785496
Short name T420
Test name
Test status
Simulation time 154939247 ps
CPU time 1.24 seconds
Started May 26 01:56:16 PM PDT 24
Finished May 26 01:56:32 PM PDT 24
Peak memory 200672 kb
Host smart-f14ac275-c6a7-45d3-8728-5619a5e9f67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973785496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.973785496
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2014572785
Short name T444
Test name
Test status
Simulation time 59579014 ps
CPU time 0.78 seconds
Started May 26 01:56:19 PM PDT 24
Finished May 26 01:56:37 PM PDT 24
Peak memory 200312 kb
Host smart-fac330ba-73cb-486e-a135-f474976a2849
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014572785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2014572785
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.3805479113
Short name T30
Test name
Test status
Simulation time 1223538946 ps
CPU time 5.53 seconds
Started May 26 01:56:20 PM PDT 24
Finished May 26 01:56:43 PM PDT 24
Peak memory 217296 kb
Host smart-302e7908-cd52-4dfa-b531-20096251c005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805479113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3805479113
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.966461310
Short name T525
Test name
Test status
Simulation time 245244126 ps
CPU time 1.05 seconds
Started May 26 01:56:20 PM PDT 24
Finished May 26 01:56:38 PM PDT 24
Peak memory 217448 kb
Host smart-0fb3e4b2-d9d5-4d4b-887b-aa4bf29c09ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966461310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.966461310
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2924483302
Short name T402
Test name
Test status
Simulation time 81371122 ps
CPU time 0.75 seconds
Started May 26 01:56:20 PM PDT 24
Finished May 26 01:56:38 PM PDT 24
Peak memory 200220 kb
Host smart-e139ee6d-483f-4c59-99b8-30b3ada653f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924483302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2924483302
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3479900235
Short name T443
Test name
Test status
Simulation time 962988415 ps
CPU time 4.8 seconds
Started May 26 01:56:20 PM PDT 24
Finished May 26 01:56:42 PM PDT 24
Peak memory 200684 kb
Host smart-99f7a9ea-9153-4750-845d-cc200c8e8980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479900235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3479900235
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.103573135
Short name T343
Test name
Test status
Simulation time 96536145 ps
CPU time 1.01 seconds
Started May 26 01:56:19 PM PDT 24
Finished May 26 01:56:37 PM PDT 24
Peak memory 200436 kb
Host smart-2b6f978a-7ebf-4ccd-963e-f44b3827be24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103573135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.103573135
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.4147584664
Short name T371
Test name
Test status
Simulation time 127916476 ps
CPU time 1.18 seconds
Started May 26 01:56:20 PM PDT 24
Finished May 26 01:56:38 PM PDT 24
Peak memory 200664 kb
Host smart-bdbb1d41-a5ce-46a5-80df-3f750902989f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147584664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.4147584664
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3521215775
Short name T504
Test name
Test status
Simulation time 4950603256 ps
CPU time 21.84 seconds
Started May 26 01:56:20 PM PDT 24
Finished May 26 01:56:59 PM PDT 24
Peak memory 200796 kb
Host smart-3788e7fb-0a18-4bbe-b969-5c50954eb86b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521215775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3521215775
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2524735352
Short name T336
Test name
Test status
Simulation time 145281489 ps
CPU time 1.77 seconds
Started May 26 01:56:19 PM PDT 24
Finished May 26 01:56:37 PM PDT 24
Peak memory 200396 kb
Host smart-e18b1212-6cf6-429a-a04d-c97d7e8048ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524735352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2524735352
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3863405733
Short name T500
Test name
Test status
Simulation time 109372668 ps
CPU time 0.98 seconds
Started May 26 01:56:20 PM PDT 24
Finished May 26 01:56:38 PM PDT 24
Peak memory 200396 kb
Host smart-1481c7b1-d2ce-41d4-a268-2017e414f632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863405733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3863405733
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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