Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8918

1

T1

36

T2

9

T4

20

auto[1]

11845

1

T1

19

T2

1

T4

81

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6204	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	7013	1			T1	20		T2	1		T3	1
reset_info_cp[2]	3226	1			T1	8		T4	14		T6	21
reset_info_cp[4]	4306	1			T1	10		T4	17		T6	18
reset_info_cp[8]	138	1			T1	1		T23	1		T141	1
reset_info_cp[16]	122	1			T22	1		T57	1		T86	2
reset_info_cp[32]	110	1			T22	3		T23	1		T86	2
reset_info_cp[64]	143	1			T6	1		T22	2		T86	1
reset_info_cp[128]	120	1			T4	2		T11	1		T22	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3392	1			T1	11		T4	20		T6	12
reset_info_cp[1]	auto[1]	3002	1			T1	8		T4	6		T6	14
reset_info_cp[2]	auto[0]	1037	1			T1	4		T22	3		T86	8
reset_info_cp[2]	auto[1]	2189	1			T1	4		T4	14		T6	21
reset_info_cp[4]	auto[0]	1538	1			T1	8		T21	4		T22	12
reset_info_cp[4]	auto[1]	2768	1			T1	2		T4	17		T6	18
reset_info_cp[8]	auto[0]	55	1			T23	1		T141	1		T136	2
reset_info_cp[8]	auto[1]	83	1			T1	1		T43	2		T44	1
reset_info_cp[16]	auto[0]	45	1			T86	2		T49	1		T53	1
reset_info_cp[16]	auto[1]	77	1			T22	1		T57	1		T43	2
reset_info_cp[32]	auto[0]	47	1			T22	2		T23	1		T86	1
reset_info_cp[32]	auto[1]	63	1			T22	1		T86	1		T44	1
reset_info_cp[64]	auto[0]	55	1			T22	1		T86	1		T141	1
reset_info_cp[64]	auto[1]	88	1			T6	1		T22	1		T51	1
reset_info_cp[128]	auto[0]	48	1			T11	1		T22	1		T86	1
reset_info_cp[128]	auto[1]	72	1			T4	2		T86	1		T51	1