Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 619
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T537 /workspace/coverage/default/22.rstmgr_alert_test.3280785633 May 28 01:38:01 PM PDT 24 May 28 01:38:06 PM PDT 24 66531983 ps
T538 /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.79033626 May 28 01:38:26 PM PDT 24 May 28 01:38:37 PM PDT 24 1229293751 ps
T539 /workspace/coverage/default/37.rstmgr_reset.2655708298 May 28 01:38:28 PM PDT 24 May 28 01:38:39 PM PDT 24 713335501 ps
T540 /workspace/coverage/default/23.rstmgr_por_stretcher.2408145041 May 28 01:37:59 PM PDT 24 May 28 01:38:03 PM PDT 24 86572887 ps
T64 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3913414389 May 28 01:36:59 PM PDT 24 May 28 01:37:04 PM PDT 24 458915828 ps
T65 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1572472991 May 28 01:36:41 PM PDT 24 May 28 01:36:44 PM PDT 24 80495533 ps
T66 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2771726484 May 28 01:36:42 PM PDT 24 May 28 01:36:46 PM PDT 24 209125770 ps
T68 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2198630955 May 28 01:36:43 PM PDT 24 May 28 01:36:49 PM PDT 24 264329697 ps
T69 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3518551093 May 28 01:36:55 PM PDT 24 May 28 01:37:02 PM PDT 24 139530508 ps
T541 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2685008586 May 28 01:36:54 PM PDT 24 May 28 01:36:59 PM PDT 24 74863733 ps
T67 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1735564433 May 28 01:36:55 PM PDT 24 May 28 01:37:00 PM PDT 24 120615917 ps
T73 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1168477922 May 28 01:36:53 PM PDT 24 May 28 01:36:57 PM PDT 24 117078339 ps
T117 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.656096840 May 28 01:36:53 PM PDT 24 May 28 01:36:57 PM PDT 24 144198827 ps
T95 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.959749598 May 28 01:36:44 PM PDT 24 May 28 01:36:50 PM PDT 24 187032948 ps
T118 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3874626576 May 28 01:36:54 PM PDT 24 May 28 01:36:59 PM PDT 24 77246992 ps
T96 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1889327572 May 28 01:36:42 PM PDT 24 May 28 01:36:47 PM PDT 24 125318558 ps
T97 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3610277599 May 28 01:36:54 PM PDT 24 May 28 01:37:01 PM PDT 24 355899609 ps
T100 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3538753712 May 28 01:36:53 PM PDT 24 May 28 01:36:59 PM PDT 24 898374108 ps
T542 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2428019264 May 28 01:37:12 PM PDT 24 May 28 01:37:14 PM PDT 24 88649302 ps
T543 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2855093636 May 28 01:36:41 PM PDT 24 May 28 01:36:50 PM PDT 24 1176789109 ps
T119 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.745249010 May 28 01:36:41 PM PDT 24 May 28 01:36:45 PM PDT 24 115580671 ps
T98 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.52859014 May 28 01:36:45 PM PDT 24 May 28 01:36:51 PM PDT 24 470705442 ps
T544 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1675037584 May 28 01:36:43 PM PDT 24 May 28 01:36:49 PM PDT 24 146200210 ps
T545 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1091704683 May 28 01:36:30 PM PDT 24 May 28 01:36:35 PM PDT 24 149331903 ps
T99 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.4213703145 May 28 01:36:42 PM PDT 24 May 28 01:36:47 PM PDT 24 302114763 ps
T546 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.132599918 May 28 01:36:44 PM PDT 24 May 28 01:36:48 PM PDT 24 109656146 ps
T547 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.132578350 May 28 01:36:39 PM PDT 24 May 28 01:36:41 PM PDT 24 73986488 ps
T120 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.886680215 May 28 01:36:57 PM PDT 24 May 28 01:37:02 PM PDT 24 99368720 ps
T101 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1783478242 May 28 01:36:42 PM PDT 24 May 28 01:36:47 PM PDT 24 120690286 ps
T102 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.766482829 May 28 01:36:55 PM PDT 24 May 28 01:37:02 PM PDT 24 471871120 ps
T548 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2792598563 May 28 01:37:07 PM PDT 24 May 28 01:37:10 PM PDT 24 178745627 ps
T549 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.713083949 May 28 01:36:41 PM PDT 24 May 28 01:36:45 PM PDT 24 300527787 ps
T121 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3842806535 May 28 01:36:45 PM PDT 24 May 28 01:36:50 PM PDT 24 190079260 ps
T134 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2513930214 May 28 01:36:43 PM PDT 24 May 28 01:36:49 PM PDT 24 210663260 ps
T127 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1878845357 May 28 01:36:52 PM PDT 24 May 28 01:36:58 PM PDT 24 511995590 ps
T550 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1712114381 May 28 01:36:45 PM PDT 24 May 28 01:36:52 PM PDT 24 271233973 ps
T132 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3659727321 May 28 01:36:41 PM PDT 24 May 28 01:36:46 PM PDT 24 302776553 ps
T551 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.248142229 May 28 01:36:42 PM PDT 24 May 28 01:36:47 PM PDT 24 147828237 ps
T133 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1982874785 May 28 01:36:54 PM PDT 24 May 28 01:37:00 PM PDT 24 214373380 ps
T131 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.488414666 May 28 01:36:32 PM PDT 24 May 28 01:36:38 PM PDT 24 170617845 ps
T552 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.65869777 May 28 01:36:30 PM PDT 24 May 28 01:36:35 PM PDT 24 115038672 ps
T139 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1101317294 May 28 01:36:42 PM PDT 24 May 28 01:36:49 PM PDT 24 1034574637 ps
T553 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1419255250 May 28 01:36:52 PM PDT 24 May 28 01:36:56 PM PDT 24 123693224 ps
T554 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.53521555 May 28 01:36:43 PM PDT 24 May 28 01:36:48 PM PDT 24 205897950 ps
T122 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2784652752 May 28 01:36:51 PM PDT 24 May 28 01:36:54 PM PDT 24 87854886 ps
T123 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2099700373 May 28 01:36:43 PM PDT 24 May 28 01:36:48 PM PDT 24 143331402 ps
T555 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3604413347 May 28 01:36:44 PM PDT 24 May 28 01:36:49 PM PDT 24 105038716 ps
T556 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.776555532 May 28 01:36:44 PM PDT 24 May 28 01:36:49 PM PDT 24 465211071 ps
T557 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1397258736 May 28 01:36:40 PM PDT 24 May 28 01:36:42 PM PDT 24 112492123 ps
T558 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.360565527 May 28 01:36:31 PM PDT 24 May 28 01:36:47 PM PDT 24 2305755825 ps
T124 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.744067993 May 28 01:36:59 PM PDT 24 May 28 01:37:03 PM PDT 24 84330863 ps
T125 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2934953000 May 28 01:36:43 PM PDT 24 May 28 01:36:48 PM PDT 24 262699456 ps
T559 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.298696188 May 28 01:36:30 PM PDT 24 May 28 01:36:34 PM PDT 24 63453033 ps
T560 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.536112681 May 28 01:36:55 PM PDT 24 May 28 01:37:00 PM PDT 24 128902200 ps
T561 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1992370910 May 28 01:36:54 PM PDT 24 May 28 01:36:59 PM PDT 24 73196674 ps
T562 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1546700424 May 28 01:36:41 PM PDT 24 May 28 01:36:44 PM PDT 24 76705800 ps
T563 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1158174992 May 28 01:36:59 PM PDT 24 May 28 01:37:04 PM PDT 24 251067187 ps
T138 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2498651699 May 28 01:37:08 PM PDT 24 May 28 01:37:12 PM PDT 24 477028407 ps
T564 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1613644349 May 28 01:36:53 PM PDT 24 May 28 01:36:59 PM PDT 24 429194649 ps
T565 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2754177903 May 28 01:36:59 PM PDT 24 May 28 01:37:05 PM PDT 24 424609538 ps
T566 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2634514729 May 28 01:36:44 PM PDT 24 May 28 01:36:49 PM PDT 24 81239844 ps
T126 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.641899212 May 28 01:36:44 PM PDT 24 May 28 01:36:50 PM PDT 24 772699770 ps
T567 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3636036641 May 28 01:36:44 PM PDT 24 May 28 01:36:49 PM PDT 24 101646625 ps
T568 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2528409514 May 28 01:36:44 PM PDT 24 May 28 01:36:49 PM PDT 24 129864235 ps
T129 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3967544540 May 28 01:36:44 PM PDT 24 May 28 01:36:50 PM PDT 24 466710239 ps
T569 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1615950652 May 28 01:36:42 PM PDT 24 May 28 01:36:51 PM PDT 24 482993415 ps
T570 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2628154280 May 28 01:36:52 PM PDT 24 May 28 01:36:57 PM PDT 24 240029278 ps
T571 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1302237671 May 28 01:36:42 PM PDT 24 May 28 01:36:47 PM PDT 24 207619354 ps
T572 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2136606011 May 28 01:36:56 PM PDT 24 May 28 01:37:01 PM PDT 24 76326181 ps
T130 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3291282601 May 28 01:36:52 PM PDT 24 May 28 01:36:57 PM PDT 24 527826342 ps
T573 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1625305 May 28 01:36:41 PM PDT 24 May 28 01:36:45 PM PDT 24 73624293 ps
T574 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.394630694 May 28 01:36:45 PM PDT 24 May 28 01:36:51 PM PDT 24 161439580 ps
T575 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3788824959 May 28 01:37:05 PM PDT 24 May 28 01:37:09 PM PDT 24 259570448 ps
T576 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.80076795 May 28 01:36:58 PM PDT 24 May 28 01:37:03 PM PDT 24 488030065 ps
T577 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2557087764 May 28 01:36:54 PM PDT 24 May 28 01:36:59 PM PDT 24 59146858 ps
T578 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1329278225 May 28 01:36:52 PM PDT 24 May 28 01:36:55 PM PDT 24 135245733 ps
T579 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1728954247 May 28 01:36:59 PM PDT 24 May 28 01:37:03 PM PDT 24 62743582 ps
T580 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3393070793 May 28 01:36:45 PM PDT 24 May 28 01:36:49 PM PDT 24 72486136 ps
T581 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.744567591 May 28 01:36:54 PM PDT 24 May 28 01:36:59 PM PDT 24 122910137 ps
T582 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3227445331 May 28 01:36:42 PM PDT 24 May 28 01:36:47 PM PDT 24 219820902 ps
T583 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.455409028 May 28 01:37:06 PM PDT 24 May 28 01:37:09 PM PDT 24 225244778 ps
T584 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3518318869 May 28 01:36:54 PM PDT 24 May 28 01:36:59 PM PDT 24 74737770 ps
T585 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.181722593 May 28 01:36:42 PM PDT 24 May 28 01:36:48 PM PDT 24 267869369 ps
T586 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3430407432 May 28 01:36:44 PM PDT 24 May 28 01:36:50 PM PDT 24 192816060 ps
T587 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3251538102 May 28 01:36:55 PM PDT 24 May 28 01:37:00 PM PDT 24 93319486 ps
T588 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.486311917 May 28 01:36:56 PM PDT 24 May 28 01:37:02 PM PDT 24 250525651 ps
T589 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3083920828 May 28 01:36:56 PM PDT 24 May 28 01:37:02 PM PDT 24 273529498 ps
T590 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1297577986 May 28 01:36:55 PM PDT 24 May 28 01:37:01 PM PDT 24 125482830 ps
T591 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2964845941 May 28 01:36:55 PM PDT 24 May 28 01:37:00 PM PDT 24 70775804 ps
T592 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.141339926 May 28 01:36:31 PM PDT 24 May 28 01:36:37 PM PDT 24 496152700 ps
T593 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.346990897 May 28 01:36:43 PM PDT 24 May 28 01:36:48 PM PDT 24 76064354 ps
T594 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4190764552 May 28 01:36:42 PM PDT 24 May 28 01:36:46 PM PDT 24 148400256 ps
T595 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2499646286 May 28 01:36:42 PM PDT 24 May 28 01:36:47 PM PDT 24 175450643 ps
T596 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3319480749 May 28 01:36:55 PM PDT 24 May 28 01:37:03 PM PDT 24 498446775 ps
T597 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2085487314 May 28 01:36:42 PM PDT 24 May 28 01:36:47 PM PDT 24 99480202 ps
T598 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.255822923 May 28 01:36:53 PM PDT 24 May 28 01:36:57 PM PDT 24 133916026 ps
T599 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3590833405 May 28 01:36:52 PM PDT 24 May 28 01:36:59 PM PDT 24 1215952485 ps
T140 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1133144584 May 28 01:36:45 PM PDT 24 May 28 01:36:51 PM PDT 24 486202904 ps
T600 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1891660228 May 28 01:36:52 PM PDT 24 May 28 01:36:56 PM PDT 24 105484016 ps
T601 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.907078237 May 28 01:36:40 PM PDT 24 May 28 01:36:43 PM PDT 24 75607925 ps
T602 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.793280628 May 28 01:36:55 PM PDT 24 May 28 01:37:01 PM PDT 24 484454594 ps
T603 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3089191667 May 28 01:36:42 PM PDT 24 May 28 01:36:47 PM PDT 24 256742988 ps
T604 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2914690876 May 28 01:37:04 PM PDT 24 May 28 01:37:06 PM PDT 24 72275060 ps
T605 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3779701698 May 28 01:36:47 PM PDT 24 May 28 01:36:51 PM PDT 24 142985075 ps
T606 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.911919210 May 28 01:36:53 PM PDT 24 May 28 01:37:01 PM PDT 24 957237409 ps
T607 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3444374999 May 28 01:36:55 PM PDT 24 May 28 01:37:00 PM PDT 24 129162779 ps
T608 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.794252922 May 28 01:36:43 PM PDT 24 May 28 01:36:48 PM PDT 24 474070699 ps
T609 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2108781096 May 28 01:36:47 PM PDT 24 May 28 01:36:52 PM PDT 24 207500471 ps
T610 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1330002037 May 28 01:36:52 PM PDT 24 May 28 01:36:58 PM PDT 24 206833391 ps
T128 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3594765391 May 28 01:36:59 PM PDT 24 May 28 01:37:05 PM PDT 24 872044278 ps
T611 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1789543974 May 28 01:36:43 PM PDT 24 May 28 01:36:48 PM PDT 24 116355422 ps
T612 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1341172487 May 28 01:36:47 PM PDT 24 May 28 01:36:53 PM PDT 24 899281230 ps
T613 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3000748250 May 28 01:36:40 PM PDT 24 May 28 01:36:43 PM PDT 24 104537293 ps
T614 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.912584055 May 28 01:36:56 PM PDT 24 May 28 01:37:03 PM PDT 24 799420281 ps
T615 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2633568197 May 28 01:37:06 PM PDT 24 May 28 01:37:09 PM PDT 24 128747428 ps
T616 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2788389586 May 28 01:36:44 PM PDT 24 May 28 01:36:49 PM PDT 24 131530032 ps
T617 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.230836044 May 28 01:37:00 PM PDT 24 May 28 01:37:04 PM PDT 24 208620364 ps
T618 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3470946975 May 28 01:36:55 PM PDT 24 May 28 01:36:59 PM PDT 24 60952991 ps
T619 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2654068355 May 28 01:36:53 PM PDT 24 May 28 01:36:58 PM PDT 24 103910446 ps

Test location /workspace/coverage/default/42.rstmgr_reset.814410469
Short name T1
Test name
Test status
Simulation time 937948355 ps
CPU time 4.59 seconds
Started May 28 01:38:45 PM PDT 24
Finished May 28 01:38:54 PM PDT 24
Peak memory 200720 kb
Host smart-463a0193-70e6-4e96-9f27-8e9f375c758f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814410469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.814410469
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1992915176
Short name T62
Test name
Test status
Simulation time 148617703 ps
CPU time 1.89 seconds
Started May 28 01:38:48 PM PDT 24
Finished May 28 01:38:54 PM PDT 24
Peak memory 200268 kb
Host smart-c6b6f34e-b90a-4abd-a045-bd47399023da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992915176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1992915176
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.434964104
Short name T4
Test name
Test status
Simulation time 2171455507 ps
CPU time 7.53 seconds
Started May 28 01:37:41 PM PDT 24
Finished May 28 01:37:52 PM PDT 24
Peak memory 217656 kb
Host smart-cea40ae6-bd28-443f-91ef-6f51ed460eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434964104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.434964104
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.959749598
Short name T95
Test name
Test status
Simulation time 187032948 ps
CPU time 1.3 seconds
Started May 28 01:36:44 PM PDT 24
Finished May 28 01:36:50 PM PDT 24
Peak memory 200372 kb
Host smart-5ca38099-4ae2-4496-9802-33458a88d758
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959749598 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.959749598
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.36607076
Short name T70
Test name
Test status
Simulation time 16944949049 ps
CPU time 25.24 seconds
Started May 28 01:37:04 PM PDT 24
Finished May 28 01:37:31 PM PDT 24
Peak memory 217476 kb
Host smart-ad63763d-aa4a-4ef9-bbb2-83a5d8fe7aed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36607076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.36607076
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.4212679518
Short name T22
Test name
Test status
Simulation time 4762935457 ps
CPU time 17.67 seconds
Started May 28 01:38:28 PM PDT 24
Finished May 28 01:38:53 PM PDT 24
Peak memory 200832 kb
Host smart-9275a379-8b92-495b-bc9e-2aa0bf9784bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212679518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.4212679518
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3538753712
Short name T100
Test name
Test status
Simulation time 898374108 ps
CPU time 3.1 seconds
Started May 28 01:36:53 PM PDT 24
Finished May 28 01:36:59 PM PDT 24
Peak memory 200568 kb
Host smart-d5db5528-36cd-4b51-af20-cb62b61b44ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538753712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3538753712
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.1059572080
Short name T91
Test name
Test status
Simulation time 87691847 ps
CPU time 0.84 seconds
Started May 28 01:37:43 PM PDT 24
Finished May 28 01:37:47 PM PDT 24
Peak memory 200260 kb
Host smart-f004dbc1-2a10-4598-a29c-fa66fea008f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059572080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1059572080
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.3200757496
Short name T43
Test name
Test status
Simulation time 2359714371 ps
CPU time 7.99 seconds
Started May 28 01:37:23 PM PDT 24
Finished May 28 01:37:34 PM PDT 24
Peak memory 218296 kb
Host smart-9e3a08e2-3a7f-4096-aefc-eb42b25d0b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200757496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3200757496
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1889327572
Short name T96
Test name
Test status
Simulation time 125318558 ps
CPU time 1.77 seconds
Started May 28 01:36:42 PM PDT 24
Finished May 28 01:36:47 PM PDT 24
Peak memory 216772 kb
Host smart-133600a5-e06f-4abd-ac26-d56e85d94d1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889327572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1889327572
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.541407348
Short name T164
Test name
Test status
Simulation time 116208276 ps
CPU time 1.08 seconds
Started May 28 01:37:46 PM PDT 24
Finished May 28 01:37:49 PM PDT 24
Peak memory 200440 kb
Host smart-4609fc29-cbae-4746-b228-253afc8d2549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541407348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.541407348
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.872364828
Short name T115
Test name
Test status
Simulation time 11895410623 ps
CPU time 49.8 seconds
Started May 28 01:37:44 PM PDT 24
Finished May 28 01:38:37 PM PDT 24
Peak memory 209036 kb
Host smart-5ec5a37d-26ae-423f-9d3a-28f01ea5b36f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872364828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.872364828
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1663758054
Short name T26
Test name
Test status
Simulation time 2363424741 ps
CPU time 8.34 seconds
Started May 28 01:39:00 PM PDT 24
Finished May 28 01:39:15 PM PDT 24
Peak memory 218224 kb
Host smart-ba437e16-36af-4ff1-852d-2f5bd463813e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663758054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1663758054
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1878845357
Short name T127
Test name
Test status
Simulation time 511995590 ps
CPU time 1.91 seconds
Started May 28 01:36:52 PM PDT 24
Finished May 28 01:36:58 PM PDT 24
Peak memory 200652 kb
Host smart-9d62e738-c8d8-4135-94d9-dcfad9ae09c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878845357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1878845357
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1613644349
Short name T564
Test name
Test status
Simulation time 429194649 ps
CPU time 2.96 seconds
Started May 28 01:36:53 PM PDT 24
Finished May 28 01:36:59 PM PDT 24
Peak memory 208784 kb
Host smart-255abeba-06ec-426a-8041-7d1f59d342ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613644349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1613644349
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2674119009
Short name T177
Test name
Test status
Simulation time 84408125 ps
CPU time 0.84 seconds
Started May 28 01:37:46 PM PDT 24
Finished May 28 01:37:49 PM PDT 24
Peak memory 200408 kb
Host smart-77a0c98b-3b46-47ef-9782-20c7ef38efa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674119009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2674119009
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.641899212
Short name T126
Test name
Test status
Simulation time 772699770 ps
CPU time 2.91 seconds
Started May 28 01:36:44 PM PDT 24
Finished May 28 01:36:50 PM PDT 24
Peak memory 200556 kb
Host smart-e3886eb7-ab8f-4eaf-8561-355521c74c7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641899212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
641899212
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.656096840
Short name T117
Test name
Test status
Simulation time 144198827 ps
CPU time 1.14 seconds
Started May 28 01:36:53 PM PDT 24
Finished May 28 01:36:57 PM PDT 24
Peak memory 200332 kb
Host smart-b0ce1fc3-09a2-4274-a590-c93ceb63aa0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656096840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.656096840
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1600645437
Short name T15
Test name
Test status
Simulation time 189023759 ps
CPU time 0.86 seconds
Started May 28 01:37:39 PM PDT 24
Finished May 28 01:37:43 PM PDT 24
Peak memory 200224 kb
Host smart-7182a963-3576-417f-860f-0be9a93b4233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600645437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1600645437
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3752074289
Short name T6
Test name
Test status
Simulation time 1220964454 ps
CPU time 5.49 seconds
Started May 28 01:37:36 PM PDT 24
Finished May 28 01:37:42 PM PDT 24
Peak memory 218052 kb
Host smart-a7f27b74-7bc5-427f-9bd4-f24c06ab63d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752074289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3752074289
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.65869777
Short name T552
Test name
Test status
Simulation time 115038672 ps
CPU time 1.46 seconds
Started May 28 01:36:30 PM PDT 24
Finished May 28 01:36:35 PM PDT 24
Peak memory 200524 kb
Host smart-f0e0cf50-6cf5-4f21-834c-f2dba79b516e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65869777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.65869777
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.360565527
Short name T558
Test name
Test status
Simulation time 2305755825 ps
CPU time 11.45 seconds
Started May 28 01:36:31 PM PDT 24
Finished May 28 01:36:47 PM PDT 24
Peak memory 216932 kb
Host smart-e30fc508-8d67-4498-9e17-bb5fda8ca4e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360565527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.360565527
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1091704683
Short name T545
Test name
Test status
Simulation time 149331903 ps
CPU time 0.95 seconds
Started May 28 01:36:30 PM PDT 24
Finished May 28 01:36:35 PM PDT 24
Peak memory 200348 kb
Host smart-877d75e7-a2a8-449e-af91-c2e5cba16356
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091704683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
091704683
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2513930214
Short name T134
Test name
Test status
Simulation time 210663260 ps
CPU time 1.32 seconds
Started May 28 01:36:43 PM PDT 24
Finished May 28 01:36:49 PM PDT 24
Peak memory 208628 kb
Host smart-4e9eaaf7-3e96-4fda-a671-e30561c8e5b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513930214 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2513930214
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.298696188
Short name T559
Test name
Test status
Simulation time 63453033 ps
CPU time 0.82 seconds
Started May 28 01:36:30 PM PDT 24
Finished May 28 01:36:34 PM PDT 24
Peak memory 200356 kb
Host smart-00967c4b-0ed8-4c18-8ab0-5230609b4623
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298696188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.298696188
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3227445331
Short name T582
Test name
Test status
Simulation time 219820902 ps
CPU time 1.52 seconds
Started May 28 01:36:42 PM PDT 24
Finished May 28 01:36:47 PM PDT 24
Peak memory 200656 kb
Host smart-01803e31-14f0-4581-ad20-397765fd26e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227445331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3227445331
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.488414666
Short name T131
Test name
Test status
Simulation time 170617845 ps
CPU time 2.45 seconds
Started May 28 01:36:32 PM PDT 24
Finished May 28 01:36:38 PM PDT 24
Peak memory 211528 kb
Host smart-3b443322-f9d3-48aa-b3f5-37adaf2a5aba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488414666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.488414666
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.141339926
Short name T592
Test name
Test status
Simulation time 496152700 ps
CPU time 1.9 seconds
Started May 28 01:36:31 PM PDT 24
Finished May 28 01:36:37 PM PDT 24
Peak memory 200636 kb
Host smart-91efa8c4-6f26-4cf2-b94a-f66b71ecc633
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141339926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.
141339926
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3604413347
Short name T555
Test name
Test status
Simulation time 105038716 ps
CPU time 1.38 seconds
Started May 28 01:36:44 PM PDT 24
Finished May 28 01:36:49 PM PDT 24
Peak memory 200532 kb
Host smart-5687882e-6920-4d5b-9b07-a39782d56a3f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604413347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
604413347
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2855093636
Short name T543
Test name
Test status
Simulation time 1176789109 ps
CPU time 5.7 seconds
Started May 28 01:36:41 PM PDT 24
Finished May 28 01:36:50 PM PDT 24
Peak memory 200536 kb
Host smart-6eca0f48-1626-40b2-8f5d-2210da1fe1cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855093636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
855093636
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.132599918
Short name T546
Test name
Test status
Simulation time 109656146 ps
CPU time 0.85 seconds
Started May 28 01:36:44 PM PDT 24
Finished May 28 01:36:48 PM PDT 24
Peak memory 200356 kb
Host smart-937b5865-8daa-457f-b838-3114a6c7f189
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132599918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.132599918
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1302237671
Short name T571
Test name
Test status
Simulation time 207619354 ps
CPU time 1.31 seconds
Started May 28 01:36:42 PM PDT 24
Finished May 28 01:36:47 PM PDT 24
Peak memory 208680 kb
Host smart-2aa92214-c376-48fd-acf5-120f447d54f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302237671 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1302237671
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.346990897
Short name T593
Test name
Test status
Simulation time 76064354 ps
CPU time 0.83 seconds
Started May 28 01:36:43 PM PDT 24
Finished May 28 01:36:48 PM PDT 24
Peak memory 200268 kb
Host smart-5c3f124a-e1b1-4e73-a607-fb091f5cec54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346990897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.346990897
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2528409514
Short name T568
Test name
Test status
Simulation time 129864235 ps
CPU time 1.16 seconds
Started May 28 01:36:44 PM PDT 24
Finished May 28 01:36:49 PM PDT 24
Peak memory 200344 kb
Host smart-307c17ff-3385-4739-95cf-7992a0d81834
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528409514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2528409514
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.713083949
Short name T549
Test name
Test status
Simulation time 300527787 ps
CPU time 2.41 seconds
Started May 28 01:36:41 PM PDT 24
Finished May 28 01:36:45 PM PDT 24
Peak memory 216848 kb
Host smart-7722b05b-1f0e-41c2-970a-36c0c5448dc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713083949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.713083949
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.776555532
Short name T556
Test name
Test status
Simulation time 465211071 ps
CPU time 1.99 seconds
Started May 28 01:36:44 PM PDT 24
Finished May 28 01:36:49 PM PDT 24
Peak memory 200572 kb
Host smart-90b8cb29-8c42-4ad6-b8d7-2a8987311328
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776555532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
776555532
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1891660228
Short name T600
Test name
Test status
Simulation time 105484016 ps
CPU time 0.94 seconds
Started May 28 01:36:52 PM PDT 24
Finished May 28 01:36:56 PM PDT 24
Peak memory 200456 kb
Host smart-064e677a-60ee-455e-87ea-a18c4799a2fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891660228 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1891660228
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2685008586
Short name T541
Test name
Test status
Simulation time 74863733 ps
CPU time 0.82 seconds
Started May 28 01:36:54 PM PDT 24
Finished May 28 01:36:59 PM PDT 24
Peak memory 200212 kb
Host smart-4648cd50-acbd-4520-9d43-faafcba40425
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685008586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2685008586
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3083920828
Short name T589
Test name
Test status
Simulation time 273529498 ps
CPU time 2.16 seconds
Started May 28 01:36:56 PM PDT 24
Finished May 28 01:37:02 PM PDT 24
Peak memory 208780 kb
Host smart-722e468d-9942-4fbd-b548-4c565c981565
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083920828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3083920828
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3291282601
Short name T130
Test name
Test status
Simulation time 527826342 ps
CPU time 1.99 seconds
Started May 28 01:36:52 PM PDT 24
Finished May 28 01:36:57 PM PDT 24
Peak memory 200580 kb
Host smart-5ed547e2-9a04-4847-be28-f21e9fb37444
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291282601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3291282601
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.255822923
Short name T598
Test name
Test status
Simulation time 133916026 ps
CPU time 1.1 seconds
Started May 28 01:36:53 PM PDT 24
Finished May 28 01:36:57 PM PDT 24
Peak memory 210216 kb
Host smart-1e46c101-6ab2-4456-8194-75a9e54e7cda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255822923 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.255822923
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1992370910
Short name T561
Test name
Test status
Simulation time 73196674 ps
CPU time 0.84 seconds
Started May 28 01:36:54 PM PDT 24
Finished May 28 01:36:59 PM PDT 24
Peak memory 200364 kb
Host smart-80fb7042-b0a4-4357-baf0-5f31735c25c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992370910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1992370910
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1329278225
Short name T578
Test name
Test status
Simulation time 135245733 ps
CPU time 1.28 seconds
Started May 28 01:36:52 PM PDT 24
Finished May 28 01:36:55 PM PDT 24
Peak memory 200508 kb
Host smart-4a8eeb24-666e-4177-85bc-627319013111
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329278225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1329278225
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.766482829
Short name T102
Test name
Test status
Simulation time 471871120 ps
CPU time 2.86 seconds
Started May 28 01:36:55 PM PDT 24
Finished May 28 01:37:02 PM PDT 24
Peak memory 208792 kb
Host smart-3bb20c18-accf-4135-92ec-afd952241c6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766482829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.766482829
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.80076795
Short name T576
Test name
Test status
Simulation time 488030065 ps
CPU time 1.86 seconds
Started May 28 01:36:58 PM PDT 24
Finished May 28 01:37:03 PM PDT 24
Peak memory 200528 kb
Host smart-77a9a3dc-2e2f-4160-b4ce-b2ef0717388e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80076795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err.80076795
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.230836044
Short name T617
Test name
Test status
Simulation time 208620364 ps
CPU time 1.39 seconds
Started May 28 01:37:00 PM PDT 24
Finished May 28 01:37:04 PM PDT 24
Peak memory 208596 kb
Host smart-9cc99145-8af4-4d35-8505-fb39e812dcee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230836044 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.230836044
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3470946975
Short name T618
Test name
Test status
Simulation time 60952991 ps
CPU time 0.78 seconds
Started May 28 01:36:55 PM PDT 24
Finished May 28 01:36:59 PM PDT 24
Peak memory 200356 kb
Host smart-fb77f03a-5039-49f0-b03d-e77ab53ad892
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470946975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3470946975
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.486311917
Short name T588
Test name
Test status
Simulation time 250525651 ps
CPU time 1.6 seconds
Started May 28 01:36:56 PM PDT 24
Finished May 28 01:37:02 PM PDT 24
Peak memory 200588 kb
Host smart-41508ff2-c0eb-4ede-a8f2-34c1ee69fc61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486311917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.486311917
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.793280628
Short name T602
Test name
Test status
Simulation time 484454594 ps
CPU time 2.06 seconds
Started May 28 01:36:55 PM PDT 24
Finished May 28 01:37:01 PM PDT 24
Peak memory 200604 kb
Host smart-c244d81f-a924-44b5-8ee7-e3706aae0bf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793280628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.793280628
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1168477922
Short name T73
Test name
Test status
Simulation time 117078339 ps
CPU time 0.95 seconds
Started May 28 01:36:53 PM PDT 24
Finished May 28 01:36:57 PM PDT 24
Peak memory 200460 kb
Host smart-7043b4df-9179-496b-8a9d-3094829155be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168477922 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.1168477922
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2557087764
Short name T577
Test name
Test status
Simulation time 59146858 ps
CPU time 0.75 seconds
Started May 28 01:36:54 PM PDT 24
Finished May 28 01:36:59 PM PDT 24
Peak memory 200296 kb
Host smart-974bf766-62dc-4809-b070-d271944efe6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557087764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2557087764
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.744567591
Short name T581
Test name
Test status
Simulation time 122910137 ps
CPU time 1.22 seconds
Started May 28 01:36:54 PM PDT 24
Finished May 28 01:36:59 PM PDT 24
Peak memory 200652 kb
Host smart-88924364-5cb5-4e54-8140-3015faaceda7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744567591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.744567591
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1982874785
Short name T133
Test name
Test status
Simulation time 214373380 ps
CPU time 1.69 seconds
Started May 28 01:36:54 PM PDT 24
Finished May 28 01:37:00 PM PDT 24
Peak memory 208784 kb
Host smart-b0f6685c-cd62-4217-b299-f1cebc698524
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982874785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1982874785
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1735564433
Short name T67
Test name
Test status
Simulation time 120615917 ps
CPU time 1.05 seconds
Started May 28 01:36:55 PM PDT 24
Finished May 28 01:37:00 PM PDT 24
Peak memory 200440 kb
Host smart-cbd90e00-0a31-4a9e-bbab-0ee81f98d0b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735564433 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.1735564433
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3874626576
Short name T118
Test name
Test status
Simulation time 77246992 ps
CPU time 0.87 seconds
Started May 28 01:36:54 PM PDT 24
Finished May 28 01:36:59 PM PDT 24
Peak memory 200272 kb
Host smart-74bafb7e-a2f3-4b22-bcb8-fc328dfe38e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874626576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3874626576
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2654068355
Short name T619
Test name
Test status
Simulation time 103910446 ps
CPU time 1.28 seconds
Started May 28 01:36:53 PM PDT 24
Finished May 28 01:36:58 PM PDT 24
Peak memory 200584 kb
Host smart-ec292493-97fe-41fe-bc35-6cba63490371
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654068355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2654068355
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2628154280
Short name T570
Test name
Test status
Simulation time 240029278 ps
CPU time 1.7 seconds
Started May 28 01:36:52 PM PDT 24
Finished May 28 01:36:57 PM PDT 24
Peak memory 208696 kb
Host smart-194d2fb9-100a-451e-9b3a-07fe232e7854
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628154280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2628154280
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1297577986
Short name T590
Test name
Test status
Simulation time 125482830 ps
CPU time 1.13 seconds
Started May 28 01:36:55 PM PDT 24
Finished May 28 01:37:01 PM PDT 24
Peak memory 208616 kb
Host smart-ef4bd076-9f60-4c71-8ec5-7bee3ecade6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297577986 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1297577986
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2964845941
Short name T591
Test name
Test status
Simulation time 70775804 ps
CPU time 0.81 seconds
Started May 28 01:36:55 PM PDT 24
Finished May 28 01:37:00 PM PDT 24
Peak memory 200244 kb
Host smart-a4f33cb4-e485-4c15-bd4e-a9e4318e678d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964845941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2964845941
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.744067993
Short name T124
Test name
Test status
Simulation time 84330863 ps
CPU time 1.02 seconds
Started May 28 01:36:59 PM PDT 24
Finished May 28 01:37:03 PM PDT 24
Peak memory 200452 kb
Host smart-c8d8fddc-b021-4430-b683-697fdcd15ea4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744067993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.744067993
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3319480749
Short name T596
Test name
Test status
Simulation time 498446775 ps
CPU time 3.59 seconds
Started May 28 01:36:55 PM PDT 24
Finished May 28 01:37:03 PM PDT 24
Peak memory 216916 kb
Host smart-78e66f79-52b3-4fda-8845-78c0fb841910
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319480749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3319480749
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3594765391
Short name T128
Test name
Test status
Simulation time 872044278 ps
CPU time 3.17 seconds
Started May 28 01:36:59 PM PDT 24
Finished May 28 01:37:05 PM PDT 24
Peak memory 200644 kb
Host smart-6d81dbcc-debe-4af9-80bf-5cba3b645fd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594765391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3594765391
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3444374999
Short name T607
Test name
Test status
Simulation time 129162779 ps
CPU time 1.02 seconds
Started May 28 01:36:55 PM PDT 24
Finished May 28 01:37:00 PM PDT 24
Peak memory 200480 kb
Host smart-12952dcf-a20e-46e7-90b1-150732fad7f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444374999 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3444374999
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2136606011
Short name T572
Test name
Test status
Simulation time 76326181 ps
CPU time 0.82 seconds
Started May 28 01:36:56 PM PDT 24
Finished May 28 01:37:01 PM PDT 24
Peak memory 200360 kb
Host smart-5fd7440f-ed69-40a3-ace3-832c0b8d5cbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136606011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2136606011
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1158174992
Short name T563
Test name
Test status
Simulation time 251067187 ps
CPU time 1.74 seconds
Started May 28 01:36:59 PM PDT 24
Finished May 28 01:37:04 PM PDT 24
Peak memory 200516 kb
Host smart-bbd38b7f-e6bf-4d86-9c1d-511bfd3a89ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158174992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1158174992
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2754177903
Short name T565
Test name
Test status
Simulation time 424609538 ps
CPU time 3.06 seconds
Started May 28 01:36:59 PM PDT 24
Finished May 28 01:37:05 PM PDT 24
Peak memory 208840 kb
Host smart-1f8beb5a-bed0-40a6-aa96-c656cbf9bac9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754177903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2754177903
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.912584055
Short name T614
Test name
Test status
Simulation time 799420281 ps
CPU time 3.01 seconds
Started May 28 01:36:56 PM PDT 24
Finished May 28 01:37:03 PM PDT 24
Peak memory 200600 kb
Host smart-9d205c50-8611-47db-82d3-cf810d9ba7d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912584055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err
.912584055
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.536112681
Short name T560
Test name
Test status
Simulation time 128902200 ps
CPU time 1.17 seconds
Started May 28 01:36:55 PM PDT 24
Finished May 28 01:37:00 PM PDT 24
Peak memory 209700 kb
Host smart-5ed9ec62-500d-462e-9235-a553d8eff8e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536112681 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.536112681
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1728954247
Short name T579
Test name
Test status
Simulation time 62743582 ps
CPU time 0.79 seconds
Started May 28 01:36:59 PM PDT 24
Finished May 28 01:37:03 PM PDT 24
Peak memory 199960 kb
Host smart-69d6a970-a604-49e9-a5bb-313ee1e51d10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728954247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1728954247
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.886680215
Short name T120
Test name
Test status
Simulation time 99368720 ps
CPU time 1.2 seconds
Started May 28 01:36:57 PM PDT 24
Finished May 28 01:37:02 PM PDT 24
Peak memory 200572 kb
Host smart-7e8ea3bd-2250-4c2e-86da-88ae7f4fb0b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886680215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.886680215
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3610277599
Short name T97
Test name
Test status
Simulation time 355899609 ps
CPU time 2.72 seconds
Started May 28 01:36:54 PM PDT 24
Finished May 28 01:37:01 PM PDT 24
Peak memory 216852 kb
Host smart-6bce206f-6653-4f2a-a5ea-a172a0026672
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610277599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3610277599
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3590833405
Short name T599
Test name
Test status
Simulation time 1215952485 ps
CPU time 3.65 seconds
Started May 28 01:36:52 PM PDT 24
Finished May 28 01:36:59 PM PDT 24
Peak memory 200652 kb
Host smart-6df75693-6439-4cba-acc1-904212b61757
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590833405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3590833405
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2633568197
Short name T615
Test name
Test status
Simulation time 128747428 ps
CPU time 1.42 seconds
Started May 28 01:37:06 PM PDT 24
Finished May 28 01:37:09 PM PDT 24
Peak memory 208860 kb
Host smart-0243c4d9-780f-49fd-a304-8bd26dae01d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633568197 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2633568197
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3251538102
Short name T587
Test name
Test status
Simulation time 93319486 ps
CPU time 0.82 seconds
Started May 28 01:36:55 PM PDT 24
Finished May 28 01:37:00 PM PDT 24
Peak memory 200344 kb
Host smart-ee5b5b60-c40c-4532-bd15-6414a1c08dab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251538102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3251538102
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2914690876
Short name T604
Test name
Test status
Simulation time 72275060 ps
CPU time 0.95 seconds
Started May 28 01:37:04 PM PDT 24
Finished May 28 01:37:06 PM PDT 24
Peak memory 200412 kb
Host smart-cd50ef1a-5e95-42c6-bb83-31951a8fc73b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914690876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2914690876
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3518551093
Short name T69
Test name
Test status
Simulation time 139530508 ps
CPU time 1.89 seconds
Started May 28 01:36:55 PM PDT 24
Finished May 28 01:37:02 PM PDT 24
Peak memory 208796 kb
Host smart-d04c3f38-d312-406e-930e-7d2638d29dd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518551093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3518551093
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.911919210
Short name T606
Test name
Test status
Simulation time 957237409 ps
CPU time 3.62 seconds
Started May 28 01:36:53 PM PDT 24
Finished May 28 01:37:01 PM PDT 24
Peak memory 200540 kb
Host smart-bc4c7dc9-6c4d-44a5-b3c7-bb671cf7353a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911919210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err
.911919210
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2792598563
Short name T548
Test name
Test status
Simulation time 178745627 ps
CPU time 1.27 seconds
Started May 28 01:37:07 PM PDT 24
Finished May 28 01:37:10 PM PDT 24
Peak memory 200320 kb
Host smart-3e8625ef-4f71-4e0c-9dd1-3cefd0b62558
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792598563 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2792598563
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2428019264
Short name T542
Test name
Test status
Simulation time 88649302 ps
CPU time 0.87 seconds
Started May 28 01:37:12 PM PDT 24
Finished May 28 01:37:14 PM PDT 24
Peak memory 200280 kb
Host smart-6be4b0e6-c19c-4008-9c0f-a997aadcbd11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428019264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2428019264
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3788824959
Short name T575
Test name
Test status
Simulation time 259570448 ps
CPU time 1.72 seconds
Started May 28 01:37:05 PM PDT 24
Finished May 28 01:37:09 PM PDT 24
Peak memory 200588 kb
Host smart-5f2ba91b-1ba2-410c-aa55-800e8e06d42b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788824959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3788824959
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.455409028
Short name T583
Test name
Test status
Simulation time 225244778 ps
CPU time 1.7 seconds
Started May 28 01:37:06 PM PDT 24
Finished May 28 01:37:09 PM PDT 24
Peak memory 200508 kb
Host smart-951802f0-2871-4990-91d1-544e3fd6fead
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455409028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.455409028
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2498651699
Short name T138
Test name
Test status
Simulation time 477028407 ps
CPU time 1.93 seconds
Started May 28 01:37:08 PM PDT 24
Finished May 28 01:37:12 PM PDT 24
Peak memory 208796 kb
Host smart-1c9cdbd9-92e3-49b8-aea9-f3c38e975ac1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498651699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2498651699
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1397258736
Short name T557
Test name
Test status
Simulation time 112492123 ps
CPU time 1.29 seconds
Started May 28 01:36:40 PM PDT 24
Finished May 28 01:36:42 PM PDT 24
Peak memory 200428 kb
Host smart-268c1662-1761-424f-9f1e-b3e1be2d676a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397258736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1
397258736
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1712114381
Short name T550
Test name
Test status
Simulation time 271233973 ps
CPU time 3.18 seconds
Started May 28 01:36:45 PM PDT 24
Finished May 28 01:36:52 PM PDT 24
Peak memory 200520 kb
Host smart-f7e8279b-ae23-4956-b5d0-693964525905
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712114381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
712114381
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.248142229
Short name T551
Test name
Test status
Simulation time 147828237 ps
CPU time 1.01 seconds
Started May 28 01:36:42 PM PDT 24
Finished May 28 01:36:47 PM PDT 24
Peak memory 200356 kb
Host smart-68458023-8577-4c8e-92cf-7262f2ece430
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248142229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.248142229
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3430407432
Short name T586
Test name
Test status
Simulation time 192816060 ps
CPU time 2.02 seconds
Started May 28 01:36:44 PM PDT 24
Finished May 28 01:36:50 PM PDT 24
Peak memory 208840 kb
Host smart-15364b60-364f-4e38-9e50-2bd7c1330936
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430407432 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.3430407432
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1572472991
Short name T65
Test name
Test status
Simulation time 80495533 ps
CPU time 0.93 seconds
Started May 28 01:36:41 PM PDT 24
Finished May 28 01:36:44 PM PDT 24
Peak memory 200264 kb
Host smart-e7e3b9ec-9acb-464b-af6d-86d5797c7eac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572472991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1572472991
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3089191667
Short name T603
Test name
Test status
Simulation time 256742988 ps
CPU time 1.58 seconds
Started May 28 01:36:42 PM PDT 24
Finished May 28 01:36:47 PM PDT 24
Peak memory 200608 kb
Host smart-9f0437ad-1fbd-4f17-869b-3d928027d867
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089191667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3089191667
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2198630955
Short name T68
Test name
Test status
Simulation time 264329697 ps
CPU time 2.15 seconds
Started May 28 01:36:43 PM PDT 24
Finished May 28 01:36:49 PM PDT 24
Peak memory 216820 kb
Host smart-50680418-eaca-4e7b-a22c-2dace892b857
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198630955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2198630955
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1341172487
Short name T612
Test name
Test status
Simulation time 899281230 ps
CPU time 3.1 seconds
Started May 28 01:36:47 PM PDT 24
Finished May 28 01:36:53 PM PDT 24
Peak memory 200608 kb
Host smart-83f9a79c-e7f6-43f7-aa58-c33fad1ccea2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341172487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1341172487
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1675037584
Short name T544
Test name
Test status
Simulation time 146200210 ps
CPU time 1.97 seconds
Started May 28 01:36:43 PM PDT 24
Finished May 28 01:36:49 PM PDT 24
Peak memory 200544 kb
Host smart-acb4dc8b-5400-41cf-b5f7-2a64fbe5a0be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675037584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
675037584
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1615950652
Short name T569
Test name
Test status
Simulation time 482993415 ps
CPU time 6.13 seconds
Started May 28 01:36:42 PM PDT 24
Finished May 28 01:36:51 PM PDT 24
Peak memory 216784 kb
Host smart-3dd44464-5be9-4478-b889-a6520f81acaf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615950652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
615950652
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3779701698
Short name T605
Test name
Test status
Simulation time 142985075 ps
CPU time 0.95 seconds
Started May 28 01:36:47 PM PDT 24
Finished May 28 01:36:51 PM PDT 24
Peak memory 200340 kb
Host smart-3b76e823-bba0-43b6-875f-c0e411138532
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779701698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
779701698
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2499646286
Short name T595
Test name
Test status
Simulation time 175450643 ps
CPU time 1.6 seconds
Started May 28 01:36:42 PM PDT 24
Finished May 28 01:36:47 PM PDT 24
Peak memory 208824 kb
Host smart-f90ca4d0-26b4-4db5-8cf8-932de64047db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499646286 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2499646286
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1625305
Short name T573
Test name
Test status
Simulation time 73624293 ps
CPU time 0.9 seconds
Started May 28 01:36:41 PM PDT 24
Finished May 28 01:36:45 PM PDT 24
Peak memory 200296 kb
Host smart-9220ba2a-0969-4c1d-a597-1aad2eb34d5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1625305
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2934953000
Short name T125
Test name
Test status
Simulation time 262699456 ps
CPU time 1.62 seconds
Started May 28 01:36:43 PM PDT 24
Finished May 28 01:36:48 PM PDT 24
Peak memory 200592 kb
Host smart-697052d6-3987-4b90-8a2a-370756432ec1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934953000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2934953000
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.52859014
Short name T98
Test name
Test status
Simulation time 470705442 ps
CPU time 1.88 seconds
Started May 28 01:36:45 PM PDT 24
Finished May 28 01:36:51 PM PDT 24
Peak memory 200632 kb
Host smart-580d328b-739a-4a8b-8db9-971dae157fc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52859014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.52859014
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1789543974
Short name T611
Test name
Test status
Simulation time 116355422 ps
CPU time 1.43 seconds
Started May 28 01:36:43 PM PDT 24
Finished May 28 01:36:48 PM PDT 24
Peak memory 200432 kb
Host smart-53c52d83-1869-4749-b01f-f4fd288c2796
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789543974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
789543974
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.181722593
Short name T585
Test name
Test status
Simulation time 267869369 ps
CPU time 3.19 seconds
Started May 28 01:36:42 PM PDT 24
Finished May 28 01:36:48 PM PDT 24
Peak memory 200540 kb
Host smart-1f68559c-f485-4c97-9fa2-57a33fd788c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181722593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.181722593
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3636036641
Short name T567
Test name
Test status
Simulation time 101646625 ps
CPU time 0.88 seconds
Started May 28 01:36:44 PM PDT 24
Finished May 28 01:36:49 PM PDT 24
Peak memory 200272 kb
Host smart-066654bc-37b5-4be9-addf-8f3383e206a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636036641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3
636036641
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2788389586
Short name T616
Test name
Test status
Simulation time 131530032 ps
CPU time 1.01 seconds
Started May 28 01:36:44 PM PDT 24
Finished May 28 01:36:49 PM PDT 24
Peak memory 200472 kb
Host smart-b3a7044d-c3ae-4d71-bc05-e065c5526b6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788389586 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2788389586
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.907078237
Short name T601
Test name
Test status
Simulation time 75607925 ps
CPU time 0.79 seconds
Started May 28 01:36:40 PM PDT 24
Finished May 28 01:36:43 PM PDT 24
Peak memory 200356 kb
Host smart-d6e3a23f-f3b5-4cdd-a578-fe527938e97f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907078237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.907078237
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3842806535
Short name T121
Test name
Test status
Simulation time 190079260 ps
CPU time 1.48 seconds
Started May 28 01:36:45 PM PDT 24
Finished May 28 01:36:50 PM PDT 24
Peak memory 200652 kb
Host smart-9c341898-bda8-4889-862f-1c617b0bff95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842806535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3842806535
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3000748250
Short name T613
Test name
Test status
Simulation time 104537293 ps
CPU time 1.52 seconds
Started May 28 01:36:40 PM PDT 24
Finished May 28 01:36:43 PM PDT 24
Peak memory 208848 kb
Host smart-2e5689a1-e41f-4257-9dab-3c0649b1aa70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000748250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3000748250
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3967544540
Short name T129
Test name
Test status
Simulation time 466710239 ps
CPU time 1.85 seconds
Started May 28 01:36:44 PM PDT 24
Finished May 28 01:36:50 PM PDT 24
Peak memory 200620 kb
Host smart-203ca53c-7a72-4add-983c-b076365588c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967544540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3967544540
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1783478242
Short name T101
Test name
Test status
Simulation time 120690286 ps
CPU time 0.98 seconds
Started May 28 01:36:42 PM PDT 24
Finished May 28 01:36:47 PM PDT 24
Peak memory 200460 kb
Host smart-c93e8d77-c243-41d9-8493-de696c6244a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783478242 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1783478242
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2634514729
Short name T566
Test name
Test status
Simulation time 81239844 ps
CPU time 0.84 seconds
Started May 28 01:36:44 PM PDT 24
Finished May 28 01:36:49 PM PDT 24
Peak memory 200200 kb
Host smart-176e522c-b014-4bce-98b4-f9db46fcddfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634514729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2634514729
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4190764552
Short name T594
Test name
Test status
Simulation time 148400256 ps
CPU time 1.14 seconds
Started May 28 01:36:42 PM PDT 24
Finished May 28 01:36:46 PM PDT 24
Peak memory 200332 kb
Host smart-1053e974-f6b3-47db-b7bd-579ebabac880
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190764552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.4190764552
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2108781096
Short name T609
Test name
Test status
Simulation time 207500471 ps
CPU time 1.63 seconds
Started May 28 01:36:47 PM PDT 24
Finished May 28 01:36:52 PM PDT 24
Peak memory 208792 kb
Host smart-b92062df-b0be-418e-aaea-a33c6b164dab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108781096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2108781096
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1101317294
Short name T139
Test name
Test status
Simulation time 1034574637 ps
CPU time 3.2 seconds
Started May 28 01:36:42 PM PDT 24
Finished May 28 01:36:49 PM PDT 24
Peak memory 200600 kb
Host smart-e11c4152-75b0-4264-a971-eac2ac9507f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101317294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1101317294
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.53521555
Short name T554
Test name
Test status
Simulation time 205897950 ps
CPU time 1.29 seconds
Started May 28 01:36:43 PM PDT 24
Finished May 28 01:36:48 PM PDT 24
Peak memory 208592 kb
Host smart-0f450159-2c26-4564-9025-16b61e68f958
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53521555 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.53521555
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.132578350
Short name T547
Test name
Test status
Simulation time 73986488 ps
CPU time 0.86 seconds
Started May 28 01:36:39 PM PDT 24
Finished May 28 01:36:41 PM PDT 24
Peak memory 200352 kb
Host smart-4af429a1-34a6-40d1-9c41-4fd7edf86c76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132578350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.132578350
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.745249010
Short name T119
Test name
Test status
Simulation time 115580671 ps
CPU time 1.03 seconds
Started May 28 01:36:41 PM PDT 24
Finished May 28 01:36:45 PM PDT 24
Peak memory 200332 kb
Host smart-c682d8c1-9079-49f7-ac9f-207c964ea9d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745249010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.745249010
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.4213703145
Short name T99
Test name
Test status
Simulation time 302114763 ps
CPU time 1.9 seconds
Started May 28 01:36:42 PM PDT 24
Finished May 28 01:36:47 PM PDT 24
Peak memory 200604 kb
Host smart-d69d1b6d-6ba2-4e65-9f79-d5478fdf2829
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213703145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.4213703145
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1133144584
Short name T140
Test name
Test status
Simulation time 486202904 ps
CPU time 2.04 seconds
Started May 28 01:36:45 PM PDT 24
Finished May 28 01:36:51 PM PDT 24
Peak memory 200552 kb
Host smart-b49d2b31-47ca-44c1-b003-9b4b3998fb43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133144584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.1133144584
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1546700424
Short name T562
Test name
Test status
Simulation time 76705800 ps
CPU time 0.77 seconds
Started May 28 01:36:41 PM PDT 24
Finished May 28 01:36:44 PM PDT 24
Peak memory 200324 kb
Host smart-0a0d18d5-c7e4-466b-91e0-e436be4d5b71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546700424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1546700424
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2099700373
Short name T123
Test name
Test status
Simulation time 143331402 ps
CPU time 1.18 seconds
Started May 28 01:36:43 PM PDT 24
Finished May 28 01:36:48 PM PDT 24
Peak memory 200424 kb
Host smart-11fa412b-d652-4879-9be6-cf0155b7c6d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099700373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.2099700373
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.394630694
Short name T574
Test name
Test status
Simulation time 161439580 ps
CPU time 2.28 seconds
Started May 28 01:36:45 PM PDT 24
Finished May 28 01:36:51 PM PDT 24
Peak memory 216984 kb
Host smart-141129fc-229b-4ae5-91df-b7390cb79d3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394630694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.394630694
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.794252922
Short name T608
Test name
Test status
Simulation time 474070699 ps
CPU time 1.91 seconds
Started May 28 01:36:43 PM PDT 24
Finished May 28 01:36:48 PM PDT 24
Peak memory 200616 kb
Host smart-40516894-c770-4866-bacd-a15df1c498f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794252922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
794252922
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2085487314
Short name T597
Test name
Test status
Simulation time 99480202 ps
CPU time 0.93 seconds
Started May 28 01:36:42 PM PDT 24
Finished May 28 01:36:47 PM PDT 24
Peak memory 200376 kb
Host smart-9fdf465d-27c8-4e07-94c2-03ad0e3feb25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085487314 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2085487314
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3393070793
Short name T580
Test name
Test status
Simulation time 72486136 ps
CPU time 0.79 seconds
Started May 28 01:36:45 PM PDT 24
Finished May 28 01:36:49 PM PDT 24
Peak memory 200388 kb
Host smart-14284add-881e-4167-b156-eac35bd19016
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393070793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3393070793
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2771726484
Short name T66
Test name
Test status
Simulation time 209125770 ps
CPU time 1.46 seconds
Started May 28 01:36:42 PM PDT 24
Finished May 28 01:36:46 PM PDT 24
Peak memory 200536 kb
Host smart-3b9a5a34-0fd5-425f-b8fa-f97f50ec50fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771726484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.2771726484
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3659727321
Short name T132
Test name
Test status
Simulation time 302776553 ps
CPU time 2.17 seconds
Started May 28 01:36:41 PM PDT 24
Finished May 28 01:36:46 PM PDT 24
Peak memory 208700 kb
Host smart-891ca1d5-06e6-4ae4-883b-82717b5cde00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659727321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3659727321
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1419255250
Short name T553
Test name
Test status
Simulation time 123693224 ps
CPU time 1.02 seconds
Started May 28 01:36:52 PM PDT 24
Finished May 28 01:36:56 PM PDT 24
Peak memory 200332 kb
Host smart-a61eac48-852a-4c81-9c77-56237125d808
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419255250 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1419255250
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3518318869
Short name T584
Test name
Test status
Simulation time 74737770 ps
CPU time 0.86 seconds
Started May 28 01:36:54 PM PDT 24
Finished May 28 01:36:59 PM PDT 24
Peak memory 200268 kb
Host smart-94054934-1173-49a8-90ea-fa107b31817c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518318869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.3518318869
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2784652752
Short name T122
Test name
Test status
Simulation time 87854886 ps
CPU time 0.99 seconds
Started May 28 01:36:51 PM PDT 24
Finished May 28 01:36:54 PM PDT 24
Peak memory 200356 kb
Host smart-b454d2a1-cfae-4cf7-bd10-4c0e7417c16c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784652752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.2784652752
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1330002037
Short name T610
Test name
Test status
Simulation time 206833391 ps
CPU time 3.22 seconds
Started May 28 01:36:52 PM PDT 24
Finished May 28 01:36:58 PM PDT 24
Peak memory 216768 kb
Host smart-8b2a00fa-76e8-48d7-a4ac-c68baa3b6f28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330002037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1330002037
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3913414389
Short name T64
Test name
Test status
Simulation time 458915828 ps
CPU time 1.85 seconds
Started May 28 01:36:59 PM PDT 24
Finished May 28 01:37:04 PM PDT 24
Peak memory 200328 kb
Host smart-4dd9901e-cc06-46d8-a45e-2f27b2a5c531
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913414389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.3913414389
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3672068876
Short name T167
Test name
Test status
Simulation time 63485404 ps
CPU time 0.7 seconds
Started May 28 01:37:12 PM PDT 24
Finished May 28 01:37:14 PM PDT 24
Peak memory 200324 kb
Host smart-5fede8c8-8451-4592-874d-7bbc7f53b5ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672068876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3672068876
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.439349219
Short name T404
Test name
Test status
Simulation time 1886119678 ps
CPU time 7.52 seconds
Started May 28 01:37:04 PM PDT 24
Finished May 28 01:37:13 PM PDT 24
Peak memory 218152 kb
Host smart-3c9dbdb5-de7f-4080-9d55-4e7c3daf497b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439349219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.439349219
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3816206093
Short name T85
Test name
Test status
Simulation time 244240744 ps
CPU time 1.19 seconds
Started May 28 01:37:11 PM PDT 24
Finished May 28 01:37:14 PM PDT 24
Peak memory 217720 kb
Host smart-5d662c51-f690-434a-9584-0ad95fe1a7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816206093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3816206093
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3126037516
Short name T337
Test name
Test status
Simulation time 124162146 ps
CPU time 0.8 seconds
Started May 28 01:37:06 PM PDT 24
Finished May 28 01:37:08 PM PDT 24
Peak memory 200284 kb
Host smart-8afef847-b390-45ca-9e9a-b87777664b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126037516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3126037516
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.880492479
Short name T174
Test name
Test status
Simulation time 739170027 ps
CPU time 4.04 seconds
Started May 28 01:37:08 PM PDT 24
Finished May 28 01:37:14 PM PDT 24
Peak memory 200684 kb
Host smart-b4728f71-cbed-43f0-8c82-7c06bbff5649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880492479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.880492479
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.229899673
Short name T373
Test name
Test status
Simulation time 145982561 ps
CPU time 1.14 seconds
Started May 28 01:37:06 PM PDT 24
Finished May 28 01:37:09 PM PDT 24
Peak memory 200520 kb
Host smart-f8138103-eb84-416d-b9c6-d426e935a113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229899673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.229899673
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.3930498106
Short name T310
Test name
Test status
Simulation time 199789103 ps
CPU time 1.46 seconds
Started May 28 01:37:04 PM PDT 24
Finished May 28 01:37:07 PM PDT 24
Peak memory 200652 kb
Host smart-fcd3bf27-fcc0-4ac4-bffc-8d0e347be42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930498106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3930498106
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1631384527
Short name T322
Test name
Test status
Simulation time 3593107191 ps
CPU time 15.21 seconds
Started May 28 01:37:07 PM PDT 24
Finished May 28 01:37:24 PM PDT 24
Peak memory 200760 kb
Host smart-4b405243-53fc-42ee-8383-c4ac21cc5014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631384527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1631384527
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.4259438729
Short name T427
Test name
Test status
Simulation time 127958047 ps
CPU time 1.65 seconds
Started May 28 01:37:08 PM PDT 24
Finished May 28 01:37:12 PM PDT 24
Peak memory 200468 kb
Host smart-5dab6275-6e5b-4865-a09f-209c63357af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259438729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.4259438729
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.1254968834
Short name T251
Test name
Test status
Simulation time 153123163 ps
CPU time 1.11 seconds
Started May 28 01:37:12 PM PDT 24
Finished May 28 01:37:15 PM PDT 24
Peak memory 200436 kb
Host smart-f7644505-1097-4f85-962f-5e65c42e84cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254968834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1254968834
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.4007197984
Short name T39
Test name
Test status
Simulation time 58238602 ps
CPU time 0.74 seconds
Started May 28 01:37:09 PM PDT 24
Finished May 28 01:37:11 PM PDT 24
Peak memory 200328 kb
Host smart-281588ef-3a5d-4700-b702-e812b1bb6196
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007197984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.4007197984
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2947104661
Short name T478
Test name
Test status
Simulation time 1889758474 ps
CPU time 7.24 seconds
Started May 28 01:37:05 PM PDT 24
Finished May 28 01:37:14 PM PDT 24
Peak memory 222136 kb
Host smart-c9a007e6-106b-4f40-8b26-176926d5fdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947104661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2947104661
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3111836434
Short name T473
Test name
Test status
Simulation time 244827013 ps
CPU time 1.07 seconds
Started May 28 01:37:11 PM PDT 24
Finished May 28 01:37:14 PM PDT 24
Peak memory 217596 kb
Host smart-70db7962-c58a-47e7-a28e-173142e6bf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111836434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3111836434
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.1129976295
Short name T281
Test name
Test status
Simulation time 96696257 ps
CPU time 0.81 seconds
Started May 28 01:37:07 PM PDT 24
Finished May 28 01:37:09 PM PDT 24
Peak memory 200280 kb
Host smart-c2c55e51-c631-4377-a9a7-bc742601700e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129976295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.1129976295
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1392201525
Short name T114
Test name
Test status
Simulation time 1471009621 ps
CPU time 6.07 seconds
Started May 28 01:37:06 PM PDT 24
Finished May 28 01:37:13 PM PDT 24
Peak memory 200608 kb
Host smart-6324bad1-9fd9-4649-a422-a030cb310a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392201525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1392201525
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2624516297
Short name T75
Test name
Test status
Simulation time 8445564827 ps
CPU time 12.28 seconds
Started May 28 01:37:11 PM PDT 24
Finished May 28 01:37:25 PM PDT 24
Peak memory 217860 kb
Host smart-635df044-a3c4-4b29-a1e9-f6321efda736
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624516297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2624516297
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1810271855
Short name T361
Test name
Test status
Simulation time 150699796 ps
CPU time 1.19 seconds
Started May 28 01:37:06 PM PDT 24
Finished May 28 01:37:08 PM PDT 24
Peak memory 200504 kb
Host smart-a23d4762-aa24-412f-8b95-17f7f2dacbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810271855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1810271855
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.2350828966
Short name T156
Test name
Test status
Simulation time 121872767 ps
CPU time 1.19 seconds
Started May 28 01:37:06 PM PDT 24
Finished May 28 01:37:09 PM PDT 24
Peak memory 200700 kb
Host smart-dab47338-717b-4837-a7b8-1aec9c0f3581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350828966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2350828966
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.4279673793
Short name T53
Test name
Test status
Simulation time 9947567181 ps
CPU time 36.7 seconds
Started May 28 01:37:12 PM PDT 24
Finished May 28 01:37:50 PM PDT 24
Peak memory 200756 kb
Host smart-39031e84-5c3d-48af-85ec-d5b30ff8471c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279673793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.4279673793
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.948395114
Short name T291
Test name
Test status
Simulation time 109356426 ps
CPU time 1.43 seconds
Started May 28 01:37:07 PM PDT 24
Finished May 28 01:37:10 PM PDT 24
Peak memory 200460 kb
Host smart-4dc8a814-c89b-447f-8d67-0c552ab75a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948395114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.948395114
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3993233290
Short name T348
Test name
Test status
Simulation time 156191679 ps
CPU time 1.06 seconds
Started May 28 01:37:11 PM PDT 24
Finished May 28 01:37:14 PM PDT 24
Peak memory 200504 kb
Host smart-032a1f94-9fe5-4276-b487-21d7a6317f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993233290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3993233290
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.109263073
Short name T198
Test name
Test status
Simulation time 66822530 ps
CPU time 0.78 seconds
Started May 28 01:37:37 PM PDT 24
Finished May 28 01:37:38 PM PDT 24
Peak memory 200324 kb
Host smart-0723a5e9-1f8a-4289-bf9c-16e7f40ee13f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109263073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.109263073
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3671837446
Short name T48
Test name
Test status
Simulation time 1231870900 ps
CPU time 5.84 seconds
Started May 28 01:37:40 PM PDT 24
Finished May 28 01:37:49 PM PDT 24
Peak memory 218076 kb
Host smart-a6a6cd88-e6f2-4bf3-82ac-6a306f61f4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671837446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3671837446
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.4121911181
Short name T79
Test name
Test status
Simulation time 244875790 ps
CPU time 1.2 seconds
Started May 28 01:37:39 PM PDT 24
Finished May 28 01:37:43 PM PDT 24
Peak memory 217548 kb
Host smart-aa0e02df-01a2-44f3-ae8a-90d7306a2654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121911181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.4121911181
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.816905899
Short name T525
Test name
Test status
Simulation time 84369760 ps
CPU time 0.76 seconds
Started May 28 01:37:19 PM PDT 24
Finished May 28 01:37:21 PM PDT 24
Peak memory 200292 kb
Host smart-919a7a39-358e-4f18-ba8c-9b6a9eacefa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816905899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.816905899
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.408449350
Short name T283
Test name
Test status
Simulation time 1591866946 ps
CPU time 6.41 seconds
Started May 28 01:37:23 PM PDT 24
Finished May 28 01:37:32 PM PDT 24
Peak memory 200680 kb
Host smart-68d0ad40-6d79-4742-a3ee-c391233df8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408449350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.408449350
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1435467548
Short name T294
Test name
Test status
Simulation time 108106653 ps
CPU time 0.99 seconds
Started May 28 01:37:42 PM PDT 24
Finished May 28 01:37:47 PM PDT 24
Peak memory 200488 kb
Host smart-d98a19e9-343d-4b3d-9cf7-00e2c514a375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435467548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1435467548
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.601909865
Short name T260
Test name
Test status
Simulation time 198152821 ps
CPU time 1.38 seconds
Started May 28 01:37:23 PM PDT 24
Finished May 28 01:37:28 PM PDT 24
Peak memory 200712 kb
Host smart-56f2100e-a52c-499f-977a-2c50a4f5f891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601909865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.601909865
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2618815533
Short name T382
Test name
Test status
Simulation time 1653295844 ps
CPU time 6.59 seconds
Started May 28 01:37:41 PM PDT 24
Finished May 28 01:37:52 PM PDT 24
Peak memory 200740 kb
Host smart-4e1ff95b-0e05-4f05-b1da-38f32be9b702
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618815533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2618815533
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2416745807
Short name T221
Test name
Test status
Simulation time 137541377 ps
CPU time 1.68 seconds
Started May 28 01:37:37 PM PDT 24
Finished May 28 01:37:40 PM PDT 24
Peak memory 208684 kb
Host smart-5405e035-2c28-4ce4-8c5f-69faf6ce95ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416745807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2416745807
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.340952014
Short name T256
Test name
Test status
Simulation time 68864081 ps
CPU time 0.77 seconds
Started May 28 01:37:40 PM PDT 24
Finished May 28 01:37:45 PM PDT 24
Peak memory 200412 kb
Host smart-db2ead35-572f-4014-9a53-b927454249f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340952014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.340952014
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.15404006
Short name T532
Test name
Test status
Simulation time 92315143 ps
CPU time 0.89 seconds
Started May 28 01:37:37 PM PDT 24
Finished May 28 01:37:39 PM PDT 24
Peak memory 200264 kb
Host smart-2409bb40-6939-4381-ac35-57592eaabb1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15404006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.15404006
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2675261376
Short name T44
Test name
Test status
Simulation time 2359544182 ps
CPU time 9.39 seconds
Started May 28 01:37:38 PM PDT 24
Finished May 28 01:37:50 PM PDT 24
Peak memory 222104 kb
Host smart-ee691845-af06-4351-bd3b-cea2f6198150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675261376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2675261376
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1073129795
Short name T308
Test name
Test status
Simulation time 245866274 ps
CPU time 1.05 seconds
Started May 28 01:37:40 PM PDT 24
Finished May 28 01:37:45 PM PDT 24
Peak memory 217636 kb
Host smart-3a5b9ad9-0835-46f6-a9b2-15b6e0617e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073129795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1073129795
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1819639233
Short name T358
Test name
Test status
Simulation time 192416651 ps
CPU time 0.95 seconds
Started May 28 01:37:39 PM PDT 24
Finished May 28 01:37:44 PM PDT 24
Peak memory 200536 kb
Host smart-913f5065-37d6-40da-a0fe-edfa7f1bdf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819639233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1819639233
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.3915819806
Short name T403
Test name
Test status
Simulation time 937987241 ps
CPU time 4.71 seconds
Started May 28 01:37:38 PM PDT 24
Finished May 28 01:37:44 PM PDT 24
Peak memory 200676 kb
Host smart-1fbf1839-bac9-42e8-82ea-9ea6c4cc172f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915819806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3915819806
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1350562095
Short name T210
Test name
Test status
Simulation time 112243865 ps
CPU time 1.15 seconds
Started May 28 01:37:40 PM PDT 24
Finished May 28 01:37:45 PM PDT 24
Peak memory 200504 kb
Host smart-c752bbbc-2069-406b-9922-47f4c85150c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350562095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1350562095
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.498419779
Short name T467
Test name
Test status
Simulation time 116898781 ps
CPU time 1.14 seconds
Started May 28 01:37:38 PM PDT 24
Finished May 28 01:37:42 PM PDT 24
Peak memory 200676 kb
Host smart-f7737c73-92f9-49e1-9569-4f7b79e7a60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498419779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.498419779
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3374369101
Short name T529
Test name
Test status
Simulation time 505957837 ps
CPU time 2.34 seconds
Started May 28 01:37:40 PM PDT 24
Finished May 28 01:37:46 PM PDT 24
Peak memory 200724 kb
Host smart-7b37bb63-4bad-4c40-abd5-008b1a4a8d15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374369101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3374369101
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.3553793711
Short name T196
Test name
Test status
Simulation time 490706673 ps
CPU time 2.9 seconds
Started May 28 01:37:42 PM PDT 24
Finished May 28 01:37:49 PM PDT 24
Peak memory 200488 kb
Host smart-6e9bd2c3-5181-410c-b7f7-1e368acd9202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553793711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3553793711
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1666608538
Short name T481
Test name
Test status
Simulation time 82737946 ps
CPU time 0.84 seconds
Started May 28 01:37:37 PM PDT 24
Finished May 28 01:37:39 PM PDT 24
Peak memory 200496 kb
Host smart-27abe032-47e9-472b-ac93-eb1f1d3f7c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666608538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1666608538
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.135766742
Short name T368
Test name
Test status
Simulation time 74272600 ps
CPU time 0.8 seconds
Started May 28 01:37:38 PM PDT 24
Finished May 28 01:37:41 PM PDT 24
Peak memory 200248 kb
Host smart-3d99a406-e604-4087-b198-824ffa91786f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135766742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.135766742
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2987509950
Short name T253
Test name
Test status
Simulation time 244526340 ps
CPU time 1.03 seconds
Started May 28 01:37:39 PM PDT 24
Finished May 28 01:37:44 PM PDT 24
Peak memory 217600 kb
Host smart-341b91c9-1544-4bd0-95fa-8434ac9946e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987509950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2987509950
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.516269351
Short name T497
Test name
Test status
Simulation time 130582009 ps
CPU time 0.8 seconds
Started May 28 01:37:38 PM PDT 24
Finished May 28 01:37:42 PM PDT 24
Peak memory 200304 kb
Host smart-417e538d-3668-46d1-b724-88a63f66e79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516269351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.516269351
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2848148460
Short name T152
Test name
Test status
Simulation time 1135452236 ps
CPU time 5.43 seconds
Started May 28 01:37:42 PM PDT 24
Finished May 28 01:37:51 PM PDT 24
Peak memory 200676 kb
Host smart-a1826db6-ccff-46f1-a308-18c64c35989f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848148460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2848148460
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1808046523
Short name T345
Test name
Test status
Simulation time 178947591 ps
CPU time 1.16 seconds
Started May 28 01:37:42 PM PDT 24
Finished May 28 01:37:47 PM PDT 24
Peak memory 200420 kb
Host smart-417bbe95-aff5-4010-8233-e1356579d17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808046523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1808046523
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3974368969
Short name T410
Test name
Test status
Simulation time 198907485 ps
CPU time 1.35 seconds
Started May 28 01:37:41 PM PDT 24
Finished May 28 01:37:46 PM PDT 24
Peak memory 200720 kb
Host smart-2d4e2651-1355-4a3a-b928-3e46d58b9643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974368969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3974368969
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.1149681464
Short name T290
Test name
Test status
Simulation time 4556074323 ps
CPU time 19.88 seconds
Started May 28 01:37:46 PM PDT 24
Finished May 28 01:38:08 PM PDT 24
Peak memory 208948 kb
Host smart-c7d32ee6-2865-40b6-b4b8-8c551b492730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149681464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1149681464
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.474600439
Short name T54
Test name
Test status
Simulation time 415693252 ps
CPU time 2.54 seconds
Started May 28 01:37:42 PM PDT 24
Finished May 28 01:37:48 PM PDT 24
Peak memory 208684 kb
Host smart-4eea10f9-db96-4e9d-8a7f-18065410f2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474600439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.474600439
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.1982854567
Short name T78
Test name
Test status
Simulation time 71499000 ps
CPU time 0.8 seconds
Started May 28 01:37:40 PM PDT 24
Finished May 28 01:37:44 PM PDT 24
Peak memory 200452 kb
Host smart-71be0627-b5f1-4344-b070-5e007826c0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982854567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1982854567
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2378326972
Short name T257
Test name
Test status
Simulation time 73286399 ps
CPU time 0.77 seconds
Started May 28 01:37:37 PM PDT 24
Finished May 28 01:37:40 PM PDT 24
Peak memory 200252 kb
Host smart-1f8673d5-d783-4dcb-8b2a-977b08329cda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378326972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2378326972
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3558694840
Short name T29
Test name
Test status
Simulation time 1889084165 ps
CPU time 6.98 seconds
Started May 28 01:37:42 PM PDT 24
Finished May 28 01:37:53 PM PDT 24
Peak memory 222264 kb
Host smart-39c00148-eaf7-4f08-8eee-7996beed37b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558694840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3558694840
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1111580553
Short name T457
Test name
Test status
Simulation time 243000460 ps
CPU time 1.12 seconds
Started May 28 01:37:38 PM PDT 24
Finished May 28 01:37:42 PM PDT 24
Peak memory 217596 kb
Host smart-8af3c51f-2e67-40ab-82bc-467bd7226235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111580553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1111580553
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_reset.1016007258
Short name T277
Test name
Test status
Simulation time 1665869250 ps
CPU time 6.72 seconds
Started May 28 01:37:37 PM PDT 24
Finished May 28 01:37:45 PM PDT 24
Peak memory 200660 kb
Host smart-7d5f26b6-174d-4e96-a668-c2fe3dcb4987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016007258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1016007258
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1344034038
Short name T415
Test name
Test status
Simulation time 154702790 ps
CPU time 1.18 seconds
Started May 28 01:37:38 PM PDT 24
Finished May 28 01:37:41 PM PDT 24
Peak memory 200496 kb
Host smart-81bfba6a-4bf0-4feb-81ed-138052fd3aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344034038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1344034038
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.789233808
Short name T510
Test name
Test status
Simulation time 192150895 ps
CPU time 1.36 seconds
Started May 28 01:37:36 PM PDT 24
Finished May 28 01:37:39 PM PDT 24
Peak memory 200656 kb
Host smart-e4696f62-be25-4d69-8220-974bd36f08b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789233808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.789233808
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.4182776034
Short name T37
Test name
Test status
Simulation time 13612976722 ps
CPU time 56.29 seconds
Started May 28 01:37:42 PM PDT 24
Finished May 28 01:38:42 PM PDT 24
Peak memory 200872 kb
Host smart-074f315e-619c-40ef-9423-5434019063cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182776034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.4182776034
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.1868028601
Short name T162
Test name
Test status
Simulation time 152580900 ps
CPU time 1.93 seconds
Started May 28 01:37:46 PM PDT 24
Finished May 28 01:37:50 PM PDT 24
Peak memory 200404 kb
Host smart-03552d7e-4871-492b-9673-b505847e1196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868028601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1868028601
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.492629834
Short name T468
Test name
Test status
Simulation time 150026069 ps
CPU time 1.06 seconds
Started May 28 01:37:41 PM PDT 24
Finished May 28 01:37:46 PM PDT 24
Peak memory 200488 kb
Host smart-bc1ce420-d75c-4eaa-b97b-54ab7ce87c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492629834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.492629834
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3757766900
Short name T276
Test name
Test status
Simulation time 244153091 ps
CPU time 1.08 seconds
Started May 28 01:37:37 PM PDT 24
Finished May 28 01:37:39 PM PDT 24
Peak memory 217668 kb
Host smart-b95edc11-3fcb-43ab-b0e0-2ab74f0a5f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757766900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3757766900
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1455233471
Short name T460
Test name
Test status
Simulation time 113039568 ps
CPU time 0.8 seconds
Started May 28 01:37:38 PM PDT 24
Finished May 28 01:37:42 PM PDT 24
Peak memory 200300 kb
Host smart-14930810-df9f-4017-9abc-ecca213c50c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455233471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1455233471
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.1503839805
Short name T314
Test name
Test status
Simulation time 2022842311 ps
CPU time 8.06 seconds
Started May 28 01:37:41 PM PDT 24
Finished May 28 01:37:52 PM PDT 24
Peak memory 200680 kb
Host smart-2e1137eb-98d2-424d-9dc3-26c75fbda377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503839805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1503839805
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3357352764
Short name T395
Test name
Test status
Simulation time 97860347 ps
CPU time 1.07 seconds
Started May 28 01:37:40 PM PDT 24
Finished May 28 01:37:45 PM PDT 24
Peak memory 200496 kb
Host smart-6eb6f4ea-cbd1-4201-9f4d-fa910937bec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357352764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3357352764
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.278942530
Short name T320
Test name
Test status
Simulation time 201531887 ps
CPU time 1.39 seconds
Started May 28 01:37:41 PM PDT 24
Finished May 28 01:37:47 PM PDT 24
Peak memory 200680 kb
Host smart-c43672e2-0890-4aed-baaa-8780b2eea9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278942530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.278942530
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.890289718
Short name T526
Test name
Test status
Simulation time 2777307832 ps
CPU time 13.36 seconds
Started May 28 01:37:39 PM PDT 24
Finished May 28 01:37:56 PM PDT 24
Peak memory 209020 kb
Host smart-2f43f387-e3b1-4305-8326-c0ead7fafd36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890289718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.890289718
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3848581284
Short name T203
Test name
Test status
Simulation time 399327586 ps
CPU time 2.52 seconds
Started May 28 01:37:38 PM PDT 24
Finished May 28 01:37:42 PM PDT 24
Peak memory 200480 kb
Host smart-3d956df7-fb91-4fc1-b7f9-0707dc7fa629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848581284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3848581284
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2828079482
Short name T265
Test name
Test status
Simulation time 66026910 ps
CPU time 0.76 seconds
Started May 28 01:37:42 PM PDT 24
Finished May 28 01:37:47 PM PDT 24
Peak memory 200328 kb
Host smart-15197719-2953-4585-b891-4d437ef022bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828079482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2828079482
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1537214931
Short name T28
Test name
Test status
Simulation time 1223079570 ps
CPU time 6 seconds
Started May 28 01:37:41 PM PDT 24
Finished May 28 01:37:50 PM PDT 24
Peak memory 222132 kb
Host smart-3221ca7b-6af0-4c98-b80e-d60e06c1c4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537214931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1537214931
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1372209366
Short name T391
Test name
Test status
Simulation time 246453318 ps
CPU time 1.07 seconds
Started May 28 01:37:39 PM PDT 24
Finished May 28 01:37:44 PM PDT 24
Peak memory 217584 kb
Host smart-58d50f7a-0fa5-4e34-9b69-36855bf6b96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372209366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1372209366
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.4281554750
Short name T331
Test name
Test status
Simulation time 204240153 ps
CPU time 0.98 seconds
Started May 28 01:37:40 PM PDT 24
Finished May 28 01:37:44 PM PDT 24
Peak memory 200288 kb
Host smart-39862a08-be00-4cd4-8a5d-8aa20dec8a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281554750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.4281554750
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.341445234
Short name T456
Test name
Test status
Simulation time 1680293258 ps
CPU time 6.02 seconds
Started May 28 01:37:42 PM PDT 24
Finished May 28 01:37:52 PM PDT 24
Peak memory 200676 kb
Host smart-9dca3902-c371-4a78-874c-6e63fc85d983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341445234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.341445234
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1208366402
Short name T313
Test name
Test status
Simulation time 187249218 ps
CPU time 1.26 seconds
Started May 28 01:37:39 PM PDT 24
Finished May 28 01:37:43 PM PDT 24
Peak memory 200404 kb
Host smart-8a417aa0-75f3-42b9-9ae8-d17a506dccb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208366402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1208366402
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3415802826
Short name T472
Test name
Test status
Simulation time 266401133 ps
CPU time 1.61 seconds
Started May 28 01:37:42 PM PDT 24
Finished May 28 01:37:48 PM PDT 24
Peak memory 200672 kb
Host smart-7b59e9da-727c-493c-ad37-eb43592bdb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415802826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3415802826
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.1525219288
Short name T401
Test name
Test status
Simulation time 6588257978 ps
CPU time 23.3 seconds
Started May 28 01:37:42 PM PDT 24
Finished May 28 01:38:09 PM PDT 24
Peak memory 200864 kb
Host smart-a85be795-2d82-4397-ba5c-240bbca3358f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525219288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1525219288
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.85565282
Short name T301
Test name
Test status
Simulation time 129114187 ps
CPU time 1.66 seconds
Started May 28 01:37:40 PM PDT 24
Finished May 28 01:37:46 PM PDT 24
Peak memory 200492 kb
Host smart-41ad8f7e-5e59-4307-a19f-af1e4dd4a4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85565282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.85565282
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.411710131
Short name T163
Test name
Test status
Simulation time 88819556 ps
CPU time 0.89 seconds
Started May 28 01:37:41 PM PDT 24
Finished May 28 01:37:45 PM PDT 24
Peak memory 200488 kb
Host smart-dceb1f0e-c050-4111-a9d7-a129a2ecd40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411710131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.411710131
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.823279584
Short name T423
Test name
Test status
Simulation time 69407093 ps
CPU time 0.79 seconds
Started May 28 01:37:46 PM PDT 24
Finished May 28 01:37:49 PM PDT 24
Peak memory 200252 kb
Host smart-042c2a5c-f016-425d-a153-436055a4bf18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823279584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.823279584
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1598638575
Short name T34
Test name
Test status
Simulation time 1214908362 ps
CPU time 5.91 seconds
Started May 28 01:37:43 PM PDT 24
Finished May 28 01:37:52 PM PDT 24
Peak memory 217508 kb
Host smart-53a49cb2-70d0-4e41-bdf2-1a7f1d3f1150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598638575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1598638575
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2706306274
Short name T259
Test name
Test status
Simulation time 244164883 ps
CPU time 1.17 seconds
Started May 28 01:37:44 PM PDT 24
Finished May 28 01:37:48 PM PDT 24
Peak memory 217784 kb
Host smart-40a3437e-1111-4f4f-8c3a-c6c40cd74bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706306274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2706306274
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2209484699
Short name T375
Test name
Test status
Simulation time 215067777 ps
CPU time 0.91 seconds
Started May 28 01:37:40 PM PDT 24
Finished May 28 01:37:44 PM PDT 24
Peak memory 200216 kb
Host smart-49b98cad-4e85-414a-9c8c-9a9f7330a89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209484699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2209484699
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.3973510189
Short name T425
Test name
Test status
Simulation time 1631801516 ps
CPU time 6.73 seconds
Started May 28 01:37:42 PM PDT 24
Finished May 28 01:37:53 PM PDT 24
Peak memory 200676 kb
Host smart-cd859632-9db9-4e73-bd6d-71db837b5361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973510189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3973510189
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3162824704
Short name T172
Test name
Test status
Simulation time 117407884 ps
CPU time 1.2 seconds
Started May 28 01:37:42 PM PDT 24
Finished May 28 01:37:47 PM PDT 24
Peak memory 200680 kb
Host smart-c1fdf53e-d5ad-46ad-9e3f-cc2ebf673a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162824704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3162824704
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.193209105
Short name T151
Test name
Test status
Simulation time 266612009 ps
CPU time 1.75 seconds
Started May 28 01:37:41 PM PDT 24
Finished May 28 01:37:46 PM PDT 24
Peak memory 200408 kb
Host smart-0ff0bca5-7fd9-41fc-98af-9b8fae009e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193209105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.193209105
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3194452949
Short name T513
Test name
Test status
Simulation time 227289983 ps
CPU time 1.39 seconds
Started May 28 01:37:42 PM PDT 24
Finished May 28 01:37:48 PM PDT 24
Peak memory 200416 kb
Host smart-41109376-ed44-4241-94ee-80492b91aefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194452949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3194452949
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.571892619
Short name T419
Test name
Test status
Simulation time 76283409 ps
CPU time 0.81 seconds
Started May 28 01:37:56 PM PDT 24
Finished May 28 01:37:59 PM PDT 24
Peak memory 200340 kb
Host smart-593e2027-b43a-47dc-b309-d9da973213bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571892619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.571892619
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.238767586
Short name T351
Test name
Test status
Simulation time 1217210368 ps
CPU time 6.2 seconds
Started May 28 01:37:58 PM PDT 24
Finished May 28 01:38:07 PM PDT 24
Peak memory 221368 kb
Host smart-5dd3e352-c6f3-432d-b0fb-abd64a6ae740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238767586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.238767586
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3706519264
Short name T420
Test name
Test status
Simulation time 243660488 ps
CPU time 1.08 seconds
Started May 28 01:37:58 PM PDT 24
Finished May 28 01:38:03 PM PDT 24
Peak memory 217608 kb
Host smart-4e448ae9-496f-48d0-bb08-a05f615213f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706519264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3706519264
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1700944251
Short name T534
Test name
Test status
Simulation time 197288396 ps
CPU time 0.9 seconds
Started May 28 01:37:44 PM PDT 24
Finished May 28 01:37:48 PM PDT 24
Peak memory 200320 kb
Host smart-0eb55b2a-01c0-472f-84f2-b41509762011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700944251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1700944251
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.115837000
Short name T225
Test name
Test status
Simulation time 967912568 ps
CPU time 4.99 seconds
Started May 28 01:37:41 PM PDT 24
Finished May 28 01:37:49 PM PDT 24
Peak memory 200684 kb
Host smart-bd1dfc97-5ed7-4c58-b4ae-05bcea410a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115837000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.115837000
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3780337388
Short name T369
Test name
Test status
Simulation time 148694371 ps
CPU time 1.14 seconds
Started May 28 01:38:02 PM PDT 24
Finished May 28 01:38:07 PM PDT 24
Peak memory 200496 kb
Host smart-b13559bf-4fb3-4886-84e5-26316566bc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780337388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3780337388
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2514602708
Short name T489
Test name
Test status
Simulation time 250917147 ps
CPU time 1.56 seconds
Started May 28 01:37:44 PM PDT 24
Finished May 28 01:37:49 PM PDT 24
Peak memory 200696 kb
Host smart-403eca3d-3d94-4ff0-a677-10db33dcf4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514602708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2514602708
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.292976319
Short name T500
Test name
Test status
Simulation time 6092493046 ps
CPU time 27.91 seconds
Started May 28 01:37:58 PM PDT 24
Finished May 28 01:38:29 PM PDT 24
Peak memory 200804 kb
Host smart-76e5bff2-eb5c-4161-a11e-4a7b9a4ecc1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292976319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.292976319
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.3633220993
Short name T327
Test name
Test status
Simulation time 270244319 ps
CPU time 1.95 seconds
Started May 28 01:37:59 PM PDT 24
Finished May 28 01:38:04 PM PDT 24
Peak memory 200460 kb
Host smart-af20e82a-e47c-4135-b73a-6b2545c4e2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633220993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3633220993
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.1491359959
Short name T366
Test name
Test status
Simulation time 146531632 ps
CPU time 1.02 seconds
Started May 28 01:37:43 PM PDT 24
Finished May 28 01:37:47 PM PDT 24
Peak memory 200468 kb
Host smart-7c7c1c58-7b25-4847-9f8d-bb05d96d0cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491359959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1491359959
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3533849707
Short name T407
Test name
Test status
Simulation time 70154290 ps
CPU time 0.83 seconds
Started May 28 01:37:56 PM PDT 24
Finished May 28 01:38:00 PM PDT 24
Peak memory 200336 kb
Host smart-6a25dd74-9776-4678-aa82-3a3e1ec78488
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533849707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3533849707
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2822908333
Short name T30
Test name
Test status
Simulation time 1889712030 ps
CPU time 8.06 seconds
Started May 28 01:37:57 PM PDT 24
Finished May 28 01:38:08 PM PDT 24
Peak memory 217044 kb
Host smart-e195750a-bd4d-4d4b-900e-e4ae8bb15e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822908333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2822908333
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.450570521
Short name T234
Test name
Test status
Simulation time 245151013 ps
CPU time 1.04 seconds
Started May 28 01:37:56 PM PDT 24
Finished May 28 01:37:59 PM PDT 24
Peak memory 217560 kb
Host smart-ca0e1566-5218-4775-89cd-c3099b4a8aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450570521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.450570521
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1042603671
Short name T17
Test name
Test status
Simulation time 198288595 ps
CPU time 0.9 seconds
Started May 28 01:37:56 PM PDT 24
Finished May 28 01:38:00 PM PDT 24
Peak memory 200292 kb
Host smart-3afd6b2e-d145-44b1-9e7e-d0315c6aa921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042603671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1042603671
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1665741606
Short name T365
Test name
Test status
Simulation time 752611004 ps
CPU time 4.16 seconds
Started May 28 01:38:00 PM PDT 24
Finished May 28 01:38:09 PM PDT 24
Peak memory 200660 kb
Host smart-572f2ec1-4b50-4381-9c24-8bff38dc4166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665741606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1665741606
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1813285776
Short name T434
Test name
Test status
Simulation time 94826737 ps
CPU time 1.03 seconds
Started May 28 01:37:58 PM PDT 24
Finished May 28 01:38:01 PM PDT 24
Peak memory 200496 kb
Host smart-06db9a8c-262e-406d-b30a-e3e0e78cce12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813285776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1813285776
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.535664877
Short name T215
Test name
Test status
Simulation time 130153086 ps
CPU time 1.25 seconds
Started May 28 01:38:03 PM PDT 24
Finished May 28 01:38:07 PM PDT 24
Peak memory 200688 kb
Host smart-ed18742f-ac29-4919-b466-653e59a0be11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535664877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.535664877
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.4123645632
Short name T428
Test name
Test status
Simulation time 7056798271 ps
CPU time 24.93 seconds
Started May 28 01:37:56 PM PDT 24
Finished May 28 01:38:23 PM PDT 24
Peak memory 200832 kb
Host smart-6cee0486-263a-41fc-8880-5adbc60d7098
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123645632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.4123645632
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.432444429
Short name T437
Test name
Test status
Simulation time 332413077 ps
CPU time 2.29 seconds
Started May 28 01:37:56 PM PDT 24
Finished May 28 01:38:01 PM PDT 24
Peak memory 208684 kb
Host smart-5c7ac5fd-9c86-4fc2-854b-ff09f03d8d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432444429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.432444429
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.676431430
Short name T49
Test name
Test status
Simulation time 213616255 ps
CPU time 1.33 seconds
Started May 28 01:37:58 PM PDT 24
Finished May 28 01:38:02 PM PDT 24
Peak memory 200488 kb
Host smart-adfcbfdd-54ab-4838-88d4-674dc7ff329f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676431430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.676431430
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2311150365
Short name T347
Test name
Test status
Simulation time 63272263 ps
CPU time 0.72 seconds
Started May 28 01:37:58 PM PDT 24
Finished May 28 01:38:01 PM PDT 24
Peak memory 200328 kb
Host smart-34cbddb8-9a24-4374-829a-03a774f96b97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311150365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2311150365
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.569254184
Short name T485
Test name
Test status
Simulation time 1889421436 ps
CPU time 7.73 seconds
Started May 28 01:37:56 PM PDT 24
Finished May 28 01:38:06 PM PDT 24
Peak memory 218164 kb
Host smart-1fc94520-9410-4245-9be2-cf06973a1c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569254184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.569254184
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3816801415
Short name T300
Test name
Test status
Simulation time 244532115 ps
CPU time 1.1 seconds
Started May 28 01:37:58 PM PDT 24
Finished May 28 01:38:02 PM PDT 24
Peak memory 217604 kb
Host smart-4cf4a614-4d7e-4a40-8d15-7282ad214d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816801415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3816801415
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.481262417
Short name T5
Test name
Test status
Simulation time 199941967 ps
CPU time 0.94 seconds
Started May 28 01:37:58 PM PDT 24
Finished May 28 01:38:02 PM PDT 24
Peak memory 200300 kb
Host smart-faabbf55-24cc-4bd2-aff8-122130b93482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481262417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.481262417
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.1382023543
Short name T336
Test name
Test status
Simulation time 974112667 ps
CPU time 4.78 seconds
Started May 28 01:37:59 PM PDT 24
Finished May 28 01:38:08 PM PDT 24
Peak memory 200600 kb
Host smart-2fbaf2c7-80c4-4969-9be7-c6a42076de20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382023543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1382023543
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2891645942
Short name T328
Test name
Test status
Simulation time 143691272 ps
CPU time 1.13 seconds
Started May 28 01:37:56 PM PDT 24
Finished May 28 01:37:59 PM PDT 24
Peak memory 200476 kb
Host smart-ec1673ad-a4f0-4f8a-b08a-2cb25cc2d8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891645942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2891645942
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2619820699
Short name T479
Test name
Test status
Simulation time 261239484 ps
CPU time 1.65 seconds
Started May 28 01:37:58 PM PDT 24
Finished May 28 01:38:03 PM PDT 24
Peak memory 200720 kb
Host smart-d425e3a3-f099-47aa-b1f9-d7fc43902f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619820699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2619820699
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2783506464
Short name T192
Test name
Test status
Simulation time 1818923595 ps
CPU time 7.76 seconds
Started May 28 01:38:00 PM PDT 24
Finished May 28 01:38:12 PM PDT 24
Peak memory 200704 kb
Host smart-d06fd9ec-b357-4c35-93a8-d86eed6a2518
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783506464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2783506464
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.2574736855
Short name T430
Test name
Test status
Simulation time 310365715 ps
CPU time 2.1 seconds
Started May 28 01:37:58 PM PDT 24
Finished May 28 01:38:03 PM PDT 24
Peak memory 208720 kb
Host smart-4b3859f5-ca2f-43bd-8d6c-7296e9dd1f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574736855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.2574736855
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2517575838
Short name T206
Test name
Test status
Simulation time 167397269 ps
CPU time 1.2 seconds
Started May 28 01:37:58 PM PDT 24
Finished May 28 01:38:02 PM PDT 24
Peak memory 200444 kb
Host smart-59930d3d-d2e9-400c-8fae-3759bd9e0fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517575838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2517575838
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.345808846
Short name T168
Test name
Test status
Simulation time 72065507 ps
CPU time 0.8 seconds
Started May 28 01:37:08 PM PDT 24
Finished May 28 01:37:11 PM PDT 24
Peak memory 200260 kb
Host smart-92b12031-bd00-4830-92f3-3f3001dc9775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345808846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.345808846
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.19847064
Short name T372
Test name
Test status
Simulation time 1884847375 ps
CPU time 7.68 seconds
Started May 28 01:37:07 PM PDT 24
Finished May 28 01:37:16 PM PDT 24
Peak memory 217532 kb
Host smart-bc1d401e-a479-4c37-b92f-43c28056a5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19847064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.19847064
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2901814817
Short name T445
Test name
Test status
Simulation time 244197066 ps
CPU time 1.06 seconds
Started May 28 01:37:06 PM PDT 24
Finished May 28 01:37:09 PM PDT 24
Peak memory 217592 kb
Host smart-2167fa0f-a139-466b-86d1-53560653efe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901814817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2901814817
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1764185582
Short name T297
Test name
Test status
Simulation time 216704550 ps
CPU time 0.91 seconds
Started May 28 01:37:12 PM PDT 24
Finished May 28 01:37:14 PM PDT 24
Peak memory 200232 kb
Host smart-a7856962-7e1a-42a2-baf3-e4295d8f12b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764185582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1764185582
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.379742680
Short name T461
Test name
Test status
Simulation time 1383501279 ps
CPU time 5.46 seconds
Started May 28 01:37:11 PM PDT 24
Finished May 28 01:37:18 PM PDT 24
Peak memory 200668 kb
Host smart-40acdb41-2176-44fa-a860-118d4f9f41ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379742680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.379742680
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2615623243
Short name T72
Test name
Test status
Simulation time 8276647400 ps
CPU time 16.05 seconds
Started May 28 01:37:12 PM PDT 24
Finished May 28 01:37:29 PM PDT 24
Peak memory 217640 kb
Host smart-10dab52e-a544-450c-99fa-0097a9e11e52
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615623243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2615623243
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1189980627
Short name T216
Test name
Test status
Simulation time 103115825 ps
CPU time 1.03 seconds
Started May 28 01:37:11 PM PDT 24
Finished May 28 01:37:14 PM PDT 24
Peak memory 200464 kb
Host smart-914ed96d-dc99-45dc-945b-85ffa3d17832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189980627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1189980627
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.4253327580
Short name T405
Test name
Test status
Simulation time 114359046 ps
CPU time 1.18 seconds
Started May 28 01:37:07 PM PDT 24
Finished May 28 01:37:10 PM PDT 24
Peak memory 200672 kb
Host smart-71c22383-7456-4be8-a3aa-900a1f38d87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253327580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.4253327580
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1882025278
Short name T507
Test name
Test status
Simulation time 7817847919 ps
CPU time 28.26 seconds
Started May 28 01:37:05 PM PDT 24
Finished May 28 01:37:35 PM PDT 24
Peak memory 200736 kb
Host smart-f991eda6-044a-4631-bb51-482669e18277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882025278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1882025278
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1414744464
Short name T188
Test name
Test status
Simulation time 134248457 ps
CPU time 1.72 seconds
Started May 28 01:37:12 PM PDT 24
Finished May 28 01:37:15 PM PDT 24
Peak memory 200412 kb
Host smart-59b0c2f4-095c-4716-850a-779f0b0b2456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414744464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1414744464
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2500047253
Short name T462
Test name
Test status
Simulation time 135819880 ps
CPU time 1.1 seconds
Started May 28 01:37:10 PM PDT 24
Finished May 28 01:37:13 PM PDT 24
Peak memory 200472 kb
Host smart-a56c7c1a-4111-4f73-af1a-6b24abe9874b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500047253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2500047253
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2962006461
Short name T429
Test name
Test status
Simulation time 66664610 ps
CPU time 0.81 seconds
Started May 28 01:37:55 PM PDT 24
Finished May 28 01:37:58 PM PDT 24
Peak memory 200252 kb
Host smart-bb9b72e8-6499-4806-a9a2-de2efe8a69d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962006461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2962006461
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1803739885
Short name T32
Test name
Test status
Simulation time 2151301424 ps
CPU time 7.92 seconds
Started May 28 01:37:57 PM PDT 24
Finished May 28 01:38:07 PM PDT 24
Peak memory 218260 kb
Host smart-35f4f1e2-0e52-470f-90c4-1e7553a3ba5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803739885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1803739885
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2688896513
Short name T175
Test name
Test status
Simulation time 244208874 ps
CPU time 1.1 seconds
Started May 28 01:37:59 PM PDT 24
Finished May 28 01:38:04 PM PDT 24
Peak memory 217736 kb
Host smart-43a3c68c-ebab-4da4-a909-20fe683a5c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688896513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2688896513
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2219001719
Short name T520
Test name
Test status
Simulation time 112194748 ps
CPU time 0.84 seconds
Started May 28 01:37:57 PM PDT 24
Finished May 28 01:38:00 PM PDT 24
Peak memory 200284 kb
Host smart-76bd9f93-272d-4224-aaf7-593738f1a3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219001719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2219001719
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.191588759
Short name T349
Test name
Test status
Simulation time 961713363 ps
CPU time 4.49 seconds
Started May 28 01:37:57 PM PDT 24
Finished May 28 01:38:04 PM PDT 24
Peak memory 200716 kb
Host smart-029ba3db-ea2b-40e8-99c2-66e10c20465a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191588759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.191588759
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3169967025
Short name T376
Test name
Test status
Simulation time 101777098 ps
CPU time 1.06 seconds
Started May 28 01:37:59 PM PDT 24
Finished May 28 01:38:04 PM PDT 24
Peak memory 200476 kb
Host smart-05d9c0eb-64b3-4a40-a025-9a6c785e0038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169967025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3169967025
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1701973966
Short name T244
Test name
Test status
Simulation time 223442234 ps
CPU time 1.56 seconds
Started May 28 01:37:56 PM PDT 24
Finished May 28 01:38:00 PM PDT 24
Peak memory 200720 kb
Host smart-a235aaac-bcc3-4077-8e43-f2eb402d7c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701973966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1701973966
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.1221764044
Short name T86
Test name
Test status
Simulation time 3166005746 ps
CPU time 14.76 seconds
Started May 28 01:37:56 PM PDT 24
Finished May 28 01:38:13 PM PDT 24
Peak memory 200828 kb
Host smart-e5116f5d-44e9-4d75-94d3-1a7d989dc768
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221764044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1221764044
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2853513302
Short name T450
Test name
Test status
Simulation time 476320865 ps
CPU time 2.64 seconds
Started May 28 01:37:56 PM PDT 24
Finished May 28 01:38:02 PM PDT 24
Peak memory 200480 kb
Host smart-39d4d8e7-0d32-441c-8fa5-35b409252e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853513302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2853513302
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.4182768606
Short name T211
Test name
Test status
Simulation time 107692682 ps
CPU time 1 seconds
Started May 28 01:37:55 PM PDT 24
Finished May 28 01:37:58 PM PDT 24
Peak memory 200488 kb
Host smart-5646a175-6c53-41cd-bb23-b4ee74aa2dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182768606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.4182768606
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3585089658
Short name T362
Test name
Test status
Simulation time 63869229 ps
CPU time 0.76 seconds
Started May 28 01:38:01 PM PDT 24
Finished May 28 01:38:06 PM PDT 24
Peak memory 200300 kb
Host smart-21e691c1-dbc1-425b-9fe2-46d6e8d7bb16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585089658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3585089658
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.144546698
Short name T480
Test name
Test status
Simulation time 1235325119 ps
CPU time 6.05 seconds
Started May 28 01:38:02 PM PDT 24
Finished May 28 01:38:12 PM PDT 24
Peak memory 222112 kb
Host smart-d34a2f91-8cc9-41cc-b995-9afcb499f943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144546698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.144546698
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2322498475
Short name T455
Test name
Test status
Simulation time 244788633 ps
CPU time 1.12 seconds
Started May 28 01:38:01 PM PDT 24
Finished May 28 01:38:06 PM PDT 24
Peak memory 217624 kb
Host smart-218504cb-d693-4acf-b6c5-9395526f476c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322498475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2322498475
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2746287189
Short name T315
Test name
Test status
Simulation time 170154503 ps
CPU time 0.87 seconds
Started May 28 01:38:02 PM PDT 24
Finished May 28 01:38:07 PM PDT 24
Peak memory 200308 kb
Host smart-19bd4533-32f7-490d-9d88-21e723e4974c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746287189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2746287189
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3194210468
Short name T51
Test name
Test status
Simulation time 1366467535 ps
CPU time 6.02 seconds
Started May 28 01:37:56 PM PDT 24
Finished May 28 01:38:05 PM PDT 24
Peak memory 200676 kb
Host smart-9b2edfb7-ca4c-4833-bc03-0bcff83bad44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194210468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3194210468
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2241893438
Short name T443
Test name
Test status
Simulation time 179287453 ps
CPU time 1.29 seconds
Started May 28 01:38:02 PM PDT 24
Finished May 28 01:38:08 PM PDT 24
Peak memory 200508 kb
Host smart-d189908d-a92a-41c7-af0f-d6bfecc258f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241893438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2241893438
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1905769435
Short name T466
Test name
Test status
Simulation time 129024605 ps
CPU time 1.29 seconds
Started May 28 01:37:59 PM PDT 24
Finished May 28 01:38:04 PM PDT 24
Peak memory 200708 kb
Host smart-d0b2751c-1c6c-4f7d-88cf-404760af75ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905769435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1905769435
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.759606276
Short name T533
Test name
Test status
Simulation time 9222270545 ps
CPU time 37.88 seconds
Started May 28 01:38:02 PM PDT 24
Finished May 28 01:38:44 PM PDT 24
Peak memory 209036 kb
Host smart-2bd00858-c1e7-4142-932e-95d0419cec18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759606276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.759606276
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1085615620
Short name T145
Test name
Test status
Simulation time 133409603 ps
CPU time 1.66 seconds
Started May 28 01:38:02 PM PDT 24
Finished May 28 01:38:08 PM PDT 24
Peak memory 200484 kb
Host smart-94b1036e-45b9-48ac-984e-385e0dbb0db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085615620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1085615620
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1769307576
Short name T416
Test name
Test status
Simulation time 171731182 ps
CPU time 1.34 seconds
Started May 28 01:38:01 PM PDT 24
Finished May 28 01:38:07 PM PDT 24
Peak memory 200684 kb
Host smart-981ecf10-1438-41f9-bf83-97d0f13e471c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769307576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1769307576
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3280785633
Short name T537
Test name
Test status
Simulation time 66531983 ps
CPU time 0.74 seconds
Started May 28 01:38:01 PM PDT 24
Finished May 28 01:38:06 PM PDT 24
Peak memory 200332 kb
Host smart-fc01077a-168c-4317-8852-46711ba9c927
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280785633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3280785633
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.4214549540
Short name T516
Test name
Test status
Simulation time 2176181264 ps
CPU time 8.95 seconds
Started May 28 01:38:01 PM PDT 24
Finished May 28 01:38:14 PM PDT 24
Peak memory 222320 kb
Host smart-6e5fa6ba-5830-405a-96c6-f957da1bddc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214549540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.4214549540
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3670093415
Short name T469
Test name
Test status
Simulation time 245025006 ps
CPU time 1.03 seconds
Started May 28 01:38:01 PM PDT 24
Finished May 28 01:38:06 PM PDT 24
Peak memory 217600 kb
Host smart-eb4abdae-56b4-4fdc-9eff-7c2164859f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670093415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3670093415
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.1046358537
Short name T436
Test name
Test status
Simulation time 84105559 ps
CPU time 0.78 seconds
Started May 28 01:38:00 PM PDT 24
Finished May 28 01:38:05 PM PDT 24
Peak memory 200276 kb
Host smart-f13c2b17-0d41-4ae9-a18b-3912332b1511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046358537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1046358537
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2213684625
Short name T135
Test name
Test status
Simulation time 1650207980 ps
CPU time 6.45 seconds
Started May 28 01:38:01 PM PDT 24
Finished May 28 01:38:11 PM PDT 24
Peak memory 200648 kb
Host smart-51634cc6-92e7-4157-8bb1-d02f69eabd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213684625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2213684625
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.4132833702
Short name T77
Test name
Test status
Simulation time 163706887 ps
CPU time 1.18 seconds
Started May 28 01:38:02 PM PDT 24
Finished May 28 01:38:07 PM PDT 24
Peak memory 200496 kb
Host smart-c3207c92-6875-4275-9541-ac0e9170f5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132833702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.4132833702
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3677871051
Short name T381
Test name
Test status
Simulation time 194078883 ps
CPU time 1.33 seconds
Started May 28 01:38:02 PM PDT 24
Finished May 28 01:38:07 PM PDT 24
Peak memory 200676 kb
Host smart-b4f7a443-6ede-4e2f-9886-796e83482e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677871051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3677871051
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2268644707
Short name T438
Test name
Test status
Simulation time 4607281943 ps
CPU time 20.96 seconds
Started May 28 01:38:01 PM PDT 24
Finished May 28 01:38:26 PM PDT 24
Peak memory 209028 kb
Host smart-fda092d9-db69-48a2-a268-60d2e233d209
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268644707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2268644707
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.1088110981
Short name T89
Test name
Test status
Simulation time 135248667 ps
CPU time 1.7 seconds
Started May 28 01:38:02 PM PDT 24
Finished May 28 01:38:07 PM PDT 24
Peak memory 208680 kb
Host smart-f945498b-c384-40b0-aece-bf62f79f1ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088110981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1088110981
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3473880128
Short name T228
Test name
Test status
Simulation time 120980512 ps
CPU time 1.06 seconds
Started May 28 01:38:00 PM PDT 24
Finished May 28 01:38:06 PM PDT 24
Peak memory 200492 kb
Host smart-8ca62502-1603-46f4-abdb-1781190ed4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473880128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3473880128
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.876545379
Short name T432
Test name
Test status
Simulation time 63863733 ps
CPU time 0.74 seconds
Started May 28 01:38:01 PM PDT 24
Finished May 28 01:38:06 PM PDT 24
Peak memory 200312 kb
Host smart-277d5b80-21ec-4426-a932-686f1fcfb890
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876545379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.876545379
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.363505884
Short name T55
Test name
Test status
Simulation time 1886221320 ps
CPU time 7.49 seconds
Started May 28 01:38:02 PM PDT 24
Finished May 28 01:38:13 PM PDT 24
Peak memory 218108 kb
Host smart-83291309-eda4-4d7c-9565-6214421f93c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363505884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.363505884
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1317287001
Short name T214
Test name
Test status
Simulation time 243740870 ps
CPU time 1.03 seconds
Started May 28 01:38:01 PM PDT 24
Finished May 28 01:38:06 PM PDT 24
Peak memory 217584 kb
Host smart-025f16ed-0253-4060-9613-8a5b09b96678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317287001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.1317287001
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2408145041
Short name T540
Test name
Test status
Simulation time 86572887 ps
CPU time 0.74 seconds
Started May 28 01:37:59 PM PDT 24
Finished May 28 01:38:03 PM PDT 24
Peak memory 200268 kb
Host smart-0ef0dc0c-4e25-4f1e-b6e8-d72b50112dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408145041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2408145041
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2806793101
Short name T531
Test name
Test status
Simulation time 1073672316 ps
CPU time 5.43 seconds
Started May 28 01:38:01 PM PDT 24
Finished May 28 01:38:11 PM PDT 24
Peak memory 200684 kb
Host smart-e0cc119a-d67e-4b4f-a5ea-9bac13c13a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806793101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2806793101
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1488308789
Short name T222
Test name
Test status
Simulation time 145444306 ps
CPU time 1.12 seconds
Started May 28 01:37:58 PM PDT 24
Finished May 28 01:38:02 PM PDT 24
Peak memory 200472 kb
Host smart-ffb75232-a6c3-4d46-a913-cdf8ee5649d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488308789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1488308789
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.3760546380
Short name T213
Test name
Test status
Simulation time 246275544 ps
CPU time 1.52 seconds
Started May 28 01:38:00 PM PDT 24
Finished May 28 01:38:06 PM PDT 24
Peak memory 200720 kb
Host smart-bae66a9d-9404-4b28-8e02-26c563d49bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760546380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3760546380
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3883474731
Short name T463
Test name
Test status
Simulation time 2993430195 ps
CPU time 11.26 seconds
Started May 28 01:38:01 PM PDT 24
Finished May 28 01:38:17 PM PDT 24
Peak memory 217160 kb
Host smart-f2c0fd88-5d7e-49dc-84db-0e393f14e2e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883474731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3883474731
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2585116734
Short name T335
Test name
Test status
Simulation time 312081396 ps
CPU time 2.02 seconds
Started May 28 01:38:01 PM PDT 24
Finished May 28 01:38:07 PM PDT 24
Peak memory 200468 kb
Host smart-fb4abc3c-d0a9-43a5-a625-6c0fbfcb9c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585116734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2585116734
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3169873516
Short name T182
Test name
Test status
Simulation time 212573074 ps
CPU time 1.35 seconds
Started May 28 01:37:58 PM PDT 24
Finished May 28 01:38:02 PM PDT 24
Peak memory 200488 kb
Host smart-eee935de-87da-4451-80fa-e094eb5b0d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169873516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3169873516
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1809960364
Short name T465
Test name
Test status
Simulation time 84319462 ps
CPU time 0.84 seconds
Started May 28 01:38:14 PM PDT 24
Finished May 28 01:38:21 PM PDT 24
Peak memory 200324 kb
Host smart-69a49419-1db3-4d3d-a380-371cc37e9e6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809960364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1809960364
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3262229818
Short name T248
Test name
Test status
Simulation time 2347588522 ps
CPU time 8.42 seconds
Started May 28 01:38:11 PM PDT 24
Finished May 28 01:38:22 PM PDT 24
Peak memory 218292 kb
Host smart-66bff945-63ff-489f-ae60-d6872ecdf783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262229818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3262229818
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3082246177
Short name T344
Test name
Test status
Simulation time 244064747 ps
CPU time 1.12 seconds
Started May 28 01:38:13 PM PDT 24
Finished May 28 01:38:19 PM PDT 24
Peak memory 217576 kb
Host smart-45d57481-1967-403c-a56e-a8b1c74b3708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082246177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3082246177
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3847377695
Short name T246
Test name
Test status
Simulation time 189041742 ps
CPU time 0.92 seconds
Started May 28 01:38:13 PM PDT 24
Finished May 28 01:38:19 PM PDT 24
Peak memory 200316 kb
Host smart-62e8f7c5-61e2-4488-b010-67c2a40fd09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847377695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3847377695
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3827491076
Short name T282
Test name
Test status
Simulation time 1599383347 ps
CPU time 5.99 seconds
Started May 28 01:38:11 PM PDT 24
Finished May 28 01:38:19 PM PDT 24
Peak memory 200680 kb
Host smart-2e093440-b370-4504-be0b-4553b8164255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827491076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3827491076
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.2146509903
Short name T150
Test name
Test status
Simulation time 102784518 ps
CPU time 1.01 seconds
Started May 28 01:38:12 PM PDT 24
Finished May 28 01:38:17 PM PDT 24
Peak memory 200496 kb
Host smart-d9d45f51-3468-48e1-90ed-eca1bceab3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146509903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.2146509903
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.371515025
Short name T371
Test name
Test status
Simulation time 249150995 ps
CPU time 1.68 seconds
Started May 28 01:38:13 PM PDT 24
Finished May 28 01:38:20 PM PDT 24
Peak memory 200672 kb
Host smart-03fb2413-a8c1-4988-b566-1964b0317343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371515025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.371515025
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.1525288142
Short name T499
Test name
Test status
Simulation time 7993223244 ps
CPU time 31.43 seconds
Started May 28 01:38:16 PM PDT 24
Finished May 28 01:38:54 PM PDT 24
Peak memory 200812 kb
Host smart-0f64e074-e9c4-4e1b-bbd0-40e0b40c876b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525288142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1525288142
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2472915456
Short name T284
Test name
Test status
Simulation time 130774814 ps
CPU time 1.67 seconds
Started May 28 01:38:11 PM PDT 24
Finished May 28 01:38:15 PM PDT 24
Peak memory 200484 kb
Host smart-3dd36534-5254-4c8b-8793-3f404ce170b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472915456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2472915456
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1906951286
Short name T452
Test name
Test status
Simulation time 122327543 ps
CPU time 1.13 seconds
Started May 28 01:38:12 PM PDT 24
Finished May 28 01:38:18 PM PDT 24
Peak memory 200472 kb
Host smart-c31ca4b1-fc9b-4adb-8a4f-8f78709f9c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906951286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1906951286
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2576517447
Short name T180
Test name
Test status
Simulation time 83329812 ps
CPU time 0.82 seconds
Started May 28 01:38:10 PM PDT 24
Finished May 28 01:38:12 PM PDT 24
Peak memory 200328 kb
Host smart-52794412-2eed-4086-9dd6-a43a00322f5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576517447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2576517447
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3819534710
Short name T302
Test name
Test status
Simulation time 1229954982 ps
CPU time 5.42 seconds
Started May 28 01:38:13 PM PDT 24
Finished May 28 01:38:25 PM PDT 24
Peak memory 218136 kb
Host smart-adb17158-5783-41cc-805b-f6300e8f8a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819534710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3819534710
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2308896496
Short name T208
Test name
Test status
Simulation time 244156243 ps
CPU time 1.11 seconds
Started May 28 01:38:08 PM PDT 24
Finished May 28 01:38:11 PM PDT 24
Peak memory 217600 kb
Host smart-80c21681-639a-4cba-ae01-49df084ecf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308896496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2308896496
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.183585858
Short name T9
Test name
Test status
Simulation time 218874634 ps
CPU time 0.97 seconds
Started May 28 01:38:14 PM PDT 24
Finished May 28 01:38:21 PM PDT 24
Peak memory 200256 kb
Host smart-9f5e499b-d1e6-427d-97d7-eb409437cf1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183585858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.183585858
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2952803797
Short name T321
Test name
Test status
Simulation time 745570318 ps
CPU time 3.95 seconds
Started May 28 01:38:11 PM PDT 24
Finished May 28 01:38:19 PM PDT 24
Peak memory 200696 kb
Host smart-8f911322-43ff-4025-8289-24d15394af24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952803797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2952803797
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3364023886
Short name T332
Test name
Test status
Simulation time 138739465 ps
CPU time 1.09 seconds
Started May 28 01:38:11 PM PDT 24
Finished May 28 01:38:16 PM PDT 24
Peak memory 200504 kb
Host smart-f8300350-25fc-4918-8e24-da7ef2cfaece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364023886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3364023886
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.1810502704
Short name T409
Test name
Test status
Simulation time 114402477 ps
CPU time 1.32 seconds
Started May 28 01:38:13 PM PDT 24
Finished May 28 01:38:20 PM PDT 24
Peak memory 200584 kb
Host smart-0e19dfdd-f51e-4e57-9616-fcd4d52da1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810502704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1810502704
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2415663660
Short name T340
Test name
Test status
Simulation time 4077610949 ps
CPU time 14.65 seconds
Started May 28 01:38:15 PM PDT 24
Finished May 28 01:38:37 PM PDT 24
Peak memory 210924 kb
Host smart-6b767a3c-19ad-4a21-ab18-843e2d2e6e4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415663660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2415663660
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3470841159
Short name T271
Test name
Test status
Simulation time 468960276 ps
CPU time 2.53 seconds
Started May 28 01:38:13 PM PDT 24
Finished May 28 01:38:20 PM PDT 24
Peak memory 200392 kb
Host smart-0b38c3e9-74e0-4e97-a681-7bb3e34f1b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470841159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3470841159
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.982022204
Short name T464
Test name
Test status
Simulation time 260235944 ps
CPU time 1.35 seconds
Started May 28 01:38:10 PM PDT 24
Finished May 28 01:38:13 PM PDT 24
Peak memory 200484 kb
Host smart-bce439b2-fcd5-4ce1-8c89-c4488c0794a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982022204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.982022204
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2887128818
Short name T329
Test name
Test status
Simulation time 78956476 ps
CPU time 0.89 seconds
Started May 28 01:38:12 PM PDT 24
Finished May 28 01:38:18 PM PDT 24
Peak memory 200332 kb
Host smart-49b19adb-dd92-4053-9e35-6e924ab2fce4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887128818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2887128818
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1597436338
Short name T363
Test name
Test status
Simulation time 1220660232 ps
CPU time 5.73 seconds
Started May 28 01:38:10 PM PDT 24
Finished May 28 01:38:16 PM PDT 24
Peak memory 218112 kb
Host smart-a6d469a1-9d1e-462e-97d3-5276c1a4cdcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597436338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1597436338
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2672328845
Short name T219
Test name
Test status
Simulation time 243406769 ps
CPU time 1.13 seconds
Started May 28 01:38:13 PM PDT 24
Finished May 28 01:38:20 PM PDT 24
Peak memory 217692 kb
Host smart-b2af925f-2167-48e7-9b8e-cd9adcb508f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672328845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2672328845
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1003953761
Short name T498
Test name
Test status
Simulation time 183250316 ps
CPU time 0.88 seconds
Started May 28 01:38:13 PM PDT 24
Finished May 28 01:38:20 PM PDT 24
Peak memory 200276 kb
Host smart-e95d0ad5-0816-4593-aa74-11592cb30a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003953761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1003953761
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1337578793
Short name T426
Test name
Test status
Simulation time 1718540561 ps
CPU time 6.77 seconds
Started May 28 01:38:11 PM PDT 24
Finished May 28 01:38:22 PM PDT 24
Peak memory 200640 kb
Host smart-fb0d5052-0725-45de-a288-e8ea1a08891a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337578793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1337578793
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1199736613
Short name T444
Test name
Test status
Simulation time 154823422 ps
CPU time 1.19 seconds
Started May 28 01:38:17 PM PDT 24
Finished May 28 01:38:25 PM PDT 24
Peak memory 200476 kb
Host smart-12e6323a-eb5d-4faa-a24c-5a57f6d46fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199736613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1199736613
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.396668138
Short name T90
Test name
Test status
Simulation time 194617532 ps
CPU time 1.37 seconds
Started May 28 01:38:12 PM PDT 24
Finished May 28 01:38:18 PM PDT 24
Peak memory 200656 kb
Host smart-a40d023f-ebc2-4409-8d96-6a71fbff704c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396668138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.396668138
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3313210607
Short name T107
Test name
Test status
Simulation time 9360138165 ps
CPU time 34.04 seconds
Started May 28 01:38:13 PM PDT 24
Finished May 28 01:38:53 PM PDT 24
Peak memory 209004 kb
Host smart-591e0981-be6a-4cd4-b6f0-ac7dfcebede2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313210607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3313210607
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2189610503
Short name T262
Test name
Test status
Simulation time 343526299 ps
CPU time 2.35 seconds
Started May 28 01:38:14 PM PDT 24
Finished May 28 01:38:23 PM PDT 24
Peak memory 200524 kb
Host smart-24dd3499-e7fe-413f-8583-56b5e5dce3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189610503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2189610503
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.1449993023
Short name T413
Test name
Test status
Simulation time 190823043 ps
CPU time 1.27 seconds
Started May 28 01:38:10 PM PDT 24
Finished May 28 01:38:12 PM PDT 24
Peak memory 200464 kb
Host smart-a99542e3-3143-47ef-b90b-8977f8881471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449993023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1449993023
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.3544767134
Short name T178
Test name
Test status
Simulation time 68192433 ps
CPU time 0.77 seconds
Started May 28 01:38:13 PM PDT 24
Finished May 28 01:38:20 PM PDT 24
Peak memory 200336 kb
Host smart-eedab4f8-9655-4d1e-993d-8f196684e84c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544767134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.3544767134
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2977343946
Short name T42
Test name
Test status
Simulation time 1882221326 ps
CPU time 7.2 seconds
Started May 28 01:38:11 PM PDT 24
Finished May 28 01:38:22 PM PDT 24
Peak memory 222168 kb
Host smart-d58310ab-3b92-4a8d-a932-9f2546a1a2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977343946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2977343946
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1267009437
Short name T474
Test name
Test status
Simulation time 245159153 ps
CPU time 1.07 seconds
Started May 28 01:38:10 PM PDT 24
Finished May 28 01:38:13 PM PDT 24
Peak memory 217584 kb
Host smart-0969b162-f122-4f30-9c18-1821ba6bc7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267009437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1267009437
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.536984543
Short name T379
Test name
Test status
Simulation time 166366403 ps
CPU time 0.9 seconds
Started May 28 01:38:15 PM PDT 24
Finished May 28 01:38:22 PM PDT 24
Peak memory 200304 kb
Host smart-eb6ff936-187e-4429-8a6d-669c735b74ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536984543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.536984543
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1498749886
Short name T299
Test name
Test status
Simulation time 954627684 ps
CPU time 4.64 seconds
Started May 28 01:38:11 PM PDT 24
Finished May 28 01:38:20 PM PDT 24
Peak memory 200604 kb
Host smart-9f7044fc-eda7-47fd-b841-4d0cc308b263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498749886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1498749886
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1437783842
Short name T360
Test name
Test status
Simulation time 179620063 ps
CPU time 1.2 seconds
Started May 28 01:38:11 PM PDT 24
Finished May 28 01:38:15 PM PDT 24
Peak memory 200476 kb
Host smart-1f1584a3-2243-4abc-9c6f-b8f2d4291f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437783842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1437783842
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.554978625
Short name T209
Test name
Test status
Simulation time 193689928 ps
CPU time 1.36 seconds
Started May 28 01:38:14 PM PDT 24
Finished May 28 01:38:22 PM PDT 24
Peak memory 200680 kb
Host smart-6497a12d-845b-4031-8e36-d25a29d07d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554978625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.554978625
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2314591001
Short name T385
Test name
Test status
Simulation time 2757598453 ps
CPU time 13.19 seconds
Started May 28 01:38:15 PM PDT 24
Finished May 28 01:38:35 PM PDT 24
Peak memory 209028 kb
Host smart-86e07be8-66d7-4fe5-a1f5-0639f0302913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314591001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2314591001
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.676130979
Short name T384
Test name
Test status
Simulation time 130857291 ps
CPU time 1.62 seconds
Started May 28 01:38:13 PM PDT 24
Finished May 28 01:38:21 PM PDT 24
Peak memory 200484 kb
Host smart-965823b3-8e0a-491a-98f6-8416e4c02642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676130979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.676130979
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.721579781
Short name T316
Test name
Test status
Simulation time 178785472 ps
CPU time 1.17 seconds
Started May 28 01:38:11 PM PDT 24
Finished May 28 01:38:16 PM PDT 24
Peak memory 200408 kb
Host smart-c98e4dec-a15c-4f92-8b0e-635d10fa0141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721579781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.721579781
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.4122446385
Short name T477
Test name
Test status
Simulation time 60404998 ps
CPU time 0.75 seconds
Started May 28 01:38:14 PM PDT 24
Finished May 28 01:38:22 PM PDT 24
Peak memory 200324 kb
Host smart-3d3fcff5-dbdf-4814-a741-6b5da41706f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122446385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.4122446385
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.261329519
Short name T38
Test name
Test status
Simulation time 1895841842 ps
CPU time 7.44 seconds
Started May 28 01:38:14 PM PDT 24
Finished May 28 01:38:28 PM PDT 24
Peak memory 218100 kb
Host smart-5a6708fb-5afb-4b3b-b830-aa759637a54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261329519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.261329519
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3397717149
Short name T330
Test name
Test status
Simulation time 243817081 ps
CPU time 1.06 seconds
Started May 28 01:38:14 PM PDT 24
Finished May 28 01:38:21 PM PDT 24
Peak memory 217632 kb
Host smart-1f0ea496-18f1-43f9-863e-669ac43c8267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397717149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3397717149
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.4034359004
Short name T442
Test name
Test status
Simulation time 94322470 ps
CPU time 0.77 seconds
Started May 28 01:38:14 PM PDT 24
Finished May 28 01:38:21 PM PDT 24
Peak memory 200300 kb
Host smart-9c9173f4-73ee-4e55-90a2-b40b6f3672b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034359004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.4034359004
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3517623107
Short name T218
Test name
Test status
Simulation time 1173789565 ps
CPU time 5.14 seconds
Started May 28 01:38:14 PM PDT 24
Finished May 28 01:38:26 PM PDT 24
Peak memory 200680 kb
Host smart-92c93ee7-bff6-4ea4-93f7-43a9d3834b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517623107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3517623107
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1835081395
Short name T417
Test name
Test status
Simulation time 155704648 ps
CPU time 1.18 seconds
Started May 28 01:38:12 PM PDT 24
Finished May 28 01:38:18 PM PDT 24
Peak memory 200496 kb
Host smart-6c742e7c-5343-4365-b563-6cc8501bc005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835081395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1835081395
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1449834974
Short name T263
Test name
Test status
Simulation time 198246028 ps
CPU time 1.33 seconds
Started May 28 01:38:11 PM PDT 24
Finished May 28 01:38:16 PM PDT 24
Peak memory 200656 kb
Host smart-3824c7f8-029f-4789-91bc-73cae41c84b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449834974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1449834974
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1304855381
Short name T94
Test name
Test status
Simulation time 13767674552 ps
CPU time 53.5 seconds
Started May 28 01:38:20 PM PDT 24
Finished May 28 01:39:18 PM PDT 24
Peak memory 210736 kb
Host smart-79702bd3-5d46-4af4-8d3f-a109edd38870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304855381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1304855381
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1454852144
Short name T511
Test name
Test status
Simulation time 122241795 ps
CPU time 1.53 seconds
Started May 28 01:38:12 PM PDT 24
Finished May 28 01:38:19 PM PDT 24
Peak memory 208900 kb
Host smart-ad22cbc8-feb9-42d0-b0ce-a04b9223196a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454852144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1454852144
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3301754778
Short name T295
Test name
Test status
Simulation time 134448531 ps
CPU time 1.01 seconds
Started May 28 01:38:12 PM PDT 24
Finished May 28 01:38:18 PM PDT 24
Peak memory 200492 kb
Host smart-446b0e60-58da-46bf-a01c-12aa92b9606c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301754778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3301754778
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1080254347
Short name T307
Test name
Test status
Simulation time 69397911 ps
CPU time 0.8 seconds
Started May 28 01:38:14 PM PDT 24
Finished May 28 01:38:21 PM PDT 24
Peak memory 200324 kb
Host smart-e83efd3c-84b1-4334-b600-24ab5c79c92a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080254347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1080254347
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3792240594
Short name T47
Test name
Test status
Simulation time 1884339534 ps
CPU time 7.2 seconds
Started May 28 01:38:14 PM PDT 24
Finished May 28 01:38:28 PM PDT 24
Peak memory 218104 kb
Host smart-7a723d4a-bd19-4784-8d25-8f660c98cf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792240594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3792240594
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2858991594
Short name T142
Test name
Test status
Simulation time 244246786 ps
CPU time 1.11 seconds
Started May 28 01:38:14 PM PDT 24
Finished May 28 01:38:21 PM PDT 24
Peak memory 217952 kb
Host smart-34c73d14-b8ab-4148-9d66-83944d96b847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858991594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2858991594
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1197906289
Short name T515
Test name
Test status
Simulation time 225575651 ps
CPU time 0.87 seconds
Started May 28 01:38:12 PM PDT 24
Finished May 28 01:38:17 PM PDT 24
Peak memory 200232 kb
Host smart-590c41a3-c240-4008-ade3-8463363d944e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197906289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1197906289
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.639745975
Short name T311
Test name
Test status
Simulation time 855612411 ps
CPU time 4.5 seconds
Started May 28 01:38:16 PM PDT 24
Finished May 28 01:38:27 PM PDT 24
Peak memory 200648 kb
Host smart-624a2ade-90eb-4e71-811a-021889651849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639745975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.639745975
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1753960706
Short name T239
Test name
Test status
Simulation time 147538358 ps
CPU time 1.19 seconds
Started May 28 01:38:12 PM PDT 24
Finished May 28 01:38:19 PM PDT 24
Peak memory 200412 kb
Host smart-b22c82f2-a7da-4185-b9db-384c773d34e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753960706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1753960706
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2255039878
Short name T207
Test name
Test status
Simulation time 121325365 ps
CPU time 1.2 seconds
Started May 28 01:38:14 PM PDT 24
Finished May 28 01:38:22 PM PDT 24
Peak memory 200680 kb
Host smart-d6b7d328-a955-4c2b-b68c-1bf5413baaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255039878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2255039878
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1563321562
Short name T261
Test name
Test status
Simulation time 8580343277 ps
CPU time 30.33 seconds
Started May 28 01:38:15 PM PDT 24
Finished May 28 01:38:52 PM PDT 24
Peak memory 210684 kb
Host smart-0f903e55-c1b5-4abc-8ba6-4843cf7dc707
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563321562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1563321562
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2852293730
Short name T185
Test name
Test status
Simulation time 369786831 ps
CPU time 2.14 seconds
Started May 28 01:38:12 PM PDT 24
Finished May 28 01:38:19 PM PDT 24
Peak memory 200480 kb
Host smart-378d8997-ea06-4354-939e-c04611332524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852293730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2852293730
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1432329485
Short name T247
Test name
Test status
Simulation time 300198642 ps
CPU time 1.54 seconds
Started May 28 01:38:16 PM PDT 24
Finished May 28 01:38:24 PM PDT 24
Peak memory 200684 kb
Host smart-3abe7053-6a8a-4dea-bfc8-ab206e98510c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432329485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1432329485
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3001739565
Short name T56
Test name
Test status
Simulation time 60031347 ps
CPU time 0.76 seconds
Started May 28 01:37:22 PM PDT 24
Finished May 28 01:37:26 PM PDT 24
Peak memory 200328 kb
Host smart-b6a19045-4cef-42ee-ab30-6a3093e73f0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001739565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3001739565
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.4143449897
Short name T45
Test name
Test status
Simulation time 2357508001 ps
CPU time 9.76 seconds
Started May 28 01:37:21 PM PDT 24
Finished May 28 01:37:34 PM PDT 24
Peak memory 222232 kb
Host smart-ec2cb916-2cb1-44f2-8092-601e24ccb132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143449897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.4143449897
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.60174705
Short name T421
Test name
Test status
Simulation time 244526047 ps
CPU time 1.06 seconds
Started May 28 01:37:18 PM PDT 24
Finished May 28 01:37:20 PM PDT 24
Peak memory 217656 kb
Host smart-da35ec02-e198-45ae-bd7a-005382fa2396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60174705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.60174705
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2073293947
Short name T370
Test name
Test status
Simulation time 145409511 ps
CPU time 0.88 seconds
Started May 28 01:37:11 PM PDT 24
Finished May 28 01:37:13 PM PDT 24
Peak memory 200272 kb
Host smart-1cf30828-f25b-45a1-980b-fe6926017d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073293947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2073293947
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.4007281747
Short name T356
Test name
Test status
Simulation time 1828086210 ps
CPU time 6.47 seconds
Started May 28 01:37:11 PM PDT 24
Finished May 28 01:37:20 PM PDT 24
Peak memory 200680 kb
Host smart-150c72ea-1d0c-489c-a390-66a1656c8ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007281747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.4007281747
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1516867457
Short name T71
Test name
Test status
Simulation time 17045703558 ps
CPU time 24.98 seconds
Started May 28 01:37:22 PM PDT 24
Finished May 28 01:37:50 PM PDT 24
Peak memory 217492 kb
Host smart-fc9d3819-a79b-4a02-9dc9-2bcd67b91e91
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516867457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1516867457
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3273642639
Short name T52
Test name
Test status
Simulation time 105941591 ps
CPU time 1.02 seconds
Started May 28 01:37:20 PM PDT 24
Finished May 28 01:37:22 PM PDT 24
Peak memory 200504 kb
Host smart-2b6b3ea9-b2d8-49cc-9c24-62904a35dac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273642639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3273642639
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.3840601165
Short name T408
Test name
Test status
Simulation time 113580789 ps
CPU time 1.29 seconds
Started May 28 01:37:13 PM PDT 24
Finished May 28 01:37:15 PM PDT 24
Peak memory 200608 kb
Host smart-ce3c9d1f-e976-4269-8e97-83d88ceaf741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840601165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3840601165
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1245909428
Short name T104
Test name
Test status
Simulation time 1744627845 ps
CPU time 6.97 seconds
Started May 28 01:37:19 PM PDT 24
Finished May 28 01:37:27 PM PDT 24
Peak memory 200732 kb
Host smart-83e7579c-2756-47e8-8496-ab5a85e62039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245909428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1245909428
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1837845628
Short name T519
Test name
Test status
Simulation time 144159341 ps
CPU time 1.82 seconds
Started May 28 01:37:05 PM PDT 24
Finished May 28 01:37:09 PM PDT 24
Peak memory 200404 kb
Host smart-a903afa1-210e-424b-a765-3e880e9a7898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837845628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1837845628
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3450858318
Short name T240
Test name
Test status
Simulation time 224699793 ps
CPU time 1.39 seconds
Started May 28 01:37:08 PM PDT 24
Finished May 28 01:37:11 PM PDT 24
Peak memory 200492 kb
Host smart-e8d29ec6-3bed-47dc-9437-53c0bea2c831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450858318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3450858318
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.90377964
Short name T166
Test name
Test status
Simulation time 68772245 ps
CPU time 0.83 seconds
Started May 28 01:38:17 PM PDT 24
Finished May 28 01:38:24 PM PDT 24
Peak memory 200272 kb
Host smart-21269ae1-e047-40fc-8dbf-d1a2f2f1e9a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90377964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.90377964
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3688132977
Short name T231
Test name
Test status
Simulation time 1882389008 ps
CPU time 8.22 seconds
Started May 28 01:38:19 PM PDT 24
Finished May 28 01:38:33 PM PDT 24
Peak memory 218136 kb
Host smart-415936ad-e13a-4702-aed6-c55cd1c9fdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688132977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3688132977
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3265941676
Short name T24
Test name
Test status
Simulation time 245155095 ps
CPU time 1.07 seconds
Started May 28 01:38:17 PM PDT 24
Finished May 28 01:38:24 PM PDT 24
Peak memory 217500 kb
Host smart-142cdf18-a19e-46d5-ba40-91ac5acdf6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265941676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3265941676
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3425977851
Short name T287
Test name
Test status
Simulation time 148615719 ps
CPU time 0.85 seconds
Started May 28 01:38:19 PM PDT 24
Finished May 28 01:38:25 PM PDT 24
Peak memory 200288 kb
Host smart-2ebe822d-6794-4542-8bed-e1d6a391695e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425977851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3425977851
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.1414990971
Short name T334
Test name
Test status
Simulation time 988210296 ps
CPU time 5.12 seconds
Started May 28 01:38:20 PM PDT 24
Finished May 28 01:38:30 PM PDT 24
Peak memory 200656 kb
Host smart-ed05e260-ce3a-49ce-b564-20807dfbbe37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414990971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1414990971
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.477868878
Short name T270
Test name
Test status
Simulation time 103826657 ps
CPU time 1.05 seconds
Started May 28 01:38:15 PM PDT 24
Finished May 28 01:38:23 PM PDT 24
Peak memory 200520 kb
Host smart-15818f5a-cae9-48d0-b52d-1ff700aba7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477868878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.477868878
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.1197989171
Short name T380
Test name
Test status
Simulation time 120448792 ps
CPU time 1.22 seconds
Started May 28 01:38:14 PM PDT 24
Finished May 28 01:38:21 PM PDT 24
Peak memory 200932 kb
Host smart-872b4694-af62-4b14-be79-8d33852872fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197989171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.1197989171
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2413051539
Short name T155
Test name
Test status
Simulation time 210614428 ps
CPU time 1.46 seconds
Started May 28 01:38:16 PM PDT 24
Finished May 28 01:38:24 PM PDT 24
Peak memory 200708 kb
Host smart-366267e6-cdd3-4bec-83f7-2a2ab5008f06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413051539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2413051539
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.2607845189
Short name T165
Test name
Test status
Simulation time 352664218 ps
CPU time 2.26 seconds
Started May 28 01:38:20 PM PDT 24
Finished May 28 01:38:27 PM PDT 24
Peak memory 200464 kb
Host smart-84e688fd-9366-4863-9954-9b8d760b8135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607845189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2607845189
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.760333437
Short name T200
Test name
Test status
Simulation time 265789430 ps
CPU time 1.58 seconds
Started May 28 01:38:15 PM PDT 24
Finished May 28 01:38:23 PM PDT 24
Peak memory 200488 kb
Host smart-f0b1e3aa-be85-4f50-a1fc-5a493103f272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760333437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.760333437
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2578612680
Short name T447
Test name
Test status
Simulation time 69996618 ps
CPU time 0.87 seconds
Started May 28 01:38:29 PM PDT 24
Finished May 28 01:38:38 PM PDT 24
Peak memory 200328 kb
Host smart-795724cd-a54e-47ad-927a-0ab903bded0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578612680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2578612680
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.45077631
Short name T411
Test name
Test status
Simulation time 1903552517 ps
CPU time 7.37 seconds
Started May 28 01:38:12 PM PDT 24
Finished May 28 01:38:25 PM PDT 24
Peak memory 222080 kb
Host smart-f72cc6ed-94d5-4711-8d82-2b43d40926c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45077631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.45077631
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3721809195
Short name T81
Test name
Test status
Simulation time 244358960 ps
CPU time 1.09 seconds
Started May 28 01:38:17 PM PDT 24
Finished May 28 01:38:24 PM PDT 24
Peak memory 217656 kb
Host smart-c4303d22-b254-49d6-8f18-1a9cd4a16dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721809195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3721809195
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.2176475618
Short name T272
Test name
Test status
Simulation time 177692774 ps
CPU time 1 seconds
Started May 28 01:38:17 PM PDT 24
Finished May 28 01:38:24 PM PDT 24
Peak memory 200252 kb
Host smart-3285b760-42f9-4c5f-8bff-27c18d713c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176475618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2176475618
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2009593550
Short name T353
Test name
Test status
Simulation time 812988592 ps
CPU time 4.32 seconds
Started May 28 01:38:12 PM PDT 24
Finished May 28 01:38:21 PM PDT 24
Peak memory 200608 kb
Host smart-0a8e6c79-4aad-4a71-9b7f-ef2032194cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009593550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2009593550
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2442984706
Short name T148
Test name
Test status
Simulation time 194489047 ps
CPU time 1.31 seconds
Started May 28 01:38:15 PM PDT 24
Finished May 28 01:38:24 PM PDT 24
Peak memory 200500 kb
Host smart-be1974ad-b6a3-408d-afd5-7210374910e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442984706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2442984706
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3415143296
Short name T509
Test name
Test status
Simulation time 109953853 ps
CPU time 1.26 seconds
Started May 28 01:38:15 PM PDT 24
Finished May 28 01:38:23 PM PDT 24
Peak memory 200680 kb
Host smart-76c9d254-3dc6-47aa-813a-c3633650855f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415143296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3415143296
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.882263334
Short name T304
Test name
Test status
Simulation time 6383325571 ps
CPU time 20.82 seconds
Started May 28 01:38:17 PM PDT 24
Finished May 28 01:38:44 PM PDT 24
Peak memory 200796 kb
Host smart-f7aba253-dec3-4d42-aade-8077dadbd9ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882263334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.882263334
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.593530867
Short name T161
Test name
Test status
Simulation time 328274157 ps
CPU time 2.17 seconds
Started May 28 01:38:14 PM PDT 24
Finished May 28 01:38:23 PM PDT 24
Peak memory 200740 kb
Host smart-133b5d9a-90cd-4a0f-8096-bfd9180b011c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593530867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.593530867
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3727660864
Short name T57
Test name
Test status
Simulation time 88273488 ps
CPU time 0.91 seconds
Started May 28 01:38:12 PM PDT 24
Finished May 28 01:38:18 PM PDT 24
Peak memory 200504 kb
Host smart-31a5a04e-225f-4541-981c-37a72bfca50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727660864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3727660864
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2772387633
Short name T390
Test name
Test status
Simulation time 76108504 ps
CPU time 0.79 seconds
Started May 28 01:38:29 PM PDT 24
Finished May 28 01:38:38 PM PDT 24
Peak memory 200268 kb
Host smart-bb4d5b5e-cbd3-41b3-9a50-3255d4c47fd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772387633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2772387633
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.79033626
Short name T538
Test name
Test status
Simulation time 1229293751 ps
CPU time 6.06 seconds
Started May 28 01:38:26 PM PDT 24
Finished May 28 01:38:37 PM PDT 24
Peak memory 222168 kb
Host smart-f959c4c4-f9aa-403c-bc45-0d2b763948b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79033626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.79033626
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3915221204
Short name T487
Test name
Test status
Simulation time 244198629 ps
CPU time 1.1 seconds
Started May 28 01:38:29 PM PDT 24
Finished May 28 01:38:38 PM PDT 24
Peak memory 217764 kb
Host smart-a1fbd705-1a81-413e-a606-20d896e42238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915221204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3915221204
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2141066728
Short name T350
Test name
Test status
Simulation time 196072938 ps
CPU time 0.91 seconds
Started May 28 01:38:27 PM PDT 24
Finished May 28 01:38:33 PM PDT 24
Peak memory 200300 kb
Host smart-3efed88a-4c46-43ed-9a0b-361637c490fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141066728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2141066728
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1224665384
Short name T264
Test name
Test status
Simulation time 789033357 ps
CPU time 4.15 seconds
Started May 28 01:38:31 PM PDT 24
Finished May 28 01:38:43 PM PDT 24
Peak memory 200348 kb
Host smart-da6e6ce5-2098-42b0-8589-3f8e699e5a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224665384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1224665384
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3605379287
Short name T223
Test name
Test status
Simulation time 173284080 ps
CPU time 1.28 seconds
Started May 28 01:38:31 PM PDT 24
Finished May 28 01:38:40 PM PDT 24
Peak memory 200492 kb
Host smart-3f6ad745-6d75-45e0-89f4-56a9d81a451c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605379287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3605379287
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.4199533093
Short name T303
Test name
Test status
Simulation time 189707120 ps
CPU time 1.36 seconds
Started May 28 01:38:31 PM PDT 24
Finished May 28 01:38:39 PM PDT 24
Peak memory 200684 kb
Host smart-9a8acfe4-71b0-4466-aebf-648bcf232129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199533093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.4199533093
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1049687595
Short name T522
Test name
Test status
Simulation time 4839745970 ps
CPU time 20.52 seconds
Started May 28 01:38:29 PM PDT 24
Finished May 28 01:38:57 PM PDT 24
Peak memory 209020 kb
Host smart-fffa5342-5577-4f49-a1bd-d150e3790c8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049687595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1049687595
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.606883834
Short name T343
Test name
Test status
Simulation time 145416379 ps
CPU time 1.88 seconds
Started May 28 01:38:26 PM PDT 24
Finished May 28 01:38:33 PM PDT 24
Peak memory 200488 kb
Host smart-5a67ecf5-6e51-4584-a767-fc808f497c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606883834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.606883834
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.3389319528
Short name T280
Test name
Test status
Simulation time 166741670 ps
CPU time 1.12 seconds
Started May 28 01:38:29 PM PDT 24
Finished May 28 01:38:37 PM PDT 24
Peak memory 200740 kb
Host smart-5439fb13-347b-4dc6-9019-b6f34c8af639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389319528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3389319528
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.126474593
Short name T212
Test name
Test status
Simulation time 61899026 ps
CPU time 0.77 seconds
Started May 28 01:38:31 PM PDT 24
Finished May 28 01:38:39 PM PDT 24
Peak memory 199928 kb
Host smart-ffe37dc8-02d0-43d7-a3d6-7103a9309313
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126474593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.126474593
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.1633729935
Short name T33
Test name
Test status
Simulation time 1221073647 ps
CPU time 5.38 seconds
Started May 28 01:38:27 PM PDT 24
Finished May 28 01:38:39 PM PDT 24
Peak memory 222212 kb
Host smart-3eda0e33-0d9d-4386-8744-0c0a2e313705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633729935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.1633729935
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.252343050
Short name T279
Test name
Test status
Simulation time 244612327 ps
CPU time 1.1 seconds
Started May 28 01:38:29 PM PDT 24
Finished May 28 01:38:38 PM PDT 24
Peak memory 217580 kb
Host smart-2df8e460-362f-4b0c-a766-c5da1d7ff495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252343050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.252343050
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.484154146
Short name T449
Test name
Test status
Simulation time 184612212 ps
CPU time 0.9 seconds
Started May 28 01:38:26 PM PDT 24
Finished May 28 01:38:32 PM PDT 24
Peak memory 200316 kb
Host smart-d8bdd045-b406-46ea-8a70-10ace5a7c276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484154146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.484154146
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1093727131
Short name T495
Test name
Test status
Simulation time 1443343207 ps
CPU time 5.33 seconds
Started May 28 01:38:29 PM PDT 24
Finished May 28 01:38:41 PM PDT 24
Peak memory 200676 kb
Host smart-3347c342-73c5-4d38-a07d-265395689b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093727131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1093727131
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1420202325
Short name T535
Test name
Test status
Simulation time 144773837 ps
CPU time 1.15 seconds
Started May 28 01:38:27 PM PDT 24
Finished May 28 01:38:34 PM PDT 24
Peak memory 200436 kb
Host smart-360434b2-b4be-4fe0-a19c-e556078559c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420202325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1420202325
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3610656576
Short name T518
Test name
Test status
Simulation time 246074770 ps
CPU time 1.54 seconds
Started May 28 01:38:31 PM PDT 24
Finished May 28 01:38:40 PM PDT 24
Peak memory 200492 kb
Host smart-73a0a696-93cd-42c5-be85-3d26365f6c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610656576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3610656576
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2830078831
Short name T224
Test name
Test status
Simulation time 16438660126 ps
CPU time 57.15 seconds
Started May 28 01:38:27 PM PDT 24
Finished May 28 01:39:31 PM PDT 24
Peak memory 200816 kb
Host smart-a585033f-0598-41e6-94ee-d3cae356a714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830078831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2830078831
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.4119400016
Short name T158
Test name
Test status
Simulation time 261533284 ps
CPU time 1.89 seconds
Started May 28 01:38:28 PM PDT 24
Finished May 28 01:38:37 PM PDT 24
Peak memory 200436 kb
Host smart-37726b4a-902f-442a-a48a-e9bf623310f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119400016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.4119400016
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.744988114
Short name T286
Test name
Test status
Simulation time 70862153 ps
CPU time 0.79 seconds
Started May 28 01:38:28 PM PDT 24
Finished May 28 01:38:36 PM PDT 24
Peak memory 200484 kb
Host smart-c57c3119-93ca-4ed3-9443-8af1c4ca08fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744988114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.744988114
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.393942582
Short name T7
Test name
Test status
Simulation time 80610175 ps
CPU time 0.81 seconds
Started May 28 01:38:27 PM PDT 24
Finished May 28 01:38:34 PM PDT 24
Peak memory 200356 kb
Host smart-2da88601-ee8e-43ba-b131-d9dc1590c384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393942582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.393942582
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3451282104
Short name T514
Test name
Test status
Simulation time 1901500998 ps
CPU time 6.81 seconds
Started May 28 01:38:26 PM PDT 24
Finished May 28 01:38:38 PM PDT 24
Peak memory 222192 kb
Host smart-a9b8e95a-fd79-4563-8b1d-681b85e8ed68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451282104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3451282104
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1586017296
Short name T50
Test name
Test status
Simulation time 244416828 ps
CPU time 1.13 seconds
Started May 28 01:38:28 PM PDT 24
Finished May 28 01:38:36 PM PDT 24
Peak memory 217600 kb
Host smart-5b69472f-d612-4041-9e7e-e80ecc2e61ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586017296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1586017296
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3056062250
Short name T359
Test name
Test status
Simulation time 120605826 ps
CPU time 0.8 seconds
Started May 28 01:38:28 PM PDT 24
Finished May 28 01:38:35 PM PDT 24
Peak memory 200308 kb
Host smart-3cdac9c0-903a-462e-8da1-74a06cf30454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056062250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3056062250
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2805482845
Short name T278
Test name
Test status
Simulation time 1477243673 ps
CPU time 6.56 seconds
Started May 28 01:38:27 PM PDT 24
Finished May 28 01:38:38 PM PDT 24
Peak memory 200628 kb
Host smart-cc4bb716-1d17-4cee-afaa-4d5a0b9ee2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805482845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2805482845
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.2531281152
Short name T226
Test name
Test status
Simulation time 101154008 ps
CPU time 1.09 seconds
Started May 28 01:38:30 PM PDT 24
Finished May 28 01:38:38 PM PDT 24
Peak memory 200508 kb
Host smart-44ce90a9-3dc9-4052-bf96-3093d3be0fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531281152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.2531281152
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.4077702008
Short name T12
Test name
Test status
Simulation time 252576363 ps
CPU time 1.49 seconds
Started May 28 01:38:27 PM PDT 24
Finished May 28 01:38:35 PM PDT 24
Peak memory 200676 kb
Host smart-44218e6b-0781-4eed-b123-3c83854d784d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077702008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.4077702008
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1870149105
Short name T448
Test name
Test status
Simulation time 7058344114 ps
CPU time 23.89 seconds
Started May 28 01:38:28 PM PDT 24
Finished May 28 01:38:59 PM PDT 24
Peak memory 209024 kb
Host smart-d8b5e010-912a-4354-9b35-a5b7362918c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870149105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1870149105
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.2997490935
Short name T273
Test name
Test status
Simulation time 370200993 ps
CPU time 2.1 seconds
Started May 28 01:38:30 PM PDT 24
Finished May 28 01:38:39 PM PDT 24
Peak memory 200428 kb
Host smart-f42e4258-ac72-406e-8443-b755ee8325cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997490935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.2997490935
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.2405811819
Short name T341
Test name
Test status
Simulation time 266321557 ps
CPU time 1.63 seconds
Started May 28 01:38:28 PM PDT 24
Finished May 28 01:38:37 PM PDT 24
Peak memory 200720 kb
Host smart-f127324b-2426-4a75-a152-824145712f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405811819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2405811819
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1150391878
Short name T367
Test name
Test status
Simulation time 61984115 ps
CPU time 0.77 seconds
Started May 28 01:38:27 PM PDT 24
Finished May 28 01:38:34 PM PDT 24
Peak memory 200332 kb
Host smart-b9bb11e3-9953-4d0b-b4cb-637ea09ae391
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150391878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1150391878
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.2089689972
Short name T502
Test name
Test status
Simulation time 1223790938 ps
CPU time 5.34 seconds
Started May 28 01:38:28 PM PDT 24
Finished May 28 01:38:40 PM PDT 24
Peak memory 222212 kb
Host smart-f248cfef-9ea6-43ae-aa46-7be7e7c394bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089689972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2089689972
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.183175776
Short name T377
Test name
Test status
Simulation time 244027555 ps
CPU time 1.08 seconds
Started May 28 01:38:27 PM PDT 24
Finished May 28 01:38:35 PM PDT 24
Peak memory 217504 kb
Host smart-fed207d8-82b3-4b13-a62c-3ffabcda4919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183175776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.183175776
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3727021848
Short name T3
Test name
Test status
Simulation time 215034884 ps
CPU time 0.91 seconds
Started May 28 01:38:26 PM PDT 24
Finished May 28 01:38:32 PM PDT 24
Peak memory 200304 kb
Host smart-53174d40-ec82-430e-927d-58c21483152d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727021848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3727021848
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.543362402
Short name T406
Test name
Test status
Simulation time 1930387905 ps
CPU time 7.19 seconds
Started May 28 01:38:27 PM PDT 24
Finished May 28 01:38:40 PM PDT 24
Peak memory 200644 kb
Host smart-c6dc3a62-b2da-4011-b511-326939410c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543362402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.543362402
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.319652251
Short name T393
Test name
Test status
Simulation time 158824235 ps
CPU time 1.17 seconds
Started May 28 01:38:27 PM PDT 24
Finished May 28 01:38:35 PM PDT 24
Peak memory 200504 kb
Host smart-be1cbfa3-a5b1-424f-bb9b-f222575277a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319652251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.319652251
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.3791903875
Short name T333
Test name
Test status
Simulation time 111647849 ps
CPU time 1.17 seconds
Started May 28 01:38:28 PM PDT 24
Finished May 28 01:38:36 PM PDT 24
Peak memory 200696 kb
Host smart-0fe0f255-470b-425f-9b26-789e2f4de33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791903875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.3791903875
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1701991289
Short name T418
Test name
Test status
Simulation time 5005023126 ps
CPU time 19.49 seconds
Started May 28 01:38:26 PM PDT 24
Finished May 28 01:38:51 PM PDT 24
Peak memory 210436 kb
Host smart-eb97f133-31fa-4413-b19c-89b82d1c3bf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701991289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1701991289
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.2514674970
Short name T61
Test name
Test status
Simulation time 354207944 ps
CPU time 2.26 seconds
Started May 28 01:38:31 PM PDT 24
Finished May 28 01:38:40 PM PDT 24
Peak memory 200252 kb
Host smart-e65337a0-a1ad-4c68-a7d6-c9607f456818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514674970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2514674970
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2394623815
Short name T524
Test name
Test status
Simulation time 158815133 ps
CPU time 1.14 seconds
Started May 28 01:38:27 PM PDT 24
Finished May 28 01:38:35 PM PDT 24
Peak memory 200508 kb
Host smart-0f2cfad4-b828-46a2-96e3-b9583b8ab456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394623815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2394623815
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.377879449
Short name T484
Test name
Test status
Simulation time 75374593 ps
CPU time 0.87 seconds
Started May 28 01:38:29 PM PDT 24
Finished May 28 01:38:38 PM PDT 24
Peak memory 200300 kb
Host smart-c75f56ae-4934-4622-b0d5-34b06045e731
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377879449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.377879449
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1064079298
Short name T412
Test name
Test status
Simulation time 1217956175 ps
CPU time 5.6 seconds
Started May 28 01:38:30 PM PDT 24
Finished May 28 01:38:43 PM PDT 24
Peak memory 229864 kb
Host smart-b5c97fed-f286-4635-8340-b4affdff5d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064079298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1064079298
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2965887033
Short name T144
Test name
Test status
Simulation time 244484247 ps
CPU time 1.11 seconds
Started May 28 01:38:29 PM PDT 24
Finished May 28 01:38:37 PM PDT 24
Peak memory 217632 kb
Host smart-cb8c5c34-d8f9-43bf-b4f9-ac36a7fa3826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965887033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2965887033
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1711983702
Short name T18
Test name
Test status
Simulation time 221457442 ps
CPU time 0.93 seconds
Started May 28 01:38:27 PM PDT 24
Finished May 28 01:38:35 PM PDT 24
Peak memory 200288 kb
Host smart-4ec92d02-425a-49d4-9ddc-7da7c3d3afab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711983702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1711983702
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1977174413
Short name T325
Test name
Test status
Simulation time 1054414720 ps
CPU time 5.07 seconds
Started May 28 01:38:28 PM PDT 24
Finished May 28 01:38:40 PM PDT 24
Peak memory 200692 kb
Host smart-327f8a0a-37e9-4d9a-b469-afba8a269cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977174413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1977174413
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.4226394677
Short name T143
Test name
Test status
Simulation time 191906555 ps
CPU time 1.31 seconds
Started May 28 01:38:29 PM PDT 24
Finished May 28 01:38:38 PM PDT 24
Peak memory 200496 kb
Host smart-d876fffd-7db0-4067-b10c-c5a553c5f6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226394677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.4226394677
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.338846115
Short name T137
Test name
Test status
Simulation time 230583504 ps
CPU time 1.53 seconds
Started May 28 01:38:29 PM PDT 24
Finished May 28 01:38:37 PM PDT 24
Peak memory 200684 kb
Host smart-582c803a-bce9-4371-93fc-4193d24bff3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338846115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.338846115
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3230779448
Short name T433
Test name
Test status
Simulation time 13056632224 ps
CPU time 47.14 seconds
Started May 28 01:38:29 PM PDT 24
Finished May 28 01:39:24 PM PDT 24
Peak memory 209000 kb
Host smart-1ee09fb2-7c1d-4e3d-a3b2-f4685ec575ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230779448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3230779448
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.339871618
Short name T414
Test name
Test status
Simulation time 157283057 ps
CPU time 1.89 seconds
Started May 28 01:38:29 PM PDT 24
Finished May 28 01:38:38 PM PDT 24
Peak memory 200476 kb
Host smart-ee6ef82d-5003-49a8-8e41-eab2a586e308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339871618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.339871618
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.651104474
Short name T235
Test name
Test status
Simulation time 242826602 ps
CPU time 1.6 seconds
Started May 28 01:38:29 PM PDT 24
Finished May 28 01:38:38 PM PDT 24
Peak memory 200684 kb
Host smart-c93d237a-7a74-4e49-b11d-fe52fd7c500b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651104474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.651104474
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.2041748216
Short name T160
Test name
Test status
Simulation time 66157179 ps
CPU time 0.8 seconds
Started May 28 01:38:30 PM PDT 24
Finished May 28 01:38:38 PM PDT 24
Peak memory 200332 kb
Host smart-d1b2112f-7712-4ed7-8655-d78888831914
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041748216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2041748216
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2874702134
Short name T402
Test name
Test status
Simulation time 2163050097 ps
CPU time 7.86 seconds
Started May 28 01:38:29 PM PDT 24
Finished May 28 01:38:44 PM PDT 24
Peak memory 222344 kb
Host smart-3ad6a523-54c4-42ea-910e-f4c6b9e3ff16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874702134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2874702134
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2847882286
Short name T470
Test name
Test status
Simulation time 243990919 ps
CPU time 1.12 seconds
Started May 28 01:38:27 PM PDT 24
Finished May 28 01:38:34 PM PDT 24
Peak memory 217556 kb
Host smart-dbceaaa3-4187-4ac7-8940-01bfcd31dc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847882286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2847882286
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.642618562
Short name T397
Test name
Test status
Simulation time 143773391 ps
CPU time 0.86 seconds
Started May 28 01:38:28 PM PDT 24
Finished May 28 01:38:36 PM PDT 24
Peak memory 200308 kb
Host smart-75319a09-65c2-4cd9-8141-b84eb33fabfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642618562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.642618562
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2655708298
Short name T539
Test name
Test status
Simulation time 713335501 ps
CPU time 3.79 seconds
Started May 28 01:38:28 PM PDT 24
Finished May 28 01:38:39 PM PDT 24
Peak memory 200688 kb
Host smart-3446d76b-3c89-44ad-87c0-e18b8b086b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655708298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2655708298
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.455312020
Short name T492
Test name
Test status
Simulation time 106322897 ps
CPU time 1 seconds
Started May 28 01:38:30 PM PDT 24
Finished May 28 01:38:38 PM PDT 24
Peak memory 200504 kb
Host smart-cbac3736-9d5c-4b8e-8a48-4e70f853acab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455312020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.455312020
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2764037802
Short name T88
Test name
Test status
Simulation time 123860220 ps
CPU time 1.33 seconds
Started May 28 01:38:33 PM PDT 24
Finished May 28 01:38:40 PM PDT 24
Peak memory 200688 kb
Host smart-f90442df-449b-4688-8b2d-7fa02ee21d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764037802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2764037802
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2601461534
Short name T146
Test name
Test status
Simulation time 144523710 ps
CPU time 1.82 seconds
Started May 28 01:38:27 PM PDT 24
Finished May 28 01:38:35 PM PDT 24
Peak memory 200496 kb
Host smart-81618d24-7476-46a1-9e24-4919a3bd20f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601461534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2601461534
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2548526056
Short name T136
Test name
Test status
Simulation time 266615440 ps
CPU time 1.59 seconds
Started May 28 01:38:29 PM PDT 24
Finished May 28 01:38:37 PM PDT 24
Peak memory 200680 kb
Host smart-4550d19b-c574-4d1f-a9c9-5dae1ecc932b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548526056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2548526056
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.554197220
Short name T493
Test name
Test status
Simulation time 57664889 ps
CPU time 0.79 seconds
Started May 28 01:38:45 PM PDT 24
Finished May 28 01:38:49 PM PDT 24
Peak memory 200272 kb
Host smart-8f91fba0-4853-4d6f-87ee-6651233a6c7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554197220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.554197220
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1191136886
Short name T326
Test name
Test status
Simulation time 1228950520 ps
CPU time 5.61 seconds
Started May 28 01:38:45 PM PDT 24
Finished May 28 01:38:55 PM PDT 24
Peak memory 222048 kb
Host smart-b8a33cb9-eea7-4cb8-a60d-38ff215c50aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191136886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1191136886
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2988640310
Short name T496
Test name
Test status
Simulation time 244203748 ps
CPU time 1.05 seconds
Started May 28 01:38:46 PM PDT 24
Finished May 28 01:38:52 PM PDT 24
Peak memory 217600 kb
Host smart-0e371284-f2ce-4a9f-976e-7e5e37023a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988640310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2988640310
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2648996950
Short name T176
Test name
Test status
Simulation time 184618614 ps
CPU time 0.85 seconds
Started May 28 01:38:31 PM PDT 24
Finished May 28 01:38:39 PM PDT 24
Peak memory 200308 kb
Host smart-43f275e5-fb2e-465e-a109-d0b3e395f0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648996950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2648996950
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1960449303
Short name T536
Test name
Test status
Simulation time 1067754647 ps
CPU time 5.67 seconds
Started May 28 01:38:30 PM PDT 24
Finished May 28 01:38:43 PM PDT 24
Peak memory 200668 kb
Host smart-a1b8d051-3715-41c3-a951-2dd172dc3509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960449303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1960449303
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2379219349
Short name T268
Test name
Test status
Simulation time 149855767 ps
CPU time 1.14 seconds
Started May 28 01:38:42 PM PDT 24
Finished May 28 01:38:44 PM PDT 24
Peak memory 200492 kb
Host smart-4cb575d3-f4cf-43aa-bb2c-dec9b59e08df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379219349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2379219349
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.1891533294
Short name T154
Test name
Test status
Simulation time 123745162 ps
CPU time 1.19 seconds
Started May 28 01:38:31 PM PDT 24
Finished May 28 01:38:39 PM PDT 24
Peak memory 200568 kb
Host smart-17fc396e-904c-4c44-89c1-54531619dde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891533294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1891533294
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.358921240
Short name T110
Test name
Test status
Simulation time 12750378937 ps
CPU time 39.91 seconds
Started May 28 01:38:43 PM PDT 24
Finished May 28 01:39:25 PM PDT 24
Peak memory 209536 kb
Host smart-8136c8b9-6597-404e-b29c-7dba2528c8d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358921240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.358921240
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3873671251
Short name T504
Test name
Test status
Simulation time 360161969 ps
CPU time 2.22 seconds
Started May 28 01:38:31 PM PDT 24
Finished May 28 01:38:40 PM PDT 24
Peak memory 200396 kb
Host smart-4d35bd4b-8401-49cb-b35c-07a2faca3997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873671251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3873671251
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.786693983
Short name T187
Test name
Test status
Simulation time 103957124 ps
CPU time 0.9 seconds
Started May 28 01:38:31 PM PDT 24
Finished May 28 01:38:39 PM PDT 24
Peak memory 200444 kb
Host smart-99f64fda-58af-4178-8dd1-cfe1df4ed991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786693983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.786693983
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.2015163111
Short name T530
Test name
Test status
Simulation time 74991804 ps
CPU time 0.81 seconds
Started May 28 01:38:47 PM PDT 24
Finished May 28 01:38:52 PM PDT 24
Peak memory 200332 kb
Host smart-b6333a0d-a378-4e12-a46c-dcac8de39a9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015163111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2015163111
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2982484367
Short name T58
Test name
Test status
Simulation time 1220867236 ps
CPU time 6.22 seconds
Started May 28 01:38:47 PM PDT 24
Finished May 28 01:38:57 PM PDT 24
Peak memory 218144 kb
Host smart-7508989a-7f30-4f45-b488-37bd76544697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982484367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2982484367
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.738643748
Short name T288
Test name
Test status
Simulation time 243359240 ps
CPU time 1.15 seconds
Started May 28 01:38:43 PM PDT 24
Finished May 28 01:38:45 PM PDT 24
Peak memory 217732 kb
Host smart-51c890a5-aa52-45bc-8f87-114e7443bfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738643748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.738643748
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.3380538651
Short name T338
Test name
Test status
Simulation time 151703745 ps
CPU time 0.88 seconds
Started May 28 01:38:43 PM PDT 24
Finished May 28 01:38:46 PM PDT 24
Peak memory 200344 kb
Host smart-28053bc7-e26b-4966-af83-91ef5f3ae92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380538651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3380538651
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1325037128
Short name T103
Test name
Test status
Simulation time 1818294928 ps
CPU time 6.92 seconds
Started May 28 01:38:45 PM PDT 24
Finished May 28 01:38:56 PM PDT 24
Peak memory 200716 kb
Host smart-3b815fb3-6a93-4ed0-9e4a-d8216345c69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325037128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1325037128
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2423952778
Short name T269
Test name
Test status
Simulation time 148022269 ps
CPU time 1.24 seconds
Started May 28 01:38:46 PM PDT 24
Finished May 28 01:38:51 PM PDT 24
Peak memory 200452 kb
Host smart-8ee61dff-f5b9-4a5d-ae3c-33bf5a79f0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423952778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2423952778
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2009820928
Short name T194
Test name
Test status
Simulation time 187328670 ps
CPU time 1.38 seconds
Started May 28 01:38:44 PM PDT 24
Finished May 28 01:38:49 PM PDT 24
Peak memory 200676 kb
Host smart-3d669107-d899-4916-8741-1def4282c325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009820928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2009820928
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2615306852
Short name T108
Test name
Test status
Simulation time 8398182000 ps
CPU time 27.35 seconds
Started May 28 01:38:43 PM PDT 24
Finished May 28 01:39:12 PM PDT 24
Peak memory 200868 kb
Host smart-93d00171-d029-44fe-803e-4fc58086b9fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615306852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2615306852
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1379870950
Short name T93
Test name
Test status
Simulation time 437404580 ps
CPU time 2.4 seconds
Started May 28 01:38:49 PM PDT 24
Finished May 28 01:38:55 PM PDT 24
Peak memory 208792 kb
Host smart-e08b6ad4-d543-4926-9092-0945f7ac0dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379870950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1379870950
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3595747845
Short name T195
Test name
Test status
Simulation time 169748661 ps
CPU time 1.31 seconds
Started May 28 01:38:49 PM PDT 24
Finished May 28 01:38:54 PM PDT 24
Peak memory 200712 kb
Host smart-95810776-12e5-45e0-828c-ea797ff79974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595747845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3595747845
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3534349610
Short name T20
Test name
Test status
Simulation time 78321283 ps
CPU time 0.78 seconds
Started May 28 01:37:18 PM PDT 24
Finished May 28 01:37:20 PM PDT 24
Peak memory 200344 kb
Host smart-14185d28-a0e4-449a-ba32-5e62bcb6dc13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534349610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3534349610
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.4191477596
Short name T292
Test name
Test status
Simulation time 1232656250 ps
CPU time 6.11 seconds
Started May 28 01:37:25 PM PDT 24
Finished May 28 01:37:34 PM PDT 24
Peak memory 221076 kb
Host smart-1a04ae75-1e8c-4c84-a98c-dd76f0a4f928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191477596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.4191477596
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2814896813
Short name T392
Test name
Test status
Simulation time 245446592 ps
CPU time 1.08 seconds
Started May 28 01:37:21 PM PDT 24
Finished May 28 01:37:24 PM PDT 24
Peak memory 217592 kb
Host smart-b60702de-94cd-4ed3-8fad-d44d17c8f0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814896813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2814896813
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3012657590
Short name T19
Test name
Test status
Simulation time 104369263 ps
CPU time 0.81 seconds
Started May 28 01:37:20 PM PDT 24
Finished May 28 01:37:23 PM PDT 24
Peak memory 200224 kb
Host smart-809d99f9-8a22-4b55-a99a-7b1f66df7932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012657590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3012657590
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2925684339
Short name T398
Test name
Test status
Simulation time 1397425404 ps
CPU time 6.01 seconds
Started May 28 01:37:23 PM PDT 24
Finished May 28 01:37:33 PM PDT 24
Peak memory 200700 kb
Host smart-bf9007f0-8c04-40dd-aa75-0af1943c2c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925684339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2925684339
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3222057951
Short name T74
Test name
Test status
Simulation time 16513738362 ps
CPU time 26.27 seconds
Started May 28 01:37:22 PM PDT 24
Finished May 28 01:37:52 PM PDT 24
Peak memory 217720 kb
Host smart-73202c6c-30a4-48b0-8e29-ba7e61d23627
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222057951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3222057951
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.669411164
Short name T324
Test name
Test status
Simulation time 158231884 ps
CPU time 1.12 seconds
Started May 28 01:37:20 PM PDT 24
Finished May 28 01:37:24 PM PDT 24
Peak memory 200444 kb
Host smart-6ab817a5-4c8d-4500-9061-33a013770de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669411164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.669411164
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1304684401
Short name T40
Test name
Test status
Simulation time 245659009 ps
CPU time 1.48 seconds
Started May 28 01:37:20 PM PDT 24
Finished May 28 01:37:23 PM PDT 24
Peak memory 200680 kb
Host smart-8b7dfd5a-dbd5-44ac-8927-6f3f90a5b13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304684401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1304684401
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3792042746
Short name T217
Test name
Test status
Simulation time 8541066190 ps
CPU time 34.06 seconds
Started May 28 01:37:22 PM PDT 24
Finished May 28 01:38:00 PM PDT 24
Peak memory 200788 kb
Host smart-e4623d0b-99a2-49b2-bc0c-65d146ab532d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792042746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3792042746
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.4163332389
Short name T249
Test name
Test status
Simulation time 516418662 ps
CPU time 2.76 seconds
Started May 28 01:37:19 PM PDT 24
Finished May 28 01:37:23 PM PDT 24
Peak memory 200428 kb
Host smart-b937b49b-6803-47a3-b706-d951237f7e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163332389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.4163332389
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1536499948
Short name T309
Test name
Test status
Simulation time 132445944 ps
CPU time 1.09 seconds
Started May 28 01:37:21 PM PDT 24
Finished May 28 01:37:24 PM PDT 24
Peak memory 200508 kb
Host smart-69cc632f-ed61-48ea-86a8-36ff63c5ef73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536499948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1536499948
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.1991573157
Short name T184
Test name
Test status
Simulation time 87940428 ps
CPU time 0.87 seconds
Started May 28 01:38:46 PM PDT 24
Finished May 28 01:38:51 PM PDT 24
Peak memory 200336 kb
Host smart-b8910713-2180-4584-952b-fbfc314af721
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991573157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.1991573157
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.873698356
Short name T59
Test name
Test status
Simulation time 1895418901 ps
CPU time 7.22 seconds
Started May 28 01:38:48 PM PDT 24
Finished May 28 01:38:59 PM PDT 24
Peak memory 216968 kb
Host smart-14973adf-dc0e-4fa4-abbc-a428d7ea0245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873698356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.873698356
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.4197509085
Short name T298
Test name
Test status
Simulation time 245982875 ps
CPU time 1.09 seconds
Started May 28 01:38:42 PM PDT 24
Finished May 28 01:38:44 PM PDT 24
Peak memory 217536 kb
Host smart-ac907672-7df6-499e-ad9c-70422bd5fda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197509085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.4197509085
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.2021718156
Short name T399
Test name
Test status
Simulation time 175785560 ps
CPU time 0.93 seconds
Started May 28 01:38:44 PM PDT 24
Finished May 28 01:38:47 PM PDT 24
Peak memory 200292 kb
Host smart-b362d003-7698-40d6-801f-40f62af7b084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021718156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2021718156
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.937802719
Short name T21
Test name
Test status
Simulation time 951753223 ps
CPU time 4.96 seconds
Started May 28 01:38:42 PM PDT 24
Finished May 28 01:38:48 PM PDT 24
Peak memory 200724 kb
Host smart-1fac98db-3401-4df6-9365-d5aa68f28b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937802719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.937802719
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1891087295
Short name T169
Test name
Test status
Simulation time 149106726 ps
CPU time 1.21 seconds
Started May 28 01:38:45 PM PDT 24
Finished May 28 01:38:49 PM PDT 24
Peak memory 200500 kb
Host smart-9e6d272d-7656-4b05-bba5-54e9004aaba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891087295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1891087295
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.839727329
Short name T312
Test name
Test status
Simulation time 114525324 ps
CPU time 1.21 seconds
Started May 28 01:38:44 PM PDT 24
Finished May 28 01:38:48 PM PDT 24
Peak memory 200700 kb
Host smart-d0ffb602-5fce-478d-a94a-e991426f3a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839727329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.839727329
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.1073416685
Short name T237
Test name
Test status
Simulation time 8142434092 ps
CPU time 27.43 seconds
Started May 28 01:38:45 PM PDT 24
Finished May 28 01:39:16 PM PDT 24
Peak memory 209048 kb
Host smart-9ef1b1cc-25d7-4b80-9084-2b0671914e1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073416685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1073416685
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.4156938855
Short name T252
Test name
Test status
Simulation time 281486211 ps
CPU time 2.01 seconds
Started May 28 01:38:46 PM PDT 24
Finished May 28 01:38:52 PM PDT 24
Peak memory 200456 kb
Host smart-341dfb39-3f61-48ad-b7a0-dcf90cce8e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156938855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.4156938855
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3430338951
Short name T220
Test name
Test status
Simulation time 247078314 ps
CPU time 1.46 seconds
Started May 28 01:38:46 PM PDT 24
Finished May 28 01:38:52 PM PDT 24
Peak memory 200472 kb
Host smart-3bac62e3-06e5-4afa-ae56-288589833d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430338951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3430338951
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1703149580
Short name T250
Test name
Test status
Simulation time 81913454 ps
CPU time 0.83 seconds
Started May 28 01:38:44 PM PDT 24
Finished May 28 01:38:48 PM PDT 24
Peak memory 200328 kb
Host smart-56cdf5f1-53fd-4793-a533-4e604d03258e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703149580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1703149580
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.1902721196
Short name T471
Test name
Test status
Simulation time 245908940 ps
CPU time 1.05 seconds
Started May 28 01:38:44 PM PDT 24
Finished May 28 01:38:47 PM PDT 24
Peak memory 217572 kb
Host smart-1e582178-cab6-4197-a32a-b6f9c47eaa6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902721196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.1902721196
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.4122223210
Short name T13
Test name
Test status
Simulation time 200831565 ps
CPU time 0.89 seconds
Started May 28 01:38:44 PM PDT 24
Finished May 28 01:38:47 PM PDT 24
Peak memory 200312 kb
Host smart-68bac35a-7094-4587-a42e-68a3cace66d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122223210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.4122223210
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3974090502
Short name T111
Test name
Test status
Simulation time 1544834903 ps
CPU time 5.73 seconds
Started May 28 01:38:45 PM PDT 24
Finished May 28 01:38:54 PM PDT 24
Peak memory 200640 kb
Host smart-30a1308b-1b9c-427c-b73b-b0d12ec41591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974090502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3974090502
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1640040171
Short name T35
Test name
Test status
Simulation time 146411161 ps
CPU time 1.23 seconds
Started May 28 01:38:46 PM PDT 24
Finished May 28 01:38:52 PM PDT 24
Peak memory 200496 kb
Host smart-620229b2-d687-4614-87a0-cf360ce60182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640040171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1640040171
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1606340005
Short name T528
Test name
Test status
Simulation time 186941463 ps
CPU time 1.3 seconds
Started May 28 01:38:46 PM PDT 24
Finished May 28 01:38:51 PM PDT 24
Peak memory 200680 kb
Host smart-dcdc1b57-e16c-465d-9768-b088c9aa2921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606340005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1606340005
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1874381228
Short name T440
Test name
Test status
Simulation time 893330077 ps
CPU time 4.36 seconds
Started May 28 01:38:44 PM PDT 24
Finished May 28 01:38:52 PM PDT 24
Peak memory 200728 kb
Host smart-08858f66-7c0d-41e0-8a7c-9f8bdd4380c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874381228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1874381228
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.147278185
Short name T306
Test name
Test status
Simulation time 122576290 ps
CPU time 1.6 seconds
Started May 28 01:38:45 PM PDT 24
Finished May 28 01:38:51 PM PDT 24
Peak memory 208712 kb
Host smart-826787e5-677d-4e1a-a495-41f6f38222e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147278185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.147278185
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2366054620
Short name T84
Test name
Test status
Simulation time 204541621 ps
CPU time 1.4 seconds
Started May 28 01:38:43 PM PDT 24
Finished May 28 01:38:47 PM PDT 24
Peak memory 200492 kb
Host smart-a2e311cd-a6dd-474f-897e-1df3875619e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366054620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2366054620
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2392921374
Short name T170
Test name
Test status
Simulation time 80611983 ps
CPU time 0.88 seconds
Started May 28 01:38:47 PM PDT 24
Finished May 28 01:38:52 PM PDT 24
Peak memory 200332 kb
Host smart-1f2a4ad1-259c-4d7a-8a3e-8721025ef9cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392921374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2392921374
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2176424645
Short name T46
Test name
Test status
Simulation time 1891461020 ps
CPU time 7.14 seconds
Started May 28 01:38:46 PM PDT 24
Finished May 28 01:38:57 PM PDT 24
Peak memory 217664 kb
Host smart-0035c2ef-a676-4c97-a589-694dfda99ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176424645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2176424645
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.4152901603
Short name T149
Test name
Test status
Simulation time 244322803 ps
CPU time 1.11 seconds
Started May 28 01:38:43 PM PDT 24
Finished May 28 01:38:46 PM PDT 24
Peak memory 217728 kb
Host smart-9edb6aee-9e41-4944-9e90-201c691e61b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152901603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.4152901603
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.4103979435
Short name T14
Test name
Test status
Simulation time 195572181 ps
CPU time 0.99 seconds
Started May 28 01:38:44 PM PDT 24
Finished May 28 01:38:47 PM PDT 24
Peak memory 200308 kb
Host smart-8c5b5e90-a4d6-4500-bb28-8640bc631e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103979435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.4103979435
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1626023151
Short name T388
Test name
Test status
Simulation time 149702072 ps
CPU time 1.09 seconds
Started May 28 01:38:47 PM PDT 24
Finished May 28 01:38:52 PM PDT 24
Peak memory 200492 kb
Host smart-fc79d28b-28b9-4ad4-87d9-680b29d472bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626023151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1626023151
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.4194145645
Short name T352
Test name
Test status
Simulation time 113241631 ps
CPU time 1.21 seconds
Started May 28 01:38:44 PM PDT 24
Finished May 28 01:38:47 PM PDT 24
Peak memory 200684 kb
Host smart-3106aca2-30cb-4b22-9f2e-ef81d1bbfeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194145645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.4194145645
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.696628724
Short name T364
Test name
Test status
Simulation time 5928037658 ps
CPU time 25.76 seconds
Started May 28 01:38:43 PM PDT 24
Finished May 28 01:39:10 PM PDT 24
Peak memory 209040 kb
Host smart-51450c11-5117-4aef-9ee3-70640d4415c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696628724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.696628724
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3986867410
Short name T36
Test name
Test status
Simulation time 387279748 ps
CPU time 2.36 seconds
Started May 28 01:38:47 PM PDT 24
Finished May 28 01:38:54 PM PDT 24
Peak memory 200484 kb
Host smart-b6186228-fd19-46bf-bce9-904b39dfde1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986867410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3986867410
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3261456057
Short name T490
Test name
Test status
Simulation time 157360163 ps
CPU time 1.19 seconds
Started May 28 01:38:47 PM PDT 24
Finished May 28 01:38:52 PM PDT 24
Peak memory 200492 kb
Host smart-2a3b7722-aed3-4d31-928f-33d1c5ad1577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261456057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3261456057
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.290259955
Short name T92
Test name
Test status
Simulation time 68161412 ps
CPU time 0.84 seconds
Started May 28 01:38:44 PM PDT 24
Finished May 28 01:38:48 PM PDT 24
Peak memory 200332 kb
Host smart-fb6ff047-5053-419d-b96f-ab6e29c19893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290259955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.290259955
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.914654790
Short name T317
Test name
Test status
Simulation time 2351962929 ps
CPU time 8.23 seconds
Started May 28 01:38:47 PM PDT 24
Finished May 28 01:38:59 PM PDT 24
Peak memory 222348 kb
Host smart-ad2d91a8-6ea1-4244-ba4b-7bb94a9cd574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914654790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.914654790
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3712554348
Short name T394
Test name
Test status
Simulation time 246148665 ps
CPU time 1.14 seconds
Started May 28 01:38:44 PM PDT 24
Finished May 28 01:38:47 PM PDT 24
Peak memory 217748 kb
Host smart-67bd46f0-a9d2-44fd-a216-3921c2f78f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712554348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3712554348
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3410255619
Short name T346
Test name
Test status
Simulation time 94236482 ps
CPU time 0.75 seconds
Started May 28 01:38:43 PM PDT 24
Finished May 28 01:38:46 PM PDT 24
Peak memory 200304 kb
Host smart-0a9bf7cf-d366-4a41-9ac1-14812549681b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410255619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3410255619
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2837528710
Short name T106
Test name
Test status
Simulation time 1937053241 ps
CPU time 7.42 seconds
Started May 28 01:38:45 PM PDT 24
Finished May 28 01:38:56 PM PDT 24
Peak memory 200696 kb
Host smart-5ee49375-295f-4b39-9d4d-a35dcff24ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837528710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2837528710
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2145156562
Short name T199
Test name
Test status
Simulation time 188500528 ps
CPU time 1.26 seconds
Started May 28 01:38:44 PM PDT 24
Finished May 28 01:38:48 PM PDT 24
Peak memory 200496 kb
Host smart-39bc22d1-5eb0-4e32-b3f1-d136fbe35014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145156562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2145156562
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1372349692
Short name T241
Test name
Test status
Simulation time 118572583 ps
CPU time 1.14 seconds
Started May 28 01:38:44 PM PDT 24
Finished May 28 01:38:47 PM PDT 24
Peak memory 200680 kb
Host smart-50496944-f5ab-4bd7-a3e4-a2e08177c8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372349692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1372349692
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3976304851
Short name T505
Test name
Test status
Simulation time 3988944098 ps
CPU time 17.58 seconds
Started May 28 01:38:44 PM PDT 24
Finished May 28 01:39:05 PM PDT 24
Peak memory 200884 kb
Host smart-466f4b7e-f5d8-486b-ba9e-e1d0e96deee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976304851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3976304851
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.154874313
Short name T378
Test name
Test status
Simulation time 424037818 ps
CPU time 2.42 seconds
Started May 28 01:38:44 PM PDT 24
Finished May 28 01:38:50 PM PDT 24
Peak memory 208776 kb
Host smart-8ec93479-6a26-475b-b477-afe6c82b3886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154874313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.154874313
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1216306521
Short name T486
Test name
Test status
Simulation time 198499558 ps
CPU time 1.27 seconds
Started May 28 01:38:46 PM PDT 24
Finished May 28 01:38:51 PM PDT 24
Peak memory 200472 kb
Host smart-16593064-7ff8-4a7b-947c-d895cf09ef2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216306521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1216306521
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3313368908
Short name T201
Test name
Test status
Simulation time 81280152 ps
CPU time 0.89 seconds
Started May 28 01:38:45 PM PDT 24
Finished May 28 01:38:49 PM PDT 24
Peak memory 200332 kb
Host smart-54c70eaa-b4bd-47c5-9315-8bf54981f34c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313368908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3313368908
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1182052604
Short name T389
Test name
Test status
Simulation time 1218758155 ps
CPU time 5.62 seconds
Started May 28 01:38:49 PM PDT 24
Finished May 28 01:38:58 PM PDT 24
Peak memory 222220 kb
Host smart-2707f147-6ec4-40a5-83a1-064194f48f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182052604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1182052604
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2554502303
Short name T232
Test name
Test status
Simulation time 246736006 ps
CPU time 1.05 seconds
Started May 28 01:38:49 PM PDT 24
Finished May 28 01:38:54 PM PDT 24
Peak memory 217768 kb
Host smart-7ac18c0d-0d37-4c0c-8744-667843a1d618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554502303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2554502303
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.305295681
Short name T254
Test name
Test status
Simulation time 143239164 ps
CPU time 0.84 seconds
Started May 28 01:38:46 PM PDT 24
Finished May 28 01:38:51 PM PDT 24
Peak memory 200300 kb
Host smart-04437c0d-a3cf-460e-bccd-b0cfaffdb3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305295681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.305295681
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3097524014
Short name T105
Test name
Test status
Simulation time 1707926622 ps
CPU time 6.13 seconds
Started May 28 01:38:46 PM PDT 24
Finished May 28 01:38:56 PM PDT 24
Peak memory 200656 kb
Host smart-40fd6ee3-2fca-4f6d-b512-44214907f7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097524014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3097524014
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3800709130
Short name T183
Test name
Test status
Simulation time 109152215 ps
CPU time 1.09 seconds
Started May 28 01:38:47 PM PDT 24
Finished May 28 01:38:52 PM PDT 24
Peak memory 200508 kb
Host smart-64aa6fee-7d2b-4ad2-9637-8ca16dadeb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800709130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3800709130
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1936689526
Short name T446
Test name
Test status
Simulation time 114196796 ps
CPU time 1.26 seconds
Started May 28 01:38:45 PM PDT 24
Finished May 28 01:38:49 PM PDT 24
Peak memory 200680 kb
Host smart-f5c0cda8-3d61-4dd8-8f3d-94e5da44ee5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936689526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1936689526
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2381752206
Short name T255
Test name
Test status
Simulation time 3919136015 ps
CPU time 14.67 seconds
Started May 28 01:38:47 PM PDT 24
Finished May 28 01:39:06 PM PDT 24
Peak memory 200824 kb
Host smart-2b02129c-363a-41e5-92d4-2d6893a4f7d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381752206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2381752206
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.4066382550
Short name T23
Test name
Test status
Simulation time 237663685 ps
CPU time 1.52 seconds
Started May 28 01:38:47 PM PDT 24
Finished May 28 01:38:53 PM PDT 24
Peak memory 200492 kb
Host smart-ee5db5e5-2e0a-46dd-b099-50ff8d66abbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066382550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.4066382550
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.1127861611
Short name T190
Test name
Test status
Simulation time 81653954 ps
CPU time 0.84 seconds
Started May 28 01:39:00 PM PDT 24
Finished May 28 01:39:05 PM PDT 24
Peak memory 200336 kb
Host smart-0bed1f9c-0dba-4fe0-8768-686cfa7e16a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127861611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1127861611
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.3010710903
Short name T439
Test name
Test status
Simulation time 1228794084 ps
CPU time 6.33 seconds
Started May 28 01:38:58 PM PDT 24
Finished May 28 01:39:08 PM PDT 24
Peak memory 217600 kb
Host smart-7f3fe77c-363a-486d-bb05-f77b48912fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010710903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.3010710903
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1039116135
Short name T488
Test name
Test status
Simulation time 244788527 ps
CPU time 1.07 seconds
Started May 28 01:38:59 PM PDT 24
Finished May 28 01:39:04 PM PDT 24
Peak memory 217572 kb
Host smart-bbf72ef6-32e0-4ef3-96cb-871c0cfaaeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039116135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1039116135
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3294360142
Short name T454
Test name
Test status
Simulation time 161572383 ps
CPU time 0.88 seconds
Started May 28 01:38:48 PM PDT 24
Finished May 28 01:38:53 PM PDT 24
Peak memory 200276 kb
Host smart-6c5fabe8-28cf-4cd7-a455-7e4eab18dee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294360142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3294360142
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1030310746
Short name T453
Test name
Test status
Simulation time 1688871743 ps
CPU time 6.45 seconds
Started May 28 01:38:47 PM PDT 24
Finished May 28 01:38:57 PM PDT 24
Peak memory 200680 kb
Host smart-48734b94-7683-4e8c-abdc-b3eb8c4cf7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030310746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1030310746
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3953048995
Short name T355
Test name
Test status
Simulation time 154904727 ps
CPU time 1.21 seconds
Started May 28 01:38:59 PM PDT 24
Finished May 28 01:39:03 PM PDT 24
Peak memory 200480 kb
Host smart-d94875ae-9e02-4009-a209-4b0b12a6df84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953048995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3953048995
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3876226879
Short name T153
Test name
Test status
Simulation time 194119744 ps
CPU time 1.48 seconds
Started May 28 01:38:47 PM PDT 24
Finished May 28 01:38:53 PM PDT 24
Peak memory 200720 kb
Host smart-d2290d48-49ef-463e-b3db-338d604e4a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876226879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3876226879
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.2305548499
Short name T113
Test name
Test status
Simulation time 3373923186 ps
CPU time 12.49 seconds
Started May 28 01:38:58 PM PDT 24
Finished May 28 01:39:12 PM PDT 24
Peak memory 200848 kb
Host smart-41d37207-6724-4779-aa3f-15043b8bece4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305548499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2305548499
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3567282346
Short name T63
Test name
Test status
Simulation time 519609720 ps
CPU time 3.07 seconds
Started May 28 01:39:02 PM PDT 24
Finished May 28 01:39:11 PM PDT 24
Peak memory 200484 kb
Host smart-405159af-579e-4fe6-992c-45efaa006d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567282346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3567282346
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2953574902
Short name T141
Test name
Test status
Simulation time 239824583 ps
CPU time 1.39 seconds
Started May 28 01:38:48 PM PDT 24
Finished May 28 01:38:53 PM PDT 24
Peak memory 200644 kb
Host smart-b1b43524-d2cf-4bcf-8112-1b301bf3e02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953574902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2953574902
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.1717557139
Short name T396
Test name
Test status
Simulation time 71204791 ps
CPU time 0.8 seconds
Started May 28 01:38:58 PM PDT 24
Finished May 28 01:39:02 PM PDT 24
Peak memory 200332 kb
Host smart-d08d51a6-6495-41ea-a174-78a3021fdb36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717557139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1717557139
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.4091678766
Short name T483
Test name
Test status
Simulation time 1890421448 ps
CPU time 8.15 seconds
Started May 28 01:39:00 PM PDT 24
Finished May 28 01:39:14 PM PDT 24
Peak memory 222168 kb
Host smart-2963679f-b73b-42e9-9a9f-9e37bd6be5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091678766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.4091678766
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.4066842424
Short name T383
Test name
Test status
Simulation time 243870923 ps
CPU time 1.09 seconds
Started May 28 01:38:57 PM PDT 24
Finished May 28 01:39:00 PM PDT 24
Peak memory 217764 kb
Host smart-2f69f558-2434-448c-ada9-81b1cb9039fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066842424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.4066842424
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.1527211567
Short name T275
Test name
Test status
Simulation time 143824177 ps
CPU time 0.9 seconds
Started May 28 01:39:01 PM PDT 24
Finished May 28 01:39:07 PM PDT 24
Peak memory 200288 kb
Host smart-140ddca1-90c6-4a73-a89b-734478a88115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527211567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1527211567
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2160042141
Short name T230
Test name
Test status
Simulation time 880990873 ps
CPU time 4.15 seconds
Started May 28 01:38:57 PM PDT 24
Finished May 28 01:39:03 PM PDT 24
Peak memory 200640 kb
Host smart-be266d21-2fa1-46f3-afa5-3dcb9f2e6d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160042141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2160042141
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.664121076
Short name T229
Test name
Test status
Simulation time 95359629 ps
CPU time 0.98 seconds
Started May 28 01:38:58 PM PDT 24
Finished May 28 01:39:01 PM PDT 24
Peak memory 200436 kb
Host smart-2cc46b4b-541e-4b10-a352-dd5efb288d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664121076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.664121076
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.2654034945
Short name T173
Test name
Test status
Simulation time 109450844 ps
CPU time 1.23 seconds
Started May 28 01:39:02 PM PDT 24
Finished May 28 01:39:09 PM PDT 24
Peak memory 200644 kb
Host smart-c852574f-5c75-4e07-9553-318e2d3e17c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654034945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2654034945
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.940191967
Short name T116
Test name
Test status
Simulation time 1603626992 ps
CPU time 6.27 seconds
Started May 28 01:38:58 PM PDT 24
Finished May 28 01:39:07 PM PDT 24
Peak memory 200704 kb
Host smart-c981ccc4-e25b-4365-b639-d18f26f3ab76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940191967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.940191967
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3515952445
Short name T441
Test name
Test status
Simulation time 140700727 ps
CPU time 1.96 seconds
Started May 28 01:39:03 PM PDT 24
Finished May 28 01:39:11 PM PDT 24
Peak memory 200488 kb
Host smart-34a0b51e-5d69-485d-b260-7c83262cfae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515952445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3515952445
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.3497073515
Short name T293
Test name
Test status
Simulation time 180120113 ps
CPU time 1.21 seconds
Started May 28 01:38:57 PM PDT 24
Finished May 28 01:39:00 PM PDT 24
Peak memory 200488 kb
Host smart-c463386a-2b5e-4a6d-b47a-0ef0ad4e8539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497073515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.3497073515
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3505429990
Short name T289
Test name
Test status
Simulation time 60789029 ps
CPU time 0.79 seconds
Started May 28 01:39:02 PM PDT 24
Finished May 28 01:39:09 PM PDT 24
Peak memory 200352 kb
Host smart-6a9dccb0-4af6-42af-be92-6866a3349e25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505429990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3505429990
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.33040960
Short name T517
Test name
Test status
Simulation time 1890543130 ps
CPU time 7.24 seconds
Started May 28 01:39:01 PM PDT 24
Finished May 28 01:39:14 PM PDT 24
Peak memory 217964 kb
Host smart-d0ae0a61-68fc-4112-b160-48429e828400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33040960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.33040960
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.4143515936
Short name T147
Test name
Test status
Simulation time 245023301 ps
CPU time 1.03 seconds
Started May 28 01:38:59 PM PDT 24
Finished May 28 01:39:03 PM PDT 24
Peak memory 217600 kb
Host smart-821ece25-8cf8-4680-b90c-019bb3928e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143515936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.4143515936
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3812760451
Short name T82
Test name
Test status
Simulation time 126817746 ps
CPU time 0.83 seconds
Started May 28 01:38:59 PM PDT 24
Finished May 28 01:39:04 PM PDT 24
Peak memory 200288 kb
Host smart-95eddffe-c858-4e22-b0c8-768efac9eb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812760451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3812760451
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1699518960
Short name T431
Test name
Test status
Simulation time 1821748404 ps
CPU time 7.37 seconds
Started May 28 01:39:00 PM PDT 24
Finished May 28 01:39:12 PM PDT 24
Peak memory 200668 kb
Host smart-29131356-c9ba-48ef-a502-660fc7aa4e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699518960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1699518960
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3578512700
Short name T227
Test name
Test status
Simulation time 108357840 ps
CPU time 0.97 seconds
Started May 28 01:39:00 PM PDT 24
Finished May 28 01:39:07 PM PDT 24
Peak memory 200472 kb
Host smart-3eda4f16-23c8-42f9-b39c-9ea43e20a1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578512700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3578512700
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2595759407
Short name T424
Test name
Test status
Simulation time 192862219 ps
CPU time 1.53 seconds
Started May 28 01:39:00 PM PDT 24
Finished May 28 01:39:08 PM PDT 24
Peak memory 200680 kb
Host smart-50295d1e-ded1-4c0f-99f3-6990682206a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595759407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2595759407
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.854064063
Short name T109
Test name
Test status
Simulation time 17998919163 ps
CPU time 69 seconds
Started May 28 01:39:00 PM PDT 24
Finished May 28 01:40:15 PM PDT 24
Peak memory 209064 kb
Host smart-90d76190-11e6-4b94-8fc9-0b09a58a687a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854064063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.854064063
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2077403800
Short name T482
Test name
Test status
Simulation time 131155592 ps
CPU time 1.55 seconds
Started May 28 01:38:59 PM PDT 24
Finished May 28 01:39:05 PM PDT 24
Peak memory 208720 kb
Host smart-e443e394-cafe-425d-a584-251ef0201981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077403800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2077403800
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1502552495
Short name T274
Test name
Test status
Simulation time 108662197 ps
CPU time 0.95 seconds
Started May 28 01:38:59 PM PDT 24
Finished May 28 01:39:04 PM PDT 24
Peak memory 200484 kb
Host smart-aa4ad609-56a5-4d2b-afff-5f8a2de6f854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502552495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1502552495
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3206067967
Short name T422
Test name
Test status
Simulation time 78985705 ps
CPU time 0.81 seconds
Started May 28 01:39:00 PM PDT 24
Finished May 28 01:39:05 PM PDT 24
Peak memory 200308 kb
Host smart-33cd30f5-d982-4027-b57d-176332c9f4e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206067967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3206067967
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2545367147
Short name T242
Test name
Test status
Simulation time 244862485 ps
CPU time 1.07 seconds
Started May 28 01:39:00 PM PDT 24
Finished May 28 01:39:07 PM PDT 24
Peak memory 217596 kb
Host smart-2655cf02-8bce-4a1f-b057-90718cb2e9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545367147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2545367147
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2531513810
Short name T233
Test name
Test status
Simulation time 199864397 ps
CPU time 0.88 seconds
Started May 28 01:38:57 PM PDT 24
Finished May 28 01:38:59 PM PDT 24
Peak memory 200308 kb
Host smart-0232e625-edb8-4f70-8f19-8ad75e3a50be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531513810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2531513810
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.2637732713
Short name T357
Test name
Test status
Simulation time 1387967519 ps
CPU time 5.94 seconds
Started May 28 01:38:58 PM PDT 24
Finished May 28 01:39:06 PM PDT 24
Peak memory 200684 kb
Host smart-11fc866c-95b8-42a2-a01e-4b2fece7f220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637732713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2637732713
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.4197458463
Short name T8
Test name
Test status
Simulation time 180194909 ps
CPU time 1.19 seconds
Started May 28 01:39:02 PM PDT 24
Finished May 28 01:39:09 PM PDT 24
Peak memory 200536 kb
Host smart-2078e07a-b9f2-408a-91d7-7b42d842d15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197458463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.4197458463
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3880698534
Short name T60
Test name
Test status
Simulation time 258791177 ps
CPU time 1.54 seconds
Started May 28 01:39:01 PM PDT 24
Finished May 28 01:39:09 PM PDT 24
Peak memory 200580 kb
Host smart-76898103-5aa5-4c84-b975-b3b638f1a22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880698534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3880698534
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1428687148
Short name T80
Test name
Test status
Simulation time 14038559726 ps
CPU time 47.19 seconds
Started May 28 01:39:00 PM PDT 24
Finished May 28 01:39:53 PM PDT 24
Peak memory 209028 kb
Host smart-d6643a7a-fb32-4b3e-aec7-95029f68cb09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428687148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1428687148
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.399899333
Short name T318
Test name
Test status
Simulation time 153033203 ps
CPU time 1.95 seconds
Started May 28 01:39:01 PM PDT 24
Finished May 28 01:39:09 PM PDT 24
Peak memory 200500 kb
Host smart-a686646e-6645-4de7-a9b6-e92da821b8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399899333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.399899333
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2107358927
Short name T191
Test name
Test status
Simulation time 151909218 ps
CPU time 1.23 seconds
Started May 28 01:38:57 PM PDT 24
Finished May 28 01:39:00 PM PDT 24
Peak memory 200684 kb
Host smart-3452bbc5-e9e9-4a0a-8407-d836534fb493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107358927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2107358927
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.421096978
Short name T459
Test name
Test status
Simulation time 61872471 ps
CPU time 0.77 seconds
Started May 28 01:39:01 PM PDT 24
Finished May 28 01:39:08 PM PDT 24
Peak memory 200308 kb
Host smart-619436e7-81fc-4273-96ca-9a161806a14a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421096978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.421096978
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.4030916012
Short name T512
Test name
Test status
Simulation time 1912167257 ps
CPU time 7.41 seconds
Started May 28 01:39:00 PM PDT 24
Finished May 28 01:39:12 PM PDT 24
Peak memory 218080 kb
Host smart-e79db095-ba48-474e-b2a7-8563b3a53b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030916012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.4030916012
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.4154294165
Short name T186
Test name
Test status
Simulation time 243658163 ps
CPU time 1.17 seconds
Started May 28 01:39:00 PM PDT 24
Finished May 28 01:39:07 PM PDT 24
Peak memory 217596 kb
Host smart-3e8a2e6e-63a8-4bcf-aeeb-484ad48d6433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154294165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.4154294165
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.123096581
Short name T267
Test name
Test status
Simulation time 165373739 ps
CPU time 0.88 seconds
Started May 28 01:38:58 PM PDT 24
Finished May 28 01:39:02 PM PDT 24
Peak memory 200288 kb
Host smart-f817a764-5c3f-4089-bac5-86075e45b0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123096581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.123096581
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.452003818
Short name T521
Test name
Test status
Simulation time 964288902 ps
CPU time 5.51 seconds
Started May 28 01:38:59 PM PDT 24
Finished May 28 01:39:09 PM PDT 24
Peak memory 200660 kb
Host smart-d1649e1e-de00-4f9b-873e-a8fcd6f4a3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452003818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.452003818
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1246122585
Short name T386
Test name
Test status
Simulation time 102483466 ps
CPU time 1 seconds
Started May 28 01:39:00 PM PDT 24
Finished May 28 01:39:07 PM PDT 24
Peak memory 200496 kb
Host smart-3bfcbc8c-c2c2-48dd-970c-2847b4c6a5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246122585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1246122585
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3095563112
Short name T339
Test name
Test status
Simulation time 194207146 ps
CPU time 1.4 seconds
Started May 28 01:38:59 PM PDT 24
Finished May 28 01:39:05 PM PDT 24
Peak memory 200712 kb
Host smart-fe38cbfe-2188-4846-8ee2-ec21e47cc1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095563112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3095563112
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1435878633
Short name T527
Test name
Test status
Simulation time 7898089393 ps
CPU time 36.75 seconds
Started May 28 01:39:00 PM PDT 24
Finished May 28 01:39:43 PM PDT 24
Peak memory 200828 kb
Host smart-5b9fa07a-e486-4aa5-89a8-3ee5910271db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435878633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1435878633
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2030196588
Short name T179
Test name
Test status
Simulation time 128535031 ps
CPU time 1.68 seconds
Started May 28 01:39:03 PM PDT 24
Finished May 28 01:39:11 PM PDT 24
Peak memory 200488 kb
Host smart-3eed2c21-b8d7-41e7-93e6-bbd688d2327e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030196588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2030196588
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3364276866
Short name T2
Test name
Test status
Simulation time 164189199 ps
CPU time 1.1 seconds
Started May 28 01:39:03 PM PDT 24
Finished May 28 01:39:10 PM PDT 24
Peak memory 200488 kb
Host smart-d7949934-5b66-420f-b3e5-9540b188d329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364276866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3364276866
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3541909427
Short name T171
Test name
Test status
Simulation time 81326118 ps
CPU time 0.83 seconds
Started May 28 01:37:21 PM PDT 24
Finished May 28 01:37:25 PM PDT 24
Peak memory 200308 kb
Host smart-6a5644da-e188-451b-b2ea-5e2ca109593f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541909427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3541909427
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2474855259
Short name T31
Test name
Test status
Simulation time 1900208877 ps
CPU time 7.53 seconds
Started May 28 01:37:23 PM PDT 24
Finished May 28 01:37:33 PM PDT 24
Peak memory 222040 kb
Host smart-4ec8aefe-0ebe-4b0f-8e15-9b568cea1cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474855259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2474855259
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1760630375
Short name T205
Test name
Test status
Simulation time 243907641 ps
CPU time 1.16 seconds
Started May 28 01:37:22 PM PDT 24
Finished May 28 01:37:27 PM PDT 24
Peak memory 217460 kb
Host smart-3381ceed-81d6-41fb-9e0f-21595ed1cc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760630375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1760630375
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.971494755
Short name T476
Test name
Test status
Simulation time 108068689 ps
CPU time 0.78 seconds
Started May 28 01:37:21 PM PDT 24
Finished May 28 01:37:24 PM PDT 24
Peak memory 200280 kb
Host smart-587417e4-db67-4d80-806f-412aa634e4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971494755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.971494755
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2656253888
Short name T523
Test name
Test status
Simulation time 1492966383 ps
CPU time 6.02 seconds
Started May 28 01:37:20 PM PDT 24
Finished May 28 01:37:28 PM PDT 24
Peak memory 200680 kb
Host smart-3a989aed-e99d-4943-93d8-e2479438e262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656253888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2656253888
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2497454286
Short name T238
Test name
Test status
Simulation time 146451093 ps
CPU time 1.13 seconds
Started May 28 01:37:24 PM PDT 24
Finished May 28 01:37:29 PM PDT 24
Peak memory 200416 kb
Host smart-d35620e1-fe23-49b1-a756-b3db50dc0231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497454286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2497454286
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.668090823
Short name T193
Test name
Test status
Simulation time 253163125 ps
CPU time 1.51 seconds
Started May 28 01:37:19 PM PDT 24
Finished May 28 01:37:22 PM PDT 24
Peak memory 200624 kb
Host smart-caaf99d3-2507-4d9a-81a5-a65450ba3903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668090823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.668090823
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1901088013
Short name T285
Test name
Test status
Simulation time 5761071682 ps
CPU time 20.58 seconds
Started May 28 01:37:22 PM PDT 24
Finished May 28 01:37:46 PM PDT 24
Peak memory 208980 kb
Host smart-26c8c6bd-2e85-4aba-95dd-9e54305055b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901088013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1901088013
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1751645740
Short name T236
Test name
Test status
Simulation time 133023989 ps
CPU time 1.78 seconds
Started May 28 01:37:19 PM PDT 24
Finished May 28 01:37:23 PM PDT 24
Peak memory 208688 kb
Host smart-08bf7e87-a2b7-445d-8ec6-7be2af120bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751645740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1751645740
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2721334152
Short name T76
Test name
Test status
Simulation time 112570334 ps
CPU time 0.99 seconds
Started May 28 01:37:20 PM PDT 24
Finished May 28 01:37:22 PM PDT 24
Peak memory 200508 kb
Host smart-71ae65b3-8407-42e7-aa84-6cb88e20e752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721334152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2721334152
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.4145458741
Short name T475
Test name
Test status
Simulation time 64622185 ps
CPU time 0.79 seconds
Started May 28 01:37:21 PM PDT 24
Finished May 28 01:37:25 PM PDT 24
Peak memory 200240 kb
Host smart-31e25295-13a7-4795-b8ec-e41320c4488c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145458741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.4145458741
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3044033891
Short name T508
Test name
Test status
Simulation time 2338709062 ps
CPU time 8.7 seconds
Started May 28 01:37:22 PM PDT 24
Finished May 28 01:37:34 PM PDT 24
Peak memory 218132 kb
Host smart-d5f862ba-9b7c-4d5e-ab46-bd9d9500ea99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044033891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3044033891
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2509650633
Short name T204
Test name
Test status
Simulation time 243731450 ps
CPU time 1.14 seconds
Started May 28 01:37:25 PM PDT 24
Finished May 28 01:37:29 PM PDT 24
Peak memory 217760 kb
Host smart-e56c21ec-5621-4e51-8834-95497911abff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509650633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2509650633
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.923383882
Short name T374
Test name
Test status
Simulation time 210747347 ps
CPU time 0.9 seconds
Started May 28 01:37:21 PM PDT 24
Finished May 28 01:37:25 PM PDT 24
Peak memory 200204 kb
Host smart-33275e82-c1e9-4d91-90b7-02d34bd1896f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923383882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.923383882
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2115513787
Short name T503
Test name
Test status
Simulation time 1191795977 ps
CPU time 4.44 seconds
Started May 28 01:37:20 PM PDT 24
Finished May 28 01:37:26 PM PDT 24
Peak memory 200608 kb
Host smart-0047888b-5665-49a8-b63e-83c9fb5aa741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115513787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2115513787
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2912143927
Short name T87
Test name
Test status
Simulation time 95359143 ps
CPU time 1.08 seconds
Started May 28 01:37:26 PM PDT 24
Finished May 28 01:37:30 PM PDT 24
Peak memory 200428 kb
Host smart-2245574a-731a-464e-9808-c0bc941fec77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912143927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2912143927
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.3536072229
Short name T181
Test name
Test status
Simulation time 112396826 ps
CPU time 1.21 seconds
Started May 28 01:37:24 PM PDT 24
Finished May 28 01:37:29 PM PDT 24
Peak memory 200672 kb
Host smart-86a9d43a-6629-4ffc-92f1-c64fea302558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536072229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3536072229
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1320576299
Short name T400
Test name
Test status
Simulation time 1217755270 ps
CPU time 6.5 seconds
Started May 28 01:37:22 PM PDT 24
Finished May 28 01:37:32 PM PDT 24
Peak memory 200608 kb
Host smart-841d97c5-829a-422f-83e4-e10e4cbaeba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320576299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1320576299
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.3308518612
Short name T83
Test name
Test status
Simulation time 274290574 ps
CPU time 2.14 seconds
Started May 28 01:37:25 PM PDT 24
Finished May 28 01:37:31 PM PDT 24
Peak memory 200400 kb
Host smart-1d8ee734-ce16-41ba-81cb-c3df41c15857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308518612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.3308518612
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.85612355
Short name T354
Test name
Test status
Simulation time 120453216 ps
CPU time 1.01 seconds
Started May 28 01:37:24 PM PDT 24
Finished May 28 01:37:28 PM PDT 24
Peak memory 200460 kb
Host smart-52675ad1-a36c-4108-adf2-11bb1f391102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85612355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.85612355
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1643677982
Short name T451
Test name
Test status
Simulation time 77618602 ps
CPU time 0.78 seconds
Started May 28 01:37:24 PM PDT 24
Finished May 28 01:37:29 PM PDT 24
Peak memory 200324 kb
Host smart-91af00eb-2551-442c-8b14-2074196d69c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643677982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1643677982
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3800386023
Short name T27
Test name
Test status
Simulation time 2175333985 ps
CPU time 7.93 seconds
Started May 28 01:37:23 PM PDT 24
Finished May 28 01:37:35 PM PDT 24
Peak memory 218160 kb
Host smart-d1a5bd5d-5863-491a-8d95-35f062d812d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800386023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3800386023
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1383178105
Short name T157
Test name
Test status
Simulation time 244657667 ps
CPU time 1.09 seconds
Started May 28 01:37:22 PM PDT 24
Finished May 28 01:37:26 PM PDT 24
Peak memory 217676 kb
Host smart-8b4e7582-f365-467e-863f-5be9531785e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383178105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1383178105
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.2607403667
Short name T491
Test name
Test status
Simulation time 105414123 ps
CPU time 0.8 seconds
Started May 28 01:37:24 PM PDT 24
Finished May 28 01:37:28 PM PDT 24
Peak memory 200268 kb
Host smart-7cd7239c-d4bb-4755-aec2-504266cd145b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607403667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2607403667
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3778581254
Short name T501
Test name
Test status
Simulation time 1727257182 ps
CPU time 6.63 seconds
Started May 28 01:37:23 PM PDT 24
Finished May 28 01:37:34 PM PDT 24
Peak memory 200672 kb
Host smart-ea77da01-0bdb-4915-8f2e-c530c49476e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778581254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3778581254
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1845843355
Short name T494
Test name
Test status
Simulation time 103819901 ps
CPU time 1 seconds
Started May 28 01:37:25 PM PDT 24
Finished May 28 01:37:29 PM PDT 24
Peak memory 200504 kb
Host smart-72bfd6e7-b709-4ad7-933a-684b1ffbbe9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845843355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1845843355
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2667819718
Short name T458
Test name
Test status
Simulation time 111690158 ps
CPU time 1.18 seconds
Started May 28 01:37:21 PM PDT 24
Finished May 28 01:37:25 PM PDT 24
Peak memory 200588 kb
Host smart-c47c1237-e0a5-4021-a2d3-2324bffa3e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667819718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2667819718
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3369206330
Short name T112
Test name
Test status
Simulation time 9755479956 ps
CPU time 35.88 seconds
Started May 28 01:37:24 PM PDT 24
Finished May 28 01:38:03 PM PDT 24
Peak memory 209020 kb
Host smart-961dbd20-dfef-44b9-be8a-6498f02b48f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369206330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3369206330
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3695435876
Short name T342
Test name
Test status
Simulation time 338493187 ps
CPU time 2.14 seconds
Started May 28 01:37:22 PM PDT 24
Finished May 28 01:37:27 PM PDT 24
Peak memory 200404 kb
Host smart-841284fa-9db1-4c65-ad33-55d699240772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695435876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3695435876
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.286934472
Short name T11
Test name
Test status
Simulation time 117159615 ps
CPU time 0.9 seconds
Started May 28 01:37:20 PM PDT 24
Finished May 28 01:37:24 PM PDT 24
Peak memory 200400 kb
Host smart-63338c84-6fc5-4229-a8e3-5b88484fcf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286934472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.286934472
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.4052897082
Short name T10
Test name
Test status
Simulation time 83532738 ps
CPU time 0.81 seconds
Started May 28 01:37:24 PM PDT 24
Finished May 28 01:37:28 PM PDT 24
Peak memory 200552 kb
Host smart-8d010a46-cf22-4828-b469-cf71a0a85084
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052897082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.4052897082
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.4142525932
Short name T25
Test name
Test status
Simulation time 2181831471 ps
CPU time 7.65 seconds
Started May 28 01:37:20 PM PDT 24
Finished May 28 01:37:30 PM PDT 24
Peak memory 222304 kb
Host smart-2e724e8d-0085-41f2-8b21-67d9272c64ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142525932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.4142525932
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2716464645
Short name T323
Test name
Test status
Simulation time 244734039 ps
CPU time 1.07 seconds
Started May 28 01:37:20 PM PDT 24
Finished May 28 01:37:23 PM PDT 24
Peak memory 217592 kb
Host smart-f7fd87f1-cfb4-4285-b842-2a8838bd67df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716464645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2716464645
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3677362106
Short name T258
Test name
Test status
Simulation time 203575748 ps
CPU time 0.99 seconds
Started May 28 01:37:21 PM PDT 24
Finished May 28 01:37:25 PM PDT 24
Peak memory 200288 kb
Host smart-040aaeb7-fb29-41f5-8f4f-c7b1eecbd3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677362106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3677362106
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3539497701
Short name T243
Test name
Test status
Simulation time 1098167306 ps
CPU time 5.06 seconds
Started May 28 01:37:21 PM PDT 24
Finished May 28 01:37:29 PM PDT 24
Peak memory 200596 kb
Host smart-a8d03113-01ea-4fa1-b227-5180b516c1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539497701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3539497701
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2849937656
Short name T41
Test name
Test status
Simulation time 150207260 ps
CPU time 1.19 seconds
Started May 28 01:37:23 PM PDT 24
Finished May 28 01:37:28 PM PDT 24
Peak memory 200432 kb
Host smart-79a11104-3706-41da-b703-c091683bbd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849937656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2849937656
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.1125433360
Short name T197
Test name
Test status
Simulation time 225028517 ps
CPU time 1.53 seconds
Started May 28 01:37:24 PM PDT 24
Finished May 28 01:37:29 PM PDT 24
Peak memory 200716 kb
Host smart-cab21789-9dc4-44b0-ab24-570cfe8940ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125433360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1125433360
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.120591930
Short name T245
Test name
Test status
Simulation time 2689095185 ps
CPU time 11.96 seconds
Started May 28 01:37:24 PM PDT 24
Finished May 28 01:37:39 PM PDT 24
Peak memory 209016 kb
Host smart-7ca4cf94-e5b3-49c9-8f8a-cf7af85025a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120591930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.120591930
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.1962910907
Short name T266
Test name
Test status
Simulation time 336917573 ps
CPU time 2.36 seconds
Started May 28 01:37:26 PM PDT 24
Finished May 28 01:37:31 PM PDT 24
Peak memory 200736 kb
Host smart-13ce127e-eaf8-4200-ad3b-6071e07e3131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962910907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1962910907
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.3503383436
Short name T305
Test name
Test status
Simulation time 84032838 ps
CPU time 0.82 seconds
Started May 28 01:37:22 PM PDT 24
Finished May 28 01:37:26 PM PDT 24
Peak memory 200504 kb
Host smart-1018ff92-e965-40ac-b830-36b41d9063f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503383436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3503383436
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3378254064
Short name T159
Test name
Test status
Simulation time 72911970 ps
CPU time 0.79 seconds
Started May 28 01:37:26 PM PDT 24
Finished May 28 01:37:30 PM PDT 24
Peak memory 200312 kb
Host smart-d9858c59-ec60-46c8-8008-571068db24cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378254064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3378254064
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2265098268
Short name T202
Test name
Test status
Simulation time 244526605 ps
CPU time 1.07 seconds
Started May 28 01:37:22 PM PDT 24
Finished May 28 01:37:26 PM PDT 24
Peak memory 217572 kb
Host smart-10c7aa27-2e01-43e3-89a0-c14949bff07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265098268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2265098268
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.276760469
Short name T16
Test name
Test status
Simulation time 166401349 ps
CPU time 1.05 seconds
Started May 28 01:37:23 PM PDT 24
Finished May 28 01:37:28 PM PDT 24
Peak memory 200224 kb
Host smart-ddfded51-b50c-4ebf-97a8-8dcda3458e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276760469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.276760469
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.578072588
Short name T506
Test name
Test status
Simulation time 868248705 ps
CPU time 4.75 seconds
Started May 28 01:37:23 PM PDT 24
Finished May 28 01:37:31 PM PDT 24
Peak memory 200744 kb
Host smart-df523414-f28f-4017-8c62-1dbb74180d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578072588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.578072588
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.3963449057
Short name T319
Test name
Test status
Simulation time 171747475 ps
CPU time 1.14 seconds
Started May 28 01:37:27 PM PDT 24
Finished May 28 01:37:30 PM PDT 24
Peak memory 200488 kb
Host smart-05c995a3-8bbb-4570-bb17-be0cf57923e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963449057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.3963449057
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.373258964
Short name T296
Test name
Test status
Simulation time 120285641 ps
CPU time 1.29 seconds
Started May 28 01:37:26 PM PDT 24
Finished May 28 01:37:30 PM PDT 24
Peak memory 200940 kb
Host smart-31a0be15-b1f3-4b66-a203-8e268c74e01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373258964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.373258964
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1390190376
Short name T435
Test name
Test status
Simulation time 3461515848 ps
CPU time 16.92 seconds
Started May 28 01:37:26 PM PDT 24
Finished May 28 01:37:46 PM PDT 24
Peak memory 200800 kb
Host smart-8615445d-30c0-4c31-9817-d06872a0102c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390190376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1390190376
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3518033821
Short name T387
Test name
Test status
Simulation time 152658477 ps
CPU time 1.85 seconds
Started May 28 01:37:22 PM PDT 24
Finished May 28 01:37:27 PM PDT 24
Peak memory 200476 kb
Host smart-6fafc1c0-ba56-4422-8fa2-2ba6bd3a667e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518033821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3518033821
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3298329242
Short name T189
Test name
Test status
Simulation time 113075503 ps
CPU time 1.09 seconds
Started May 28 01:37:25 PM PDT 24
Finished May 28 01:37:29 PM PDT 24
Peak memory 200416 kb
Host smart-6841962b-d448-4fa9-939f-8e904d46eb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298329242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3298329242
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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