Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8590

1

T2

27

T4

33

T5

16

auto[1]

11568

1

T2

25

T4

29

T5

85

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6119	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6804	1			T1	1		T2	20		T3	1
reset_info_cp[2]	3143	1			T2	7		T4	11		T5	17
reset_info_cp[4]	4146	1			T2	12		T4	15		T5	18
reset_info_cp[8]	104	1			T6	3		T9	1		T21	3
reset_info_cp[16]	108	1			T4	1		T5	1		T6	2
reset_info_cp[32]	121	1			T2	1		T5	1		T11	1
reset_info_cp[64]	125	1			T2	1		T6	3		T11	3
reset_info_cp[128]	108	1			T6	4		T11	1		T21	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3287	1			T2	9		T4	10		T5	16
reset_info_cp[1]	auto[1]	2897	1			T2	10		T4	10		T5	10
reset_info_cp[2]	auto[0]	1009	1			T2	2		T4	4		T6	41
reset_info_cp[2]	auto[1]	2134	1			T2	5		T4	7		T5	17
reset_info_cp[4]	auto[0]	1509	1			T2	9		T4	10		T6	68
reset_info_cp[4]	auto[1]	2637	1			T2	3		T4	5		T5	18
reset_info_cp[8]	auto[0]	37	1			T6	2		T21	2		T75	1
reset_info_cp[8]	auto[1]	67	1			T6	1		T9	1		T21	1
reset_info_cp[16]	auto[0]	43	1			T4	1		T6	1		T21	1
reset_info_cp[16]	auto[1]	65	1			T5	1		T6	1		T21	1
reset_info_cp[32]	auto[0]	40	1			T21	2		T75	1		T79	1
reset_info_cp[32]	auto[1]	81	1			T2	1		T5	1		T11	1
reset_info_cp[64]	auto[0]	43	1			T6	1		T21	1		T42	2
reset_info_cp[64]	auto[1]	82	1			T2	1		T6	2		T11	3
reset_info_cp[128]	auto[0]	45	1			T6	2		T21	1		T40	1
reset_info_cp[128]	auto[1]	63	1			T6	2		T11	1		T21	1