Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
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T536 /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1494171403 May 30 02:22:49 PM PDT 24 May 30 02:22:51 PM PDT 24 161070079 ps
T537 /workspace/coverage/default/10.rstmgr_por_stretcher.1927234040 May 30 02:19:25 PM PDT 24 May 30 02:19:26 PM PDT 24 131868468 ps
T538 /workspace/coverage/default/11.rstmgr_sw_rst.2261048604 May 30 02:19:35 PM PDT 24 May 30 02:19:37 PM PDT 24 122074313 ps
T539 /workspace/coverage/default/9.rstmgr_sw_rst.3454904184 May 30 02:19:20 PM PDT 24 May 30 02:19:23 PM PDT 24 369613095 ps
T540 /workspace/coverage/default/35.rstmgr_reset.989359143 May 30 02:21:51 PM PDT 24 May 30 02:21:59 PM PDT 24 1688380091 ps
T53 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3997426594 May 30 02:36:05 PM PDT 24 May 30 02:36:10 PM PDT 24 453328467 ps
T49 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2174975807 May 30 02:35:37 PM PDT 24 May 30 02:35:39 PM PDT 24 80324052 ps
T50 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1713201101 May 30 02:35:44 PM PDT 24 May 30 02:35:51 PM PDT 24 1009862336 ps
T51 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2792642982 May 30 02:36:05 PM PDT 24 May 30 02:36:09 PM PDT 24 807374423 ps
T107 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2018692179 May 30 02:35:42 PM PDT 24 May 30 02:35:44 PM PDT 24 113831801 ps
T97 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2380897661 May 30 02:35:33 PM PDT 24 May 30 02:35:35 PM PDT 24 61906458 ps
T98 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.4274287631 May 30 02:35:43 PM PDT 24 May 30 02:35:46 PM PDT 24 87867490 ps
T106 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3772985266 May 30 02:35:37 PM PDT 24 May 30 02:35:49 PM PDT 24 2283807667 ps
T54 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3634535730 May 30 02:35:52 PM PDT 24 May 30 02:35:56 PM PDT 24 205500670 ps
T55 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1034640536 May 30 02:35:58 PM PDT 24 May 30 02:36:02 PM PDT 24 144540945 ps
T56 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.59099020 May 30 02:35:53 PM PDT 24 May 30 02:35:57 PM PDT 24 415070353 ps
T81 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.4010771000 May 30 02:36:06 PM PDT 24 May 30 02:36:08 PM PDT 24 117525267 ps
T82 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.206183001 May 30 02:35:50 PM PDT 24 May 30 02:35:52 PM PDT 24 196817276 ps
T83 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.159923450 May 30 02:35:54 PM PDT 24 May 30 02:35:58 PM PDT 24 419033853 ps
T84 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2249124937 May 30 02:35:57 PM PDT 24 May 30 02:36:03 PM PDT 24 982953331 ps
T85 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.736865125 May 30 02:35:56 PM PDT 24 May 30 02:36:01 PM PDT 24 272496767 ps
T541 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3312287 May 30 02:35:54 PM PDT 24 May 30 02:35:57 PM PDT 24 74700064 ps
T89 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2259241860 May 30 02:35:54 PM PDT 24 May 30 02:35:58 PM PDT 24 456910655 ps
T99 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1206139299 May 30 02:35:51 PM PDT 24 May 30 02:35:54 PM PDT 24 129985083 ps
T100 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3865559390 May 30 02:35:53 PM PDT 24 May 30 02:35:56 PM PDT 24 88620770 ps
T86 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2313630051 May 30 02:36:08 PM PDT 24 May 30 02:36:10 PM PDT 24 122490099 ps
T101 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3868563472 May 30 02:36:00 PM PDT 24 May 30 02:36:04 PM PDT 24 78995288 ps
T109 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2449932222 May 30 02:35:35 PM PDT 24 May 30 02:35:39 PM PDT 24 1020034855 ps
T87 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2496998986 May 30 02:35:53 PM PDT 24 May 30 02:35:56 PM PDT 24 180196973 ps
T102 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3838920466 May 30 02:35:44 PM PDT 24 May 30 02:35:47 PM PDT 24 87197986 ps
T542 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2151298972 May 30 02:35:35 PM PDT 24 May 30 02:35:38 PM PDT 24 155783622 ps
T88 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2569959004 May 30 02:35:43 PM PDT 24 May 30 02:35:47 PM PDT 24 296079188 ps
T543 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.55850841 May 30 02:35:53 PM PDT 24 May 30 02:35:57 PM PDT 24 473245135 ps
T103 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3390139330 May 30 02:35:51 PM PDT 24 May 30 02:35:53 PM PDT 24 56985844 ps
T108 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1830519865 May 30 02:35:55 PM PDT 24 May 30 02:36:02 PM PDT 24 439443561 ps
T544 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2902582006 May 30 02:35:39 PM PDT 24 May 30 02:35:41 PM PDT 24 85152323 ps
T104 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4020651464 May 30 02:35:32 PM PDT 24 May 30 02:35:35 PM PDT 24 132158275 ps
T110 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.4190538840 May 30 02:35:53 PM PDT 24 May 30 02:35:58 PM PDT 24 931122062 ps
T545 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2302373572 May 30 02:35:56 PM PDT 24 May 30 02:36:02 PM PDT 24 364366180 ps
T111 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.722457801 May 30 02:35:44 PM PDT 24 May 30 02:35:48 PM PDT 24 775364851 ps
T105 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.772982764 May 30 02:35:52 PM PDT 24 May 30 02:35:54 PM PDT 24 118188615 ps
T113 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2932907495 May 30 02:35:56 PM PDT 24 May 30 02:36:03 PM PDT 24 874659434 ps
T546 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4121961910 May 30 02:35:39 PM PDT 24 May 30 02:35:45 PM PDT 24 823948785 ps
T547 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3229977997 May 30 02:35:36 PM PDT 24 May 30 02:35:37 PM PDT 24 67442898 ps
T548 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.4289191788 May 30 02:35:33 PM PDT 24 May 30 02:35:44 PM PDT 24 1988047691 ps
T549 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2319882189 May 30 02:35:33 PM PDT 24 May 30 02:35:38 PM PDT 24 898114894 ps
T550 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.4005300940 May 30 02:35:41 PM PDT 24 May 30 02:35:46 PM PDT 24 526494818 ps
T551 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.770720121 May 30 02:36:00 PM PDT 24 May 30 02:36:04 PM PDT 24 233203643 ps
T552 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3728470459 May 30 02:35:57 PM PDT 24 May 30 02:36:02 PM PDT 24 197315707 ps
T553 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3238352064 May 30 02:36:00 PM PDT 24 May 30 02:36:03 PM PDT 24 126156708 ps
T554 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1388288389 May 30 02:35:53 PM PDT 24 May 30 02:35:56 PM PDT 24 69232973 ps
T117 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1702886058 May 30 02:35:56 PM PDT 24 May 30 02:36:01 PM PDT 24 418279688 ps
T555 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.715833654 May 30 02:35:43 PM PDT 24 May 30 02:35:46 PM PDT 24 425992079 ps
T556 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1242045946 May 30 02:35:54 PM PDT 24 May 30 02:35:57 PM PDT 24 76328700 ps
T557 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.20249323 May 30 02:35:55 PM PDT 24 May 30 02:35:59 PM PDT 24 183119164 ps
T558 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1362589389 May 30 02:36:12 PM PDT 24 May 30 02:36:16 PM PDT 24 73898358 ps
T559 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1378368705 May 30 02:36:05 PM PDT 24 May 30 02:36:07 PM PDT 24 128280344 ps
T560 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2774699123 May 30 02:35:49 PM PDT 24 May 30 02:35:51 PM PDT 24 137651022 ps
T561 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2841446097 May 30 02:35:40 PM PDT 24 May 30 02:35:44 PM PDT 24 425959050 ps
T562 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3069045438 May 30 02:35:53 PM PDT 24 May 30 02:35:56 PM PDT 24 143440258 ps
T563 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2904285375 May 30 02:35:45 PM PDT 24 May 30 02:35:48 PM PDT 24 137703538 ps
T564 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1043653643 May 30 02:35:35 PM PDT 24 May 30 02:35:37 PM PDT 24 111649266 ps
T565 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2373526579 May 30 02:35:53 PM PDT 24 May 30 02:35:56 PM PDT 24 165451843 ps
T566 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2983479977 May 30 02:35:52 PM PDT 24 May 30 02:35:54 PM PDT 24 72496059 ps
T567 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2808875921 May 30 02:35:49 PM PDT 24 May 30 02:35:51 PM PDT 24 204955541 ps
T568 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2420971166 May 30 02:35:51 PM PDT 24 May 30 02:35:53 PM PDT 24 87155246 ps
T569 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2831920689 May 30 02:35:57 PM PDT 24 May 30 02:36:03 PM PDT 24 866619609 ps
T570 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2696671536 May 30 02:35:57 PM PDT 24 May 30 02:36:01 PM PDT 24 248694585 ps
T571 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1407345158 May 30 02:36:06 PM PDT 24 May 30 02:36:10 PM PDT 24 579530295 ps
T572 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1815146383 May 30 02:35:43 PM PDT 24 May 30 02:35:46 PM PDT 24 71578234 ps
T573 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2475726954 May 30 02:36:07 PM PDT 24 May 30 02:36:09 PM PDT 24 74150545 ps
T574 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1444027036 May 30 02:35:52 PM PDT 24 May 30 02:35:55 PM PDT 24 65290184 ps
T575 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.566927728 May 30 02:35:42 PM PDT 24 May 30 02:35:45 PM PDT 24 139829582 ps
T112 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.4134339634 May 30 02:35:44 PM PDT 24 May 30 02:35:48 PM PDT 24 792368770 ps
T576 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.735621816 May 30 02:35:55 PM PDT 24 May 30 02:36:00 PM PDT 24 142323682 ps
T577 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3573888868 May 30 02:35:50 PM PDT 24 May 30 02:35:53 PM PDT 24 240703519 ps
T578 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3863898464 May 30 02:35:54 PM PDT 24 May 30 02:35:58 PM PDT 24 58329878 ps
T579 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2207598547 May 30 02:36:08 PM PDT 24 May 30 02:36:10 PM PDT 24 125535043 ps
T580 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.37076941 May 30 02:35:35 PM PDT 24 May 30 02:35:37 PM PDT 24 96355376 ps
T581 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1375449655 May 30 02:35:44 PM PDT 24 May 30 02:35:51 PM PDT 24 480617015 ps
T582 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.4037945082 May 30 02:35:49 PM PDT 24 May 30 02:35:50 PM PDT 24 84032646 ps
T583 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.927406601 May 30 02:35:32 PM PDT 24 May 30 02:35:35 PM PDT 24 183316626 ps
T584 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.665821072 May 30 02:35:54 PM PDT 24 May 30 02:35:57 PM PDT 24 92911105 ps
T585 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3599897366 May 30 02:35:58 PM PDT 24 May 30 02:36:02 PM PDT 24 64696333 ps
T586 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3427079298 May 30 02:35:53 PM PDT 24 May 30 02:35:57 PM PDT 24 206161655 ps
T587 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1961860642 May 30 02:35:42 PM PDT 24 May 30 02:35:45 PM PDT 24 425955110 ps
T588 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.4278590051 May 30 02:35:53 PM PDT 24 May 30 02:35:56 PM PDT 24 64788119 ps
T589 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.540790153 May 30 02:35:44 PM PDT 24 May 30 02:35:48 PM PDT 24 157992157 ps
T590 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2869743347 May 30 02:36:09 PM PDT 24 May 30 02:36:14 PM PDT 24 381448354 ps
T591 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2522055077 May 30 02:35:42 PM PDT 24 May 30 02:35:45 PM PDT 24 433326520 ps
T592 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.902175590 May 30 02:36:07 PM PDT 24 May 30 02:36:09 PM PDT 24 94995412 ps
T593 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1763806904 May 30 02:35:55 PM PDT 24 May 30 02:36:01 PM PDT 24 460917521 ps
T594 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2024979961 May 30 02:35:54 PM PDT 24 May 30 02:36:01 PM PDT 24 600169276 ps
T595 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.361576206 May 30 02:36:02 PM PDT 24 May 30 02:36:07 PM PDT 24 207277096 ps
T596 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3079955401 May 30 02:35:54 PM PDT 24 May 30 02:35:57 PM PDT 24 65814093 ps
T597 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2931059590 May 30 02:35:35 PM PDT 24 May 30 02:35:38 PM PDT 24 360373731 ps
T598 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2728347971 May 30 02:36:00 PM PDT 24 May 30 02:36:04 PM PDT 24 136107319 ps
T599 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.4177871222 May 30 02:35:37 PM PDT 24 May 30 02:35:39 PM PDT 24 134289595 ps
T600 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2114546917 May 30 02:35:38 PM PDT 24 May 30 02:35:40 PM PDT 24 188730707 ps
T601 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3653875580 May 30 02:35:44 PM PDT 24 May 30 02:35:46 PM PDT 24 105570068 ps
T602 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.291122606 May 30 02:35:31 PM PDT 24 May 30 02:35:35 PM PDT 24 134565833 ps
T603 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.4115626568 May 30 02:35:55 PM PDT 24 May 30 02:36:00 PM PDT 24 131700879 ps
T604 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3478020840 May 30 02:35:34 PM PDT 24 May 30 02:35:39 PM PDT 24 431860817 ps
T605 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1376674851 May 30 02:35:32 PM PDT 24 May 30 02:35:35 PM PDT 24 79661887 ps
T606 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1094625519 May 30 02:35:40 PM PDT 24 May 30 02:35:43 PM PDT 24 154243453 ps
T607 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2541301809 May 30 02:35:45 PM PDT 24 May 30 02:35:48 PM PDT 24 150233938 ps
T608 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.869099155 May 30 02:35:54 PM PDT 24 May 30 02:35:57 PM PDT 24 69399415 ps
T114 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3883084044 May 30 02:35:58 PM PDT 24 May 30 02:36:03 PM PDT 24 497525305 ps
T609 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3726763418 May 30 02:35:55 PM PDT 24 May 30 02:35:59 PM PDT 24 134484026 ps
T610 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1038928347 May 30 02:35:41 PM PDT 24 May 30 02:35:43 PM PDT 24 117939013 ps
T611 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2879691183 May 30 02:35:53 PM PDT 24 May 30 02:35:57 PM PDT 24 143949838 ps
T612 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3379353625 May 30 02:35:56 PM PDT 24 May 30 02:36:00 PM PDT 24 133997011 ps
T613 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4239695236 May 30 02:35:43 PM PDT 24 May 30 02:35:45 PM PDT 24 105451065 ps
T614 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.640453323 May 30 02:35:35 PM PDT 24 May 30 02:35:37 PM PDT 24 210783400 ps
T615 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.23816313 May 30 02:35:43 PM PDT 24 May 30 02:35:47 PM PDT 24 296032355 ps
T616 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1032556467 May 30 02:35:42 PM PDT 24 May 30 02:35:44 PM PDT 24 111567020 ps
T617 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1838021544 May 30 02:35:56 PM PDT 24 May 30 02:36:00 PM PDT 24 185649832 ps
T618 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3374298694 May 30 02:35:44 PM PDT 24 May 30 02:35:47 PM PDT 24 200491674 ps
T619 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1652225093 May 30 02:35:51 PM PDT 24 May 30 02:35:55 PM PDT 24 943961489 ps
T620 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.4246025412 May 30 02:36:00 PM PDT 24 May 30 02:36:03 PM PDT 24 59646692 ps

Test location /workspace/coverage/default/32.rstmgr_stress_all.4242482509
Short name T6
Test name
Test status
Simulation time 16027028928 ps
CPU time 57.06 seconds
Started May 30 02:21:45 PM PDT 24
Finished May 30 02:22:43 PM PDT 24
Peak memory 209384 kb
Host smart-d292ba85-35b2-4bbb-bde2-e4a812174b5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242482509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.4242482509
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1643709162
Short name T80
Test name
Test status
Simulation time 141957979 ps
CPU time 1.86 seconds
Started May 30 02:20:49 PM PDT 24
Finished May 30 02:20:52 PM PDT 24
Peak memory 200912 kb
Host smart-5860b14a-7cab-4aeb-aec9-7599ecb8a220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643709162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1643709162
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2792642982
Short name T51
Test name
Test status
Simulation time 807374423 ps
CPU time 2.88 seconds
Started May 30 02:36:05 PM PDT 24
Finished May 30 02:36:09 PM PDT 24
Peak memory 200604 kb
Host smart-7bec3833-a214-443a-b383-bf5d95231fbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792642982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2792642982
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2136833669
Short name T59
Test name
Test status
Simulation time 8283599057 ps
CPU time 14.34 seconds
Started May 30 02:18:24 PM PDT 24
Finished May 30 02:18:40 PM PDT 24
Peak memory 218044 kb
Host smart-a2d87058-b310-45c4-88b1-95ca941bddb1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136833669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2136833669
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.390307886
Short name T22
Test name
Test status
Simulation time 2179873485 ps
CPU time 8.13 seconds
Started May 30 02:23:17 PM PDT 24
Finished May 30 02:23:25 PM PDT 24
Peak memory 218656 kb
Host smart-79cec5ca-7fe8-45cd-8c85-90d418ec7ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390307886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.390307886
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3997426594
Short name T53
Test name
Test status
Simulation time 453328467 ps
CPU time 3.73 seconds
Started May 30 02:36:05 PM PDT 24
Finished May 30 02:36:10 PM PDT 24
Peak memory 208784 kb
Host smart-bff13160-cc6e-48d2-8933-1c5b6990eb38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997426594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3997426594
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3960183900
Short name T124
Test name
Test status
Simulation time 64456458 ps
CPU time 0.79 seconds
Started May 30 02:20:48 PM PDT 24
Finished May 30 02:20:50 PM PDT 24
Peak memory 200788 kb
Host smart-b7b6a504-4a7c-44a3-bb40-eb8a88f340a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960183900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3960183900
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.4159770426
Short name T118
Test name
Test status
Simulation time 144666252 ps
CPU time 1.11 seconds
Started May 30 02:18:23 PM PDT 24
Finished May 30 02:18:25 PM PDT 24
Peak memory 200884 kb
Host smart-09b405fc-a65b-492f-9ae8-7e5b17a08d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159770426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.4159770426
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.2413700428
Short name T79
Test name
Test status
Simulation time 11314997474 ps
CPU time 43.08 seconds
Started May 30 02:22:35 PM PDT 24
Finished May 30 02:23:19 PM PDT 24
Peak memory 210172 kb
Host smart-c351be4b-a6bb-47f4-85c8-f06699c091a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413700428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2413700428
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.722457801
Short name T111
Test name
Test status
Simulation time 775364851 ps
CPU time 2.95 seconds
Started May 30 02:35:44 PM PDT 24
Finished May 30 02:35:48 PM PDT 24
Peak memory 200704 kb
Host smart-929b99f0-61fc-485a-a4f4-a26e03296172
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722457801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
722457801
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3971239343
Short name T24
Test name
Test status
Simulation time 2372641308 ps
CPU time 9.02 seconds
Started May 30 02:20:25 PM PDT 24
Finished May 30 02:20:35 PM PDT 24
Peak memory 222724 kb
Host smart-8a9718c7-08b9-4ed0-bf20-fb5abad7b295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971239343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3971239343
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.429597430
Short name T8
Test name
Test status
Simulation time 66159546 ps
CPU time 0.77 seconds
Started May 30 02:18:26 PM PDT 24
Finished May 30 02:18:28 PM PDT 24
Peak memory 200892 kb
Host smart-1a5e2d81-d2b7-41fd-9e1b-bc7229892bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429597430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.429597430
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3845530061
Short name T31
Test name
Test status
Simulation time 1230451545 ps
CPU time 5.7 seconds
Started May 30 02:19:48 PM PDT 24
Finished May 30 02:19:55 PM PDT 24
Peak memory 218456 kb
Host smart-8820fbd0-370d-4ae8-aaef-d97c46870432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845530061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3845530061
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.4005300940
Short name T550
Test name
Test status
Simulation time 526494818 ps
CPU time 3.32 seconds
Started May 30 02:35:41 PM PDT 24
Finished May 30 02:35:46 PM PDT 24
Peak memory 208760 kb
Host smart-0cbfc442-a98a-4fac-8905-0d4bc58256d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005300940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.4005300940
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3883084044
Short name T114
Test name
Test status
Simulation time 497525305 ps
CPU time 1.96 seconds
Started May 30 02:35:58 PM PDT 24
Finished May 30 02:36:03 PM PDT 24
Peak memory 200588 kb
Host smart-52441cdb-4197-454f-9bf7-869216adb7f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883084044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3883084044
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2380897661
Short name T97
Test name
Test status
Simulation time 61906458 ps
CPU time 0.82 seconds
Started May 30 02:35:33 PM PDT 24
Finished May 30 02:35:35 PM PDT 24
Peak memory 200380 kb
Host smart-9826b523-c18f-4a41-910b-3ceb72c92a2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380897661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2380897661
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.847259193
Short name T12
Test name
Test status
Simulation time 139691106 ps
CPU time 0.83 seconds
Started May 30 02:19:36 PM PDT 24
Finished May 30 02:19:37 PM PDT 24
Peak memory 200700 kb
Host smart-bcb1dd23-8130-4640-a32f-363afcb167fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847259193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.847259193
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1845814313
Short name T128
Test name
Test status
Simulation time 243866476 ps
CPU time 1.11 seconds
Started May 30 02:19:49 PM PDT 24
Finished May 30 02:19:51 PM PDT 24
Peak memory 218024 kb
Host smart-e10e162b-53a8-47ce-8ffd-0edc8f34d3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845814313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1845814313
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2931059590
Short name T597
Test name
Test status
Simulation time 360373731 ps
CPU time 2.38 seconds
Started May 30 02:35:35 PM PDT 24
Finished May 30 02:35:38 PM PDT 24
Peak memory 200504 kb
Host smart-47d0153e-cebd-4d3d-99a7-159677c9d421
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931059590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
931059590
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.4289191788
Short name T548
Test name
Test status
Simulation time 1988047691 ps
CPU time 9.17 seconds
Started May 30 02:35:33 PM PDT 24
Finished May 30 02:35:44 PM PDT 24
Peak memory 200556 kb
Host smart-f3263840-09b0-43a3-b986-4153fa5117fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289191788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.4
289191788
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.37076941
Short name T580
Test name
Test status
Simulation time 96355376 ps
CPU time 0.85 seconds
Started May 30 02:35:35 PM PDT 24
Finished May 30 02:35:37 PM PDT 24
Peak memory 200380 kb
Host smart-017721a9-19c8-4a5c-acf8-0aafa5816fd4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37076941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.37076941
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2114546917
Short name T600
Test name
Test status
Simulation time 188730707 ps
CPU time 1.27 seconds
Started May 30 02:35:38 PM PDT 24
Finished May 30 02:35:40 PM PDT 24
Peak memory 208648 kb
Host smart-b364fe53-2038-417c-991c-55cc96abf118
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114546917 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2114546917
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3838920466
Short name T102
Test name
Test status
Simulation time 87197986 ps
CPU time 1.09 seconds
Started May 30 02:35:44 PM PDT 24
Finished May 30 02:35:47 PM PDT 24
Peak memory 200348 kb
Host smart-6a022815-6fa5-4243-b5c9-f69e4550b784
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838920466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3838920466
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2319882189
Short name T549
Test name
Test status
Simulation time 898114894 ps
CPU time 3.05 seconds
Started May 30 02:35:33 PM PDT 24
Finished May 30 02:35:38 PM PDT 24
Peak memory 200596 kb
Host smart-f50ba6f7-2688-4fff-b8e8-412eef51664b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319882189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2319882189
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2151298972
Short name T542
Test name
Test status
Simulation time 155783622 ps
CPU time 1.96 seconds
Started May 30 02:35:35 PM PDT 24
Finished May 30 02:35:38 PM PDT 24
Peak memory 200512 kb
Host smart-f793d7d4-b998-4a8f-a1a5-fa66f5c5e518
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151298972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
151298972
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1375449655
Short name T581
Test name
Test status
Simulation time 480617015 ps
CPU time 5.86 seconds
Started May 30 02:35:44 PM PDT 24
Finished May 30 02:35:51 PM PDT 24
Peak memory 200536 kb
Host smart-5e25043c-a562-4315-b4e1-f81633cf4fcd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375449655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
375449655
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2774699123
Short name T560
Test name
Test status
Simulation time 137651022 ps
CPU time 1.04 seconds
Started May 30 02:35:49 PM PDT 24
Finished May 30 02:35:51 PM PDT 24
Peak memory 200280 kb
Host smart-7d8973dc-e310-4b28-9c79-1cd80acda85b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774699123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
774699123
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2808875921
Short name T567
Test name
Test status
Simulation time 204955541 ps
CPU time 1.49 seconds
Started May 30 02:35:49 PM PDT 24
Finished May 30 02:35:51 PM PDT 24
Peak memory 208600 kb
Host smart-6e62ba23-4741-4802-8c80-7647c1ce045c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808875921 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2808875921
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.4037945082
Short name T582
Test name
Test status
Simulation time 84032646 ps
CPU time 0.88 seconds
Started May 30 02:35:49 PM PDT 24
Finished May 30 02:35:50 PM PDT 24
Peak memory 200216 kb
Host smart-d65ae9cd-c4c3-49c1-9d3c-3e41143cd5ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037945082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.4037945082
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.4177871222
Short name T599
Test name
Test status
Simulation time 134289595 ps
CPU time 1.13 seconds
Started May 30 02:35:37 PM PDT 24
Finished May 30 02:35:39 PM PDT 24
Peak memory 200388 kb
Host smart-6eac14eb-29e6-4215-be56-eaa2dfff29c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177871222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.4177871222
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3478020840
Short name T604
Test name
Test status
Simulation time 431860817 ps
CPU time 3.21 seconds
Started May 30 02:35:34 PM PDT 24
Finished May 30 02:35:39 PM PDT 24
Peak memory 216968 kb
Host smart-63693ce6-3119-40d7-a1c6-a0c191b69664
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478020840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3478020840
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2449932222
Short name T109
Test name
Test status
Simulation time 1020034855 ps
CPU time 3.15 seconds
Started May 30 02:35:35 PM PDT 24
Finished May 30 02:35:39 PM PDT 24
Peak memory 200584 kb
Host smart-f132894b-3845-43fe-91db-aa2e800484e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449932222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.2449932222
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1838021544
Short name T617
Test name
Test status
Simulation time 185649832 ps
CPU time 1.29 seconds
Started May 30 02:35:56 PM PDT 24
Finished May 30 02:36:00 PM PDT 24
Peak memory 208684 kb
Host smart-f7d162c7-0f7b-4f40-9b4a-70f7b222fc80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838021544 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1838021544
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.4278590051
Short name T588
Test name
Test status
Simulation time 64788119 ps
CPU time 0.79 seconds
Started May 30 02:35:53 PM PDT 24
Finished May 30 02:35:56 PM PDT 24
Peak memory 200324 kb
Host smart-7e218f83-1110-4b20-99ae-f9455f51b5aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278590051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.4278590051
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.735621816
Short name T576
Test name
Test status
Simulation time 142323682 ps
CPU time 1.15 seconds
Started May 30 02:35:55 PM PDT 24
Finished May 30 02:36:00 PM PDT 24
Peak memory 200408 kb
Host smart-07f1cbb7-dfed-42df-a1cb-532659da1dfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735621816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.735621816
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3634535730
Short name T54
Test name
Test status
Simulation time 205500670 ps
CPU time 3.09 seconds
Started May 30 02:35:52 PM PDT 24
Finished May 30 02:35:56 PM PDT 24
Peak memory 208840 kb
Host smart-075db095-9cd5-4734-a43f-efc29082d53b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634535730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3634535730
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.20249323
Short name T557
Test name
Test status
Simulation time 183119164 ps
CPU time 1.26 seconds
Started May 30 02:35:55 PM PDT 24
Finished May 30 02:35:59 PM PDT 24
Peak memory 210436 kb
Host smart-d196ea7b-1045-4655-9dcd-48086367e5c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20249323 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.20249323
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3312287
Short name T541
Test name
Test status
Simulation time 74700064 ps
CPU time 0.85 seconds
Started May 30 02:35:54 PM PDT 24
Finished May 30 02:35:57 PM PDT 24
Peak memory 200420 kb
Host smart-023b279a-d1a3-4a7b-baf4-f74e3b100f83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3312287
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2728347971
Short name T598
Test name
Test status
Simulation time 136107319 ps
CPU time 1.16 seconds
Started May 30 02:36:00 PM PDT 24
Finished May 30 02:36:04 PM PDT 24
Peak memory 200344 kb
Host smart-58ffc2a0-e500-4582-9f84-c6fc507c4e4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728347971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2728347971
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3726763418
Short name T609
Test name
Test status
Simulation time 134484026 ps
CPU time 2.01 seconds
Started May 30 02:35:55 PM PDT 24
Finished May 30 02:35:59 PM PDT 24
Peak memory 211216 kb
Host smart-0a4bfd72-66bb-4d9c-bf9e-60e62f7be7c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726763418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3726763418
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1702886058
Short name T117
Test name
Test status
Simulation time 418279688 ps
CPU time 1.88 seconds
Started May 30 02:35:56 PM PDT 24
Finished May 30 02:36:01 PM PDT 24
Peak memory 200664 kb
Host smart-95f69a84-a973-4bcb-b82f-fe295433c263
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702886058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1702886058
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3379353625
Short name T612
Test name
Test status
Simulation time 133997011 ps
CPU time 1.02 seconds
Started May 30 02:35:56 PM PDT 24
Finished May 30 02:36:00 PM PDT 24
Peak memory 200484 kb
Host smart-e35e5c8a-c5d9-4f26-b052-4e8c35105c6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379353625 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3379353625
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3599897366
Short name T585
Test name
Test status
Simulation time 64696333 ps
CPU time 0.78 seconds
Started May 30 02:35:58 PM PDT 24
Finished May 30 02:36:02 PM PDT 24
Peak memory 200284 kb
Host smart-cb770345-8303-4f6c-a06d-cd6a4fd7a7da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599897366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3599897366
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.772982764
Short name T105
Test name
Test status
Simulation time 118188615 ps
CPU time 1.07 seconds
Started May 30 02:35:52 PM PDT 24
Finished May 30 02:35:54 PM PDT 24
Peak memory 200424 kb
Host smart-9c982b81-d8f4-4e62-b700-9700c9e2d2a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772982764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.772982764
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1763806904
Short name T593
Test name
Test status
Simulation time 460917521 ps
CPU time 3.84 seconds
Started May 30 02:35:55 PM PDT 24
Finished May 30 02:36:01 PM PDT 24
Peak memory 216824 kb
Host smart-4d6e65f1-9ed7-4ff6-92bc-0a112be110c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763806904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1763806904
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1652225093
Short name T619
Test name
Test status
Simulation time 943961489 ps
CPU time 3.55 seconds
Started May 30 02:35:51 PM PDT 24
Finished May 30 02:35:55 PM PDT 24
Peak memory 200680 kb
Host smart-14cfc9ab-1b42-4731-aaa3-e553ba595df5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652225093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1652225093
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.206183001
Short name T82
Test name
Test status
Simulation time 196817276 ps
CPU time 1.36 seconds
Started May 30 02:35:50 PM PDT 24
Finished May 30 02:35:52 PM PDT 24
Peak memory 208688 kb
Host smart-42cd73dc-e651-4ff0-8947-a4d39c5a038d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206183001 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.206183001
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.869099155
Short name T608
Test name
Test status
Simulation time 69399415 ps
CPU time 0.8 seconds
Started May 30 02:35:54 PM PDT 24
Finished May 30 02:35:57 PM PDT 24
Peak memory 200376 kb
Host smart-caf5a583-c702-4819-8664-f0e3203b5698
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869099155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.869099155
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2420971166
Short name T568
Test name
Test status
Simulation time 87155246 ps
CPU time 0.98 seconds
Started May 30 02:35:51 PM PDT 24
Finished May 30 02:35:53 PM PDT 24
Peak memory 200408 kb
Host smart-d4b640d9-8f77-4664-ba66-c3422c330084
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420971166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2420971166
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.361576206
Short name T595
Test name
Test status
Simulation time 207277096 ps
CPU time 2.95 seconds
Started May 30 02:36:02 PM PDT 24
Finished May 30 02:36:07 PM PDT 24
Peak memory 211912 kb
Host smart-a2bade55-bcf3-4491-b1fb-8fc6a0e639a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361576206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.361576206
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2932907495
Short name T113
Test name
Test status
Simulation time 874659434 ps
CPU time 3.45 seconds
Started May 30 02:35:56 PM PDT 24
Finished May 30 02:36:03 PM PDT 24
Peak memory 200624 kb
Host smart-962a7d8f-9daa-4e69-87f4-7d4bf92fc45d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932907495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.2932907495
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1034640536
Short name T55
Test name
Test status
Simulation time 144540945 ps
CPU time 1.17 seconds
Started May 30 02:35:58 PM PDT 24
Finished May 30 02:36:02 PM PDT 24
Peak memory 208668 kb
Host smart-76daf7ef-5ff3-4080-b93a-e091aeebc7d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034640536 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.1034640536
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.665821072
Short name T584
Test name
Test status
Simulation time 92911105 ps
CPU time 0.84 seconds
Started May 30 02:35:54 PM PDT 24
Finished May 30 02:35:57 PM PDT 24
Peak memory 200364 kb
Host smart-5168cf27-8980-4e4c-a885-d7db2a1c3cae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665821072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.665821072
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3238352064
Short name T553
Test name
Test status
Simulation time 126156708 ps
CPU time 1.18 seconds
Started May 30 02:36:00 PM PDT 24
Finished May 30 02:36:03 PM PDT 24
Peak memory 200432 kb
Host smart-02e5baac-6c11-4ac4-a015-0a72b6608dc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238352064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3238352064
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1830519865
Short name T108
Test name
Test status
Simulation time 439443561 ps
CPU time 3.31 seconds
Started May 30 02:35:55 PM PDT 24
Finished May 30 02:36:02 PM PDT 24
Peak memory 208788 kb
Host smart-daf0b0e4-8c6e-46fa-8fc3-d02c2408e175
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830519865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1830519865
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.55850841
Short name T543
Test name
Test status
Simulation time 473245135 ps
CPU time 1.93 seconds
Started May 30 02:35:53 PM PDT 24
Finished May 30 02:35:57 PM PDT 24
Peak memory 200608 kb
Host smart-e655e75d-09e7-4c0d-bfac-afb9e0d51f1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55850841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err.55850841
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2373526579
Short name T565
Test name
Test status
Simulation time 165451843 ps
CPU time 1.53 seconds
Started May 30 02:35:53 PM PDT 24
Finished May 30 02:35:56 PM PDT 24
Peak memory 208860 kb
Host smart-9007d0f0-481f-4f66-bd06-3b7caedd0044
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373526579 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2373526579
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3079955401
Short name T596
Test name
Test status
Simulation time 65814093 ps
CPU time 0.77 seconds
Started May 30 02:35:54 PM PDT 24
Finished May 30 02:35:57 PM PDT 24
Peak memory 200356 kb
Host smart-ec62754c-af18-48bf-81bb-15c9adf97dfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079955401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3079955401
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2879691183
Short name T611
Test name
Test status
Simulation time 143949838 ps
CPU time 1.33 seconds
Started May 30 02:35:53 PM PDT 24
Finished May 30 02:35:57 PM PDT 24
Peak memory 200656 kb
Host smart-5adbec1d-948f-44cf-9ccd-e6d18aa89efa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879691183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2879691183
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.770720121
Short name T551
Test name
Test status
Simulation time 233203643 ps
CPU time 1.76 seconds
Started May 30 02:36:00 PM PDT 24
Finished May 30 02:36:04 PM PDT 24
Peak memory 216956 kb
Host smart-e6bf964a-fb8a-4bd9-a498-a83042a3c894
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770720121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.770720121
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.159923450
Short name T83
Test name
Test status
Simulation time 419033853 ps
CPU time 1.77 seconds
Started May 30 02:35:54 PM PDT 24
Finished May 30 02:35:58 PM PDT 24
Peak memory 200692 kb
Host smart-c7edfe47-6615-48e0-9cb7-2cde739e192f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159923450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err
.159923450
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3728470459
Short name T552
Test name
Test status
Simulation time 197315707 ps
CPU time 1.9 seconds
Started May 30 02:35:57 PM PDT 24
Finished May 30 02:36:02 PM PDT 24
Peak memory 208900 kb
Host smart-eee37326-cd04-48a2-8e01-e7d248d5b700
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728470459 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3728470459
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.4246025412
Short name T620
Test name
Test status
Simulation time 59646692 ps
CPU time 0.84 seconds
Started May 30 02:36:00 PM PDT 24
Finished May 30 02:36:03 PM PDT 24
Peak memory 200376 kb
Host smart-fb8a62f1-e6d7-4042-ba06-006ac749d12a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246025412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.4246025412
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3069045438
Short name T562
Test name
Test status
Simulation time 143440258 ps
CPU time 1.18 seconds
Started May 30 02:35:53 PM PDT 24
Finished May 30 02:35:56 PM PDT 24
Peak memory 200412 kb
Host smart-d4099742-6fc2-433a-85b1-810056b004e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069045438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3069045438
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2024979961
Short name T594
Test name
Test status
Simulation time 600169276 ps
CPU time 3.82 seconds
Started May 30 02:35:54 PM PDT 24
Finished May 30 02:36:01 PM PDT 24
Peak memory 208792 kb
Host smart-1cd82a86-18af-4096-aac0-9b82346ac494
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024979961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2024979961
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2259241860
Short name T89
Test name
Test status
Simulation time 456910655 ps
CPU time 1.82 seconds
Started May 30 02:35:54 PM PDT 24
Finished May 30 02:35:58 PM PDT 24
Peak memory 200684 kb
Host smart-8aad4475-b656-4902-b109-7e7d7b1bd3ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259241860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2259241860
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.902175590
Short name T592
Test name
Test status
Simulation time 94995412 ps
CPU time 0.94 seconds
Started May 30 02:36:07 PM PDT 24
Finished May 30 02:36:09 PM PDT 24
Peak memory 200472 kb
Host smart-b583cac9-6acc-4ada-b9ce-b4b2fceb8371
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902175590 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.902175590
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3863898464
Short name T578
Test name
Test status
Simulation time 58329878 ps
CPU time 0.73 seconds
Started May 30 02:35:54 PM PDT 24
Finished May 30 02:35:58 PM PDT 24
Peak memory 200288 kb
Host smart-8bc96306-f19d-4102-958c-ae96bd3775a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863898464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3863898464
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3868563472
Short name T101
Test name
Test status
Simulation time 78995288 ps
CPU time 1.01 seconds
Started May 30 02:36:00 PM PDT 24
Finished May 30 02:36:04 PM PDT 24
Peak memory 200432 kb
Host smart-8759afca-92ec-4d21-901b-4171ae81992d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868563472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.3868563472
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2696671536
Short name T570
Test name
Test status
Simulation time 248694585 ps
CPU time 1.72 seconds
Started May 30 02:35:57 PM PDT 24
Finished May 30 02:36:01 PM PDT 24
Peak memory 208808 kb
Host smart-f97ffea0-fa2c-4d33-94f4-83f584a3279c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696671536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2696671536
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2249124937
Short name T84
Test name
Test status
Simulation time 982953331 ps
CPU time 3.28 seconds
Started May 30 02:35:57 PM PDT 24
Finished May 30 02:36:03 PM PDT 24
Peak memory 200624 kb
Host smart-3d91f09d-b339-405d-b014-b50561620e9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249124937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2249124937
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.4010771000
Short name T81
Test name
Test status
Simulation time 117525267 ps
CPU time 1.36 seconds
Started May 30 02:36:06 PM PDT 24
Finished May 30 02:36:08 PM PDT 24
Peak memory 208708 kb
Host smart-0d1ef52f-be56-4e2a-8141-d556a7a828d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010771000 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.4010771000
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1362589389
Short name T558
Test name
Test status
Simulation time 73898358 ps
CPU time 0.83 seconds
Started May 30 02:36:12 PM PDT 24
Finished May 30 02:36:16 PM PDT 24
Peak memory 200328 kb
Host smart-7b238517-de0e-4d26-bb9f-06c7864bc552
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362589389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1362589389
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1378368705
Short name T559
Test name
Test status
Simulation time 128280344 ps
CPU time 1.36 seconds
Started May 30 02:36:05 PM PDT 24
Finished May 30 02:36:07 PM PDT 24
Peak memory 200604 kb
Host smart-08b99e81-03ce-42c1-a89f-9d54f8644e82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378368705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1378368705
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2869743347
Short name T590
Test name
Test status
Simulation time 381448354 ps
CPU time 3.04 seconds
Started May 30 02:36:09 PM PDT 24
Finished May 30 02:36:14 PM PDT 24
Peak memory 211888 kb
Host smart-8c65d0ca-b472-4ae9-9cbc-880767a8038d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869743347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2869743347
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2313630051
Short name T86
Test name
Test status
Simulation time 122490099 ps
CPU time 1.42 seconds
Started May 30 02:36:08 PM PDT 24
Finished May 30 02:36:10 PM PDT 24
Peak memory 208688 kb
Host smart-85ef7ca7-27d7-41b6-94ec-4c3661420cee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313630051 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2313630051
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2475726954
Short name T573
Test name
Test status
Simulation time 74150545 ps
CPU time 0.91 seconds
Started May 30 02:36:07 PM PDT 24
Finished May 30 02:36:09 PM PDT 24
Peak memory 200372 kb
Host smart-29a806a9-c300-4f81-bcb2-3445e474270e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475726954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2475726954
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2207598547
Short name T579
Test name
Test status
Simulation time 125535043 ps
CPU time 1.11 seconds
Started May 30 02:36:08 PM PDT 24
Finished May 30 02:36:10 PM PDT 24
Peak memory 200424 kb
Host smart-4ff018b8-0c7a-48c3-b454-61f5941ec3d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207598547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.2207598547
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1407345158
Short name T571
Test name
Test status
Simulation time 579530295 ps
CPU time 2.1 seconds
Started May 30 02:36:06 PM PDT 24
Finished May 30 02:36:10 PM PDT 24
Peak memory 200628 kb
Host smart-d36f003f-53ac-417c-ba74-98ae68fea3a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407345158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.1407345158
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1094625519
Short name T606
Test name
Test status
Simulation time 154243453 ps
CPU time 1.95 seconds
Started May 30 02:35:40 PM PDT 24
Finished May 30 02:35:43 PM PDT 24
Peak memory 200508 kb
Host smart-2da540be-4068-420a-8c12-4564203f1fac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094625519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1
094625519
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1713201101
Short name T50
Test name
Test status
Simulation time 1009862336 ps
CPU time 4.95 seconds
Started May 30 02:35:44 PM PDT 24
Finished May 30 02:35:51 PM PDT 24
Peak memory 200544 kb
Host smart-93829a2a-47bf-42f9-9700-42179adfd3b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713201101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
713201101
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3653875580
Short name T601
Test name
Test status
Simulation time 105570068 ps
CPU time 0.88 seconds
Started May 30 02:35:44 PM PDT 24
Finished May 30 02:35:46 PM PDT 24
Peak memory 200344 kb
Host smart-d31dafa5-3156-4399-9fc1-366043fbc31f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653875580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
653875580
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1043653643
Short name T564
Test name
Test status
Simulation time 111649266 ps
CPU time 0.98 seconds
Started May 30 02:35:35 PM PDT 24
Finished May 30 02:35:37 PM PDT 24
Peak memory 200488 kb
Host smart-fabb0903-18de-46a2-b5af-508816d8a17f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043653643 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1043653643
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3229977997
Short name T547
Test name
Test status
Simulation time 67442898 ps
CPU time 0.85 seconds
Started May 30 02:35:36 PM PDT 24
Finished May 30 02:35:37 PM PDT 24
Peak memory 200376 kb
Host smart-912fb87d-6a1f-403d-a996-8c85e6266186
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229977997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3229977997
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2174975807
Short name T49
Test name
Test status
Simulation time 80324052 ps
CPU time 1.01 seconds
Started May 30 02:35:37 PM PDT 24
Finished May 30 02:35:39 PM PDT 24
Peak memory 200388 kb
Host smart-c8b45eea-330b-4c02-82de-9b9856d75b50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174975807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2174975807
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2841446097
Short name T561
Test name
Test status
Simulation time 425959050 ps
CPU time 2.82 seconds
Started May 30 02:35:40 PM PDT 24
Finished May 30 02:35:44 PM PDT 24
Peak memory 208832 kb
Host smart-3eececee-3069-40d8-ba2f-2a5662da53e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841446097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2841446097
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.4134339634
Short name T112
Test name
Test status
Simulation time 792368770 ps
CPU time 2.76 seconds
Started May 30 02:35:44 PM PDT 24
Finished May 30 02:35:48 PM PDT 24
Peak memory 200604 kb
Host smart-c6bebc91-ea57-4f32-9dd5-7de46f6f7f42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134339634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.4134339634
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3374298694
Short name T618
Test name
Test status
Simulation time 200491674 ps
CPU time 1.61 seconds
Started May 30 02:35:44 PM PDT 24
Finished May 30 02:35:47 PM PDT 24
Peak memory 200596 kb
Host smart-195a4850-62ec-4d05-a941-7004b9041494
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374298694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
374298694
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3772985266
Short name T106
Test name
Test status
Simulation time 2283807667 ps
CPU time 11.23 seconds
Started May 30 02:35:37 PM PDT 24
Finished May 30 02:35:49 PM PDT 24
Peak memory 200548 kb
Host smart-1c302e4d-5b09-44cf-b608-67a1249d174f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772985266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3
772985266
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4239695236
Short name T613
Test name
Test status
Simulation time 105451065 ps
CPU time 0.85 seconds
Started May 30 02:35:43 PM PDT 24
Finished May 30 02:35:45 PM PDT 24
Peak memory 200332 kb
Host smart-2ead17a6-fb6b-4093-8a14-5662f3aad9b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239695236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.4
239695236
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2541301809
Short name T607
Test name
Test status
Simulation time 150233938 ps
CPU time 1.18 seconds
Started May 30 02:35:45 PM PDT 24
Finished May 30 02:35:48 PM PDT 24
Peak memory 208600 kb
Host smart-38abbb29-e184-4787-ac73-1c61eaec5794
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541301809 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2541301809
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.4274287631
Short name T98
Test name
Test status
Simulation time 87867490 ps
CPU time 0.93 seconds
Started May 30 02:35:43 PM PDT 24
Finished May 30 02:35:46 PM PDT 24
Peak memory 200388 kb
Host smart-f2457d30-e786-4c07-9508-68bc7293d473
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274287631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.4274287631
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2904285375
Short name T563
Test name
Test status
Simulation time 137703538 ps
CPU time 1.15 seconds
Started May 30 02:35:45 PM PDT 24
Finished May 30 02:35:48 PM PDT 24
Peak memory 200408 kb
Host smart-9d206829-ceef-43d5-aa6d-72c427ec8b49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904285375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2904285375
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1038928347
Short name T610
Test name
Test status
Simulation time 117939013 ps
CPU time 1.47 seconds
Started May 30 02:35:41 PM PDT 24
Finished May 30 02:35:43 PM PDT 24
Peak memory 208816 kb
Host smart-fbef1ee6-4426-4ca7-82af-b14cb476cf9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038928347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1038928347
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2522055077
Short name T591
Test name
Test status
Simulation time 433326520 ps
CPU time 1.9 seconds
Started May 30 02:35:42 PM PDT 24
Finished May 30 02:35:45 PM PDT 24
Peak memory 200648 kb
Host smart-afc5e507-98eb-41a9-a7d3-256bbe3c72e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522055077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2522055077
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.640453323
Short name T614
Test name
Test status
Simulation time 210783400 ps
CPU time 1.6 seconds
Started May 30 02:35:35 PM PDT 24
Finished May 30 02:35:37 PM PDT 24
Peak memory 200556 kb
Host smart-45dab711-fb47-45a8-a944-131d82c25615
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640453323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.640453323
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4121961910
Short name T546
Test name
Test status
Simulation time 823948785 ps
CPU time 4.95 seconds
Started May 30 02:35:39 PM PDT 24
Finished May 30 02:35:45 PM PDT 24
Peak memory 200540 kb
Host smart-b16de2df-5599-4cce-b922-96d810e90895
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121961910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.4
121961910
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2018692179
Short name T107
Test name
Test status
Simulation time 113831801 ps
CPU time 0.91 seconds
Started May 30 02:35:42 PM PDT 24
Finished May 30 02:35:44 PM PDT 24
Peak memory 200376 kb
Host smart-d0505e15-6e70-4959-a87c-92b6db9f9555
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018692179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
018692179
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.566927728
Short name T575
Test name
Test status
Simulation time 139829582 ps
CPU time 1.53 seconds
Started May 30 02:35:42 PM PDT 24
Finished May 30 02:35:45 PM PDT 24
Peak memory 208892 kb
Host smart-bc634b7e-ab17-48b6-b514-e5c274ccb3d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566927728 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.566927728
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2902582006
Short name T544
Test name
Test status
Simulation time 85152323 ps
CPU time 0.87 seconds
Started May 30 02:35:39 PM PDT 24
Finished May 30 02:35:41 PM PDT 24
Peak memory 200356 kb
Host smart-4a6e22e8-f49a-43a7-bfe3-50e774c622da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902582006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2902582006
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4020651464
Short name T104
Test name
Test status
Simulation time 132158275 ps
CPU time 1.1 seconds
Started May 30 02:35:32 PM PDT 24
Finished May 30 02:35:35 PM PDT 24
Peak memory 200436 kb
Host smart-7fd2eded-e726-492c-9daa-d811888d4397
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020651464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.4020651464
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.540790153
Short name T589
Test name
Test status
Simulation time 157992157 ps
CPU time 2.46 seconds
Started May 30 02:35:44 PM PDT 24
Finished May 30 02:35:48 PM PDT 24
Peak memory 208836 kb
Host smart-08118b4a-2fac-4c5d-aab4-cffea9c2b9af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540790153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.540790153
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1961860642
Short name T587
Test name
Test status
Simulation time 425955110 ps
CPU time 1.68 seconds
Started May 30 02:35:42 PM PDT 24
Finished May 30 02:35:45 PM PDT 24
Peak memory 200652 kb
Host smart-e7dd6007-82bc-495c-8d72-8068d9c834fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961860642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1961860642
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1032556467
Short name T616
Test name
Test status
Simulation time 111567020 ps
CPU time 0.92 seconds
Started May 30 02:35:42 PM PDT 24
Finished May 30 02:35:44 PM PDT 24
Peak memory 200452 kb
Host smart-b9346764-b6c9-4c49-b242-a59465d08394
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032556467 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1032556467
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1815146383
Short name T572
Test name
Test status
Simulation time 71578234 ps
CPU time 0.8 seconds
Started May 30 02:35:43 PM PDT 24
Finished May 30 02:35:46 PM PDT 24
Peak memory 200336 kb
Host smart-fbe822ba-cf01-410d-a5ae-2eddc67c481f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815146383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1815146383
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.23816313
Short name T615
Test name
Test status
Simulation time 296032355 ps
CPU time 1.83 seconds
Started May 30 02:35:43 PM PDT 24
Finished May 30 02:35:47 PM PDT 24
Peak memory 200580 kb
Host smart-84ff8d8d-78aa-4d44-b09b-07e23d848f4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23816313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_same
_csr_outstanding.23816313
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2569959004
Short name T88
Test name
Test status
Simulation time 296079188 ps
CPU time 2.17 seconds
Started May 30 02:35:43 PM PDT 24
Finished May 30 02:35:47 PM PDT 24
Peak memory 216708 kb
Host smart-2a6e09da-44d4-437b-bf24-8c9bd44370fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569959004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2569959004
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.715833654
Short name T555
Test name
Test status
Simulation time 425992079 ps
CPU time 1.85 seconds
Started May 30 02:35:43 PM PDT 24
Finished May 30 02:35:46 PM PDT 24
Peak memory 200648 kb
Host smart-54622d2e-781e-4346-846f-6f2bfaffd7e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715833654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.
715833654
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.927406601
Short name T583
Test name
Test status
Simulation time 183316626 ps
CPU time 1.16 seconds
Started May 30 02:35:32 PM PDT 24
Finished May 30 02:35:35 PM PDT 24
Peak memory 200496 kb
Host smart-790ee37f-0da3-452f-88b8-2a3b6024311f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927406601 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.927406601
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3390139330
Short name T103
Test name
Test status
Simulation time 56985844 ps
CPU time 0.74 seconds
Started May 30 02:35:51 PM PDT 24
Finished May 30 02:35:53 PM PDT 24
Peak memory 200388 kb
Host smart-a39beba2-dc01-4429-893f-3757865f37af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390139330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3390139330
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1376674851
Short name T605
Test name
Test status
Simulation time 79661887 ps
CPU time 1.02 seconds
Started May 30 02:35:32 PM PDT 24
Finished May 30 02:35:35 PM PDT 24
Peak memory 200416 kb
Host smart-b2fa82fb-a405-4780-9611-90aaaa28ccb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376674851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1376674851
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.291122606
Short name T602
Test name
Test status
Simulation time 134565833 ps
CPU time 1.99 seconds
Started May 30 02:35:31 PM PDT 24
Finished May 30 02:35:35 PM PDT 24
Peak memory 211892 kb
Host smart-b0b7f1c8-7314-41b5-b579-e7ffcb7f64bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291122606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.291122606
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.4115626568
Short name T603
Test name
Test status
Simulation time 131700879 ps
CPU time 1.11 seconds
Started May 30 02:35:55 PM PDT 24
Finished May 30 02:36:00 PM PDT 24
Peak memory 200480 kb
Host smart-bc62c7d1-e1b6-4b1b-8aa7-765163428015
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115626568 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.4115626568
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2983479977
Short name T566
Test name
Test status
Simulation time 72496059 ps
CPU time 0.91 seconds
Started May 30 02:35:52 PM PDT 24
Finished May 30 02:35:54 PM PDT 24
Peak memory 200356 kb
Host smart-3dc1da2b-24c4-4f34-8895-080a17ac6697
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983479977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2983479977
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1206139299
Short name T99
Test name
Test status
Simulation time 129985083 ps
CPU time 1.1 seconds
Started May 30 02:35:51 PM PDT 24
Finished May 30 02:35:54 PM PDT 24
Peak memory 200416 kb
Host smart-d3249bf2-9568-4c2b-bc45-1d582a2ea189
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206139299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1206139299
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3573888868
Short name T577
Test name
Test status
Simulation time 240703519 ps
CPU time 1.9 seconds
Started May 30 02:35:50 PM PDT 24
Finished May 30 02:35:53 PM PDT 24
Peak memory 200624 kb
Host smart-1f4ff6b4-8cd4-4fa6-a0c8-0513ef4fa41b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573888868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3573888868
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.59099020
Short name T56
Test name
Test status
Simulation time 415070353 ps
CPU time 1.84 seconds
Started May 30 02:35:53 PM PDT 24
Finished May 30 02:35:57 PM PDT 24
Peak memory 200740 kb
Host smart-69fd3df0-2d20-4a8d-90eb-70e44cf7d0f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59099020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.59099020
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2496998986
Short name T87
Test name
Test status
Simulation time 180196973 ps
CPU time 1.37 seconds
Started May 30 02:35:53 PM PDT 24
Finished May 30 02:35:56 PM PDT 24
Peak memory 208620 kb
Host smart-53a75987-909d-47b6-9abd-fe86f539968a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496998986 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2496998986
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1242045946
Short name T556
Test name
Test status
Simulation time 76328700 ps
CPU time 0.82 seconds
Started May 30 02:35:54 PM PDT 24
Finished May 30 02:35:57 PM PDT 24
Peak memory 200312 kb
Host smart-d2adc161-fae8-456f-9d8a-df3f67b109b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242045946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1242045946
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3865559390
Short name T100
Test name
Test status
Simulation time 88620770 ps
CPU time 1.11 seconds
Started May 30 02:35:53 PM PDT 24
Finished May 30 02:35:56 PM PDT 24
Peak memory 200428 kb
Host smart-7fa9c600-9297-47fa-ab18-798407fe8b36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865559390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3865559390
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.736865125
Short name T85
Test name
Test status
Simulation time 272496767 ps
CPU time 2.24 seconds
Started May 30 02:35:56 PM PDT 24
Finished May 30 02:36:01 PM PDT 24
Peak memory 208788 kb
Host smart-798a9b24-20e5-4b33-abb4-eec43c905c4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736865125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.736865125
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2831920689
Short name T569
Test name
Test status
Simulation time 866619609 ps
CPU time 3 seconds
Started May 30 02:35:57 PM PDT 24
Finished May 30 02:36:03 PM PDT 24
Peak memory 200624 kb
Host smart-d9d127ea-7e2a-4e61-8168-77c86e4652e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831920689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.2831920689
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3427079298
Short name T586
Test name
Test status
Simulation time 206161655 ps
CPU time 1.4 seconds
Started May 30 02:35:53 PM PDT 24
Finished May 30 02:35:57 PM PDT 24
Peak memory 211192 kb
Host smart-e162aba5-ff1e-499b-9994-ece1aab6d5df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427079298 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3427079298
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1444027036
Short name T574
Test name
Test status
Simulation time 65290184 ps
CPU time 0.83 seconds
Started May 30 02:35:52 PM PDT 24
Finished May 30 02:35:55 PM PDT 24
Peak memory 200356 kb
Host smart-b00b7df5-6252-401d-81c3-429c25f6a942
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444027036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1444027036
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1388288389
Short name T554
Test name
Test status
Simulation time 69232973 ps
CPU time 1 seconds
Started May 30 02:35:53 PM PDT 24
Finished May 30 02:35:56 PM PDT 24
Peak memory 200428 kb
Host smart-214e694a-457b-4f5c-8a10-f2f95004cec8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388288389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1388288389
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2302373572
Short name T545
Test name
Test status
Simulation time 364366180 ps
CPU time 2.54 seconds
Started May 30 02:35:56 PM PDT 24
Finished May 30 02:36:02 PM PDT 24
Peak memory 208800 kb
Host smart-62c1e363-c388-47ab-94d8-bc44e928bfbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302373572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2302373572
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.4190538840
Short name T110
Test name
Test status
Simulation time 931122062 ps
CPU time 3.12 seconds
Started May 30 02:35:53 PM PDT 24
Finished May 30 02:35:58 PM PDT 24
Peak memory 200632 kb
Host smart-c0ae11e6-07db-4c82-abf3-388b68047c76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190538840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.4190538840
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3142845983
Short name T277
Test name
Test status
Simulation time 76272725 ps
CPU time 0.89 seconds
Started May 30 02:18:29 PM PDT 24
Finished May 30 02:18:31 PM PDT 24
Peak memory 200652 kb
Host smart-86103567-8285-47ff-afe9-d56fe2cf9cca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142845983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3142845983
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3659161888
Short name T424
Test name
Test status
Simulation time 1227914680 ps
CPU time 5.71 seconds
Started May 30 02:18:22 PM PDT 24
Finished May 30 02:18:29 PM PDT 24
Peak memory 218512 kb
Host smart-98b7f351-6db9-4aa4-9c6e-f6a6b1ae9999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659161888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3659161888
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.77292765
Short name T407
Test name
Test status
Simulation time 244329131 ps
CPU time 1.08 seconds
Started May 30 02:18:21 PM PDT 24
Finished May 30 02:18:23 PM PDT 24
Peak memory 217988 kb
Host smart-57131ccc-63fa-4d62-8f30-09ae58fc8555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77292765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.77292765
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3586054136
Short name T347
Test name
Test status
Simulation time 178499353 ps
CPU time 0.89 seconds
Started May 30 02:18:25 PM PDT 24
Finished May 30 02:18:26 PM PDT 24
Peak memory 200680 kb
Host smart-ed9ad7e6-25a6-4b2e-977a-dc7496fd264c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586054136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3586054136
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1570314942
Short name T367
Test name
Test status
Simulation time 1655753619 ps
CPU time 6.44 seconds
Started May 30 02:18:24 PM PDT 24
Finished May 30 02:18:32 PM PDT 24
Peak memory 201056 kb
Host smart-f734237e-a9df-476e-9a67-38354852cace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570314942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1570314942
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2480903108
Short name T312
Test name
Test status
Simulation time 193524283 ps
CPU time 1.45 seconds
Started May 30 02:18:22 PM PDT 24
Finished May 30 02:18:24 PM PDT 24
Peak memory 201044 kb
Host smart-d85c8b9a-eb51-4c0e-b588-886affa0560d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480903108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2480903108
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.2468464273
Short name T501
Test name
Test status
Simulation time 4486940926 ps
CPU time 21.66 seconds
Started May 30 02:18:23 PM PDT 24
Finished May 30 02:18:46 PM PDT 24
Peak memory 211016 kb
Host smart-5b1e7138-a220-434c-95f5-dc16eeb6e21e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468464273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2468464273
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3139843168
Short name T518
Test name
Test status
Simulation time 395983143 ps
CPU time 2.37 seconds
Started May 30 02:18:24 PM PDT 24
Finished May 30 02:18:27 PM PDT 24
Peak memory 200824 kb
Host smart-61d923c5-764a-4f6a-b017-535a638ae691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139843168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3139843168
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.1925278602
Short name T224
Test name
Test status
Simulation time 183000180 ps
CPU time 1.14 seconds
Started May 30 02:18:24 PM PDT 24
Finished May 30 02:18:26 PM PDT 24
Peak memory 200852 kb
Host smart-103fce26-7804-4f6b-bad0-3ad4ce374c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925278602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1925278602
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.772740430
Short name T375
Test name
Test status
Simulation time 78665732 ps
CPU time 0.82 seconds
Started May 30 02:18:37 PM PDT 24
Finished May 30 02:18:39 PM PDT 24
Peak memory 200684 kb
Host smart-400a985c-de87-4492-a525-6a09d2ef8f0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772740430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.772740430
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.493955946
Short name T378
Test name
Test status
Simulation time 2167915422 ps
CPU time 8.09 seconds
Started May 30 02:18:34 PM PDT 24
Finished May 30 02:18:43 PM PDT 24
Peak memory 218652 kb
Host smart-cb37006a-384d-491e-b192-5b51774c5996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493955946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.493955946
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1891491876
Short name T437
Test name
Test status
Simulation time 243789656 ps
CPU time 1.08 seconds
Started May 30 02:18:37 PM PDT 24
Finished May 30 02:18:39 PM PDT 24
Peak memory 218064 kb
Host smart-eccdb1f4-d689-4537-b365-e57d7aaea907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891491876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1891491876
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.616597449
Short name T356
Test name
Test status
Simulation time 112527856 ps
CPU time 0.79 seconds
Started May 30 02:18:26 PM PDT 24
Finished May 30 02:18:27 PM PDT 24
Peak memory 200696 kb
Host smart-76d9e11d-c472-44df-b0d5-2c55ad47df16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616597449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.616597449
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1877093314
Short name T432
Test name
Test status
Simulation time 1372288880 ps
CPU time 5.75 seconds
Started May 30 02:18:35 PM PDT 24
Finished May 30 02:18:42 PM PDT 24
Peak memory 201120 kb
Host smart-b243774b-0293-42a2-b18c-959f24dd57de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877093314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1877093314
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3564272462
Short name T57
Test name
Test status
Simulation time 16529330244 ps
CPU time 27.02 seconds
Started May 30 02:18:37 PM PDT 24
Finished May 30 02:19:05 PM PDT 24
Peak memory 217720 kb
Host smart-7491c230-da37-4e1f-86c2-b9d9d3843135
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564272462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3564272462
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.102712312
Short name T140
Test name
Test status
Simulation time 143781866 ps
CPU time 1.25 seconds
Started May 30 02:18:34 PM PDT 24
Finished May 30 02:18:35 PM PDT 24
Peak memory 200848 kb
Host smart-9cc9c529-1d70-4669-8668-14e24c5b81ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102712312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.102712312
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.3265209543
Short name T333
Test name
Test status
Simulation time 117109080 ps
CPU time 1.21 seconds
Started May 30 02:18:26 PM PDT 24
Finished May 30 02:18:28 PM PDT 24
Peak memory 201068 kb
Host smart-aab764b4-e2d4-43c2-a4c9-adaa91f261d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265209543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3265209543
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2647165862
Short name T443
Test name
Test status
Simulation time 2347957474 ps
CPU time 11.87 seconds
Started May 30 02:18:32 PM PDT 24
Finished May 30 02:18:45 PM PDT 24
Peak memory 201216 kb
Host smart-9704f2b2-a862-4343-8bd8-8c8e89a2b659
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647165862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2647165862
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.621622135
Short name T495
Test name
Test status
Simulation time 403293522 ps
CPU time 2.2 seconds
Started May 30 02:18:32 PM PDT 24
Finished May 30 02:18:35 PM PDT 24
Peak memory 209108 kb
Host smart-9e945082-cbac-4f68-9950-e79ec8c417a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621622135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.621622135
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.434943026
Short name T361
Test name
Test status
Simulation time 63859987 ps
CPU time 0.76 seconds
Started May 30 02:19:38 PM PDT 24
Finished May 30 02:19:39 PM PDT 24
Peak memory 200156 kb
Host smart-8bd2a19a-8908-44f8-b85a-156d725ca461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434943026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.434943026
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.425320491
Short name T32
Test name
Test status
Simulation time 1884087752 ps
CPU time 7.17 seconds
Started May 30 02:19:35 PM PDT 24
Finished May 30 02:19:43 PM PDT 24
Peak memory 217472 kb
Host smart-84cee810-a64c-4c3b-96b0-7f33c36dc8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425320491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.425320491
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.518580807
Short name T158
Test name
Test status
Simulation time 243824294 ps
CPU time 1.14 seconds
Started May 30 02:19:38 PM PDT 24
Finished May 30 02:19:41 PM PDT 24
Peak memory 218180 kb
Host smart-b5d563d4-7c8d-4041-9fb3-4e741b2375aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518580807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.518580807
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.1927234040
Short name T537
Test name
Test status
Simulation time 131868468 ps
CPU time 0.85 seconds
Started May 30 02:19:25 PM PDT 24
Finished May 30 02:19:26 PM PDT 24
Peak memory 200620 kb
Host smart-00892750-bd56-401c-95b0-4056a942cabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927234040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.1927234040
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.541399812
Short name T72
Test name
Test status
Simulation time 1582673275 ps
CPU time 6.74 seconds
Started May 30 02:19:23 PM PDT 24
Finished May 30 02:19:30 PM PDT 24
Peak memory 201068 kb
Host smart-e85f4ec0-5424-48ca-8354-b76442e21638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541399812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.541399812
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1424088240
Short name T268
Test name
Test status
Simulation time 108788697 ps
CPU time 1.05 seconds
Started May 30 02:19:21 PM PDT 24
Finished May 30 02:19:23 PM PDT 24
Peak memory 200848 kb
Host smart-8b6e0854-ff4e-425d-9f5b-b551e34cdd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424088240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1424088240
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.3550813196
Short name T67
Test name
Test status
Simulation time 196195050 ps
CPU time 1.41 seconds
Started May 30 02:19:21 PM PDT 24
Finished May 30 02:19:23 PM PDT 24
Peak memory 201032 kb
Host smart-f87a8183-9376-43cf-87df-0c89de289d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550813196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3550813196
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1629728699
Short name T369
Test name
Test status
Simulation time 3050595304 ps
CPU time 14.45 seconds
Started May 30 02:19:36 PM PDT 24
Finished May 30 02:19:51 PM PDT 24
Peak memory 201240 kb
Host smart-fe5744c1-8ed7-43a1-a466-ceb29749d800
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629728699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1629728699
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3052800766
Short name T323
Test name
Test status
Simulation time 375197735 ps
CPU time 2.41 seconds
Started May 30 02:19:22 PM PDT 24
Finished May 30 02:19:25 PM PDT 24
Peak memory 200932 kb
Host smart-ff0d6893-c53a-493c-95d1-37c10f523600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052800766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3052800766
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2175433178
Short name T77
Test name
Test status
Simulation time 86242926 ps
CPU time 0.87 seconds
Started May 30 02:19:20 PM PDT 24
Finished May 30 02:19:21 PM PDT 24
Peak memory 200860 kb
Host smart-1c7245ac-5dea-4f73-bd27-969fd815f1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175433178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2175433178
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.3878474772
Short name T493
Test name
Test status
Simulation time 67199069 ps
CPU time 0.81 seconds
Started May 30 02:19:35 PM PDT 24
Finished May 30 02:19:37 PM PDT 24
Peak memory 200716 kb
Host smart-13c728e3-d327-48f7-8cdc-7e9a7a0874d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878474772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3878474772
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1115165275
Short name T352
Test name
Test status
Simulation time 2357962726 ps
CPU time 8.9 seconds
Started May 30 02:19:35 PM PDT 24
Finished May 30 02:19:45 PM PDT 24
Peak memory 222620 kb
Host smart-f6fa8f2f-e9e2-4dca-b819-1a07c7c2297d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115165275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1115165275
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3531903335
Short name T376
Test name
Test status
Simulation time 246529164 ps
CPU time 1.05 seconds
Started May 30 02:19:34 PM PDT 24
Finished May 30 02:19:36 PM PDT 24
Peak memory 218104 kb
Host smart-66a203fe-8479-4b35-8be3-6f99507b669c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531903335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3531903335
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_reset.3398117837
Short name T293
Test name
Test status
Simulation time 982654741 ps
CPU time 5.38 seconds
Started May 30 02:19:34 PM PDT 24
Finished May 30 02:19:40 PM PDT 24
Peak memory 201064 kb
Host smart-341e9cb4-5cd2-4252-8907-1964d65f755d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398117837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3398117837
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1824876545
Short name T273
Test name
Test status
Simulation time 95606848 ps
CPU time 1.03 seconds
Started May 30 02:19:35 PM PDT 24
Finished May 30 02:19:37 PM PDT 24
Peak memory 200948 kb
Host smart-83ba9b6e-7004-43ba-a281-71be54848939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824876545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1824876545
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3848274815
Short name T447
Test name
Test status
Simulation time 116066301 ps
CPU time 1.21 seconds
Started May 30 02:19:37 PM PDT 24
Finished May 30 02:19:39 PM PDT 24
Peak memory 201024 kb
Host smart-81406b33-e8c9-4569-b874-b59bb0ae703b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848274815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3848274815
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2754199320
Short name T192
Test name
Test status
Simulation time 9886142929 ps
CPU time 34.88 seconds
Started May 30 02:19:38 PM PDT 24
Finished May 30 02:20:13 PM PDT 24
Peak memory 208848 kb
Host smart-137ec5ff-bffa-4de6-ac51-4bac25d3d0c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754199320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2754199320
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2261048604
Short name T538
Test name
Test status
Simulation time 122074313 ps
CPU time 1.5 seconds
Started May 30 02:19:35 PM PDT 24
Finished May 30 02:19:37 PM PDT 24
Peak memory 200836 kb
Host smart-f6eb23dc-21d0-42d1-8060-f58078818df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261048604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2261048604
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1606865286
Short name T526
Test name
Test status
Simulation time 122366321 ps
CPU time 1.15 seconds
Started May 30 02:19:35 PM PDT 24
Finished May 30 02:19:37 PM PDT 24
Peak memory 200832 kb
Host smart-b1db2dfc-c8c9-42d8-8116-175b120b4b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606865286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1606865286
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.213752124
Short name T428
Test name
Test status
Simulation time 109818673 ps
CPU time 0.87 seconds
Started May 30 02:19:50 PM PDT 24
Finished May 30 02:19:51 PM PDT 24
Peak memory 200716 kb
Host smart-3ac1f025-535c-41f5-b8bd-1957b3e719f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213752124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.213752124
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.467329080
Short name T289
Test name
Test status
Simulation time 214289363 ps
CPU time 0.97 seconds
Started May 30 02:19:36 PM PDT 24
Finished May 30 02:19:37 PM PDT 24
Peak memory 200688 kb
Host smart-48dc55b3-3b50-4c3f-921f-87614c14ed19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467329080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.467329080
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.927737258
Short name T503
Test name
Test status
Simulation time 1139869116 ps
CPU time 4.72 seconds
Started May 30 02:19:50 PM PDT 24
Finished May 30 02:19:56 PM PDT 24
Peak memory 201036 kb
Host smart-fa7c2c13-2570-4c73-838a-27c57505dc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927737258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.927737258
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1376232807
Short name T360
Test name
Test status
Simulation time 174201496 ps
CPU time 1.22 seconds
Started May 30 02:19:49 PM PDT 24
Finished May 30 02:19:51 PM PDT 24
Peak memory 200888 kb
Host smart-219b8111-2743-432b-9d5d-33d994d53328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376232807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1376232807
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1776002832
Short name T514
Test name
Test status
Simulation time 233281513 ps
CPU time 1.45 seconds
Started May 30 02:19:34 PM PDT 24
Finished May 30 02:19:36 PM PDT 24
Peak memory 201024 kb
Host smart-288e5107-2ae3-47b7-9ef0-1617df7a700d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776002832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1776002832
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2553758944
Short name T136
Test name
Test status
Simulation time 5752085471 ps
CPU time 24.29 seconds
Started May 30 02:19:53 PM PDT 24
Finished May 30 02:20:18 PM PDT 24
Peak memory 211124 kb
Host smart-f645fecc-8636-47f8-bf1b-560e73ebc050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553758944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2553758944
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.787188041
Short name T454
Test name
Test status
Simulation time 262112403 ps
CPU time 1.91 seconds
Started May 30 02:19:50 PM PDT 24
Finished May 30 02:19:54 PM PDT 24
Peak memory 200888 kb
Host smart-b99ac2dc-2b6f-4a57-9b88-b5b3b5021a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787188041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.787188041
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3033542673
Short name T63
Test name
Test status
Simulation time 80107094 ps
CPU time 0.85 seconds
Started May 30 02:19:49 PM PDT 24
Finished May 30 02:19:51 PM PDT 24
Peak memory 200868 kb
Host smart-b9b9a0c1-76a2-4526-aa0d-ecf0a6dfcb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033542673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3033542673
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.4032348170
Short name T176
Test name
Test status
Simulation time 65701523 ps
CPU time 0.84 seconds
Started May 30 02:19:49 PM PDT 24
Finished May 30 02:19:50 PM PDT 24
Peak memory 200688 kb
Host smart-f1db123d-4cc2-4b89-befd-26775a59904e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032348170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.4032348170
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3377737556
Short name T465
Test name
Test status
Simulation time 2368333723 ps
CPU time 9.96 seconds
Started May 30 02:19:51 PM PDT 24
Finished May 30 02:20:02 PM PDT 24
Peak memory 218724 kb
Host smart-502b2d21-a258-4f5d-9e1a-afd430ea4125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377737556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3377737556
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2065689768
Short name T146
Test name
Test status
Simulation time 244663286 ps
CPU time 1.08 seconds
Started May 30 02:19:50 PM PDT 24
Finished May 30 02:19:52 PM PDT 24
Peak memory 218012 kb
Host smart-ed0ee75f-5950-4b1b-b03c-39e2a47cb521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065689768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2065689768
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3303697905
Short name T334
Test name
Test status
Simulation time 125325575 ps
CPU time 0.81 seconds
Started May 30 02:19:50 PM PDT 24
Finished May 30 02:19:52 PM PDT 24
Peak memory 200648 kb
Host smart-506b9915-0efa-43ef-a89b-4652c3ce6ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303697905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3303697905
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.869393618
Short name T446
Test name
Test status
Simulation time 1026210001 ps
CPU time 5.2 seconds
Started May 30 02:19:48 PM PDT 24
Finished May 30 02:19:54 PM PDT 24
Peak memory 201060 kb
Host smart-b16f0c6c-3aed-4dbf-bf41-b2889745e601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869393618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.869393618
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1500359831
Short name T120
Test name
Test status
Simulation time 178447026 ps
CPU time 1.21 seconds
Started May 30 02:19:48 PM PDT 24
Finished May 30 02:19:50 PM PDT 24
Peak memory 200884 kb
Host smart-0a390b9d-c830-4dec-a5db-b5d6f0f80bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500359831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1500359831
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.373595673
Short name T506
Test name
Test status
Simulation time 120109737 ps
CPU time 1.24 seconds
Started May 30 02:19:52 PM PDT 24
Finished May 30 02:19:55 PM PDT 24
Peak memory 201044 kb
Host smart-dcf486b2-7369-46d8-a1a4-e23d4af14a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373595673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.373595673
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1142229891
Short name T78
Test name
Test status
Simulation time 6570036459 ps
CPU time 23.56 seconds
Started May 30 02:19:52 PM PDT 24
Finished May 30 02:20:16 PM PDT 24
Peak memory 209448 kb
Host smart-876549f3-bb1a-4e69-a415-a08c6a7bee4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142229891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1142229891
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.978625468
Short name T527
Test name
Test status
Simulation time 257541300 ps
CPU time 1.75 seconds
Started May 30 02:19:49 PM PDT 24
Finished May 30 02:19:51 PM PDT 24
Peak memory 200876 kb
Host smart-fcd82eef-8bdb-4c6c-84ef-93798ef1c15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978625468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.978625468
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1986916623
Short name T266
Test name
Test status
Simulation time 87199352 ps
CPU time 0.93 seconds
Started May 30 02:19:50 PM PDT 24
Finished May 30 02:19:52 PM PDT 24
Peak memory 200964 kb
Host smart-4e58f346-d732-4b19-bd22-9535a65ebd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986916623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1986916623
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.1128634107
Short name T207
Test name
Test status
Simulation time 63192402 ps
CPU time 0.75 seconds
Started May 30 02:19:51 PM PDT 24
Finished May 30 02:19:53 PM PDT 24
Peak memory 200716 kb
Host smart-13e04bab-f409-4947-be04-2fe7245b28ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128634107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1128634107
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1609787073
Short name T321
Test name
Test status
Simulation time 1898425476 ps
CPU time 7 seconds
Started May 30 02:19:51 PM PDT 24
Finished May 30 02:19:59 PM PDT 24
Peak memory 222456 kb
Host smart-fdb4652d-1457-401d-a954-becccd9bc55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609787073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1609787073
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3835001284
Short name T240
Test name
Test status
Simulation time 245649405 ps
CPU time 1.07 seconds
Started May 30 02:19:53 PM PDT 24
Finished May 30 02:19:55 PM PDT 24
Peak memory 218020 kb
Host smart-eed64498-b13d-4023-98d4-3455f16d0506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835001284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3835001284
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3122670743
Short name T482
Test name
Test status
Simulation time 222898494 ps
CPU time 0.92 seconds
Started May 30 02:19:50 PM PDT 24
Finished May 30 02:19:52 PM PDT 24
Peak memory 200680 kb
Host smart-28ccab40-ba8d-44df-bac0-c8f040a217b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122670743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3122670743
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.4076657081
Short name T450
Test name
Test status
Simulation time 925035240 ps
CPU time 5.3 seconds
Started May 30 02:19:50 PM PDT 24
Finished May 30 02:19:56 PM PDT 24
Peak memory 201052 kb
Host smart-a1e17ff3-4473-4b03-98d7-7509a6353b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076657081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.4076657081
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3536620825
Short name T261
Test name
Test status
Simulation time 183994588 ps
CPU time 1.16 seconds
Started May 30 02:19:52 PM PDT 24
Finished May 30 02:19:54 PM PDT 24
Peak memory 200848 kb
Host smart-5b2374e7-c076-4aa4-a500-c72e81cbb1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536620825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3536620825
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.1522621212
Short name T486
Test name
Test status
Simulation time 231358775 ps
CPU time 1.4 seconds
Started May 30 02:19:52 PM PDT 24
Finished May 30 02:19:54 PM PDT 24
Peak memory 201068 kb
Host smart-c9cf54b0-2538-45e8-9936-9c34abbd479e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522621212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.1522621212
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.881302710
Short name T94
Test name
Test status
Simulation time 16035816172 ps
CPU time 54.51 seconds
Started May 30 02:19:53 PM PDT 24
Finished May 30 02:20:49 PM PDT 24
Peak memory 201168 kb
Host smart-27c96635-9172-4c20-a610-26cc4a74f885
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881302710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.881302710
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2279870434
Short name T252
Test name
Test status
Simulation time 280875451 ps
CPU time 1.84 seconds
Started May 30 02:19:51 PM PDT 24
Finished May 30 02:19:54 PM PDT 24
Peak memory 200832 kb
Host smart-6b84cc87-daa6-4476-a897-d06bbd0c9607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279870434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2279870434
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1748101283
Short name T530
Test name
Test status
Simulation time 89405105 ps
CPU time 0.9 seconds
Started May 30 02:19:51 PM PDT 24
Finished May 30 02:19:53 PM PDT 24
Peak memory 200888 kb
Host smart-df4daca6-0106-4cb5-b121-c24e629288e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748101283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1748101283
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.1909393494
Short name T505
Test name
Test status
Simulation time 89163111 ps
CPU time 0.87 seconds
Started May 30 02:20:01 PM PDT 24
Finished May 30 02:20:03 PM PDT 24
Peak memory 200720 kb
Host smart-04928823-5755-427a-a4e8-491e27dd762f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909393494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.1909393494
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1191823743
Short name T477
Test name
Test status
Simulation time 1899136575 ps
CPU time 8.15 seconds
Started May 30 02:20:10 PM PDT 24
Finished May 30 02:20:20 PM PDT 24
Peak memory 222592 kb
Host smart-d739b30c-058e-4246-95f4-5011a986ceba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191823743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1191823743
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2187966366
Short name T175
Test name
Test status
Simulation time 246775322 ps
CPU time 1.07 seconds
Started May 30 02:20:10 PM PDT 24
Finished May 30 02:20:13 PM PDT 24
Peak memory 218040 kb
Host smart-7ac8bca8-befb-4490-b559-a96aa22c12fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187966366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2187966366
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.317630564
Short name T19
Test name
Test status
Simulation time 86324278 ps
CPU time 0.81 seconds
Started May 30 02:20:02 PM PDT 24
Finished May 30 02:20:04 PM PDT 24
Peak memory 200676 kb
Host smart-2fad4612-723e-41fa-b19e-a58a4fcf2368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317630564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.317630564
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2510957668
Short name T438
Test name
Test status
Simulation time 1340044611 ps
CPU time 5.56 seconds
Started May 30 02:20:03 PM PDT 24
Finished May 30 02:20:10 PM PDT 24
Peak memory 201056 kb
Host smart-ea04ec08-46d2-4acd-9e40-623e362fa5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510957668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2510957668
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1909531507
Short name T237
Test name
Test status
Simulation time 97859114 ps
CPU time 1.01 seconds
Started May 30 02:20:07 PM PDT 24
Finished May 30 02:20:09 PM PDT 24
Peak memory 200852 kb
Host smart-7f20c5ab-fc0b-4b5f-bcf2-32bc820ee1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909531507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1909531507
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.32749900
Short name T299
Test name
Test status
Simulation time 120332333 ps
CPU time 1.23 seconds
Started May 30 02:20:08 PM PDT 24
Finished May 30 02:20:10 PM PDT 24
Peak memory 201084 kb
Host smart-92e66965-2e2f-4b10-9d50-d4453074e96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32749900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.32749900
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2030255402
Short name T115
Test name
Test status
Simulation time 5630157000 ps
CPU time 19.17 seconds
Started May 30 02:20:02 PM PDT 24
Finished May 30 02:20:22 PM PDT 24
Peak memory 209388 kb
Host smart-47b7bc36-92d6-4768-aafe-0eb79bb4652f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030255402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2030255402
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.3651151097
Short name T230
Test name
Test status
Simulation time 390816462 ps
CPU time 2.75 seconds
Started May 30 02:20:03 PM PDT 24
Finished May 30 02:20:07 PM PDT 24
Peak memory 200872 kb
Host smart-5d45e9c9-97eb-4784-adab-9d30bceca64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651151097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.3651151097
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.654398299
Short name T345
Test name
Test status
Simulation time 200499400 ps
CPU time 1.2 seconds
Started May 30 02:20:02 PM PDT 24
Finished May 30 02:20:04 PM PDT 24
Peak memory 200872 kb
Host smart-a6d64e0b-e0b3-43c1-9a2b-f1dae9dbf014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654398299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.654398299
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1997840457
Short name T246
Test name
Test status
Simulation time 63035187 ps
CPU time 0.72 seconds
Started May 30 02:20:03 PM PDT 24
Finished May 30 02:20:05 PM PDT 24
Peak memory 200716 kb
Host smart-ef198239-b4de-4bd2-92ea-e29e66709e43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997840457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1997840457
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.3024703952
Short name T259
Test name
Test status
Simulation time 1227417161 ps
CPU time 5.84 seconds
Started May 30 02:20:01 PM PDT 24
Finished May 30 02:20:08 PM PDT 24
Peak memory 218512 kb
Host smart-b990ed5e-4b17-4651-bf20-ac2d4e37a793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024703952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.3024703952
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.710597189
Short name T350
Test name
Test status
Simulation time 243648574 ps
CPU time 1.09 seconds
Started May 30 02:20:01 PM PDT 24
Finished May 30 02:20:03 PM PDT 24
Peak memory 218028 kb
Host smart-f007db31-9301-483b-8aca-9bd8c32d02e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710597189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.710597189
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2038348986
Short name T382
Test name
Test status
Simulation time 230065455 ps
CPU time 0.96 seconds
Started May 30 02:20:01 PM PDT 24
Finished May 30 02:20:03 PM PDT 24
Peak memory 200680 kb
Host smart-5beccdb8-4e34-430f-baf1-7ecc411c79ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038348986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2038348986
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.3485513799
Short name T4
Test name
Test status
Simulation time 1012613711 ps
CPU time 5.5 seconds
Started May 30 02:20:04 PM PDT 24
Finished May 30 02:20:10 PM PDT 24
Peak memory 201064 kb
Host smart-61f687c3-fe91-430e-b9ee-f2836de515d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485513799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3485513799
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3989009403
Short name T262
Test name
Test status
Simulation time 166664655 ps
CPU time 1.21 seconds
Started May 30 02:20:04 PM PDT 24
Finished May 30 02:20:06 PM PDT 24
Peak memory 200864 kb
Host smart-67bb3f33-80fe-4e09-a62a-dab5187cf4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989009403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3989009403
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.144183431
Short name T365
Test name
Test status
Simulation time 116647000 ps
CPU time 1.3 seconds
Started May 30 02:20:03 PM PDT 24
Finished May 30 02:20:06 PM PDT 24
Peak memory 201056 kb
Host smart-ce887770-1d8b-46b6-8f69-9a08f82d339c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144183431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.144183431
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1948262698
Short name T150
Test name
Test status
Simulation time 2665167468 ps
CPU time 12.73 seconds
Started May 30 02:20:04 PM PDT 24
Finished May 30 02:20:18 PM PDT 24
Peak memory 201204 kb
Host smart-371df488-c512-4cb5-8924-3bbe83236084
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948262698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1948262698
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2643292323
Short name T489
Test name
Test status
Simulation time 404411578 ps
CPU time 2.22 seconds
Started May 30 02:20:01 PM PDT 24
Finished May 30 02:20:04 PM PDT 24
Peak memory 200804 kb
Host smart-5ab82d42-092e-47f5-8b51-4b3bc4f9a762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643292323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2643292323
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.603361803
Short name T332
Test name
Test status
Simulation time 62195191 ps
CPU time 0.86 seconds
Started May 30 02:20:00 PM PDT 24
Finished May 30 02:20:02 PM PDT 24
Peak memory 200880 kb
Host smart-26a9505e-504b-4dc4-ae52-122b413a6e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603361803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.603361803
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1899814941
Short name T430
Test name
Test status
Simulation time 75663741 ps
CPU time 0.85 seconds
Started May 30 02:20:21 PM PDT 24
Finished May 30 02:20:23 PM PDT 24
Peak memory 200728 kb
Host smart-5d723bc9-bd73-4cdb-82c8-0e4514555a4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899814941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1899814941
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.773489235
Short name T33
Test name
Test status
Simulation time 1216668708 ps
CPU time 6.61 seconds
Started May 30 02:20:07 PM PDT 24
Finished May 30 02:20:15 PM PDT 24
Peak memory 222100 kb
Host smart-34294f36-6ea0-422f-a0d6-3c2ff6b7fd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773489235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.773489235
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1680418822
Short name T219
Test name
Test status
Simulation time 243699448 ps
CPU time 1.13 seconds
Started May 30 02:20:08 PM PDT 24
Finished May 30 02:20:10 PM PDT 24
Peak memory 218192 kb
Host smart-c2fe7e2a-9a23-4138-ad6f-9d3a07b6ce73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680418822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1680418822
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.387870017
Short name T14
Test name
Test status
Simulation time 169944385 ps
CPU time 0.88 seconds
Started May 30 02:20:07 PM PDT 24
Finished May 30 02:20:09 PM PDT 24
Peak memory 200684 kb
Host smart-5c30a76d-3d28-4fbb-a577-5cb77a1044be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387870017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.387870017
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1267898078
Short name T2
Test name
Test status
Simulation time 1471045933 ps
CPU time 6.97 seconds
Started May 30 02:20:05 PM PDT 24
Finished May 30 02:20:13 PM PDT 24
Peak memory 201020 kb
Host smart-99ba8bdf-8e53-4bd7-8a96-5ed46a6f9723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267898078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1267898078
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.206943739
Short name T353
Test name
Test status
Simulation time 165155155 ps
CPU time 1.23 seconds
Started May 30 02:20:02 PM PDT 24
Finished May 30 02:20:04 PM PDT 24
Peak memory 200876 kb
Host smart-37256056-5814-4ec9-abb7-66211f3ceb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206943739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.206943739
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.895907370
Short name T337
Test name
Test status
Simulation time 124733532 ps
CPU time 1.19 seconds
Started May 30 02:20:06 PM PDT 24
Finished May 30 02:20:09 PM PDT 24
Peak memory 201028 kb
Host smart-ebd873f6-c091-4a9d-b332-c3b74658d29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895907370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.895907370
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.2101563446
Short name T241
Test name
Test status
Simulation time 223576415 ps
CPU time 1.41 seconds
Started May 30 02:20:07 PM PDT 24
Finished May 30 02:20:10 PM PDT 24
Peak memory 201120 kb
Host smart-5dc6f0e2-3fa9-4e9b-9f6b-522fd5477026
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101563446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2101563446
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1201898957
Short name T412
Test name
Test status
Simulation time 139946652 ps
CPU time 1.76 seconds
Started May 30 02:20:07 PM PDT 24
Finished May 30 02:20:10 PM PDT 24
Peak memory 200900 kb
Host smart-919cae4f-c9ab-4609-9ccc-36c79845d051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201898957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1201898957
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.1852865855
Short name T211
Test name
Test status
Simulation time 73620443 ps
CPU time 0.79 seconds
Started May 30 02:20:02 PM PDT 24
Finished May 30 02:20:04 PM PDT 24
Peak memory 200868 kb
Host smart-bf5da030-9916-45df-aa52-ddf444437b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852865855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1852865855
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.159259025
Short name T509
Test name
Test status
Simulation time 74318381 ps
CPU time 0.87 seconds
Started May 30 02:20:24 PM PDT 24
Finished May 30 02:20:25 PM PDT 24
Peak memory 200720 kb
Host smart-653eb6c0-ccbf-4127-b45a-dabeef2e72c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159259025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.159259025
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2375148053
Short name T5
Test name
Test status
Simulation time 1236168090 ps
CPU time 5.81 seconds
Started May 30 02:20:23 PM PDT 24
Finished May 30 02:20:29 PM PDT 24
Peak memory 218504 kb
Host smart-48b6c32b-ff26-4732-ba08-0532359116d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375148053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2375148053
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.200099961
Short name T195
Test name
Test status
Simulation time 244287119 ps
CPU time 1.19 seconds
Started May 30 02:20:22 PM PDT 24
Finished May 30 02:20:24 PM PDT 24
Peak memory 218200 kb
Host smart-73285c4b-e511-4248-8653-a66e6de6eec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200099961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.200099961
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.540988803
Short name T442
Test name
Test status
Simulation time 219441248 ps
CPU time 0.99 seconds
Started May 30 02:20:22 PM PDT 24
Finished May 30 02:20:24 PM PDT 24
Peak memory 200700 kb
Host smart-2c7c931f-0e25-47fb-be6f-b626ce9c4ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540988803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.540988803
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.2915872609
Short name T218
Test name
Test status
Simulation time 1867917960 ps
CPU time 7.19 seconds
Started May 30 02:20:20 PM PDT 24
Finished May 30 02:20:28 PM PDT 24
Peak memory 201092 kb
Host smart-85ecf12b-3113-4146-b7db-596b488e0310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915872609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2915872609
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2605502678
Short name T263
Test name
Test status
Simulation time 98650301 ps
CPU time 1.01 seconds
Started May 30 02:20:23 PM PDT 24
Finished May 30 02:20:25 PM PDT 24
Peak memory 200852 kb
Host smart-78a008f6-a159-4a70-9744-ce45f367679f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605502678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2605502678
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.3049252360
Short name T178
Test name
Test status
Simulation time 194540836 ps
CPU time 1.5 seconds
Started May 30 02:20:21 PM PDT 24
Finished May 30 02:20:23 PM PDT 24
Peak memory 201036 kb
Host smart-5a90c27d-11c5-4f91-92af-1a807651ac5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049252360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.3049252360
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2399126715
Short name T166
Test name
Test status
Simulation time 10068976971 ps
CPU time 38.67 seconds
Started May 30 02:20:23 PM PDT 24
Finished May 30 02:21:03 PM PDT 24
Peak memory 201204 kb
Host smart-92c6948a-1983-4d70-a4cd-0b29d333bcdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399126715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2399126715
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3967394988
Short name T456
Test name
Test status
Simulation time 274153116 ps
CPU time 1.91 seconds
Started May 30 02:20:21 PM PDT 24
Finished May 30 02:20:24 PM PDT 24
Peak memory 200936 kb
Host smart-3a2f64be-26ff-41f6-b6e4-37a89abb09a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967394988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3967394988
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.213322769
Short name T473
Test name
Test status
Simulation time 67744278 ps
CPU time 0.76 seconds
Started May 30 02:20:20 PM PDT 24
Finished May 30 02:20:22 PM PDT 24
Peak memory 200860 kb
Host smart-8f1e98ac-c54c-4fb9-94fc-9f2ea761b51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213322769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.213322769
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.3400394759
Short name T296
Test name
Test status
Simulation time 98706145 ps
CPU time 0.88 seconds
Started May 30 02:20:22 PM PDT 24
Finished May 30 02:20:24 PM PDT 24
Peak memory 200708 kb
Host smart-3cf69fc5-dda1-4674-ac32-b7f3185ed148
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400394759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3400394759
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2934253630
Short name T161
Test name
Test status
Simulation time 245156479 ps
CPU time 1.15 seconds
Started May 30 02:20:23 PM PDT 24
Finished May 30 02:20:25 PM PDT 24
Peak memory 218040 kb
Host smart-276ebfce-f520-4214-be29-1e793fc05d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934253630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2934253630
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2866719923
Short name T318
Test name
Test status
Simulation time 233580331 ps
CPU time 0.93 seconds
Started May 30 02:20:23 PM PDT 24
Finished May 30 02:20:25 PM PDT 24
Peak memory 200700 kb
Host smart-6219f8e3-4282-45f4-9644-3154a12514dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866719923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2866719923
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.1762408062
Short name T381
Test name
Test status
Simulation time 1008321880 ps
CPU time 4.89 seconds
Started May 30 02:20:25 PM PDT 24
Finished May 30 02:20:31 PM PDT 24
Peak memory 201064 kb
Host smart-5a9666ff-ef97-4b72-98ff-6ff7cf8f32f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762408062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1762408062
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3473054596
Short name T210
Test name
Test status
Simulation time 99403018 ps
CPU time 1.03 seconds
Started May 30 02:20:23 PM PDT 24
Finished May 30 02:20:25 PM PDT 24
Peak memory 200892 kb
Host smart-f9819177-dfbf-4caa-b629-c3d07c96d2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473054596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3473054596
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2495816908
Short name T359
Test name
Test status
Simulation time 109442034 ps
CPU time 1.24 seconds
Started May 30 02:20:25 PM PDT 24
Finished May 30 02:20:27 PM PDT 24
Peak memory 201044 kb
Host smart-86e555d0-1b37-4358-9310-827d4860bd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495816908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2495816908
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2538403497
Short name T208
Test name
Test status
Simulation time 4695240607 ps
CPU time 24.06 seconds
Started May 30 02:20:25 PM PDT 24
Finished May 30 02:20:50 PM PDT 24
Peak memory 201216 kb
Host smart-e282b7c5-ae88-48f4-bd3f-05bbfadbe412
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538403497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2538403497
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3028072416
Short name T508
Test name
Test status
Simulation time 157358355 ps
CPU time 1.86 seconds
Started May 30 02:20:20 PM PDT 24
Finished May 30 02:20:23 PM PDT 24
Peak memory 200876 kb
Host smart-6048553a-c7e7-4177-ace5-d7b1f7155efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028072416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3028072416
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3585832120
Short name T182
Test name
Test status
Simulation time 88039444 ps
CPU time 0.93 seconds
Started May 30 02:20:22 PM PDT 24
Finished May 30 02:20:24 PM PDT 24
Peak memory 200876 kb
Host smart-4fe2d072-c00d-4194-9609-fc05feb463fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585832120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3585832120
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1009522522
Short name T234
Test name
Test status
Simulation time 74816275 ps
CPU time 0.8 seconds
Started May 30 02:18:56 PM PDT 24
Finished May 30 02:18:58 PM PDT 24
Peak memory 200680 kb
Host smart-a9589723-ff51-4591-ba0e-53540c3ecb3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009522522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1009522522
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3677177458
Short name T26
Test name
Test status
Simulation time 2353892638 ps
CPU time 8.43 seconds
Started May 30 02:18:47 PM PDT 24
Finished May 30 02:18:56 PM PDT 24
Peak memory 222444 kb
Host smart-ef11e2cd-84ef-4b42-972c-cc1666803361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677177458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3677177458
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.145551761
Short name T69
Test name
Test status
Simulation time 247783764 ps
CPU time 1.1 seconds
Started May 30 02:18:37 PM PDT 24
Finished May 30 02:18:40 PM PDT 24
Peak memory 217964 kb
Host smart-f1f28e0c-5c54-4953-a8aa-8005b66771b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145551761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.145551761
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.360175572
Short name T290
Test name
Test status
Simulation time 213025877 ps
CPU time 0.91 seconds
Started May 30 02:18:30 PM PDT 24
Finished May 30 02:18:32 PM PDT 24
Peak memory 200676 kb
Host smart-5d45779f-da28-4bbe-be65-7003e8d30db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360175572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.360175572
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1090650219
Short name T143
Test name
Test status
Simulation time 1425372690 ps
CPU time 5.57 seconds
Started May 30 02:18:36 PM PDT 24
Finished May 30 02:18:42 PM PDT 24
Peak memory 201016 kb
Host smart-4307b852-413c-4ff9-8742-a6b967201301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090650219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1090650219
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.3124683822
Short name T58
Test name
Test status
Simulation time 16537118063 ps
CPU time 30.98 seconds
Started May 30 02:18:48 PM PDT 24
Finished May 30 02:19:20 PM PDT 24
Peak memory 218068 kb
Host smart-c45e8bb4-d799-46d9-9de1-f237ab6f0b44
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124683822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3124683822
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.262254023
Short name T343
Test name
Test status
Simulation time 105855495 ps
CPU time 1.06 seconds
Started May 30 02:18:44 PM PDT 24
Finished May 30 02:18:47 PM PDT 24
Peak memory 200888 kb
Host smart-2e54dad1-b5e9-4885-b242-4386a0202583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262254023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.262254023
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.2550019944
Short name T445
Test name
Test status
Simulation time 258732642 ps
CPU time 1.55 seconds
Started May 30 02:18:36 PM PDT 24
Finished May 30 02:18:39 PM PDT 24
Peak memory 201044 kb
Host smart-fdcb2eb1-95de-4e83-94e7-3a3d7b9fbfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550019944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2550019944
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2256065432
Short name T179
Test name
Test status
Simulation time 2740254934 ps
CPU time 12.01 seconds
Started May 30 02:18:43 PM PDT 24
Finished May 30 02:18:56 PM PDT 24
Peak memory 201144 kb
Host smart-10258c91-746f-4ec3-b034-1faf9246d4a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256065432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2256065432
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2438293517
Short name T217
Test name
Test status
Simulation time 127149583 ps
CPU time 1.62 seconds
Started May 30 02:18:38 PM PDT 24
Finished May 30 02:18:41 PM PDT 24
Peak memory 200868 kb
Host smart-9472c371-7c6a-4ddc-9a71-59a393cd3f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438293517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2438293517
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2405330172
Short name T322
Test name
Test status
Simulation time 180197720 ps
CPU time 1.34 seconds
Started May 30 02:18:40 PM PDT 24
Finished May 30 02:18:43 PM PDT 24
Peak memory 201064 kb
Host smart-a3e3db56-8ea9-430f-ad7d-02b8071e4dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405330172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2405330172
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.817860792
Short name T341
Test name
Test status
Simulation time 75272071 ps
CPU time 0.77 seconds
Started May 30 02:20:33 PM PDT 24
Finished May 30 02:20:34 PM PDT 24
Peak memory 200708 kb
Host smart-0b52fe26-4fac-4c3d-8ef2-6ac7e9b3afcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817860792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.817860792
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2351289995
Short name T25
Test name
Test status
Simulation time 1235550001 ps
CPU time 5.88 seconds
Started May 30 02:20:36 PM PDT 24
Finished May 30 02:20:42 PM PDT 24
Peak memory 218468 kb
Host smart-d9f09887-4be8-496d-bbc6-b397828d6388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351289995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2351289995
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3401162055
Short name T338
Test name
Test status
Simulation time 243533490 ps
CPU time 1.04 seconds
Started May 30 02:20:35 PM PDT 24
Finished May 30 02:20:37 PM PDT 24
Peak memory 217968 kb
Host smart-71f4726a-aff8-4c28-bd9d-155963d2c50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401162055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3401162055
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2659914449
Short name T183
Test name
Test status
Simulation time 150567713 ps
CPU time 0.88 seconds
Started May 30 02:20:24 PM PDT 24
Finished May 30 02:20:26 PM PDT 24
Peak memory 200680 kb
Host smart-45c9d0e5-4a52-4dcd-92f9-30b0276c0a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659914449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2659914449
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3746847798
Short name T34
Test name
Test status
Simulation time 1806004903 ps
CPU time 6.89 seconds
Started May 30 02:20:34 PM PDT 24
Finished May 30 02:20:42 PM PDT 24
Peak memory 201048 kb
Host smart-71c45a48-1762-4639-a4a4-0005fb9ac771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746847798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3746847798
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2786680089
Short name T165
Test name
Test status
Simulation time 106237748 ps
CPU time 1 seconds
Started May 30 02:20:37 PM PDT 24
Finished May 30 02:20:39 PM PDT 24
Peak memory 200868 kb
Host smart-fdc0b32c-745a-4015-bb2f-a769bcb2aee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786680089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2786680089
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.189639471
Short name T490
Test name
Test status
Simulation time 111580640 ps
CPU time 1.22 seconds
Started May 30 02:20:20 PM PDT 24
Finished May 30 02:20:22 PM PDT 24
Peak memory 201064 kb
Host smart-b2ea6cab-4b72-41e7-816b-73418bd8ee5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189639471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.189639471
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3341306359
Short name T497
Test name
Test status
Simulation time 14193567801 ps
CPU time 49.46 seconds
Started May 30 02:20:35 PM PDT 24
Finished May 30 02:21:25 PM PDT 24
Peak memory 209408 kb
Host smart-c0f6bff7-bd71-4ce2-9eca-801b0d12a632
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341306359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3341306359
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3319772707
Short name T41
Test name
Test status
Simulation time 334735372 ps
CPU time 2.21 seconds
Started May 30 02:20:37 PM PDT 24
Finished May 30 02:20:40 PM PDT 24
Peak memory 200832 kb
Host smart-ed8fa431-f6d2-46a0-80d2-d458a6cd6d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319772707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3319772707
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.457621917
Short name T409
Test name
Test status
Simulation time 187356550 ps
CPU time 1.21 seconds
Started May 30 02:20:35 PM PDT 24
Finished May 30 02:20:37 PM PDT 24
Peak memory 200876 kb
Host smart-58a2a010-96b8-4bcf-95da-f1d55c3cf6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457621917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.457621917
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.4124046531
Short name T189
Test name
Test status
Simulation time 68271763 ps
CPU time 0.8 seconds
Started May 30 02:20:41 PM PDT 24
Finished May 30 02:20:42 PM PDT 24
Peak memory 200720 kb
Host smart-546031ef-972c-46bb-a750-ac0378f75f05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124046531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.4124046531
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2713430433
Short name T521
Test name
Test status
Simulation time 2363874453 ps
CPU time 8.45 seconds
Started May 30 02:20:35 PM PDT 24
Finished May 30 02:20:44 PM PDT 24
Peak memory 218380 kb
Host smart-fe1906ff-bbaa-4b88-831c-5be02bff4d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713430433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2713430433
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.178626237
Short name T131
Test name
Test status
Simulation time 243706244 ps
CPU time 1.02 seconds
Started May 30 02:20:34 PM PDT 24
Finished May 30 02:20:36 PM PDT 24
Peak memory 218036 kb
Host smart-836bbd0e-1d9d-43cb-a884-9456fdf6172c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178626237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.178626237
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3634488345
Short name T479
Test name
Test status
Simulation time 124151465 ps
CPU time 0.84 seconds
Started May 30 02:20:38 PM PDT 24
Finished May 30 02:20:40 PM PDT 24
Peak memory 200632 kb
Host smart-fd369456-b2e7-40ab-a904-e95493307efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634488345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3634488345
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.2608455045
Short name T397
Test name
Test status
Simulation time 1743249802 ps
CPU time 6.83 seconds
Started May 30 02:20:36 PM PDT 24
Finished May 30 02:20:43 PM PDT 24
Peak memory 201064 kb
Host smart-1c1ac980-cf9d-4d2b-aac5-cf49060abc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608455045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2608455045
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.4005952749
Short name T532
Test name
Test status
Simulation time 152116776 ps
CPU time 1.2 seconds
Started May 30 02:20:42 PM PDT 24
Finished May 30 02:20:44 PM PDT 24
Peak memory 200868 kb
Host smart-ae9ba80a-7571-4e17-b33c-6f64da8bdf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005952749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.4005952749
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2659651412
Short name T66
Test name
Test status
Simulation time 123119272 ps
CPU time 1.18 seconds
Started May 30 02:20:35 PM PDT 24
Finished May 30 02:20:37 PM PDT 24
Peak memory 201036 kb
Host smart-8dc79dff-298b-4c8a-a420-a8f43c9122e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659651412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2659651412
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2425242270
Short name T433
Test name
Test status
Simulation time 10443191775 ps
CPU time 35.58 seconds
Started May 30 02:20:41 PM PDT 24
Finished May 30 02:21:17 PM PDT 24
Peak memory 209412 kb
Host smart-b93ca484-2f84-4304-bb0c-61790e488af4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425242270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2425242270
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3326072530
Short name T535
Test name
Test status
Simulation time 338494027 ps
CPU time 2.16 seconds
Started May 30 02:20:35 PM PDT 24
Finished May 30 02:20:38 PM PDT 24
Peak memory 200872 kb
Host smart-5d0a474d-a281-4914-aa1e-c9b0e03bc984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326072530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3326072530
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3153250694
Short name T520
Test name
Test status
Simulation time 119283057 ps
CPU time 1.03 seconds
Started May 30 02:20:38 PM PDT 24
Finished May 30 02:20:39 PM PDT 24
Peak memory 200812 kb
Host smart-5f5c8b0d-3aa9-42a1-b9e7-1bbdded91f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153250694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3153250694
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3551113346
Short name T145
Test name
Test status
Simulation time 70566933 ps
CPU time 0.78 seconds
Started May 30 02:20:50 PM PDT 24
Finished May 30 02:20:51 PM PDT 24
Peak memory 200660 kb
Host smart-8ff88796-e779-4b4c-998d-42acf6a65c79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551113346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3551113346
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.287386047
Short name T436
Test name
Test status
Simulation time 1888547660 ps
CPU time 7.78 seconds
Started May 30 02:20:48 PM PDT 24
Finished May 30 02:20:56 PM PDT 24
Peak memory 217980 kb
Host smart-a5f9abb5-6212-4649-b013-e1a9479dbc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287386047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.287386047
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1286048385
Short name T355
Test name
Test status
Simulation time 243117511 ps
CPU time 1.09 seconds
Started May 30 02:20:47 PM PDT 24
Finished May 30 02:20:49 PM PDT 24
Peak memory 218012 kb
Host smart-62c28e28-9bf3-407e-ae4a-93e9404f4284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286048385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1286048385
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2344056819
Short name T513
Test name
Test status
Simulation time 107443114 ps
CPU time 0.82 seconds
Started May 30 02:20:35 PM PDT 24
Finished May 30 02:20:36 PM PDT 24
Peak memory 200700 kb
Host smart-15a84ebd-700d-472e-8ff3-8ccd930a8b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344056819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2344056819
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1181273313
Short name T92
Test name
Test status
Simulation time 1786121289 ps
CPU time 6.72 seconds
Started May 30 02:20:42 PM PDT 24
Finished May 30 02:20:50 PM PDT 24
Peak memory 201048 kb
Host smart-be014046-e3e1-479b-873a-c8fdf037ce04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181273313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1181273313
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3299469346
Short name T529
Test name
Test status
Simulation time 109997955 ps
CPU time 1.05 seconds
Started May 30 02:20:35 PM PDT 24
Finished May 30 02:20:37 PM PDT 24
Peak memory 200828 kb
Host smart-1cd1b477-cae2-4a4d-b790-919c0e44ff04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299469346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3299469346
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2505614240
Short name T185
Test name
Test status
Simulation time 199366417 ps
CPU time 1.52 seconds
Started May 30 02:20:33 PM PDT 24
Finished May 30 02:20:35 PM PDT 24
Peak memory 201048 kb
Host smart-55058063-e58a-473f-b140-2df07a09688e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505614240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2505614240
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1997325716
Short name T470
Test name
Test status
Simulation time 9187895917 ps
CPU time 37.17 seconds
Started May 30 02:20:49 PM PDT 24
Finished May 30 02:21:27 PM PDT 24
Peak memory 210348 kb
Host smart-943a1648-e197-4c73-82ea-be4a1e6a23a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997325716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1997325716
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2938041342
Short name T280
Test name
Test status
Simulation time 140406332 ps
CPU time 2 seconds
Started May 30 02:20:34 PM PDT 24
Finished May 30 02:20:36 PM PDT 24
Peak memory 200856 kb
Host smart-6476449a-4d61-4f90-bd77-1eefb3c0fe97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938041342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2938041342
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2119593923
Short name T310
Test name
Test status
Simulation time 211453234 ps
CPU time 1.43 seconds
Started May 30 02:20:37 PM PDT 24
Finished May 30 02:20:39 PM PDT 24
Peak memory 200876 kb
Host smart-141dceab-380d-4e7e-84c7-0a5a1522997d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119593923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2119593923
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1365595002
Short name T512
Test name
Test status
Simulation time 2355010313 ps
CPU time 8.84 seconds
Started May 30 02:20:50 PM PDT 24
Finished May 30 02:21:00 PM PDT 24
Peak memory 218356 kb
Host smart-a2a2cd34-87f1-48b8-a85e-357af02dec81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365595002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1365595002
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3222869845
Short name T517
Test name
Test status
Simulation time 244239616 ps
CPU time 1.09 seconds
Started May 30 02:20:49 PM PDT 24
Finished May 30 02:20:51 PM PDT 24
Peak memory 218064 kb
Host smart-bc9520f4-e278-41b2-805b-8a1875cbf284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222869845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3222869845
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1319492780
Short name T239
Test name
Test status
Simulation time 91647281 ps
CPU time 0.75 seconds
Started May 30 02:20:54 PM PDT 24
Finished May 30 02:20:55 PM PDT 24
Peak memory 200700 kb
Host smart-99636cda-5d33-4307-bb0b-a23ada5feac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319492780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1319492780
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.558609709
Short name T90
Test name
Test status
Simulation time 1989002435 ps
CPU time 7.51 seconds
Started May 30 02:20:48 PM PDT 24
Finished May 30 02:20:56 PM PDT 24
Peak memory 201040 kb
Host smart-1ceb0216-2421-485e-b922-abbe2112f9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558609709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.558609709
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.4250469066
Short name T281
Test name
Test status
Simulation time 100246217 ps
CPU time 0.99 seconds
Started May 30 02:20:47 PM PDT 24
Finished May 30 02:20:48 PM PDT 24
Peak memory 200820 kb
Host smart-c59457bf-cddc-4351-b319-34bf67748232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250469066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.4250469066
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.115981604
Short name T130
Test name
Test status
Simulation time 126457626 ps
CPU time 1.24 seconds
Started May 30 02:20:48 PM PDT 24
Finished May 30 02:20:50 PM PDT 24
Peak memory 201040 kb
Host smart-a52fcc5f-156c-4baa-882b-946fc8977d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115981604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.115981604
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.1296926626
Short name T327
Test name
Test status
Simulation time 5255656734 ps
CPU time 21.55 seconds
Started May 30 02:20:50 PM PDT 24
Finished May 30 02:21:12 PM PDT 24
Peak memory 201244 kb
Host smart-41337013-0f75-42e0-84c1-072fac7b606d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296926626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1296926626
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2719736633
Short name T368
Test name
Test status
Simulation time 359326689 ps
CPU time 2.25 seconds
Started May 30 02:20:46 PM PDT 24
Finished May 30 02:20:49 PM PDT 24
Peak memory 200756 kb
Host smart-e84d78b3-33b9-40b2-97b0-9685b1d52aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719736633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2719736633
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.740428519
Short name T251
Test name
Test status
Simulation time 69288004 ps
CPU time 0.78 seconds
Started May 30 02:20:48 PM PDT 24
Finished May 30 02:20:50 PM PDT 24
Peak memory 200852 kb
Host smart-34fc09fe-3616-4663-ad89-7fe9b0476b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740428519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.740428519
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2158044904
Short name T149
Test name
Test status
Simulation time 72121357 ps
CPU time 0.81 seconds
Started May 30 02:20:47 PM PDT 24
Finished May 30 02:20:48 PM PDT 24
Peak memory 200672 kb
Host smart-d8e58796-175f-44ec-b5e3-04b957f23dee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158044904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2158044904
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.4080098302
Short name T410
Test name
Test status
Simulation time 1891763789 ps
CPU time 6.85 seconds
Started May 30 02:20:49 PM PDT 24
Finished May 30 02:20:57 PM PDT 24
Peak memory 218520 kb
Host smart-4a6a7454-0ea7-4c29-88e8-b7122837a0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080098302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.4080098302
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.976274305
Short name T461
Test name
Test status
Simulation time 243739749 ps
CPU time 1.1 seconds
Started May 30 02:20:50 PM PDT 24
Finished May 30 02:20:52 PM PDT 24
Peak memory 218200 kb
Host smart-c1c6014b-3a6d-4811-87a1-9e201b06ebf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976274305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.976274305
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3889753318
Short name T194
Test name
Test status
Simulation time 197699305 ps
CPU time 0.97 seconds
Started May 30 02:20:46 PM PDT 24
Finished May 30 02:20:48 PM PDT 24
Peak memory 200696 kb
Host smart-aee6744d-9e07-420d-9a44-bba496fae027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889753318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3889753318
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.1316040689
Short name T494
Test name
Test status
Simulation time 1835220110 ps
CPU time 7.15 seconds
Started May 30 02:20:49 PM PDT 24
Finished May 30 02:20:57 PM PDT 24
Peak memory 201064 kb
Host smart-ad405801-9549-434d-a250-1fba3ed21f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316040689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1316040689
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.568772006
Short name T187
Test name
Test status
Simulation time 154655638 ps
CPU time 1.17 seconds
Started May 30 02:20:55 PM PDT 24
Finished May 30 02:20:56 PM PDT 24
Peak memory 200912 kb
Host smart-9d567eb0-ebb0-41ba-a8b4-22e4d04f870e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568772006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.568772006
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.4111282603
Short name T52
Test name
Test status
Simulation time 124321537 ps
CPU time 1.27 seconds
Started May 30 02:20:50 PM PDT 24
Finished May 30 02:20:53 PM PDT 24
Peak memory 201068 kb
Host smart-abecfe3e-4642-46e7-aa22-cd6381b42dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111282603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.4111282603
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3091209683
Short name T257
Test name
Test status
Simulation time 1332450754 ps
CPU time 6.79 seconds
Started May 30 02:20:50 PM PDT 24
Finished May 30 02:20:57 PM PDT 24
Peak memory 210352 kb
Host smart-3ac13723-1e15-44b9-bfd7-dd72c63e4a8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091209683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3091209683
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1178850704
Short name T181
Test name
Test status
Simulation time 164872349 ps
CPU time 1.21 seconds
Started May 30 02:20:46 PM PDT 24
Finished May 30 02:20:48 PM PDT 24
Peak memory 200868 kb
Host smart-7a161d80-1ec1-4f3d-9289-0bdb7168478f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178850704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1178850704
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3111992055
Short name T377
Test name
Test status
Simulation time 64413319 ps
CPU time 0.77 seconds
Started May 30 02:21:01 PM PDT 24
Finished May 30 02:21:02 PM PDT 24
Peak memory 200728 kb
Host smart-24548eb8-b93f-4727-9c64-2abb7270eadf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111992055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3111992055
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.411297739
Short name T44
Test name
Test status
Simulation time 1887801696 ps
CPU time 7.55 seconds
Started May 30 02:21:08 PM PDT 24
Finished May 30 02:21:16 PM PDT 24
Peak memory 222488 kb
Host smart-03c8c0bc-ea27-4d03-88be-608358a316e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411297739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.411297739
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2567424683
Short name T468
Test name
Test status
Simulation time 244356579 ps
CPU time 1.11 seconds
Started May 30 02:21:00 PM PDT 24
Finished May 30 02:21:02 PM PDT 24
Peak memory 218040 kb
Host smart-e1abbfd1-ff25-495c-9503-d6583bc55c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567424683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2567424683
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.2398826913
Short name T291
Test name
Test status
Simulation time 101124560 ps
CPU time 0.78 seconds
Started May 30 02:20:51 PM PDT 24
Finished May 30 02:20:53 PM PDT 24
Peak memory 200632 kb
Host smart-f88480e8-cdc5-4c3c-a833-8cd046d4dd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398826913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2398826913
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2080444564
Short name T160
Test name
Test status
Simulation time 1731548235 ps
CPU time 5.85 seconds
Started May 30 02:20:48 PM PDT 24
Finished May 30 02:20:55 PM PDT 24
Peak memory 201024 kb
Host smart-4472c968-e3f5-42c4-8aaf-c2fdd2a96ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080444564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2080444564
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3463394336
Short name T243
Test name
Test status
Simulation time 101068589 ps
CPU time 1.02 seconds
Started May 30 02:21:01 PM PDT 24
Finished May 30 02:21:02 PM PDT 24
Peak memory 200848 kb
Host smart-b2bf32bc-cc1e-4444-82d9-aa0b2a2d2fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463394336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3463394336
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.1146986040
Short name T20
Test name
Test status
Simulation time 118238887 ps
CPU time 1.16 seconds
Started May 30 02:20:50 PM PDT 24
Finished May 30 02:20:52 PM PDT 24
Peak memory 200996 kb
Host smart-f18d7e0e-e8db-45e5-b652-c01ad25ad26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146986040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1146986040
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2082436368
Short name T488
Test name
Test status
Simulation time 3703069118 ps
CPU time 18.61 seconds
Started May 30 02:21:00 PM PDT 24
Finished May 30 02:21:20 PM PDT 24
Peak memory 201208 kb
Host smart-c744539b-c9ec-48a4-9ecc-ed4933a8cd16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082436368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2082436368
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1366084763
Short name T139
Test name
Test status
Simulation time 314366080 ps
CPU time 2.13 seconds
Started May 30 02:21:08 PM PDT 24
Finished May 30 02:21:11 PM PDT 24
Peak memory 200836 kb
Host smart-c6640e4f-d8f9-46e9-8179-61dc4cba33c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366084763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1366084763
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.714822830
Short name T159
Test name
Test status
Simulation time 88565972 ps
CPU time 0.95 seconds
Started May 30 02:21:08 PM PDT 24
Finished May 30 02:21:10 PM PDT 24
Peak memory 200844 kb
Host smart-6a250a23-728f-466e-9dfe-e9a1ab29ca1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714822830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.714822830
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1552610455
Short name T1
Test name
Test status
Simulation time 68372579 ps
CPU time 0.78 seconds
Started May 30 02:21:01 PM PDT 24
Finished May 30 02:21:03 PM PDT 24
Peak memory 200692 kb
Host smart-9146f1b2-c08a-44e8-9d83-1541ab742cdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552610455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1552610455
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1719223541
Short name T304
Test name
Test status
Simulation time 2173540711 ps
CPU time 8.75 seconds
Started May 30 02:21:01 PM PDT 24
Finished May 30 02:21:11 PM PDT 24
Peak memory 218084 kb
Host smart-5ff3b10a-47be-47d4-85eb-5fbe8fe14ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719223541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1719223541
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3191825703
Short name T162
Test name
Test status
Simulation time 244439842 ps
CPU time 1.24 seconds
Started May 30 02:21:02 PM PDT 24
Finished May 30 02:21:04 PM PDT 24
Peak memory 217956 kb
Host smart-43f78a68-0143-490e-8776-cc2df795b912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191825703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3191825703
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2118176835
Short name T481
Test name
Test status
Simulation time 221653130 ps
CPU time 0.92 seconds
Started May 30 02:20:59 PM PDT 24
Finished May 30 02:21:01 PM PDT 24
Peak memory 200660 kb
Host smart-b27851e9-fe29-4dd1-9a6a-0928ca689699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118176835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2118176835
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1154201617
Short name T285
Test name
Test status
Simulation time 974654969 ps
CPU time 4.9 seconds
Started May 30 02:21:03 PM PDT 24
Finished May 30 02:21:09 PM PDT 24
Peak memory 201080 kb
Host smart-95388b4f-3670-486a-afa3-0cd40e9fc595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154201617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1154201617
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1406610134
Short name T65
Test name
Test status
Simulation time 103398190 ps
CPU time 1.11 seconds
Started May 30 02:21:01 PM PDT 24
Finished May 30 02:21:04 PM PDT 24
Peak memory 200868 kb
Host smart-4e86111a-2433-4b69-a554-b7b60661cb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406610134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1406610134
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.759735256
Short name T357
Test name
Test status
Simulation time 235998195 ps
CPU time 1.48 seconds
Started May 30 02:21:03 PM PDT 24
Finished May 30 02:21:05 PM PDT 24
Peak memory 201072 kb
Host smart-a7449608-6eaa-45a2-ad97-df84b0c9a40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759735256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.759735256
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.4050665440
Short name T404
Test name
Test status
Simulation time 5506199483 ps
CPU time 23.6 seconds
Started May 30 02:21:03 PM PDT 24
Finished May 30 02:21:28 PM PDT 24
Peak memory 210148 kb
Host smart-d9d617cf-0f48-447e-9621-3142e83cff3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050665440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.4050665440
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2806162767
Short name T274
Test name
Test status
Simulation time 413831654 ps
CPU time 2.57 seconds
Started May 30 02:21:00 PM PDT 24
Finished May 30 02:21:03 PM PDT 24
Peak memory 200856 kb
Host smart-030e3ac8-83d1-45b4-a5f4-2f2c5630a696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806162767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2806162767
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.4056623975
Short name T133
Test name
Test status
Simulation time 109038457 ps
CPU time 1.02 seconds
Started May 30 02:21:01 PM PDT 24
Finished May 30 02:21:03 PM PDT 24
Peak memory 200896 kb
Host smart-4abc0ea7-8c23-4cfe-9898-5004630cf742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056623975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.4056623975
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1379526557
Short name T317
Test name
Test status
Simulation time 93147490 ps
CPU time 0.87 seconds
Started May 30 02:21:13 PM PDT 24
Finished May 30 02:21:14 PM PDT 24
Peak memory 200724 kb
Host smart-b3eccb59-6d23-4227-8122-33a2168bcb7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379526557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1379526557
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.4279549610
Short name T467
Test name
Test status
Simulation time 1214170424 ps
CPU time 6.44 seconds
Started May 30 02:21:02 PM PDT 24
Finished May 30 02:21:09 PM PDT 24
Peak memory 222560 kb
Host smart-0f522f8b-8a5a-4a6a-9d1c-e019a9b18e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279549610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.4279549610
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3953341508
Short name T74
Test name
Test status
Simulation time 243484015 ps
CPU time 1.14 seconds
Started May 30 02:21:08 PM PDT 24
Finished May 30 02:21:10 PM PDT 24
Peak memory 217996 kb
Host smart-95cb3bcd-8eb1-41d5-adbc-b15e4dc51b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953341508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3953341508
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2295371642
Short name T256
Test name
Test status
Simulation time 130577551 ps
CPU time 0.85 seconds
Started May 30 02:21:02 PM PDT 24
Finished May 30 02:21:04 PM PDT 24
Peak memory 200692 kb
Host smart-a90f0272-0a94-4902-9769-40d529bd1522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295371642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2295371642
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.761517201
Short name T95
Test name
Test status
Simulation time 1600331328 ps
CPU time 6.07 seconds
Started May 30 02:21:02 PM PDT 24
Finished May 30 02:21:09 PM PDT 24
Peak memory 201052 kb
Host smart-5f993b3e-f4ec-469c-922e-d4a0b2e73ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761517201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.761517201
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3338215761
Short name T70
Test name
Test status
Simulation time 99863010 ps
CPU time 1.13 seconds
Started May 30 02:21:00 PM PDT 24
Finished May 30 02:21:02 PM PDT 24
Peak memory 200868 kb
Host smart-a178ba2c-ca1e-472d-bd15-5b203e53cf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338215761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3338215761
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2048345835
Short name T523
Test name
Test status
Simulation time 254905010 ps
CPU time 1.55 seconds
Started May 30 02:21:03 PM PDT 24
Finished May 30 02:21:05 PM PDT 24
Peak memory 201072 kb
Host smart-5e3b4bcc-f768-4349-8d28-18bc01e1c215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048345835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2048345835
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2231633265
Short name T441
Test name
Test status
Simulation time 13270094510 ps
CPU time 48.31 seconds
Started May 30 02:20:59 PM PDT 24
Finished May 30 02:21:48 PM PDT 24
Peak memory 209404 kb
Host smart-f0b9b731-4574-4afc-89df-a92a64418b86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231633265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2231633265
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.832425464
Short name T265
Test name
Test status
Simulation time 137620925 ps
CPU time 1.63 seconds
Started May 30 02:21:01 PM PDT 24
Finished May 30 02:21:03 PM PDT 24
Peak memory 209096 kb
Host smart-45d46be0-4c7d-4a21-a955-76146176bd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832425464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.832425464
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2322642945
Short name T42
Test name
Test status
Simulation time 175065760 ps
CPU time 1.2 seconds
Started May 30 02:21:03 PM PDT 24
Finished May 30 02:21:05 PM PDT 24
Peak memory 200888 kb
Host smart-33d4e318-e589-4114-b8d8-4b3ed21f6b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322642945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2322642945
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3346554423
Short name T264
Test name
Test status
Simulation time 93951065 ps
CPU time 0.89 seconds
Started May 30 02:21:12 PM PDT 24
Finished May 30 02:21:13 PM PDT 24
Peak memory 200692 kb
Host smart-145c1f11-2b0c-42f2-a8ba-adb00a2dada1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346554423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3346554423
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.68793413
Short name T373
Test name
Test status
Simulation time 2192047732 ps
CPU time 8.96 seconds
Started May 30 02:21:14 PM PDT 24
Finished May 30 02:21:24 PM PDT 24
Peak memory 222632 kb
Host smart-fc8da537-1c4e-4349-ab7b-8a232fa24310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68793413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.68793413
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1809509113
Short name T301
Test name
Test status
Simulation time 244153012 ps
CPU time 1.18 seconds
Started May 30 02:21:13 PM PDT 24
Finished May 30 02:21:15 PM PDT 24
Peak memory 218020 kb
Host smart-7bb67d40-cace-4ca5-880c-11bce4a54336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809509113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1809509113
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2974932934
Short name T510
Test name
Test status
Simulation time 160235528 ps
CPU time 0.9 seconds
Started May 30 02:21:13 PM PDT 24
Finished May 30 02:21:15 PM PDT 24
Peak memory 200680 kb
Host smart-bb8a4fca-2ae3-4957-b749-84c321010067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974932934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2974932934
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.67865773
Short name T214
Test name
Test status
Simulation time 887253511 ps
CPU time 4.37 seconds
Started May 30 02:21:16 PM PDT 24
Finished May 30 02:21:21 PM PDT 24
Peak memory 201132 kb
Host smart-98b4c237-428a-47e1-8d1c-9cec93e533ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67865773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.67865773
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2839777356
Short name T502
Test name
Test status
Simulation time 171447222 ps
CPU time 1.19 seconds
Started May 30 02:21:14 PM PDT 24
Finished May 30 02:21:16 PM PDT 24
Peak memory 200844 kb
Host smart-a9cc985d-324b-4f14-b761-575d0fb0f1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839777356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2839777356
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1971931523
Short name T157
Test name
Test status
Simulation time 106364591 ps
CPU time 1.32 seconds
Started May 30 02:21:14 PM PDT 24
Finished May 30 02:21:16 PM PDT 24
Peak memory 201136 kb
Host smart-b1827355-fe84-4873-9a8f-cfaedf09440d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971931523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1971931523
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3608530054
Short name T202
Test name
Test status
Simulation time 224734898 ps
CPU time 1.28 seconds
Started May 30 02:21:14 PM PDT 24
Finished May 30 02:21:16 PM PDT 24
Peak memory 200884 kb
Host smart-8b4adc56-e384-4ef9-8667-efd9567b5514
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608530054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3608530054
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1789013164
Short name T499
Test name
Test status
Simulation time 518568266 ps
CPU time 2.91 seconds
Started May 30 02:21:15 PM PDT 24
Finished May 30 02:21:19 PM PDT 24
Peak memory 200804 kb
Host smart-9a6f283a-4f25-4301-8355-4cc73a591bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789013164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1789013164
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.767138455
Short name T336
Test name
Test status
Simulation time 222773364 ps
CPU time 1.37 seconds
Started May 30 02:21:22 PM PDT 24
Finished May 30 02:21:24 PM PDT 24
Peak memory 200824 kb
Host smart-a4ced8bf-6668-47c2-b3af-b20168374aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767138455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.767138455
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.2015933133
Short name T498
Test name
Test status
Simulation time 67239678 ps
CPU time 0.79 seconds
Started May 30 02:21:12 PM PDT 24
Finished May 30 02:21:14 PM PDT 24
Peak memory 200704 kb
Host smart-09ac055e-7f58-4569-bbad-cb1d613df23b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015933133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2015933133
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1535653106
Short name T28
Test name
Test status
Simulation time 2350459453 ps
CPU time 8.02 seconds
Started May 30 02:21:13 PM PDT 24
Finished May 30 02:21:21 PM PDT 24
Peak memory 222668 kb
Host smart-613849a9-2758-417c-8fe0-88c6247504ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535653106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1535653106
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2300285728
Short name T399
Test name
Test status
Simulation time 243453622 ps
CPU time 1.14 seconds
Started May 30 02:21:15 PM PDT 24
Finished May 30 02:21:17 PM PDT 24
Peak memory 218000 kb
Host smart-f2f75503-85dc-428c-8499-b61c7c95d573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300285728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2300285728
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.302474745
Short name T16
Test name
Test status
Simulation time 70241701 ps
CPU time 0.78 seconds
Started May 30 02:21:22 PM PDT 24
Finished May 30 02:21:23 PM PDT 24
Peak memory 200632 kb
Host smart-92920a8e-f846-48bc-b09b-d0c5da7c0db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302474745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.302474745
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3728402325
Short name T515
Test name
Test status
Simulation time 1722203233 ps
CPU time 6.37 seconds
Started May 30 02:21:13 PM PDT 24
Finished May 30 02:21:21 PM PDT 24
Peak memory 201064 kb
Host smart-3611fb35-6f9e-48c0-9e24-e7b49129cb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728402325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3728402325
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3453991806
Short name T286
Test name
Test status
Simulation time 165695531 ps
CPU time 1.26 seconds
Started May 30 02:21:15 PM PDT 24
Finished May 30 02:21:17 PM PDT 24
Peak memory 200768 kb
Host smart-dabf40a4-aea7-4962-a8f4-7aeaaaf7d047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453991806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3453991806
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3009718355
Short name T221
Test name
Test status
Simulation time 113286659 ps
CPU time 1.2 seconds
Started May 30 02:21:13 PM PDT 24
Finished May 30 02:21:15 PM PDT 24
Peak memory 201064 kb
Host smart-a49d8d4d-ef4c-46d6-8f95-16dcea2f4fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009718355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3009718355
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3733957686
Short name T174
Test name
Test status
Simulation time 3097381080 ps
CPU time 13.88 seconds
Started May 30 02:21:22 PM PDT 24
Finished May 30 02:21:36 PM PDT 24
Peak memory 201184 kb
Host smart-94201bde-d3a6-4c69-b057-5113a7c8eeff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733957686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3733957686
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.4204197675
Short name T245
Test name
Test status
Simulation time 142157012 ps
CPU time 1.75 seconds
Started May 30 02:21:14 PM PDT 24
Finished May 30 02:21:17 PM PDT 24
Peak memory 200832 kb
Host smart-b6282e2e-9267-41e2-9a80-6aa138ae87d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204197675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.4204197675
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.686612831
Short name T405
Test name
Test status
Simulation time 271834258 ps
CPU time 1.59 seconds
Started May 30 02:21:12 PM PDT 24
Finished May 30 02:21:14 PM PDT 24
Peak memory 200860 kb
Host smart-a55b9468-137d-426e-8338-24e4b4ee48e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686612831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.686612831
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1715432539
Short name T60
Test name
Test status
Simulation time 72952299 ps
CPU time 0.78 seconds
Started May 30 02:18:53 PM PDT 24
Finished May 30 02:18:55 PM PDT 24
Peak memory 200676 kb
Host smart-6b5b2f97-8712-4864-b965-838382497235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715432539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1715432539
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1710015855
Short name T45
Test name
Test status
Simulation time 1896501070 ps
CPU time 8 seconds
Started May 30 02:18:42 PM PDT 24
Finished May 30 02:18:52 PM PDT 24
Peak memory 218472 kb
Host smart-ff984f1c-1f36-4514-8fde-e321cd174eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710015855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1710015855
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1334383322
Short name T439
Test name
Test status
Simulation time 243814441 ps
CPU time 1.11 seconds
Started May 30 02:18:50 PM PDT 24
Finished May 30 02:18:52 PM PDT 24
Peak memory 218004 kb
Host smart-868ed5b3-cc24-41cb-a02e-acae612081a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334383322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1334383322
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3512753591
Short name T3
Test name
Test status
Simulation time 193653431 ps
CPU time 0.91 seconds
Started May 30 02:18:55 PM PDT 24
Finished May 30 02:18:57 PM PDT 24
Peak memory 200628 kb
Host smart-7b18c4b5-cc72-48e8-b242-47d2b3b3fe50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512753591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3512753591
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3410390771
Short name T116
Test name
Test status
Simulation time 2029173950 ps
CPU time 7.97 seconds
Started May 30 02:18:50 PM PDT 24
Finished May 30 02:18:59 PM PDT 24
Peak memory 201044 kb
Host smart-acf478c4-3570-4245-a319-5e95d1a74783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410390771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3410390771
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.876806124
Short name T61
Test name
Test status
Simulation time 16679172066 ps
CPU time 24.44 seconds
Started May 30 02:18:54 PM PDT 24
Finished May 30 02:19:20 PM PDT 24
Peak memory 217952 kb
Host smart-5260b0fd-a69c-4892-bef0-19a5af3b0b68
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876806124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.876806124
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3436970948
Short name T533
Test name
Test status
Simulation time 144188626 ps
CPU time 1.13 seconds
Started May 30 02:18:54 PM PDT 24
Finished May 30 02:18:56 PM PDT 24
Peak memory 200864 kb
Host smart-45dc2996-0d35-4d87-8c16-c6ec5290447a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436970948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3436970948
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.839614191
Short name T418
Test name
Test status
Simulation time 123249684 ps
CPU time 1.25 seconds
Started May 30 02:18:41 PM PDT 24
Finished May 30 02:18:44 PM PDT 24
Peak memory 200972 kb
Host smart-585abd3b-57ff-4f8d-ad9c-301d366f10a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839614191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.839614191
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1065275803
Short name T188
Test name
Test status
Simulation time 2416007180 ps
CPU time 9.35 seconds
Started May 30 02:18:50 PM PDT 24
Finished May 30 02:19:01 PM PDT 24
Peak memory 201188 kb
Host smart-eb8b797b-0551-4dcc-8631-6b8d28c16de5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065275803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1065275803
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1862102718
Short name T154
Test name
Test status
Simulation time 120580886 ps
CPU time 1.53 seconds
Started May 30 02:18:54 PM PDT 24
Finished May 30 02:18:57 PM PDT 24
Peak memory 200836 kb
Host smart-fdbdefe4-6f9a-4033-85c2-d142baac85f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862102718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1862102718
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.1428993141
Short name T316
Test name
Test status
Simulation time 128824359 ps
CPU time 1.06 seconds
Started May 30 02:18:54 PM PDT 24
Finished May 30 02:18:56 PM PDT 24
Peak memory 200864 kb
Host smart-07c0dc99-7b93-4d7d-a034-e7215ed2346b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428993141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1428993141
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.2999396777
Short name T204
Test name
Test status
Simulation time 78275931 ps
CPU time 0.81 seconds
Started May 30 02:21:28 PM PDT 24
Finished May 30 02:21:30 PM PDT 24
Peak memory 200716 kb
Host smart-29708e77-c5e0-48b7-ab96-e8efed0694ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999396777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.2999396777
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.430932418
Short name T392
Test name
Test status
Simulation time 1223293074 ps
CPU time 6.13 seconds
Started May 30 02:21:31 PM PDT 24
Finished May 30 02:21:37 PM PDT 24
Peak memory 218532 kb
Host smart-21ef8f53-f305-4ec0-ba39-35e804bd495f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430932418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.430932418
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2998117986
Short name T340
Test name
Test status
Simulation time 243790126 ps
CPU time 1.09 seconds
Started May 30 02:21:29 PM PDT 24
Finished May 30 02:21:31 PM PDT 24
Peak memory 218028 kb
Host smart-17303c49-224d-4a80-8ebd-c224dbd48184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998117986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2998117986
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2768211980
Short name T315
Test name
Test status
Simulation time 203695973 ps
CPU time 0.93 seconds
Started May 30 02:21:14 PM PDT 24
Finished May 30 02:21:16 PM PDT 24
Peak memory 200584 kb
Host smart-e2ed95b6-fe9f-4ec1-bdfb-0b45c97c7a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768211980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2768211980
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.192618858
Short name T91
Test name
Test status
Simulation time 771249292 ps
CPU time 4.03 seconds
Started May 30 02:21:23 PM PDT 24
Finished May 30 02:21:27 PM PDT 24
Peak memory 201060 kb
Host smart-17c06731-73c9-4ea7-bb13-4484e13e23dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192618858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.192618858
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3032031562
Short name T484
Test name
Test status
Simulation time 98194725 ps
CPU time 1.01 seconds
Started May 30 02:21:29 PM PDT 24
Finished May 30 02:21:31 PM PDT 24
Peak memory 200948 kb
Host smart-cfb7fa6f-a2d6-4452-9e43-2cbdf2df6081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032031562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3032031562
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2274021517
Short name T516
Test name
Test status
Simulation time 122148422 ps
CPU time 1.27 seconds
Started May 30 02:21:13 PM PDT 24
Finished May 30 02:21:15 PM PDT 24
Peak memory 201064 kb
Host smart-82e0f606-4cc6-444a-bd7c-bbf98df2f2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274021517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2274021517
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2331566196
Short name T75
Test name
Test status
Simulation time 3169841177 ps
CPU time 11.88 seconds
Started May 30 02:21:33 PM PDT 24
Finished May 30 02:21:45 PM PDT 24
Peak memory 201256 kb
Host smart-9092b97e-f449-4c0e-bd6e-06720296aa1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331566196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2331566196
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.103912242
Short name T453
Test name
Test status
Simulation time 150739883 ps
CPU time 1.96 seconds
Started May 30 02:21:23 PM PDT 24
Finished May 30 02:21:25 PM PDT 24
Peak memory 200808 kb
Host smart-a8b387e9-1664-4dd4-bff2-5c3ed0743624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103912242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.103912242
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3495116305
Short name T384
Test name
Test status
Simulation time 75370319 ps
CPU time 0.78 seconds
Started May 30 02:21:25 PM PDT 24
Finished May 30 02:21:27 PM PDT 24
Peak memory 200856 kb
Host smart-b6bc8331-0103-4f74-b61a-6874dcfbb381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495116305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3495116305
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.949791304
Short name T349
Test name
Test status
Simulation time 69818143 ps
CPU time 0.81 seconds
Started May 30 02:21:30 PM PDT 24
Finished May 30 02:21:31 PM PDT 24
Peak memory 200720 kb
Host smart-f4406eaf-dc48-48a0-971b-41b9f22e2974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949791304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.949791304
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1861322379
Short name T27
Test name
Test status
Simulation time 1221627886 ps
CPU time 5.52 seconds
Started May 30 02:21:30 PM PDT 24
Finished May 30 02:21:36 PM PDT 24
Peak memory 217464 kb
Host smart-d5134b84-8db2-4f9a-a48d-b6ad3a550638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861322379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1861322379
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1914606470
Short name T232
Test name
Test status
Simulation time 243446600 ps
CPU time 1.12 seconds
Started May 30 02:21:31 PM PDT 24
Finished May 30 02:21:33 PM PDT 24
Peak memory 218008 kb
Host smart-c00dbf84-4b37-44e5-bbd9-67e58b032a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914606470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1914606470
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.2493150700
Short name T414
Test name
Test status
Simulation time 150078256 ps
CPU time 0.83 seconds
Started May 30 02:21:35 PM PDT 24
Finished May 30 02:21:37 PM PDT 24
Peak memory 200700 kb
Host smart-3b667cf4-3c2a-4330-ada3-f14a9685c953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493150700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2493150700
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3305396952
Short name T288
Test name
Test status
Simulation time 1690499163 ps
CPU time 6.52 seconds
Started May 30 02:21:31 PM PDT 24
Finished May 30 02:21:38 PM PDT 24
Peak memory 201008 kb
Host smart-afe0f83f-5daf-435f-8359-577d67787d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305396952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3305396952
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2586284394
Short name T144
Test name
Test status
Simulation time 144281296 ps
CPU time 1.19 seconds
Started May 30 02:21:23 PM PDT 24
Finished May 30 02:21:25 PM PDT 24
Peak memory 200884 kb
Host smart-2d4c267c-03ef-4876-81b7-236971ee8802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586284394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2586284394
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3412556824
Short name T272
Test name
Test status
Simulation time 129789858 ps
CPU time 1.14 seconds
Started May 30 02:21:29 PM PDT 24
Finished May 30 02:21:31 PM PDT 24
Peak memory 201044 kb
Host smart-ef602b4f-a056-4057-8005-d9f1fc70a9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412556824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3412556824
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2894598400
Short name T228
Test name
Test status
Simulation time 6139903642 ps
CPU time 24.25 seconds
Started May 30 02:21:33 PM PDT 24
Finished May 30 02:21:58 PM PDT 24
Peak memory 209376 kb
Host smart-f493b9b6-7df0-470a-b9a7-aca4beb0e0bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894598400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2894598400
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3746918839
Short name T422
Test name
Test status
Simulation time 345984691 ps
CPU time 2.5 seconds
Started May 30 02:21:30 PM PDT 24
Finished May 30 02:21:33 PM PDT 24
Peak memory 200876 kb
Host smart-b4404497-fa26-4ae3-a107-2fb0d10dec6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746918839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3746918839
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3191513514
Short name T164
Test name
Test status
Simulation time 119911738 ps
CPU time 0.95 seconds
Started May 30 02:21:32 PM PDT 24
Finished May 30 02:21:34 PM PDT 24
Peak memory 200828 kb
Host smart-c3159d6a-9124-4a88-9ed4-affd635bd1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191513514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3191513514
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3232168924
Short name T276
Test name
Test status
Simulation time 72206511 ps
CPU time 0.76 seconds
Started May 30 02:21:40 PM PDT 24
Finished May 30 02:21:42 PM PDT 24
Peak memory 200716 kb
Host smart-278ceed5-77c2-4468-a6d7-5e43d89cd140
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232168924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3232168924
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2844826347
Short name T29
Test name
Test status
Simulation time 1226876510 ps
CPU time 5.69 seconds
Started May 30 02:21:38 PM PDT 24
Finished May 30 02:21:45 PM PDT 24
Peak memory 218508 kb
Host smart-921a62cc-ae43-4572-82f5-c6b0b93790b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844826347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2844826347
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.4240016795
Short name T122
Test name
Test status
Simulation time 244622436 ps
CPU time 1.05 seconds
Started May 30 02:21:38 PM PDT 24
Finished May 30 02:21:41 PM PDT 24
Peak memory 218036 kb
Host smart-fe2c7061-1461-4a37-89fa-730e86c84ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240016795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.4240016795
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2991456532
Short name T464
Test name
Test status
Simulation time 147442248 ps
CPU time 0.86 seconds
Started May 30 02:21:45 PM PDT 24
Finished May 30 02:21:46 PM PDT 24
Peak memory 200716 kb
Host smart-dff847b9-7cbc-43b9-8379-41cf25f401f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991456532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2991456532
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2334819807
Short name T500
Test name
Test status
Simulation time 1589450344 ps
CPU time 5.93 seconds
Started May 30 02:21:42 PM PDT 24
Finished May 30 02:21:49 PM PDT 24
Peak memory 201044 kb
Host smart-26e9f6d8-a5f9-4ab7-9c28-cb0fa5fe39af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334819807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2334819807
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1154748254
Short name T225
Test name
Test status
Simulation time 104526002 ps
CPU time 1.02 seconds
Started May 30 02:21:41 PM PDT 24
Finished May 30 02:21:43 PM PDT 24
Peak memory 200956 kb
Host smart-eeb5ee62-3dc1-4d28-a541-0b613621366b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154748254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1154748254
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1532056972
Short name T196
Test name
Test status
Simulation time 115396903 ps
CPU time 1.22 seconds
Started May 30 02:21:32 PM PDT 24
Finished May 30 02:21:34 PM PDT 24
Peak memory 201024 kb
Host smart-22178f97-c824-455c-845c-f47a95bb2ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532056972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1532056972
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.1926227193
Short name T295
Test name
Test status
Simulation time 134272213 ps
CPU time 1.73 seconds
Started May 30 02:21:38 PM PDT 24
Finished May 30 02:21:41 PM PDT 24
Peak memory 200836 kb
Host smart-11d5d3a9-a4ed-488f-8d38-34e6304e257e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926227193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1926227193
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2036189306
Short name T496
Test name
Test status
Simulation time 170415769 ps
CPU time 1.4 seconds
Started May 30 02:21:41 PM PDT 24
Finished May 30 02:21:43 PM PDT 24
Peak memory 201084 kb
Host smart-502daf7e-724b-423d-afc0-9bfaf8333fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036189306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2036189306
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1955968652
Short name T123
Test name
Test status
Simulation time 74823565 ps
CPU time 0.76 seconds
Started May 30 02:21:41 PM PDT 24
Finished May 30 02:21:42 PM PDT 24
Peak memory 200696 kb
Host smart-4fec3ded-f264-4c63-ab37-61e2d450e836
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955968652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1955968652
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.1856250915
Short name T348
Test name
Test status
Simulation time 1891755889 ps
CPU time 6.71 seconds
Started May 30 02:21:39 PM PDT 24
Finished May 30 02:21:47 PM PDT 24
Peak memory 222072 kb
Host smart-c1ffc22e-aa55-4f35-b0f2-848f1c32517b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856250915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.1856250915
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2922659794
Short name T457
Test name
Test status
Simulation time 244327605 ps
CPU time 1.06 seconds
Started May 30 02:21:43 PM PDT 24
Finished May 30 02:21:45 PM PDT 24
Peak memory 218008 kb
Host smart-1a5a70ea-d70c-45d4-8048-31f1aeaee7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922659794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2922659794
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.173208197
Short name T528
Test name
Test status
Simulation time 100872652 ps
CPU time 0.77 seconds
Started May 30 02:21:37 PM PDT 24
Finished May 30 02:21:38 PM PDT 24
Peak memory 200676 kb
Host smart-bf3d98f8-c9ec-4a83-a9c5-0f369f57c009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173208197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.173208197
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1383193793
Short name T339
Test name
Test status
Simulation time 851574171 ps
CPU time 4.25 seconds
Started May 30 02:21:40 PM PDT 24
Finished May 30 02:21:45 PM PDT 24
Peak memory 201112 kb
Host smart-5ede86b9-83a0-47be-b179-0d5f0f8bc766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383193793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1383193793
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3377766479
Short name T193
Test name
Test status
Simulation time 173151462 ps
CPU time 1.24 seconds
Started May 30 02:21:45 PM PDT 24
Finished May 30 02:21:47 PM PDT 24
Peak memory 200816 kb
Host smart-7fab3dcf-2e7d-41e5-82f2-f68d9ebfc2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377766479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3377766479
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2674888994
Short name T213
Test name
Test status
Simulation time 209165475 ps
CPU time 1.4 seconds
Started May 30 02:21:37 PM PDT 24
Finished May 30 02:21:39 PM PDT 24
Peak memory 201036 kb
Host smart-36f80f35-104d-4a77-842b-ecc65bf3e145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674888994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2674888994
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.4032347211
Short name T402
Test name
Test status
Simulation time 3984349166 ps
CPU time 18.02 seconds
Started May 30 02:21:39 PM PDT 24
Finished May 30 02:21:59 PM PDT 24
Peak memory 201216 kb
Host smart-0bfdd890-ae75-4c69-9e7b-08f48638fac5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032347211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.4032347211
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2382450113
Short name T229
Test name
Test status
Simulation time 464576956 ps
CPU time 2.53 seconds
Started May 30 02:21:39 PM PDT 24
Finished May 30 02:21:43 PM PDT 24
Peak memory 200872 kb
Host smart-e6b69425-b3b8-492b-b6bd-6487a53cb38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382450113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2382450113
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2334642826
Short name T209
Test name
Test status
Simulation time 219659724 ps
CPU time 1.3 seconds
Started May 30 02:21:38 PM PDT 24
Finished May 30 02:21:40 PM PDT 24
Peak memory 200884 kb
Host smart-1e25f283-bcaf-4859-b278-100b07805345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334642826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2334642826
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2561314916
Short name T203
Test name
Test status
Simulation time 70577338 ps
CPU time 0.77 seconds
Started May 30 02:21:50 PM PDT 24
Finished May 30 02:21:52 PM PDT 24
Peak memory 200664 kb
Host smart-0d12d4c9-2d44-4c71-956d-53801bbe14f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561314916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2561314916
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.54880179
Short name T9
Test name
Test status
Simulation time 1219710532 ps
CPU time 5.99 seconds
Started May 30 02:21:54 PM PDT 24
Finished May 30 02:22:01 PM PDT 24
Peak memory 218520 kb
Host smart-ee9df115-0207-44f4-9b29-7f743ce8e953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54880179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.54880179
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3173787528
Short name T391
Test name
Test status
Simulation time 244155466 ps
CPU time 1.1 seconds
Started May 30 02:21:51 PM PDT 24
Finished May 30 02:21:53 PM PDT 24
Peak memory 218032 kb
Host smart-0faf41f4-515a-4bc8-891a-f152953a2a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173787528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3173787528
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1832158749
Short name T205
Test name
Test status
Simulation time 195649291 ps
CPU time 0.95 seconds
Started May 30 02:21:38 PM PDT 24
Finished May 30 02:21:40 PM PDT 24
Peak memory 200704 kb
Host smart-902591c0-1a16-473f-95d9-0a982f65298f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832158749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1832158749
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2516160830
Short name T40
Test name
Test status
Simulation time 1040130603 ps
CPU time 4.78 seconds
Started May 30 02:21:53 PM PDT 24
Finished May 30 02:21:59 PM PDT 24
Peak memory 201084 kb
Host smart-b2021a5d-d238-4471-9f7f-39b681b07256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516160830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2516160830
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.528700138
Short name T419
Test name
Test status
Simulation time 107205844 ps
CPU time 1.09 seconds
Started May 30 02:21:51 PM PDT 24
Finished May 30 02:21:53 PM PDT 24
Peak memory 200912 kb
Host smart-64e1f089-8344-4134-8eef-7492e7c69df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528700138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.528700138
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.1305120394
Short name T216
Test name
Test status
Simulation time 123788936 ps
CPU time 1.24 seconds
Started May 30 02:21:38 PM PDT 24
Finished May 30 02:21:41 PM PDT 24
Peak memory 201024 kb
Host smart-c47122ac-0f3f-4d61-a871-36c47fb84f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305120394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1305120394
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1879711339
Short name T408
Test name
Test status
Simulation time 5162661060 ps
CPU time 24.66 seconds
Started May 30 02:21:52 PM PDT 24
Finished May 30 02:22:17 PM PDT 24
Peak memory 201196 kb
Host smart-3209a258-346f-4fc1-bfe0-a8fd762e8c77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879711339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1879711339
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1950199745
Short name T507
Test name
Test status
Simulation time 135023767 ps
CPU time 1.85 seconds
Started May 30 02:21:56 PM PDT 24
Finished May 30 02:21:58 PM PDT 24
Peak memory 200880 kb
Host smart-38ecefa1-3b97-44cc-816e-97cc4ce5afd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950199745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1950199745
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3750915295
Short name T125
Test name
Test status
Simulation time 154288189 ps
CPU time 1.25 seconds
Started May 30 02:21:52 PM PDT 24
Finished May 30 02:21:54 PM PDT 24
Peak memory 200856 kb
Host smart-7c85c9e6-4f0a-4954-a99d-bc166c5307d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750915295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3750915295
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.757053829
Short name T147
Test name
Test status
Simulation time 67319823 ps
CPU time 0.75 seconds
Started May 30 02:21:50 PM PDT 24
Finished May 30 02:21:51 PM PDT 24
Peak memory 200708 kb
Host smart-606d1494-405e-4f63-b174-29b9aea3877e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757053829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.757053829
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3044413534
Short name T30
Test name
Test status
Simulation time 1230867172 ps
CPU time 6.12 seconds
Started May 30 02:21:56 PM PDT 24
Finished May 30 02:22:03 PM PDT 24
Peak memory 222608 kb
Host smart-d07cd860-3466-42c6-b2dd-9e9bd2da1c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044413534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3044413534
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1432307644
Short name T148
Test name
Test status
Simulation time 244625950 ps
CPU time 1.05 seconds
Started May 30 02:21:52 PM PDT 24
Finished May 30 02:21:53 PM PDT 24
Peak memory 218092 kb
Host smart-8658ea59-df33-4729-b038-dc90be529fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432307644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1432307644
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.950495352
Short name T17
Test name
Test status
Simulation time 213817887 ps
CPU time 0.98 seconds
Started May 30 02:21:53 PM PDT 24
Finished May 30 02:21:55 PM PDT 24
Peak memory 200668 kb
Host smart-d4fccdad-a792-4e60-89be-5db9e5a1d038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950495352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.950495352
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.989359143
Short name T540
Test name
Test status
Simulation time 1688380091 ps
CPU time 7.39 seconds
Started May 30 02:21:51 PM PDT 24
Finished May 30 02:21:59 PM PDT 24
Peak memory 201048 kb
Host smart-72a60b4c-6c05-4b9e-b221-ae5782a3d7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989359143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.989359143
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.4120473565
Short name T403
Test name
Test status
Simulation time 156275713 ps
CPU time 1.12 seconds
Started May 30 02:21:49 PM PDT 24
Finished May 30 02:21:51 PM PDT 24
Peak memory 200872 kb
Host smart-d09fe45f-b5a7-4fb5-bfd6-4b18f981bf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120473565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.4120473565
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.752777355
Short name T328
Test name
Test status
Simulation time 191079504 ps
CPU time 1.52 seconds
Started May 30 02:21:51 PM PDT 24
Finished May 30 02:21:53 PM PDT 24
Peak memory 201128 kb
Host smart-9f7ab374-5ec7-455f-bd46-e2c77afc7b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752777355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.752777355
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3014564728
Short name T249
Test name
Test status
Simulation time 2540426583 ps
CPU time 12.43 seconds
Started May 30 02:21:53 PM PDT 24
Finished May 30 02:22:06 PM PDT 24
Peak memory 201236 kb
Host smart-b1da9f1d-b3e1-4b7d-a124-eae8851625e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014564728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3014564728
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3144103471
Short name T452
Test name
Test status
Simulation time 487081889 ps
CPU time 2.74 seconds
Started May 30 02:21:50 PM PDT 24
Finished May 30 02:21:53 PM PDT 24
Peak memory 200852 kb
Host smart-1ac35d8c-5762-4376-b4ed-17d4d5116105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144103471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3144103471
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3262693757
Short name T305
Test name
Test status
Simulation time 156109652 ps
CPU time 1.09 seconds
Started May 30 02:21:50 PM PDT 24
Finished May 30 02:21:52 PM PDT 24
Peak memory 200832 kb
Host smart-f866ff7d-544c-4ae6-81e5-507f98a91bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262693757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3262693757
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1842663347
Short name T39
Test name
Test status
Simulation time 57486286 ps
CPU time 0.72 seconds
Started May 30 02:22:09 PM PDT 24
Finished May 30 02:22:10 PM PDT 24
Peak memory 200712 kb
Host smart-f1929753-3861-4dde-a325-6e9b9b86060f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842663347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1842663347
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.854339598
Short name T23
Test name
Test status
Simulation time 2339675949 ps
CPU time 8.02 seconds
Started May 30 02:22:08 PM PDT 24
Finished May 30 02:22:17 PM PDT 24
Peak memory 217808 kb
Host smart-f7491764-0a47-4203-9da3-3c816482c635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854339598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.854339598
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.867470945
Short name T309
Test name
Test status
Simulation time 244869802 ps
CPU time 1.26 seconds
Started May 30 02:22:11 PM PDT 24
Finished May 30 02:22:14 PM PDT 24
Peak memory 218244 kb
Host smart-7740b7fb-0c08-4c85-b53d-ab375fdb125d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867470945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.867470945
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.4008836307
Short name T13
Test name
Test status
Simulation time 131914535 ps
CPU time 0.8 seconds
Started May 30 02:21:51 PM PDT 24
Finished May 30 02:21:53 PM PDT 24
Peak memory 200696 kb
Host smart-2efd055a-cbf4-4192-a4a7-9ac3f5f4098d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008836307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.4008836307
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.72781021
Short name T93
Test name
Test status
Simulation time 1625340350 ps
CPU time 6.22 seconds
Started May 30 02:21:51 PM PDT 24
Finished May 30 02:21:58 PM PDT 24
Peak memory 201092 kb
Host smart-c137c3d5-dcec-4bcb-82ec-7ad7a0b440dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72781021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.72781021
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.128792428
Short name T415
Test name
Test status
Simulation time 98399536 ps
CPU time 0.97 seconds
Started May 30 02:22:10 PM PDT 24
Finished May 30 02:22:12 PM PDT 24
Peak memory 200896 kb
Host smart-a6b0cbc5-5d54-452f-af53-a27c50a34b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128792428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.128792428
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.213971824
Short name T238
Test name
Test status
Simulation time 119524167 ps
CPU time 1.2 seconds
Started May 30 02:21:52 PM PDT 24
Finished May 30 02:21:54 PM PDT 24
Peak memory 201064 kb
Host smart-7d36f059-1282-401e-a3d4-e3e7ccbdbf22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213971824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.213971824
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1397164156
Short name T197
Test name
Test status
Simulation time 6235920407 ps
CPU time 25.46 seconds
Started May 30 02:22:11 PM PDT 24
Finished May 30 02:22:38 PM PDT 24
Peak memory 201264 kb
Host smart-4adf796d-112e-4e88-a8da-2d1b1ab837bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397164156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1397164156
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.2661854334
Short name T267
Test name
Test status
Simulation time 144397654 ps
CPU time 1.75 seconds
Started May 30 02:22:11 PM PDT 24
Finished May 30 02:22:14 PM PDT 24
Peak memory 209004 kb
Host smart-8420c767-f457-4d3a-8063-e3d0f3502e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661854334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2661854334
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.550432963
Short name T400
Test name
Test status
Simulation time 82413181 ps
CPU time 0.86 seconds
Started May 30 02:21:50 PM PDT 24
Finished May 30 02:21:51 PM PDT 24
Peak memory 200880 kb
Host smart-d9364f8e-e6d9-439e-8965-5ecdff89c8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550432963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.550432963
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.4125572758
Short name T325
Test name
Test status
Simulation time 66656078 ps
CPU time 0.79 seconds
Started May 30 02:22:10 PM PDT 24
Finished May 30 02:22:12 PM PDT 24
Peak memory 200704 kb
Host smart-f9f21ede-89a3-43f1-ada6-0ad683ac4a48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125572758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.4125572758
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2334247446
Short name T451
Test name
Test status
Simulation time 1902674106 ps
CPU time 7.5 seconds
Started May 30 02:22:09 PM PDT 24
Finished May 30 02:22:17 PM PDT 24
Peak memory 218504 kb
Host smart-69f6782e-9658-46a8-8ccf-149dafc08007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334247446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2334247446
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2820259033
Short name T466
Test name
Test status
Simulation time 245359187 ps
CPU time 1.08 seconds
Started May 30 02:22:11 PM PDT 24
Finished May 30 02:22:14 PM PDT 24
Peak memory 218028 kb
Host smart-8ee02ce7-ec71-404a-836b-c29ff5f4dd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820259033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2820259033
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.947859307
Short name T244
Test name
Test status
Simulation time 174984475 ps
CPU time 0.88 seconds
Started May 30 02:22:10 PM PDT 24
Finished May 30 02:22:12 PM PDT 24
Peak memory 200736 kb
Host smart-83a31766-b322-4298-bd50-9df00310ec38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947859307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.947859307
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2002027724
Short name T258
Test name
Test status
Simulation time 1179295828 ps
CPU time 4.73 seconds
Started May 30 02:22:11 PM PDT 24
Finished May 30 02:22:17 PM PDT 24
Peak memory 201068 kb
Host smart-4ab33693-1684-4b3e-b14c-ce85c577b46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002027724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2002027724
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.870695833
Short name T282
Test name
Test status
Simulation time 189166227 ps
CPU time 1.23 seconds
Started May 30 02:22:09 PM PDT 24
Finished May 30 02:22:12 PM PDT 24
Peak memory 200892 kb
Host smart-2bb28f78-7c47-43cd-8ca0-0447961f7ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870695833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.870695833
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2162892541
Short name T331
Test name
Test status
Simulation time 203195874 ps
CPU time 1.47 seconds
Started May 30 02:22:10 PM PDT 24
Finished May 30 02:22:13 PM PDT 24
Peak memory 201056 kb
Host smart-e619cfa7-bf4f-4b40-adea-cad1f6de0463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162892541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2162892541
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.1314256304
Short name T389
Test name
Test status
Simulation time 628285494 ps
CPU time 3.12 seconds
Started May 30 02:22:12 PM PDT 24
Finished May 30 02:22:17 PM PDT 24
Peak memory 201100 kb
Host smart-c17a27b2-0be2-42ef-a9a6-2db7c1859209
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314256304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1314256304
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.60587787
Short name T413
Test name
Test status
Simulation time 118612567 ps
CPU time 1.59 seconds
Started May 30 02:22:11 PM PDT 24
Finished May 30 02:22:14 PM PDT 24
Peak memory 200872 kb
Host smart-74a872d0-fa32-4157-aff3-809294aaf1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60587787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.60587787
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2665816151
Short name T226
Test name
Test status
Simulation time 76737332 ps
CPU time 0.84 seconds
Started May 30 02:22:10 PM PDT 24
Finished May 30 02:22:12 PM PDT 24
Peak memory 200864 kb
Host smart-6201884b-44b9-4079-922f-e8ba59c3067d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665816151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2665816151
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.212846555
Short name T199
Test name
Test status
Simulation time 63572173 ps
CPU time 0.72 seconds
Started May 30 02:22:19 PM PDT 24
Finished May 30 02:22:21 PM PDT 24
Peak memory 200724 kb
Host smart-071a1753-72fb-45c6-b2e9-de2967400044
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212846555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.212846555
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.893217975
Short name T435
Test name
Test status
Simulation time 2343090846 ps
CPU time 9.6 seconds
Started May 30 02:22:11 PM PDT 24
Finished May 30 02:22:22 PM PDT 24
Peak memory 218644 kb
Host smart-efd4da34-2990-4a1a-a76a-758f25ed1628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893217975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.893217975
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1226378611
Short name T170
Test name
Test status
Simulation time 251861618 ps
CPU time 1.08 seconds
Started May 30 02:22:10 PM PDT 24
Finished May 30 02:22:13 PM PDT 24
Peak memory 218172 kb
Host smart-17bc284f-b615-45aa-94be-960e0f086fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226378611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1226378611
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2377198230
Short name T201
Test name
Test status
Simulation time 113615943 ps
CPU time 0.84 seconds
Started May 30 02:22:10 PM PDT 24
Finished May 30 02:22:12 PM PDT 24
Peak memory 200668 kb
Host smart-6bec724a-593e-40fc-80dd-6fcc4c249c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377198230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2377198230
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.585218346
Short name T534
Test name
Test status
Simulation time 1441210717 ps
CPU time 6.09 seconds
Started May 30 02:22:11 PM PDT 24
Finished May 30 02:22:19 PM PDT 24
Peak memory 201064 kb
Host smart-a34e37e2-4db8-4165-8b5a-94a3215ba20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585218346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.585218346
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1400618677
Short name T191
Test name
Test status
Simulation time 151234237 ps
CPU time 1.22 seconds
Started May 30 02:22:11 PM PDT 24
Finished May 30 02:22:13 PM PDT 24
Peak memory 200860 kb
Host smart-7724b5f8-4b93-4d38-ab93-3388af1cb12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400618677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1400618677
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.378501100
Short name T137
Test name
Test status
Simulation time 120818664 ps
CPU time 1.19 seconds
Started May 30 02:22:11 PM PDT 24
Finished May 30 02:22:13 PM PDT 24
Peak memory 201052 kb
Host smart-d3214924-739f-4c40-b1b7-8d727b38fc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378501100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.378501100
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3525324705
Short name T231
Test name
Test status
Simulation time 232986992 ps
CPU time 1.63 seconds
Started May 30 02:22:10 PM PDT 24
Finished May 30 02:22:13 PM PDT 24
Peak memory 201084 kb
Host smart-d513b415-5097-4e23-a664-0ae89f0f8f09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525324705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3525324705
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2036223598
Short name T222
Test name
Test status
Simulation time 432983216 ps
CPU time 2.38 seconds
Started May 30 02:22:10 PM PDT 24
Finished May 30 02:22:13 PM PDT 24
Peak memory 200804 kb
Host smart-31060987-dcbe-47fd-b267-b8568710e8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036223598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2036223598
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1512707050
Short name T342
Test name
Test status
Simulation time 94815705 ps
CPU time 0.92 seconds
Started May 30 02:22:10 PM PDT 24
Finished May 30 02:22:12 PM PDT 24
Peak memory 200888 kb
Host smart-a1b6b654-cfb5-4cd9-9f7a-cd358382f693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512707050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1512707050
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.772155886
Short name T260
Test name
Test status
Simulation time 68777865 ps
CPU time 0.84 seconds
Started May 30 02:22:21 PM PDT 24
Finished May 30 02:22:23 PM PDT 24
Peak memory 200672 kb
Host smart-7698670a-b756-40af-a075-56469c71ebfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772155886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.772155886
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.4208946411
Short name T298
Test name
Test status
Simulation time 1226341797 ps
CPU time 5.61 seconds
Started May 30 02:22:17 PM PDT 24
Finished May 30 02:22:23 PM PDT 24
Peak memory 217604 kb
Host smart-2126fcfd-13dd-4756-bb96-aa15a93cd11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208946411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.4208946411
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2455748808
Short name T294
Test name
Test status
Simulation time 244499129 ps
CPU time 1.16 seconds
Started May 30 02:22:20 PM PDT 24
Finished May 30 02:22:22 PM PDT 24
Peak memory 218056 kb
Host smart-06651982-3e01-429e-beee-6901919679fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455748808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2455748808
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.694895500
Short name T411
Test name
Test status
Simulation time 198524427 ps
CPU time 0.99 seconds
Started May 30 02:22:19 PM PDT 24
Finished May 30 02:22:20 PM PDT 24
Peak memory 200676 kb
Host smart-2a1f6876-cf9b-40c2-82b5-c651a53b976b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694895500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.694895500
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1465855352
Short name T351
Test name
Test status
Simulation time 1573748523 ps
CPU time 6.74 seconds
Started May 30 02:22:18 PM PDT 24
Finished May 30 02:22:25 PM PDT 24
Peak memory 201048 kb
Host smart-714709e7-07ad-4b39-8ca5-73e6f3560fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465855352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1465855352
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1679440585
Short name T455
Test name
Test status
Simulation time 171326581 ps
CPU time 1.29 seconds
Started May 30 02:22:20 PM PDT 24
Finished May 30 02:22:22 PM PDT 24
Peak memory 200844 kb
Host smart-b327cded-971e-46f4-a894-4c85a9b62802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679440585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1679440585
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.479002866
Short name T132
Test name
Test status
Simulation time 194375300 ps
CPU time 1.39 seconds
Started May 30 02:22:19 PM PDT 24
Finished May 30 02:22:21 PM PDT 24
Peak memory 201064 kb
Host smart-483f7485-1ebf-439c-a29b-7557adb81841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479002866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.479002866
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1927801487
Short name T297
Test name
Test status
Simulation time 8815638865 ps
CPU time 32.94 seconds
Started May 30 02:22:16 PM PDT 24
Finished May 30 02:22:50 PM PDT 24
Peak memory 201224 kb
Host smart-7e8cbec3-bf96-4a4f-b836-5d1655796972
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927801487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1927801487
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3566961577
Short name T401
Test name
Test status
Simulation time 483575420 ps
CPU time 2.73 seconds
Started May 30 02:22:21 PM PDT 24
Finished May 30 02:22:25 PM PDT 24
Peak memory 209084 kb
Host smart-85060287-2639-48e9-960c-1da6ed472508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566961577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3566961577
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2837768619
Short name T121
Test name
Test status
Simulation time 102828727 ps
CPU time 0.92 seconds
Started May 30 02:22:19 PM PDT 24
Finished May 30 02:22:21 PM PDT 24
Peak memory 200884 kb
Host smart-cb8b8293-1359-4942-ad2a-65155f7a68f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837768619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2837768619
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.1318085006
Short name T248
Test name
Test status
Simulation time 75414508 ps
CPU time 0.77 seconds
Started May 30 02:19:00 PM PDT 24
Finished May 30 02:19:03 PM PDT 24
Peak memory 200660 kb
Host smart-40df5f3a-9c82-4699-ab2c-f3601289cec8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318085006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1318085006
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1418096291
Short name T469
Test name
Test status
Simulation time 2367169378 ps
CPU time 8.87 seconds
Started May 30 02:18:54 PM PDT 24
Finished May 30 02:19:04 PM PDT 24
Peak memory 218288 kb
Host smart-cbbdc1a1-34a9-4e17-bb77-39e97ac94d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418096291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1418096291
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1734995826
Short name T134
Test name
Test status
Simulation time 244245176 ps
CPU time 1.03 seconds
Started May 30 02:18:54 PM PDT 24
Finished May 30 02:18:56 PM PDT 24
Peak memory 218068 kb
Host smart-ea14891c-3f9b-4b48-ad24-76fc885d9b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734995826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1734995826
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3930404094
Short name T308
Test name
Test status
Simulation time 177698282 ps
CPU time 0.96 seconds
Started May 30 02:18:47 PM PDT 24
Finished May 30 02:18:49 PM PDT 24
Peak memory 200684 kb
Host smart-63855b25-7478-4622-92fd-d7950eff3ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930404094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3930404094
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.3659767168
Short name T142
Test name
Test status
Simulation time 1065912847 ps
CPU time 5.55 seconds
Started May 30 02:18:53 PM PDT 24
Finished May 30 02:18:59 PM PDT 24
Peak memory 201088 kb
Host smart-bf63e64d-d26c-42b9-820c-b4b34d771c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659767168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3659767168
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.4081406938
Short name T62
Test name
Test status
Simulation time 19579771165 ps
CPU time 30.38 seconds
Started May 30 02:18:53 PM PDT 24
Finished May 30 02:19:25 PM PDT 24
Peak memory 218700 kb
Host smart-30099211-e329-4c00-aa25-36da2693d60d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081406938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.4081406938
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1024573658
Short name T354
Test name
Test status
Simulation time 107193118 ps
CPU time 1 seconds
Started May 30 02:19:00 PM PDT 24
Finished May 30 02:19:02 PM PDT 24
Peak memory 200844 kb
Host smart-9ea09618-3c36-4ca4-bcd4-6ba2cb548670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024573658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1024573658
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.845543350
Short name T511
Test name
Test status
Simulation time 197865356 ps
CPU time 1.37 seconds
Started May 30 02:18:55 PM PDT 24
Finished May 30 02:18:57 PM PDT 24
Peak memory 201020 kb
Host smart-7de78377-91d6-42a2-8cc9-292609afea14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845543350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.845543350
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.236573534
Short name T474
Test name
Test status
Simulation time 2849008448 ps
CPU time 13.3 seconds
Started May 30 02:19:01 PM PDT 24
Finished May 30 02:19:15 PM PDT 24
Peak memory 201152 kb
Host smart-a81ba075-92fe-4138-9ae0-a4e20ea865b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236573534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.236573534
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.4283331037
Short name T472
Test name
Test status
Simulation time 136231468 ps
CPU time 1.62 seconds
Started May 30 02:18:54 PM PDT 24
Finished May 30 02:18:57 PM PDT 24
Peak memory 209092 kb
Host smart-bcc3ef1f-ad15-4a88-b6ff-bf36171fdd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283331037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.4283331037
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.4129127737
Short name T423
Test name
Test status
Simulation time 144453301 ps
CPU time 1.24 seconds
Started May 30 02:18:46 PM PDT 24
Finished May 30 02:18:49 PM PDT 24
Peak memory 200888 kb
Host smart-a56d6f38-1591-473f-a48a-761fa3dc73c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129127737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.4129127737
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.259444524
Short name T233
Test name
Test status
Simulation time 64124270 ps
CPU time 0.78 seconds
Started May 30 02:22:20 PM PDT 24
Finished May 30 02:22:22 PM PDT 24
Peak memory 200728 kb
Host smart-4bfded8c-aa3a-4aa3-8a0b-89bbb316deb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259444524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.259444524
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1384449350
Short name T11
Test name
Test status
Simulation time 1230368412 ps
CPU time 5.42 seconds
Started May 30 02:22:17 PM PDT 24
Finished May 30 02:22:23 PM PDT 24
Peak memory 217972 kb
Host smart-c87821dc-3572-480f-8a78-0c95fb4907be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384449350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1384449350
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1087555870
Short name T127
Test name
Test status
Simulation time 244118316 ps
CPU time 1.15 seconds
Started May 30 02:22:18 PM PDT 24
Finished May 30 02:22:20 PM PDT 24
Peak memory 218016 kb
Host smart-72c7d107-73c4-424f-bed3-5b3f07ca6c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087555870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1087555870
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.4288312261
Short name T300
Test name
Test status
Simulation time 118576983 ps
CPU time 0.8 seconds
Started May 30 02:22:19 PM PDT 24
Finished May 30 02:22:20 PM PDT 24
Peak memory 200700 kb
Host smart-833f41ae-9b3c-4a19-92e6-583534496e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288312261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.4288312261
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.4257294240
Short name T35
Test name
Test status
Simulation time 1198739282 ps
CPU time 5.15 seconds
Started May 30 02:22:18 PM PDT 24
Finished May 30 02:22:24 PM PDT 24
Peak memory 201036 kb
Host smart-a8a03355-8d5c-4226-aac6-e975bcdfe7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257294240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.4257294240
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3641653713
Short name T119
Test name
Test status
Simulation time 150656513 ps
CPU time 1.21 seconds
Started May 30 02:22:21 PM PDT 24
Finished May 30 02:22:23 PM PDT 24
Peak memory 200904 kb
Host smart-5a66394c-d081-4be5-a806-cf8b98033ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641653713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3641653713
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.431863182
Short name T155
Test name
Test status
Simulation time 116456463 ps
CPU time 1.27 seconds
Started May 30 02:22:19 PM PDT 24
Finished May 30 02:22:21 PM PDT 24
Peak memory 201044 kb
Host smart-4044b84d-6eb3-4186-bdc0-5fb3beee5707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431863182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.431863182
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3102883704
Short name T398
Test name
Test status
Simulation time 9680223800 ps
CPU time 33.61 seconds
Started May 30 02:22:17 PM PDT 24
Finished May 30 02:22:51 PM PDT 24
Peak memory 209940 kb
Host smart-cc01cd7b-3811-46f4-85c6-106ff2aa2ffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102883704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3102883704
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.569633877
Short name T167
Test name
Test status
Simulation time 115946634 ps
CPU time 1.55 seconds
Started May 30 02:22:20 PM PDT 24
Finished May 30 02:22:23 PM PDT 24
Peak memory 200936 kb
Host smart-15271c9f-94b0-4a91-9d32-872980e3e920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569633877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.569633877
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3355289308
Short name T283
Test name
Test status
Simulation time 226607032 ps
CPU time 1.44 seconds
Started May 30 02:22:20 PM PDT 24
Finished May 30 02:22:22 PM PDT 24
Peak memory 200868 kb
Host smart-ee51f9d9-a3f8-4909-b731-c52a7f32a25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355289308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3355289308
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1032310043
Short name T504
Test name
Test status
Simulation time 80314844 ps
CPU time 0.81 seconds
Started May 30 02:22:35 PM PDT 24
Finished May 30 02:22:37 PM PDT 24
Peak memory 200728 kb
Host smart-8f0eaaf3-1b37-4258-a356-31fb4b7c91db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032310043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1032310043
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3897291795
Short name T364
Test name
Test status
Simulation time 1888803917 ps
CPU time 8.01 seconds
Started May 30 02:22:34 PM PDT 24
Finished May 30 02:22:43 PM PDT 24
Peak memory 218452 kb
Host smart-ccdbe682-4093-4df7-a5ce-255cda4a235d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897291795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3897291795
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.781214989
Short name T215
Test name
Test status
Simulation time 243909153 ps
CPU time 1.08 seconds
Started May 30 02:22:35 PM PDT 24
Finished May 30 02:22:37 PM PDT 24
Peak memory 218228 kb
Host smart-e6b2450a-4886-4f1a-9328-f4ea47840b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781214989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.781214989
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.2472383854
Short name T476
Test name
Test status
Simulation time 107985120 ps
CPU time 0.81 seconds
Started May 30 02:22:35 PM PDT 24
Finished May 30 02:22:37 PM PDT 24
Peak memory 200704 kb
Host smart-5ab97bd2-d5a4-4870-bc32-1566e7c0a3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472383854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2472383854
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3380604004
Short name T420
Test name
Test status
Simulation time 1399675310 ps
CPU time 5.67 seconds
Started May 30 02:22:35 PM PDT 24
Finished May 30 02:22:42 PM PDT 24
Peak memory 201064 kb
Host smart-d1082117-054b-4317-92f0-b279cc0d4b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380604004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3380604004
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3454236855
Short name T475
Test name
Test status
Simulation time 141282405 ps
CPU time 1.16 seconds
Started May 30 02:22:34 PM PDT 24
Finished May 30 02:22:36 PM PDT 24
Peak memory 200868 kb
Host smart-ea8357b1-0d69-4fa7-8b62-08a6a8f84a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454236855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3454236855
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.960263538
Short name T169
Test name
Test status
Simulation time 115456175 ps
CPU time 1.27 seconds
Started May 30 02:22:21 PM PDT 24
Finished May 30 02:22:23 PM PDT 24
Peak memory 201068 kb
Host smart-4ce0cb95-cef0-4994-b3ee-fcd536df7dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960263538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.960263538
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.880770852
Short name T362
Test name
Test status
Simulation time 510410960 ps
CPU time 2.86 seconds
Started May 30 02:22:35 PM PDT 24
Finished May 30 02:22:39 PM PDT 24
Peak memory 200876 kb
Host smart-52455854-a2dc-4823-a58e-1e8f98c08772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880770852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.880770852
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1698801130
Short name T394
Test name
Test status
Simulation time 111493436 ps
CPU time 0.94 seconds
Started May 30 02:22:34 PM PDT 24
Finished May 30 02:22:36 PM PDT 24
Peak memory 200896 kb
Host smart-8d83f3f8-93f5-4fe6-99e2-b486b23c58e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698801130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1698801130
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1464861263
Short name T344
Test name
Test status
Simulation time 82483940 ps
CPU time 0.89 seconds
Started May 30 02:22:39 PM PDT 24
Finished May 30 02:22:41 PM PDT 24
Peak memory 200716 kb
Host smart-0abb19a9-72fb-41b8-8ba2-31a8428158e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464861263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1464861263
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.809466386
Short name T387
Test name
Test status
Simulation time 2381351383 ps
CPU time 8.68 seconds
Started May 30 02:22:38 PM PDT 24
Finished May 30 02:22:48 PM PDT 24
Peak memory 218580 kb
Host smart-5b58b3fc-fa46-4dd9-97e1-7670f53c6594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809466386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.809466386
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.356687033
Short name T242
Test name
Test status
Simulation time 243867410 ps
CPU time 1.13 seconds
Started May 30 02:22:38 PM PDT 24
Finished May 30 02:22:40 PM PDT 24
Peak memory 218176 kb
Host smart-1fe6287c-a0b2-4035-9541-87db24111a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356687033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.356687033
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1020027403
Short name T335
Test name
Test status
Simulation time 203079899 ps
CPU time 1.01 seconds
Started May 30 02:22:38 PM PDT 24
Finished May 30 02:22:41 PM PDT 24
Peak memory 200680 kb
Host smart-4d4f290a-bf1c-4998-b26f-377f1d681f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020027403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1020027403
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1115244157
Short name T254
Test name
Test status
Simulation time 1049256082 ps
CPU time 5.23 seconds
Started May 30 02:22:35 PM PDT 24
Finished May 30 02:22:41 PM PDT 24
Peak memory 201056 kb
Host smart-4e3c7616-ed06-4d63-945a-4fcd918eeef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115244157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1115244157
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.742891910
Short name T358
Test name
Test status
Simulation time 139065970 ps
CPU time 1.13 seconds
Started May 30 02:22:40 PM PDT 24
Finished May 30 02:22:42 PM PDT 24
Peak memory 200876 kb
Host smart-9678b90f-ec6c-4f36-b3ba-f15abab31ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742891910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.742891910
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.814722794
Short name T519
Test name
Test status
Simulation time 189456125 ps
CPU time 1.46 seconds
Started May 30 02:22:35 PM PDT 24
Finished May 30 02:22:38 PM PDT 24
Peak memory 201068 kb
Host smart-8f3df640-8e35-41bd-9e0b-8ab3e426d7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814722794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.814722794
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1779886123
Short name T76
Test name
Test status
Simulation time 218360680 ps
CPU time 1.32 seconds
Started May 30 02:22:40 PM PDT 24
Finished May 30 02:22:42 PM PDT 24
Peak memory 200904 kb
Host smart-0b06ff35-7b2d-4bc6-abde-b9f17134ca3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779886123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1779886123
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1899527237
Short name T47
Test name
Test status
Simulation time 338530137 ps
CPU time 2.22 seconds
Started May 30 02:22:38 PM PDT 24
Finished May 30 02:22:41 PM PDT 24
Peak memory 209040 kb
Host smart-7cf84df9-2906-460b-920a-af4d1c1755df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899527237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1899527237
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.2034240095
Short name T329
Test name
Test status
Simulation time 286580665 ps
CPU time 1.53 seconds
Started May 30 02:22:41 PM PDT 24
Finished May 30 02:22:43 PM PDT 24
Peak memory 200820 kb
Host smart-3856b152-d6dd-42df-8a56-a0cb9af2eb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034240095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2034240095
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3653068311
Short name T163
Test name
Test status
Simulation time 72704956 ps
CPU time 0.78 seconds
Started May 30 02:22:49 PM PDT 24
Finished May 30 02:22:51 PM PDT 24
Peak memory 200644 kb
Host smart-20cc4c07-9d30-4c25-baff-ab912dd20efd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653068311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3653068311
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3128039845
Short name T429
Test name
Test status
Simulation time 1233078611 ps
CPU time 6.69 seconds
Started May 30 02:22:49 PM PDT 24
Finished May 30 02:22:56 PM PDT 24
Peak memory 218476 kb
Host smart-2bf54892-5169-473a-bd83-6c1c447d8972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128039845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3128039845
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3116683756
Short name T126
Test name
Test status
Simulation time 244704739 ps
CPU time 1.05 seconds
Started May 30 02:22:50 PM PDT 24
Finished May 30 02:22:52 PM PDT 24
Peak memory 218136 kb
Host smart-4d74a6bd-9aee-444c-84a2-9188992e3ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116683756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3116683756
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.384137770
Short name T525
Test name
Test status
Simulation time 143071654 ps
CPU time 0.8 seconds
Started May 30 02:22:40 PM PDT 24
Finished May 30 02:22:42 PM PDT 24
Peak memory 200772 kb
Host smart-e4db07d0-3555-4690-87c5-c28c68b8c43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384137770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.384137770
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2961982662
Short name T460
Test name
Test status
Simulation time 993877618 ps
CPU time 4.71 seconds
Started May 30 02:22:40 PM PDT 24
Finished May 30 02:22:46 PM PDT 24
Peak memory 201172 kb
Host smart-8b2bc15d-04cf-4f1a-868a-462281f76fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961982662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2961982662
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1177879992
Short name T320
Test name
Test status
Simulation time 104660063 ps
CPU time 1.12 seconds
Started May 30 02:22:50 PM PDT 24
Finished May 30 02:22:52 PM PDT 24
Peak memory 200948 kb
Host smart-48d418bd-cca5-4d2e-b101-d8251d169df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177879992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1177879992
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1812637036
Short name T235
Test name
Test status
Simulation time 198076430 ps
CPU time 1.45 seconds
Started May 30 02:22:38 PM PDT 24
Finished May 30 02:22:41 PM PDT 24
Peak memory 201060 kb
Host smart-9365d185-80bd-4578-b969-caa02602f6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812637036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1812637036
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1867443551
Short name T21
Test name
Test status
Simulation time 10434654964 ps
CPU time 46.06 seconds
Started May 30 02:22:49 PM PDT 24
Finished May 30 02:23:36 PM PDT 24
Peak memory 201248 kb
Host smart-7689724d-2517-4e34-9691-a31f762678ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867443551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1867443551
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.2506212601
Short name T374
Test name
Test status
Simulation time 347867167 ps
CPU time 2.32 seconds
Started May 30 02:22:49 PM PDT 24
Finished May 30 02:22:52 PM PDT 24
Peak memory 200844 kb
Host smart-3a9a3cde-8538-47c5-bd9f-a145c5b22463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506212601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2506212601
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1494171403
Short name T536
Test name
Test status
Simulation time 161070079 ps
CPU time 1.24 seconds
Started May 30 02:22:49 PM PDT 24
Finished May 30 02:22:51 PM PDT 24
Peak memory 201040 kb
Host smart-630e98de-8107-435c-8f71-ff3736967c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494171403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1494171403
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1661150154
Short name T385
Test name
Test status
Simulation time 86278939 ps
CPU time 0.86 seconds
Started May 30 02:22:52 PM PDT 24
Finished May 30 02:22:54 PM PDT 24
Peak memory 200644 kb
Host smart-5f2249ed-e4a4-47f7-b44b-b7c3798bf58c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661150154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1661150154
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2315603797
Short name T292
Test name
Test status
Simulation time 2172208886 ps
CPU time 8.7 seconds
Started May 30 02:22:52 PM PDT 24
Finished May 30 02:23:02 PM PDT 24
Peak memory 218644 kb
Host smart-2e011433-bb03-4111-8131-6ef0e215992a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315603797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2315603797
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1462225205
Short name T73
Test name
Test status
Simulation time 244080815 ps
CPU time 1.17 seconds
Started May 30 02:22:53 PM PDT 24
Finished May 30 02:22:55 PM PDT 24
Peak memory 218200 kb
Host smart-83b6c58d-775f-4a71-831d-cafe3a484554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462225205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1462225205
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3764465108
Short name T212
Test name
Test status
Simulation time 151576466 ps
CPU time 0.82 seconds
Started May 30 02:22:50 PM PDT 24
Finished May 30 02:22:52 PM PDT 24
Peak memory 200704 kb
Host smart-712df9d5-493b-48d5-97a6-38c1afbedad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764465108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3764465108
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3997916632
Short name T141
Test name
Test status
Simulation time 1687588055 ps
CPU time 6.95 seconds
Started May 30 02:22:52 PM PDT 24
Finished May 30 02:23:00 PM PDT 24
Peak memory 201052 kb
Host smart-1b78d107-5330-4aae-9c5d-5f7d85f1168a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997916632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3997916632
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3265837484
Short name T383
Test name
Test status
Simulation time 161865969 ps
CPU time 1.17 seconds
Started May 30 02:22:51 PM PDT 24
Finished May 30 02:22:53 PM PDT 24
Peak memory 200868 kb
Host smart-9589c2af-fa7c-4167-a35b-4f728e55b078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265837484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3265837484
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3267094452
Short name T153
Test name
Test status
Simulation time 125332862 ps
CPU time 1.28 seconds
Started May 30 02:22:51 PM PDT 24
Finished May 30 02:22:53 PM PDT 24
Peak memory 201048 kb
Host smart-fe4de2dd-ffc1-4cb9-be44-c56a75980640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267094452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3267094452
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2176087767
Short name T156
Test name
Test status
Simulation time 2899463695 ps
CPU time 11.59 seconds
Started May 30 02:22:52 PM PDT 24
Finished May 30 02:23:05 PM PDT 24
Peak memory 210696 kb
Host smart-48d28ed0-5162-45a6-b762-b356d83e800f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176087767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2176087767
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1972434438
Short name T431
Test name
Test status
Simulation time 275489222 ps
CPU time 1.86 seconds
Started May 30 02:22:54 PM PDT 24
Finished May 30 02:22:56 PM PDT 24
Peak memory 200804 kb
Host smart-21d62187-4bd9-48f0-8e58-c71ad49d9460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972434438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1972434438
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2450478881
Short name T151
Test name
Test status
Simulation time 171538840 ps
CPU time 1.32 seconds
Started May 30 02:22:51 PM PDT 24
Finished May 30 02:22:54 PM PDT 24
Peak memory 200888 kb
Host smart-5c8c1dad-a370-488f-b264-52e497c65f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450478881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2450478881
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.49566536
Short name T278
Test name
Test status
Simulation time 63981410 ps
CPU time 0.8 seconds
Started May 30 02:23:00 PM PDT 24
Finished May 30 02:23:02 PM PDT 24
Peak memory 200716 kb
Host smart-784d974f-ae3f-465d-a02a-6143278a7358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49566536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.49566536
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.3125634728
Short name T371
Test name
Test status
Simulation time 2366501240 ps
CPU time 8.32 seconds
Started May 30 02:22:56 PM PDT 24
Finished May 30 02:23:05 PM PDT 24
Peak memory 222644 kb
Host smart-ca31cb32-c173-4471-bf1a-fd2c3172ad45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125634728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.3125634728
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.4173200526
Short name T417
Test name
Test status
Simulation time 244664114 ps
CPU time 1.18 seconds
Started May 30 02:23:00 PM PDT 24
Finished May 30 02:23:02 PM PDT 24
Peak memory 218076 kb
Host smart-2b3c28af-8619-4fac-8af5-f5c66ed821da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173200526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.4173200526
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1433030800
Short name T15
Test name
Test status
Simulation time 182605600 ps
CPU time 0.94 seconds
Started May 30 02:22:54 PM PDT 24
Finished May 30 02:22:57 PM PDT 24
Peak memory 200672 kb
Host smart-acb72135-29f6-4299-9af0-5903443defb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433030800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1433030800
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1516080207
Short name T379
Test name
Test status
Simulation time 1393458132 ps
CPU time 5.31 seconds
Started May 30 02:22:56 PM PDT 24
Finished May 30 02:23:02 PM PDT 24
Peak memory 201004 kb
Host smart-b0fa9d54-886f-4c61-8225-b0a62c644214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516080207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1516080207
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2404409645
Short name T250
Test name
Test status
Simulation time 175741621 ps
CPU time 1.27 seconds
Started May 30 02:22:54 PM PDT 24
Finished May 30 02:22:56 PM PDT 24
Peak memory 200892 kb
Host smart-a0e58294-1b12-4d3f-9ad9-3db53500e84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404409645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2404409645
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3866992943
Short name T173
Test name
Test status
Simulation time 117449854 ps
CPU time 1.27 seconds
Started May 30 02:22:52 PM PDT 24
Finished May 30 02:22:55 PM PDT 24
Peak memory 201064 kb
Host smart-e2359c5f-2aa8-4864-bc79-f23019fb18be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866992943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3866992943
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3710600791
Short name T68
Test name
Test status
Simulation time 8769479237 ps
CPU time 40.04 seconds
Started May 30 02:23:01 PM PDT 24
Finished May 30 02:23:43 PM PDT 24
Peak memory 209432 kb
Host smart-07cf0352-f161-4c70-9cdf-6388472bad3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710600791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3710600791
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.844358000
Short name T458
Test name
Test status
Simulation time 128529325 ps
CPU time 1.72 seconds
Started May 30 02:22:55 PM PDT 24
Finished May 30 02:22:58 PM PDT 24
Peak memory 200812 kb
Host smart-2c8fe8e4-22a9-4561-9ee6-ce1aa56d525a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844358000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.844358000
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3317522704
Short name T168
Test name
Test status
Simulation time 74950545 ps
CPU time 0.81 seconds
Started May 30 02:22:56 PM PDT 24
Finished May 30 02:22:57 PM PDT 24
Peak memory 200884 kb
Host smart-d6918389-ff86-4beb-871e-ee979cedc833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317522704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3317522704
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2442659345
Short name T449
Test name
Test status
Simulation time 55858089 ps
CPU time 0.73 seconds
Started May 30 02:23:05 PM PDT 24
Finished May 30 02:23:06 PM PDT 24
Peak memory 200696 kb
Host smart-f52c90ce-f421-451c-9ce5-b35668942527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442659345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2442659345
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.962904299
Short name T390
Test name
Test status
Simulation time 1229340181 ps
CPU time 5.45 seconds
Started May 30 02:23:04 PM PDT 24
Finished May 30 02:23:11 PM PDT 24
Peak memory 222020 kb
Host smart-31ee0d29-f616-4319-b383-1af6796b5df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962904299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.962904299
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1149070905
Short name T459
Test name
Test status
Simulation time 243530458 ps
CPU time 1.09 seconds
Started May 30 02:23:03 PM PDT 24
Finished May 30 02:23:05 PM PDT 24
Peak memory 218004 kb
Host smart-f91f1c5b-dac0-4f16-90e3-e7ecac64af9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149070905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1149070905
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.1038503528
Short name T253
Test name
Test status
Simulation time 97581748 ps
CPU time 0.82 seconds
Started May 30 02:23:07 PM PDT 24
Finished May 30 02:23:09 PM PDT 24
Peak memory 200680 kb
Host smart-e7320d22-1d04-4a6b-ac61-3e18443b0568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038503528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1038503528
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2289188410
Short name T129
Test name
Test status
Simulation time 715074219 ps
CPU time 3.83 seconds
Started May 30 02:23:05 PM PDT 24
Finished May 30 02:23:10 PM PDT 24
Peak memory 201072 kb
Host smart-d7dce6d0-28a7-4e61-986d-ec50dd4be3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289188410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2289188410
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.18033590
Short name T64
Test name
Test status
Simulation time 108827420 ps
CPU time 1.1 seconds
Started May 30 02:23:02 PM PDT 24
Finished May 30 02:23:04 PM PDT 24
Peak memory 200908 kb
Host smart-f7b91b56-6ce5-479b-b404-713e6220f63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18033590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.18033590
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.3661815803
Short name T471
Test name
Test status
Simulation time 117912902 ps
CPU time 1.18 seconds
Started May 30 02:23:04 PM PDT 24
Finished May 30 02:23:07 PM PDT 24
Peak memory 201048 kb
Host smart-8a9c7b9a-348e-402f-89e4-6d922d046c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661815803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3661815803
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.840861087
Short name T255
Test name
Test status
Simulation time 8359005392 ps
CPU time 31.09 seconds
Started May 30 02:23:01 PM PDT 24
Finished May 30 02:23:33 PM PDT 24
Peak memory 201244 kb
Host smart-fafef6d4-b0e6-43b2-8c08-45d8eae9ba7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840861087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.840861087
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.1695812725
Short name T223
Test name
Test status
Simulation time 432610705 ps
CPU time 2.63 seconds
Started May 30 02:23:00 PM PDT 24
Finished May 30 02:23:04 PM PDT 24
Peak memory 200820 kb
Host smart-8dfc9486-7d06-4ff0-94fd-1c55ea086428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695812725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1695812725
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.3285283535
Short name T200
Test name
Test status
Simulation time 111035805 ps
CPU time 0.99 seconds
Started May 30 02:23:04 PM PDT 24
Finished May 30 02:23:06 PM PDT 24
Peak memory 200864 kb
Host smart-57fed556-358a-448a-8c3d-df7290d422f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285283535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.3285283535
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.2399241361
Short name T303
Test name
Test status
Simulation time 64856265 ps
CPU time 0.78 seconds
Started May 30 02:23:02 PM PDT 24
Finished May 30 02:23:04 PM PDT 24
Peak memory 200732 kb
Host smart-e2e1c489-c785-4b3d-8564-955b9ae2b380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399241361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.2399241361
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1336225085
Short name T406
Test name
Test status
Simulation time 2365248474 ps
CPU time 8.44 seconds
Started May 30 02:23:05 PM PDT 24
Finished May 30 02:23:14 PM PDT 24
Peak memory 218672 kb
Host smart-a35d3cb4-49b8-4791-b340-ad95e8c57d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336225085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1336225085
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2384183116
Short name T491
Test name
Test status
Simulation time 243746465 ps
CPU time 1.05 seconds
Started May 30 02:23:03 PM PDT 24
Finished May 30 02:23:05 PM PDT 24
Peak memory 218020 kb
Host smart-b4ffdbd0-5465-43b8-b535-37feacc1ec36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384183116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2384183116
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.1989349802
Short name T177
Test name
Test status
Simulation time 215823856 ps
CPU time 0.89 seconds
Started May 30 02:23:16 PM PDT 24
Finished May 30 02:23:17 PM PDT 24
Peak memory 200668 kb
Host smart-650619e6-f895-4a24-9f15-5aec9404bdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989349802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1989349802
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2144634452
Short name T190
Test name
Test status
Simulation time 2079590759 ps
CPU time 7.48 seconds
Started May 30 02:23:07 PM PDT 24
Finished May 30 02:23:16 PM PDT 24
Peak memory 201044 kb
Host smart-8975d4f3-57f8-480b-a683-37820eb0a498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144634452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2144634452
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.482662293
Short name T311
Test name
Test status
Simulation time 182150128 ps
CPU time 1.29 seconds
Started May 30 02:23:02 PM PDT 24
Finished May 30 02:23:04 PM PDT 24
Peak memory 200956 kb
Host smart-3b9570c0-3d9d-4e9e-972a-e021a12abc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482662293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.482662293
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.3224185267
Short name T269
Test name
Test status
Simulation time 203568659 ps
CPU time 1.47 seconds
Started May 30 02:23:02 PM PDT 24
Finished May 30 02:23:04 PM PDT 24
Peak memory 201064 kb
Host smart-8b39f145-ce9f-4c13-9f40-e3c34a8a20fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224185267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3224185267
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.407413665
Short name T319
Test name
Test status
Simulation time 6802831233 ps
CPU time 26.73 seconds
Started May 30 02:23:03 PM PDT 24
Finished May 30 02:23:30 PM PDT 24
Peak memory 210096 kb
Host smart-b22f1139-d2c4-44c4-9272-66076532f24c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407413665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.407413665
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.1990252978
Short name T346
Test name
Test status
Simulation time 137534267 ps
CPU time 1.79 seconds
Started May 30 02:23:04 PM PDT 24
Finished May 30 02:23:07 PM PDT 24
Peak memory 200920 kb
Host smart-ff36c218-c59d-43cf-878d-7e9e26b79f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990252978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1990252978
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1129482770
Short name T186
Test name
Test status
Simulation time 281607634 ps
CPU time 1.6 seconds
Started May 30 02:23:08 PM PDT 24
Finished May 30 02:23:11 PM PDT 24
Peak memory 201044 kb
Host smart-7223bcf8-fdc6-447c-b9fe-3740e8595d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129482770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1129482770
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.4040178301
Short name T492
Test name
Test status
Simulation time 76400148 ps
CPU time 0.78 seconds
Started May 30 02:23:13 PM PDT 24
Finished May 30 02:23:15 PM PDT 24
Peak memory 200652 kb
Host smart-9b39e186-9749-4db5-ba68-766b1fcdf377
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040178301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.4040178301
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2504514305
Short name T524
Test name
Test status
Simulation time 1214323053 ps
CPU time 6.3 seconds
Started May 30 02:23:14 PM PDT 24
Finished May 30 02:23:21 PM PDT 24
Peak memory 218516 kb
Host smart-a88e7531-1ef4-422f-abc9-76ad17f9d9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504514305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2504514305
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1313450272
Short name T426
Test name
Test status
Simulation time 245371569 ps
CPU time 1.04 seconds
Started May 30 02:23:13 PM PDT 24
Finished May 30 02:23:15 PM PDT 24
Peak memory 218032 kb
Host smart-38ff17e4-6153-4355-8e3f-85c146c6bfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313450272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1313450272
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1704913758
Short name T247
Test name
Test status
Simulation time 229949420 ps
CPU time 0.92 seconds
Started May 30 02:23:03 PM PDT 24
Finished May 30 02:23:05 PM PDT 24
Peak memory 200688 kb
Host smart-448d3f2d-92f6-453f-bee5-aaf43c54d3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704913758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1704913758
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3112305715
Short name T425
Test name
Test status
Simulation time 2047371012 ps
CPU time 8.51 seconds
Started May 30 02:23:16 PM PDT 24
Finished May 30 02:23:25 PM PDT 24
Peak memory 201072 kb
Host smart-272c773c-4e1c-4ad2-92dc-bddc57c1de9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112305715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3112305715
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1749401116
Short name T440
Test name
Test status
Simulation time 98872196 ps
CPU time 1.17 seconds
Started May 30 02:23:07 PM PDT 24
Finished May 30 02:23:09 PM PDT 24
Peak memory 200852 kb
Host smart-b78e2fba-34b9-44d9-b61c-70ad4c19cd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749401116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1749401116
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1905970458
Short name T522
Test name
Test status
Simulation time 249486213 ps
CPU time 1.44 seconds
Started May 30 02:23:10 PM PDT 24
Finished May 30 02:23:13 PM PDT 24
Peak memory 201040 kb
Host smart-c7c33e59-2276-40e7-9c2e-7d642ed73771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905970458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1905970458
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1235638933
Short name T421
Test name
Test status
Simulation time 4358562946 ps
CPU time 18.93 seconds
Started May 30 02:23:15 PM PDT 24
Finished May 30 02:23:34 PM PDT 24
Peak memory 201228 kb
Host smart-dbf91f16-fda2-40d8-973b-f283e73fb256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235638933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1235638933
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.843092163
Short name T236
Test name
Test status
Simulation time 116576336 ps
CPU time 1.58 seconds
Started May 30 02:23:07 PM PDT 24
Finished May 30 02:23:09 PM PDT 24
Peak memory 200844 kb
Host smart-39f8a7b3-1140-493c-af97-86c4cab76f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843092163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.843092163
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.1700647584
Short name T372
Test name
Test status
Simulation time 114400760 ps
CPU time 0.93 seconds
Started May 30 02:23:02 PM PDT 24
Finished May 30 02:23:04 PM PDT 24
Peak memory 200828 kb
Host smart-4951a7a7-b980-4ccf-ab52-a028f1a6c067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700647584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1700647584
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2358511076
Short name T270
Test name
Test status
Simulation time 71653828 ps
CPU time 0.77 seconds
Started May 30 02:23:15 PM PDT 24
Finished May 30 02:23:17 PM PDT 24
Peak memory 200724 kb
Host smart-f6c934c8-79c1-4d76-b7d7-7b2ae677e6e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358511076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2358511076
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.203059058
Short name T313
Test name
Test status
Simulation time 244039338 ps
CPU time 1.09 seconds
Started May 30 02:23:18 PM PDT 24
Finished May 30 02:23:19 PM PDT 24
Peak memory 218004 kb
Host smart-ad877cb6-83d2-4281-84f2-6f712ff65d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203059058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.203059058
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2796770883
Short name T10
Test name
Test status
Simulation time 155274189 ps
CPU time 0.86 seconds
Started May 30 02:23:17 PM PDT 24
Finished May 30 02:23:18 PM PDT 24
Peak memory 200700 kb
Host smart-8172e85c-a382-433e-bbc5-63d1698e132b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796770883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2796770883
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3884517667
Short name T531
Test name
Test status
Simulation time 1463575181 ps
CPU time 5.84 seconds
Started May 30 02:23:16 PM PDT 24
Finished May 30 02:23:23 PM PDT 24
Peak memory 201060 kb
Host smart-7128154a-4ee0-451c-8e51-ab148d724bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884517667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3884517667
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1706593124
Short name T138
Test name
Test status
Simulation time 170165101 ps
CPU time 1.16 seconds
Started May 30 02:23:14 PM PDT 24
Finished May 30 02:23:16 PM PDT 24
Peak memory 200948 kb
Host smart-4336a003-1376-4418-80ac-7843d603e0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706593124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1706593124
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2027271105
Short name T46
Test name
Test status
Simulation time 194903502 ps
CPU time 1.45 seconds
Started May 30 02:23:14 PM PDT 24
Finished May 30 02:23:16 PM PDT 24
Peak memory 201084 kb
Host smart-a41b6d64-3490-45c1-8df5-369ee27f5bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027271105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2027271105
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.54159206
Short name T370
Test name
Test status
Simulation time 6832163635 ps
CPU time 30.46 seconds
Started May 30 02:23:16 PM PDT 24
Finished May 30 02:23:47 PM PDT 24
Peak memory 209408 kb
Host smart-c840eab7-a119-49e2-9589-ab63ae4725e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54159206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.54159206
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2008551944
Short name T48
Test name
Test status
Simulation time 149867647 ps
CPU time 1.86 seconds
Started May 30 02:23:14 PM PDT 24
Finished May 30 02:23:16 PM PDT 24
Peak memory 200864 kb
Host smart-b2c2c094-7bc0-412c-bfd2-5fb7a0e5a562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008551944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2008551944
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.2341119950
Short name T275
Test name
Test status
Simulation time 96112281 ps
CPU time 0.94 seconds
Started May 30 02:23:14 PM PDT 24
Finished May 30 02:23:16 PM PDT 24
Peak memory 200884 kb
Host smart-d1668633-cf9f-47e4-8c0f-396e96c51b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341119950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.2341119950
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2360192309
Short name T366
Test name
Test status
Simulation time 98654476 ps
CPU time 0.9 seconds
Started May 30 02:19:03 PM PDT 24
Finished May 30 02:19:06 PM PDT 24
Peak memory 200720 kb
Host smart-71ec9345-8bbd-4fc5-adca-e26b6a912ae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360192309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2360192309
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1599076911
Short name T485
Test name
Test status
Simulation time 1234877715 ps
CPU time 5.89 seconds
Started May 30 02:19:01 PM PDT 24
Finished May 30 02:19:08 PM PDT 24
Peak memory 230720 kb
Host smart-854c3a1b-232e-49fc-a277-a9319d8c3519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599076911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1599076911
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.984387853
Short name T483
Test name
Test status
Simulation time 244898584 ps
CPU time 1.06 seconds
Started May 30 02:18:57 PM PDT 24
Finished May 30 02:18:59 PM PDT 24
Peak memory 217956 kb
Host smart-d45168d8-acf8-461d-be33-f7ab64782460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984387853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.984387853
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3909942552
Short name T220
Test name
Test status
Simulation time 106235771 ps
CPU time 0.8 seconds
Started May 30 02:19:00 PM PDT 24
Finished May 30 02:19:03 PM PDT 24
Peak memory 200676 kb
Host smart-1a6eea88-70d7-4042-8cfb-7bb2f6bcb503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909942552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3909942552
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.563114300
Short name T287
Test name
Test status
Simulation time 1615386602 ps
CPU time 6.69 seconds
Started May 30 02:19:02 PM PDT 24
Finished May 30 02:19:10 PM PDT 24
Peak memory 201072 kb
Host smart-7078eb4c-0a59-40f5-be33-dd4615dae4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563114300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.563114300
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2678936057
Short name T206
Test name
Test status
Simulation time 154411805 ps
CPU time 1.16 seconds
Started May 30 02:19:01 PM PDT 24
Finished May 30 02:19:03 PM PDT 24
Peak memory 200844 kb
Host smart-f5460691-fe78-4155-b9dd-90934de5e8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678936057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2678936057
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3710394860
Short name T462
Test name
Test status
Simulation time 201359916 ps
CPU time 1.38 seconds
Started May 30 02:18:54 PM PDT 24
Finished May 30 02:18:57 PM PDT 24
Peak memory 200996 kb
Host smart-fdc1bb55-04e7-4e74-957f-8a8d6200fb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710394860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3710394860
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2202783345
Short name T198
Test name
Test status
Simulation time 489409717 ps
CPU time 2.46 seconds
Started May 30 02:18:56 PM PDT 24
Finished May 30 02:18:59 PM PDT 24
Peak memory 201092 kb
Host smart-da3a0fff-bd05-404d-b118-73559d33af57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202783345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2202783345
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.166894077
Short name T386
Test name
Test status
Simulation time 117363534 ps
CPU time 1.51 seconds
Started May 30 02:19:02 PM PDT 24
Finished May 30 02:19:05 PM PDT 24
Peak memory 200852 kb
Host smart-8e8d1db1-3a5c-4364-b8fe-910e59f9b473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166894077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.166894077
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2859703006
Short name T307
Test name
Test status
Simulation time 175193011 ps
CPU time 1.08 seconds
Started May 30 02:18:52 PM PDT 24
Finished May 30 02:18:54 PM PDT 24
Peak memory 200880 kb
Host smart-565000bd-0610-459d-bdd8-6ce7bc582626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859703006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2859703006
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.733595809
Short name T135
Test name
Test status
Simulation time 118872681 ps
CPU time 0.95 seconds
Started May 30 02:19:10 PM PDT 24
Finished May 30 02:19:12 PM PDT 24
Peak memory 200724 kb
Host smart-b8c89e46-6c52-4f87-8a91-d4cff5798480
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733595809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.733595809
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3848130840
Short name T38
Test name
Test status
Simulation time 1896208905 ps
CPU time 6.7 seconds
Started May 30 02:19:01 PM PDT 24
Finished May 30 02:19:09 PM PDT 24
Peak memory 222472 kb
Host smart-d9afffa0-8c06-406a-b90b-397120f36444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848130840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3848130840
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3065515312
Short name T363
Test name
Test status
Simulation time 244617580 ps
CPU time 1.09 seconds
Started May 30 02:19:09 PM PDT 24
Finished May 30 02:19:11 PM PDT 24
Peak memory 218132 kb
Host smart-66676468-66fb-4d0f-bcd3-d46009e2d760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065515312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3065515312
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2498093866
Short name T18
Test name
Test status
Simulation time 151325945 ps
CPU time 0.84 seconds
Started May 30 02:19:02 PM PDT 24
Finished May 30 02:19:05 PM PDT 24
Peak memory 200700 kb
Host smart-59f883ae-7b15-457e-b68c-c502e7972832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498093866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2498093866
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1219186301
Short name T314
Test name
Test status
Simulation time 1569590522 ps
CPU time 6.11 seconds
Started May 30 02:19:02 PM PDT 24
Finished May 30 02:19:10 PM PDT 24
Peak memory 201064 kb
Host smart-84e25f92-afe2-44cd-875b-a1c94002afa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219186301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1219186301
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.692845411
Short name T463
Test name
Test status
Simulation time 104617721 ps
CPU time 1.06 seconds
Started May 30 02:19:01 PM PDT 24
Finished May 30 02:19:04 PM PDT 24
Peak memory 200912 kb
Host smart-1e9a6798-635b-4df0-89ae-7b8de1ccf980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692845411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.692845411
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.971085772
Short name T478
Test name
Test status
Simulation time 117193963 ps
CPU time 1.24 seconds
Started May 30 02:19:01 PM PDT 24
Finished May 30 02:19:04 PM PDT 24
Peak memory 201068 kb
Host smart-b480f3bb-f65e-47c2-81a0-4cebbb509988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971085772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.971085772
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.842841431
Short name T227
Test name
Test status
Simulation time 502318084 ps
CPU time 2.47 seconds
Started May 30 02:19:08 PM PDT 24
Finished May 30 02:19:12 PM PDT 24
Peak memory 201084 kb
Host smart-a6c111fe-552e-4649-9103-5a86443220f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842841431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.842841431
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1310397315
Short name T171
Test name
Test status
Simulation time 371286573 ps
CPU time 2.19 seconds
Started May 30 02:19:01 PM PDT 24
Finished May 30 02:19:05 PM PDT 24
Peak memory 200816 kb
Host smart-5f5d8866-26ad-43ea-8861-c64c81da46fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310397315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1310397315
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3883868158
Short name T324
Test name
Test status
Simulation time 89701802 ps
CPU time 0.93 seconds
Started May 30 02:19:01 PM PDT 24
Finished May 30 02:19:04 PM PDT 24
Peak memory 200904 kb
Host smart-b8216dc8-b26f-4e78-89c8-4e8a03a61d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883868158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3883868158
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1318162617
Short name T330
Test name
Test status
Simulation time 61166068 ps
CPU time 0.78 seconds
Started May 30 02:19:09 PM PDT 24
Finished May 30 02:19:11 PM PDT 24
Peak memory 200648 kb
Host smart-ff9a7e39-7b8b-4e71-a6d7-8c9833c87fca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318162617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1318162617
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1609898182
Short name T43
Test name
Test status
Simulation time 2365265638 ps
CPU time 7.87 seconds
Started May 30 02:19:09 PM PDT 24
Finished May 30 02:19:18 PM PDT 24
Peak memory 218584 kb
Host smart-d580cd1e-8ec3-4c4f-85b6-11027107e776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609898182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1609898182
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3738599259
Short name T184
Test name
Test status
Simulation time 245071496 ps
CPU time 1.1 seconds
Started May 30 02:19:12 PM PDT 24
Finished May 30 02:19:14 PM PDT 24
Peak memory 218196 kb
Host smart-fd7455f2-1758-4b28-969e-2c23893d8685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738599259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3738599259
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.4168101214
Short name T393
Test name
Test status
Simulation time 213405395 ps
CPU time 0.92 seconds
Started May 30 02:19:09 PM PDT 24
Finished May 30 02:19:12 PM PDT 24
Peak memory 200692 kb
Host smart-5dadb0c8-8776-47e4-9dae-9d69530db5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168101214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.4168101214
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.2130989116
Short name T434
Test name
Test status
Simulation time 818363618 ps
CPU time 4.04 seconds
Started May 30 02:19:11 PM PDT 24
Finished May 30 02:19:16 PM PDT 24
Peak memory 201088 kb
Host smart-abad079c-707c-4295-b9c7-233658d5b6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130989116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2130989116
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2895113577
Short name T395
Test name
Test status
Simulation time 136524363 ps
CPU time 1.17 seconds
Started May 30 02:19:09 PM PDT 24
Finished May 30 02:19:11 PM PDT 24
Peak memory 200896 kb
Host smart-bd7a5162-b802-49b0-8385-a3cbf67b2ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895113577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2895113577
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3307087352
Short name T71
Test name
Test status
Simulation time 197691347 ps
CPU time 1.36 seconds
Started May 30 02:19:11 PM PDT 24
Finished May 30 02:19:14 PM PDT 24
Peak memory 201020 kb
Host smart-a08248fa-ae70-438e-9082-800ca35d58ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307087352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3307087352
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.547407526
Short name T302
Test name
Test status
Simulation time 15603777249 ps
CPU time 56.35 seconds
Started May 30 02:19:12 PM PDT 24
Finished May 30 02:20:10 PM PDT 24
Peak memory 209368 kb
Host smart-75cd19d9-aee8-4162-9e6e-a8fd67141217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547407526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.547407526
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.2877893062
Short name T172
Test name
Test status
Simulation time 289358728 ps
CPU time 2 seconds
Started May 30 02:19:08 PM PDT 24
Finished May 30 02:19:10 PM PDT 24
Peak memory 200852 kb
Host smart-c5d24b10-ebf2-4b40-941d-e8f81466e3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877893062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2877893062
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1330981839
Short name T271
Test name
Test status
Simulation time 256036779 ps
CPU time 1.48 seconds
Started May 30 02:19:12 PM PDT 24
Finished May 30 02:19:14 PM PDT 24
Peak memory 201008 kb
Host smart-a2cfb112-0f2e-4873-a063-4ec2935f007d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330981839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1330981839
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1021611299
Short name T152
Test name
Test status
Simulation time 69191115 ps
CPU time 0.77 seconds
Started May 30 02:19:10 PM PDT 24
Finished May 30 02:19:12 PM PDT 24
Peak memory 200372 kb
Host smart-66d82db5-9ae5-4f7c-b530-c9eebf509c44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021611299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1021611299
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3463324127
Short name T36
Test name
Test status
Simulation time 1920847223 ps
CPU time 6.84 seconds
Started May 30 02:19:16 PM PDT 24
Finished May 30 02:19:24 PM PDT 24
Peak memory 222596 kb
Host smart-950b6c56-f39b-4c14-ab2e-30e166782a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463324127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3463324127
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2138417870
Short name T396
Test name
Test status
Simulation time 244989395 ps
CPU time 1 seconds
Started May 30 02:19:10 PM PDT 24
Finished May 30 02:19:12 PM PDT 24
Peak memory 218008 kb
Host smart-e025e6e5-0122-44ea-9779-8f15efaadee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138417870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2138417870
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3434295517
Short name T416
Test name
Test status
Simulation time 152412036 ps
CPU time 0.87 seconds
Started May 30 02:19:10 PM PDT 24
Finished May 30 02:19:12 PM PDT 24
Peak memory 200676 kb
Host smart-ee108c65-99ad-4030-8e0c-95aa48c94430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434295517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3434295517
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.4080056318
Short name T487
Test name
Test status
Simulation time 860323189 ps
CPU time 4.49 seconds
Started May 30 02:19:16 PM PDT 24
Finished May 30 02:19:21 PM PDT 24
Peak memory 201064 kb
Host smart-895dc71e-3dc1-4d6e-b9ce-7006cd054f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080056318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.4080056318
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3411824856
Short name T444
Test name
Test status
Simulation time 109489449 ps
CPU time 1.01 seconds
Started May 30 02:19:14 PM PDT 24
Finished May 30 02:19:16 PM PDT 24
Peak memory 200872 kb
Host smart-702ef469-12d5-4c21-b2c6-d9e25199343b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411824856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3411824856
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2445688622
Short name T284
Test name
Test status
Simulation time 112707172 ps
CPU time 1.19 seconds
Started May 30 02:19:08 PM PDT 24
Finished May 30 02:19:10 PM PDT 24
Peak memory 201088 kb
Host smart-dfe3e0b8-77af-4c58-a7a0-8941c0e3b0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445688622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2445688622
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.3617269370
Short name T180
Test name
Test status
Simulation time 4287888886 ps
CPU time 21.55 seconds
Started May 30 02:19:12 PM PDT 24
Finished May 30 02:19:35 PM PDT 24
Peak memory 210208 kb
Host smart-898277f3-6885-462f-9d69-49271d9cc668
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617269370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3617269370
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3751229224
Short name T279
Test name
Test status
Simulation time 145156868 ps
CPU time 1.89 seconds
Started May 30 02:19:10 PM PDT 24
Finished May 30 02:19:13 PM PDT 24
Peak memory 208884 kb
Host smart-20d1e43a-7ca4-40eb-b80f-e866b4a2669c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751229224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3751229224
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.3991965790
Short name T306
Test name
Test status
Simulation time 207947252 ps
CPU time 1.3 seconds
Started May 30 02:19:10 PM PDT 24
Finished May 30 02:19:12 PM PDT 24
Peak memory 200872 kb
Host smart-bb53f07d-ddb4-4a63-9514-4279c76b315e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991965790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3991965790
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2525387612
Short name T427
Test name
Test status
Simulation time 73999707 ps
CPU time 0.79 seconds
Started May 30 02:19:20 PM PDT 24
Finished May 30 02:19:22 PM PDT 24
Peak memory 200704 kb
Host smart-f8340bbe-7527-4893-a147-e57c05f619a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525387612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2525387612
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.441597777
Short name T37
Test name
Test status
Simulation time 1228994636 ps
CPU time 5.77 seconds
Started May 30 02:19:20 PM PDT 24
Finished May 30 02:19:27 PM PDT 24
Peak memory 230276 kb
Host smart-49234643-71c3-4770-ad66-8ae95b9876f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441597777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.441597777
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2397967831
Short name T480
Test name
Test status
Simulation time 244076785 ps
CPU time 1.2 seconds
Started May 30 02:19:20 PM PDT 24
Finished May 30 02:19:22 PM PDT 24
Peak memory 218036 kb
Host smart-10a52e2c-dac8-4200-8cec-9996d2185953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397967831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2397967831
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2132636747
Short name T388
Test name
Test status
Simulation time 185455029 ps
CPU time 0.92 seconds
Started May 30 02:19:11 PM PDT 24
Finished May 30 02:19:13 PM PDT 24
Peak memory 200680 kb
Host smart-de6c5982-9618-47f4-8463-40b775a6cbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132636747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2132636747
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.611891984
Short name T96
Test name
Test status
Simulation time 908237667 ps
CPU time 5.23 seconds
Started May 30 02:19:20 PM PDT 24
Finished May 30 02:19:26 PM PDT 24
Peak memory 201084 kb
Host smart-6e32d130-932e-482f-88d6-8d7241db993b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611891984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.611891984
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.3355388267
Short name T380
Test name
Test status
Simulation time 179355741 ps
CPU time 1.19 seconds
Started May 30 02:19:21 PM PDT 24
Finished May 30 02:19:23 PM PDT 24
Peak memory 200860 kb
Host smart-891e8af0-da6c-4db2-896c-96a97616d8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355388267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.3355388267
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.633910742
Short name T326
Test name
Test status
Simulation time 117202714 ps
CPU time 1.25 seconds
Started May 30 02:19:10 PM PDT 24
Finished May 30 02:19:12 PM PDT 24
Peak memory 201072 kb
Host smart-1cc18a28-d14b-4cf8-9381-6a23b4be9c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633910742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.633910742
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3151549357
Short name T7
Test name
Test status
Simulation time 615710300 ps
CPU time 2.69 seconds
Started May 30 02:19:20 PM PDT 24
Finished May 30 02:19:24 PM PDT 24
Peak memory 201088 kb
Host smart-17923ca8-4804-4ef8-9c6a-327db26746be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151549357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3151549357
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3454904184
Short name T539
Test name
Test status
Simulation time 369613095 ps
CPU time 2.58 seconds
Started May 30 02:19:20 PM PDT 24
Finished May 30 02:19:23 PM PDT 24
Peak memory 200852 kb
Host smart-ad2023fc-5b15-4151-b299-9c24c29d0dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454904184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3454904184
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.328374522
Short name T448
Test name
Test status
Simulation time 62784250 ps
CPU time 0.82 seconds
Started May 30 02:19:21 PM PDT 24
Finished May 30 02:19:23 PM PDT 24
Peak memory 200836 kb
Host smart-1c85c53e-7f4f-47d6-af68-240e24173339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328374522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.328374522
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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