Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8090 |
1 |
|
|
T4 |
15 |
|
T7 |
20 |
|
T8 |
19 |
auto[1] |
10968 |
1 |
|
|
T1 |
4 |
|
T2 |
4 |
|
T4 |
86 |
Summary for Variable reset_info_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for reset_info_cp
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
6035 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
reset_info_cp[1] |
6345 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
1 |
reset_info_cp[2] |
2906 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
17 |
reset_info_cp[4] |
3830 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
19 |
reset_info_cp[8] |
102 |
1 |
|
|
T4 |
1 |
|
T23 |
1 |
|
T28 |
1 |
reset_info_cp[16] |
115 |
1 |
|
|
T4 |
1 |
|
T7 |
1 |
|
T8 |
1 |
reset_info_cp[32] |
119 |
1 |
|
|
T4 |
1 |
|
T10 |
2 |
|
T24 |
1 |
reset_info_cp[64] |
124 |
1 |
|
|
T4 |
1 |
|
T115 |
2 |
|
T68 |
1 |
reset_info_cp[128] |
102 |
1 |
|
|
T4 |
1 |
|
T7 |
1 |
|
T13 |
1 |
Summary for Cross capture_cross
Samples crossed: reset_info_cp enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for capture_cross
Bins
reset_info_cp | enable_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
reset_info_cp[1] |
auto[0] |
3039 |
1 |
|
|
T4 |
15 |
|
T7 |
20 |
|
T8 |
19 |
reset_info_cp[1] |
auto[1] |
2686 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
11 |
reset_info_cp[2] |
auto[0] |
948 |
1 |
|
|
T9 |
13 |
|
T10 |
5 |
|
T13 |
5 |
reset_info_cp[2] |
auto[1] |
1958 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
17 |
reset_info_cp[4] |
auto[0] |
1376 |
1 |
|
|
T9 |
29 |
|
T10 |
6 |
|
T13 |
6 |
reset_info_cp[4] |
auto[1] |
2454 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
19 |
reset_info_cp[8] |
auto[0] |
36 |
1 |
|
|
T23 |
1 |
|
T28 |
1 |
|
T68 |
1 |
reset_info_cp[8] |
auto[1] |
66 |
1 |
|
|
T4 |
1 |
|
T31 |
1 |
|
T84 |
1 |
reset_info_cp[16] |
auto[0] |
46 |
1 |
|
|
T68 |
1 |
|
T120 |
1 |
|
T87 |
1 |
reset_info_cp[16] |
auto[1] |
69 |
1 |
|
|
T4 |
1 |
|
T7 |
1 |
|
T8 |
1 |
reset_info_cp[32] |
auto[0] |
48 |
1 |
|
|
T10 |
1 |
|
T24 |
1 |
|
T67 |
1 |
reset_info_cp[32] |
auto[1] |
71 |
1 |
|
|
T4 |
1 |
|
T10 |
1 |
|
T28 |
3 |
reset_info_cp[64] |
auto[0] |
64 |
1 |
|
|
T70 |
1 |
|
T71 |
1 |
|
T89 |
3 |
reset_info_cp[64] |
auto[1] |
60 |
1 |
|
|
T4 |
1 |
|
T115 |
2 |
|
T68 |
1 |
reset_info_cp[128] |
auto[0] |
41 |
1 |
|
|
T24 |
1 |
|
T28 |
2 |
|
T68 |
1 |
reset_info_cp[128] |
auto[1] |
61 |
1 |
|
|
T4 |
1 |
|
T7 |
1 |
|
T13 |
1 |