Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg
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Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv



Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 16 0 16 100.00


Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable_cp 2 0 2 100.00 100 1 1 2
reset_info_cp 8 0 8 100.00 100 1 1 0


Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
capture_cross 16 0 16 100.00 100 1 1 0


Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8090 1 T4 15 T7 20 T8 19
auto[1] 10968 1 T1 4 T2 4 T4 86



Summary for Variable reset_info_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for reset_info_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 6035 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
reset_info_cp[1] 6345 1 T1 2 T2 2 T3 1
reset_info_cp[2] 2906 1 T1 1 T2 1 T4 17
reset_info_cp[4] 3830 1 T1 1 T2 1 T4 19
reset_info_cp[8] 102 1 T4 1 T23 1 T28 1
reset_info_cp[16] 115 1 T4 1 T7 1 T8 1
reset_info_cp[32] 119 1 T4 1 T10 2 T24 1
reset_info_cp[64] 124 1 T4 1 T115 2 T68 1
reset_info_cp[128] 102 1 T4 1 T7 1 T13 1



Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for capture_cross

Bins
reset_info_cpenable_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
reset_info_cp[1] auto[0] 3039 1 T4 15 T7 20 T8 19
reset_info_cp[1] auto[1] 2686 1 T1 1 T2 1 T4 11
reset_info_cp[2] auto[0] 948 1 T9 13 T10 5 T13 5
reset_info_cp[2] auto[1] 1958 1 T1 1 T2 1 T4 17
reset_info_cp[4] auto[0] 1376 1 T9 29 T10 6 T13 6
reset_info_cp[4] auto[1] 2454 1 T1 1 T2 1 T4 19
reset_info_cp[8] auto[0] 36 1 T23 1 T28 1 T68 1
reset_info_cp[8] auto[1] 66 1 T4 1 T31 1 T84 1
reset_info_cp[16] auto[0] 46 1 T68 1 T120 1 T87 1
reset_info_cp[16] auto[1] 69 1 T4 1 T7 1 T8 1
reset_info_cp[32] auto[0] 48 1 T10 1 T24 1 T67 1
reset_info_cp[32] auto[1] 71 1 T4 1 T10 1 T28 3
reset_info_cp[64] auto[0] 64 1 T70 1 T71 1 T89 3
reset_info_cp[64] auto[1] 60 1 T4 1 T115 2 T68 1
reset_info_cp[128] auto[0] 41 1 T24 1 T28 2 T68 1
reset_info_cp[128] auto[1] 61 1 T4 1 T7 1 T13 1

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