Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8029

1

T4

15

T7

20

T8

19

auto[1]

11029

1

T1

4

T2

4

T4

86

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6035	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6345	1			T1	2		T2	2		T3	1
reset_info_cp[2]	2906	1			T1	1		T2	1		T4	17
reset_info_cp[4]	3830	1			T1	1		T2	1		T4	19
reset_info_cp[8]	102	1			T4	1		T23	1		T28	1
reset_info_cp[16]	115	1			T4	1		T7	1		T8	1
reset_info_cp[32]	119	1			T4	1		T10	2		T24	1
reset_info_cp[64]	124	1			T4	1		T115	2		T68	1
reset_info_cp[128]	102	1			T4	1		T7	1		T13	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3025	1			T4	15		T7	20		T8	19
reset_info_cp[1]	auto[1]	2700	1			T1	1		T2	1		T4	11
reset_info_cp[2]	auto[0]	879	1			T9	13		T10	4		T13	5
reset_info_cp[2]	auto[1]	2027	1			T1	1		T2	1		T4	17
reset_info_cp[4]	auto[0]	1349	1			T9	22		T10	5		T13	5
reset_info_cp[4]	auto[1]	2481	1			T1	1		T2	1		T4	19
reset_info_cp[8]	auto[0]	39	1			T23	1		T68	1		T119	1
reset_info_cp[8]	auto[1]	63	1			T4	1		T28	1		T31	1
reset_info_cp[16]	auto[0]	50	1			T67	1		T68	1		T120	1
reset_info_cp[16]	auto[1]	65	1			T4	1		T7	1		T8	1
reset_info_cp[32]	auto[0]	48	1			T10	2		T24	1		T28	1
reset_info_cp[32]	auto[1]	71	1			T4	1		T28	2		T32	3
reset_info_cp[64]	auto[0]	55	1			T70	2		T83	1		T71	1
reset_info_cp[64]	auto[1]	69	1			T4	1		T115	2		T68	1
reset_info_cp[128]	auto[0]	52	1			T24	1		T68	1		T70	2
reset_info_cp[128]	auto[1]	50	1			T4	1		T7	1		T13	1