Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T535 /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1635940794 Jun 02 12:43:56 PM PDT 24 Jun 02 12:43:57 PM PDT 24 243315071 ps
T536 /workspace/coverage/default/38.rstmgr_reset.763705964 Jun 02 12:44:34 PM PDT 24 Jun 02 12:44:40 PM PDT 24 1043030671 ps
T537 /workspace/coverage/default/32.rstmgr_sw_rst.855056253 Jun 02 12:44:22 PM PDT 24 Jun 02 12:44:24 PM PDT 24 266071684 ps
T538 /workspace/coverage/default/14.rstmgr_por_stretcher.2803652632 Jun 02 12:43:57 PM PDT 24 Jun 02 12:43:58 PM PDT 24 173785583 ps
T539 /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2432803608 Jun 02 12:44:12 PM PDT 24 Jun 02 12:44:19 PM PDT 24 1225627775 ps
T52 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.291403891 Jun 02 12:45:13 PM PDT 24 Jun 02 12:45:14 PM PDT 24 74579512 ps
T53 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3707525608 Jun 02 12:44:42 PM PDT 24 Jun 02 12:44:45 PM PDT 24 498540450 ps
T54 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2833050466 Jun 02 12:44:57 PM PDT 24 Jun 02 12:44:59 PM PDT 24 106402481 ps
T55 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1886587409 Jun 02 12:44:56 PM PDT 24 Jun 02 12:44:58 PM PDT 24 197648267 ps
T57 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.971211172 Jun 02 12:44:59 PM PDT 24 Jun 02 12:45:01 PM PDT 24 91360309 ps
T85 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3799448443 Jun 02 12:44:58 PM PDT 24 Jun 02 12:44:59 PM PDT 24 57580679 ps
T58 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1997717302 Jun 02 12:45:07 PM PDT 24 Jun 02 12:45:11 PM PDT 24 282741771 ps
T73 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3278967785 Jun 02 12:44:53 PM PDT 24 Jun 02 12:44:56 PM PDT 24 398543032 ps
T62 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3750495874 Jun 02 12:45:27 PM PDT 24 Jun 02 12:45:30 PM PDT 24 487408892 ps
T540 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2592308979 Jun 02 12:44:44 PM PDT 24 Jun 02 12:44:46 PM PDT 24 110740742 ps
T74 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.405988394 Jun 02 12:45:04 PM PDT 24 Jun 02 12:45:07 PM PDT 24 109789100 ps
T94 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2907849401 Jun 02 12:44:52 PM PDT 24 Jun 02 12:44:53 PM PDT 24 112864715 ps
T80 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1435360408 Jun 02 12:44:58 PM PDT 24 Jun 02 12:45:00 PM PDT 24 465903742 ps
T75 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3054371681 Jun 02 12:45:00 PM PDT 24 Jun 02 12:45:03 PM PDT 24 135860328 ps
T95 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2937813990 Jun 02 12:45:05 PM PDT 24 Jun 02 12:45:08 PM PDT 24 209868186 ps
T96 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1669333995 Jun 02 12:45:23 PM PDT 24 Jun 02 12:45:24 PM PDT 24 54949502 ps
T79 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3676202111 Jun 02 12:45:05 PM PDT 24 Jun 02 12:45:10 PM PDT 24 875797680 ps
T541 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2845036982 Jun 02 12:45:01 PM PDT 24 Jun 02 12:45:03 PM PDT 24 88244566 ps
T97 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2058714962 Jun 02 12:44:43 PM PDT 24 Jun 02 12:44:44 PM PDT 24 73821619 ps
T542 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1273994565 Jun 02 12:44:59 PM PDT 24 Jun 02 12:45:03 PM PDT 24 275243905 ps
T81 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3707387868 Jun 02 12:45:08 PM PDT 24 Jun 02 12:45:12 PM PDT 24 933293659 ps
T543 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3500877810 Jun 02 12:45:05 PM PDT 24 Jun 02 12:45:07 PM PDT 24 61738231 ps
T76 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2015383257 Jun 02 12:45:04 PM PDT 24 Jun 02 12:45:08 PM PDT 24 921001652 ps
T98 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.184017309 Jun 02 12:45:16 PM PDT 24 Jun 02 12:45:18 PM PDT 24 248290876 ps
T77 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3060621976 Jun 02 12:44:54 PM PDT 24 Jun 02 12:44:57 PM PDT 24 155162525 ps
T99 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.15926869 Jun 02 12:44:57 PM PDT 24 Jun 02 12:44:59 PM PDT 24 120856333 ps
T100 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4283124012 Jun 02 12:45:06 PM PDT 24 Jun 02 12:45:13 PM PDT 24 81650870 ps
T78 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.4009413562 Jun 02 12:45:04 PM PDT 24 Jun 02 12:45:08 PM PDT 24 779781187 ps
T544 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1764511184 Jun 02 12:45:03 PM PDT 24 Jun 02 12:45:05 PM PDT 24 79829708 ps
T101 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2958352056 Jun 02 12:44:58 PM PDT 24 Jun 02 12:45:02 PM PDT 24 564150565 ps
T545 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2593012701 Jun 02 12:45:03 PM PDT 24 Jun 02 12:45:05 PM PDT 24 217609631 ps
T546 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3266012549 Jun 02 12:45:03 PM PDT 24 Jun 02 12:45:05 PM PDT 24 126539147 ps
T547 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.534975826 Jun 02 12:44:43 PM PDT 24 Jun 02 12:44:45 PM PDT 24 220906570 ps
T548 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.11526820 Jun 02 12:44:52 PM PDT 24 Jun 02 12:44:54 PM PDT 24 127325550 ps
T549 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1337404109 Jun 02 12:44:56 PM PDT 24 Jun 02 12:44:58 PM PDT 24 261484481 ps
T550 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.568537952 Jun 02 12:45:27 PM PDT 24 Jun 02 12:45:29 PM PDT 24 96495139 ps
T118 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.4099826346 Jun 02 12:45:00 PM PDT 24 Jun 02 12:45:03 PM PDT 24 466289791 ps
T551 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2829805593 Jun 02 12:45:17 PM PDT 24 Jun 02 12:45:20 PM PDT 24 195910352 ps
T552 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.185016308 Jun 02 12:44:53 PM PDT 24 Jun 02 12:44:55 PM PDT 24 175488673 ps
T553 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3284355032 Jun 02 12:45:06 PM PDT 24 Jun 02 12:45:09 PM PDT 24 167526684 ps
T554 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3090794574 Jun 02 12:44:57 PM PDT 24 Jun 02 12:45:00 PM PDT 24 381274637 ps
T555 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3151306014 Jun 02 12:45:05 PM PDT 24 Jun 02 12:45:07 PM PDT 24 64692868 ps
T556 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.676634850 Jun 02 12:44:51 PM PDT 24 Jun 02 12:44:53 PM PDT 24 137693143 ps
T557 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3199361605 Jun 02 12:45:11 PM PDT 24 Jun 02 12:45:13 PM PDT 24 169612650 ps
T558 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2413563896 Jun 02 12:45:05 PM PDT 24 Jun 02 12:45:07 PM PDT 24 78652893 ps
T559 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.710164542 Jun 02 12:45:07 PM PDT 24 Jun 02 12:45:14 PM PDT 24 115999105 ps
T560 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1937835883 Jun 02 12:45:03 PM PDT 24 Jun 02 12:45:05 PM PDT 24 252912913 ps
T561 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.508655891 Jun 02 12:45:21 PM PDT 24 Jun 02 12:45:23 PM PDT 24 156324823 ps
T562 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.816714567 Jun 02 12:45:18 PM PDT 24 Jun 02 12:45:20 PM PDT 24 127072674 ps
T563 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.269495295 Jun 02 12:44:51 PM PDT 24 Jun 02 12:44:54 PM PDT 24 196413149 ps
T564 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1413533061 Jun 02 12:44:42 PM PDT 24 Jun 02 12:44:44 PM PDT 24 158457214 ps
T565 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2707313968 Jun 02 12:45:04 PM PDT 24 Jun 02 12:45:09 PM PDT 24 782074980 ps
T566 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.818927245 Jun 02 12:44:54 PM PDT 24 Jun 02 12:44:56 PM PDT 24 100523433 ps
T567 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1292173390 Jun 02 12:45:13 PM PDT 24 Jun 02 12:45:15 PM PDT 24 109408378 ps
T568 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1260835550 Jun 02 12:45:07 PM PDT 24 Jun 02 12:45:10 PM PDT 24 197532456 ps
T107 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1357612252 Jun 02 12:44:53 PM PDT 24 Jun 02 12:44:56 PM PDT 24 414164619 ps
T569 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.210773357 Jun 02 12:45:06 PM PDT 24 Jun 02 12:45:09 PM PDT 24 118486099 ps
T570 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2024503691 Jun 02 12:45:08 PM PDT 24 Jun 02 12:45:10 PM PDT 24 86071548 ps
T571 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1448373681 Jun 02 12:45:06 PM PDT 24 Jun 02 12:45:10 PM PDT 24 293027258 ps
T102 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1088585239 Jun 02 12:44:45 PM PDT 24 Jun 02 12:44:49 PM PDT 24 1067125410 ps
T572 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1258632379 Jun 02 12:45:06 PM PDT 24 Jun 02 12:45:11 PM PDT 24 406657673 ps
T103 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1661328495 Jun 02 12:44:51 PM PDT 24 Jun 02 12:44:53 PM PDT 24 540651824 ps
T573 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1384396604 Jun 02 12:44:47 PM PDT 24 Jun 02 12:44:49 PM PDT 24 95656935 ps
T574 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.259265188 Jun 02 12:45:07 PM PDT 24 Jun 02 12:45:10 PM PDT 24 144111987 ps
T575 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.987800342 Jun 02 12:44:58 PM PDT 24 Jun 02 12:45:01 PM PDT 24 137608922 ps
T576 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3396714428 Jun 02 12:45:06 PM PDT 24 Jun 02 12:45:09 PM PDT 24 110404423 ps
T108 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1460597171 Jun 02 12:45:09 PM PDT 24 Jun 02 12:45:13 PM PDT 24 905332966 ps
T577 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3101496673 Jun 02 12:45:18 PM PDT 24 Jun 02 12:45:19 PM PDT 24 69862824 ps
T578 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1976094083 Jun 02 12:44:53 PM PDT 24 Jun 02 12:44:54 PM PDT 24 117866316 ps
T579 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.105943343 Jun 02 12:45:15 PM PDT 24 Jun 02 12:45:18 PM PDT 24 419279896 ps
T580 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1830315846 Jun 02 12:45:13 PM PDT 24 Jun 02 12:45:15 PM PDT 24 261530461 ps
T104 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1050188306 Jun 02 12:45:07 PM PDT 24 Jun 02 12:45:11 PM PDT 24 426669159 ps
T581 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1147209550 Jun 02 12:44:56 PM PDT 24 Jun 02 12:45:00 PM PDT 24 785169476 ps
T582 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.119467667 Jun 02 12:45:04 PM PDT 24 Jun 02 12:45:07 PM PDT 24 71524799 ps
T583 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.440216091 Jun 02 12:45:03 PM PDT 24 Jun 02 12:45:06 PM PDT 24 92871969 ps
T584 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.167473423 Jun 02 12:44:53 PM PDT 24 Jun 02 12:44:56 PM PDT 24 483287701 ps
T585 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3794943347 Jun 02 12:44:59 PM PDT 24 Jun 02 12:45:01 PM PDT 24 187450429 ps
T586 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.4138485028 Jun 02 12:45:04 PM PDT 24 Jun 02 12:45:06 PM PDT 24 87367048 ps
T587 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2028717117 Jun 02 12:45:01 PM PDT 24 Jun 02 12:45:04 PM PDT 24 129242255 ps
T588 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1405591534 Jun 02 12:45:17 PM PDT 24 Jun 02 12:45:19 PM PDT 24 115651392 ps
T589 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3963646354 Jun 02 12:45:03 PM PDT 24 Jun 02 12:45:05 PM PDT 24 144195816 ps
T590 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1493618474 Jun 02 12:44:49 PM PDT 24 Jun 02 12:44:55 PM PDT 24 486110604 ps
T591 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.950926510 Jun 02 12:45:04 PM PDT 24 Jun 02 12:45:07 PM PDT 24 90453898 ps
T592 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.221186671 Jun 02 12:45:20 PM PDT 24 Jun 02 12:45:22 PM PDT 24 126781875 ps
T593 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.966435412 Jun 02 12:44:59 PM PDT 24 Jun 02 12:45:01 PM PDT 24 71065244 ps
T594 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3671998434 Jun 02 12:44:57 PM PDT 24 Jun 02 12:45:03 PM PDT 24 480160596 ps
T595 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3948314232 Jun 02 12:45:04 PM PDT 24 Jun 02 12:45:08 PM PDT 24 275824274 ps
T596 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1679588585 Jun 02 12:45:05 PM PDT 24 Jun 02 12:45:07 PM PDT 24 57035431 ps
T597 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.131103108 Jun 02 12:44:54 PM PDT 24 Jun 02 12:44:56 PM PDT 24 106445575 ps
T598 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2453632982 Jun 02 12:45:05 PM PDT 24 Jun 02 12:45:08 PM PDT 24 215278814 ps
T599 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2880183169 Jun 02 12:45:00 PM PDT 24 Jun 02 12:45:02 PM PDT 24 76196866 ps
T600 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.366267766 Jun 02 12:45:03 PM PDT 24 Jun 02 12:45:05 PM PDT 24 110606677 ps
T601 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1369302420 Jun 02 12:45:00 PM PDT 24 Jun 02 12:45:03 PM PDT 24 120689018 ps
T602 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2579288998 Jun 02 12:45:13 PM PDT 24 Jun 02 12:45:14 PM PDT 24 149692033 ps
T603 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3789889269 Jun 02 12:44:58 PM PDT 24 Jun 02 12:44:59 PM PDT 24 84360410 ps
T604 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3251671705 Jun 02 12:45:23 PM PDT 24 Jun 02 12:45:24 PM PDT 24 68699411 ps
T605 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2191786253 Jun 02 12:45:05 PM PDT 24 Jun 02 12:45:07 PM PDT 24 65618437 ps
T606 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1705162678 Jun 02 12:44:53 PM PDT 24 Jun 02 12:44:55 PM PDT 24 169440842 ps
T105 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2067263426 Jun 02 12:45:00 PM PDT 24 Jun 02 12:45:03 PM PDT 24 469955068 ps
T607 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3086275381 Jun 02 12:45:02 PM PDT 24 Jun 02 12:45:04 PM PDT 24 143578750 ps
T608 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3879277432 Jun 02 12:45:04 PM PDT 24 Jun 02 12:45:07 PM PDT 24 247447843 ps
T609 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1022800237 Jun 02 12:45:11 PM PDT 24 Jun 02 12:45:13 PM PDT 24 69980698 ps
T610 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2415399146 Jun 02 12:44:53 PM PDT 24 Jun 02 12:44:55 PM PDT 24 213529580 ps
T611 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1337934176 Jun 02 12:44:45 PM PDT 24 Jun 02 12:44:47 PM PDT 24 116534049 ps
T612 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1006414390 Jun 02 12:45:23 PM PDT 24 Jun 02 12:45:31 PM PDT 24 166024255 ps
T613 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1192418588 Jun 02 12:44:55 PM PDT 24 Jun 02 12:45:05 PM PDT 24 2292095550 ps
T614 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2263040062 Jun 02 12:44:51 PM PDT 24 Jun 02 12:44:53 PM PDT 24 114817955 ps
T615 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2785038060 Jun 02 12:45:21 PM PDT 24 Jun 02 12:45:22 PM PDT 24 197246650 ps
T106 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2097841652 Jun 02 12:45:01 PM PDT 24 Jun 02 12:45:05 PM PDT 24 853123187 ps
T616 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.956054579 Jun 02 12:45:12 PM PDT 24 Jun 02 12:45:14 PM PDT 24 124830642 ps
T617 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.479066731 Jun 02 12:45:00 PM PDT 24 Jun 02 12:45:02 PM PDT 24 68698129 ps
T618 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1412947766 Jun 02 12:44:39 PM PDT 24 Jun 02 12:44:41 PM PDT 24 146148008 ps
T619 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.663369629 Jun 02 12:44:59 PM PDT 24 Jun 02 12:45:05 PM PDT 24 809081862 ps
T620 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.246149670 Jun 02 12:45:15 PM PDT 24 Jun 02 12:45:16 PM PDT 24 79996458 ps
T109 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.578405287 Jun 02 12:45:04 PM PDT 24 Jun 02 12:45:07 PM PDT 24 418487348 ps

Test location /workspace/coverage/default/3.rstmgr_stress_all.3936800191
Short name T9
Test name
Test status
Simulation time 5649205501 ps
CPU time 21.13 seconds
Started Jun 02 12:43:42 PM PDT 24
Finished Jun 02 12:44:03 PM PDT 24
Peak memory 209176 kb
Host smart-ee8a119e-c85f-47d3-84dc-6849909654e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936800191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3936800191
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1815362270
Short name T49
Test name
Test status
Simulation time 427406913 ps
CPU time 2.56 seconds
Started Jun 02 12:43:56 PM PDT 24
Finished Jun 02 12:44:00 PM PDT 24
Peak memory 200748 kb
Host smart-d0049049-dd0d-42f4-96c9-a3a242077e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815362270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1815362270
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1886587409
Short name T55
Test name
Test status
Simulation time 197648267 ps
CPU time 1.36 seconds
Started Jun 02 12:44:56 PM PDT 24
Finished Jun 02 12:44:58 PM PDT 24
Peak memory 210996 kb
Host smart-ba4fd244-c84d-4813-82f0-70fd2be25773
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886587409 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1886587409
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1065710432
Short name T27
Test name
Test status
Simulation time 16845656474 ps
CPU time 25.77 seconds
Started Jun 02 12:43:38 PM PDT 24
Finished Jun 02 12:44:04 PM PDT 24
Peak memory 218348 kb
Host smart-b5ff8a59-3f7b-4f75-a747-4a9dcc6b7895
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065710432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1065710432
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2785136921
Short name T4
Test name
Test status
Simulation time 1905096221 ps
CPU time 7.56 seconds
Started Jun 02 12:44:01 PM PDT 24
Finished Jun 02 12:44:09 PM PDT 24
Peak memory 217328 kb
Host smart-82a1f969-bae5-4901-a320-d49c047af726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785136921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2785136921
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3676202111
Short name T79
Test name
Test status
Simulation time 875797680 ps
CPU time 3.49 seconds
Started Jun 02 12:45:05 PM PDT 24
Finished Jun 02 12:45:10 PM PDT 24
Peak memory 200528 kb
Host smart-c292fdc1-c4be-40e2-83b9-e6e91e00fed8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676202111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3676202111
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1098911945
Short name T88
Test name
Test status
Simulation time 9913865425 ps
CPU time 35.41 seconds
Started Jun 02 12:43:57 PM PDT 24
Finished Jun 02 12:44:33 PM PDT 24
Peak memory 209308 kb
Host smart-e0cd1198-7362-4ce1-a418-821ddee2b5ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098911945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1098911945
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.63788816
Short name T60
Test name
Test status
Simulation time 88371580 ps
CPU time 0.78 seconds
Started Jun 02 12:43:58 PM PDT 24
Finished Jun 02 12:43:59 PM PDT 24
Peak memory 200564 kb
Host smart-5f9e38af-4b80-4406-83d9-79c3cce9d9ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63788816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.63788816
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2958352056
Short name T101
Test name
Test status
Simulation time 564150565 ps
CPU time 3.77 seconds
Started Jun 02 12:44:58 PM PDT 24
Finished Jun 02 12:45:02 PM PDT 24
Peak memory 208752 kb
Host smart-25a0f09c-b81d-49ec-a51d-ad7a3178d38c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958352056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2958352056
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.889677615
Short name T117
Test name
Test status
Simulation time 98582402 ps
CPU time 1.03 seconds
Started Jun 02 12:43:59 PM PDT 24
Finished Jun 02 12:44:01 PM PDT 24
Peak memory 200856 kb
Host smart-1c5f3840-cc45-43e3-b89d-3e520ce90d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889677615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.889677615
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2036482689
Short name T68
Test name
Test status
Simulation time 111860086 ps
CPU time 1.03 seconds
Started Jun 02 12:44:04 PM PDT 24
Finished Jun 02 12:44:06 PM PDT 24
Peak memory 200808 kb
Host smart-343eacc6-cfbf-4ee3-a6e8-102426a1e658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036482689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2036482689
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.670867527
Short name T32
Test name
Test status
Simulation time 1226623121 ps
CPU time 5.43 seconds
Started Jun 02 12:44:11 PM PDT 24
Finished Jun 02 12:44:17 PM PDT 24
Peak memory 218416 kb
Host smart-42c002c8-a110-4fe6-b2e2-44ea3daa6e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670867527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.670867527
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1357612252
Short name T107
Test name
Test status
Simulation time 414164619 ps
CPU time 1.92 seconds
Started Jun 02 12:44:53 PM PDT 24
Finished Jun 02 12:44:56 PM PDT 24
Peak memory 200632 kb
Host smart-6243122d-77de-493b-8dc3-432e37b74b44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357612252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1357612252
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3414675367
Short name T43
Test name
Test status
Simulation time 1876383808 ps
CPU time 8.2 seconds
Started Jun 02 12:44:32 PM PDT 24
Finished Jun 02 12:44:41 PM PDT 24
Peak memory 221572 kb
Host smart-fc1e81c9-3f23-46e1-8bc8-34cbfecb51ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414675367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3414675367
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1337404109
Short name T549
Test name
Test status
Simulation time 261484481 ps
CPU time 2.06 seconds
Started Jun 02 12:44:56 PM PDT 24
Finished Jun 02 12:44:58 PM PDT 24
Peak memory 208804 kb
Host smart-88c8319c-1cb8-48e5-a01b-3f10206c4526
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337404109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1337404109
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1088585239
Short name T102
Test name
Test status
Simulation time 1067125410 ps
CPU time 3.36 seconds
Started Jun 02 12:44:45 PM PDT 24
Finished Jun 02 12:44:49 PM PDT 24
Peak memory 200552 kb
Host smart-9e2d7ff8-80d0-4240-96ec-f2a31a617ef6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088585239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1088585239
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2058714962
Short name T97
Test name
Test status
Simulation time 73821619 ps
CPU time 0.85 seconds
Started Jun 02 12:44:43 PM PDT 24
Finished Jun 02 12:44:44 PM PDT 24
Peak memory 200260 kb
Host smart-afc5d8c6-6845-47d8-ac33-900595366e75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058714962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2058714962
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.660716329
Short name T17
Test name
Test status
Simulation time 161950438 ps
CPU time 0.87 seconds
Started Jun 02 12:44:00 PM PDT 24
Finished Jun 02 12:44:02 PM PDT 24
Peak memory 200576 kb
Host smart-7ab088cf-a814-483b-99d1-0a67fdb42509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660716329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.660716329
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1050188306
Short name T104
Test name
Test status
Simulation time 426669159 ps
CPU time 1.81 seconds
Started Jun 02 12:45:07 PM PDT 24
Finished Jun 02 12:45:11 PM PDT 24
Peak memory 200576 kb
Host smart-96382242-0fdf-4936-81d9-6d8cee46e07c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050188306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1050188306
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.14739560
Short name T175
Test name
Test status
Simulation time 130528633 ps
CPU time 1.52 seconds
Started Jun 02 12:43:57 PM PDT 24
Finished Jun 02 12:44:00 PM PDT 24
Peak memory 200764 kb
Host smart-b4dc3a6a-a33a-4252-a79a-28de599e21d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14739560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.14739560
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2592308979
Short name T540
Test name
Test status
Simulation time 110740742 ps
CPU time 1.32 seconds
Started Jun 02 12:44:44 PM PDT 24
Finished Jun 02 12:44:46 PM PDT 24
Peak memory 200484 kb
Host smart-6bb55202-087e-4c7c-afe4-f003c597db26
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592308979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
592308979
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1493618474
Short name T590
Test name
Test status
Simulation time 486110604 ps
CPU time 5.43 seconds
Started Jun 02 12:44:49 PM PDT 24
Finished Jun 02 12:44:55 PM PDT 24
Peak memory 200364 kb
Host smart-5203a697-8f7f-45bf-92b5-d712052bcd98
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493618474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
493618474
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2263040062
Short name T614
Test name
Test status
Simulation time 114817955 ps
CPU time 0.93 seconds
Started Jun 02 12:44:51 PM PDT 24
Finished Jun 02 12:44:53 PM PDT 24
Peak memory 200264 kb
Host smart-222a501e-add6-4816-a660-c1223861dd7b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263040062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
263040062
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1413533061
Short name T564
Test name
Test status
Simulation time 158457214 ps
CPU time 1.2 seconds
Started Jun 02 12:44:42 PM PDT 24
Finished Jun 02 12:44:44 PM PDT 24
Peak memory 200320 kb
Host smart-fd98d6e4-c5f4-4c26-8860-80850098d1b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413533061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1413533061
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.534975826
Short name T547
Test name
Test status
Simulation time 220906570 ps
CPU time 1.66 seconds
Started Jun 02 12:44:43 PM PDT 24
Finished Jun 02 12:44:45 PM PDT 24
Peak memory 208700 kb
Host smart-847f1cff-581c-4840-a96f-3739ac8f9ceb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534975826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.534975826
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3707525608
Short name T53
Test name
Test status
Simulation time 498540450 ps
CPU time 1.94 seconds
Started Jun 02 12:44:42 PM PDT 24
Finished Jun 02 12:44:45 PM PDT 24
Peak memory 200572 kb
Host smart-e7616f5b-5a14-4cf1-a19c-6fca3ae12bee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707525608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.3707525608
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3090794574
Short name T554
Test name
Test status
Simulation time 381274637 ps
CPU time 2.6 seconds
Started Jun 02 12:44:57 PM PDT 24
Finished Jun 02 12:45:00 PM PDT 24
Peak memory 200364 kb
Host smart-17f50fb2-5c20-48a2-a45a-6e953a2c1e8b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090794574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
090794574
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.663369629
Short name T619
Test name
Test status
Simulation time 809081862 ps
CPU time 4.92 seconds
Started Jun 02 12:44:59 PM PDT 24
Finished Jun 02 12:45:05 PM PDT 24
Peak memory 200492 kb
Host smart-f45649ec-138e-4899-a302-e2d31a7d2e62
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663369629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.663369629
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1412947766
Short name T618
Test name
Test status
Simulation time 146148008 ps
CPU time 0.94 seconds
Started Jun 02 12:44:39 PM PDT 24
Finished Jun 02 12:44:41 PM PDT 24
Peak memory 200592 kb
Host smart-692f2087-e91b-4a11-b46f-23f77428e15a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412947766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1
412947766
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3266012549
Short name T546
Test name
Test status
Simulation time 126539147 ps
CPU time 1 seconds
Started Jun 02 12:45:03 PM PDT 24
Finished Jun 02 12:45:05 PM PDT 24
Peak memory 200360 kb
Host smart-97633a61-ce51-4ba6-8947-75a8f6b469f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266012549 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3266012549
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3799448443
Short name T85
Test name
Test status
Simulation time 57580679 ps
CPU time 0.79 seconds
Started Jun 02 12:44:58 PM PDT 24
Finished Jun 02 12:44:59 PM PDT 24
Peak memory 200184 kb
Host smart-5b340df4-c9fd-47b3-bdac-26750ac75b57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799448443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3799448443
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3086275381
Short name T607
Test name
Test status
Simulation time 143578750 ps
CPU time 1.23 seconds
Started Jun 02 12:45:02 PM PDT 24
Finished Jun 02 12:45:04 PM PDT 24
Peak memory 200408 kb
Host smart-ec08f5ce-879a-453e-905a-ca592c6c84c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086275381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3086275381
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.710164542
Short name T559
Test name
Test status
Simulation time 115999105 ps
CPU time 0.98 seconds
Started Jun 02 12:45:07 PM PDT 24
Finished Jun 02 12:45:14 PM PDT 24
Peak memory 200420 kb
Host smart-09a7c9de-435d-4608-aa49-d7b021919eac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710164542 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.710164542
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2191786253
Short name T605
Test name
Test status
Simulation time 65618437 ps
CPU time 0.79 seconds
Started Jun 02 12:45:05 PM PDT 24
Finished Jun 02 12:45:07 PM PDT 24
Peak memory 200248 kb
Host smart-04942413-a8d6-4d26-adae-d312c7c6981a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191786253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2191786253
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.816714567
Short name T562
Test name
Test status
Simulation time 127072674 ps
CPU time 1.34 seconds
Started Jun 02 12:45:18 PM PDT 24
Finished Jun 02 12:45:20 PM PDT 24
Peak memory 200600 kb
Host smart-d13e00db-8d88-4449-963f-47bed1d7b44f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816714567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.816714567
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3963646354
Short name T589
Test name
Test status
Simulation time 144195816 ps
CPU time 2.14 seconds
Started Jun 02 12:45:03 PM PDT 24
Finished Jun 02 12:45:05 PM PDT 24
Peak memory 211896 kb
Host smart-31a80d7c-7a6f-4c63-935d-de5615e13c82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963646354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3963646354
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.105943343
Short name T579
Test name
Test status
Simulation time 419279896 ps
CPU time 1.73 seconds
Started Jun 02 12:45:15 PM PDT 24
Finished Jun 02 12:45:18 PM PDT 24
Peak memory 200592 kb
Host smart-64d963a3-c04f-46d6-9a08-a27381b8e421
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105943343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.105943343
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3396714428
Short name T576
Test name
Test status
Simulation time 110404423 ps
CPU time 0.95 seconds
Started Jun 02 12:45:06 PM PDT 24
Finished Jun 02 12:45:09 PM PDT 24
Peak memory 200424 kb
Host smart-daa21ded-1d2e-41fc-875e-08157157eb28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396714428 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3396714428
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3251671705
Short name T604
Test name
Test status
Simulation time 68699411 ps
CPU time 0.85 seconds
Started Jun 02 12:45:23 PM PDT 24
Finished Jun 02 12:45:24 PM PDT 24
Peak memory 200244 kb
Host smart-89dec834-10fa-4a7f-bc6c-955e728d0724
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251671705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3251671705
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1764511184
Short name T544
Test name
Test status
Simulation time 79829708 ps
CPU time 0.96 seconds
Started Jun 02 12:45:03 PM PDT 24
Finished Jun 02 12:45:05 PM PDT 24
Peak memory 200352 kb
Host smart-de6dfa36-ba22-4b2c-8e27-9004ed9ba721
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764511184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1764511184
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1997717302
Short name T58
Test name
Test status
Simulation time 282741771 ps
CPU time 2.17 seconds
Started Jun 02 12:45:07 PM PDT 24
Finished Jun 02 12:45:11 PM PDT 24
Peak memory 208728 kb
Host smart-ea798f2f-343d-4edc-95bb-a54bb5d0cd80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997717302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1997717302
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1460597171
Short name T108
Test name
Test status
Simulation time 905332966 ps
CPU time 3.64 seconds
Started Jun 02 12:45:09 PM PDT 24
Finished Jun 02 12:45:13 PM PDT 24
Peak memory 200588 kb
Host smart-4c210194-eaeb-48d2-8781-70dc37145737
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460597171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1460597171
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3054371681
Short name T75
Test name
Test status
Simulation time 135860328 ps
CPU time 1.17 seconds
Started Jun 02 12:45:00 PM PDT 24
Finished Jun 02 12:45:03 PM PDT 24
Peak memory 200448 kb
Host smart-57aef723-e5db-496c-a12e-23ef1607ac7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054371681 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3054371681
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1022800237
Short name T609
Test name
Test status
Simulation time 69980698 ps
CPU time 0.83 seconds
Started Jun 02 12:45:11 PM PDT 24
Finished Jun 02 12:45:13 PM PDT 24
Peak memory 200300 kb
Host smart-15c06756-1aa3-47e8-9857-b02eae8589fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022800237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1022800237
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4283124012
Short name T100
Test name
Test status
Simulation time 81650870 ps
CPU time 1.14 seconds
Started Jun 02 12:45:06 PM PDT 24
Finished Jun 02 12:45:13 PM PDT 24
Peak memory 200344 kb
Host smart-7af23712-0fb6-4e19-8454-c64a447fb73d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283124012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.4283124012
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3284355032
Short name T553
Test name
Test status
Simulation time 167526684 ps
CPU time 1.22 seconds
Started Jun 02 12:45:06 PM PDT 24
Finished Jun 02 12:45:09 PM PDT 24
Peak memory 200408 kb
Host smart-20f0e9d0-4115-4450-9243-e7ff2b216233
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284355032 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3284355032
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.4138485028
Short name T586
Test name
Test status
Simulation time 87367048 ps
CPU time 0.88 seconds
Started Jun 02 12:45:04 PM PDT 24
Finished Jun 02 12:45:06 PM PDT 24
Peak memory 200204 kb
Host smart-77f69c00-afef-4a4f-9cc1-f07d59da9034
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138485028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.4138485028
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.184017309
Short name T98
Test name
Test status
Simulation time 248290876 ps
CPU time 1.72 seconds
Started Jun 02 12:45:16 PM PDT 24
Finished Jun 02 12:45:18 PM PDT 24
Peak memory 200540 kb
Host smart-fbb8cf89-349a-4653-bf80-f7c07cd1f6f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184017309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.184017309
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1937835883
Short name T560
Test name
Test status
Simulation time 252912913 ps
CPU time 1.92 seconds
Started Jun 02 12:45:03 PM PDT 24
Finished Jun 02 12:45:05 PM PDT 24
Peak memory 208808 kb
Host smart-9d393504-667a-45c5-9e80-27693a1aa578
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937835883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1937835883
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3750495874
Short name T62
Test name
Test status
Simulation time 487408892 ps
CPU time 1.83 seconds
Started Jun 02 12:45:27 PM PDT 24
Finished Jun 02 12:45:30 PM PDT 24
Peak memory 200548 kb
Host smart-f82baff3-402c-4e12-95b0-e900a45a07c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750495874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3750495874
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.950926510
Short name T591
Test name
Test status
Simulation time 90453898 ps
CPU time 0.89 seconds
Started Jun 02 12:45:04 PM PDT 24
Finished Jun 02 12:45:07 PM PDT 24
Peak memory 200348 kb
Host smart-96f021f5-9a6b-437e-8e0a-840e1fb2690d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950926510 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.950926510
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1679588585
Short name T596
Test name
Test status
Simulation time 57035431 ps
CPU time 0.76 seconds
Started Jun 02 12:45:05 PM PDT 24
Finished Jun 02 12:45:07 PM PDT 24
Peak memory 200260 kb
Host smart-f90876d8-9f46-426d-80d5-65db77becdc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679588585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1679588585
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2453632982
Short name T598
Test name
Test status
Simulation time 215278814 ps
CPU time 1.59 seconds
Started Jun 02 12:45:05 PM PDT 24
Finished Jun 02 12:45:08 PM PDT 24
Peak memory 200492 kb
Host smart-5f0fd750-f3cf-4d30-984c-aea7a323f111
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453632982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2453632982
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1369302420
Short name T601
Test name
Test status
Simulation time 120689018 ps
CPU time 1.68 seconds
Started Jun 02 12:45:00 PM PDT 24
Finished Jun 02 12:45:03 PM PDT 24
Peak memory 208792 kb
Host smart-47ec61df-4a86-4cf0-8b19-694b49cce4b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369302420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1369302420
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.956054579
Short name T616
Test name
Test status
Simulation time 124830642 ps
CPU time 1.06 seconds
Started Jun 02 12:45:12 PM PDT 24
Finished Jun 02 12:45:14 PM PDT 24
Peak memory 200436 kb
Host smart-28d9c09d-bc72-478e-a1f1-56995e4e9184
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956054579 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.956054579
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3101496673
Short name T577
Test name
Test status
Simulation time 69862824 ps
CPU time 0.86 seconds
Started Jun 02 12:45:18 PM PDT 24
Finished Jun 02 12:45:19 PM PDT 24
Peak memory 200292 kb
Host smart-8dd9c588-4ef1-4e8e-ac9a-552b2c91a843
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101496673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3101496673
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2579288998
Short name T602
Test name
Test status
Simulation time 149692033 ps
CPU time 1.16 seconds
Started Jun 02 12:45:13 PM PDT 24
Finished Jun 02 12:45:14 PM PDT 24
Peak memory 200340 kb
Host smart-bba8cb42-5ee0-4eeb-811d-aeb19f2ce24b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579288998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2579288998
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1405591534
Short name T588
Test name
Test status
Simulation time 115651392 ps
CPU time 1.6 seconds
Started Jun 02 12:45:17 PM PDT 24
Finished Jun 02 12:45:19 PM PDT 24
Peak memory 216924 kb
Host smart-0acfd74f-bf79-4326-9413-9918fbec2f17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405591534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1405591534
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.578405287
Short name T109
Test name
Test status
Simulation time 418487348 ps
CPU time 1.94 seconds
Started Jun 02 12:45:04 PM PDT 24
Finished Jun 02 12:45:07 PM PDT 24
Peak memory 200552 kb
Host smart-f8b1e7b6-77da-4eaf-86a4-b140369270a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578405287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err
.578405287
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2785038060
Short name T615
Test name
Test status
Simulation time 197246650 ps
CPU time 1.3 seconds
Started Jun 02 12:45:21 PM PDT 24
Finished Jun 02 12:45:22 PM PDT 24
Peak memory 208632 kb
Host smart-7db4aaf0-6bfb-47ed-b11d-017d197991cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785038060 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2785038060
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.568537952
Short name T550
Test name
Test status
Simulation time 96495139 ps
CPU time 0.85 seconds
Started Jun 02 12:45:27 PM PDT 24
Finished Jun 02 12:45:29 PM PDT 24
Peak memory 200256 kb
Host smart-7a8b7070-acf0-45f3-937c-afd059b942f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568537952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.568537952
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.259265188
Short name T574
Test name
Test status
Simulation time 144111987 ps
CPU time 1.12 seconds
Started Jun 02 12:45:07 PM PDT 24
Finished Jun 02 12:45:10 PM PDT 24
Peak memory 200376 kb
Host smart-703ae07c-19b1-45ef-a36d-ee57ab886447
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259265188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.259265188
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.221186671
Short name T592
Test name
Test status
Simulation time 126781875 ps
CPU time 1.78 seconds
Started Jun 02 12:45:20 PM PDT 24
Finished Jun 02 12:45:22 PM PDT 24
Peak memory 208672 kb
Host smart-a64f041b-84f3-4e2a-9ecb-16a8dd19e897
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221186671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.221186671
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3707387868
Short name T81
Test name
Test status
Simulation time 933293659 ps
CPU time 3.11 seconds
Started Jun 02 12:45:08 PM PDT 24
Finished Jun 02 12:45:12 PM PDT 24
Peak memory 200460 kb
Host smart-979d441b-7448-48c4-b573-fcce598b29c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707387868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3707387868
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1292173390
Short name T567
Test name
Test status
Simulation time 109408378 ps
CPU time 0.94 seconds
Started Jun 02 12:45:13 PM PDT 24
Finished Jun 02 12:45:15 PM PDT 24
Peak memory 200400 kb
Host smart-2083d642-59ea-462e-bac0-cde8b90c3dcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292173390 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.1292173390
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.291403891
Short name T52
Test name
Test status
Simulation time 74579512 ps
CPU time 0.79 seconds
Started Jun 02 12:45:13 PM PDT 24
Finished Jun 02 12:45:14 PM PDT 24
Peak memory 200164 kb
Host smart-8b6e8c46-ba5b-473e-908d-251c23631668
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291403891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.291403891
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.508655891
Short name T561
Test name
Test status
Simulation time 156324823 ps
CPU time 1.15 seconds
Started Jun 02 12:45:21 PM PDT 24
Finished Jun 02 12:45:23 PM PDT 24
Peak memory 200404 kb
Host smart-73ce1d22-117e-4b40-8ff0-bc539aee6ca0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508655891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.508655891
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1448373681
Short name T571
Test name
Test status
Simulation time 293027258 ps
CPU time 2.04 seconds
Started Jun 02 12:45:06 PM PDT 24
Finished Jun 02 12:45:10 PM PDT 24
Peak memory 200520 kb
Host smart-76f69c1b-9c2c-459b-a5c0-4c87edc01886
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448373681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1448373681
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2015383257
Short name T76
Test name
Test status
Simulation time 921001652 ps
CPU time 3.39 seconds
Started Jun 02 12:45:04 PM PDT 24
Finished Jun 02 12:45:08 PM PDT 24
Peak memory 200512 kb
Host smart-05020b78-b501-40c2-ac87-46b2ad11268c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015383257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2015383257
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1260835550
Short name T568
Test name
Test status
Simulation time 197532456 ps
CPU time 1.36 seconds
Started Jun 02 12:45:07 PM PDT 24
Finished Jun 02 12:45:10 PM PDT 24
Peak memory 208632 kb
Host smart-0d0cfb78-aa69-4181-b37e-4e26e929cb5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260835550 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1260835550
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2024503691
Short name T570
Test name
Test status
Simulation time 86071548 ps
CPU time 0.93 seconds
Started Jun 02 12:45:08 PM PDT 24
Finished Jun 02 12:45:10 PM PDT 24
Peak memory 200304 kb
Host smart-ca5f4c79-174d-495b-925b-9d3bda7e7d3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024503691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2024503691
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3879277432
Short name T608
Test name
Test status
Simulation time 247447843 ps
CPU time 1.59 seconds
Started Jun 02 12:45:04 PM PDT 24
Finished Jun 02 12:45:07 PM PDT 24
Peak memory 200192 kb
Host smart-508e8b3a-e5b8-4bd2-8662-ff73ae88c55e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879277432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3879277432
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1830315846
Short name T580
Test name
Test status
Simulation time 261530461 ps
CPU time 1.95 seconds
Started Jun 02 12:45:13 PM PDT 24
Finished Jun 02 12:45:15 PM PDT 24
Peak memory 208788 kb
Host smart-6ffe1ad2-ef6e-46fd-99e2-81b11f779410
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830315846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1830315846
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2707313968
Short name T565
Test name
Test status
Simulation time 782074980 ps
CPU time 3.04 seconds
Started Jun 02 12:45:04 PM PDT 24
Finished Jun 02 12:45:09 PM PDT 24
Peak memory 200624 kb
Host smart-33fa3efa-398b-4707-a6ca-714eb21643d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707313968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2707313968
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1006414390
Short name T612
Test name
Test status
Simulation time 166024255 ps
CPU time 1.6 seconds
Started Jun 02 12:45:23 PM PDT 24
Finished Jun 02 12:45:31 PM PDT 24
Peak memory 208792 kb
Host smart-5f2c1508-2758-4bf6-9044-c537fee39ec9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006414390 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1006414390
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1669333995
Short name T96
Test name
Test status
Simulation time 54949502 ps
CPU time 0.77 seconds
Started Jun 02 12:45:23 PM PDT 24
Finished Jun 02 12:45:24 PM PDT 24
Peak memory 200304 kb
Host smart-35f283b3-d6e0-4c82-a811-69d027afb7e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669333995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1669333995
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2413563896
Short name T558
Test name
Test status
Simulation time 78652893 ps
CPU time 0.91 seconds
Started Jun 02 12:45:05 PM PDT 24
Finished Jun 02 12:45:07 PM PDT 24
Peak memory 200240 kb
Host smart-abe3aa1c-0b8d-4288-b623-eeb7a05d14fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413563896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.2413563896
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.405988394
Short name T74
Test name
Test status
Simulation time 109789100 ps
CPU time 1.55 seconds
Started Jun 02 12:45:04 PM PDT 24
Finished Jun 02 12:45:07 PM PDT 24
Peak memory 210888 kb
Host smart-1cb22acd-9b3b-443e-95eb-f8fde2c831a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405988394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.405988394
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.4009413562
Short name T78
Test name
Test status
Simulation time 779781187 ps
CPU time 2.67 seconds
Started Jun 02 12:45:04 PM PDT 24
Finished Jun 02 12:45:08 PM PDT 24
Peak memory 200460 kb
Host smart-42f26631-8b98-4cdf-a06d-d063f77341e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009413562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.4009413562
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2415399146
Short name T610
Test name
Test status
Simulation time 213529580 ps
CPU time 1.54 seconds
Started Jun 02 12:44:53 PM PDT 24
Finished Jun 02 12:44:55 PM PDT 24
Peak memory 200344 kb
Host smart-a4685ac8-308c-4b20-b180-f6ca924ddf73
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415399146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
415399146
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1273994565
Short name T542
Test name
Test status
Simulation time 275243905 ps
CPU time 3.48 seconds
Started Jun 02 12:44:59 PM PDT 24
Finished Jun 02 12:45:03 PM PDT 24
Peak memory 200388 kb
Host smart-00afb25e-6b9b-4729-b779-3a117a5f4048
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273994565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
273994565
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.11526820
Short name T548
Test name
Test status
Simulation time 127325550 ps
CPU time 0.92 seconds
Started Jun 02 12:44:52 PM PDT 24
Finished Jun 02 12:44:54 PM PDT 24
Peak memory 200264 kb
Host smart-dc753d6f-4f25-4c90-a878-16b7fab023a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11526820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.11526820
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.818927245
Short name T566
Test name
Test status
Simulation time 100523433 ps
CPU time 1.06 seconds
Started Jun 02 12:44:54 PM PDT 24
Finished Jun 02 12:44:56 PM PDT 24
Peak memory 208560 kb
Host smart-a9735b86-43d6-4a04-8874-fb51ea2bf058
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818927245 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.818927245
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3151306014
Short name T555
Test name
Test status
Simulation time 64692868 ps
CPU time 0.74 seconds
Started Jun 02 12:45:05 PM PDT 24
Finished Jun 02 12:45:07 PM PDT 24
Peak memory 200304 kb
Host smart-355b7434-043f-4aa1-96a4-999822b0eea6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151306014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3151306014
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2907849401
Short name T94
Test name
Test status
Simulation time 112864715 ps
CPU time 1.06 seconds
Started Jun 02 12:44:52 PM PDT 24
Finished Jun 02 12:44:53 PM PDT 24
Peak memory 200260 kb
Host smart-5ceac8a7-0ca8-437d-9701-d0770f8b1b62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907849401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2907849401
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3060621976
Short name T77
Test name
Test status
Simulation time 155162525 ps
CPU time 2.3 seconds
Started Jun 02 12:44:54 PM PDT 24
Finished Jun 02 12:44:57 PM PDT 24
Peak memory 211916 kb
Host smart-c0972833-1060-421b-a26d-f834ac44e3e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060621976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3060621976
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1661328495
Short name T103
Test name
Test status
Simulation time 540651824 ps
CPU time 1.99 seconds
Started Jun 02 12:44:51 PM PDT 24
Finished Jun 02 12:44:53 PM PDT 24
Peak memory 200620 kb
Host smart-ee54d307-d028-47d7-8abb-430bc0ea0290
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661328495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1661328495
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.131103108
Short name T597
Test name
Test status
Simulation time 106445575 ps
CPU time 1.39 seconds
Started Jun 02 12:44:54 PM PDT 24
Finished Jun 02 12:44:56 PM PDT 24
Peak memory 200464 kb
Host smart-c3fe3bad-c1d4-4817-bfe0-a7a2c0331753
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131103108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.131103108
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3671998434
Short name T594
Test name
Test status
Simulation time 480160596 ps
CPU time 5.5 seconds
Started Jun 02 12:44:57 PM PDT 24
Finished Jun 02 12:45:03 PM PDT 24
Peak memory 200552 kb
Host smart-9bfd2191-1fd0-429b-8b87-32f703df6fea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671998434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3
671998434
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1976094083
Short name T578
Test name
Test status
Simulation time 117866316 ps
CPU time 0.95 seconds
Started Jun 02 12:44:53 PM PDT 24
Finished Jun 02 12:44:54 PM PDT 24
Peak memory 200240 kb
Host smart-7d50096c-5313-47a3-b462-5f3821e6b59a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976094083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
976094083
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.366267766
Short name T600
Test name
Test status
Simulation time 110606677 ps
CPU time 0.96 seconds
Started Jun 02 12:45:03 PM PDT 24
Finished Jun 02 12:45:05 PM PDT 24
Peak memory 200432 kb
Host smart-ef60a8d1-9154-4ab2-a626-21b89e586ed0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366267766 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.366267766
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.479066731
Short name T617
Test name
Test status
Simulation time 68698129 ps
CPU time 0.78 seconds
Started Jun 02 12:45:00 PM PDT 24
Finished Jun 02 12:45:02 PM PDT 24
Peak memory 200304 kb
Host smart-f58ba659-3931-4366-89cd-f74142703774
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479066731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.479066731
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2833050466
Short name T54
Test name
Test status
Simulation time 106402481 ps
CPU time 1.41 seconds
Started Jun 02 12:44:57 PM PDT 24
Finished Jun 02 12:44:59 PM PDT 24
Peak memory 200576 kb
Host smart-dfd8b9d7-0fc5-44ae-b6fc-5b90d43b0484
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833050466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2833050466
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.971211172
Short name T57
Test name
Test status
Simulation time 91360309 ps
CPU time 1.35 seconds
Started Jun 02 12:44:59 PM PDT 24
Finished Jun 02 12:45:01 PM PDT 24
Peak memory 208704 kb
Host smart-0db6c8d7-d6a5-4de2-8e8b-e9ce7c53d182
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971211172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.971211172
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2067263426
Short name T105
Test name
Test status
Simulation time 469955068 ps
CPU time 1.92 seconds
Started Jun 02 12:45:00 PM PDT 24
Finished Jun 02 12:45:03 PM PDT 24
Peak memory 200564 kb
Host smart-139fdff0-42db-4561-a289-5bd878756ff2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067263426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2067263426
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1258632379
Short name T572
Test name
Test status
Simulation time 406657673 ps
CPU time 2.93 seconds
Started Jun 02 12:45:06 PM PDT 24
Finished Jun 02 12:45:11 PM PDT 24
Peak memory 200488 kb
Host smart-427c95c3-057c-48ef-b4b2-624fdabed372
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258632379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
258632379
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1192418588
Short name T613
Test name
Test status
Simulation time 2292095550 ps
CPU time 10.08 seconds
Started Jun 02 12:44:55 PM PDT 24
Finished Jun 02 12:45:05 PM PDT 24
Peak memory 200572 kb
Host smart-06df1fe5-7d03-4ea9-a03a-a9c9daf16b38
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192418588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
192418588
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2845036982
Short name T541
Test name
Test status
Simulation time 88244566 ps
CPU time 0.82 seconds
Started Jun 02 12:45:01 PM PDT 24
Finished Jun 02 12:45:03 PM PDT 24
Peak memory 200300 kb
Host smart-66faeba6-83be-4d05-844b-7b94e13c1914
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845036982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
845036982
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1384396604
Short name T573
Test name
Test status
Simulation time 95656935 ps
CPU time 0.99 seconds
Started Jun 02 12:44:47 PM PDT 24
Finished Jun 02 12:44:49 PM PDT 24
Peak memory 208544 kb
Host smart-22b83e6d-fc36-4bc9-b547-aea873d36f23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384396604 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1384396604
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.119467667
Short name T582
Test name
Test status
Simulation time 71524799 ps
CPU time 0.82 seconds
Started Jun 02 12:45:04 PM PDT 24
Finished Jun 02 12:45:07 PM PDT 24
Peak memory 199900 kb
Host smart-7a3c84c1-0b45-4fc5-94b1-ba0cbd20eac1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119467667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.119467667
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2937813990
Short name T95
Test name
Test status
Simulation time 209868186 ps
CPU time 1.56 seconds
Started Jun 02 12:45:05 PM PDT 24
Finished Jun 02 12:45:08 PM PDT 24
Peak memory 200556 kb
Host smart-3d456803-4f5d-4279-a841-e08eb8073c01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937813990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.2937813990
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3199361605
Short name T557
Test name
Test status
Simulation time 169612650 ps
CPU time 2.38 seconds
Started Jun 02 12:45:11 PM PDT 24
Finished Jun 02 12:45:13 PM PDT 24
Peak memory 200492 kb
Host smart-7d573c1c-4092-4245-b9c4-16696aecfde9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199361605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3199361605
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3794943347
Short name T585
Test name
Test status
Simulation time 187450429 ps
CPU time 1.26 seconds
Started Jun 02 12:44:59 PM PDT 24
Finished Jun 02 12:45:01 PM PDT 24
Peak memory 200348 kb
Host smart-3b4c2343-4861-4866-931e-52ac5fe88e9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794943347 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3794943347
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3789889269
Short name T603
Test name
Test status
Simulation time 84360410 ps
CPU time 0.89 seconds
Started Jun 02 12:44:58 PM PDT 24
Finished Jun 02 12:44:59 PM PDT 24
Peak memory 200416 kb
Host smart-f784b1ae-d157-4546-828a-f4f2122b4fe9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789889269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3789889269
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1705162678
Short name T606
Test name
Test status
Simulation time 169440842 ps
CPU time 1.24 seconds
Started Jun 02 12:44:53 PM PDT 24
Finished Jun 02 12:44:55 PM PDT 24
Peak memory 200276 kb
Host smart-466540aa-c204-4362-bf7d-b0314b63298f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705162678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1705162678
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3278967785
Short name T73
Test name
Test status
Simulation time 398543032 ps
CPU time 2.86 seconds
Started Jun 02 12:44:53 PM PDT 24
Finished Jun 02 12:44:56 PM PDT 24
Peak memory 208924 kb
Host smart-08b7cfdb-f014-4f0c-b8b6-0c7b10c108ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278967785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3278967785
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.4099826346
Short name T118
Test name
Test status
Simulation time 466289791 ps
CPU time 2.12 seconds
Started Jun 02 12:45:00 PM PDT 24
Finished Jun 02 12:45:03 PM PDT 24
Peak memory 200636 kb
Host smart-afaf3a22-35d1-43db-88e0-6c33e32c2cbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099826346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.4099826346
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2593012701
Short name T545
Test name
Test status
Simulation time 217609631 ps
CPU time 1.35 seconds
Started Jun 02 12:45:03 PM PDT 24
Finished Jun 02 12:45:05 PM PDT 24
Peak memory 208648 kb
Host smart-cfd33b67-98d8-46c0-a8d2-6a2b04982f65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593012701 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2593012701
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.966435412
Short name T593
Test name
Test status
Simulation time 71065244 ps
CPU time 0.84 seconds
Started Jun 02 12:44:59 PM PDT 24
Finished Jun 02 12:45:01 PM PDT 24
Peak memory 200180 kb
Host smart-7e684f75-af64-49b6-91bf-b08e228d0a20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966435412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.966435412
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.15926869
Short name T99
Test name
Test status
Simulation time 120856333 ps
CPU time 1.17 seconds
Started Jun 02 12:44:57 PM PDT 24
Finished Jun 02 12:44:59 PM PDT 24
Peak memory 200312 kb
Host smart-fc6b37ad-09a2-4207-87c3-a03bb442eb36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15926869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_same
_csr_outstanding.15926869
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3948314232
Short name T595
Test name
Test status
Simulation time 275824274 ps
CPU time 2.25 seconds
Started Jun 02 12:45:04 PM PDT 24
Finished Jun 02 12:45:08 PM PDT 24
Peak memory 208704 kb
Host smart-5ed0d53a-cd00-4f3b-a716-28eb42b2ff8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948314232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3948314232
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.167473423
Short name T584
Test name
Test status
Simulation time 483287701 ps
CPU time 1.85 seconds
Started Jun 02 12:44:53 PM PDT 24
Finished Jun 02 12:44:56 PM PDT 24
Peak memory 200608 kb
Host smart-125e73ea-241f-437b-962b-d2e1642ef77c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167473423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
167473423
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1337934176
Short name T611
Test name
Test status
Simulation time 116534049 ps
CPU time 1 seconds
Started Jun 02 12:44:45 PM PDT 24
Finished Jun 02 12:44:47 PM PDT 24
Peak memory 200356 kb
Host smart-8a9e7a1c-620f-4d5b-a917-1ad15291babb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337934176 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1337934176
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3500877810
Short name T543
Test name
Test status
Simulation time 61738231 ps
CPU time 0.78 seconds
Started Jun 02 12:45:05 PM PDT 24
Finished Jun 02 12:45:07 PM PDT 24
Peak memory 200260 kb
Host smart-c2393200-9cb6-4beb-a92c-44345dc34322
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500877810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.3500877810
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.210773357
Short name T569
Test name
Test status
Simulation time 118486099 ps
CPU time 1.03 seconds
Started Jun 02 12:45:06 PM PDT 24
Finished Jun 02 12:45:09 PM PDT 24
Peak memory 200320 kb
Host smart-84960e63-1bef-41d4-b2ed-de658950f6ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210773357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sam
e_csr_outstanding.210773357
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.987800342
Short name T575
Test name
Test status
Simulation time 137608922 ps
CPU time 2.03 seconds
Started Jun 02 12:44:58 PM PDT 24
Finished Jun 02 12:45:01 PM PDT 24
Peak memory 216800 kb
Host smart-69dfb33c-2895-40d1-84e4-1f96b99afa1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987800342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.987800342
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2097841652
Short name T106
Test name
Test status
Simulation time 853123187 ps
CPU time 2.89 seconds
Started Jun 02 12:45:01 PM PDT 24
Finished Jun 02 12:45:05 PM PDT 24
Peak memory 200768 kb
Host smart-12d76e9d-c645-4a45-a584-5acc014b0d5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097841652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.2097841652
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.185016308
Short name T552
Test name
Test status
Simulation time 175488673 ps
CPU time 1.72 seconds
Started Jun 02 12:44:53 PM PDT 24
Finished Jun 02 12:44:55 PM PDT 24
Peak memory 208828 kb
Host smart-f0529ceb-185a-4d6a-a7f9-201e676ec39b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185016308 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.185016308
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2880183169
Short name T599
Test name
Test status
Simulation time 76196866 ps
CPU time 0.89 seconds
Started Jun 02 12:45:00 PM PDT 24
Finished Jun 02 12:45:02 PM PDT 24
Peak memory 200308 kb
Host smart-382883fb-be9d-4132-b02e-c98f4f24f959
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880183169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.2880183169
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.676634850
Short name T556
Test name
Test status
Simulation time 137693143 ps
CPU time 1.08 seconds
Started Jun 02 12:44:51 PM PDT 24
Finished Jun 02 12:44:53 PM PDT 24
Peak memory 200344 kb
Host smart-b64e0761-e019-4ffd-8b90-a00c0ebc0357
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676634850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.676634850
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2028717117
Short name T587
Test name
Test status
Simulation time 129242255 ps
CPU time 1.9 seconds
Started Jun 02 12:45:01 PM PDT 24
Finished Jun 02 12:45:04 PM PDT 24
Peak memory 208668 kb
Host smart-db3c848a-d471-4e88-a173-ee66eb311764
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028717117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2028717117
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1435360408
Short name T80
Test name
Test status
Simulation time 465903742 ps
CPU time 1.85 seconds
Started Jun 02 12:44:58 PM PDT 24
Finished Jun 02 12:45:00 PM PDT 24
Peak memory 200520 kb
Host smart-8ba3d5cd-c67a-45cf-ad32-a72db7237920
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435360408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1435360408
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2829805593
Short name T551
Test name
Test status
Simulation time 195910352 ps
CPU time 2.13 seconds
Started Jun 02 12:45:17 PM PDT 24
Finished Jun 02 12:45:20 PM PDT 24
Peak memory 208860 kb
Host smart-41fe0223-43c2-4f92-9940-93bfd7d02b1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829805593 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2829805593
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.246149670
Short name T620
Test name
Test status
Simulation time 79996458 ps
CPU time 0.93 seconds
Started Jun 02 12:45:15 PM PDT 24
Finished Jun 02 12:45:16 PM PDT 24
Peak memory 200232 kb
Host smart-f3bd14ae-c0c3-434e-b835-a8fba7077af9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246149670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.246149670
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.440216091
Short name T583
Test name
Test status
Simulation time 92871969 ps
CPU time 1.21 seconds
Started Jun 02 12:45:03 PM PDT 24
Finished Jun 02 12:45:06 PM PDT 24
Peak memory 200516 kb
Host smart-4a213f20-77ff-4100-90a0-1a35fd61c0c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440216091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.440216091
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.269495295
Short name T563
Test name
Test status
Simulation time 196413149 ps
CPU time 2.76 seconds
Started Jun 02 12:44:51 PM PDT 24
Finished Jun 02 12:44:54 PM PDT 24
Peak memory 208672 kb
Host smart-488f80f6-a37d-4017-b477-87dcc23da296
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269495295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.269495295
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1147209550
Short name T581
Test name
Test status
Simulation time 785169476 ps
CPU time 3.21 seconds
Started Jun 02 12:44:56 PM PDT 24
Finished Jun 02 12:45:00 PM PDT 24
Peak memory 200624 kb
Host smart-d6f87636-a2b3-4d51-98a3-6b5e62b8bbb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147209550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1147209550
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.1487977122
Short name T202
Test name
Test status
Simulation time 71898839 ps
CPU time 0.75 seconds
Started Jun 02 12:43:37 PM PDT 24
Finished Jun 02 12:43:38 PM PDT 24
Peak memory 200556 kb
Host smart-d9276e43-149f-4801-9ac1-fa4f203ec337
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487977122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1487977122
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1815489793
Short name T197
Test name
Test status
Simulation time 1215631507 ps
CPU time 5.68 seconds
Started Jun 02 12:43:35 PM PDT 24
Finished Jun 02 12:43:41 PM PDT 24
Peak memory 218296 kb
Host smart-104f349f-9f76-4b32-9edf-d767f6b36bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815489793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1815489793
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.4147529327
Short name T471
Test name
Test status
Simulation time 244246170 ps
CPU time 1.12 seconds
Started Jun 02 12:43:33 PM PDT 24
Finished Jun 02 12:43:35 PM PDT 24
Peak memory 217852 kb
Host smart-ddea32db-6f02-44f1-9055-8393c537dde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147529327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.4147529327
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.40511546
Short name T456
Test name
Test status
Simulation time 181039688 ps
CPU time 0.86 seconds
Started Jun 02 12:43:38 PM PDT 24
Finished Jun 02 12:43:40 PM PDT 24
Peak memory 200496 kb
Host smart-dbef3db1-7286-4372-b72c-1ef1490875bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40511546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.40511546
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1546360288
Short name T13
Test name
Test status
Simulation time 1921134174 ps
CPU time 6.51 seconds
Started Jun 02 12:43:38 PM PDT 24
Finished Jun 02 12:43:45 PM PDT 24
Peak memory 200872 kb
Host smart-5f6d876e-ff73-4d5a-9591-f45be41372fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546360288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1546360288
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3974755199
Short name T379
Test name
Test status
Simulation time 94646733 ps
CPU time 0.93 seconds
Started Jun 02 12:43:39 PM PDT 24
Finished Jun 02 12:43:41 PM PDT 24
Peak memory 200700 kb
Host smart-bfeeea7e-4510-47e2-b53c-406f9454d834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974755199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3974755199
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1279177177
Short name T436
Test name
Test status
Simulation time 121941790 ps
CPU time 1.18 seconds
Started Jun 02 12:43:30 PM PDT 24
Finished Jun 02 12:43:32 PM PDT 24
Peak memory 201132 kb
Host smart-96242e55-d0a5-46ff-85bb-e120c459a4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279177177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1279177177
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1404187898
Short name T66
Test name
Test status
Simulation time 1153874280 ps
CPU time 4.52 seconds
Started Jun 02 12:43:32 PM PDT 24
Finished Jun 02 12:43:37 PM PDT 24
Peak memory 200940 kb
Host smart-4f598eaf-2083-4192-be36-e70700673b27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404187898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1404187898
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.45271010
Short name T377
Test name
Test status
Simulation time 525236913 ps
CPU time 2.82 seconds
Started Jun 02 12:43:36 PM PDT 24
Finished Jun 02 12:43:39 PM PDT 24
Peak memory 200800 kb
Host smart-97bc7df0-c3cb-4d69-b131-fd898c7c8afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45271010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.45271010
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3982956937
Short name T11
Test name
Test status
Simulation time 107189789 ps
CPU time 0.92 seconds
Started Jun 02 12:43:33 PM PDT 24
Finished Jun 02 12:43:34 PM PDT 24
Peak memory 200808 kb
Host smart-7e520e39-61de-423b-a451-f3732c3a0cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982956937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3982956937
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3654683807
Short name T132
Test name
Test status
Simulation time 83830608 ps
CPU time 0.82 seconds
Started Jun 02 12:43:47 PM PDT 24
Finished Jun 02 12:43:49 PM PDT 24
Peak memory 199960 kb
Host smart-a4bf0ef8-fb6a-4abd-9b84-42000b2b6691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654683807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3654683807
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1409547394
Short name T329
Test name
Test status
Simulation time 2161930090 ps
CPU time 8.56 seconds
Started Jun 02 12:43:34 PM PDT 24
Finished Jun 02 12:43:44 PM PDT 24
Peak memory 218432 kb
Host smart-b31107ea-2a82-4f6e-8e90-cdf5701e2505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409547394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1409547394
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3052246031
Short name T325
Test name
Test status
Simulation time 246320654 ps
CPU time 1.07 seconds
Started Jun 02 12:43:37 PM PDT 24
Finished Jun 02 12:43:39 PM PDT 24
Peak memory 217868 kb
Host smart-677e0713-cb67-48c0-926f-e4c76bbae61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052246031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3052246031
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3103091972
Short name T169
Test name
Test status
Simulation time 101940376 ps
CPU time 0.76 seconds
Started Jun 02 12:43:40 PM PDT 24
Finished Jun 02 12:43:42 PM PDT 24
Peak memory 200520 kb
Host smart-79605c0d-fe75-445d-8288-221f62728330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103091972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3103091972
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.4002565583
Short name T438
Test name
Test status
Simulation time 1705085579 ps
CPU time 6.72 seconds
Started Jun 02 12:43:36 PM PDT 24
Finished Jun 02 12:43:44 PM PDT 24
Peak memory 200984 kb
Host smart-2bd4af65-f88e-4557-be52-de786a53851c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002565583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.4002565583
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2738071663
Short name T64
Test name
Test status
Simulation time 8818802467 ps
CPU time 13.97 seconds
Started Jun 02 12:43:37 PM PDT 24
Finished Jun 02 12:43:52 PM PDT 24
Peak memory 217588 kb
Host smart-54309544-9d09-4af0-9b89-a65a0cdcdc96
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738071663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2738071663
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1205142854
Short name T199
Test name
Test status
Simulation time 154617309 ps
CPU time 1.24 seconds
Started Jun 02 12:43:39 PM PDT 24
Finished Jun 02 12:43:41 PM PDT 24
Peak memory 201084 kb
Host smart-161ec0a7-3141-4738-8f27-f9ed9eeb0b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205142854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1205142854
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.14341782
Short name T403
Test name
Test status
Simulation time 116025292 ps
CPU time 1.14 seconds
Started Jun 02 12:43:37 PM PDT 24
Finished Jun 02 12:43:39 PM PDT 24
Peak memory 200936 kb
Host smart-b04c6a8e-f05b-483e-a20a-b9dfe9add3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14341782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.14341782
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.922321899
Short name T26
Test name
Test status
Simulation time 1003244677 ps
CPU time 4.84 seconds
Started Jun 02 12:43:37 PM PDT 24
Finished Jun 02 12:43:43 PM PDT 24
Peak memory 209148 kb
Host smart-bf81383a-ad8e-4444-8b96-1e950d35cd39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922321899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.922321899
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2567312511
Short name T488
Test name
Test status
Simulation time 144651072 ps
CPU time 1.87 seconds
Started Jun 02 12:43:38 PM PDT 24
Finished Jun 02 12:43:41 PM PDT 24
Peak memory 200780 kb
Host smart-3640c744-9ba7-4c0b-81de-dfdbdf4eceab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567312511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2567312511
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3050467331
Short name T425
Test name
Test status
Simulation time 104698848 ps
CPU time 0.9 seconds
Started Jun 02 12:43:38 PM PDT 24
Finished Jun 02 12:43:39 PM PDT 24
Peak memory 200828 kb
Host smart-c37320b3-0df0-486c-a347-6676f1d29a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050467331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3050467331
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.2982132961
Short name T387
Test name
Test status
Simulation time 66831156 ps
CPU time 0.8 seconds
Started Jun 02 12:43:56 PM PDT 24
Finished Jun 02 12:43:58 PM PDT 24
Peak memory 200900 kb
Host smart-1115cdfa-6314-40b8-b6b3-629821a93e1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982132961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2982132961
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3299351668
Short name T269
Test name
Test status
Simulation time 1230257210 ps
CPU time 5.75 seconds
Started Jun 02 12:43:57 PM PDT 24
Finished Jun 02 12:44:04 PM PDT 24
Peak memory 217264 kb
Host smart-33978994-cab9-4be7-ab25-eebc794d182e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299351668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3299351668
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2104181966
Short name T291
Test name
Test status
Simulation time 245275644 ps
CPU time 1.12 seconds
Started Jun 02 12:43:57 PM PDT 24
Finished Jun 02 12:43:59 PM PDT 24
Peak memory 217972 kb
Host smart-825062ce-6d83-4c20-a9c3-fb99c6c1fd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104181966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2104181966
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_reset.4161876721
Short name T478
Test name
Test status
Simulation time 874164063 ps
CPU time 4.35 seconds
Started Jun 02 12:43:56 PM PDT 24
Finished Jun 02 12:44:02 PM PDT 24
Peak memory 200988 kb
Host smart-f54d69ef-5d7f-45d3-be24-2d30084a95d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161876721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.4161876721
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1889779125
Short name T361
Test name
Test status
Simulation time 161736965 ps
CPU time 1.17 seconds
Started Jun 02 12:43:51 PM PDT 24
Finished Jun 02 12:43:52 PM PDT 24
Peak memory 200832 kb
Host smart-afed7e8b-f8ee-4570-a51d-bd1b8cb30c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889779125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1889779125
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2377304285
Short name T148
Test name
Test status
Simulation time 187612948 ps
CPU time 1.59 seconds
Started Jun 02 12:43:58 PM PDT 24
Finished Jun 02 12:44:01 PM PDT 24
Peak memory 201012 kb
Host smart-b3a9634e-7b8a-4419-8ed4-d4afdeb65af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377304285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2377304285
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3706562295
Short name T228
Test name
Test status
Simulation time 421442752 ps
CPU time 2.3 seconds
Started Jun 02 12:43:51 PM PDT 24
Finished Jun 02 12:43:54 PM PDT 24
Peak memory 200756 kb
Host smart-5be8e792-b714-44c1-869d-abcc838e8a7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706562295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3706562295
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1238944533
Short name T192
Test name
Test status
Simulation time 268491290 ps
CPU time 1.9 seconds
Started Jun 02 12:43:54 PM PDT 24
Finished Jun 02 12:43:56 PM PDT 24
Peak memory 200772 kb
Host smart-e12958ae-b49a-4c60-a1bf-990d8c8de4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238944533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1238944533
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.116879115
Short name T528
Test name
Test status
Simulation time 229315864 ps
CPU time 1.47 seconds
Started Jun 02 12:44:01 PM PDT 24
Finished Jun 02 12:44:04 PM PDT 24
Peak memory 200768 kb
Host smart-ff48e215-c91c-499c-b801-fb50f13eae0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116879115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.116879115
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.878058719
Short name T129
Test name
Test status
Simulation time 64872695 ps
CPU time 0.71 seconds
Started Jun 02 12:43:54 PM PDT 24
Finished Jun 02 12:43:55 PM PDT 24
Peak memory 200588 kb
Host smart-9b8e7889-1ee4-4007-9663-27fa476027c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878058719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.878058719
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.640499100
Short name T42
Test name
Test status
Simulation time 1895011549 ps
CPU time 7.85 seconds
Started Jun 02 12:43:51 PM PDT 24
Finished Jun 02 12:44:00 PM PDT 24
Peak memory 218392 kb
Host smart-d1b4807c-43ee-4c0f-be97-fd3daf1c476d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640499100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.640499100
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2824100696
Short name T185
Test name
Test status
Simulation time 244865577 ps
CPU time 1.05 seconds
Started Jun 02 12:43:52 PM PDT 24
Finished Jun 02 12:43:53 PM PDT 24
Peak memory 217952 kb
Host smart-5327bc7f-e772-473d-a495-052351948f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824100696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.2824100696
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.132707639
Short name T497
Test name
Test status
Simulation time 92315191 ps
CPU time 0.79 seconds
Started Jun 02 12:43:57 PM PDT 24
Finished Jun 02 12:43:58 PM PDT 24
Peak memory 200584 kb
Host smart-4c1a158c-eb6b-48be-96ac-a217836fe36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132707639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.132707639
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1701476139
Short name T120
Test name
Test status
Simulation time 1053448634 ps
CPU time 4.69 seconds
Started Jun 02 12:43:58 PM PDT 24
Finished Jun 02 12:44:03 PM PDT 24
Peak memory 201008 kb
Host smart-f2ee6271-be02-4cbf-ae5a-f57d4695819c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701476139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1701476139
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.16624023
Short name T462
Test name
Test status
Simulation time 141903916 ps
CPU time 1.14 seconds
Started Jun 02 12:43:52 PM PDT 24
Finished Jun 02 12:43:54 PM PDT 24
Peak memory 200724 kb
Host smart-1cfb526a-e455-4eff-9baf-f8911a2035bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16624023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.16624023
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1454980573
Short name T149
Test name
Test status
Simulation time 117857130 ps
CPU time 1.16 seconds
Started Jun 02 12:44:01 PM PDT 24
Finished Jun 02 12:44:03 PM PDT 24
Peak memory 200912 kb
Host smart-c5fa3378-30c7-4547-8b77-b8c5ee27b34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454980573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1454980573
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3409719841
Short name T196
Test name
Test status
Simulation time 15427823899 ps
CPU time 53.82 seconds
Started Jun 02 12:43:58 PM PDT 24
Finished Jun 02 12:44:53 PM PDT 24
Peak memory 201140 kb
Host smart-2328923a-f0b7-4400-b283-f7ad5f657514
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409719841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3409719841
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.249985908
Short name T432
Test name
Test status
Simulation time 335538486 ps
CPU time 2.28 seconds
Started Jun 02 12:43:53 PM PDT 24
Finished Jun 02 12:43:56 PM PDT 24
Peak memory 209000 kb
Host smart-3371ea38-e051-4835-aae3-779a1c178f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249985908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.249985908
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2716331191
Short name T435
Test name
Test status
Simulation time 215163717 ps
CPU time 1.28 seconds
Started Jun 02 12:43:52 PM PDT 24
Finished Jun 02 12:43:54 PM PDT 24
Peak memory 200752 kb
Host smart-20f8b5e5-8425-45d4-9523-682c2bf90893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716331191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2716331191
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3501655677
Short name T354
Test name
Test status
Simulation time 97165289 ps
CPU time 0.84 seconds
Started Jun 02 12:43:55 PM PDT 24
Finished Jun 02 12:43:56 PM PDT 24
Peak memory 200588 kb
Host smart-25f683b1-fcb8-48b1-b5ca-03302566be0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501655677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3501655677
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2075155477
Short name T498
Test name
Test status
Simulation time 1216324964 ps
CPU time 5.45 seconds
Started Jun 02 12:44:00 PM PDT 24
Finished Jun 02 12:44:06 PM PDT 24
Peak memory 222356 kb
Host smart-f00beda3-d9d7-4889-9b0d-3608ea5c6b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075155477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2075155477
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.66152723
Short name T317
Test name
Test status
Simulation time 244365911 ps
CPU time 1.19 seconds
Started Jun 02 12:43:54 PM PDT 24
Finished Jun 02 12:43:56 PM PDT 24
Peak memory 217868 kb
Host smart-9acf9152-c140-4a63-bee3-22d90a00684e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66152723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.66152723
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.1311645717
Short name T367
Test name
Test status
Simulation time 79454664 ps
CPU time 0.78 seconds
Started Jun 02 12:43:58 PM PDT 24
Finished Jun 02 12:44:00 PM PDT 24
Peak memory 200640 kb
Host smart-dd94e0ea-4c1a-4a3d-acf5-773b6f1bb991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311645717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1311645717
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2845525984
Short name T273
Test name
Test status
Simulation time 1135586976 ps
CPU time 4.79 seconds
Started Jun 02 12:43:56 PM PDT 24
Finished Jun 02 12:44:02 PM PDT 24
Peak memory 200972 kb
Host smart-6fa7e500-70af-4e45-aa3c-168dad6b56e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845525984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2845525984
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.4236870249
Short name T220
Test name
Test status
Simulation time 145523551 ps
CPU time 1.11 seconds
Started Jun 02 12:43:54 PM PDT 24
Finished Jun 02 12:43:55 PM PDT 24
Peak memory 200792 kb
Host smart-f092a4cb-393b-45a9-806a-3a089178acce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236870249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.4236870249
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3425601587
Short name T524
Test name
Test status
Simulation time 206156930 ps
CPU time 1.33 seconds
Started Jun 02 12:43:54 PM PDT 24
Finished Jun 02 12:43:56 PM PDT 24
Peak memory 200968 kb
Host smart-4bbfa031-4d02-46bf-bf33-3bc7d69769f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425601587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3425601587
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.1143189032
Short name T89
Test name
Test status
Simulation time 6247964365 ps
CPU time 21.91 seconds
Started Jun 02 12:44:00 PM PDT 24
Finished Jun 02 12:44:23 PM PDT 24
Peak memory 209272 kb
Host smart-014a3675-cde6-4d30-9034-de068c3585a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143189032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1143189032
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3546144446
Short name T250
Test name
Test status
Simulation time 146524567 ps
CPU time 1.25 seconds
Started Jun 02 12:43:54 PM PDT 24
Finished Jun 02 12:43:56 PM PDT 24
Peak memory 200752 kb
Host smart-3349cf70-ab10-4cef-b06d-378dd670be85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546144446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3546144446
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3508685908
Short name T115
Test name
Test status
Simulation time 1899830196 ps
CPU time 7.04 seconds
Started Jun 02 12:43:54 PM PDT 24
Finished Jun 02 12:44:01 PM PDT 24
Peak memory 217544 kb
Host smart-7856edf4-b410-48fe-a8a0-381d39deaaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508685908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3508685908
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1201997719
Short name T29
Test name
Test status
Simulation time 244124101 ps
CPU time 1.07 seconds
Started Jun 02 12:43:56 PM PDT 24
Finished Jun 02 12:43:57 PM PDT 24
Peak memory 218088 kb
Host smart-8dbb6df2-6edb-452d-aa35-8512132edcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201997719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1201997719
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.642474972
Short name T160
Test name
Test status
Simulation time 112660565 ps
CPU time 0.79 seconds
Started Jun 02 12:43:53 PM PDT 24
Finished Jun 02 12:43:55 PM PDT 24
Peak memory 200600 kb
Host smart-baf21c83-1238-42ae-931b-20f324020dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642474972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.642474972
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3276759090
Short name T307
Test name
Test status
Simulation time 778160639 ps
CPU time 3.68 seconds
Started Jun 02 12:43:56 PM PDT 24
Finished Jun 02 12:44:01 PM PDT 24
Peak memory 200936 kb
Host smart-d0f4a04a-1d9c-4b08-a34f-20aac714a4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276759090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3276759090
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1953868563
Short name T469
Test name
Test status
Simulation time 145249602 ps
CPU time 1.08 seconds
Started Jun 02 12:43:57 PM PDT 24
Finished Jun 02 12:43:59 PM PDT 24
Peak memory 200736 kb
Host smart-ac8ab5c0-e44c-4a14-b0d9-c86ea066800a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953868563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1953868563
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3164403521
Short name T529
Test name
Test status
Simulation time 106249940 ps
CPU time 1.15 seconds
Started Jun 02 12:43:55 PM PDT 24
Finished Jun 02 12:43:57 PM PDT 24
Peak memory 200984 kb
Host smart-bcf522f9-e64b-436c-a955-1cac27c6e6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164403521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3164403521
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3644703533
Short name T222
Test name
Test status
Simulation time 324487415 ps
CPU time 2.18 seconds
Started Jun 02 12:44:05 PM PDT 24
Finished Jun 02 12:44:07 PM PDT 24
Peak memory 200760 kb
Host smart-77b28a71-c194-4cb9-b0fd-7c3861b5122c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644703533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3644703533
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.4219288700
Short name T413
Test name
Test status
Simulation time 59243864 ps
CPU time 0.76 seconds
Started Jun 02 12:43:55 PM PDT 24
Finished Jun 02 12:43:56 PM PDT 24
Peak memory 200808 kb
Host smart-646c5ebf-79ee-4d83-918d-b145a9c04629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219288700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.4219288700
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.333344436
Short name T484
Test name
Test status
Simulation time 75998791 ps
CPU time 0.8 seconds
Started Jun 02 12:43:57 PM PDT 24
Finished Jun 02 12:43:59 PM PDT 24
Peak memory 200608 kb
Host smart-06d4de2a-04c7-4af9-b1f2-f60169389599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333344436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.333344436
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1581838535
Short name T445
Test name
Test status
Simulation time 1221660581 ps
CPU time 5.89 seconds
Started Jun 02 12:43:59 PM PDT 24
Finished Jun 02 12:44:06 PM PDT 24
Peak memory 217900 kb
Host smart-2d852865-6a76-433a-a041-9fffef654405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581838535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1581838535
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.897156424
Short name T136
Test name
Test status
Simulation time 244248634 ps
CPU time 1.07 seconds
Started Jun 02 12:43:54 PM PDT 24
Finished Jun 02 12:43:56 PM PDT 24
Peak memory 217948 kb
Host smart-85665097-b7c9-4f7f-a299-a183eaacc9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897156424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.897156424
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2803652632
Short name T538
Test name
Test status
Simulation time 173785583 ps
CPU time 0.9 seconds
Started Jun 02 12:43:57 PM PDT 24
Finished Jun 02 12:43:58 PM PDT 24
Peak memory 200532 kb
Host smart-51717d84-6b1e-4103-95d6-345fa05d4efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803652632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2803652632
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2395957599
Short name T492
Test name
Test status
Simulation time 1906837169 ps
CPU time 6.64 seconds
Started Jun 02 12:43:57 PM PDT 24
Finished Jun 02 12:44:05 PM PDT 24
Peak memory 200948 kb
Host smart-55647515-1cc8-4a04-8b50-bd20d355db55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395957599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2395957599
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.285260738
Short name T264
Test name
Test status
Simulation time 143784343 ps
CPU time 1.16 seconds
Started Jun 02 12:43:57 PM PDT 24
Finished Jun 02 12:43:59 PM PDT 24
Peak memory 200796 kb
Host smart-9cffddf6-9ccf-4a95-b9c3-d78cd36f1e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285260738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.285260738
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.4244020295
Short name T292
Test name
Test status
Simulation time 256700990 ps
CPU time 1.45 seconds
Started Jun 02 12:43:55 PM PDT 24
Finished Jun 02 12:43:57 PM PDT 24
Peak memory 201016 kb
Host smart-0022c90f-8b50-4193-a2b6-0806fb08df3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244020295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.4244020295
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2587368831
Short name T323
Test name
Test status
Simulation time 1829792995 ps
CPU time 7.93 seconds
Started Jun 02 12:43:57 PM PDT 24
Finished Jun 02 12:44:06 PM PDT 24
Peak memory 200940 kb
Host smart-d2a8ae0c-7dc4-4844-aa06-ad83416e6322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587368831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2587368831
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.807668457
Short name T337
Test name
Test status
Simulation time 141789855 ps
CPU time 1.06 seconds
Started Jun 02 12:43:52 PM PDT 24
Finished Jun 02 12:43:54 PM PDT 24
Peak memory 200800 kb
Host smart-f2b052c1-f76f-4eea-b89e-89342bc691e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807668457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.807668457
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.157442629
Short name T265
Test name
Test status
Simulation time 74564151 ps
CPU time 0.86 seconds
Started Jun 02 12:44:01 PM PDT 24
Finished Jun 02 12:44:04 PM PDT 24
Peak memory 200268 kb
Host smart-e6228d33-7fcf-4778-b83a-a4a5309bc7e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157442629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.157442629
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.589127271
Short name T406
Test name
Test status
Simulation time 1230541560 ps
CPU time 5.69 seconds
Started Jun 02 12:43:58 PM PDT 24
Finished Jun 02 12:44:04 PM PDT 24
Peak memory 218692 kb
Host smart-c9bb9af2-328c-4f12-8621-cde4b58bebdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589127271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.589127271
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1285116588
Short name T172
Test name
Test status
Simulation time 243915874 ps
CPU time 1.07 seconds
Started Jun 02 12:43:57 PM PDT 24
Finished Jun 02 12:43:59 PM PDT 24
Peak memory 217936 kb
Host smart-79248c65-4a1e-4684-b251-0ca8d30fbddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285116588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1285116588
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3832862365
Short name T417
Test name
Test status
Simulation time 112825529 ps
CPU time 0.82 seconds
Started Jun 02 12:43:54 PM PDT 24
Finished Jun 02 12:43:56 PM PDT 24
Peak memory 200560 kb
Host smart-985f188b-9497-4f7b-839b-0574777aff7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832862365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3832862365
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2957600473
Short name T428
Test name
Test status
Simulation time 1168113666 ps
CPU time 5.33 seconds
Started Jun 02 12:43:58 PM PDT 24
Finished Jun 02 12:44:04 PM PDT 24
Peak memory 201012 kb
Host smart-025d8a16-bb36-418a-a014-fdee28cf7ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957600473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2957600473
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2254671900
Short name T384
Test name
Test status
Simulation time 163741684 ps
CPU time 1.13 seconds
Started Jun 02 12:43:53 PM PDT 24
Finished Jun 02 12:43:55 PM PDT 24
Peak memory 200848 kb
Host smart-3a679fb7-61d8-4dbe-b0d2-414471f53c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254671900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2254671900
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.2255506026
Short name T407
Test name
Test status
Simulation time 121064569 ps
CPU time 1.21 seconds
Started Jun 02 12:43:53 PM PDT 24
Finished Jun 02 12:43:54 PM PDT 24
Peak memory 200968 kb
Host smart-a6efc492-1263-4c7d-a435-ff07d598ca09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255506026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.2255506026
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.1647311919
Short name T237
Test name
Test status
Simulation time 1314170956 ps
CPU time 6.22 seconds
Started Jun 02 12:44:12 PM PDT 24
Finished Jun 02 12:44:19 PM PDT 24
Peak memory 201012 kb
Host smart-df0a81ba-1871-47f3-a43c-e2d9800423de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647311919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1647311919
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.657813247
Short name T114
Test name
Test status
Simulation time 518581664 ps
CPU time 2.77 seconds
Started Jun 02 12:43:55 PM PDT 24
Finished Jun 02 12:43:58 PM PDT 24
Peak memory 200804 kb
Host smart-387a5814-6363-4a91-8683-c24e08a06083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657813247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.657813247
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2554296428
Short name T23
Test name
Test status
Simulation time 142124374 ps
CPU time 1.1 seconds
Started Jun 02 12:43:58 PM PDT 24
Finished Jun 02 12:44:00 PM PDT 24
Peak memory 200836 kb
Host smart-90b26bf3-8876-4019-997e-f6aa9c19c682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554296428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2554296428
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.3541775422
Short name T318
Test name
Test status
Simulation time 89666504 ps
CPU time 0.84 seconds
Started Jun 02 12:44:01 PM PDT 24
Finished Jun 02 12:44:03 PM PDT 24
Peak memory 200628 kb
Host smart-e42fd922-1dac-4b9a-8c63-0b8fa75d5bd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541775422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3541775422
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.3654221126
Short name T242
Test name
Test status
Simulation time 2374386126 ps
CPU time 8.38 seconds
Started Jun 02 12:44:06 PM PDT 24
Finished Jun 02 12:44:15 PM PDT 24
Peak memory 217812 kb
Host smart-43046e3f-4fa6-4ccb-a016-c68888342ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654221126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.3654221126
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3749126937
Short name T319
Test name
Test status
Simulation time 243984281 ps
CPU time 1.06 seconds
Started Jun 02 12:44:01 PM PDT 24
Finished Jun 02 12:44:03 PM PDT 24
Peak memory 217896 kb
Host smart-4d731d7d-b986-4846-8cf7-47519eb0cea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749126937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3749126937
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1784418855
Short name T253
Test name
Test status
Simulation time 179737930 ps
CPU time 0.98 seconds
Started Jun 02 12:44:02 PM PDT 24
Finished Jun 02 12:44:04 PM PDT 24
Peak memory 200640 kb
Host smart-c85d766f-c643-41d7-b9f8-42dcba3f7af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784418855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1784418855
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.1448817719
Short name T525
Test name
Test status
Simulation time 877123987 ps
CPU time 4.62 seconds
Started Jun 02 12:43:59 PM PDT 24
Finished Jun 02 12:44:05 PM PDT 24
Peak memory 200988 kb
Host smart-820d293b-9f12-478c-9db3-312beefdea7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448817719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1448817719
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.813649574
Short name T232
Test name
Test status
Simulation time 198027678 ps
CPU time 1.38 seconds
Started Jun 02 12:43:56 PM PDT 24
Finished Jun 02 12:43:59 PM PDT 24
Peak memory 200972 kb
Host smart-3bc785bc-9448-4e9f-aedf-97b41e19b116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813649574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.813649574
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.3274843052
Short name T443
Test name
Test status
Simulation time 6469494527 ps
CPU time 23.59 seconds
Started Jun 02 12:44:04 PM PDT 24
Finished Jun 02 12:44:28 PM PDT 24
Peak memory 209336 kb
Host smart-d849d38a-c24a-4d3e-8a8b-27121567728e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274843052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3274843052
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.40242876
Short name T494
Test name
Test status
Simulation time 416369850 ps
CPU time 2.46 seconds
Started Jun 02 12:43:57 PM PDT 24
Finished Jun 02 12:44:00 PM PDT 24
Peak memory 200816 kb
Host smart-fe42d93b-4180-489d-87d3-d8b9f02c028f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40242876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.40242876
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2462485256
Short name T437
Test name
Test status
Simulation time 191991109 ps
CPU time 1.31 seconds
Started Jun 02 12:44:04 PM PDT 24
Finished Jun 02 12:44:06 PM PDT 24
Peak memory 200788 kb
Host smart-c3aaa23d-b99f-46a4-82e0-f4ef685e77cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462485256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2462485256
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.306409439
Short name T280
Test name
Test status
Simulation time 78617619 ps
CPU time 0.79 seconds
Started Jun 02 12:44:09 PM PDT 24
Finished Jun 02 12:44:11 PM PDT 24
Peak memory 200652 kb
Host smart-6c87b33d-966c-484c-b303-2725ae30a3c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306409439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.306409439
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1062106111
Short name T229
Test name
Test status
Simulation time 1902328222 ps
CPU time 6.81 seconds
Started Jun 02 12:44:00 PM PDT 24
Finished Jun 02 12:44:08 PM PDT 24
Peak memory 218736 kb
Host smart-ac735cb0-c034-443d-8f2f-1d695f9f3f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062106111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1062106111
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.4257383555
Short name T127
Test name
Test status
Simulation time 243484576 ps
CPU time 1.09 seconds
Started Jun 02 12:44:11 PM PDT 24
Finished Jun 02 12:44:12 PM PDT 24
Peak memory 217876 kb
Host smart-aeda6a45-ab2e-48fe-b9e5-49e3d75e2f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257383555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.4257383555
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3665042218
Short name T305
Test name
Test status
Simulation time 110286063 ps
CPU time 0.79 seconds
Started Jun 02 12:44:02 PM PDT 24
Finished Jun 02 12:44:04 PM PDT 24
Peak memory 200628 kb
Host smart-84080379-919e-4244-826a-1f8c43fb2a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665042218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3665042218
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.977729728
Short name T517
Test name
Test status
Simulation time 2015554027 ps
CPU time 8.08 seconds
Started Jun 02 12:44:01 PM PDT 24
Finished Jun 02 12:44:10 PM PDT 24
Peak memory 200920 kb
Host smart-2af36135-97ee-4629-95fa-5aea3880664e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977729728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.977729728
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.34454756
Short name T313
Test name
Test status
Simulation time 146373332 ps
CPU time 1.14 seconds
Started Jun 02 12:44:10 PM PDT 24
Finished Jun 02 12:44:11 PM PDT 24
Peak memory 200772 kb
Host smart-9ff0577f-cfab-47f9-883a-05fa784277a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34454756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.34454756
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1958470621
Short name T134
Test name
Test status
Simulation time 116829283 ps
CPU time 1.2 seconds
Started Jun 02 12:44:09 PM PDT 24
Finished Jun 02 12:44:11 PM PDT 24
Peak memory 200924 kb
Host smart-cb2afc41-b1dd-418b-8d4b-a8ab1052e06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958470621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1958470621
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3251091870
Short name T339
Test name
Test status
Simulation time 1112207579 ps
CPU time 5.25 seconds
Started Jun 02 12:43:59 PM PDT 24
Finished Jun 02 12:44:06 PM PDT 24
Peak memory 209188 kb
Host smart-e31cb4ae-1ab6-4c93-a1bd-1bc4e9652599
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251091870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3251091870
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.3613536630
Short name T533
Test name
Test status
Simulation time 259951841 ps
CPU time 1.88 seconds
Started Jun 02 12:44:01 PM PDT 24
Finished Jun 02 12:44:04 PM PDT 24
Peak memory 200716 kb
Host smart-c11df458-1384-4025-bf20-5845378b8ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613536630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3613536630
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3229933319
Short name T171
Test name
Test status
Simulation time 223161183 ps
CPU time 1.38 seconds
Started Jun 02 12:44:01 PM PDT 24
Finished Jun 02 12:44:04 PM PDT 24
Peak memory 200412 kb
Host smart-fe83d2ab-9cdc-4740-b374-726b769c052b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229933319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3229933319
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3076577982
Short name T180
Test name
Test status
Simulation time 108647991 ps
CPU time 0.88 seconds
Started Jun 02 12:44:01 PM PDT 24
Finished Jun 02 12:44:03 PM PDT 24
Peak memory 200644 kb
Host smart-9ca0406b-927e-47fa-8fd0-8681dc1514cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076577982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3076577982
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2027697431
Short name T36
Test name
Test status
Simulation time 1218167264 ps
CPU time 6.03 seconds
Started Jun 02 12:44:05 PM PDT 24
Finished Jun 02 12:44:12 PM PDT 24
Peak memory 218400 kb
Host smart-2f4c631f-7c01-4663-ad04-017cb54c5800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027697431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2027697431
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.4155096317
Short name T347
Test name
Test status
Simulation time 244443258 ps
CPU time 1.1 seconds
Started Jun 02 12:44:00 PM PDT 24
Finished Jun 02 12:44:02 PM PDT 24
Peak memory 217840 kb
Host smart-8be5737e-7905-4681-a006-d70421ea4d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155096317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.4155096317
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1961116240
Short name T20
Test name
Test status
Simulation time 175704393 ps
CPU time 0.88 seconds
Started Jun 02 12:44:07 PM PDT 24
Finished Jun 02 12:44:08 PM PDT 24
Peak memory 200636 kb
Host smart-fd249215-1345-4862-9210-9d21e00e5c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961116240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1961116240
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1163666665
Short name T281
Test name
Test status
Simulation time 1647588341 ps
CPU time 6.17 seconds
Started Jun 02 12:44:00 PM PDT 24
Finished Jun 02 12:44:07 PM PDT 24
Peak memory 200892 kb
Host smart-c8fb8286-be64-4449-ab0e-3ab7d3e5d3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163666665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1163666665
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.4165696406
Short name T474
Test name
Test status
Simulation time 147496133 ps
CPU time 1.12 seconds
Started Jun 02 12:44:08 PM PDT 24
Finished Jun 02 12:44:10 PM PDT 24
Peak memory 200760 kb
Host smart-8c755a34-cf52-4df0-b5eb-2afc2ebfb491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165696406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.4165696406
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.2362300906
Short name T402
Test name
Test status
Simulation time 125367220 ps
CPU time 1.27 seconds
Started Jun 02 12:43:58 PM PDT 24
Finished Jun 02 12:44:01 PM PDT 24
Peak memory 200952 kb
Host smart-b8a36972-aaae-45e7-9aea-61738bb64f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362300906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2362300906
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3073857299
Short name T297
Test name
Test status
Simulation time 3938057071 ps
CPU time 17.36 seconds
Started Jun 02 12:44:12 PM PDT 24
Finished Jun 02 12:44:30 PM PDT 24
Peak memory 201108 kb
Host smart-b5d90ceb-33f7-4cb5-8fef-dd4b9361806a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073857299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3073857299
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1302745678
Short name T128
Test name
Test status
Simulation time 271278426 ps
CPU time 1.95 seconds
Started Jun 02 12:44:09 PM PDT 24
Finished Jun 02 12:44:12 PM PDT 24
Peak memory 200740 kb
Host smart-b4534388-9d22-4a4b-bb4d-f1aff6c47774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302745678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1302745678
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2880317467
Short name T486
Test name
Test status
Simulation time 136898571 ps
CPU time 1.01 seconds
Started Jun 02 12:44:07 PM PDT 24
Finished Jun 02 12:44:09 PM PDT 24
Peak memory 200724 kb
Host smart-61602984-e9a2-4e47-85c3-39709a68f4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880317467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2880317467
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2183504713
Short name T514
Test name
Test status
Simulation time 62367329 ps
CPU time 0.73 seconds
Started Jun 02 12:44:02 PM PDT 24
Finished Jun 02 12:44:03 PM PDT 24
Peak memory 200572 kb
Host smart-30b16174-39ae-49cb-bb43-b8146ea28676
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183504713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2183504713
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.680322440
Short name T31
Test name
Test status
Simulation time 1886461406 ps
CPU time 6.89 seconds
Started Jun 02 12:44:12 PM PDT 24
Finished Jun 02 12:44:20 PM PDT 24
Peak memory 217312 kb
Host smart-e5ec800d-b2cd-40e0-905d-07debea76ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680322440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.680322440
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.825308227
Short name T276
Test name
Test status
Simulation time 243584104 ps
CPU time 1.07 seconds
Started Jun 02 12:44:03 PM PDT 24
Finished Jun 02 12:44:05 PM PDT 24
Peak memory 217948 kb
Host smart-b032ee3b-0909-4db8-952f-2816448c7c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825308227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.825308227
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1028207470
Short name T12
Test name
Test status
Simulation time 231280707 ps
CPU time 0.96 seconds
Started Jun 02 12:43:59 PM PDT 24
Finished Jun 02 12:44:01 PM PDT 24
Peak memory 200584 kb
Host smart-01a850f5-cf73-4ff1-944a-bf57996d7dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028207470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1028207470
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.239944891
Short name T331
Test name
Test status
Simulation time 816701218 ps
CPU time 4.17 seconds
Started Jun 02 12:44:01 PM PDT 24
Finished Jun 02 12:44:07 PM PDT 24
Peak memory 200988 kb
Host smart-7bea6869-0771-47b0-9b20-6e4175d2ae2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239944891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.239944891
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3493546816
Short name T30
Test name
Test status
Simulation time 185533171 ps
CPU time 1.17 seconds
Started Jun 02 12:44:00 PM PDT 24
Finished Jun 02 12:44:03 PM PDT 24
Peak memory 201068 kb
Host smart-72c19e55-c8ac-4b58-b8ec-0756f98ad636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493546816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3493546816
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3881979186
Short name T214
Test name
Test status
Simulation time 117158250 ps
CPU time 1.18 seconds
Started Jun 02 12:44:01 PM PDT 24
Finished Jun 02 12:44:04 PM PDT 24
Peak memory 200908 kb
Host smart-e6342e76-20dc-42f9-b855-1935fffdd081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881979186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3881979186
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.4165877864
Short name T87
Test name
Test status
Simulation time 18015183109 ps
CPU time 57.99 seconds
Started Jun 02 12:44:01 PM PDT 24
Finished Jun 02 12:45:01 PM PDT 24
Peak memory 201132 kb
Host smart-c1b6fb3f-9f48-4bd9-a882-3dc9db23fc29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165877864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.4165877864
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.4267308010
Short name T296
Test name
Test status
Simulation time 557613939 ps
CPU time 2.69 seconds
Started Jun 02 12:43:57 PM PDT 24
Finished Jun 02 12:44:01 PM PDT 24
Peak memory 200748 kb
Host smart-2df1debd-df93-428f-8710-1856df886591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267308010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.4267308010
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.336613956
Short name T215
Test name
Test status
Simulation time 58443407 ps
CPU time 0.77 seconds
Started Jun 02 12:43:36 PM PDT 24
Finished Jun 02 12:43:37 PM PDT 24
Peak memory 200636 kb
Host smart-35ac5a03-6398-42b0-86b2-d50de603f6d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336613956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.336613956
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3198783627
Short name T441
Test name
Test status
Simulation time 1223202394 ps
CPU time 5.65 seconds
Started Jun 02 12:43:39 PM PDT 24
Finished Jun 02 12:43:45 PM PDT 24
Peak memory 217860 kb
Host smart-738a3f83-acfe-404e-b4d5-f140861031b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198783627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3198783627
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2762384475
Short name T526
Test name
Test status
Simulation time 244697892 ps
CPU time 1.09 seconds
Started Jun 02 12:43:35 PM PDT 24
Finished Jun 02 12:43:37 PM PDT 24
Peak memory 217820 kb
Host smart-6949df56-289f-4e3b-8800-314c3ab71353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762384475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2762384475
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.916569423
Short name T395
Test name
Test status
Simulation time 171119423 ps
CPU time 0.87 seconds
Started Jun 02 12:43:37 PM PDT 24
Finished Jun 02 12:43:38 PM PDT 24
Peak memory 200476 kb
Host smart-3338e7cb-fc1e-464c-94a4-aa2db9b62682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916569423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.916569423
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.927445949
Short name T358
Test name
Test status
Simulation time 935588755 ps
CPU time 4.81 seconds
Started Jun 02 12:43:39 PM PDT 24
Finished Jun 02 12:43:44 PM PDT 24
Peak memory 201040 kb
Host smart-096cc04b-bb26-46a6-9e32-cee4b620724e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927445949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.927445949
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2784321118
Short name T6
Test name
Test status
Simulation time 16932132497 ps
CPU time 25.46 seconds
Started Jun 02 12:43:38 PM PDT 24
Finished Jun 02 12:44:05 PM PDT 24
Peak memory 218684 kb
Host smart-e088db1e-0a0e-4884-b6d3-91f516cfe715
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784321118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2784321118
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3417432037
Short name T431
Test name
Test status
Simulation time 173289288 ps
CPU time 1.14 seconds
Started Jun 02 12:43:38 PM PDT 24
Finished Jun 02 12:43:40 PM PDT 24
Peak memory 200820 kb
Host smart-6884fbb1-5435-42a1-ad67-4a15e2f7196d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417432037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3417432037
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3216321468
Short name T374
Test name
Test status
Simulation time 247482059 ps
CPU time 1.56 seconds
Started Jun 02 12:43:36 PM PDT 24
Finished Jun 02 12:43:38 PM PDT 24
Peak memory 200928 kb
Host smart-add57cea-cac1-4224-a87d-c3d390e01a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216321468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3216321468
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1971371580
Short name T458
Test name
Test status
Simulation time 8439464702 ps
CPU time 29.5 seconds
Started Jun 02 12:43:38 PM PDT 24
Finished Jun 02 12:44:08 PM PDT 24
Peak memory 201088 kb
Host smart-2d5477ac-4aa2-4b1e-a77b-396618e2e10f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971371580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1971371580
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2662611623
Short name T177
Test name
Test status
Simulation time 149773451 ps
CPU time 1.81 seconds
Started Jun 02 12:43:38 PM PDT 24
Finished Jun 02 12:43:41 PM PDT 24
Peak memory 200836 kb
Host smart-ad28cafe-e914-47b2-84c4-feeb41de186a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662611623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2662611623
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1106763205
Short name T338
Test name
Test status
Simulation time 111068170 ps
CPU time 0.98 seconds
Started Jun 02 12:43:37 PM PDT 24
Finished Jun 02 12:43:39 PM PDT 24
Peak memory 200776 kb
Host smart-893d836b-2924-4085-9e0c-748b6067518d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106763205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1106763205
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1216913886
Short name T282
Test name
Test status
Simulation time 73860273 ps
CPU time 0.79 seconds
Started Jun 02 12:44:05 PM PDT 24
Finished Jun 02 12:44:07 PM PDT 24
Peak memory 200628 kb
Host smart-266c9022-b813-4672-b730-9f2b3b7bf994
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216913886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1216913886
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2590452436
Short name T140
Test name
Test status
Simulation time 243748875 ps
CPU time 1.1 seconds
Started Jun 02 12:44:01 PM PDT 24
Finished Jun 02 12:44:04 PM PDT 24
Peak memory 218012 kb
Host smart-409e4a70-d271-4583-9f2b-9aa00088100c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590452436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2590452436
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1589997116
Short name T266
Test name
Test status
Simulation time 92323531 ps
CPU time 0.77 seconds
Started Jun 02 12:44:11 PM PDT 24
Finished Jun 02 12:44:12 PM PDT 24
Peak memory 200612 kb
Host smart-c5af9a09-6fd9-40ea-9a06-64a6f22e69af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589997116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1589997116
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.1211360671
Short name T206
Test name
Test status
Simulation time 1027286814 ps
CPU time 5.42 seconds
Started Jun 02 12:44:04 PM PDT 24
Finished Jun 02 12:44:10 PM PDT 24
Peak memory 200944 kb
Host smart-bc30c278-9a87-4201-9602-455c54c66905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211360671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1211360671
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2928652723
Short name T187
Test name
Test status
Simulation time 183243470 ps
CPU time 1.13 seconds
Started Jun 02 12:44:05 PM PDT 24
Finished Jun 02 12:44:07 PM PDT 24
Peak memory 200792 kb
Host smart-871eb334-611b-442d-906d-1527e5a36d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928652723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2928652723
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1270041459
Short name T410
Test name
Test status
Simulation time 254331941 ps
CPU time 1.53 seconds
Started Jun 02 12:43:59 PM PDT 24
Finished Jun 02 12:44:01 PM PDT 24
Peak memory 200936 kb
Host smart-0990ac85-dfb0-4768-8424-1fcf90ed1241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270041459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1270041459
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3744365110
Short name T91
Test name
Test status
Simulation time 3083101792 ps
CPU time 13.24 seconds
Started Jun 02 12:44:07 PM PDT 24
Finished Jun 02 12:44:21 PM PDT 24
Peak memory 209280 kb
Host smart-75cecfab-b69b-4148-ad25-e00bb9069f22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744365110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3744365110
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2135755402
Short name T463
Test name
Test status
Simulation time 339791732 ps
CPU time 2.29 seconds
Started Jun 02 12:44:10 PM PDT 24
Finished Jun 02 12:44:12 PM PDT 24
Peak memory 200732 kb
Host smart-d12b69bb-8329-48a0-b246-ae0d1b411107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135755402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2135755402
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1016780137
Short name T164
Test name
Test status
Simulation time 62569664 ps
CPU time 0.78 seconds
Started Jun 02 12:44:08 PM PDT 24
Finished Jun 02 12:44:10 PM PDT 24
Peak memory 200812 kb
Host smart-cf644b38-20e0-4eee-9dfd-cbe478cc4eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016780137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1016780137
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3721290320
Short name T495
Test name
Test status
Simulation time 63905683 ps
CPU time 0.78 seconds
Started Jun 02 12:44:10 PM PDT 24
Finished Jun 02 12:44:11 PM PDT 24
Peak memory 200584 kb
Host smart-1d6434b0-c071-4672-a063-25548b4dfb28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721290320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3721290320
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3960519053
Short name T44
Test name
Test status
Simulation time 2188914297 ps
CPU time 8.4 seconds
Started Jun 02 12:44:02 PM PDT 24
Finished Jun 02 12:44:11 PM PDT 24
Peak memory 218528 kb
Host smart-9621c52d-1ab7-4e63-b971-6a56bc7b064a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960519053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3960519053
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1567551308
Short name T213
Test name
Test status
Simulation time 247376013 ps
CPU time 1.05 seconds
Started Jun 02 12:44:05 PM PDT 24
Finished Jun 02 12:44:07 PM PDT 24
Peak memory 218016 kb
Host smart-03027021-ba37-4c79-bfb6-242e70f615b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567551308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1567551308
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2251649797
Short name T341
Test name
Test status
Simulation time 165857524 ps
CPU time 0.85 seconds
Started Jun 02 12:44:09 PM PDT 24
Finished Jun 02 12:44:10 PM PDT 24
Peak memory 200568 kb
Host smart-733f3e60-878f-4434-afd9-3578ff0f0a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251649797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2251649797
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.739188250
Short name T389
Test name
Test status
Simulation time 941998345 ps
CPU time 5.1 seconds
Started Jun 02 12:44:03 PM PDT 24
Finished Jun 02 12:44:09 PM PDT 24
Peak memory 200912 kb
Host smart-de1fd0a3-7550-499f-a813-eec378ea8f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739188250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.739188250
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2383140999
Short name T444
Test name
Test status
Simulation time 107912803 ps
CPU time 0.99 seconds
Started Jun 02 12:44:01 PM PDT 24
Finished Jun 02 12:44:04 PM PDT 24
Peak memory 200812 kb
Host smart-63b15fad-a4e2-4671-9066-f263c68189cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383140999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2383140999
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.594400376
Short name T223
Test name
Test status
Simulation time 119746035 ps
CPU time 1.31 seconds
Started Jun 02 12:44:00 PM PDT 24
Finished Jun 02 12:44:02 PM PDT 24
Peak memory 200988 kb
Host smart-839db57b-d9f0-4d8e-a88b-fc45d5503d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594400376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.594400376
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1830104982
Short name T181
Test name
Test status
Simulation time 7164007152 ps
CPU time 33.27 seconds
Started Jun 02 12:44:00 PM PDT 24
Finished Jun 02 12:44:35 PM PDT 24
Peak memory 209352 kb
Host smart-34c9f108-5147-4b10-af5c-d0c23611c7b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830104982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1830104982
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3511523356
Short name T247
Test name
Test status
Simulation time 425700644 ps
CPU time 2.35 seconds
Started Jun 02 12:44:01 PM PDT 24
Finished Jun 02 12:44:05 PM PDT 24
Peak memory 208916 kb
Host smart-eaa82eb5-5194-4d1c-9b57-1f94e978f7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511523356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3511523356
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3590448114
Short name T531
Test name
Test status
Simulation time 128029287 ps
CPU time 1.07 seconds
Started Jun 02 12:44:02 PM PDT 24
Finished Jun 02 12:44:04 PM PDT 24
Peak memory 200820 kb
Host smart-fbe38d5f-d7d0-407a-85eb-e686a8e4f7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590448114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3590448114
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.406109735
Short name T141
Test name
Test status
Simulation time 65147657 ps
CPU time 0.74 seconds
Started Jun 02 12:44:07 PM PDT 24
Finished Jun 02 12:44:09 PM PDT 24
Peak memory 200660 kb
Host smart-c64997bc-8d2d-4cdf-82b4-5c72554487a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406109735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.406109735
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.958294124
Short name T439
Test name
Test status
Simulation time 1221338199 ps
CPU time 5.31 seconds
Started Jun 02 12:44:07 PM PDT 24
Finished Jun 02 12:44:13 PM PDT 24
Peak memory 218388 kb
Host smart-4763ecfc-9396-458b-a7b1-dc36912904a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958294124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.958294124
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3766356351
Short name T152
Test name
Test status
Simulation time 243486268 ps
CPU time 1.1 seconds
Started Jun 02 12:44:09 PM PDT 24
Finished Jun 02 12:44:11 PM PDT 24
Peak memory 218100 kb
Host smart-27083561-1afb-4a6a-9343-7a3270161283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766356351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3766356351
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.1806110437
Short name T194
Test name
Test status
Simulation time 188458850 ps
CPU time 0.84 seconds
Started Jun 02 12:44:06 PM PDT 24
Finished Jun 02 12:44:08 PM PDT 24
Peak memory 200628 kb
Host smart-60eb15f8-c84c-41be-80ee-418a78de211a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806110437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1806110437
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3443592684
Short name T376
Test name
Test status
Simulation time 1189582177 ps
CPU time 5.71 seconds
Started Jun 02 12:44:07 PM PDT 24
Finished Jun 02 12:44:14 PM PDT 24
Peak memory 200996 kb
Host smart-19d4ca11-2c50-43a4-9021-01d9ac22b77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443592684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3443592684
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3831062678
Short name T218
Test name
Test status
Simulation time 183030171 ps
CPU time 1.28 seconds
Started Jun 02 12:44:06 PM PDT 24
Finished Jun 02 12:44:08 PM PDT 24
Peak memory 200816 kb
Host smart-d71e488e-62a5-4a08-b7ca-a770e70b9e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831062678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3831062678
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1714520457
Short name T429
Test name
Test status
Simulation time 258532046 ps
CPU time 1.48 seconds
Started Jun 02 12:44:07 PM PDT 24
Finished Jun 02 12:44:09 PM PDT 24
Peak memory 200992 kb
Host smart-4dd38228-af61-4f7a-9c61-9c3ad78377bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714520457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1714520457
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.3581673658
Short name T485
Test name
Test status
Simulation time 8667923490 ps
CPU time 31.49 seconds
Started Jun 02 12:44:14 PM PDT 24
Finished Jun 02 12:44:46 PM PDT 24
Peak memory 209332 kb
Host smart-4910947a-4687-4e2e-86f4-811cc80c4c67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581673658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3581673658
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2179993913
Short name T394
Test name
Test status
Simulation time 254621870 ps
CPU time 1.74 seconds
Started Jun 02 12:44:12 PM PDT 24
Finished Jun 02 12:44:15 PM PDT 24
Peak memory 200772 kb
Host smart-e2d056bb-4b37-4a22-86bb-578789dc5997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179993913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2179993913
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2826653488
Short name T506
Test name
Test status
Simulation time 98249876 ps
CPU time 0.93 seconds
Started Jun 02 12:44:08 PM PDT 24
Finished Jun 02 12:44:10 PM PDT 24
Peak memory 200808 kb
Host smart-648b4b8b-2dbd-4521-ab5d-1946423ce53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826653488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2826653488
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3141736896
Short name T333
Test name
Test status
Simulation time 75873766 ps
CPU time 0.77 seconds
Started Jun 02 12:44:14 PM PDT 24
Finished Jun 02 12:44:16 PM PDT 24
Peak memory 200520 kb
Host smart-0cbe90fa-b1db-4a21-b067-fb8debebf251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141736896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3141736896
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.984958315
Short name T47
Test name
Test status
Simulation time 1227917320 ps
CPU time 5.61 seconds
Started Jun 02 12:44:09 PM PDT 24
Finished Jun 02 12:44:16 PM PDT 24
Peak memory 221880 kb
Host smart-5b2d354b-20db-427c-b803-74837858294c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984958315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.984958315
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.2027683809
Short name T422
Test name
Test status
Simulation time 243535426 ps
CPU time 1.31 seconds
Started Jun 02 12:44:14 PM PDT 24
Finished Jun 02 12:44:16 PM PDT 24
Peak memory 217972 kb
Host smart-da82ff94-b242-4134-9bce-0918b298c921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027683809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.2027683809
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2647593726
Short name T205
Test name
Test status
Simulation time 98705530 ps
CPU time 0.76 seconds
Started Jun 02 12:44:05 PM PDT 24
Finished Jun 02 12:44:06 PM PDT 24
Peak memory 200588 kb
Host smart-3c520a25-f3e1-4c4b-8e4c-8519e7c4712b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647593726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2647593726
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.3602266646
Short name T472
Test name
Test status
Simulation time 861286293 ps
CPU time 4.47 seconds
Started Jun 02 12:44:11 PM PDT 24
Finished Jun 02 12:44:17 PM PDT 24
Peak memory 200964 kb
Host smart-5a091295-ef9f-4b0b-b86b-b90615c60303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602266646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3602266646
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3279701368
Short name T139
Test name
Test status
Simulation time 177231354 ps
CPU time 1.17 seconds
Started Jun 02 12:44:06 PM PDT 24
Finished Jun 02 12:44:08 PM PDT 24
Peak memory 200756 kb
Host smart-991fe83c-49f7-4a5a-9a66-1f672b50542b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279701368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3279701368
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.3792371486
Short name T182
Test name
Test status
Simulation time 252077486 ps
CPU time 1.44 seconds
Started Jun 02 12:44:06 PM PDT 24
Finished Jun 02 12:44:09 PM PDT 24
Peak memory 200932 kb
Host smart-0cd83ec1-ff19-492d-a73f-f8fbcaef0b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792371486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3792371486
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2709476947
Short name T476
Test name
Test status
Simulation time 4328647808 ps
CPU time 20.78 seconds
Started Jun 02 12:44:09 PM PDT 24
Finished Jun 02 12:44:31 PM PDT 24
Peak memory 209308 kb
Host smart-cd84eae9-ed39-4a14-90e3-38e5ed1d66e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709476947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2709476947
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.423403961
Short name T286
Test name
Test status
Simulation time 132730722 ps
CPU time 1.71 seconds
Started Jun 02 12:44:14 PM PDT 24
Finished Jun 02 12:44:17 PM PDT 24
Peak memory 200724 kb
Host smart-6a356780-80f8-4bc4-b6a1-c703fd9c4a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423403961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.423403961
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.4055994112
Short name T365
Test name
Test status
Simulation time 104869358 ps
CPU time 0.96 seconds
Started Jun 02 12:44:15 PM PDT 24
Finished Jun 02 12:44:17 PM PDT 24
Peak memory 200752 kb
Host smart-29815a76-6c7c-43dd-a388-009f1255255b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055994112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.4055994112
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.301840071
Short name T405
Test name
Test status
Simulation time 69203919 ps
CPU time 0.75 seconds
Started Jun 02 12:44:04 PM PDT 24
Finished Jun 02 12:44:06 PM PDT 24
Peak memory 200660 kb
Host smart-25d13973-e7ee-4da0-ba56-b2793d16df00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301840071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.301840071
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.4263056013
Short name T122
Test name
Test status
Simulation time 244667332 ps
CPU time 1.06 seconds
Started Jun 02 12:44:11 PM PDT 24
Finished Jun 02 12:44:13 PM PDT 24
Peak memory 217948 kb
Host smart-86ad7755-d42e-4deb-a0e4-42a9eaa2d6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263056013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.4263056013
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.200074626
Short name T454
Test name
Test status
Simulation time 113860633 ps
CPU time 0.78 seconds
Started Jun 02 12:44:08 PM PDT 24
Finished Jun 02 12:44:09 PM PDT 24
Peak memory 200616 kb
Host smart-a6cfae4d-7018-445f-8c8c-30de14e4f120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200074626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.200074626
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.519966883
Short name T238
Test name
Test status
Simulation time 1385453679 ps
CPU time 5.33 seconds
Started Jun 02 12:44:12 PM PDT 24
Finished Jun 02 12:44:18 PM PDT 24
Peak memory 200964 kb
Host smart-8a0c4124-f03c-4321-afda-9baa5bc7620c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519966883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.519966883
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.2160486513
Short name T421
Test name
Test status
Simulation time 154320633 ps
CPU time 1.18 seconds
Started Jun 02 12:44:06 PM PDT 24
Finished Jun 02 12:44:08 PM PDT 24
Peak memory 200804 kb
Host smart-e4daf27f-2d0e-4caf-a32e-d650459afc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160486513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.2160486513
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.3254948086
Short name T217
Test name
Test status
Simulation time 113657388 ps
CPU time 1.23 seconds
Started Jun 02 12:44:14 PM PDT 24
Finished Jun 02 12:44:16 PM PDT 24
Peak memory 200988 kb
Host smart-9ef9e1d0-a98f-4a4a-8cf1-0fd7c25f89a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254948086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.3254948086
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3379586554
Short name T28
Test name
Test status
Simulation time 7922340351 ps
CPU time 30.58 seconds
Started Jun 02 12:44:19 PM PDT 24
Finished Jun 02 12:44:50 PM PDT 24
Peak memory 217488 kb
Host smart-b7eaa2d9-a675-42d8-bb77-b9e518281841
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379586554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3379586554
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.3698814717
Short name T522
Test name
Test status
Simulation time 383956580 ps
CPU time 2.4 seconds
Started Jun 02 12:44:06 PM PDT 24
Finished Jun 02 12:44:09 PM PDT 24
Peak memory 200796 kb
Host smart-47122f56-007a-4cff-9c6f-a67cebd5183f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698814717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.3698814717
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.988362271
Short name T518
Test name
Test status
Simulation time 96899396 ps
CPU time 0.87 seconds
Started Jun 02 12:44:07 PM PDT 24
Finished Jun 02 12:44:09 PM PDT 24
Peak memory 200724 kb
Host smart-e8e9e53d-ed8d-4a2e-9190-817a451e0149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988362271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.988362271
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3046473751
Short name T311
Test name
Test status
Simulation time 77245054 ps
CPU time 0.79 seconds
Started Jun 02 12:44:17 PM PDT 24
Finished Jun 02 12:44:19 PM PDT 24
Peak memory 200644 kb
Host smart-0027cfb3-1a93-4d53-b8dc-1e53d4d82ceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046473751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3046473751
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1154140830
Short name T523
Test name
Test status
Simulation time 2347635106 ps
CPU time 7.95 seconds
Started Jun 02 12:44:13 PM PDT 24
Finished Jun 02 12:44:22 PM PDT 24
Peak memory 218140 kb
Host smart-fba495ac-57f6-493b-a9ae-9085f09dc649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154140830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1154140830
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.4275823308
Short name T135
Test name
Test status
Simulation time 247496225 ps
CPU time 1.02 seconds
Started Jun 02 12:44:12 PM PDT 24
Finished Jun 02 12:44:14 PM PDT 24
Peak memory 217876 kb
Host smart-79b2aab2-58c7-427a-91ea-4486f94e9109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275823308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.4275823308
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.575115447
Short name T345
Test name
Test status
Simulation time 132122441 ps
CPU time 0.79 seconds
Started Jun 02 12:44:14 PM PDT 24
Finished Jun 02 12:44:16 PM PDT 24
Peak memory 200556 kb
Host smart-73fbc950-8a87-4c0b-b119-f4c3248b4ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575115447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.575115447
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2795739730
Short name T195
Test name
Test status
Simulation time 1169071906 ps
CPU time 4.63 seconds
Started Jun 02 12:44:13 PM PDT 24
Finished Jun 02 12:44:19 PM PDT 24
Peak memory 200932 kb
Host smart-629c9dcb-64d5-4d5b-b30e-aaf0f1ccb68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795739730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2795739730
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.4283240850
Short name T161
Test name
Test status
Simulation time 142189505 ps
CPU time 1.06 seconds
Started Jun 02 12:44:11 PM PDT 24
Finished Jun 02 12:44:13 PM PDT 24
Peak memory 200836 kb
Host smart-ba7f1abf-26d1-46bb-b930-7be41b82102c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283240850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.4283240850
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.4077576074
Short name T512
Test name
Test status
Simulation time 113957747 ps
CPU time 1.28 seconds
Started Jun 02 12:44:09 PM PDT 24
Finished Jun 02 12:44:11 PM PDT 24
Peak memory 201016 kb
Host smart-510022c9-9fe9-4a9e-99cf-e02222cf8981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077576074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.4077576074
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.320007559
Short name T245
Test name
Test status
Simulation time 6788158592 ps
CPU time 29.97 seconds
Started Jun 02 12:44:24 PM PDT 24
Finished Jun 02 12:44:55 PM PDT 24
Peak memory 201124 kb
Host smart-18088253-e118-4d61-96f1-a271543efa9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320007559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.320007559
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1507904733
Short name T170
Test name
Test status
Simulation time 327733181 ps
CPU time 2.06 seconds
Started Jun 02 12:44:12 PM PDT 24
Finished Jun 02 12:44:15 PM PDT 24
Peak memory 200744 kb
Host smart-07af7012-529b-45df-a257-612b1ef747fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507904733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1507904733
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2667789553
Short name T496
Test name
Test status
Simulation time 181700738 ps
CPU time 1.32 seconds
Started Jun 02 12:44:16 PM PDT 24
Finished Jun 02 12:44:18 PM PDT 24
Peak memory 200888 kb
Host smart-767ba917-8f86-472d-8b70-a01aadf6728c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667789553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2667789553
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.405731324
Short name T254
Test name
Test status
Simulation time 60361048 ps
CPU time 0.73 seconds
Started Jun 02 12:44:15 PM PDT 24
Finished Jun 02 12:44:16 PM PDT 24
Peak memory 200600 kb
Host smart-77660cd5-c8e0-410f-9fda-c8b92aa21aa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405731324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.405731324
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1810762224
Short name T391
Test name
Test status
Simulation time 1228034790 ps
CPU time 5.77 seconds
Started Jun 02 12:44:10 PM PDT 24
Finished Jun 02 12:44:17 PM PDT 24
Peak memory 217836 kb
Host smart-a6853e43-fe29-4d40-b010-03d065bbd303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810762224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1810762224
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2682732913
Short name T440
Test name
Test status
Simulation time 244658044 ps
CPU time 1.12 seconds
Started Jun 02 12:44:13 PM PDT 24
Finished Jun 02 12:44:15 PM PDT 24
Peak memory 217936 kb
Host smart-58614998-14e1-4025-8ece-5a813fc43c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682732913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2682732913
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1006830209
Short name T336
Test name
Test status
Simulation time 166991284 ps
CPU time 0.89 seconds
Started Jun 02 12:44:13 PM PDT 24
Finished Jun 02 12:44:15 PM PDT 24
Peak memory 200640 kb
Host smart-e90496e8-83f9-4b96-b4c1-1fca9b27bbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006830209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1006830209
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1907891101
Short name T457
Test name
Test status
Simulation time 694877431 ps
CPU time 3.98 seconds
Started Jun 02 12:44:16 PM PDT 24
Finished Jun 02 12:44:21 PM PDT 24
Peak memory 200980 kb
Host smart-bb0dd407-815a-4fae-af95-450b6825e18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907891101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1907891101
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.486322031
Short name T360
Test name
Test status
Simulation time 144951326 ps
CPU time 1.2 seconds
Started Jun 02 12:44:14 PM PDT 24
Finished Jun 02 12:44:16 PM PDT 24
Peak memory 200840 kb
Host smart-bfd8a16b-8188-4c78-ad59-d33c1c6eaec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486322031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.486322031
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3720423873
Short name T475
Test name
Test status
Simulation time 249690708 ps
CPU time 1.54 seconds
Started Jun 02 12:44:12 PM PDT 24
Finished Jun 02 12:44:15 PM PDT 24
Peak memory 200984 kb
Host smart-67691004-d27a-4238-be80-edc7405c001f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720423873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3720423873
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.4124267864
Short name T71
Test name
Test status
Simulation time 3119547283 ps
CPU time 15.17 seconds
Started Jun 02 12:44:17 PM PDT 24
Finished Jun 02 12:44:33 PM PDT 24
Peak memory 201048 kb
Host smart-f89ca05d-8f65-4194-8b43-8c00034684df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124267864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.4124267864
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.4008442746
Short name T390
Test name
Test status
Simulation time 307984481 ps
CPU time 2.09 seconds
Started Jun 02 12:44:16 PM PDT 24
Finished Jun 02 12:44:19 PM PDT 24
Peak memory 208976 kb
Host smart-10c3f3f5-d282-4328-a550-3bd4ce2596dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008442746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.4008442746
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.226008939
Short name T467
Test name
Test status
Simulation time 167404451 ps
CPU time 1.24 seconds
Started Jun 02 12:44:11 PM PDT 24
Finished Jun 02 12:44:12 PM PDT 24
Peak memory 200824 kb
Host smart-e58936df-b746-4778-9ff2-c09c3f0032b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226008939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.226008939
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2973743089
Short name T212
Test name
Test status
Simulation time 75698142 ps
CPU time 0.83 seconds
Started Jun 02 12:44:12 PM PDT 24
Finished Jun 02 12:44:14 PM PDT 24
Peak memory 200664 kb
Host smart-a3a63c98-b1f3-4e87-bdb7-a141664e7496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973743089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2973743089
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2432803608
Short name T539
Test name
Test status
Simulation time 1225627775 ps
CPU time 5.8 seconds
Started Jun 02 12:44:12 PM PDT 24
Finished Jun 02 12:44:19 PM PDT 24
Peak memory 221912 kb
Host smart-404fba1b-0dca-460c-9412-e1ade3911caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432803608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2432803608
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.209116393
Short name T479
Test name
Test status
Simulation time 243777381 ps
CPU time 1.21 seconds
Started Jun 02 12:44:14 PM PDT 24
Finished Jun 02 12:44:16 PM PDT 24
Peak memory 217996 kb
Host smart-5562e86f-7a7d-4fb6-a47d-4d911b9f89d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209116393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.209116393
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2115999285
Short name T22
Test name
Test status
Simulation time 250905014 ps
CPU time 0.99 seconds
Started Jun 02 12:44:12 PM PDT 24
Finished Jun 02 12:44:19 PM PDT 24
Peak memory 200796 kb
Host smart-80b811f4-1d53-400c-b6fb-c602b99ee6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115999285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2115999285
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.889085283
Short name T92
Test name
Test status
Simulation time 920572530 ps
CPU time 4.31 seconds
Started Jun 02 12:44:16 PM PDT 24
Finished Jun 02 12:44:21 PM PDT 24
Peak memory 200956 kb
Host smart-313d09e2-809f-49f2-b353-7c9f52761dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889085283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.889085283
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1776708897
Short name T236
Test name
Test status
Simulation time 145361419 ps
CPU time 1.11 seconds
Started Jun 02 12:44:12 PM PDT 24
Finished Jun 02 12:44:15 PM PDT 24
Peak memory 200764 kb
Host smart-f7313345-513a-47b7-9dbd-d231a8b855ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776708897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1776708897
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.970768269
Short name T334
Test name
Test status
Simulation time 204791337 ps
CPU time 1.38 seconds
Started Jun 02 12:44:12 PM PDT 24
Finished Jun 02 12:44:15 PM PDT 24
Peak memory 200992 kb
Host smart-021168d4-8b9f-466c-bee6-9f318589b0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970768269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.970768269
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.87476248
Short name T346
Test name
Test status
Simulation time 2021507229 ps
CPU time 7.71 seconds
Started Jun 02 12:44:14 PM PDT 24
Finished Jun 02 12:44:22 PM PDT 24
Peak memory 200984 kb
Host smart-f81f1ea7-3733-4942-a3ce-21fc68707569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87476248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.87476248
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1564581157
Short name T256
Test name
Test status
Simulation time 301943259 ps
CPU time 2.13 seconds
Started Jun 02 12:44:37 PM PDT 24
Finished Jun 02 12:44:39 PM PDT 24
Peak memory 209028 kb
Host smart-812b58c7-fe77-4137-b04a-5cad72c2ee28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564581157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1564581157
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1377984677
Short name T446
Test name
Test status
Simulation time 135739686 ps
CPU time 1.03 seconds
Started Jun 02 12:44:14 PM PDT 24
Finished Jun 02 12:44:16 PM PDT 24
Peak memory 200768 kb
Host smart-89cc293e-783c-4fda-89ee-784e5533e376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377984677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1377984677
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.2642109184
Short name T239
Test name
Test status
Simulation time 57653998 ps
CPU time 0.78 seconds
Started Jun 02 12:44:17 PM PDT 24
Finished Jun 02 12:44:18 PM PDT 24
Peak memory 200640 kb
Host smart-cd57a504-719d-469a-ab73-c571c670b191
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642109184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2642109184
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3420612016
Short name T7
Test name
Test status
Simulation time 1223215289 ps
CPU time 5.68 seconds
Started Jun 02 12:44:17 PM PDT 24
Finished Jun 02 12:44:24 PM PDT 24
Peak memory 221384 kb
Host smart-fde0f27b-ccdf-440e-ac7d-9a5483fc04c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420612016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3420612016
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2018458210
Short name T167
Test name
Test status
Simulation time 244734796 ps
CPU time 1.06 seconds
Started Jun 02 12:44:25 PM PDT 24
Finished Jun 02 12:44:26 PM PDT 24
Peak memory 209548 kb
Host smart-c21b30d7-970b-4453-b438-d0e3ef04d1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018458210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2018458210
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2168878171
Short name T261
Test name
Test status
Simulation time 165904249 ps
CPU time 0.87 seconds
Started Jun 02 12:44:13 PM PDT 24
Finished Jun 02 12:44:15 PM PDT 24
Peak memory 200596 kb
Host smart-07a456c5-6d90-4e90-8dfa-81b4870814b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168878171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2168878171
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.92192498
Short name T414
Test name
Test status
Simulation time 1749011159 ps
CPU time 6.72 seconds
Started Jun 02 12:44:33 PM PDT 24
Finished Jun 02 12:44:41 PM PDT 24
Peak memory 201016 kb
Host smart-1f5a4b62-e546-47fd-8897-a82cf3715665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92192498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.92192498
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1203918959
Short name T520
Test name
Test status
Simulation time 149607498 ps
CPU time 1.1 seconds
Started Jun 02 12:44:11 PM PDT 24
Finished Jun 02 12:44:13 PM PDT 24
Peak memory 200832 kb
Host smart-ea8c99d8-2b4a-4d7e-80eb-a751aff4fd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203918959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1203918959
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2415277461
Short name T328
Test name
Test status
Simulation time 252038198 ps
CPU time 1.47 seconds
Started Jun 02 12:44:17 PM PDT 24
Finished Jun 02 12:44:19 PM PDT 24
Peak memory 200992 kb
Host smart-d0eb2ff8-72d4-40be-9499-97e7d5ab560c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415277461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2415277461
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2569529377
Short name T168
Test name
Test status
Simulation time 6894827034 ps
CPU time 26.9 seconds
Started Jun 02 12:44:11 PM PDT 24
Finished Jun 02 12:44:39 PM PDT 24
Peak memory 209940 kb
Host smart-b1a925be-1a3b-4bda-9f80-d75b0e8374eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569529377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2569529377
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1031200025
Short name T364
Test name
Test status
Simulation time 376869506 ps
CPU time 2.1 seconds
Started Jun 02 12:44:24 PM PDT 24
Finished Jun 02 12:44:27 PM PDT 24
Peak memory 200788 kb
Host smart-fd32f153-6467-4a94-b807-3fbb9de9be65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031200025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1031200025
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2905035518
Short name T521
Test name
Test status
Simulation time 176573767 ps
CPU time 1.25 seconds
Started Jun 02 12:44:13 PM PDT 24
Finished Jun 02 12:44:15 PM PDT 24
Peak memory 200928 kb
Host smart-af02179f-6781-4fba-a417-b08b7cd46103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905035518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2905035518
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1855979205
Short name T411
Test name
Test status
Simulation time 124499844 ps
CPU time 0.9 seconds
Started Jun 02 12:44:15 PM PDT 24
Finished Jun 02 12:44:16 PM PDT 24
Peak memory 200576 kb
Host smart-c51a8a23-4d27-4422-81ff-5b0b28006c29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855979205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1855979205
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1783223445
Short name T34
Test name
Test status
Simulation time 2356628670 ps
CPU time 7.97 seconds
Started Jun 02 12:44:32 PM PDT 24
Finished Jun 02 12:44:41 PM PDT 24
Peak memory 218156 kb
Host smart-2d52b7ec-c1cf-4a0a-9c7a-3a602b38ef6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783223445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1783223445
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.4077390523
Short name T355
Test name
Test status
Simulation time 244373573 ps
CPU time 1.09 seconds
Started Jun 02 12:44:14 PM PDT 24
Finished Jun 02 12:44:16 PM PDT 24
Peak memory 218040 kb
Host smart-e9060f70-942e-43af-aa39-4127ab60b754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077390523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.4077390523
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2794585479
Short name T277
Test name
Test status
Simulation time 214404753 ps
CPU time 0.93 seconds
Started Jun 02 12:44:17 PM PDT 24
Finished Jun 02 12:44:19 PM PDT 24
Peak memory 200524 kb
Host smart-935cb05d-1f72-4575-9cca-c61104cd694e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794585479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2794585479
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.40325184
Short name T208
Test name
Test status
Simulation time 1029122313 ps
CPU time 5.11 seconds
Started Jun 02 12:44:11 PM PDT 24
Finished Jun 02 12:44:18 PM PDT 24
Peak memory 201056 kb
Host smart-0c1de9d2-7096-40f5-9c45-e1840caf617f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40325184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.40325184
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2824959278
Short name T65
Test name
Test status
Simulation time 166480714 ps
CPU time 1.16 seconds
Started Jun 02 12:44:12 PM PDT 24
Finished Jun 02 12:44:14 PM PDT 24
Peak memory 200812 kb
Host smart-072748d0-6909-4ca5-ba90-bafdc171226f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824959278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2824959278
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2516398767
Short name T510
Test name
Test status
Simulation time 251324038 ps
CPU time 1.48 seconds
Started Jun 02 12:44:33 PM PDT 24
Finished Jun 02 12:44:36 PM PDT 24
Peak memory 201028 kb
Host smart-664edefb-fc5c-4721-8db8-228a529ba9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516398767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2516398767
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.454004672
Short name T534
Test name
Test status
Simulation time 3970431466 ps
CPU time 18.13 seconds
Started Jun 02 12:44:17 PM PDT 24
Finished Jun 02 12:44:36 PM PDT 24
Peak memory 201036 kb
Host smart-9c76c1a0-f58d-41f0-bafb-d003e91deba7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454004672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.454004672
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1479925105
Short name T299
Test name
Test status
Simulation time 354399938 ps
CPU time 2.27 seconds
Started Jun 02 12:44:12 PM PDT 24
Finished Jun 02 12:44:15 PM PDT 24
Peak memory 201060 kb
Host smart-8a06c161-e58a-4e8b-a3bd-2f0e03e08d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479925105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1479925105
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.623519363
Short name T119
Test name
Test status
Simulation time 89565616 ps
CPU time 0.86 seconds
Started Jun 02 12:44:24 PM PDT 24
Finished Jun 02 12:44:25 PM PDT 24
Peak memory 200796 kb
Host smart-47ee1616-0abe-42ef-a9b6-6a06d7a174e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623519363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.623519363
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3177023653
Short name T163
Test name
Test status
Simulation time 63665121 ps
CPU time 0.77 seconds
Started Jun 02 12:43:37 PM PDT 24
Finished Jun 02 12:43:38 PM PDT 24
Peak memory 200624 kb
Host smart-c2572135-863e-497e-896e-c0284e03c3f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177023653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3177023653
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.689458636
Short name T41
Test name
Test status
Simulation time 1220918748 ps
CPU time 5.99 seconds
Started Jun 02 12:43:37 PM PDT 24
Finished Jun 02 12:43:44 PM PDT 24
Peak memory 218348 kb
Host smart-7914bd9c-d2b2-4762-9061-96ba024d9361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689458636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.689458636
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2313266062
Short name T490
Test name
Test status
Simulation time 247743636 ps
CPU time 1.08 seconds
Started Jun 02 12:43:37 PM PDT 24
Finished Jun 02 12:43:39 PM PDT 24
Peak memory 217944 kb
Host smart-7b639b5e-4523-4a02-b02e-c4135228f982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313266062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2313266062
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.797774610
Short name T477
Test name
Test status
Simulation time 192149307 ps
CPU time 0.9 seconds
Started Jun 02 12:43:38 PM PDT 24
Finished Jun 02 12:43:40 PM PDT 24
Peak memory 200616 kb
Host smart-f628ddd2-01f5-4dc4-a347-e98395209e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797774610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.797774610
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1794036367
Short name T362
Test name
Test status
Simulation time 1006824644 ps
CPU time 4.65 seconds
Started Jun 02 12:43:47 PM PDT 24
Finished Jun 02 12:43:53 PM PDT 24
Peak memory 200412 kb
Host smart-2d597abd-72d1-4133-9452-4a6c773f7a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794036367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1794036367
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3297922032
Short name T63
Test name
Test status
Simulation time 16556742325 ps
CPU time 26.07 seconds
Started Jun 02 12:43:35 PM PDT 24
Finished Jun 02 12:44:02 PM PDT 24
Peak memory 217636 kb
Host smart-fbc6b941-b1f5-46f8-bb60-c7abb266f5f4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297922032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3297922032
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.4221074879
Short name T124
Test name
Test status
Simulation time 105072063 ps
CPU time 1.01 seconds
Started Jun 02 12:43:37 PM PDT 24
Finished Jun 02 12:43:39 PM PDT 24
Peak memory 200824 kb
Host smart-4a80df87-52be-48fd-a660-ff7da08c1c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221074879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.4221074879
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2990785635
Short name T400
Test name
Test status
Simulation time 244316729 ps
CPU time 1.44 seconds
Started Jun 02 12:43:37 PM PDT 24
Finished Jun 02 12:43:39 PM PDT 24
Peak memory 201052 kb
Host smart-38101c91-c95e-4625-ae60-c36000379a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990785635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2990785635
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2692523212
Short name T509
Test name
Test status
Simulation time 395818557 ps
CPU time 2.36 seconds
Started Jun 02 12:43:34 PM PDT 24
Finished Jun 02 12:43:37 PM PDT 24
Peak memory 200732 kb
Host smart-d4ec579c-f7d1-4349-9e2e-979ca6377235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692523212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2692523212
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.1085057106
Short name T515
Test name
Test status
Simulation time 244204563 ps
CPU time 1.55 seconds
Started Jun 02 12:43:36 PM PDT 24
Finished Jun 02 12:43:38 PM PDT 24
Peak memory 200896 kb
Host smart-c881d366-a522-4024-a437-5d15e1222308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085057106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1085057106
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3193869226
Short name T327
Test name
Test status
Simulation time 58330799 ps
CPU time 0.75 seconds
Started Jun 02 12:44:30 PM PDT 24
Finished Jun 02 12:44:32 PM PDT 24
Peak memory 200652 kb
Host smart-595bc1cf-4415-472d-b977-384cf1dcba86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193869226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3193869226
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3775568803
Short name T46
Test name
Test status
Simulation time 2359052788 ps
CPU time 8.63 seconds
Started Jun 02 12:44:24 PM PDT 24
Finished Jun 02 12:44:34 PM PDT 24
Peak memory 218232 kb
Host smart-9edc1043-0f42-42be-832b-16c259aaecfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775568803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3775568803
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1804851961
Short name T174
Test name
Test status
Simulation time 243997197 ps
CPU time 1.19 seconds
Started Jun 02 12:44:35 PM PDT 24
Finished Jun 02 12:44:37 PM PDT 24
Peak memory 217960 kb
Host smart-bc833d88-dc05-4ac6-9e36-9c4bcd467be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804851961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1804851961
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3471258552
Short name T18
Test name
Test status
Simulation time 104240561 ps
CPU time 0.74 seconds
Started Jun 02 12:44:13 PM PDT 24
Finished Jun 02 12:44:14 PM PDT 24
Peak memory 200640 kb
Host smart-17a7b363-09a0-4b77-8c4b-b94f1560f3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471258552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3471258552
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3834694490
Short name T274
Test name
Test status
Simulation time 739286220 ps
CPU time 3.76 seconds
Started Jun 02 12:44:32 PM PDT 24
Finished Jun 02 12:44:37 PM PDT 24
Peak memory 200864 kb
Host smart-ed4ceb86-f6f5-44a3-9d56-2fa315bf366d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834694490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3834694490
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2827989577
Short name T460
Test name
Test status
Simulation time 181744442 ps
CPU time 1.17 seconds
Started Jun 02 12:44:32 PM PDT 24
Finished Jun 02 12:44:34 PM PDT 24
Peak memory 200804 kb
Host smart-7af5378a-e9f9-4901-a5e2-22ddecd43b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827989577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2827989577
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.1993740672
Short name T178
Test name
Test status
Simulation time 111566428 ps
CPU time 1.14 seconds
Started Jun 02 12:44:16 PM PDT 24
Finished Jun 02 12:44:18 PM PDT 24
Peak memory 200920 kb
Host smart-12b1f6c9-9ced-4ac7-b0f3-5c512e37144d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993740672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.1993740672
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2472638846
Short name T482
Test name
Test status
Simulation time 8693427855 ps
CPU time 28.45 seconds
Started Jun 02 12:44:28 PM PDT 24
Finished Jun 02 12:44:57 PM PDT 24
Peak memory 201136 kb
Host smart-321a8202-073e-459f-a00b-207cc70fb841
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472638846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2472638846
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.2063643397
Short name T453
Test name
Test status
Simulation time 127119015 ps
CPU time 1.48 seconds
Started Jun 02 12:44:12 PM PDT 24
Finished Jun 02 12:44:14 PM PDT 24
Peak memory 200796 kb
Host smart-1596e459-f4e5-4377-9125-7bbc5e492074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063643397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2063643397
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.730967746
Short name T351
Test name
Test status
Simulation time 272070988 ps
CPU time 1.58 seconds
Started Jun 02 12:44:13 PM PDT 24
Finished Jun 02 12:44:16 PM PDT 24
Peak memory 200832 kb
Host smart-bf0e2aae-4948-4491-a5cf-9b258f024eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730967746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.730967746
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2946874444
Short name T231
Test name
Test status
Simulation time 99452077 ps
CPU time 0.83 seconds
Started Jun 02 12:44:30 PM PDT 24
Finished Jun 02 12:44:31 PM PDT 24
Peak memory 200600 kb
Host smart-dbe0949a-a30d-400a-abc0-0c27e5bed17f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946874444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2946874444
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2285752349
Short name T342
Test name
Test status
Simulation time 1213925295 ps
CPU time 5.95 seconds
Started Jun 02 12:44:18 PM PDT 24
Finished Jun 02 12:44:25 PM PDT 24
Peak memory 218452 kb
Host smart-33363fd1-204d-4ccc-832d-466e0a7a6da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285752349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2285752349
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.590731355
Short name T278
Test name
Test status
Simulation time 244027492 ps
CPU time 1.08 seconds
Started Jun 02 12:44:29 PM PDT 24
Finished Jun 02 12:44:31 PM PDT 24
Peak memory 217880 kb
Host smart-cf02baa3-57fe-4d7c-9d5b-4a28dd23c68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590731355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.590731355
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.2755437700
Short name T499
Test name
Test status
Simulation time 96073146 ps
CPU time 0.78 seconds
Started Jun 02 12:44:33 PM PDT 24
Finished Jun 02 12:44:35 PM PDT 24
Peak memory 200612 kb
Host smart-527c9ac7-f0eb-4500-8137-5cb63bb3f1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755437700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2755437700
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3313556072
Short name T10
Test name
Test status
Simulation time 1636880426 ps
CPU time 6.17 seconds
Started Jun 02 12:44:22 PM PDT 24
Finished Jun 02 12:44:28 PM PDT 24
Peak memory 200976 kb
Host smart-d04553d4-4dfd-4773-bb3b-40259cce81b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313556072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3313556072
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.4225410041
Short name T189
Test name
Test status
Simulation time 104742737 ps
CPU time 1.1 seconds
Started Jun 02 12:44:24 PM PDT 24
Finished Jun 02 12:44:26 PM PDT 24
Peak memory 200752 kb
Host smart-3be3f40c-59d5-4213-8c7f-ef9115aa080e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225410041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.4225410041
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1542584137
Short name T489
Test name
Test status
Simulation time 121566076 ps
CPU time 1.19 seconds
Started Jun 02 12:44:19 PM PDT 24
Finished Jun 02 12:44:21 PM PDT 24
Peak memory 200892 kb
Host smart-603ede14-eceb-4202-97a8-d3b248710909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542584137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1542584137
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3216867254
Short name T200
Test name
Test status
Simulation time 17564372504 ps
CPU time 65.02 seconds
Started Jun 02 12:44:30 PM PDT 24
Finished Jun 02 12:45:36 PM PDT 24
Peak memory 201140 kb
Host smart-f19525ce-b5e7-4642-b4e1-7cb406c46fc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216867254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3216867254
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.348521194
Short name T426
Test name
Test status
Simulation time 130736004 ps
CPU time 1.71 seconds
Started Jun 02 12:44:20 PM PDT 24
Finished Jun 02 12:44:22 PM PDT 24
Peak memory 208940 kb
Host smart-cc0c89ef-8a41-48db-93d4-1cce26f58d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348521194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.348521194
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2180979383
Short name T255
Test name
Test status
Simulation time 139902224 ps
CPU time 1.19 seconds
Started Jun 02 12:44:24 PM PDT 24
Finished Jun 02 12:44:26 PM PDT 24
Peak memory 200748 kb
Host smart-7856b25c-fc43-4d8e-9e27-1c2b33f9cf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180979383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2180979383
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3401301696
Short name T145
Test name
Test status
Simulation time 74194868 ps
CPU time 0.76 seconds
Started Jun 02 12:44:29 PM PDT 24
Finished Jun 02 12:44:36 PM PDT 24
Peak memory 200652 kb
Host smart-20fe4283-aa42-4b8b-824e-1cabebfeecb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401301696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3401301696
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1676170030
Short name T416
Test name
Test status
Simulation time 1899969889 ps
CPU time 7.12 seconds
Started Jun 02 12:44:26 PM PDT 24
Finished Jun 02 12:44:34 PM PDT 24
Peak memory 218368 kb
Host smart-0b573e34-ddc7-426e-847e-9dc48a7bb8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676170030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1676170030
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.425206456
Short name T272
Test name
Test status
Simulation time 244995428 ps
CPU time 1.04 seconds
Started Jun 02 12:44:22 PM PDT 24
Finished Jun 02 12:44:24 PM PDT 24
Peak memory 217948 kb
Host smart-6dcb478a-2bc1-4f0b-bed4-3373ed61ae61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425206456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.425206456
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3549391728
Short name T14
Test name
Test status
Simulation time 240495895 ps
CPU time 0.95 seconds
Started Jun 02 12:44:24 PM PDT 24
Finished Jun 02 12:44:26 PM PDT 24
Peak memory 200600 kb
Host smart-1f5b002a-beb2-4ccd-b6fa-73777c1c98e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549391728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3549391728
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.4107473956
Short name T184
Test name
Test status
Simulation time 1772969973 ps
CPU time 6.78 seconds
Started Jun 02 12:44:18 PM PDT 24
Finished Jun 02 12:44:25 PM PDT 24
Peak memory 200996 kb
Host smart-889fbb60-f4b7-4c9a-9c1f-4d0bfa6358ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107473956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.4107473956
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1409560498
Short name T230
Test name
Test status
Simulation time 165999519 ps
CPU time 1.17 seconds
Started Jun 02 12:44:31 PM PDT 24
Finished Jun 02 12:44:33 PM PDT 24
Peak memory 200760 kb
Host smart-ce6fcbbd-40d6-44ab-b76b-06af2b3476c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409560498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1409560498
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1660304309
Short name T300
Test name
Test status
Simulation time 121248052 ps
CPU time 1.19 seconds
Started Jun 02 12:44:30 PM PDT 24
Finished Jun 02 12:44:32 PM PDT 24
Peak memory 200904 kb
Host smart-0934a19f-9d52-42c5-b8ec-4d6a323e5360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660304309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1660304309
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.452549414
Short name T434
Test name
Test status
Simulation time 216875251 ps
CPU time 1.3 seconds
Started Jun 02 12:44:22 PM PDT 24
Finished Jun 02 12:44:24 PM PDT 24
Peak memory 200636 kb
Host smart-18b32a3c-457a-49be-beff-3d020a67fe3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452549414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.452549414
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.855056253
Short name T537
Test name
Test status
Simulation time 266071684 ps
CPU time 1.76 seconds
Started Jun 02 12:44:22 PM PDT 24
Finished Jun 02 12:44:24 PM PDT 24
Peak memory 200796 kb
Host smart-c451ece7-3544-47a0-b946-0e3787e1d69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855056253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.855056253
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.633447825
Short name T386
Test name
Test status
Simulation time 192861026 ps
CPU time 1.17 seconds
Started Jun 02 12:44:20 PM PDT 24
Finished Jun 02 12:44:22 PM PDT 24
Peak memory 200792 kb
Host smart-5f2e6812-1eeb-4c8c-adf4-2c9df48c4e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633447825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.633447825
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2102279291
Short name T388
Test name
Test status
Simulation time 71113001 ps
CPU time 0.76 seconds
Started Jun 02 12:44:39 PM PDT 24
Finished Jun 02 12:44:40 PM PDT 24
Peak memory 200660 kb
Host smart-08f0bb67-1026-47b8-9f0f-a88a62e4604b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102279291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2102279291
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.902401165
Short name T283
Test name
Test status
Simulation time 1886049798 ps
CPU time 8.1 seconds
Started Jun 02 12:44:30 PM PDT 24
Finished Jun 02 12:44:38 PM PDT 24
Peak memory 218408 kb
Host smart-256a4519-05f7-4583-b6d1-e4445cf82f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902401165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.902401165
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.4164641435
Short name T298
Test name
Test status
Simulation time 244408704 ps
CPU time 1.12 seconds
Started Jun 02 12:44:31 PM PDT 24
Finished Jun 02 12:44:32 PM PDT 24
Peak memory 217980 kb
Host smart-d580e34f-ae20-4db4-be57-650e76690871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164641435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.4164641435
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.4193182298
Short name T385
Test name
Test status
Simulation time 203899602 ps
CPU time 0.87 seconds
Started Jun 02 12:44:34 PM PDT 24
Finished Jun 02 12:44:36 PM PDT 24
Peak memory 200572 kb
Host smart-9f7fbee7-85d4-4fa6-9d4a-2c397b56280e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193182298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.4193182298
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3883711487
Short name T430
Test name
Test status
Simulation time 1382873159 ps
CPU time 6.19 seconds
Started Jun 02 12:44:22 PM PDT 24
Finished Jun 02 12:44:29 PM PDT 24
Peak memory 200988 kb
Host smart-05f00ec8-36fc-4447-b693-af8db9357882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883711487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3883711487
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1639913470
Short name T504
Test name
Test status
Simulation time 103023454 ps
CPU time 0.96 seconds
Started Jun 02 12:44:33 PM PDT 24
Finished Jun 02 12:44:36 PM PDT 24
Peak memory 200788 kb
Host smart-d8f85a65-b4b4-4abe-a5a5-bd5016aea9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639913470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1639913470
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3238513676
Short name T503
Test name
Test status
Simulation time 106367682 ps
CPU time 1.19 seconds
Started Jun 02 12:44:24 PM PDT 24
Finished Jun 02 12:44:26 PM PDT 24
Peak memory 200928 kb
Host smart-ad630444-d2a1-4772-a4ef-dfb5f09fc4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238513676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3238513676
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1899209943
Short name T69
Test name
Test status
Simulation time 669414585 ps
CPU time 3.06 seconds
Started Jun 02 12:44:30 PM PDT 24
Finished Jun 02 12:44:34 PM PDT 24
Peak memory 201040 kb
Host smart-2cd79952-fe59-445c-b715-f4ececc4ad09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899209943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1899209943
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3707502517
Short name T144
Test name
Test status
Simulation time 310041735 ps
CPU time 2.4 seconds
Started Jun 02 12:44:35 PM PDT 24
Finished Jun 02 12:44:38 PM PDT 24
Peak memory 200800 kb
Host smart-db727376-4647-4e67-873e-abe9735f6344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707502517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3707502517
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.230226677
Short name T146
Test name
Test status
Simulation time 124116182 ps
CPU time 1.08 seconds
Started Jun 02 12:44:17 PM PDT 24
Finished Jun 02 12:44:19 PM PDT 24
Peak memory 200760 kb
Host smart-31b14460-c99d-4002-a856-b3d82e5f418c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230226677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.230226677
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.1022270786
Short name T348
Test name
Test status
Simulation time 71820074 ps
CPU time 0.77 seconds
Started Jun 02 12:44:28 PM PDT 24
Finished Jun 02 12:44:30 PM PDT 24
Peak memory 200676 kb
Host smart-f8706eb8-a0b2-4438-a26e-ed705218bd83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022270786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1022270786
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.2327017501
Short name T35
Test name
Test status
Simulation time 2357639946 ps
CPU time 8.42 seconds
Started Jun 02 12:44:20 PM PDT 24
Finished Jun 02 12:44:29 PM PDT 24
Peak memory 230692 kb
Host smart-5eca7b5c-910f-4b33-93c7-4eae152cb3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327017501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2327017501
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3563721675
Short name T366
Test name
Test status
Simulation time 245324467 ps
CPU time 1.22 seconds
Started Jun 02 12:44:26 PM PDT 24
Finished Jun 02 12:44:28 PM PDT 24
Peak memory 218156 kb
Host smart-76c0489d-e4bf-4390-8846-e387efbe705b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563721675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3563721675
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3040405903
Short name T15
Test name
Test status
Simulation time 115401205 ps
CPU time 0.76 seconds
Started Jun 02 12:44:34 PM PDT 24
Finished Jun 02 12:44:36 PM PDT 24
Peak memory 200576 kb
Host smart-ee7aba57-3849-44a3-831f-3ecb3768a6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040405903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3040405903
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.4131167779
Short name T398
Test name
Test status
Simulation time 1746749937 ps
CPU time 6.88 seconds
Started Jun 02 12:44:18 PM PDT 24
Finished Jun 02 12:44:26 PM PDT 24
Peak memory 200988 kb
Host smart-a4b90bae-7dee-45f9-8b62-4c748bc76d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131167779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.4131167779
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3363141784
Short name T252
Test name
Test status
Simulation time 156444342 ps
CPU time 1.12 seconds
Started Jun 02 12:44:34 PM PDT 24
Finished Jun 02 12:44:37 PM PDT 24
Peak memory 200816 kb
Host smart-8bee199e-72f7-4fd0-8e3b-4df296daf499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363141784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3363141784
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2138190375
Short name T363
Test name
Test status
Simulation time 243746000 ps
CPU time 1.57 seconds
Started Jun 02 12:44:18 PM PDT 24
Finished Jun 02 12:44:20 PM PDT 24
Peak memory 200992 kb
Host smart-a8014015-72f3-404f-8bf3-5e9fe67e76ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138190375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2138190375
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.480758743
Short name T449
Test name
Test status
Simulation time 1092132668 ps
CPU time 5.32 seconds
Started Jun 02 12:44:37 PM PDT 24
Finished Jun 02 12:44:43 PM PDT 24
Peak memory 209156 kb
Host smart-8488fd2f-be6d-400e-ab6e-1e79179f5154
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480758743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.480758743
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.614314561
Short name T275
Test name
Test status
Simulation time 150619916 ps
CPU time 1.85 seconds
Started Jun 02 12:44:24 PM PDT 24
Finished Jun 02 12:44:27 PM PDT 24
Peak memory 200740 kb
Host smart-afb030d9-c61b-40a1-b395-f7763cab31bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614314561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.614314561
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.2673931381
Short name T491
Test name
Test status
Simulation time 99737902 ps
CPU time 1 seconds
Started Jun 02 12:44:24 PM PDT 24
Finished Jun 02 12:44:25 PM PDT 24
Peak memory 200808 kb
Host smart-0d501df7-9cc9-433a-b00f-99dac668cd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673931381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2673931381
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1703597518
Short name T39
Test name
Test status
Simulation time 61244743 ps
CPU time 0.74 seconds
Started Jun 02 12:44:28 PM PDT 24
Finished Jun 02 12:44:30 PM PDT 24
Peak memory 200596 kb
Host smart-ca28ff4f-8505-4e53-a2f1-dee843ce45b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703597518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1703597518
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.2283670846
Short name T532
Test name
Test status
Simulation time 1883044745 ps
CPU time 7.82 seconds
Started Jun 02 12:44:39 PM PDT 24
Finished Jun 02 12:44:48 PM PDT 24
Peak memory 222604 kb
Host smart-139fab77-401c-4655-98ed-88258ef09cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283670846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2283670846
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3474610187
Short name T308
Test name
Test status
Simulation time 244693663 ps
CPU time 1.11 seconds
Started Jun 02 12:44:33 PM PDT 24
Finished Jun 02 12:44:35 PM PDT 24
Peak memory 218036 kb
Host smart-1f227730-8f40-4e6a-b97a-eda688def8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474610187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3474610187
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3728614852
Short name T459
Test name
Test status
Simulation time 141701551 ps
CPU time 0.82 seconds
Started Jun 02 12:44:28 PM PDT 24
Finished Jun 02 12:44:30 PM PDT 24
Peak memory 200568 kb
Host smart-af02dd4d-9691-41e9-9dbd-0b2c99611d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728614852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3728614852
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3542846891
Short name T110
Test name
Test status
Simulation time 1943802768 ps
CPU time 7.29 seconds
Started Jun 02 12:44:34 PM PDT 24
Finished Jun 02 12:44:42 PM PDT 24
Peak memory 200976 kb
Host smart-5ff800fe-d23e-4d33-b537-0529e39ca893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542846891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3542846891
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.123233340
Short name T370
Test name
Test status
Simulation time 100990853 ps
CPU time 0.99 seconds
Started Jun 02 12:44:38 PM PDT 24
Finished Jun 02 12:44:40 PM PDT 24
Peak memory 200808 kb
Host smart-ba177342-ae15-4daf-948a-14d5070039e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123233340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.123233340
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2070544777
Short name T143
Test name
Test status
Simulation time 120860778 ps
CPU time 1.23 seconds
Started Jun 02 12:44:25 PM PDT 24
Finished Jun 02 12:44:27 PM PDT 24
Peak memory 200964 kb
Host smart-3a78f6d7-bcd0-4f66-89a0-150ba103cb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070544777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2070544777
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1010520041
Short name T314
Test name
Test status
Simulation time 6480210422 ps
CPU time 23.91 seconds
Started Jun 02 12:44:38 PM PDT 24
Finished Jun 02 12:45:02 PM PDT 24
Peak memory 201276 kb
Host smart-c0b12aa3-dbc7-4c95-aab6-0d971c9649d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010520041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1010520041
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1387155712
Short name T511
Test name
Test status
Simulation time 358204374 ps
CPU time 2.27 seconds
Started Jun 02 12:44:38 PM PDT 24
Finished Jun 02 12:44:41 PM PDT 24
Peak memory 200932 kb
Host smart-e7e24468-f78e-4ee7-b141-949b0067be0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387155712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1387155712
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.55921976
Short name T24
Test name
Test status
Simulation time 218525795 ps
CPU time 1.33 seconds
Started Jun 02 12:44:50 PM PDT 24
Finished Jun 02 12:44:52 PM PDT 24
Peak memory 200948 kb
Host smart-a6b0ddf6-e1f5-40e8-829a-7be1c693f14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55921976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.55921976
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1795219681
Short name T293
Test name
Test status
Simulation time 81451124 ps
CPU time 0.83 seconds
Started Jun 02 12:44:38 PM PDT 24
Finished Jun 02 12:44:39 PM PDT 24
Peak memory 200576 kb
Host smart-97b5cacc-f602-4752-836e-6e9b453c9e9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795219681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1795219681
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2394387191
Short name T40
Test name
Test status
Simulation time 2179724529 ps
CPU time 7.88 seconds
Started Jun 02 12:44:36 PM PDT 24
Finished Jun 02 12:44:44 PM PDT 24
Peak memory 218552 kb
Host smart-a9188450-0507-4a5d-a1c4-eed8b1f0708a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394387191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2394387191
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.642390787
Short name T397
Test name
Test status
Simulation time 244209154 ps
CPU time 1.02 seconds
Started Jun 02 12:44:45 PM PDT 24
Finished Jun 02 12:44:46 PM PDT 24
Peak memory 218164 kb
Host smart-bf83e995-fac0-4765-b50a-eb640fabfb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642390787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.642390787
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.113739341
Short name T527
Test name
Test status
Simulation time 191238583 ps
CPU time 0.94 seconds
Started Jun 02 12:44:32 PM PDT 24
Finished Jun 02 12:44:34 PM PDT 24
Peak memory 200604 kb
Host smart-1d269930-9f80-4cd8-b638-e98a80e4e6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113739341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.113739341
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.522996913
Short name T420
Test name
Test status
Simulation time 1381580048 ps
CPU time 5.39 seconds
Started Jun 02 12:44:27 PM PDT 24
Finished Jun 02 12:44:34 PM PDT 24
Peak memory 200960 kb
Host smart-755a0ccc-f0bf-46f0-ae1d-b470c809f625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522996913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.522996913
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3441997704
Short name T243
Test name
Test status
Simulation time 158000053 ps
CPU time 1.16 seconds
Started Jun 02 12:44:25 PM PDT 24
Finished Jun 02 12:44:26 PM PDT 24
Peak memory 200836 kb
Host smart-d45d26f3-1359-4dac-a991-f830c7795d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441997704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3441997704
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2216817717
Short name T260
Test name
Test status
Simulation time 246035168 ps
CPU time 1.56 seconds
Started Jun 02 12:44:31 PM PDT 24
Finished Jun 02 12:44:33 PM PDT 24
Peak memory 200944 kb
Host smart-5a74c9b5-958c-4f93-9918-9b11841f3dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216817717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2216817717
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3646577206
Short name T427
Test name
Test status
Simulation time 1778873732 ps
CPU time 8.48 seconds
Started Jun 02 12:44:38 PM PDT 24
Finished Jun 02 12:44:47 PM PDT 24
Peak memory 200996 kb
Host smart-36c0234a-6502-4caa-b3f5-6e550fd96a99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646577206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3646577206
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.2153170202
Short name T451
Test name
Test status
Simulation time 336823056 ps
CPU time 2.29 seconds
Started Jun 02 12:44:33 PM PDT 24
Finished Jun 02 12:44:36 PM PDT 24
Peak memory 208932 kb
Host smart-5631aa3d-ad90-45e7-a582-5286dce93bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153170202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2153170202
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.4292289540
Short name T408
Test name
Test status
Simulation time 144943476 ps
CPU time 1.23 seconds
Started Jun 02 12:44:26 PM PDT 24
Finished Jun 02 12:44:28 PM PDT 24
Peak memory 200832 kb
Host smart-159f6153-0a8b-4640-9c11-35d262ed6225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292289540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.4292289540
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1459992989
Short name T424
Test name
Test status
Simulation time 77748382 ps
CPU time 0.79 seconds
Started Jun 02 12:44:25 PM PDT 24
Finished Jun 02 12:44:27 PM PDT 24
Peak memory 200608 kb
Host smart-dff10219-c247-4388-8a46-361499609624
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459992989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1459992989
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.983302050
Short name T48
Test name
Test status
Simulation time 1233705749 ps
CPU time 6.31 seconds
Started Jun 02 12:44:27 PM PDT 24
Finished Jun 02 12:44:35 PM PDT 24
Peak memory 218460 kb
Host smart-d593348e-6813-406f-8819-04ea8e1e94cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983302050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.983302050
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.4026515550
Short name T179
Test name
Test status
Simulation time 244792648 ps
CPU time 1.02 seconds
Started Jun 02 12:44:40 PM PDT 24
Finished Jun 02 12:44:41 PM PDT 24
Peak memory 218240 kb
Host smart-8d6ac456-6406-4384-a457-1a38b585eba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026515550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.4026515550
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.525759089
Short name T295
Test name
Test status
Simulation time 138030954 ps
CPU time 0.82 seconds
Started Jun 02 12:44:27 PM PDT 24
Finished Jun 02 12:44:29 PM PDT 24
Peak memory 200608 kb
Host smart-42fe5d0d-e716-43be-b1bd-264fc7f608ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525759089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.525759089
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.3717449941
Short name T225
Test name
Test status
Simulation time 1053668521 ps
CPU time 5.25 seconds
Started Jun 02 12:44:27 PM PDT 24
Finished Jun 02 12:44:33 PM PDT 24
Peak memory 200972 kb
Host smart-a63196b8-3181-43cd-b41c-a2f06f7b4f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717449941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3717449941
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.1057803478
Short name T150
Test name
Test status
Simulation time 103241183 ps
CPU time 1.04 seconds
Started Jun 02 12:44:28 PM PDT 24
Finished Jun 02 12:44:29 PM PDT 24
Peak memory 200804 kb
Host smart-0cdcd0a7-5ff4-48f4-9536-3e8aaac6196b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057803478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.1057803478
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.136683790
Short name T350
Test name
Test status
Simulation time 256404369 ps
CPU time 1.45 seconds
Started Jun 02 12:44:36 PM PDT 24
Finished Jun 02 12:44:38 PM PDT 24
Peak memory 200844 kb
Host smart-b4e72593-f235-489f-9e4c-f5ba9b77e1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136683790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.136683790
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3459870618
Short name T392
Test name
Test status
Simulation time 7503831842 ps
CPU time 28.96 seconds
Started Jun 02 12:44:37 PM PDT 24
Finished Jun 02 12:45:06 PM PDT 24
Peak memory 209284 kb
Host smart-8f74f31f-c719-4bff-a5bd-04bedeca3070
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459870618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3459870618
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2013158594
Short name T198
Test name
Test status
Simulation time 452357800 ps
CPU time 2.35 seconds
Started Jun 02 12:44:49 PM PDT 24
Finished Jun 02 12:44:52 PM PDT 24
Peak memory 200932 kb
Host smart-a9a8dc60-8449-4b80-af27-067b8fc3d9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013158594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2013158594
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.3077247503
Short name T211
Test name
Test status
Simulation time 176825078 ps
CPU time 1.26 seconds
Started Jun 02 12:44:25 PM PDT 24
Finished Jun 02 12:44:27 PM PDT 24
Peak memory 200988 kb
Host smart-12028107-ee9d-4ee8-92c6-e399e15f3c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077247503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3077247503
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.527074121
Short name T461
Test name
Test status
Simulation time 64064125 ps
CPU time 0.77 seconds
Started Jun 02 12:44:33 PM PDT 24
Finished Jun 02 12:44:35 PM PDT 24
Peak memory 200588 kb
Host smart-e8e99fbf-c5bf-444a-9104-3a4819bf13a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527074121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.527074121
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2177250660
Short name T3
Test name
Test status
Simulation time 244082998 ps
CPU time 1.14 seconds
Started Jun 02 12:44:36 PM PDT 24
Finished Jun 02 12:44:38 PM PDT 24
Peak memory 217900 kb
Host smart-af500c3b-43af-4cc2-90bc-cf98219c5eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177250660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2177250660
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3598470305
Short name T501
Test name
Test status
Simulation time 158824959 ps
CPU time 0.91 seconds
Started Jun 02 12:44:36 PM PDT 24
Finished Jun 02 12:44:38 PM PDT 24
Peak memory 200568 kb
Host smart-6b379c47-430e-4302-8423-cffaf5f4ebe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598470305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3598470305
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.763705964
Short name T536
Test name
Test status
Simulation time 1043030671 ps
CPU time 4.95 seconds
Started Jun 02 12:44:34 PM PDT 24
Finished Jun 02 12:44:40 PM PDT 24
Peak memory 201000 kb
Host smart-5dd94387-3fb1-4d8b-abc2-c5254fd1f2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763705964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.763705964
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.92812764
Short name T371
Test name
Test status
Simulation time 176530092 ps
CPU time 1.21 seconds
Started Jun 02 12:44:33 PM PDT 24
Finished Jun 02 12:44:36 PM PDT 24
Peak memory 200820 kb
Host smart-d3616223-cf94-46f4-b429-4e8670b490b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92812764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.92812764
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.3238627996
Short name T203
Test name
Test status
Simulation time 260083707 ps
CPU time 1.5 seconds
Started Jun 02 12:44:27 PM PDT 24
Finished Jun 02 12:44:29 PM PDT 24
Peak memory 200980 kb
Host smart-7b93f8d2-96f9-4c5a-b902-a121fb631882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238627996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3238627996
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.249663441
Short name T357
Test name
Test status
Simulation time 6947845724 ps
CPU time 24.63 seconds
Started Jun 02 12:44:46 PM PDT 24
Finished Jun 02 12:45:11 PM PDT 24
Peak memory 209280 kb
Host smart-988763ea-0e81-40b4-8893-1d7f37ff5f11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249663441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.249663441
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.112463993
Short name T381
Test name
Test status
Simulation time 314985054 ps
CPU time 2.15 seconds
Started Jun 02 12:44:33 PM PDT 24
Finished Jun 02 12:44:36 PM PDT 24
Peak memory 200732 kb
Host smart-a54dc2f6-3fa5-476b-b1d1-60225a678e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112463993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.112463993
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2049894558
Short name T324
Test name
Test status
Simulation time 148148130 ps
CPU time 1.12 seconds
Started Jun 02 12:44:37 PM PDT 24
Finished Jun 02 12:44:38 PM PDT 24
Peak memory 200780 kb
Host smart-387da915-fde0-461c-8184-41bd05493f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049894558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2049894558
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.4269388400
Short name T244
Test name
Test status
Simulation time 89371619 ps
CPU time 0.88 seconds
Started Jun 02 12:44:32 PM PDT 24
Finished Jun 02 12:44:34 PM PDT 24
Peak memory 200660 kb
Host smart-14ef185b-6a45-436c-b71d-7e44c1693682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269388400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.4269388400
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.4114209424
Short name T312
Test name
Test status
Simulation time 1888793236 ps
CPU time 7.25 seconds
Started Jun 02 12:44:31 PM PDT 24
Finished Jun 02 12:44:40 PM PDT 24
Peak memory 221984 kb
Host smart-ac582b77-b7fa-4d89-b211-22c5567e6030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114209424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.4114209424
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1177595757
Short name T423
Test name
Test status
Simulation time 243792527 ps
CPU time 1.17 seconds
Started Jun 02 12:44:38 PM PDT 24
Finished Jun 02 12:44:40 PM PDT 24
Peak memory 217968 kb
Host smart-aba395c5-d374-4eca-891e-1746cd3276c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177595757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1177595757
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.3308877184
Short name T246
Test name
Test status
Simulation time 89244044 ps
CPU time 0.74 seconds
Started Jun 02 12:44:43 PM PDT 24
Finished Jun 02 12:44:44 PM PDT 24
Peak memory 200624 kb
Host smart-50e7816f-20f7-4c82-85cc-7aabc0aa4ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308877184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3308877184
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.774645804
Short name T201
Test name
Test status
Simulation time 1010753798 ps
CPU time 4.98 seconds
Started Jun 02 12:44:45 PM PDT 24
Finished Jun 02 12:44:51 PM PDT 24
Peak memory 201028 kb
Host smart-4c8f8fac-9c45-460d-8830-885ee2636a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774645804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.774645804
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.625605775
Short name T224
Test name
Test status
Simulation time 101023995 ps
CPU time 1 seconds
Started Jun 02 12:44:33 PM PDT 24
Finished Jun 02 12:44:36 PM PDT 24
Peak memory 200788 kb
Host smart-929826a1-e6ab-4577-a46f-12219795cd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625605775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.625605775
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1634802182
Short name T204
Test name
Test status
Simulation time 252362968 ps
CPU time 1.56 seconds
Started Jun 02 12:44:44 PM PDT 24
Finished Jun 02 12:44:47 PM PDT 24
Peak memory 200980 kb
Host smart-f0b86e85-be23-4a48-9a0a-cde19a9405ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634802182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1634802182
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2292619407
Short name T493
Test name
Test status
Simulation time 2070120897 ps
CPU time 9.18 seconds
Started Jun 02 12:44:45 PM PDT 24
Finished Jun 02 12:44:55 PM PDT 24
Peak memory 201020 kb
Host smart-6ba8bc48-8b90-4c05-9135-052e74461af6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292619407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2292619407
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.808755181
Short name T359
Test name
Test status
Simulation time 158106969 ps
CPU time 2.04 seconds
Started Jun 02 12:44:47 PM PDT 24
Finished Jun 02 12:44:50 PM PDT 24
Peak memory 200764 kb
Host smart-76acc70d-2355-46b4-858f-d6faac89d8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808755181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.808755181
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1504943208
Short name T191
Test name
Test status
Simulation time 132821243 ps
CPU time 0.97 seconds
Started Jun 02 12:44:35 PM PDT 24
Finished Jun 02 12:44:37 PM PDT 24
Peak memory 200756 kb
Host smart-0f025378-d618-41aa-92e6-3befd7109518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504943208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1504943208
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.4191734332
Short name T271
Test name
Test status
Simulation time 70534469 ps
CPU time 0.77 seconds
Started Jun 02 12:43:44 PM PDT 24
Finished Jun 02 12:43:45 PM PDT 24
Peak memory 200632 kb
Host smart-390f2701-76e2-44f7-aa67-1679637e9673
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191734332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.4191734332
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2460807067
Short name T378
Test name
Test status
Simulation time 2365391689 ps
CPU time 7.86 seconds
Started Jun 02 12:43:46 PM PDT 24
Finished Jun 02 12:43:54 PM PDT 24
Peak memory 222476 kb
Host smart-48a4fdb8-6e02-4cc7-8f88-ed22668295ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460807067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2460807067
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3689656503
Short name T193
Test name
Test status
Simulation time 245408951 ps
CPU time 1.15 seconds
Started Jun 02 12:43:50 PM PDT 24
Finished Jun 02 12:43:52 PM PDT 24
Peak memory 218104 kb
Host smart-1a622406-88e6-4a69-87d7-a38d4134cb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689656503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3689656503
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.4094640024
Short name T290
Test name
Test status
Simulation time 191695706 ps
CPU time 0.89 seconds
Started Jun 02 12:43:38 PM PDT 24
Finished Jun 02 12:43:40 PM PDT 24
Peak memory 200612 kb
Host smart-1ab7c77c-6284-4c84-85d6-30fc63740a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094640024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.4094640024
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2954032015
Short name T86
Test name
Test status
Simulation time 1002045856 ps
CPU time 5.43 seconds
Started Jun 02 12:43:34 PM PDT 24
Finished Jun 02 12:43:39 PM PDT 24
Peak memory 200912 kb
Host smart-de314e0b-e745-45d7-97e3-54e0de04a09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954032015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2954032015
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.1106494710
Short name T59
Test name
Test status
Simulation time 8323522353 ps
CPU time 13.16 seconds
Started Jun 02 12:43:48 PM PDT 24
Finished Jun 02 12:44:02 PM PDT 24
Peak memory 217500 kb
Host smart-8bab23d9-bc72-45bf-adbb-a008b9335d7f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106494710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1106494710
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3549648402
Short name T321
Test name
Test status
Simulation time 173817724 ps
CPU time 1.33 seconds
Started Jun 02 12:43:37 PM PDT 24
Finished Jun 02 12:43:39 PM PDT 24
Peak memory 200820 kb
Host smart-42305b7c-df21-4722-9769-c8353b49b804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549648402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3549648402
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1896286291
Short name T419
Test name
Test status
Simulation time 126203530 ps
CPU time 1.19 seconds
Started Jun 02 12:43:36 PM PDT 24
Finished Jun 02 12:43:37 PM PDT 24
Peak memory 201028 kb
Host smart-fcc64126-7878-45b8-adc2-09197857c2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896286291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1896286291
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.910231277
Short name T483
Test name
Test status
Simulation time 5512749937 ps
CPU time 21.04 seconds
Started Jun 02 12:43:46 PM PDT 24
Finished Jun 02 12:44:07 PM PDT 24
Peak memory 209328 kb
Host smart-2a9331a9-e290-4377-8c9f-69b65f763b53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910231277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.910231277
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3343725092
Short name T404
Test name
Test status
Simulation time 143990940 ps
CPU time 2.03 seconds
Started Jun 02 12:43:37 PM PDT 24
Finished Jun 02 12:43:40 PM PDT 24
Peak memory 200696 kb
Host smart-bb86ddc7-312e-41dc-86a4-1a21a57e560a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343725092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3343725092
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.142828705
Short name T221
Test name
Test status
Simulation time 117041625 ps
CPU time 1 seconds
Started Jun 02 12:43:37 PM PDT 24
Finished Jun 02 12:43:38 PM PDT 24
Peak memory 200692 kb
Host smart-54a8c6aa-79a6-4baf-b5e7-299e6c226bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142828705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.142828705
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3594417366
Short name T137
Test name
Test status
Simulation time 57777474 ps
CPU time 0.74 seconds
Started Jun 02 12:44:33 PM PDT 24
Finished Jun 02 12:44:35 PM PDT 24
Peak memory 200600 kb
Host smart-96da4ae7-2189-444d-a249-e8ce7466ade0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594417366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3594417366
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.941903828
Short name T116
Test name
Test status
Simulation time 1906661255 ps
CPU time 7.6 seconds
Started Jun 02 12:44:38 PM PDT 24
Finished Jun 02 12:44:47 PM PDT 24
Peak memory 222496 kb
Host smart-8620a775-3b3f-4ea9-ae0e-df5d2916f245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941903828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.941903828
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1237319852
Short name T507
Test name
Test status
Simulation time 244289628 ps
CPU time 1.11 seconds
Started Jun 02 12:44:38 PM PDT 24
Finished Jun 02 12:44:40 PM PDT 24
Peak memory 218084 kb
Host smart-69d782f9-f0ca-4576-b776-4758a4b1c8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237319852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1237319852
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.2555565583
Short name T156
Test name
Test status
Simulation time 210782061 ps
CPU time 0.89 seconds
Started Jun 02 12:44:31 PM PDT 24
Finished Jun 02 12:44:32 PM PDT 24
Peak memory 200620 kb
Host smart-6491ccf2-bfd8-4375-86b2-c32a46ccd328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555565583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2555565583
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.869905479
Short name T466
Test name
Test status
Simulation time 1736326858 ps
CPU time 6.82 seconds
Started Jun 02 12:44:38 PM PDT 24
Finished Jun 02 12:44:45 PM PDT 24
Peak memory 200992 kb
Host smart-e5dd0151-c03c-4d23-ac87-8d296a1369cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869905479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.869905479
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.624444863
Short name T1
Test name
Test status
Simulation time 99749652 ps
CPU time 0.97 seconds
Started Jun 02 12:44:47 PM PDT 24
Finished Jun 02 12:44:48 PM PDT 24
Peak memory 200764 kb
Host smart-5b8326cf-6313-4128-b8c5-316d04365195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624444863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.624444863
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3396318279
Short name T227
Test name
Test status
Simulation time 191749925 ps
CPU time 1.35 seconds
Started Jun 02 12:44:31 PM PDT 24
Finished Jun 02 12:44:34 PM PDT 24
Peak memory 200996 kb
Host smart-c6447d03-7021-4a4f-9e26-a87941c61d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396318279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3396318279
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.1238524755
Short name T216
Test name
Test status
Simulation time 2042462482 ps
CPU time 7.06 seconds
Started Jun 02 12:44:36 PM PDT 24
Finished Jun 02 12:44:44 PM PDT 24
Peak memory 200972 kb
Host smart-c28f89b3-ca19-4734-8c8a-f3e4f32d61c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238524755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1238524755
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2299992777
Short name T131
Test name
Test status
Simulation time 334567073 ps
CPU time 2.25 seconds
Started Jun 02 12:44:32 PM PDT 24
Finished Jun 02 12:44:35 PM PDT 24
Peak memory 200776 kb
Host smart-8837e278-b624-4e31-aef2-ada80ccde4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299992777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2299992777
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.96787798
Short name T304
Test name
Test status
Simulation time 116781016 ps
CPU time 0.98 seconds
Started Jun 02 12:44:50 PM PDT 24
Finished Jun 02 12:44:52 PM PDT 24
Peak memory 200816 kb
Host smart-4c9327e9-6957-4493-b8bc-e76f897bae71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96787798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.96787798
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.85573986
Short name T123
Test name
Test status
Simulation time 81569045 ps
CPU time 0.85 seconds
Started Jun 02 12:44:34 PM PDT 24
Finished Jun 02 12:44:36 PM PDT 24
Peak memory 200592 kb
Host smart-e7653fba-a9de-4351-aae3-60a1093f1c79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85573986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.85573986
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3350549318
Short name T340
Test name
Test status
Simulation time 1226544732 ps
CPU time 5.52 seconds
Started Jun 02 12:44:34 PM PDT 24
Finished Jun 02 12:44:41 PM PDT 24
Peak memory 218448 kb
Host smart-62657d4c-2900-41c9-bb7b-f1f3e9648f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350549318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3350549318
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.995413922
Short name T147
Test name
Test status
Simulation time 244487027 ps
CPU time 1.09 seconds
Started Jun 02 12:44:29 PM PDT 24
Finished Jun 02 12:44:31 PM PDT 24
Peak memory 218088 kb
Host smart-5cfe0a4a-44ef-4137-bebd-b6b15af2b8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995413922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.995413922
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.799116215
Short name T21
Test name
Test status
Simulation time 227362611 ps
CPU time 0.98 seconds
Started Jun 02 12:44:41 PM PDT 24
Finished Jun 02 12:44:43 PM PDT 24
Peak memory 200800 kb
Host smart-0a2a3cd2-d949-4bd4-8c14-d627658d7029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799116215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.799116215
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.4248387202
Short name T82
Test name
Test status
Simulation time 1530791846 ps
CPU time 5.79 seconds
Started Jun 02 12:44:58 PM PDT 24
Finished Jun 02 12:45:05 PM PDT 24
Peak memory 200884 kb
Host smart-68b86c19-6ec7-41f0-8992-8203c95b32b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248387202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.4248387202
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1247443346
Short name T508
Test name
Test status
Simulation time 150820255 ps
CPU time 1.1 seconds
Started Jun 02 12:44:40 PM PDT 24
Finished Jun 02 12:44:42 PM PDT 24
Peak memory 200768 kb
Host smart-a0c3b8a5-33bb-426e-84be-c7529e787d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247443346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1247443346
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3824431906
Short name T249
Test name
Test status
Simulation time 262031987 ps
CPU time 1.5 seconds
Started Jun 02 12:44:44 PM PDT 24
Finished Jun 02 12:44:47 PM PDT 24
Peak memory 200984 kb
Host smart-a17d7e0b-e43e-4b64-8ab2-7250486ed999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824431906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3824431906
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.2132250784
Short name T93
Test name
Test status
Simulation time 11477331637 ps
CPU time 39.96 seconds
Started Jun 02 12:44:38 PM PDT 24
Finished Jun 02 12:45:18 PM PDT 24
Peak memory 201120 kb
Host smart-28acb13f-4eff-4a03-907a-13e5c6bab2af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132250784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2132250784
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1175403464
Short name T50
Test name
Test status
Simulation time 256334466 ps
CPU time 1.9 seconds
Started Jun 02 12:44:58 PM PDT 24
Finished Jun 02 12:45:01 PM PDT 24
Peak memory 200720 kb
Host smart-90a2cc7e-641d-4285-9129-e83492f78afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175403464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1175403464
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3242805325
Short name T401
Test name
Test status
Simulation time 162526424 ps
CPU time 1.12 seconds
Started Jun 02 12:44:32 PM PDT 24
Finished Jun 02 12:44:38 PM PDT 24
Peak memory 200792 kb
Host smart-e5c270e2-4d90-4ed9-bf50-6ba7c8fdd337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242805325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3242805325
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.970412878
Short name T165
Test name
Test status
Simulation time 69532456 ps
CPU time 0.81 seconds
Started Jun 02 12:44:33 PM PDT 24
Finished Jun 02 12:44:35 PM PDT 24
Peak memory 200592 kb
Host smart-de3cd391-1424-47e2-b5bc-d2b372d6d366
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970412878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.970412878
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2620562652
Short name T284
Test name
Test status
Simulation time 2351386849 ps
CPU time 8.84 seconds
Started Jun 02 12:44:41 PM PDT 24
Finished Jun 02 12:44:51 PM PDT 24
Peak memory 222548 kb
Host smart-772005b8-bcad-4c5a-945f-f6cfe608f34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620562652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2620562652
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1800955520
Short name T353
Test name
Test status
Simulation time 246074147 ps
CPU time 1.08 seconds
Started Jun 02 12:44:56 PM PDT 24
Finished Jun 02 12:44:58 PM PDT 24
Peak memory 218000 kb
Host smart-23a506c4-f8fe-4d6b-8ade-40fdd8d5699b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800955520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1800955520
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1995196236
Short name T487
Test name
Test status
Simulation time 111028309 ps
CPU time 0.78 seconds
Started Jun 02 12:44:34 PM PDT 24
Finished Jun 02 12:44:36 PM PDT 24
Peak memory 200588 kb
Host smart-6a635447-641b-4884-9843-394916a9e879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995196236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1995196236
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1361318227
Short name T470
Test name
Test status
Simulation time 1333834481 ps
CPU time 5.46 seconds
Started Jun 02 12:44:38 PM PDT 24
Finished Jun 02 12:44:44 PM PDT 24
Peak memory 201004 kb
Host smart-96f42d3d-4adb-48f3-ab9e-9c9f2f867d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361318227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1361318227
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1972729220
Short name T142
Test name
Test status
Simulation time 144375037 ps
CPU time 1.12 seconds
Started Jun 02 12:44:30 PM PDT 24
Finished Jun 02 12:44:31 PM PDT 24
Peak memory 200800 kb
Host smart-ade56512-72e1-46a5-bc0e-ab778c24edbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972729220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1972729220
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.973986663
Short name T505
Test name
Test status
Simulation time 255981677 ps
CPU time 1.6 seconds
Started Jun 02 12:44:39 PM PDT 24
Finished Jun 02 12:44:41 PM PDT 24
Peak memory 200960 kb
Host smart-99e9cecd-fed7-4ca3-9b21-ed718aca9604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973986663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.973986663
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.829213738
Short name T84
Test name
Test status
Simulation time 1444586211 ps
CPU time 5.14 seconds
Started Jun 02 12:44:57 PM PDT 24
Finished Jun 02 12:45:03 PM PDT 24
Peak memory 200940 kb
Host smart-dce73094-c071-419c-bb1a-371e2f413e58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829213738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.829213738
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3385602580
Short name T51
Test name
Test status
Simulation time 361706177 ps
CPU time 2.35 seconds
Started Jun 02 12:44:40 PM PDT 24
Finished Jun 02 12:44:43 PM PDT 24
Peak memory 200744 kb
Host smart-224364db-253c-4c67-b37e-5c1700c9984b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385602580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3385602580
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3448812624
Short name T130
Test name
Test status
Simulation time 140125127 ps
CPU time 1.09 seconds
Started Jun 02 12:44:39 PM PDT 24
Finished Jun 02 12:44:41 PM PDT 24
Peak memory 200824 kb
Host smart-4fc91eb2-c99c-46bf-9a58-afc260449797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448812624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3448812624
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2733697676
Short name T240
Test name
Test status
Simulation time 80453161 ps
CPU time 0.8 seconds
Started Jun 02 12:44:48 PM PDT 24
Finished Jun 02 12:44:50 PM PDT 24
Peak memory 200636 kb
Host smart-04a60b15-8a21-4b81-8477-e45fda60e806
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733697676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2733697676
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.660585834
Short name T45
Test name
Test status
Simulation time 1232287672 ps
CPU time 5.75 seconds
Started Jun 02 12:44:39 PM PDT 24
Finished Jun 02 12:44:45 PM PDT 24
Peak memory 222496 kb
Host smart-32b56834-973a-41ab-927a-5851551c910a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660585834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.660585834
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3167787450
Short name T226
Test name
Test status
Simulation time 243866311 ps
CPU time 1.11 seconds
Started Jun 02 12:44:39 PM PDT 24
Finished Jun 02 12:44:41 PM PDT 24
Peak memory 218120 kb
Host smart-688b33bf-ff23-4b95-af5d-7d7c8c1a5144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167787450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3167787450
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.4217908524
Short name T287
Test name
Test status
Simulation time 142149281 ps
CPU time 0.78 seconds
Started Jun 02 12:44:32 PM PDT 24
Finished Jun 02 12:44:34 PM PDT 24
Peak memory 200604 kb
Host smart-d2d2c793-75dd-430f-82ee-afa5da927426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217908524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.4217908524
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.982092950
Short name T90
Test name
Test status
Simulation time 1518090748 ps
CPU time 6.51 seconds
Started Jun 02 12:44:32 PM PDT 24
Finished Jun 02 12:44:40 PM PDT 24
Peak memory 200996 kb
Host smart-db746b66-5452-47e6-8505-094031be5759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982092950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.982092950
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.249759157
Short name T125
Test name
Test status
Simulation time 186569626 ps
CPU time 1.18 seconds
Started Jun 02 12:44:38 PM PDT 24
Finished Jun 02 12:44:40 PM PDT 24
Peak memory 200840 kb
Host smart-98dd6dd0-1da0-449d-8da1-301abd4ecdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249759157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.249759157
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.16356742
Short name T380
Test name
Test status
Simulation time 127190198 ps
CPU time 1.23 seconds
Started Jun 02 12:44:31 PM PDT 24
Finished Jun 02 12:44:34 PM PDT 24
Peak memory 201016 kb
Host smart-5cce9714-2513-43ae-a194-ae7ae80b0638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16356742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.16356742
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.2327753837
Short name T382
Test name
Test status
Simulation time 9171429815 ps
CPU time 35.8 seconds
Started Jun 02 12:44:39 PM PDT 24
Finished Jun 02 12:45:15 PM PDT 24
Peak memory 201180 kb
Host smart-7e451c9d-3050-4dc5-9f8e-fb989085e656
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327753837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2327753837
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1014389
Short name T159
Test name
Test status
Simulation time 258948140 ps
CPU time 1.82 seconds
Started Jun 02 12:44:37 PM PDT 24
Finished Jun 02 12:44:39 PM PDT 24
Peak memory 200772 kb
Host smart-f82aeae8-aa47-4464-84e5-1d04a49bdb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1014389
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1916600137
Short name T133
Test name
Test status
Simulation time 127662514 ps
CPU time 0.97 seconds
Started Jun 02 12:44:33 PM PDT 24
Finished Jun 02 12:44:35 PM PDT 24
Peak memory 200796 kb
Host smart-ebc2dd7c-c202-40ce-b8cf-f95e38778711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916600137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1916600137
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1944206095
Short name T500
Test name
Test status
Simulation time 79749625 ps
CPU time 0.82 seconds
Started Jun 02 12:44:59 PM PDT 24
Finished Jun 02 12:45:01 PM PDT 24
Peak memory 200620 kb
Host smart-f6b131ef-b945-4c22-a2d6-4da42c453f1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944206095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1944206095
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3508405196
Short name T8
Test name
Test status
Simulation time 1889258575 ps
CPU time 6.9 seconds
Started Jun 02 12:44:51 PM PDT 24
Finished Jun 02 12:44:58 PM PDT 24
Peak memory 222496 kb
Host smart-17548ed9-9410-4643-b99b-84979373c5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508405196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3508405196
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.115159095
Short name T288
Test name
Test status
Simulation time 244069658 ps
CPU time 1.06 seconds
Started Jun 02 12:44:41 PM PDT 24
Finished Jun 02 12:44:43 PM PDT 24
Peak memory 218924 kb
Host smart-83e23c4f-6bf6-4ad0-a7cb-034b266e7fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115159095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.115159095
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3498580580
Short name T19
Test name
Test status
Simulation time 187288184 ps
CPU time 0.85 seconds
Started Jun 02 12:44:50 PM PDT 24
Finished Jun 02 12:44:52 PM PDT 24
Peak memory 200560 kb
Host smart-7fdf7386-a991-4e9a-a43c-44e7764c4973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498580580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3498580580
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3807914493
Short name T415
Test name
Test status
Simulation time 1455658471 ps
CPU time 5.54 seconds
Started Jun 02 12:44:52 PM PDT 24
Finished Jun 02 12:44:58 PM PDT 24
Peak memory 201004 kb
Host smart-38710dc0-1a0c-4ad4-a96b-6604b28d0028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807914493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3807914493
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3534365001
Short name T285
Test name
Test status
Simulation time 113151728 ps
CPU time 0.98 seconds
Started Jun 02 12:44:50 PM PDT 24
Finished Jun 02 12:44:51 PM PDT 24
Peak memory 200816 kb
Host smart-e0848980-718e-4bf0-bf50-e2a17675811d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534365001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3534365001
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1829780334
Short name T162
Test name
Test status
Simulation time 116154369 ps
CPU time 1.27 seconds
Started Jun 02 12:44:40 PM PDT 24
Finished Jun 02 12:44:42 PM PDT 24
Peak memory 200980 kb
Host smart-1a8cbaac-91ee-4b76-89d2-c9a3123167c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829780334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1829780334
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2185169196
Short name T83
Test name
Test status
Simulation time 1891760106 ps
CPU time 8.29 seconds
Started Jun 02 12:44:41 PM PDT 24
Finished Jun 02 12:44:50 PM PDT 24
Peak memory 201024 kb
Host smart-433431cf-d155-4f30-9a0b-56971af8719f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185169196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2185169196
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.2526964351
Short name T263
Test name
Test status
Simulation time 494619808 ps
CPU time 2.6 seconds
Started Jun 02 12:44:41 PM PDT 24
Finished Jun 02 12:44:44 PM PDT 24
Peak memory 200748 kb
Host smart-b1c9a970-56ff-4d72-a4e1-e6171a151277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526964351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2526964351
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.3616600237
Short name T154
Test name
Test status
Simulation time 140863287 ps
CPU time 1.18 seconds
Started Jun 02 12:44:51 PM PDT 24
Finished Jun 02 12:44:53 PM PDT 24
Peak memory 200736 kb
Host smart-12568d2d-c6cb-446d-8646-fb0536aff39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616600237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3616600237
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.2608466323
Short name T310
Test name
Test status
Simulation time 66288319 ps
CPU time 0.74 seconds
Started Jun 02 12:44:47 PM PDT 24
Finished Jun 02 12:44:48 PM PDT 24
Peak memory 200588 kb
Host smart-8043a6c7-1a92-49e2-ba2b-2f3bdf8c3cbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608466323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2608466323
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2673044567
Short name T33
Test name
Test status
Simulation time 2354545818 ps
CPU time 8.53 seconds
Started Jun 02 12:45:02 PM PDT 24
Finished Jun 02 12:45:12 PM PDT 24
Peak memory 218560 kb
Host smart-467dfc0f-3d5a-4630-9db8-1d24f32f8132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673044567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2673044567
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.645929155
Short name T166
Test name
Test status
Simulation time 244575194 ps
CPU time 1.11 seconds
Started Jun 02 12:44:49 PM PDT 24
Finished Jun 02 12:44:51 PM PDT 24
Peak memory 217956 kb
Host smart-a1f1d94f-fbcb-4920-9094-6bed25d683df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645929155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.645929155
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1514250437
Short name T309
Test name
Test status
Simulation time 125118027 ps
CPU time 0.78 seconds
Started Jun 02 12:44:45 PM PDT 24
Finished Jun 02 12:44:46 PM PDT 24
Peak memory 200624 kb
Host smart-93a5f181-6662-4f2d-ba23-02e6fb15117c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514250437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1514250437
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.928525102
Short name T335
Test name
Test status
Simulation time 1485879564 ps
CPU time 6 seconds
Started Jun 02 12:44:37 PM PDT 24
Finished Jun 02 12:44:43 PM PDT 24
Peak memory 200952 kb
Host smart-3bc476b4-f9f6-4a74-8522-02c2d5ff8c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928525102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.928525102
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3943084086
Short name T344
Test name
Test status
Simulation time 143907508 ps
CPU time 1.17 seconds
Started Jun 02 12:45:05 PM PDT 24
Finished Jun 02 12:45:08 PM PDT 24
Peak memory 200828 kb
Host smart-ff5ea389-82e8-4c9a-9f83-5fc546a61509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943084086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3943084086
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.4124790123
Short name T56
Test name
Test status
Simulation time 250991272 ps
CPU time 1.61 seconds
Started Jun 02 12:44:46 PM PDT 24
Finished Jun 02 12:44:48 PM PDT 24
Peak memory 201016 kb
Host smart-ac081bca-2190-4c7e-bfaf-40b7dcfff192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124790123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.4124790123
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1043193638
Short name T433
Test name
Test status
Simulation time 9477854827 ps
CPU time 32.37 seconds
Started Jun 02 12:44:39 PM PDT 24
Finished Jun 02 12:45:12 PM PDT 24
Peak memory 209360 kb
Host smart-63e448cc-204b-4def-8dc4-c35fea598fca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043193638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1043193638
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.2013625526
Short name T112
Test name
Test status
Simulation time 525784970 ps
CPU time 2.78 seconds
Started Jun 02 12:44:50 PM PDT 24
Finished Jun 02 12:44:53 PM PDT 24
Peak memory 200736 kb
Host smart-2a724f92-53da-4ea2-b828-d9e0a2713f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013625526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2013625526
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.345944228
Short name T516
Test name
Test status
Simulation time 186650946 ps
CPU time 1.21 seconds
Started Jun 02 12:44:47 PM PDT 24
Finished Jun 02 12:44:49 PM PDT 24
Peak memory 200804 kb
Host smart-8197a74d-5a82-4b42-a5c7-ee7fe6366abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345944228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.345944228
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2287467655
Short name T480
Test name
Test status
Simulation time 173873689 ps
CPU time 0.96 seconds
Started Jun 02 12:44:50 PM PDT 24
Finished Jun 02 12:44:52 PM PDT 24
Peak memory 200624 kb
Host smart-ff2c1d95-d76c-450f-ab66-ece88cc4a35e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287467655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2287467655
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1270483246
Short name T502
Test name
Test status
Simulation time 2164375819 ps
CPU time 8.24 seconds
Started Jun 02 12:44:44 PM PDT 24
Finished Jun 02 12:44:53 PM PDT 24
Peak memory 218648 kb
Host smart-e1af9b86-7cc4-4dda-a1b0-84b4c115002d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270483246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1270483246
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2423765816
Short name T316
Test name
Test status
Simulation time 244610336 ps
CPU time 1.07 seconds
Started Jun 02 12:44:47 PM PDT 24
Finished Jun 02 12:44:49 PM PDT 24
Peak memory 218164 kb
Host smart-be3678f9-bd09-48c4-828d-193ee750d55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423765816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2423765816
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.1891576121
Short name T383
Test name
Test status
Simulation time 98244603 ps
CPU time 0.82 seconds
Started Jun 02 12:44:44 PM PDT 24
Finished Jun 02 12:44:45 PM PDT 24
Peak memory 200608 kb
Host smart-70a23ac7-09f5-43f9-89d0-5635d7022155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891576121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1891576121
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2707023451
Short name T369
Test name
Test status
Simulation time 1434120469 ps
CPU time 6.01 seconds
Started Jun 02 12:44:39 PM PDT 24
Finished Jun 02 12:44:46 PM PDT 24
Peak memory 201260 kb
Host smart-46053aef-915c-4485-9944-ed0502102b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707023451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2707023451
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.48848960
Short name T409
Test name
Test status
Simulation time 92243193 ps
CPU time 0.98 seconds
Started Jun 02 12:44:44 PM PDT 24
Finished Jun 02 12:44:45 PM PDT 24
Peak memory 200808 kb
Host smart-94674af8-2757-49c7-9b7b-3b7459b2817d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48848960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.48848960
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.4242678426
Short name T356
Test name
Test status
Simulation time 187745071 ps
CPU time 1.39 seconds
Started Jun 02 12:44:45 PM PDT 24
Finished Jun 02 12:44:47 PM PDT 24
Peak memory 200944 kb
Host smart-3b6839a6-b19b-4eee-bf5c-161aff8de378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242678426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.4242678426
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.95732438
Short name T302
Test name
Test status
Simulation time 1050754997 ps
CPU time 4.12 seconds
Started Jun 02 12:44:45 PM PDT 24
Finished Jun 02 12:44:50 PM PDT 24
Peak memory 200796 kb
Host smart-32509754-5aa2-450b-a30d-542455982e31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95732438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.95732438
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3655482421
Short name T190
Test name
Test status
Simulation time 137693990 ps
CPU time 1.63 seconds
Started Jun 02 12:44:47 PM PDT 24
Finished Jun 02 12:44:49 PM PDT 24
Peak memory 200772 kb
Host smart-a5d52258-a937-458a-b6bc-ffc0e1f63a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655482421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3655482421
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.26632693
Short name T268
Test name
Test status
Simulation time 218162784 ps
CPU time 1.29 seconds
Started Jun 02 12:44:45 PM PDT 24
Finished Jun 02 12:44:47 PM PDT 24
Peak memory 200756 kb
Host smart-7c67f21b-3d0e-4c18-8c46-09b55895a093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26632693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.26632693
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1869144784
Short name T176
Test name
Test status
Simulation time 117237745 ps
CPU time 0.9 seconds
Started Jun 02 12:45:03 PM PDT 24
Finished Jun 02 12:45:05 PM PDT 24
Peak memory 200544 kb
Host smart-0a92e631-1704-4a1b-bc56-3440a1ffab8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869144784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1869144784
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3914635905
Short name T455
Test name
Test status
Simulation time 2347594534 ps
CPU time 9.31 seconds
Started Jun 02 12:44:44 PM PDT 24
Finished Jun 02 12:44:54 PM PDT 24
Peak memory 222344 kb
Host smart-d977a424-8429-45b8-b8e0-75322666c7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914635905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3914635905
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.277683271
Short name T138
Test name
Test status
Simulation time 244693886 ps
CPU time 1.06 seconds
Started Jun 02 12:44:43 PM PDT 24
Finished Jun 02 12:44:44 PM PDT 24
Peak memory 218108 kb
Host smart-efe6bb7d-92cb-43fa-9e9c-07e99dfae3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277683271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.277683271
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3711802338
Short name T16
Test name
Test status
Simulation time 119659601 ps
CPU time 0.84 seconds
Started Jun 02 12:44:38 PM PDT 24
Finished Jun 02 12:44:40 PM PDT 24
Peak memory 200596 kb
Host smart-888621b1-8bb2-4df2-8aab-97e52c0184b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711802338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3711802338
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1923749182
Short name T151
Test name
Test status
Simulation time 1233916242 ps
CPU time 5.62 seconds
Started Jun 02 12:44:40 PM PDT 24
Finished Jun 02 12:44:46 PM PDT 24
Peak memory 200984 kb
Host smart-0d28a498-345f-41d2-bc16-066fb9f04235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923749182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1923749182
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.942925439
Short name T25
Test name
Test status
Simulation time 96995432 ps
CPU time 0.94 seconds
Started Jun 02 12:44:49 PM PDT 24
Finished Jun 02 12:44:51 PM PDT 24
Peak memory 200820 kb
Host smart-6d759e16-708e-4405-802d-7e9035eda5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942925439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.942925439
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.4043721753
Short name T113
Test name
Test status
Simulation time 253162809 ps
CPU time 1.55 seconds
Started Jun 02 12:44:56 PM PDT 24
Finished Jun 02 12:44:58 PM PDT 24
Peak memory 201012 kb
Host smart-f0320625-1f52-4ba4-887a-28ed718261e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043721753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.4043721753
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1915712469
Short name T294
Test name
Test status
Simulation time 3547597007 ps
CPU time 12.79 seconds
Started Jun 02 12:44:45 PM PDT 24
Finished Jun 02 12:44:59 PM PDT 24
Peak memory 201084 kb
Host smart-a4906749-2829-4b98-8e63-b2b47319a8c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915712469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1915712469
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3611107601
Short name T173
Test name
Test status
Simulation time 336122451 ps
CPU time 2.18 seconds
Started Jun 02 12:44:43 PM PDT 24
Finished Jun 02 12:44:46 PM PDT 24
Peak memory 200784 kb
Host smart-e2986e02-9881-4ad3-9771-0d910082aca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611107601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3611107601
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.4195000842
Short name T153
Test name
Test status
Simulation time 113902683 ps
CPU time 1.07 seconds
Started Jun 02 12:44:45 PM PDT 24
Finished Jun 02 12:44:47 PM PDT 24
Peak memory 200636 kb
Host smart-167493c6-9861-4359-8abb-6934ef6601e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195000842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.4195000842
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.4069966304
Short name T188
Test name
Test status
Simulation time 66994910 ps
CPU time 0.78 seconds
Started Jun 02 12:44:58 PM PDT 24
Finished Jun 02 12:44:59 PM PDT 24
Peak memory 200584 kb
Host smart-ab14bb7d-63f0-42cf-8762-dcd2c38b3764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069966304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.4069966304
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1697480472
Short name T513
Test name
Test status
Simulation time 1228672820 ps
CPU time 5.69 seconds
Started Jun 02 12:44:58 PM PDT 24
Finished Jun 02 12:45:04 PM PDT 24
Peak memory 221764 kb
Host smart-31137ebc-e392-4625-9f67-c693ddf5a4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697480472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1697480472
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2712121581
Short name T5
Test name
Test status
Simulation time 244034993 ps
CPU time 1.06 seconds
Started Jun 02 12:44:46 PM PDT 24
Finished Jun 02 12:44:48 PM PDT 24
Peak memory 217976 kb
Host smart-d87c97e1-2e3e-434a-9183-9e6254a65a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712121581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2712121581
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3027672434
Short name T519
Test name
Test status
Simulation time 181486976 ps
CPU time 0.85 seconds
Started Jun 02 12:44:41 PM PDT 24
Finished Jun 02 12:44:42 PM PDT 24
Peak memory 200628 kb
Host smart-149c0908-45a0-4ed9-a6f5-e1a4d69b0ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027672434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3027672434
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3521123359
Short name T186
Test name
Test status
Simulation time 1267585312 ps
CPU time 5.43 seconds
Started Jun 02 12:44:43 PM PDT 24
Finished Jun 02 12:44:49 PM PDT 24
Peak memory 201052 kb
Host smart-9620b7cf-9241-4c72-871e-98c4c92887cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521123359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3521123359
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1426991275
Short name T121
Test name
Test status
Simulation time 104993388 ps
CPU time 1.03 seconds
Started Jun 02 12:44:50 PM PDT 24
Finished Jun 02 12:44:52 PM PDT 24
Peak memory 200824 kb
Host smart-50a1ad41-3e66-44c0-9158-fe687f85913b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426991275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1426991275
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3081764284
Short name T219
Test name
Test status
Simulation time 113958096 ps
CPU time 1.24 seconds
Started Jun 02 12:44:38 PM PDT 24
Finished Jun 02 12:44:40 PM PDT 24
Peak memory 201028 kb
Host smart-54000d95-d5a1-4c38-a571-f41e73acd519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081764284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3081764284
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3905193322
Short name T158
Test name
Test status
Simulation time 4515782923 ps
CPU time 19.58 seconds
Started Jun 02 12:44:39 PM PDT 24
Finished Jun 02 12:44:59 PM PDT 24
Peak memory 201144 kb
Host smart-3ca0c25d-2c89-47d2-a531-76694a88a0cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905193322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3905193322
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.1056853355
Short name T448
Test name
Test status
Simulation time 347326112 ps
CPU time 1.94 seconds
Started Jun 02 12:44:41 PM PDT 24
Finished Jun 02 12:44:44 PM PDT 24
Peak memory 200796 kb
Host smart-4cb0f705-6115-46d6-9e89-342273e0cd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056853355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1056853355
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.225248917
Short name T442
Test name
Test status
Simulation time 226239828 ps
CPU time 1.39 seconds
Started Jun 02 12:44:46 PM PDT 24
Finished Jun 02 12:44:48 PM PDT 24
Peak memory 201004 kb
Host smart-9220b809-2a7e-4347-a950-5a6cb24c2c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225248917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.225248917
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.618605959
Short name T343
Test name
Test status
Simulation time 84951409 ps
CPU time 0.82 seconds
Started Jun 02 12:44:57 PM PDT 24
Finished Jun 02 12:44:58 PM PDT 24
Peak memory 200536 kb
Host smart-2b70a573-b1e0-499d-a357-3cef7510a528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618605959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.618605959
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.969996068
Short name T326
Test name
Test status
Simulation time 2361916071 ps
CPU time 8.63 seconds
Started Jun 02 12:44:40 PM PDT 24
Finished Jun 02 12:44:49 PM PDT 24
Peak memory 222364 kb
Host smart-8209634b-d86c-48f3-a737-321bdd652ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969996068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.969996068
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3170107305
Short name T301
Test name
Test status
Simulation time 245616646 ps
CPU time 1.11 seconds
Started Jun 02 12:44:43 PM PDT 24
Finished Jun 02 12:44:45 PM PDT 24
Peak memory 217984 kb
Host smart-410d5bf2-1244-4bdb-be37-773d9a728b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170107305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3170107305
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2459905986
Short name T258
Test name
Test status
Simulation time 117208032 ps
CPU time 0.83 seconds
Started Jun 02 12:44:58 PM PDT 24
Finished Jun 02 12:45:00 PM PDT 24
Peak memory 200628 kb
Host smart-59655676-84d7-4b2d-831c-bd373ee4b006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459905986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2459905986
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.953407554
Short name T452
Test name
Test status
Simulation time 987116184 ps
CPU time 5.04 seconds
Started Jun 02 12:45:08 PM PDT 24
Finished Jun 02 12:45:14 PM PDT 24
Peak memory 201020 kb
Host smart-24a6e35c-5ba9-4b3e-b82d-6214aad3024d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953407554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.953407554
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.455131618
Short name T155
Test name
Test status
Simulation time 94786285 ps
CPU time 0.96 seconds
Started Jun 02 12:45:01 PM PDT 24
Finished Jun 02 12:45:03 PM PDT 24
Peak memory 200856 kb
Host smart-7345c6f8-ccda-41e4-a013-a72ad3e2b0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455131618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.455131618
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.890592728
Short name T320
Test name
Test status
Simulation time 115743663 ps
CPU time 1.21 seconds
Started Jun 02 12:44:37 PM PDT 24
Finished Jun 02 12:44:39 PM PDT 24
Peak memory 201012 kb
Host smart-8ed51514-2022-496a-8dea-b20f161edc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890592728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.890592728
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3824226535
Short name T375
Test name
Test status
Simulation time 3870443738 ps
CPU time 14.05 seconds
Started Jun 02 12:44:50 PM PDT 24
Finished Jun 02 12:45:05 PM PDT 24
Peak memory 209356 kb
Host smart-d406cb53-2c39-4d89-a5c6-e1cfa1bf9481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824226535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3824226535
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3765772835
Short name T322
Test name
Test status
Simulation time 373039327 ps
CPU time 2.66 seconds
Started Jun 02 12:44:48 PM PDT 24
Finished Jun 02 12:44:51 PM PDT 24
Peak memory 200764 kb
Host smart-eca9e476-cdd2-4b12-a1b0-77f123a3fb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765772835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3765772835
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.626347328
Short name T157
Test name
Test status
Simulation time 83206258 ps
CPU time 0.81 seconds
Started Jun 02 12:44:39 PM PDT 24
Finished Jun 02 12:44:40 PM PDT 24
Peak memory 200808 kb
Host smart-e136a9c0-34fe-44e0-855e-7d0073f4a5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626347328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.626347328
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3884523809
Short name T241
Test name
Test status
Simulation time 56365070 ps
CPU time 0.74 seconds
Started Jun 02 12:43:45 PM PDT 24
Finished Jun 02 12:43:46 PM PDT 24
Peak memory 200608 kb
Host smart-f07bf0e6-9b13-4d4e-b7ec-aa347c6a37ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884523809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3884523809
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2583504084
Short name T37
Test name
Test status
Simulation time 2348008786 ps
CPU time 8.5 seconds
Started Jun 02 12:43:50 PM PDT 24
Finished Jun 02 12:43:59 PM PDT 24
Peak memory 217724 kb
Host smart-67abc300-b830-4ec2-8c68-9eb82e11f9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583504084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2583504084
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1952623689
Short name T279
Test name
Test status
Simulation time 245028165 ps
CPU time 1.06 seconds
Started Jun 02 12:43:44 PM PDT 24
Finished Jun 02 12:43:45 PM PDT 24
Peak memory 218068 kb
Host smart-57be9e24-8740-4036-a6c4-d0ec3e4a582b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952623689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1952623689
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.494090393
Short name T210
Test name
Test status
Simulation time 176570432 ps
CPU time 0.87 seconds
Started Jun 02 12:43:47 PM PDT 24
Finished Jun 02 12:43:48 PM PDT 24
Peak memory 200616 kb
Host smart-1c924b15-be30-43fa-b11c-eb711d915667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494090393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.494090393
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.4053976989
Short name T111
Test name
Test status
Simulation time 1791125755 ps
CPU time 7.01 seconds
Started Jun 02 12:43:45 PM PDT 24
Finished Jun 02 12:43:52 PM PDT 24
Peak memory 200852 kb
Host smart-edb44557-1a62-42b2-bb7e-83bc10427f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053976989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.4053976989
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3030131105
Short name T183
Test name
Test status
Simulation time 165783825 ps
CPU time 1.15 seconds
Started Jun 02 12:43:43 PM PDT 24
Finished Jun 02 12:43:44 PM PDT 24
Peak memory 200824 kb
Host smart-a4c80287-ac55-4ddc-a582-c56b037b204f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030131105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3030131105
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.131631991
Short name T412
Test name
Test status
Simulation time 130786315 ps
CPU time 1.28 seconds
Started Jun 02 12:43:47 PM PDT 24
Finished Jun 02 12:43:49 PM PDT 24
Peak memory 200960 kb
Host smart-8b4c5562-5e81-483a-b1c4-b1695a1093f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131631991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.131631991
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3864946920
Short name T209
Test name
Test status
Simulation time 5720247920 ps
CPU time 27.43 seconds
Started Jun 02 12:43:44 PM PDT 24
Finished Jun 02 12:44:12 PM PDT 24
Peak memory 201172 kb
Host smart-c376da14-2fe5-4bfd-9d0e-26d762975218
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864946920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3864946920
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.2184070150
Short name T447
Test name
Test status
Simulation time 111442822 ps
CPU time 1.52 seconds
Started Jun 02 12:43:45 PM PDT 24
Finished Jun 02 12:43:47 PM PDT 24
Peak memory 200684 kb
Host smart-fb19d8d9-a1bd-415c-a635-0da0b1ab9efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184070150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.2184070150
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.3314746318
Short name T349
Test name
Test status
Simulation time 264244306 ps
CPU time 1.46 seconds
Started Jun 02 12:43:44 PM PDT 24
Finished Jun 02 12:43:46 PM PDT 24
Peak memory 200840 kb
Host smart-f0be63dd-7ef4-47b4-8e68-dd99a5b8aca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314746318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3314746318
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3860997245
Short name T61
Test name
Test status
Simulation time 76789827 ps
CPU time 0.85 seconds
Started Jun 02 12:43:45 PM PDT 24
Finished Jun 02 12:43:47 PM PDT 24
Peak memory 200672 kb
Host smart-429f2a9e-b33d-4e95-9b90-dd500cfbf834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860997245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3860997245
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3975844004
Short name T393
Test name
Test status
Simulation time 1233205996 ps
CPU time 6.05 seconds
Started Jun 02 12:43:48 PM PDT 24
Finished Jun 02 12:43:54 PM PDT 24
Peak memory 217292 kb
Host smart-11f3fa27-a3e6-49d4-b31a-206dad9a8aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975844004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3975844004
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2500697368
Short name T330
Test name
Test status
Simulation time 244112367 ps
CPU time 1.09 seconds
Started Jun 02 12:43:46 PM PDT 24
Finished Jun 02 12:43:48 PM PDT 24
Peak memory 217992 kb
Host smart-2a864be9-73aa-44b8-98ed-bf8a7c4ca9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500697368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2500697368
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3174784150
Short name T332
Test name
Test status
Simulation time 210148720 ps
CPU time 0.93 seconds
Started Jun 02 12:43:47 PM PDT 24
Finished Jun 02 12:43:49 PM PDT 24
Peak memory 200572 kb
Host smart-e4268672-5601-4f52-b33b-2f2a037f147c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174784150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3174784150
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2523261488
Short name T262
Test name
Test status
Simulation time 1436790528 ps
CPU time 5.19 seconds
Started Jun 02 12:43:48 PM PDT 24
Finished Jun 02 12:43:53 PM PDT 24
Peak memory 200964 kb
Host smart-e6c40438-bbfb-42e0-bd1a-5552ca9dffb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523261488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2523261488
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.855279124
Short name T233
Test name
Test status
Simulation time 156859337 ps
CPU time 1.14 seconds
Started Jun 02 12:43:49 PM PDT 24
Finished Jun 02 12:43:50 PM PDT 24
Peak memory 200788 kb
Host smart-9df59a39-ec4c-4a54-bf62-9e233948a740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855279124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.855279124
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2450266230
Short name T251
Test name
Test status
Simulation time 110151434 ps
CPU time 1.16 seconds
Started Jun 02 12:43:48 PM PDT 24
Finished Jun 02 12:43:50 PM PDT 24
Peak memory 200956 kb
Host smart-83bdc1b4-728e-48bc-9263-cceafd50ecc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450266230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2450266230
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.625245094
Short name T267
Test name
Test status
Simulation time 2063344749 ps
CPU time 7.07 seconds
Started Jun 02 12:43:50 PM PDT 24
Finished Jun 02 12:43:58 PM PDT 24
Peak memory 201028 kb
Host smart-9753381b-086c-4226-b68e-838d1f7d2972
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625245094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.625245094
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.4226380986
Short name T530
Test name
Test status
Simulation time 466074200 ps
CPU time 2.62 seconds
Started Jun 02 12:43:48 PM PDT 24
Finished Jun 02 12:43:51 PM PDT 24
Peak memory 200716 kb
Host smart-b73fe339-e027-40ab-a779-8c24b9c15dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226380986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.4226380986
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.2822225594
Short name T126
Test name
Test status
Simulation time 92532899 ps
CPU time 0.89 seconds
Started Jun 02 12:43:46 PM PDT 24
Finished Jun 02 12:43:48 PM PDT 24
Peak memory 200756 kb
Host smart-2ffdfc57-5651-4fc3-8481-4446afde499c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822225594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2822225594
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2368937683
Short name T396
Test name
Test status
Simulation time 58444071 ps
CPU time 0.81 seconds
Started Jun 02 12:43:49 PM PDT 24
Finished Jun 02 12:43:50 PM PDT 24
Peak memory 200564 kb
Host smart-4d94b9f9-3251-4369-8665-5c2b3c5011f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368937683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2368937683
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.4287933022
Short name T38
Test name
Test status
Simulation time 1224156407 ps
CPU time 5.64 seconds
Started Jun 02 12:43:49 PM PDT 24
Finished Jun 02 12:43:56 PM PDT 24
Peak memory 218412 kb
Host smart-c29a41ba-51f2-47bf-9d3a-79f359915815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287933022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.4287933022
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1407723116
Short name T352
Test name
Test status
Simulation time 244289005 ps
CPU time 1.05 seconds
Started Jun 02 12:43:50 PM PDT 24
Finished Jun 02 12:43:52 PM PDT 24
Peak memory 217992 kb
Host smart-1b22fbd7-b964-4a4c-94ed-2a2e15243f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407723116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1407723116
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.298971677
Short name T465
Test name
Test status
Simulation time 86283349 ps
CPU time 0.78 seconds
Started Jun 02 12:43:47 PM PDT 24
Finished Jun 02 12:43:48 PM PDT 24
Peak memory 200884 kb
Host smart-e5dbab74-a2b6-452c-ba35-b8758d56b571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298971677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.298971677
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.1878912810
Short name T399
Test name
Test status
Simulation time 1318038949 ps
CPU time 5.41 seconds
Started Jun 02 12:43:49 PM PDT 24
Finished Jun 02 12:43:55 PM PDT 24
Peak memory 200948 kb
Host smart-5a34026f-139c-4a71-88d4-53c091bdfb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878912810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1878912810
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.780823378
Short name T235
Test name
Test status
Simulation time 149615653 ps
CPU time 1.21 seconds
Started Jun 02 12:43:44 PM PDT 24
Finished Jun 02 12:43:46 PM PDT 24
Peak memory 200860 kb
Host smart-11994595-7ddb-4b8c-8661-4d639c780ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780823378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.780823378
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.869712618
Short name T289
Test name
Test status
Simulation time 123702839 ps
CPU time 1.22 seconds
Started Jun 02 12:43:48 PM PDT 24
Finished Jun 02 12:43:49 PM PDT 24
Peak memory 200936 kb
Host smart-3d313273-95f0-451b-a922-91fffde442c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869712618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.869712618
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2528065441
Short name T67
Test name
Test status
Simulation time 5301203685 ps
CPU time 20.85 seconds
Started Jun 02 12:43:46 PM PDT 24
Finished Jun 02 12:44:08 PM PDT 24
Peak memory 210936 kb
Host smart-85d14cf9-911e-42a9-8714-17c291984838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528065441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2528065441
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.674096716
Short name T468
Test name
Test status
Simulation time 388792156 ps
CPU time 2.03 seconds
Started Jun 02 12:43:46 PM PDT 24
Finished Jun 02 12:43:49 PM PDT 24
Peak memory 200776 kb
Host smart-2127e002-ce8f-41af-8332-3407934bc65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674096716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.674096716
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3728802041
Short name T234
Test name
Test status
Simulation time 125741502 ps
CPU time 1.07 seconds
Started Jun 02 12:43:45 PM PDT 24
Finished Jun 02 12:43:47 PM PDT 24
Peak memory 200772 kb
Host smart-9974c3a9-7c9a-449f-ab6f-a931f65c0eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728802041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3728802041
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.4123564914
Short name T473
Test name
Test status
Simulation time 62364059 ps
CPU time 0.8 seconds
Started Jun 02 12:43:58 PM PDT 24
Finished Jun 02 12:44:00 PM PDT 24
Peak memory 200608 kb
Host smart-02e9ceb9-d1cc-46dd-9990-dfbf9ae9f265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123564914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.4123564914
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.882471838
Short name T464
Test name
Test status
Simulation time 2355050607 ps
CPU time 9 seconds
Started Jun 02 12:43:44 PM PDT 24
Finished Jun 02 12:43:53 PM PDT 24
Peak memory 222620 kb
Host smart-cb135d72-7bab-495b-9ac7-1b203b22c022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882471838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.882471838
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3662242762
Short name T373
Test name
Test status
Simulation time 245615276 ps
CPU time 1.05 seconds
Started Jun 02 12:43:50 PM PDT 24
Finished Jun 02 12:43:52 PM PDT 24
Peak memory 218108 kb
Host smart-74816775-79c6-481c-9b70-86992ff16f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662242762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3662242762
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.435291329
Short name T259
Test name
Test status
Simulation time 136648156 ps
CPU time 0.85 seconds
Started Jun 02 12:43:47 PM PDT 24
Finished Jun 02 12:43:49 PM PDT 24
Peak memory 200884 kb
Host smart-fefcd028-f0b1-4200-a474-feabcf5f59a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435291329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.435291329
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2138254150
Short name T207
Test name
Test status
Simulation time 1086583283 ps
CPU time 5.59 seconds
Started Jun 02 12:43:53 PM PDT 24
Finished Jun 02 12:44:00 PM PDT 24
Peak memory 201008 kb
Host smart-046031a9-2d92-4927-baf1-a022a9f3a878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138254150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2138254150
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.931987003
Short name T306
Test name
Test status
Simulation time 152539354 ps
CPU time 1.15 seconds
Started Jun 02 12:43:46 PM PDT 24
Finished Jun 02 12:43:48 PM PDT 24
Peak memory 200784 kb
Host smart-d8176073-c626-4393-966b-b80aefc42644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931987003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.931987003
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3967305796
Short name T2
Test name
Test status
Simulation time 116083002 ps
CPU time 1.17 seconds
Started Jun 02 12:43:47 PM PDT 24
Finished Jun 02 12:43:49 PM PDT 24
Peak memory 200940 kb
Host smart-c795f21a-c7d9-457b-aaca-4c86e91dc442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967305796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3967305796
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.177806011
Short name T257
Test name
Test status
Simulation time 2213926225 ps
CPU time 8.24 seconds
Started Jun 02 12:43:50 PM PDT 24
Finished Jun 02 12:43:59 PM PDT 24
Peak memory 201108 kb
Host smart-9fcfb03c-886a-43e9-befe-50c796e505f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177806011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.177806011
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.4163247512
Short name T270
Test name
Test status
Simulation time 396945043 ps
CPU time 2.14 seconds
Started Jun 02 12:43:46 PM PDT 24
Finished Jun 02 12:43:48 PM PDT 24
Peak memory 209012 kb
Host smart-bd48c5a1-88bb-4165-a9e4-1dab4eedb171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163247512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.4163247512
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.244757994
Short name T481
Test name
Test status
Simulation time 111864922 ps
CPU time 1.12 seconds
Started Jun 02 12:43:45 PM PDT 24
Finished Jun 02 12:43:46 PM PDT 24
Peak memory 200748 kb
Host smart-626bca7f-368d-424b-9365-3a3ed4fac0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244757994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.244757994
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2224090465
Short name T248
Test name
Test status
Simulation time 70742243 ps
CPU time 0.78 seconds
Started Jun 02 12:43:57 PM PDT 24
Finished Jun 02 12:43:58 PM PDT 24
Peak memory 200548 kb
Host smart-48eaab40-4c31-4f20-9774-2523927ae31c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224090465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2224090465
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2624848665
Short name T315
Test name
Test status
Simulation time 1886633128 ps
CPU time 6.95 seconds
Started Jun 02 12:43:54 PM PDT 24
Finished Jun 02 12:44:02 PM PDT 24
Peak memory 218416 kb
Host smart-560a22c1-0a47-461b-aecf-dbeb9b5cd687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624848665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2624848665
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1635940794
Short name T535
Test name
Test status
Simulation time 243315071 ps
CPU time 1.13 seconds
Started Jun 02 12:43:56 PM PDT 24
Finished Jun 02 12:43:57 PM PDT 24
Peak memory 218004 kb
Host smart-e0b56c90-94fe-4eab-99a0-403af89489ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635940794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1635940794
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.631475268
Short name T450
Test name
Test status
Simulation time 223452575 ps
CPU time 0.93 seconds
Started Jun 02 12:43:56 PM PDT 24
Finished Jun 02 12:43:57 PM PDT 24
Peak memory 200632 kb
Host smart-ebf6b794-eceb-4564-859b-6a111fac5bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631475268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.631475268
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.1696988941
Short name T368
Test name
Test status
Simulation time 1702130735 ps
CPU time 6.67 seconds
Started Jun 02 12:43:52 PM PDT 24
Finished Jun 02 12:43:59 PM PDT 24
Peak memory 200992 kb
Host smart-afac3ea5-9821-41f9-bc9d-122b29506fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696988941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1696988941
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2667946542
Short name T418
Test name
Test status
Simulation time 173701048 ps
CPU time 1.2 seconds
Started Jun 02 12:43:51 PM PDT 24
Finished Jun 02 12:43:53 PM PDT 24
Peak memory 200784 kb
Host smart-164829f5-3f62-485f-bd44-43693f703b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667946542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2667946542
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1223255700
Short name T372
Test name
Test status
Simulation time 216205618 ps
CPU time 1.42 seconds
Started Jun 02 12:43:52 PM PDT 24
Finished Jun 02 12:43:54 PM PDT 24
Peak memory 200944 kb
Host smart-cfe989cd-bc1d-4b47-9f71-cec5e23f2fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223255700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1223255700
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1904860900
Short name T70
Test name
Test status
Simulation time 8071212892 ps
CPU time 37.37 seconds
Started Jun 02 12:43:58 PM PDT 24
Finished Jun 02 12:44:36 PM PDT 24
Peak memory 209324 kb
Host smart-2beba71e-9969-4b5e-b44e-97df5c31199f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904860900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1904860900
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.4072824475
Short name T72
Test name
Test status
Simulation time 139413093 ps
CPU time 1.8 seconds
Started Jun 02 12:43:55 PM PDT 24
Finished Jun 02 12:43:58 PM PDT 24
Peak memory 200832 kb
Host smart-f5c9232f-3c8b-4f49-b7b4-9d4b44d6dd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072824475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.4072824475
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3157223623
Short name T303
Test name
Test status
Simulation time 97205556 ps
CPU time 0.9 seconds
Started Jun 02 12:43:56 PM PDT 24
Finished Jun 02 12:43:57 PM PDT 24
Peak memory 200768 kb
Host smart-3e46617d-0f98-40fa-b41e-0246d9e6defc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157223623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3157223623
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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