Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8264

1

T5

48

T6

30

T7

168

auto[1]

11047

1

T5

58

T6

24

T7

160

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5990	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6543	1			T1	1		T2	1		T3	1
reset_info_cp[2]	3019	1			T5	23		T6	10		T7	55
reset_info_cp[4]	3852	1			T5	25		T6	12		T7	68
reset_info_cp[8]	106	1			T7	1		T23	1		T89	1
reset_info_cp[16]	96	1			T7	1		T109	1		T48	1
reset_info_cp[32]	103	1			T7	1		T8	3		T89	3
reset_info_cp[64]	119	1			T5	1		T8	1		T89	3
reset_info_cp[128]	103	1			T7	1		T110	1		T91	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3161	1			T5	13		T6	11		T7	50
reset_info_cp[1]	auto[1]	2762	1			T5	17		T6	4		T7	49
reset_info_cp[2]	auto[0]	961	1			T5	12		T6	3		T7	26
reset_info_cp[2]	auto[1]	2058	1			T5	11		T6	7		T7	29
reset_info_cp[4]	auto[0]	1385	1			T5	8		T6	5		T7	30
reset_info_cp[4]	auto[1]	2467	1			T5	17		T6	7		T7	38
reset_info_cp[8]	auto[0]	47	1			T7	1		T115	1		T148	1
reset_info_cp[8]	auto[1]	59	1			T23	1		T89	1		T42	1
reset_info_cp[16]	auto[0]	42	1			T109	1		T112	1		T124	1
reset_info_cp[16]	auto[1]	54	1			T7	1		T48	1		T24	2
reset_info_cp[32]	auto[0]	38	1			T8	3		T89	1		T111	1
reset_info_cp[32]	auto[1]	65	1			T7	1		T89	2		T51	1
reset_info_cp[64]	auto[0]	53	1			T5	1		T8	1		T89	1
reset_info_cp[64]	auto[1]	66	1			T89	2		T42	1		T48	1
reset_info_cp[128]	auto[0]	37	1			T91	1		T112	1		T150	2
reset_info_cp[128]	auto[1]	66	1			T7	1		T110	1		T92	1