Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T541 /workspace/coverage/default/12.rstmgr_por_stretcher.3772568115 Jun 04 12:54:20 PM PDT 24 Jun 04 12:54:23 PM PDT 24 115373608 ps
T542 /workspace/coverage/default/46.rstmgr_por_stretcher.4236554681 Jun 04 12:55:06 PM PDT 24 Jun 04 12:55:08 PM PDT 24 154537601 ps
T79 /workspace/coverage/default/0.rstmgr_sec_cm.538947742 Jun 04 12:53:51 PM PDT 24 Jun 04 12:54:23 PM PDT 24 16517040511 ps
T543 /workspace/coverage/default/25.rstmgr_sw_rst.1593572362 Jun 04 12:54:35 PM PDT 24 Jun 04 12:54:37 PM PDT 24 386525242 ps
T544 /workspace/coverage/default/32.rstmgr_stress_all.1661510745 Jun 04 12:54:48 PM PDT 24 Jun 04 12:55:03 PM PDT 24 2968515323 ps
T70 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1821558827 Jun 04 12:47:46 PM PDT 24 Jun 04 12:47:50 PM PDT 24 189527162 ps
T63 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1111205281 Jun 04 12:47:49 PM PDT 24 Jun 04 12:47:52 PM PDT 24 88438227 ps
T64 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.377912588 Jun 04 12:47:27 PM PDT 24 Jun 04 12:47:29 PM PDT 24 154483598 ps
T65 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3336140098 Jun 04 12:47:44 PM PDT 24 Jun 04 12:47:47 PM PDT 24 135855754 ps
T66 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2197891724 Jun 04 12:47:14 PM PDT 24 Jun 04 12:47:17 PM PDT 24 104788215 ps
T67 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.270543630 Jun 04 12:47:17 PM PDT 24 Jun 04 12:47:20 PM PDT 24 87035117 ps
T68 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.794283094 Jun 04 12:47:38 PM PDT 24 Jun 04 12:47:40 PM PDT 24 137315199 ps
T545 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.4131520130 Jun 04 12:47:33 PM PDT 24 Jun 04 12:47:35 PM PDT 24 62775503 ps
T71 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2212126241 Jun 04 12:47:13 PM PDT 24 Jun 04 12:47:19 PM PDT 24 958870931 ps
T546 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1129854743 Jun 04 12:47:14 PM PDT 24 Jun 04 12:47:18 PM PDT 24 91277684 ps
T127 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.407784313 Jun 04 12:47:15 PM PDT 24 Jun 04 12:47:18 PM PDT 24 63779215 ps
T128 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1044369078 Jun 04 12:47:29 PM PDT 24 Jun 04 12:47:36 PM PDT 24 65444822 ps
T129 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1705725430 Jun 04 12:47:42 PM PDT 24 Jun 04 12:47:45 PM PDT 24 225316580 ps
T72 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1670127613 Jun 04 12:47:54 PM PDT 24 Jun 04 12:47:57 PM PDT 24 171315858 ps
T98 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1115310574 Jun 04 12:47:23 PM PDT 24 Jun 04 12:47:25 PM PDT 24 108290563 ps
T547 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1187877155 Jun 04 12:47:17 PM PDT 24 Jun 04 12:47:20 PM PDT 24 93332462 ps
T135 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4178776120 Jun 04 12:47:36 PM PDT 24 Jun 04 12:47:40 PM PDT 24 613197795 ps
T130 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.389243234 Jun 04 12:47:29 PM PDT 24 Jun 04 12:47:31 PM PDT 24 256500064 ps
T99 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3057717912 Jun 04 12:47:26 PM PDT 24 Jun 04 12:47:29 PM PDT 24 408196690 ps
T131 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1617405480 Jun 04 12:47:27 PM PDT 24 Jun 04 12:47:30 PM PDT 24 68323890 ps
T132 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4235661783 Jun 04 12:47:27 PM PDT 24 Jun 04 12:47:31 PM PDT 24 229120557 ps
T100 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1739528447 Jun 04 12:47:28 PM PDT 24 Jun 04 12:47:30 PM PDT 24 125659657 ps
T108 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4193149006 Jun 04 12:47:23 PM PDT 24 Jun 04 12:47:26 PM PDT 24 443410766 ps
T101 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2482903088 Jun 04 12:47:47 PM PDT 24 Jun 04 12:47:50 PM PDT 24 494532331 ps
T102 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.916624601 Jun 04 12:47:23 PM PDT 24 Jun 04 12:47:27 PM PDT 24 942626361 ps
T548 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1547019413 Jun 04 12:47:44 PM PDT 24 Jun 04 12:47:47 PM PDT 24 80399372 ps
T133 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2874448522 Jun 04 12:47:44 PM PDT 24 Jun 04 12:47:47 PM PDT 24 83578249 ps
T103 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.260313019 Jun 04 12:47:15 PM PDT 24 Jun 04 12:47:18 PM PDT 24 101482327 ps
T104 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.948172875 Jun 04 12:47:27 PM PDT 24 Jun 04 12:47:31 PM PDT 24 809002830 ps
T549 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1839481966 Jun 04 12:47:27 PM PDT 24 Jun 04 12:47:30 PM PDT 24 75156718 ps
T134 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2742346315 Jun 04 12:47:47 PM PDT 24 Jun 04 12:47:50 PM PDT 24 75118111 ps
T105 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2647109755 Jun 04 12:47:24 PM PDT 24 Jun 04 12:47:26 PM PDT 24 120038137 ps
T138 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3928732322 Jun 04 12:47:20 PM PDT 24 Jun 04 12:47:25 PM PDT 24 915081694 ps
T550 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3708128262 Jun 04 12:47:14 PM PDT 24 Jun 04 12:47:22 PM PDT 24 1041502622 ps
T106 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2983301628 Jun 04 12:47:43 PM PDT 24 Jun 04 12:47:47 PM PDT 24 193240663 ps
T107 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.691854021 Jun 04 12:47:22 PM PDT 24 Jun 04 12:47:25 PM PDT 24 167704308 ps
T551 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3325588035 Jun 04 12:47:21 PM PDT 24 Jun 04 12:47:25 PM PDT 24 500627008 ps
T137 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1785606235 Jun 04 12:47:24 PM PDT 24 Jun 04 12:47:29 PM PDT 24 572833012 ps
T136 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1564186077 Jun 04 12:47:22 PM PDT 24 Jun 04 12:47:26 PM PDT 24 797454313 ps
T552 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3666829976 Jun 04 12:47:48 PM PDT 24 Jun 04 12:47:51 PM PDT 24 89201484 ps
T553 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2844603589 Jun 04 12:47:25 PM PDT 24 Jun 04 12:47:28 PM PDT 24 479785968 ps
T143 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3318886001 Jun 04 12:47:43 PM PDT 24 Jun 04 12:47:48 PM PDT 24 468409777 ps
T554 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1918861431 Jun 04 12:47:12 PM PDT 24 Jun 04 12:47:15 PM PDT 24 175953259 ps
T555 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.4274467465 Jun 04 12:47:44 PM PDT 24 Jun 04 12:47:47 PM PDT 24 120788628 ps
T556 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3893321908 Jun 04 12:47:45 PM PDT 24 Jun 04 12:47:47 PM PDT 24 116605560 ps
T557 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2682476110 Jun 04 12:47:21 PM PDT 24 Jun 04 12:47:23 PM PDT 24 70609976 ps
T558 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.695658456 Jun 04 12:47:16 PM PDT 24 Jun 04 12:47:20 PM PDT 24 107276834 ps
T139 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.4086585343 Jun 04 12:47:47 PM PDT 24 Jun 04 12:47:51 PM PDT 24 496652044 ps
T559 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3575563721 Jun 04 12:47:28 PM PDT 24 Jun 04 12:47:30 PM PDT 24 68451004 ps
T560 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1114983928 Jun 04 12:47:16 PM PDT 24 Jun 04 12:47:19 PM PDT 24 59241381 ps
T561 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1688411320 Jun 04 12:47:46 PM PDT 24 Jun 04 12:47:49 PM PDT 24 192116425 ps
T562 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3679894822 Jun 04 12:47:21 PM PDT 24 Jun 04 12:47:25 PM PDT 24 864623756 ps
T563 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1504199026 Jun 04 12:47:40 PM PDT 24 Jun 04 12:47:42 PM PDT 24 174903862 ps
T564 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.636474818 Jun 04 12:47:23 PM PDT 24 Jun 04 12:47:25 PM PDT 24 67817899 ps
T565 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2829262581 Jun 04 12:47:16 PM PDT 24 Jun 04 12:47:21 PM PDT 24 315079490 ps
T566 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.447162581 Jun 04 12:47:45 PM PDT 24 Jun 04 12:47:47 PM PDT 24 147533869 ps
T567 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2502073663 Jun 04 12:47:20 PM PDT 24 Jun 04 12:47:23 PM PDT 24 128747324 ps
T568 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2453241499 Jun 04 12:47:14 PM PDT 24 Jun 04 12:47:17 PM PDT 24 138617910 ps
T569 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1080931325 Jun 04 12:47:21 PM PDT 24 Jun 04 12:47:27 PM PDT 24 806245256 ps
T570 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.4112911252 Jun 04 12:47:15 PM PDT 24 Jun 04 12:47:23 PM PDT 24 1174631562 ps
T571 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2663434577 Jun 04 12:47:37 PM PDT 24 Jun 04 12:47:41 PM PDT 24 436453934 ps
T572 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3267575367 Jun 04 12:47:20 PM PDT 24 Jun 04 12:47:22 PM PDT 24 103778190 ps
T573 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1153145185 Jun 04 12:47:24 PM PDT 24 Jun 04 12:47:27 PM PDT 24 369110471 ps
T574 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3226055340 Jun 04 12:47:25 PM PDT 24 Jun 04 12:47:27 PM PDT 24 112232196 ps
T575 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.4034432697 Jun 04 12:47:14 PM PDT 24 Jun 04 12:47:17 PM PDT 24 174739376 ps
T140 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.4120550330 Jun 04 12:47:31 PM PDT 24 Jun 04 12:47:35 PM PDT 24 891000884 ps
T576 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2502426834 Jun 04 12:47:28 PM PDT 24 Jun 04 12:47:31 PM PDT 24 457822266 ps
T577 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1331168441 Jun 04 12:47:25 PM PDT 24 Jun 04 12:47:27 PM PDT 24 186655168 ps
T578 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1132474256 Jun 04 12:47:39 PM PDT 24 Jun 04 12:47:40 PM PDT 24 75615544 ps
T579 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1923199878 Jun 04 12:47:15 PM PDT 24 Jun 04 12:47:22 PM PDT 24 805159886 ps
T580 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1755378147 Jun 04 12:47:43 PM PDT 24 Jun 04 12:47:46 PM PDT 24 117862922 ps
T581 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.761810853 Jun 04 12:47:30 PM PDT 24 Jun 04 12:47:33 PM PDT 24 120831580 ps
T582 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1756159956 Jun 04 12:47:31 PM PDT 24 Jun 04 12:47:34 PM PDT 24 274322689 ps
T583 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1468298430 Jun 04 12:47:45 PM PDT 24 Jun 04 12:47:47 PM PDT 24 174371469 ps
T584 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.407402131 Jun 04 12:47:43 PM PDT 24 Jun 04 12:47:45 PM PDT 24 92232843 ps
T585 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.58519144 Jun 04 12:47:26 PM PDT 24 Jun 04 12:47:29 PM PDT 24 200454027 ps
T586 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.35966644 Jun 04 12:47:33 PM PDT 24 Jun 04 12:47:35 PM PDT 24 284611297 ps
T587 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3482059697 Jun 04 12:47:15 PM PDT 24 Jun 04 12:47:20 PM PDT 24 442994195 ps
T588 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.118245186 Jun 04 12:47:27 PM PDT 24 Jun 04 12:47:31 PM PDT 24 200158426 ps
T589 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1472658774 Jun 04 12:47:27 PM PDT 24 Jun 04 12:47:30 PM PDT 24 74692963 ps
T590 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2779026062 Jun 04 12:47:43 PM PDT 24 Jun 04 12:47:46 PM PDT 24 85693089 ps
T591 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3185943166 Jun 04 12:47:36 PM PDT 24 Jun 04 12:47:39 PM PDT 24 79241487 ps
T592 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.589015511 Jun 04 12:47:27 PM PDT 24 Jun 04 12:47:29 PM PDT 24 132941752 ps
T593 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.86591102 Jun 04 12:47:25 PM PDT 24 Jun 04 12:47:27 PM PDT 24 209332267 ps
T594 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3101516586 Jun 04 12:47:31 PM PDT 24 Jun 04 12:47:33 PM PDT 24 113197624 ps
T595 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2553144211 Jun 04 12:47:26 PM PDT 24 Jun 04 12:47:28 PM PDT 24 87111732 ps
T596 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1993422998 Jun 04 12:47:11 PM PDT 24 Jun 04 12:47:16 PM PDT 24 619786218 ps
T597 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2531170832 Jun 04 12:47:26 PM PDT 24 Jun 04 12:47:29 PM PDT 24 147748588 ps
T598 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3820046362 Jun 04 12:47:21 PM PDT 24 Jun 04 12:47:25 PM PDT 24 296652814 ps
T146 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1099229073 Jun 04 12:47:49 PM PDT 24 Jun 04 12:47:54 PM PDT 24 788944037 ps
T599 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.853085160 Jun 04 12:47:17 PM PDT 24 Jun 04 12:47:22 PM PDT 24 179982628 ps
T600 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.936340670 Jun 04 12:47:49 PM PDT 24 Jun 04 12:47:52 PM PDT 24 172863048 ps
T601 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.460385017 Jun 04 12:47:14 PM PDT 24 Jun 04 12:47:18 PM PDT 24 67700288 ps
T602 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2699479319 Jun 04 12:47:28 PM PDT 24 Jun 04 12:47:30 PM PDT 24 113619844 ps
T603 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.509174393 Jun 04 12:47:14 PM PDT 24 Jun 04 12:47:17 PM PDT 24 80319167 ps
T604 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.334526513 Jun 04 12:47:20 PM PDT 24 Jun 04 12:47:24 PM PDT 24 141235850 ps
T605 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.315162238 Jun 04 12:47:22 PM PDT 24 Jun 04 12:47:24 PM PDT 24 128291190 ps
T606 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.25214968 Jun 04 12:47:35 PM PDT 24 Jun 04 12:47:36 PM PDT 24 66410188 ps
T607 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3850068573 Jun 04 12:47:28 PM PDT 24 Jun 04 12:47:31 PM PDT 24 213485571 ps
T141 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2325748914 Jun 04 12:47:28 PM PDT 24 Jun 04 12:47:31 PM PDT 24 470492067 ps
T608 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.702891494 Jun 04 12:47:27 PM PDT 24 Jun 04 12:47:30 PM PDT 24 172322100 ps
T609 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.197944140 Jun 04 12:47:45 PM PDT 24 Jun 04 12:47:49 PM PDT 24 162858237 ps
T610 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.291866385 Jun 04 12:47:33 PM PDT 24 Jun 04 12:47:35 PM PDT 24 196439839 ps
T142 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3596565118 Jun 04 12:47:46 PM PDT 24 Jun 04 12:47:49 PM PDT 24 473080946 ps
T147 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.647618011 Jun 04 12:47:47 PM PDT 24 Jun 04 12:47:51 PM PDT 24 458704070 ps
T611 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2609837412 Jun 04 12:47:28 PM PDT 24 Jun 04 12:47:31 PM PDT 24 124328051 ps
T612 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3703473556 Jun 04 12:47:36 PM PDT 24 Jun 04 12:47:38 PM PDT 24 67360648 ps
T613 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.378525794 Jun 04 12:47:50 PM PDT 24 Jun 04 12:47:54 PM PDT 24 259158078 ps
T614 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1243397910 Jun 04 12:47:16 PM PDT 24 Jun 04 12:47:19 PM PDT 24 94994930 ps
T615 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1486263907 Jun 04 12:47:20 PM PDT 24 Jun 04 12:47:21 PM PDT 24 81900333 ps
T616 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1723850191 Jun 04 12:47:36 PM PDT 24 Jun 04 12:47:39 PM PDT 24 117153743 ps
T617 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1611864586 Jun 04 12:47:15 PM PDT 24 Jun 04 12:47:19 PM PDT 24 114695763 ps
T618 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2055324813 Jun 04 12:47:15 PM PDT 24 Jun 04 12:47:19 PM PDT 24 228772891 ps
T619 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1515163973 Jun 04 12:47:43 PM PDT 24 Jun 04 12:47:46 PM PDT 24 269565860 ps
T620 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2368689225 Jun 04 12:47:26 PM PDT 24 Jun 04 12:47:34 PM PDT 24 1559543675 ps

Test location /workspace/coverage/default/19.rstmgr_stress_all.4156573967
Short name T5
Test name
Test status
Simulation time 2865212392 ps
CPU time 11.15 seconds
Started Jun 04 12:54:28 PM PDT 24
Finished Jun 04 12:54:40 PM PDT 24
Peak memory 201152 kb
Host smart-2363cc27-c28b-44b6-a676-58e446420b45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156573967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.4156573967
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3076143
Short name T53
Test name
Test status
Simulation time 437858928 ps
CPU time 2.28 seconds
Started Jun 04 12:54:54 PM PDT 24
Finished Jun 04 12:54:58 PM PDT 24
Peak memory 209056 kb
Host smart-5d73548f-4bc7-458e-aae5-a40265425321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3076143
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.314746197
Short name T7
Test name
Test status
Simulation time 8883471798 ps
CPU time 32.95 seconds
Started Jun 04 12:55:14 PM PDT 24
Finished Jun 04 12:55:49 PM PDT 24
Peak memory 201164 kb
Host smart-73999d6e-2b28-4add-b388-392eb0ef86ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314746197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.314746197
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2212126241
Short name T71
Test name
Test status
Simulation time 958870931 ps
CPU time 3.25 seconds
Started Jun 04 12:47:13 PM PDT 24
Finished Jun 04 12:47:19 PM PDT 24
Peak memory 200536 kb
Host smart-d6de7b93-cb4b-4dec-8ca2-8761d49432b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212126241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.2212126241
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.538947742
Short name T79
Test name
Test status
Simulation time 16517040511 ps
CPU time 31.54 seconds
Started Jun 04 12:53:51 PM PDT 24
Finished Jun 04 12:54:23 PM PDT 24
Peak memory 217876 kb
Host smart-15b45e30-3fd0-48e0-acb9-fa051e791d5b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538947742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.538947742
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3751477968
Short name T47
Test name
Test status
Simulation time 1892744977 ps
CPU time 7.01 seconds
Started Jun 04 12:54:09 PM PDT 24
Finished Jun 04 12:54:17 PM PDT 24
Peak memory 217444 kb
Host smart-4ea9e773-a56e-403e-98c6-11e06c5a9283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751477968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3751477968
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.691854021
Short name T107
Test name
Test status
Simulation time 167704308 ps
CPU time 1.47 seconds
Started Jun 04 12:47:22 PM PDT 24
Finished Jun 04 12:47:25 PM PDT 24
Peak memory 208556 kb
Host smart-bc4b53ff-89d2-4255-906b-95739ff9cca6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691854021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.691854021
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.141022519
Short name T3
Test name
Test status
Simulation time 80567241 ps
CPU time 0.87 seconds
Started Jun 04 12:53:59 PM PDT 24
Finished Jun 04 12:54:01 PM PDT 24
Peak memory 200684 kb
Host smart-44cbd2e9-2c07-4cf6-b1b5-b12fa67e7d66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141022519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.141022519
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3777178399
Short name T223
Test name
Test status
Simulation time 10005065652 ps
CPU time 35.37 seconds
Started Jun 04 12:54:22 PM PDT 24
Finished Jun 04 12:54:59 PM PDT 24
Peak memory 210016 kb
Host smart-090c7897-8095-48be-82b9-13605021fb0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777178399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3777178399
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2175802113
Short name T29
Test name
Test status
Simulation time 1887924784 ps
CPU time 7.21 seconds
Started Jun 04 12:54:27 PM PDT 24
Finished Jun 04 12:54:36 PM PDT 24
Peak memory 218424 kb
Host smart-a6746380-880c-4d79-a3b1-96db347472dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175802113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2175802113
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.4154978313
Short name T40
Test name
Test status
Simulation time 154039997 ps
CPU time 1.23 seconds
Started Jun 04 12:54:22 PM PDT 24
Finished Jun 04 12:54:25 PM PDT 24
Peak memory 200828 kb
Host smart-c044921b-ac29-4126-b690-49261a87dcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154978313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.4154978313
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.361582630
Short name T118
Test name
Test status
Simulation time 11294702766 ps
CPU time 35.66 seconds
Started Jun 04 12:55:13 PM PDT 24
Finished Jun 04 12:55:51 PM PDT 24
Peak memory 217584 kb
Host smart-a796d547-c5e9-4130-8499-3819b5c81eed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361582630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.361582630
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4178776120
Short name T135
Test name
Test status
Simulation time 613197795 ps
CPU time 2.15 seconds
Started Jun 04 12:47:36 PM PDT 24
Finished Jun 04 12:47:40 PM PDT 24
Peak memory 200676 kb
Host smart-e85ae82b-70d9-4191-9376-caf044ce5bb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178776120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.4178776120
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3596565118
Short name T142
Test name
Test status
Simulation time 473080946 ps
CPU time 2.08 seconds
Started Jun 04 12:47:46 PM PDT 24
Finished Jun 04 12:47:49 PM PDT 24
Peak memory 200540 kb
Host smart-beb49976-8d02-4ef3-a57a-5463073e4b25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596565118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3596565118
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.1622987209
Short name T91
Test name
Test status
Simulation time 127948120 ps
CPU time 1.13 seconds
Started Jun 04 12:53:54 PM PDT 24
Finished Jun 04 12:53:56 PM PDT 24
Peak memory 200880 kb
Host smart-380ec754-541a-4936-beb7-51792e268ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622987209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1622987209
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3318886001
Short name T143
Test name
Test status
Simulation time 468409777 ps
CPU time 3.43 seconds
Started Jun 04 12:47:43 PM PDT 24
Finished Jun 04 12:47:48 PM PDT 24
Peak memory 208688 kb
Host smart-d86a8b47-180c-4a5c-abcb-0ec3cb34e601
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318886001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3318886001
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.553953457
Short name T89
Test name
Test status
Simulation time 5174536106 ps
CPU time 23.89 seconds
Started Jun 04 12:54:59 PM PDT 24
Finished Jun 04 12:55:25 PM PDT 24
Peak memory 201204 kb
Host smart-a4a3853c-2d5b-4bac-b545-9c17ccc6c421
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553953457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.553953457
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.214202324
Short name T25
Test name
Test status
Simulation time 2168339996 ps
CPU time 7.52 seconds
Started Jun 04 12:54:43 PM PDT 24
Finished Jun 04 12:54:57 PM PDT 24
Peak memory 222632 kb
Host smart-054ae417-6089-4497-b6e8-fdf108523d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214202324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.214202324
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2874448522
Short name T133
Test name
Test status
Simulation time 83578249 ps
CPU time 0.94 seconds
Started Jun 04 12:47:44 PM PDT 24
Finished Jun 04 12:47:47 PM PDT 24
Peak memory 200332 kb
Host smart-adb7ef89-3864-4b5c-a39f-bbffd550731c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874448522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.2874448522
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2689760642
Short name T18
Test name
Test status
Simulation time 211998299 ps
CPU time 0.89 seconds
Started Jun 04 12:54:23 PM PDT 24
Finished Jun 04 12:54:25 PM PDT 24
Peak memory 200672 kb
Host smart-b8c3534d-6440-40a5-bab4-90a99d194ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689760642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2689760642
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2325748914
Short name T141
Test name
Test status
Simulation time 470492067 ps
CPU time 1.96 seconds
Started Jun 04 12:47:28 PM PDT 24
Finished Jun 04 12:47:31 PM PDT 24
Peak memory 200580 kb
Host smart-0b1ac4ab-7522-4845-929b-244b978c5751
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325748914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2325748914
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.291866385
Short name T610
Test name
Test status
Simulation time 196439839 ps
CPU time 1.47 seconds
Started Jun 04 12:47:33 PM PDT 24
Finished Jun 04 12:47:35 PM PDT 24
Peak memory 200388 kb
Host smart-a8cbaf45-e782-4f73-8287-c9a8bc97b011
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291866385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.291866385
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3708128262
Short name T550
Test name
Test status
Simulation time 1041502622 ps
CPU time 4.77 seconds
Started Jun 04 12:47:14 PM PDT 24
Finished Jun 04 12:47:22 PM PDT 24
Peak memory 200356 kb
Host smart-e4eb8000-2940-4876-97ed-db5a6f7d78b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708128262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
708128262
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.377912588
Short name T64
Test name
Test status
Simulation time 154483598 ps
CPU time 0.94 seconds
Started Jun 04 12:47:27 PM PDT 24
Finished Jun 04 12:47:29 PM PDT 24
Peak memory 200236 kb
Host smart-a02e77e0-cf5f-463e-b7eb-4fb881d050e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377912588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.377912588
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.4034432697
Short name T575
Test name
Test status
Simulation time 174739376 ps
CPU time 1.15 seconds
Started Jun 04 12:47:14 PM PDT 24
Finished Jun 04 12:47:17 PM PDT 24
Peak memory 208492 kb
Host smart-4ed44a17-6c32-4e94-82b5-d7b92b019393
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034432697 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.4034432697
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.460385017
Short name T601
Test name
Test status
Simulation time 67700288 ps
CPU time 0.82 seconds
Started Jun 04 12:47:14 PM PDT 24
Finished Jun 04 12:47:18 PM PDT 24
Peak memory 200304 kb
Host smart-877e0c00-bcf3-407e-a711-dc7bd1161b5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460385017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.460385017
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.509174393
Short name T603
Test name
Test status
Simulation time 80319167 ps
CPU time 0.99 seconds
Started Jun 04 12:47:14 PM PDT 24
Finished Jun 04 12:47:17 PM PDT 24
Peak memory 200408 kb
Host smart-5a686f56-484d-46ac-a27b-b6cce87abc52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509174393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sam
e_csr_outstanding.509174393
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1153145185
Short name T573
Test name
Test status
Simulation time 369110471 ps
CPU time 2.31 seconds
Started Jun 04 12:47:24 PM PDT 24
Finished Jun 04 12:47:27 PM PDT 24
Peak memory 208660 kb
Host smart-1d11a072-2c90-4e1b-aa0d-a295bc584408
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153145185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1153145185
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.948172875
Short name T104
Test name
Test status
Simulation time 809002830 ps
CPU time 2.74 seconds
Started Jun 04 12:47:27 PM PDT 24
Finished Jun 04 12:47:31 PM PDT 24
Peak memory 200548 kb
Host smart-2931c3c8-0132-4e4f-aeb5-50cb4537c589
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948172875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.
948172875
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3101516586
Short name T594
Test name
Test status
Simulation time 113197624 ps
CPU time 1.31 seconds
Started Jun 04 12:47:31 PM PDT 24
Finished Jun 04 12:47:33 PM PDT 24
Peak memory 200428 kb
Host smart-4617f767-8322-4426-9d9e-d5e813d59e38
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101516586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
101516586
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2368689225
Short name T620
Test name
Test status
Simulation time 1559543675 ps
CPU time 7.81 seconds
Started Jun 04 12:47:26 PM PDT 24
Finished Jun 04 12:47:34 PM PDT 24
Peak memory 200472 kb
Host smart-735518ea-f0a8-4e61-b09d-607a2ec39d9e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368689225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
368689225
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1187877155
Short name T547
Test name
Test status
Simulation time 93332462 ps
CPU time 0.83 seconds
Started Jun 04 12:47:17 PM PDT 24
Finished Jun 04 12:47:20 PM PDT 24
Peak memory 200228 kb
Host smart-93998c79-6343-4fd9-9264-cb80d9464954
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187877155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1
187877155
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2197891724
Short name T66
Test name
Test status
Simulation time 104788215 ps
CPU time 0.99 seconds
Started Jun 04 12:47:14 PM PDT 24
Finished Jun 04 12:47:17 PM PDT 24
Peak memory 208664 kb
Host smart-a467cb49-de59-4ed4-843f-87f6dcd03e7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197891724 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2197891724
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1486263907
Short name T615
Test name
Test status
Simulation time 81900333 ps
CPU time 0.76 seconds
Started Jun 04 12:47:20 PM PDT 24
Finished Jun 04 12:47:21 PM PDT 24
Peak memory 200280 kb
Host smart-85e9fa6e-4990-4cbb-ab48-e114597dd8c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486263907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1486263907
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2453241499
Short name T568
Test name
Test status
Simulation time 138617910 ps
CPU time 1.09 seconds
Started Jun 04 12:47:14 PM PDT 24
Finished Jun 04 12:47:17 PM PDT 24
Peak memory 200416 kb
Host smart-6277d8e2-7501-4bc7-a7de-77bc0cd42023
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453241499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2453241499
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1993422998
Short name T596
Test name
Test status
Simulation time 619786218 ps
CPU time 4.06 seconds
Started Jun 04 12:47:11 PM PDT 24
Finished Jun 04 12:47:16 PM PDT 24
Peak memory 216924 kb
Host smart-8e26e07c-1c1c-4788-8d44-95a411c62fe2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993422998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1993422998
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3679894822
Short name T562
Test name
Test status
Simulation time 864623756 ps
CPU time 2.93 seconds
Started Jun 04 12:47:21 PM PDT 24
Finished Jun 04 12:47:25 PM PDT 24
Peak memory 200532 kb
Host smart-3bf3f178-78eb-4925-9148-f77e49fbbee1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679894822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3679894822
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.936340670
Short name T600
Test name
Test status
Simulation time 172863048 ps
CPU time 1.3 seconds
Started Jun 04 12:47:49 PM PDT 24
Finished Jun 04 12:47:52 PM PDT 24
Peak memory 208572 kb
Host smart-2d27109c-2123-4601-9124-5e5f22e3a278
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936340670 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.936340670
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1839481966
Short name T549
Test name
Test status
Simulation time 75156718 ps
CPU time 0.81 seconds
Started Jun 04 12:47:27 PM PDT 24
Finished Jun 04 12:47:30 PM PDT 24
Peak memory 200196 kb
Host smart-c1ca1f59-bd8f-483d-b864-51add36cb87a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839481966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1839481966
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1670127613
Short name T72
Test name
Test status
Simulation time 171315858 ps
CPU time 2.34 seconds
Started Jun 04 12:47:54 PM PDT 24
Finished Jun 04 12:47:57 PM PDT 24
Peak memory 208752 kb
Host smart-2179a8b9-aee9-44bb-a0f2-59aee63cd072
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670127613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1670127613
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2502073663
Short name T567
Test name
Test status
Simulation time 128747324 ps
CPU time 1.32 seconds
Started Jun 04 12:47:20 PM PDT 24
Finished Jun 04 12:47:23 PM PDT 24
Peak memory 208504 kb
Host smart-bc8b35ad-9a75-4910-8741-937a661bebe5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502073663 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2502073663
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3666829976
Short name T552
Test name
Test status
Simulation time 89201484 ps
CPU time 0.89 seconds
Started Jun 04 12:47:48 PM PDT 24
Finished Jun 04 12:47:51 PM PDT 24
Peak memory 200252 kb
Host smart-a358be57-d5a9-4487-821a-121e8a690d2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666829976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3666829976
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2531170832
Short name T597
Test name
Test status
Simulation time 147748588 ps
CPU time 1.13 seconds
Started Jun 04 12:47:26 PM PDT 24
Finished Jun 04 12:47:29 PM PDT 24
Peak memory 200408 kb
Host smart-ad10e642-ce40-4170-8455-7890058280bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531170832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2531170832
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2482903088
Short name T101
Test name
Test status
Simulation time 494532331 ps
CPU time 1.99 seconds
Started Jun 04 12:47:47 PM PDT 24
Finished Jun 04 12:47:50 PM PDT 24
Peak memory 200476 kb
Host smart-3171b6bd-9aaa-40b4-b6b1-fb525c2707ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482903088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2482903088
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.702891494
Short name T608
Test name
Test status
Simulation time 172322100 ps
CPU time 1.67 seconds
Started Jun 04 12:47:27 PM PDT 24
Finished Jun 04 12:47:30 PM PDT 24
Peak memory 208376 kb
Host smart-4aebd028-fda0-42dc-8941-ed352ee4852e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702891494 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.702891494
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.636474818
Short name T564
Test name
Test status
Simulation time 67817899 ps
CPU time 0.84 seconds
Started Jun 04 12:47:23 PM PDT 24
Finished Jun 04 12:47:25 PM PDT 24
Peak memory 200324 kb
Host smart-6ea87a02-f1e9-4d89-8f87-8237f2538179
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636474818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.636474818
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4235661783
Short name T132
Test name
Test status
Simulation time 229120557 ps
CPU time 1.46 seconds
Started Jun 04 12:47:27 PM PDT 24
Finished Jun 04 12:47:31 PM PDT 24
Peak memory 208660 kb
Host smart-286c61c6-3e17-4ab9-be79-45683ede47db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235661783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.4235661783
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.197944140
Short name T609
Test name
Test status
Simulation time 162858237 ps
CPU time 2.41 seconds
Started Jun 04 12:47:45 PM PDT 24
Finished Jun 04 12:47:49 PM PDT 24
Peak memory 208852 kb
Host smart-0f830aed-5fdd-4310-b996-629055b05079
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197944140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.197944140
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1504199026
Short name T563
Test name
Test status
Simulation time 174903862 ps
CPU time 1.67 seconds
Started Jun 04 12:47:40 PM PDT 24
Finished Jun 04 12:47:42 PM PDT 24
Peak memory 208660 kb
Host smart-7e6c0b8f-e174-4ea4-9968-926989222035
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504199026 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.1504199026
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.25214968
Short name T606
Test name
Test status
Simulation time 66410188 ps
CPU time 0.81 seconds
Started Jun 04 12:47:35 PM PDT 24
Finished Jun 04 12:47:36 PM PDT 24
Peak memory 200328 kb
Host smart-a19aa7ea-868b-4d3e-816b-2541f97671d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25214968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.25214968
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1331168441
Short name T577
Test name
Test status
Simulation time 186655168 ps
CPU time 1.35 seconds
Started Jun 04 12:47:25 PM PDT 24
Finished Jun 04 12:47:27 PM PDT 24
Peak memory 200520 kb
Host smart-a3bce783-d0ca-48ad-88d0-73b6b8e7861c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331168441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1331168441
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.334526513
Short name T604
Test name
Test status
Simulation time 141235850 ps
CPU time 2 seconds
Started Jun 04 12:47:20 PM PDT 24
Finished Jun 04 12:47:24 PM PDT 24
Peak memory 208704 kb
Host smart-47feeab2-61d7-4e4e-9189-5fe41c843bee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334526513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.334526513
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3057717912
Short name T99
Test name
Test status
Simulation time 408196690 ps
CPU time 1.83 seconds
Started Jun 04 12:47:26 PM PDT 24
Finished Jun 04 12:47:29 PM PDT 24
Peak memory 200536 kb
Host smart-654b4fb4-7861-45f8-9b5d-b4ddcad36bd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057717912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3057717912
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1115310574
Short name T98
Test name
Test status
Simulation time 108290563 ps
CPU time 0.96 seconds
Started Jun 04 12:47:23 PM PDT 24
Finished Jun 04 12:47:25 PM PDT 24
Peak memory 200312 kb
Host smart-3d9beb0e-76d6-4994-a095-45a813f3b62b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115310574 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.1115310574
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3703473556
Short name T612
Test name
Test status
Simulation time 67360648 ps
CPU time 0.8 seconds
Started Jun 04 12:47:36 PM PDT 24
Finished Jun 04 12:47:38 PM PDT 24
Peak memory 200344 kb
Host smart-7e0f6cb9-8720-43e8-b623-63ab90579dcb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703473556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3703473556
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2779026062
Short name T590
Test name
Test status
Simulation time 85693089 ps
CPU time 1.05 seconds
Started Jun 04 12:47:43 PM PDT 24
Finished Jun 04 12:47:46 PM PDT 24
Peak memory 200248 kb
Host smart-afccd8fa-7362-4397-992c-64e866d7eb0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779026062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2779026062
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3850068573
Short name T607
Test name
Test status
Simulation time 213485571 ps
CPU time 1.54 seconds
Started Jun 04 12:47:28 PM PDT 24
Finished Jun 04 12:47:31 PM PDT 24
Peak memory 208584 kb
Host smart-a95032eb-231f-483e-9f47-d5d344cca26c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850068573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3850068573
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3928732322
Short name T138
Test name
Test status
Simulation time 915081694 ps
CPU time 2.98 seconds
Started Jun 04 12:47:20 PM PDT 24
Finished Jun 04 12:47:25 PM PDT 24
Peak memory 200564 kb
Host smart-98aa1f88-c396-43e2-a926-a7523e71d508
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928732322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3928732322
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3336140098
Short name T65
Test name
Test status
Simulation time 135855754 ps
CPU time 1.13 seconds
Started Jun 04 12:47:44 PM PDT 24
Finished Jun 04 12:47:47 PM PDT 24
Peak memory 208544 kb
Host smart-fed8b7bf-e05f-4de4-b510-fae264793539
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336140098 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3336140098
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1547019413
Short name T548
Test name
Test status
Simulation time 80399372 ps
CPU time 0.89 seconds
Started Jun 04 12:47:44 PM PDT 24
Finished Jun 04 12:47:47 PM PDT 24
Peak memory 200332 kb
Host smart-96f3ac0d-ac35-4f30-92c2-74a1fc14b351
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547019413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.1547019413
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1705725430
Short name T129
Test name
Test status
Simulation time 225316580 ps
CPU time 1.49 seconds
Started Jun 04 12:47:42 PM PDT 24
Finished Jun 04 12:47:45 PM PDT 24
Peak memory 200480 kb
Host smart-61500323-5d1c-4590-a813-00f73c1463e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705725430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1705725430
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.118245186
Short name T588
Test name
Test status
Simulation time 200158426 ps
CPU time 3.05 seconds
Started Jun 04 12:47:27 PM PDT 24
Finished Jun 04 12:47:31 PM PDT 24
Peak memory 211252 kb
Host smart-4c2d8b6c-1fad-4a77-b66c-b62bcf3b1644
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118245186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.118245186
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4193149006
Short name T108
Test name
Test status
Simulation time 443410766 ps
CPU time 1.83 seconds
Started Jun 04 12:47:23 PM PDT 24
Finished Jun 04 12:47:26 PM PDT 24
Peak memory 200624 kb
Host smart-2af3981c-5667-410d-850c-a6cab27a338a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193149006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.4193149006
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.58519144
Short name T585
Test name
Test status
Simulation time 200454027 ps
CPU time 1.97 seconds
Started Jun 04 12:47:26 PM PDT 24
Finished Jun 04 12:47:29 PM PDT 24
Peak memory 208908 kb
Host smart-5ef6d998-8637-4918-9b25-a03373efc350
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58519144 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.58519144
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1617405480
Short name T131
Test name
Test status
Simulation time 68323890 ps
CPU time 0.8 seconds
Started Jun 04 12:47:27 PM PDT 24
Finished Jun 04 12:47:30 PM PDT 24
Peak memory 200268 kb
Host smart-be0040d9-a41e-4a23-b209-63a5d96ece4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617405480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1617405480
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.378525794
Short name T613
Test name
Test status
Simulation time 259158078 ps
CPU time 1.56 seconds
Started Jun 04 12:47:50 PM PDT 24
Finished Jun 04 12:47:54 PM PDT 24
Peak memory 200456 kb
Host smart-60f44f05-89de-425e-9354-9fcc1dbff671
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378525794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.378525794
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1756159956
Short name T582
Test name
Test status
Simulation time 274322689 ps
CPU time 2.04 seconds
Started Jun 04 12:47:31 PM PDT 24
Finished Jun 04 12:47:34 PM PDT 24
Peak memory 208704 kb
Host smart-ed482e37-8b7b-451c-beed-ec0f254ae8e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756159956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1756159956
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2844603589
Short name T553
Test name
Test status
Simulation time 479785968 ps
CPU time 1.82 seconds
Started Jun 04 12:47:25 PM PDT 24
Finished Jun 04 12:47:28 PM PDT 24
Peak memory 200460 kb
Host smart-05c0a1b6-e733-41d7-b8a6-d68cc6a7cc3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844603589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2844603589
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1468298430
Short name T583
Test name
Test status
Simulation time 174371469 ps
CPU time 1.17 seconds
Started Jun 04 12:47:45 PM PDT 24
Finished Jun 04 12:47:47 PM PDT 24
Peak memory 200444 kb
Host smart-64c2b580-9fc8-4441-8885-706316a1c8ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468298430 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.1468298430
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2742346315
Short name T134
Test name
Test status
Simulation time 75118111 ps
CPU time 0.84 seconds
Started Jun 04 12:47:47 PM PDT 24
Finished Jun 04 12:47:50 PM PDT 24
Peak memory 200256 kb
Host smart-85460520-8ff5-4e89-b599-3b4f238a84eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742346315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2742346315
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2699479319
Short name T602
Test name
Test status
Simulation time 113619844 ps
CPU time 1.08 seconds
Started Jun 04 12:47:28 PM PDT 24
Finished Jun 04 12:47:30 PM PDT 24
Peak memory 200220 kb
Host smart-c88d8f61-2142-44f7-8d6d-ff9543c3cf34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699479319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2699479319
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.4086585343
Short name T139
Test name
Test status
Simulation time 496652044 ps
CPU time 2.05 seconds
Started Jun 04 12:47:47 PM PDT 24
Finished Jun 04 12:47:51 PM PDT 24
Peak memory 200572 kb
Host smart-45b25970-f6f5-4e9c-8d6d-53fef967f6c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086585343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.4086585343
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1755378147
Short name T580
Test name
Test status
Simulation time 117862922 ps
CPU time 1.01 seconds
Started Jun 04 12:47:43 PM PDT 24
Finished Jun 04 12:47:46 PM PDT 24
Peak memory 200208 kb
Host smart-9eccf072-9213-42dc-94f7-cd08299cc7e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755378147 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1755378147
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.4131520130
Short name T545
Test name
Test status
Simulation time 62775503 ps
CPU time 0.82 seconds
Started Jun 04 12:47:33 PM PDT 24
Finished Jun 04 12:47:35 PM PDT 24
Peak memory 200140 kb
Host smart-9b3dc6b8-0391-48b0-b636-24bfa6430f39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131520130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.4131520130
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3185943166
Short name T591
Test name
Test status
Simulation time 79241487 ps
CPU time 0.97 seconds
Started Jun 04 12:47:36 PM PDT 24
Finished Jun 04 12:47:39 PM PDT 24
Peak memory 200316 kb
Host smart-92ed3be6-f797-41bb-bc2c-0af8a2176254
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185943166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3185943166
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1821558827
Short name T70
Test name
Test status
Simulation time 189527162 ps
CPU time 2.79 seconds
Started Jun 04 12:47:46 PM PDT 24
Finished Jun 04 12:47:50 PM PDT 24
Peak memory 208708 kb
Host smart-d2b52cc6-03c6-40b8-8805-ff9c46e0e1d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821558827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1821558827
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1099229073
Short name T146
Test name
Test status
Simulation time 788944037 ps
CPU time 3.05 seconds
Started Jun 04 12:47:49 PM PDT 24
Finished Jun 04 12:47:54 PM PDT 24
Peak memory 200528 kb
Host smart-8ae56c1a-c5ea-48f8-a6ad-a3e5df701224
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099229073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1099229073
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.761810853
Short name T581
Test name
Test status
Simulation time 120831580 ps
CPU time 1.03 seconds
Started Jun 04 12:47:30 PM PDT 24
Finished Jun 04 12:47:33 PM PDT 24
Peak memory 200296 kb
Host smart-c72d8db8-af82-47fd-b3d2-c3f0ddbb9ec0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761810853 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.761810853
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.407402131
Short name T584
Test name
Test status
Simulation time 92232843 ps
CPU time 0.87 seconds
Started Jun 04 12:47:43 PM PDT 24
Finished Jun 04 12:47:45 PM PDT 24
Peak memory 200292 kb
Host smart-5b68f761-0c4c-4d94-8193-10bbdc9b09ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407402131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.407402131
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.389243234
Short name T130
Test name
Test status
Simulation time 256500064 ps
CPU time 1.54 seconds
Started Jun 04 12:47:29 PM PDT 24
Finished Jun 04 12:47:31 PM PDT 24
Peak memory 200552 kb
Host smart-5ba61689-c472-4e47-9d10-465b12d10479
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389243234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.389243234
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2609837412
Short name T611
Test name
Test status
Simulation time 124328051 ps
CPU time 1.71 seconds
Started Jun 04 12:47:28 PM PDT 24
Finished Jun 04 12:47:31 PM PDT 24
Peak memory 208776 kb
Host smart-f26967f5-b9e4-4e15-8409-c17ce5b5a1f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609837412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2609837412
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.695658456
Short name T558
Test name
Test status
Simulation time 107276834 ps
CPU time 1.37 seconds
Started Jun 04 12:47:16 PM PDT 24
Finished Jun 04 12:47:20 PM PDT 24
Peak memory 200468 kb
Host smart-cbf4e9bd-10ce-4712-a9e0-64d0394b9823
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695658456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.695658456
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1923199878
Short name T579
Test name
Test status
Simulation time 805159886 ps
CPU time 4.52 seconds
Started Jun 04 12:47:15 PM PDT 24
Finished Jun 04 12:47:22 PM PDT 24
Peak memory 200420 kb
Host smart-52ebeba6-64be-4e64-9a53-590adcb6ad7f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923199878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
923199878
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1243397910
Short name T614
Test name
Test status
Simulation time 94994930 ps
CPU time 0.87 seconds
Started Jun 04 12:47:16 PM PDT 24
Finished Jun 04 12:47:19 PM PDT 24
Peak memory 200260 kb
Host smart-ba88f67a-4013-4d89-ba29-7f837a7468ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243397910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
243397910
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1918861431
Short name T554
Test name
Test status
Simulation time 175953259 ps
CPU time 1.55 seconds
Started Jun 04 12:47:12 PM PDT 24
Finished Jun 04 12:47:15 PM PDT 24
Peak memory 208748 kb
Host smart-90a9f9f5-1e1c-4628-bcb4-e1423cbf2233
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918861431 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1918861431
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.407784313
Short name T127
Test name
Test status
Simulation time 63779215 ps
CPU time 0.79 seconds
Started Jun 04 12:47:15 PM PDT 24
Finished Jun 04 12:47:18 PM PDT 24
Peak memory 200244 kb
Host smart-b8e58f8c-9cf7-4dd8-b087-42cc1c27d183
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407784313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.407784313
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.270543630
Short name T67
Test name
Test status
Simulation time 87035117 ps
CPU time 0.92 seconds
Started Jun 04 12:47:17 PM PDT 24
Finished Jun 04 12:47:20 PM PDT 24
Peak memory 200256 kb
Host smart-2211ae36-9797-41a8-a682-0054d5264897
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270543630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.270543630
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.853085160
Short name T599
Test name
Test status
Simulation time 179982628 ps
CPU time 2.62 seconds
Started Jun 04 12:47:17 PM PDT 24
Finished Jun 04 12:47:22 PM PDT 24
Peak memory 200456 kb
Host smart-7316c535-fe02-46b8-b7c5-af7d3c88baf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853085160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.853085160
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1611864586
Short name T617
Test name
Test status
Simulation time 114695763 ps
CPU time 1.4 seconds
Started Jun 04 12:47:15 PM PDT 24
Finished Jun 04 12:47:19 PM PDT 24
Peak memory 200460 kb
Host smart-aefb06cc-9003-46ba-9bad-d6e091722681
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611864586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
611864586
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.4112911252
Short name T570
Test name
Test status
Simulation time 1174631562 ps
CPU time 5.59 seconds
Started Jun 04 12:47:15 PM PDT 24
Finished Jun 04 12:47:23 PM PDT 24
Peak memory 200408 kb
Host smart-b8f117e4-287f-4328-bf58-7aa8d1087eea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112911252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.4
112911252
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1129854743
Short name T546
Test name
Test status
Simulation time 91277684 ps
CPU time 0.8 seconds
Started Jun 04 12:47:14 PM PDT 24
Finished Jun 04 12:47:18 PM PDT 24
Peak memory 200252 kb
Host smart-088fba48-24bd-4f88-bd0d-7283140453fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129854743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
129854743
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.260313019
Short name T103
Test name
Test status
Simulation time 101482327 ps
CPU time 1.03 seconds
Started Jun 04 12:47:15 PM PDT 24
Finished Jun 04 12:47:18 PM PDT 24
Peak memory 200524 kb
Host smart-fd47d9c0-7319-4112-a307-54dcd3eec00c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260313019 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.260313019
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1114983928
Short name T560
Test name
Test status
Simulation time 59241381 ps
CPU time 0.8 seconds
Started Jun 04 12:47:16 PM PDT 24
Finished Jun 04 12:47:19 PM PDT 24
Peak memory 200264 kb
Host smart-f012ecc4-2df1-4c16-91c7-b2bcf2350b84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114983928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1114983928
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2055324813
Short name T618
Test name
Test status
Simulation time 228772891 ps
CPU time 1.49 seconds
Started Jun 04 12:47:15 PM PDT 24
Finished Jun 04 12:47:19 PM PDT 24
Peak memory 200432 kb
Host smart-355d8e54-0c93-47db-8085-19c8b640a0b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055324813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2055324813
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2829262581
Short name T565
Test name
Test status
Simulation time 315079490 ps
CPU time 2.45 seconds
Started Jun 04 12:47:16 PM PDT 24
Finished Jun 04 12:47:21 PM PDT 24
Peak memory 208668 kb
Host smart-5dea539c-5db7-411f-af6b-98b667eeea15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829262581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2829262581
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3482059697
Short name T587
Test name
Test status
Simulation time 442994195 ps
CPU time 1.81 seconds
Started Jun 04 12:47:15 PM PDT 24
Finished Jun 04 12:47:20 PM PDT 24
Peak memory 200536 kb
Host smart-146c7d1d-2559-400c-b481-c41a67473b7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482059697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3482059697
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1515163973
Short name T619
Test name
Test status
Simulation time 269565860 ps
CPU time 1.8 seconds
Started Jun 04 12:47:43 PM PDT 24
Finished Jun 04 12:47:46 PM PDT 24
Peak memory 200488 kb
Host smart-221ccb06-a77f-42df-9285-b36b54ab2ef6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515163973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
515163973
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1080931325
Short name T569
Test name
Test status
Simulation time 806245256 ps
CPU time 4.51 seconds
Started Jun 04 12:47:21 PM PDT 24
Finished Jun 04 12:47:27 PM PDT 24
Peak memory 216648 kb
Host smart-87fdd72b-c862-4c22-8f7f-c764814c9c7e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080931325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
080931325
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3267575367
Short name T572
Test name
Test status
Simulation time 103778190 ps
CPU time 0.85 seconds
Started Jun 04 12:47:20 PM PDT 24
Finished Jun 04 12:47:22 PM PDT 24
Peak memory 200148 kb
Host smart-a90572fc-7a53-4d2e-bc24-7c0781dabe5d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267575367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3
267575367
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.447162581
Short name T566
Test name
Test status
Simulation time 147533869 ps
CPU time 1.29 seconds
Started Jun 04 12:47:45 PM PDT 24
Finished Jun 04 12:47:47 PM PDT 24
Peak memory 208644 kb
Host smart-37b97219-9390-4a5b-b540-5694e9e48a02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447162581 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.447162581
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1472658774
Short name T589
Test name
Test status
Simulation time 74692963 ps
CPU time 0.82 seconds
Started Jun 04 12:47:27 PM PDT 24
Finished Jun 04 12:47:30 PM PDT 24
Peak memory 200352 kb
Host smart-2f533faf-6b52-4fc1-a47a-ca2ba5c747b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472658774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1472658774
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.794283094
Short name T68
Test name
Test status
Simulation time 137315199 ps
CPU time 1.15 seconds
Started Jun 04 12:47:38 PM PDT 24
Finished Jun 04 12:47:40 PM PDT 24
Peak memory 200248 kb
Host smart-2b7f88b5-6e4e-4245-a357-18b2d7822279
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794283094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.794283094
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.4274467465
Short name T555
Test name
Test status
Simulation time 120788628 ps
CPU time 1.74 seconds
Started Jun 04 12:47:44 PM PDT 24
Finished Jun 04 12:47:47 PM PDT 24
Peak memory 208608 kb
Host smart-bcc6dac3-1b36-4cdf-9e1a-13ee334788a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274467465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.4274467465
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.916624601
Short name T102
Test name
Test status
Simulation time 942626361 ps
CPU time 3.18 seconds
Started Jun 04 12:47:23 PM PDT 24
Finished Jun 04 12:47:27 PM PDT 24
Peak memory 200492 kb
Host smart-0e85558b-f1d0-4a33-9276-2b6a136ff404
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916624601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
916624601
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1723850191
Short name T616
Test name
Test status
Simulation time 117153743 ps
CPU time 1.26 seconds
Started Jun 04 12:47:36 PM PDT 24
Finished Jun 04 12:47:39 PM PDT 24
Peak memory 208580 kb
Host smart-ac21115f-b5dd-41ed-9ef4-eae7ddd614b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723850191 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1723850191
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1044369078
Short name T128
Test name
Test status
Simulation time 65444822 ps
CPU time 0.82 seconds
Started Jun 04 12:47:29 PM PDT 24
Finished Jun 04 12:47:36 PM PDT 24
Peak memory 200176 kb
Host smart-26e54474-0b26-480e-b27e-be9fc997d228
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044369078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1044369078
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3226055340
Short name T574
Test name
Test status
Simulation time 112232196 ps
CPU time 0.98 seconds
Started Jun 04 12:47:25 PM PDT 24
Finished Jun 04 12:47:27 PM PDT 24
Peak memory 200336 kb
Host smart-bc610ec6-4163-4526-9066-f410e7baaa81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226055340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3226055340
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1785606235
Short name T137
Test name
Test status
Simulation time 572833012 ps
CPU time 3.95 seconds
Started Jun 04 12:47:24 PM PDT 24
Finished Jun 04 12:47:29 PM PDT 24
Peak memory 208684 kb
Host smart-2cb2d3de-9828-4498-a07d-ddad885f0140
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785606235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1785606235
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1564186077
Short name T136
Test name
Test status
Simulation time 797454313 ps
CPU time 3.15 seconds
Started Jun 04 12:47:22 PM PDT 24
Finished Jun 04 12:47:26 PM PDT 24
Peak memory 200444 kb
Host smart-58b1f140-53b2-43ab-a088-2682cc46fe08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564186077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1564186077
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1688411320
Short name T561
Test name
Test status
Simulation time 192116425 ps
CPU time 1.19 seconds
Started Jun 04 12:47:46 PM PDT 24
Finished Jun 04 12:47:49 PM PDT 24
Peak memory 200464 kb
Host smart-79a16379-08ec-4f8d-8efa-72137db4450d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688411320 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1688411320
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2682476110
Short name T557
Test name
Test status
Simulation time 70609976 ps
CPU time 0.83 seconds
Started Jun 04 12:47:21 PM PDT 24
Finished Jun 04 12:47:23 PM PDT 24
Peak memory 200352 kb
Host smart-1367cc0b-3806-437f-8e1b-e17897f80e96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682476110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2682476110
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.35966644
Short name T586
Test name
Test status
Simulation time 284611297 ps
CPU time 1.65 seconds
Started Jun 04 12:47:33 PM PDT 24
Finished Jun 04 12:47:35 PM PDT 24
Peak memory 200568 kb
Host smart-06bb1ec3-a495-4691-ae1f-8f84cd5847c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35966644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_same
_csr_outstanding.35966644
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2983301628
Short name T106
Test name
Test status
Simulation time 193240663 ps
CPU time 2.65 seconds
Started Jun 04 12:47:43 PM PDT 24
Finished Jun 04 12:47:47 PM PDT 24
Peak memory 208696 kb
Host smart-5aaa8a8e-594f-4162-a1ec-3dd68dfdc535
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983301628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2983301628
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.4120550330
Short name T140
Test name
Test status
Simulation time 891000884 ps
CPU time 2.89 seconds
Started Jun 04 12:47:31 PM PDT 24
Finished Jun 04 12:47:35 PM PDT 24
Peak memory 200552 kb
Host smart-5e3f040f-3eca-47e4-a395-7e1528eefcaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120550330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.4120550330
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3893321908
Short name T556
Test name
Test status
Simulation time 116605560 ps
CPU time 1.07 seconds
Started Jun 04 12:47:45 PM PDT 24
Finished Jun 04 12:47:47 PM PDT 24
Peak memory 200352 kb
Host smart-dafd2604-580a-46a0-9f98-593e2c72c958
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893321908 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3893321908
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1132474256
Short name T578
Test name
Test status
Simulation time 75615544 ps
CPU time 0.86 seconds
Started Jun 04 12:47:39 PM PDT 24
Finished Jun 04 12:47:40 PM PDT 24
Peak memory 200200 kb
Host smart-dd29fa93-c0ff-45ab-961d-046955cf9644
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132474256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1132474256
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.589015511
Short name T592
Test name
Test status
Simulation time 132941752 ps
CPU time 1.08 seconds
Started Jun 04 12:47:27 PM PDT 24
Finished Jun 04 12:47:29 PM PDT 24
Peak memory 200408 kb
Host smart-aca1fb4f-b3c1-4ddb-91f1-e5e0f8dca6c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589015511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sam
e_csr_outstanding.589015511
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3820046362
Short name T598
Test name
Test status
Simulation time 296652814 ps
CPU time 2.43 seconds
Started Jun 04 12:47:21 PM PDT 24
Finished Jun 04 12:47:25 PM PDT 24
Peak memory 208744 kb
Host smart-33712242-4641-41ae-8213-8b567fc5eb91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820046362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3820046362
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.647618011
Short name T147
Test name
Test status
Simulation time 458704070 ps
CPU time 2.07 seconds
Started Jun 04 12:47:47 PM PDT 24
Finished Jun 04 12:47:51 PM PDT 24
Peak memory 200664 kb
Host smart-fe5a4a93-b9bf-403b-8eaf-225c4a61e320
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647618011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
647618011
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2647109755
Short name T105
Test name
Test status
Simulation time 120038137 ps
CPU time 1.1 seconds
Started Jun 04 12:47:24 PM PDT 24
Finished Jun 04 12:47:26 PM PDT 24
Peak memory 208568 kb
Host smart-b000c0d9-5496-4907-89c9-ed6a6f27a134
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647109755 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2647109755
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3575563721
Short name T559
Test name
Test status
Simulation time 68451004 ps
CPU time 0.84 seconds
Started Jun 04 12:47:28 PM PDT 24
Finished Jun 04 12:47:30 PM PDT 24
Peak memory 200152 kb
Host smart-230b7eb9-0bae-47ed-b100-10375471368d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575563721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3575563721
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2553144211
Short name T595
Test name
Test status
Simulation time 87111732 ps
CPU time 0.95 seconds
Started Jun 04 12:47:26 PM PDT 24
Finished Jun 04 12:47:28 PM PDT 24
Peak memory 200284 kb
Host smart-458b1792-aa28-4b11-af8b-4ece598abc4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553144211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.2553144211
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2663434577
Short name T571
Test name
Test status
Simulation time 436453934 ps
CPU time 3.01 seconds
Started Jun 04 12:47:37 PM PDT 24
Finished Jun 04 12:47:41 PM PDT 24
Peak memory 216616 kb
Host smart-fe4c2380-40a7-4fb0-a21a-3dc74d400f84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663434577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2663434577
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3325588035
Short name T551
Test name
Test status
Simulation time 500627008 ps
CPU time 2.1 seconds
Started Jun 04 12:47:21 PM PDT 24
Finished Jun 04 12:47:25 PM PDT 24
Peak memory 200572 kb
Host smart-071aca42-a6f4-4b6f-a3b5-56ca8abc033b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325588035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3325588035
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1739528447
Short name T100
Test name
Test status
Simulation time 125659657 ps
CPU time 0.98 seconds
Started Jun 04 12:47:28 PM PDT 24
Finished Jun 04 12:47:30 PM PDT 24
Peak memory 200320 kb
Host smart-5a98465f-b0a4-44f7-ba36-870414b496b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739528447 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1739528447
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1111205281
Short name T63
Test name
Test status
Simulation time 88438227 ps
CPU time 0.87 seconds
Started Jun 04 12:47:49 PM PDT 24
Finished Jun 04 12:47:52 PM PDT 24
Peak memory 200340 kb
Host smart-d59616bc-c47b-4b85-b3e0-16ac9416c62e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111205281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1111205281
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.86591102
Short name T593
Test name
Test status
Simulation time 209332267 ps
CPU time 1.42 seconds
Started Jun 04 12:47:25 PM PDT 24
Finished Jun 04 12:47:27 PM PDT 24
Peak memory 200504 kb
Host smart-38b93c86-5409-4cfc-bcc5-9efca863af11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86591102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_same
_csr_outstanding.86591102
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.315162238
Short name T605
Test name
Test status
Simulation time 128291190 ps
CPU time 1.8 seconds
Started Jun 04 12:47:22 PM PDT 24
Finished Jun 04 12:47:24 PM PDT 24
Peak memory 211616 kb
Host smart-e061f87c-aeee-4ba1-9cde-ab111de59d05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315162238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.315162238
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2502426834
Short name T576
Test name
Test status
Simulation time 457822266 ps
CPU time 1.91 seconds
Started Jun 04 12:47:28 PM PDT 24
Finished Jun 04 12:47:31 PM PDT 24
Peak memory 200404 kb
Host smart-26ea3fc0-c4a5-44c3-9607-13bab0212407
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502426834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.2502426834
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.1109265742
Short name T41
Test name
Test status
Simulation time 65402673 ps
CPU time 0.78 seconds
Started Jun 04 12:54:07 PM PDT 24
Finished Jun 04 12:54:09 PM PDT 24
Peak memory 200700 kb
Host smart-6b9c5af5-8360-4634-b6bf-9490f8f76c8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109265742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1109265742
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2651975273
Short name T348
Test name
Test status
Simulation time 2338715315 ps
CPU time 7.87 seconds
Started Jun 04 12:54:01 PM PDT 24
Finished Jun 04 12:54:10 PM PDT 24
Peak memory 222692 kb
Host smart-3c6cce7f-a9bc-4a51-8567-50fbe6989686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651975273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2651975273
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2271074782
Short name T218
Test name
Test status
Simulation time 244069879 ps
CPU time 1.11 seconds
Started Jun 04 12:54:00 PM PDT 24
Finished Jun 04 12:54:02 PM PDT 24
Peak memory 217964 kb
Host smart-7a7bd123-40f9-4ad0-9b5d-7cca786262b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271074782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2271074782
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.2369998279
Short name T174
Test name
Test status
Simulation time 147398134 ps
CPU time 0.83 seconds
Started Jun 04 12:53:55 PM PDT 24
Finished Jun 04 12:53:56 PM PDT 24
Peak memory 200604 kb
Host smart-8cb64b57-de14-40dd-a4b6-1d15e49bd7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369998279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2369998279
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.2417422172
Short name T249
Test name
Test status
Simulation time 882287659 ps
CPU time 4.3 seconds
Started Jun 04 12:53:54 PM PDT 24
Finished Jun 04 12:53:59 PM PDT 24
Peak memory 201084 kb
Host smart-68639beb-f651-444d-8de5-dbd33e82f7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417422172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2417422172
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2404728416
Short name T165
Test name
Test status
Simulation time 176358796 ps
CPU time 1.13 seconds
Started Jun 04 12:53:59 PM PDT 24
Finished Jun 04 12:54:00 PM PDT 24
Peak memory 200868 kb
Host smart-f70f5b40-9e3d-48e6-8489-a73f1930435d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404728416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2404728416
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.754503823
Short name T339
Test name
Test status
Simulation time 118157046 ps
CPU time 1.16 seconds
Started Jun 04 12:54:00 PM PDT 24
Finished Jun 04 12:54:02 PM PDT 24
Peak memory 201060 kb
Host smart-d20b6b97-9f0b-49f4-ab7e-276b9155f1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754503823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.754503823
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.606966625
Short name T84
Test name
Test status
Simulation time 10076947269 ps
CPU time 34.18 seconds
Started Jun 04 12:54:00 PM PDT 24
Finished Jun 04 12:54:36 PM PDT 24
Peak memory 210008 kb
Host smart-4a4eb7fb-833e-43c8-ad78-63c173ece898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606966625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.606966625
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1673878269
Short name T186
Test name
Test status
Simulation time 372910308 ps
CPU time 2.3 seconds
Started Jun 04 12:54:07 PM PDT 24
Finished Jun 04 12:54:10 PM PDT 24
Peak memory 200852 kb
Host smart-21ed29dd-084a-48b7-b7c7-880dc8b7de06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673878269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1673878269
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2698424287
Short name T160
Test name
Test status
Simulation time 70539667 ps
CPU time 0.82 seconds
Started Jun 04 12:54:08 PM PDT 24
Finished Jun 04 12:54:10 PM PDT 24
Peak memory 200668 kb
Host smart-ba513813-6476-4a83-b53d-a97a6e46c60f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698424287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2698424287
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.975870263
Short name T213
Test name
Test status
Simulation time 1900585411 ps
CPU time 7.11 seconds
Started Jun 04 12:54:00 PM PDT 24
Finished Jun 04 12:54:08 PM PDT 24
Peak memory 222520 kb
Host smart-a023feb2-8522-4d96-803d-dda718957b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975870263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.975870263
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2311633089
Short name T179
Test name
Test status
Simulation time 243957506 ps
CPU time 1.08 seconds
Started Jun 04 12:53:59 PM PDT 24
Finished Jun 04 12:54:01 PM PDT 24
Peak memory 217976 kb
Host smart-22befad3-107c-4efd-ae49-c34a07fdfa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311633089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2311633089
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.1187351961
Short name T484
Test name
Test status
Simulation time 201939951 ps
CPU time 0.89 seconds
Started Jun 04 12:53:59 PM PDT 24
Finished Jun 04 12:54:01 PM PDT 24
Peak memory 200552 kb
Host smart-f7ead3c2-b95b-4bcc-9fbe-3a252ceeaa38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187351961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.1187351961
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3269771914
Short name T450
Test name
Test status
Simulation time 1259909493 ps
CPU time 4.92 seconds
Started Jun 04 12:54:08 PM PDT 24
Finished Jun 04 12:54:14 PM PDT 24
Peak memory 201008 kb
Host smart-33d7d438-05c2-4d76-9c1e-82c256ebc778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269771914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3269771914
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3875201748
Short name T78
Test name
Test status
Simulation time 16794324388 ps
CPU time 25.48 seconds
Started Jun 04 12:53:56 PM PDT 24
Finished Jun 04 12:54:22 PM PDT 24
Peak memory 218676 kb
Host smart-a8bc2893-6bfb-4281-be54-f9fe7ac3c4ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875201748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3875201748
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2335957137
Short name T429
Test name
Test status
Simulation time 181106751 ps
CPU time 1.22 seconds
Started Jun 04 12:53:51 PM PDT 24
Finished Jun 04 12:53:52 PM PDT 24
Peak memory 200844 kb
Host smart-e83fef54-fb70-4839-88f0-9d589cf997c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335957137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2335957137
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.2947171472
Short name T461
Test name
Test status
Simulation time 109773961 ps
CPU time 1.28 seconds
Started Jun 04 12:53:59 PM PDT 24
Finished Jun 04 12:54:01 PM PDT 24
Peak memory 201044 kb
Host smart-40f62597-d23c-45e4-b476-7678eebb9178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947171472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2947171472
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2622337572
Short name T390
Test name
Test status
Simulation time 1618923738 ps
CPU time 6.96 seconds
Started Jun 04 12:53:59 PM PDT 24
Finished Jun 04 12:54:07 PM PDT 24
Peak memory 201052 kb
Host smart-354724db-638c-4fcb-891f-543771602611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622337572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2622337572
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3311424122
Short name T473
Test name
Test status
Simulation time 520786138 ps
CPU time 2.93 seconds
Started Jun 04 12:53:54 PM PDT 24
Finished Jun 04 12:53:58 PM PDT 24
Peak memory 200756 kb
Host smart-3cdeeca0-3d46-403c-b394-b0e53cfaa01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311424122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3311424122
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2586446024
Short name T244
Test name
Test status
Simulation time 96278428 ps
CPU time 0.86 seconds
Started Jun 04 12:54:00 PM PDT 24
Finished Jun 04 12:54:02 PM PDT 24
Peak memory 200784 kb
Host smart-8235be86-0f06-4235-a756-8e09ea31b42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586446024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2586446024
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.304226054
Short name T477
Test name
Test status
Simulation time 79039409 ps
CPU time 0.76 seconds
Started Jun 04 12:54:17 PM PDT 24
Finished Jun 04 12:54:19 PM PDT 24
Peak memory 200692 kb
Host smart-6d452942-6f23-43a7-9c65-4cd33844a9b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304226054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.304226054
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3088151800
Short name T28
Test name
Test status
Simulation time 1221245214 ps
CPU time 6.04 seconds
Started Jun 04 12:54:12 PM PDT 24
Finished Jun 04 12:54:19 PM PDT 24
Peak memory 217452 kb
Host smart-cc898934-9882-40b5-92c8-d64c3dadccca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088151800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3088151800
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3390146500
Short name T338
Test name
Test status
Simulation time 244281110 ps
CPU time 1.09 seconds
Started Jun 04 12:54:18 PM PDT 24
Finished Jun 04 12:54:21 PM PDT 24
Peak memory 217988 kb
Host smart-01f248b2-4823-4fbb-af88-bad60e829f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390146500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3390146500
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2850088184
Short name T171
Test name
Test status
Simulation time 115997109 ps
CPU time 0.8 seconds
Started Jun 04 12:54:27 PM PDT 24
Finished Jun 04 12:54:34 PM PDT 24
Peak memory 200572 kb
Host smart-9fbd7824-e818-425e-9dbf-b668df782c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850088184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2850088184
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.656252292
Short name T224
Test name
Test status
Simulation time 1015990653 ps
CPU time 4.7 seconds
Started Jun 04 12:54:12 PM PDT 24
Finished Jun 04 12:54:18 PM PDT 24
Peak memory 200948 kb
Host smart-c16c0d13-6d42-46bd-81c1-0ecc2f8b5684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656252292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.656252292
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1528169119
Short name T365
Test name
Test status
Simulation time 152111592 ps
CPU time 1.12 seconds
Started Jun 04 12:54:18 PM PDT 24
Finished Jun 04 12:54:21 PM PDT 24
Peak memory 200844 kb
Host smart-dbce14c8-6922-4811-af46-f6cd943019bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528169119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1528169119
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.214946380
Short name T313
Test name
Test status
Simulation time 116028573 ps
CPU time 1.28 seconds
Started Jun 04 12:54:10 PM PDT 24
Finished Jun 04 12:54:12 PM PDT 24
Peak memory 201024 kb
Host smart-8251e11e-d154-451b-91c6-c89b4f2bb88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214946380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.214946380
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.4138031995
Short name T283
Test name
Test status
Simulation time 2743133140 ps
CPU time 10.41 seconds
Started Jun 04 12:54:20 PM PDT 24
Finished Jun 04 12:54:33 PM PDT 24
Peak memory 201144 kb
Host smart-e4826d78-a899-45a3-b3b0-5e83e32d34fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138031995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.4138031995
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.4037421951
Short name T233
Test name
Test status
Simulation time 423998770 ps
CPU time 2.22 seconds
Started Jun 04 12:54:13 PM PDT 24
Finished Jun 04 12:54:16 PM PDT 24
Peak memory 208956 kb
Host smart-ea547f42-2e90-44b8-9af6-cac8f77f7ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037421951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.4037421951
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.372721130
Short name T9
Test name
Test status
Simulation time 125697800 ps
CPU time 1 seconds
Started Jun 04 12:54:14 PM PDT 24
Finished Jun 04 12:54:15 PM PDT 24
Peak memory 200844 kb
Host smart-799c4e82-c289-4092-8f60-c7bb283d3d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372721130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.372721130
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2662674744
Short name T155
Test name
Test status
Simulation time 82825363 ps
CPU time 0.79 seconds
Started Jun 04 12:54:25 PM PDT 24
Finished Jun 04 12:54:27 PM PDT 24
Peak memory 200620 kb
Host smart-1064efbe-f5c6-40b0-bb48-de0449ab9cb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662674744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2662674744
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2259631153
Short name T24
Test name
Test status
Simulation time 2178677848 ps
CPU time 7.43 seconds
Started Jun 04 12:54:16 PM PDT 24
Finished Jun 04 12:54:25 PM PDT 24
Peak memory 222452 kb
Host smart-c51e4a3b-d277-448f-8690-0df1a6a8498a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259631153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2259631153
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1524516277
Short name T231
Test name
Test status
Simulation time 244112201 ps
CPU time 1.11 seconds
Started Jun 04 12:54:18 PM PDT 24
Finished Jun 04 12:54:21 PM PDT 24
Peak memory 218168 kb
Host smart-8d61ac66-5f09-4cf3-935c-0b10f5c52be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524516277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1524516277
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.3482336110
Short name T398
Test name
Test status
Simulation time 136397399 ps
CPU time 0.77 seconds
Started Jun 04 12:54:13 PM PDT 24
Finished Jun 04 12:54:14 PM PDT 24
Peak memory 200628 kb
Host smart-9a5a8036-4eae-4709-9cd2-cb864bf80119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482336110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3482336110
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.244618400
Short name T6
Test name
Test status
Simulation time 817786909 ps
CPU time 4.1 seconds
Started Jun 04 12:54:17 PM PDT 24
Finished Jun 04 12:54:22 PM PDT 24
Peak memory 201036 kb
Host smart-9d47ea28-90ff-4d23-a75a-4f4ea0d72bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244618400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.244618400
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3049055217
Short name T423
Test name
Test status
Simulation time 110996384 ps
CPU time 1.02 seconds
Started Jun 04 12:54:15 PM PDT 24
Finished Jun 04 12:54:17 PM PDT 24
Peak memory 200728 kb
Host smart-e61b4dc2-1367-4210-9c90-6087a4ba503c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049055217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3049055217
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.134111705
Short name T374
Test name
Test status
Simulation time 118657082 ps
CPU time 1.17 seconds
Started Jun 04 12:54:14 PM PDT 24
Finished Jun 04 12:54:16 PM PDT 24
Peak memory 201028 kb
Host smart-cea5a68f-1613-46fc-945d-6dd9d7c1e80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134111705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.134111705
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.760172821
Short name T237
Test name
Test status
Simulation time 2848509446 ps
CPU time 11.21 seconds
Started Jun 04 12:54:19 PM PDT 24
Finished Jun 04 12:54:33 PM PDT 24
Peak memory 209364 kb
Host smart-7b4db60c-7a90-49c4-977b-d43d98073ccd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760172821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.760172821
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.3185597535
Short name T264
Test name
Test status
Simulation time 368828085 ps
CPU time 2.39 seconds
Started Jun 04 12:54:17 PM PDT 24
Finished Jun 04 12:54:20 PM PDT 24
Peak memory 200828 kb
Host smart-1cecfb07-e649-44e4-b0d0-1f5f643df420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185597535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3185597535
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3411840695
Short name T474
Test name
Test status
Simulation time 160497365 ps
CPU time 1.29 seconds
Started Jun 04 12:54:21 PM PDT 24
Finished Jun 04 12:54:24 PM PDT 24
Peak memory 201032 kb
Host smart-1db9d5b3-9425-43ce-a47b-0a6b01ac2a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411840695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3411840695
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.412780848
Short name T189
Test name
Test status
Simulation time 66537856 ps
CPU time 0.83 seconds
Started Jun 04 12:54:20 PM PDT 24
Finished Jun 04 12:54:23 PM PDT 24
Peak memory 200628 kb
Host smart-3f4a2dd6-c368-4834-ae04-1a6b66a732b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412780848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.412780848
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.897757323
Short name T284
Test name
Test status
Simulation time 2355343765 ps
CPU time 9.03 seconds
Started Jun 04 12:54:25 PM PDT 24
Finished Jun 04 12:54:35 PM PDT 24
Peak memory 222684 kb
Host smart-ed0871e1-c05e-4a7e-8c6f-be23b2e73951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897757323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.897757323
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.4237158695
Short name T336
Test name
Test status
Simulation time 243584245 ps
CPU time 1.18 seconds
Started Jun 04 12:54:19 PM PDT 24
Finished Jun 04 12:54:22 PM PDT 24
Peak memory 217896 kb
Host smart-85dc1560-a799-4016-a274-cbe2788b9632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237158695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.4237158695
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3772568115
Short name T541
Test name
Test status
Simulation time 115373608 ps
CPU time 0.77 seconds
Started Jun 04 12:54:20 PM PDT 24
Finished Jun 04 12:54:23 PM PDT 24
Peak memory 200668 kb
Host smart-79e62e94-b381-4aad-88cf-56a63198109d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772568115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3772568115
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2027396879
Short name T521
Test name
Test status
Simulation time 1895541037 ps
CPU time 7.71 seconds
Started Jun 04 12:54:15 PM PDT 24
Finished Jun 04 12:54:24 PM PDT 24
Peak memory 200948 kb
Host smart-862ed4ca-31a5-4862-ad22-6c41e0f79132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027396879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2027396879
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1070841384
Short name T204
Test name
Test status
Simulation time 142648132 ps
CPU time 1.1 seconds
Started Jun 04 12:54:18 PM PDT 24
Finished Jun 04 12:54:20 PM PDT 24
Peak memory 200832 kb
Host smart-52a0a12f-7f2f-4c92-ab8f-fbb7f65c18c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070841384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1070841384
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3362921374
Short name T377
Test name
Test status
Simulation time 118904187 ps
CPU time 1.17 seconds
Started Jun 04 12:54:20 PM PDT 24
Finished Jun 04 12:54:23 PM PDT 24
Peak memory 201016 kb
Host smart-ee4f14a2-862e-4f6a-a9fa-5ff3576c243a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362921374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3362921374
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.26045701
Short name T334
Test name
Test status
Simulation time 1381416213 ps
CPU time 6.67 seconds
Started Jun 04 12:54:23 PM PDT 24
Finished Jun 04 12:54:31 PM PDT 24
Peak memory 209280 kb
Host smart-3ef0405c-cf22-49fe-b141-09489affff29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26045701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.26045701
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1590877988
Short name T240
Test name
Test status
Simulation time 337571627 ps
CPU time 1.98 seconds
Started Jun 04 12:54:25 PM PDT 24
Finished Jun 04 12:54:28 PM PDT 24
Peak memory 200768 kb
Host smart-f7b96ed0-34f1-4ba3-bf3a-4ddea3d43ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590877988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1590877988
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.777261765
Short name T364
Test name
Test status
Simulation time 70077267 ps
CPU time 0.81 seconds
Started Jun 04 12:54:22 PM PDT 24
Finished Jun 04 12:54:25 PM PDT 24
Peak memory 200696 kb
Host smart-0f544985-ef11-4c4b-9e33-177722ff1660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777261765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.777261765
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1888934834
Short name T55
Test name
Test status
Simulation time 72366799 ps
CPU time 0.76 seconds
Started Jun 04 12:54:23 PM PDT 24
Finished Jun 04 12:54:25 PM PDT 24
Peak memory 200664 kb
Host smart-e6f3cfd6-bd7f-4d4d-8dbb-b2352149231f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888934834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1888934834
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2800639286
Short name T343
Test name
Test status
Simulation time 1229422580 ps
CPU time 6.09 seconds
Started Jun 04 12:54:19 PM PDT 24
Finished Jun 04 12:54:27 PM PDT 24
Peak memory 218056 kb
Host smart-a8a24645-8f62-4a6a-89cf-93a35734d026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800639286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2800639286
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.625074099
Short name T437
Test name
Test status
Simulation time 244777427 ps
CPU time 1.08 seconds
Started Jun 04 12:54:23 PM PDT 24
Finished Jun 04 12:54:31 PM PDT 24
Peak memory 217880 kb
Host smart-fab6b547-4efb-4f99-b647-36ec43845a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625074099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.625074099
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3061395034
Short name T404
Test name
Test status
Simulation time 155157853 ps
CPU time 0.88 seconds
Started Jun 04 12:54:19 PM PDT 24
Finished Jun 04 12:54:23 PM PDT 24
Peak memory 200636 kb
Host smart-61131f7c-989b-453c-906f-dd2b717c467f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061395034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3061395034
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.550103870
Short name T110
Test name
Test status
Simulation time 1585286008 ps
CPU time 5.95 seconds
Started Jun 04 12:54:20 PM PDT 24
Finished Jun 04 12:54:28 PM PDT 24
Peak memory 201024 kb
Host smart-0ec0ead1-0d88-4899-8b41-b9f677f754d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550103870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.550103870
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.968800228
Short name T158
Test name
Test status
Simulation time 188243324 ps
CPU time 1.17 seconds
Started Jun 04 12:54:23 PM PDT 24
Finished Jun 04 12:54:25 PM PDT 24
Peak memory 200896 kb
Host smart-985fc910-a044-42fb-a661-661fa180c9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968800228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.968800228
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.964690540
Short name T37
Test name
Test status
Simulation time 108403489 ps
CPU time 1.14 seconds
Started Jun 04 12:54:22 PM PDT 24
Finished Jun 04 12:54:25 PM PDT 24
Peak memory 200948 kb
Host smart-63bf063b-c6b7-42fa-b5e5-215055d285cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964690540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.964690540
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.1430311160
Short name T239
Test name
Test status
Simulation time 352530903 ps
CPU time 1.87 seconds
Started Jun 04 12:54:21 PM PDT 24
Finished Jun 04 12:54:25 PM PDT 24
Peak memory 200828 kb
Host smart-c3ae4853-4e3b-435c-b8ed-a818ad74212b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430311160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1430311160
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.508910981
Short name T502
Test name
Test status
Simulation time 130708436 ps
CPU time 1.03 seconds
Started Jun 04 12:54:18 PM PDT 24
Finished Jun 04 12:54:20 PM PDT 24
Peak memory 200752 kb
Host smart-def3c933-81b7-437f-b60f-20bea588ec04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508910981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.508910981
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3303370721
Short name T215
Test name
Test status
Simulation time 81445134 ps
CPU time 0.81 seconds
Started Jun 04 12:54:19 PM PDT 24
Finished Jun 04 12:54:21 PM PDT 24
Peak memory 200668 kb
Host smart-d13f74f7-3339-428f-a32a-4cdb4755109c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303370721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3303370721
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2552228037
Short name T87
Test name
Test status
Simulation time 2339517209 ps
CPU time 8.03 seconds
Started Jun 04 12:54:21 PM PDT 24
Finished Jun 04 12:54:31 PM PDT 24
Peak memory 222584 kb
Host smart-85289121-5ba7-4d71-bb05-e8b536586480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552228037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2552228037
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3050387769
Short name T407
Test name
Test status
Simulation time 243790438 ps
CPU time 1.06 seconds
Started Jun 04 12:54:18 PM PDT 24
Finished Jun 04 12:54:21 PM PDT 24
Peak memory 218176 kb
Host smart-66905b86-f462-4d77-a6b2-d9a9ac1572aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050387769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3050387769
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.980035835
Short name T453
Test name
Test status
Simulation time 142530693 ps
CPU time 0.8 seconds
Started Jun 04 12:54:18 PM PDT 24
Finished Jun 04 12:54:20 PM PDT 24
Peak memory 200616 kb
Host smart-9dbc747b-1bce-48e6-995e-7eeb02ee2d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980035835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.980035835
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.107450616
Short name T278
Test name
Test status
Simulation time 1352917856 ps
CPU time 5.62 seconds
Started Jun 04 12:54:19 PM PDT 24
Finished Jun 04 12:54:27 PM PDT 24
Peak memory 200940 kb
Host smart-bead0941-e53c-486b-b663-a9cede5b3563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107450616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.107450616
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.1719866059
Short name T299
Test name
Test status
Simulation time 202996957 ps
CPU time 1.36 seconds
Started Jun 04 12:54:24 PM PDT 24
Finished Jun 04 12:54:27 PM PDT 24
Peak memory 201028 kb
Host smart-b8cdf980-44a1-4b0d-948b-406ef98f8245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719866059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.1719866059
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1011578153
Short name T351
Test name
Test status
Simulation time 2455257838 ps
CPU time 9 seconds
Started Jun 04 12:54:20 PM PDT 24
Finished Jun 04 12:54:31 PM PDT 24
Peak memory 210324 kb
Host smart-01a02af6-7d6e-429d-9c16-2401d815bcbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011578153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1011578153
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3390430109
Short name T530
Test name
Test status
Simulation time 279774033 ps
CPU time 2.08 seconds
Started Jun 04 12:54:20 PM PDT 24
Finished Jun 04 12:54:25 PM PDT 24
Peak memory 200752 kb
Host smart-49df3fee-139c-427a-9366-d68f1729d15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390430109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3390430109
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1092055642
Short name T331
Test name
Test status
Simulation time 180404419 ps
CPU time 1.16 seconds
Started Jun 04 12:54:20 PM PDT 24
Finished Jun 04 12:54:23 PM PDT 24
Peak memory 200792 kb
Host smart-37b1f191-9e41-45c3-9639-38269c14f6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092055642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1092055642
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2388785623
Short name T250
Test name
Test status
Simulation time 70825027 ps
CPU time 0.8 seconds
Started Jun 04 12:54:19 PM PDT 24
Finished Jun 04 12:54:22 PM PDT 24
Peak memory 200656 kb
Host smart-e72f848b-965e-4bff-b588-46d198add76c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388785623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2388785623
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.834067962
Short name T38
Test name
Test status
Simulation time 1905292767 ps
CPU time 7.39 seconds
Started Jun 04 12:54:19 PM PDT 24
Finished Jun 04 12:54:29 PM PDT 24
Peak memory 218504 kb
Host smart-44a8d167-052f-42de-91a7-5055bc69aa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834067962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.834067962
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3175605179
Short name T485
Test name
Test status
Simulation time 244525621 ps
CPU time 1.15 seconds
Started Jun 04 12:54:19 PM PDT 24
Finished Jun 04 12:54:22 PM PDT 24
Peak memory 217956 kb
Host smart-5e919f41-2021-4cab-882e-e42c18cd3ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175605179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3175605179
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.592290973
Short name T403
Test name
Test status
Simulation time 95398410 ps
CPU time 0.85 seconds
Started Jun 04 12:54:16 PM PDT 24
Finished Jun 04 12:54:18 PM PDT 24
Peak memory 200560 kb
Host smart-593a06f3-3a5c-49e7-a058-71baf2fc743c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592290973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.592290973
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3584498863
Short name T23
Test name
Test status
Simulation time 1896590486 ps
CPU time 6.84 seconds
Started Jun 04 12:54:20 PM PDT 24
Finished Jun 04 12:54:29 PM PDT 24
Peak memory 201168 kb
Host smart-aa4eb37f-dff0-4ce8-80c7-74fa12e8b40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584498863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3584498863
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2533941067
Short name T83
Test name
Test status
Simulation time 112706584 ps
CPU time 1.05 seconds
Started Jun 04 12:54:20 PM PDT 24
Finished Jun 04 12:54:23 PM PDT 24
Peak memory 200736 kb
Host smart-c3bad166-5833-4c35-acec-a5044fb3c6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533941067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2533941067
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.2603794330
Short name T94
Test name
Test status
Simulation time 200747027 ps
CPU time 1.43 seconds
Started Jun 04 12:54:26 PM PDT 24
Finished Jun 04 12:54:28 PM PDT 24
Peak memory 201032 kb
Host smart-9403a105-7e72-4f1a-aef2-83a472166901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603794330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.2603794330
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2077115692
Short name T326
Test name
Test status
Simulation time 572246509 ps
CPU time 2.68 seconds
Started Jun 04 12:54:18 PM PDT 24
Finished Jun 04 12:54:22 PM PDT 24
Peak memory 200936 kb
Host smart-7ac488e8-ae16-471e-a0dd-854f1d2ddf83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077115692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2077115692
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2173632882
Short name T522
Test name
Test status
Simulation time 338195892 ps
CPU time 2 seconds
Started Jun 04 12:54:23 PM PDT 24
Finished Jun 04 12:54:26 PM PDT 24
Peak memory 200776 kb
Host smart-f4a7c189-37a5-4b71-8ab9-134375d9bada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173632882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2173632882
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.962869876
Short name T472
Test name
Test status
Simulation time 66661182 ps
CPU time 0.73 seconds
Started Jun 04 12:54:26 PM PDT 24
Finished Jun 04 12:54:28 PM PDT 24
Peak memory 200844 kb
Host smart-f4f1ed06-368d-47e7-a5ea-91432e4f19b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962869876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.962869876
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1966596854
Short name T192
Test name
Test status
Simulation time 62771998 ps
CPU time 0.74 seconds
Started Jun 04 12:54:16 PM PDT 24
Finished Jun 04 12:54:17 PM PDT 24
Peak memory 200712 kb
Host smart-46c84513-5c3c-449f-bd84-e94500768d83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966596854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1966596854
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2644463129
Short name T538
Test name
Test status
Simulation time 1231371314 ps
CPU time 5.56 seconds
Started Jun 04 12:54:20 PM PDT 24
Finished Jun 04 12:54:28 PM PDT 24
Peak memory 218420 kb
Host smart-c6e2d8fb-b062-45a3-a509-b3be8dc62046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644463129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2644463129
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3572206834
Short name T274
Test name
Test status
Simulation time 246858223 ps
CPU time 1.06 seconds
Started Jun 04 12:54:20 PM PDT 24
Finished Jun 04 12:54:23 PM PDT 24
Peak memory 217972 kb
Host smart-158e0b83-aaeb-44e6-8f4c-dad0f018a025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572206834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3572206834
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1583128929
Short name T269
Test name
Test status
Simulation time 223488155 ps
CPU time 0.93 seconds
Started Jun 04 12:54:16 PM PDT 24
Finished Jun 04 12:54:18 PM PDT 24
Peak memory 200552 kb
Host smart-f64a6f89-c8a4-48e6-9717-74ecc767dc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583128929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1583128929
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.243427665
Short name T279
Test name
Test status
Simulation time 1239290508 ps
CPU time 5.13 seconds
Started Jun 04 12:54:16 PM PDT 24
Finished Jun 04 12:54:22 PM PDT 24
Peak memory 201032 kb
Host smart-a3535d83-c23a-45b2-a1c1-309845898cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243427665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.243427665
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1780916900
Short name T468
Test name
Test status
Simulation time 168164682 ps
CPU time 1.26 seconds
Started Jun 04 12:54:20 PM PDT 24
Finished Jun 04 12:54:23 PM PDT 24
Peak memory 200832 kb
Host smart-8e93ffcc-0e7b-4250-a6d4-e264513bbf44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780916900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1780916900
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1985625750
Short name T498
Test name
Test status
Simulation time 124328995 ps
CPU time 1.23 seconds
Started Jun 04 12:54:18 PM PDT 24
Finished Jun 04 12:54:21 PM PDT 24
Peak memory 201016 kb
Host smart-f5218084-1445-45e2-8187-2caa2a8b7371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985625750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1985625750
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1750386422
Short name T316
Test name
Test status
Simulation time 1466503269 ps
CPU time 6.18 seconds
Started Jun 04 12:54:17 PM PDT 24
Finished Jun 04 12:54:24 PM PDT 24
Peak memory 201048 kb
Host smart-29ab0135-7cbc-4d9d-8a1f-99f03f144d86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750386422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1750386422
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3663389896
Short name T300
Test name
Test status
Simulation time 119152802 ps
CPU time 1.39 seconds
Started Jun 04 12:54:22 PM PDT 24
Finished Jun 04 12:54:25 PM PDT 24
Peak memory 200788 kb
Host smart-d72b8010-95c9-4019-b73b-a0423a94044d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663389896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3663389896
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.4245253100
Short name T238
Test name
Test status
Simulation time 206161624 ps
CPU time 1.19 seconds
Started Jun 04 12:54:24 PM PDT 24
Finished Jun 04 12:54:26 PM PDT 24
Peak memory 200852 kb
Host smart-7158516b-6caf-4371-9512-46ff550de907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245253100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.4245253100
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2758614490
Short name T356
Test name
Test status
Simulation time 91730877 ps
CPU time 0.88 seconds
Started Jun 04 12:54:23 PM PDT 24
Finished Jun 04 12:54:25 PM PDT 24
Peak memory 200540 kb
Host smart-5699078d-5790-48a9-af38-296a6cf0ad72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758614490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2758614490
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.137956699
Short name T417
Test name
Test status
Simulation time 1225633866 ps
CPU time 5.46 seconds
Started Jun 04 12:54:24 PM PDT 24
Finished Jun 04 12:54:30 PM PDT 24
Peak memory 217444 kb
Host smart-58c3e198-de46-4b16-996e-91d45a04574b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137956699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.137956699
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2524411120
Short name T349
Test name
Test status
Simulation time 244249562 ps
CPU time 1.1 seconds
Started Jun 04 12:54:22 PM PDT 24
Finished Jun 04 12:54:25 PM PDT 24
Peak memory 218164 kb
Host smart-7b5abe7b-f003-4894-8f20-ba58afe7273d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524411120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2524411120
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1843609382
Short name T208
Test name
Test status
Simulation time 192576997 ps
CPU time 0.89 seconds
Started Jun 04 12:54:18 PM PDT 24
Finished Jun 04 12:54:20 PM PDT 24
Peak memory 200684 kb
Host smart-e386209e-8184-4c97-9176-993e01fb4f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843609382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1843609382
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1948360985
Short name T121
Test name
Test status
Simulation time 1063949060 ps
CPU time 5.24 seconds
Started Jun 04 12:54:20 PM PDT 24
Finished Jun 04 12:54:28 PM PDT 24
Peak memory 201064 kb
Host smart-aefc19d2-0730-4774-9e14-ea772462a17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948360985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1948360985
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1104518658
Short name T221
Test name
Test status
Simulation time 169942354 ps
CPU time 1.21 seconds
Started Jun 04 12:54:18 PM PDT 24
Finished Jun 04 12:54:21 PM PDT 24
Peak memory 200820 kb
Host smart-7434daca-ec1f-4a9e-a37a-ce5c7cb92c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104518658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1104518658
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.60073224
Short name T500
Test name
Test status
Simulation time 230283475 ps
CPU time 1.43 seconds
Started Jun 04 12:54:17 PM PDT 24
Finished Jun 04 12:54:20 PM PDT 24
Peak memory 201012 kb
Host smart-b8af9e41-f3a7-401b-95cd-aaf152faad75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60073224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.60073224
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3793352754
Short name T318
Test name
Test status
Simulation time 1297422475 ps
CPU time 5.24 seconds
Started Jun 04 12:54:25 PM PDT 24
Finished Jun 04 12:54:32 PM PDT 24
Peak memory 201096 kb
Host smart-120a9a43-e928-471c-8b08-6f5e26d191e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793352754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3793352754
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.395662488
Short name T329
Test name
Test status
Simulation time 136366225 ps
CPU time 1.64 seconds
Started Jun 04 12:54:24 PM PDT 24
Finished Jun 04 12:54:27 PM PDT 24
Peak memory 200820 kb
Host smart-087abaaa-1979-4c04-a7e0-387bb8a67d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395662488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.395662488
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3427860189
Short name T419
Test name
Test status
Simulation time 122358924 ps
CPU time 1.02 seconds
Started Jun 04 12:54:25 PM PDT 24
Finished Jun 04 12:54:27 PM PDT 24
Peak memory 200856 kb
Host smart-917abf07-f89a-4bfc-a5e8-0cb91d2f358e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427860189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3427860189
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2428607061
Short name T345
Test name
Test status
Simulation time 75947395 ps
CPU time 0.86 seconds
Started Jun 04 12:54:18 PM PDT 24
Finished Jun 04 12:54:20 PM PDT 24
Peak memory 200624 kb
Host smart-c56bff48-649d-446a-9b46-e8198b8d6d84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428607061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2428607061
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.1472607107
Short name T42
Test name
Test status
Simulation time 2354506248 ps
CPU time 9.27 seconds
Started Jun 04 12:54:32 PM PDT 24
Finished Jun 04 12:54:42 PM PDT 24
Peak memory 218624 kb
Host smart-498819ee-e15e-464a-8009-1cd044bd3802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472607107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1472607107
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.4180054952
Short name T52
Test name
Test status
Simulation time 244916975 ps
CPU time 1.08 seconds
Started Jun 04 12:54:28 PM PDT 24
Finished Jun 04 12:54:31 PM PDT 24
Peak memory 218160 kb
Host smart-fa814a90-3efc-4b8a-bb3d-08a9317f75cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180054952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.4180054952
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_reset.915814223
Short name T426
Test name
Test status
Simulation time 1765592255 ps
CPU time 7.23 seconds
Started Jun 04 12:54:18 PM PDT 24
Finished Jun 04 12:54:27 PM PDT 24
Peak memory 200920 kb
Host smart-dccfeda0-b784-42fb-9bb8-469f71399d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915814223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.915814223
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2910877239
Short name T386
Test name
Test status
Simulation time 158744862 ps
CPU time 1.1 seconds
Started Jun 04 12:54:25 PM PDT 24
Finished Jun 04 12:54:28 PM PDT 24
Peak memory 200836 kb
Host smart-55105420-a046-4b1b-9591-60ee88758241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910877239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2910877239
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1938246349
Short name T397
Test name
Test status
Simulation time 200734890 ps
CPU time 1.4 seconds
Started Jun 04 12:54:24 PM PDT 24
Finished Jun 04 12:54:27 PM PDT 24
Peak memory 201052 kb
Host smart-87f9d5a7-bc22-4138-8a88-88778053c1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938246349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1938246349
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3276291958
Short name T387
Test name
Test status
Simulation time 18002292257 ps
CPU time 67.4 seconds
Started Jun 04 12:54:20 PM PDT 24
Finished Jun 04 12:55:30 PM PDT 24
Peak memory 209432 kb
Host smart-fafb4438-a192-44ec-878c-b09206e0bfc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276291958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3276291958
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.96769770
Short name T235
Test name
Test status
Simulation time 360665798 ps
CPU time 2.12 seconds
Started Jun 04 12:54:19 PM PDT 24
Finished Jun 04 12:54:24 PM PDT 24
Peak memory 200968 kb
Host smart-678a6a63-6af9-4c0b-ae45-2313a3bf8322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96769770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.96769770
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1498436173
Short name T440
Test name
Test status
Simulation time 167456698 ps
CPU time 1.34 seconds
Started Jun 04 12:54:25 PM PDT 24
Finished Jun 04 12:54:28 PM PDT 24
Peak memory 200816 kb
Host smart-e40b257b-d93d-4464-a0f1-b27dd4d49af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498436173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1498436173
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1312265414
Short name T516
Test name
Test status
Simulation time 65692038 ps
CPU time 0.78 seconds
Started Jun 04 12:54:38 PM PDT 24
Finished Jun 04 12:54:40 PM PDT 24
Peak memory 200688 kb
Host smart-5eeb66e8-e104-4a85-ac83-65fee0eed112
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312265414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1312265414
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.421884724
Short name T86
Test name
Test status
Simulation time 2379128195 ps
CPU time 8.27 seconds
Started Jun 04 12:54:27 PM PDT 24
Finished Jun 04 12:54:37 PM PDT 24
Peak memory 222324 kb
Host smart-047fc865-08d6-4b43-a307-a8d5a2591caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421884724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.421884724
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3765571033
Short name T222
Test name
Test status
Simulation time 243732602 ps
CPU time 1.07 seconds
Started Jun 04 12:54:29 PM PDT 24
Finished Jun 04 12:54:32 PM PDT 24
Peak memory 218056 kb
Host smart-06336f7f-9850-4a54-8927-ac6015a810d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765571033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3765571033
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3509543864
Short name T16
Test name
Test status
Simulation time 84037390 ps
CPU time 0.77 seconds
Started Jun 04 12:54:45 PM PDT 24
Finished Jun 04 12:54:47 PM PDT 24
Peak memory 200660 kb
Host smart-a4b11d2a-31e3-408d-963a-f8747f035d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509543864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3509543864
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.520047902
Short name T445
Test name
Test status
Simulation time 1375206242 ps
CPU time 5.86 seconds
Started Jun 04 12:54:28 PM PDT 24
Finished Jun 04 12:54:35 PM PDT 24
Peak memory 201036 kb
Host smart-7337f14b-a3f7-4ae0-89b9-fd0475fa8678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520047902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.520047902
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2405783117
Short name T261
Test name
Test status
Simulation time 165024663 ps
CPU time 1.2 seconds
Started Jun 04 12:54:30 PM PDT 24
Finished Jun 04 12:54:32 PM PDT 24
Peak memory 200844 kb
Host smart-33eced2e-bbb9-4cb9-a222-07ce70a25d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405783117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2405783117
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.12770603
Short name T95
Test name
Test status
Simulation time 251791155 ps
CPU time 1.48 seconds
Started Jun 04 12:54:22 PM PDT 24
Finished Jun 04 12:54:25 PM PDT 24
Peak memory 201064 kb
Host smart-9ada1f6c-f3ef-4d21-a2e2-a70afbd51f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12770603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.12770603
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.789649710
Short name T517
Test name
Test status
Simulation time 354289584 ps
CPU time 2.06 seconds
Started Jun 04 12:54:26 PM PDT 24
Finished Jun 04 12:54:30 PM PDT 24
Peak memory 200836 kb
Host smart-d0d75be8-4a8e-49f9-89e4-b3d415d092ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789649710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.789649710
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3201447831
Short name T456
Test name
Test status
Simulation time 135939612 ps
CPU time 1.05 seconds
Started Jun 04 12:54:28 PM PDT 24
Finished Jun 04 12:54:31 PM PDT 24
Peak memory 200840 kb
Host smart-60b16230-8ec9-4aed-96a9-a141a19f41f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201447831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3201447831
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2952639531
Short name T384
Test name
Test status
Simulation time 1880754239 ps
CPU time 7.21 seconds
Started Jun 04 12:53:53 PM PDT 24
Finished Jun 04 12:54:01 PM PDT 24
Peak memory 230752 kb
Host smart-32db4810-1b33-4a0e-badc-072f998f48fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952639531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2952639531
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.549713366
Short name T315
Test name
Test status
Simulation time 243872822 ps
CPU time 1.16 seconds
Started Jun 04 12:53:59 PM PDT 24
Finished Jun 04 12:54:01 PM PDT 24
Peak memory 218036 kb
Host smart-0d596741-ae79-45cc-8438-4e4487ae8c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549713366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.549713366
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1619284237
Short name T425
Test name
Test status
Simulation time 191033234 ps
CPU time 0.96 seconds
Started Jun 04 12:53:51 PM PDT 24
Finished Jun 04 12:53:52 PM PDT 24
Peak memory 200540 kb
Host smart-976c9627-d7e0-4fa8-9f16-87ef5faa1f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619284237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1619284237
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3899321868
Short name T362
Test name
Test status
Simulation time 2129378001 ps
CPU time 7.65 seconds
Started Jun 04 12:54:12 PM PDT 24
Finished Jun 04 12:54:21 PM PDT 24
Peak memory 201012 kb
Host smart-5d682175-69b0-45f7-a57d-30c7706d065a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899321868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3899321868
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1037193247
Short name T75
Test name
Test status
Simulation time 8716816559 ps
CPU time 13.58 seconds
Started Jun 04 12:53:59 PM PDT 24
Finished Jun 04 12:54:14 PM PDT 24
Peak memory 217648 kb
Host smart-2e16a9a6-f350-40cb-9101-6f1d66589245
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037193247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1037193247
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2243372365
Short name T448
Test name
Test status
Simulation time 174692173 ps
CPU time 1.22 seconds
Started Jun 04 12:54:06 PM PDT 24
Finished Jun 04 12:54:08 PM PDT 24
Peak memory 200844 kb
Host smart-b08f0b16-6866-4d98-95c7-b695f625051a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243372365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2243372365
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1465959297
Short name T241
Test name
Test status
Simulation time 115332206 ps
CPU time 1.21 seconds
Started Jun 04 12:53:52 PM PDT 24
Finished Jun 04 12:53:54 PM PDT 24
Peak memory 200944 kb
Host smart-ce3f7c52-adde-42a3-90f5-162d5685c323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465959297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1465959297
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.995037973
Short name T290
Test name
Test status
Simulation time 12872631176 ps
CPU time 48.22 seconds
Started Jun 04 12:54:07 PM PDT 24
Finished Jun 04 12:54:56 PM PDT 24
Peak memory 209316 kb
Host smart-a654333f-04d5-4e35-8248-58bcf259b213
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995037973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.995037973
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2308635671
Short name T515
Test name
Test status
Simulation time 155610556 ps
CPU time 1.85 seconds
Started Jun 04 12:54:08 PM PDT 24
Finished Jun 04 12:54:11 PM PDT 24
Peak memory 200816 kb
Host smart-c0a38352-8295-4f94-9bb4-706232ccae84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308635671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2308635671
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.147414778
Short name T199
Test name
Test status
Simulation time 264613137 ps
CPU time 1.51 seconds
Started Jun 04 12:54:06 PM PDT 24
Finished Jun 04 12:54:09 PM PDT 24
Peak memory 201000 kb
Host smart-222ad952-6a7c-4a97-a33a-6d3de8085d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147414778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.147414778
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.402403166
Short name T210
Test name
Test status
Simulation time 69247576 ps
CPU time 0.79 seconds
Started Jun 04 12:54:27 PM PDT 24
Finished Jun 04 12:54:29 PM PDT 24
Peak memory 200632 kb
Host smart-b3562a44-2a38-4bbf-b319-9a4acd53c82e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402403166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.402403166
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.189672107
Short name T359
Test name
Test status
Simulation time 1230003502 ps
CPU time 5.86 seconds
Started Jun 04 12:54:29 PM PDT 24
Finished Jun 04 12:54:36 PM PDT 24
Peak memory 218576 kb
Host smart-8083e963-49d4-45a3-ac57-6aec62eb1bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189672107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.189672107
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.649419557
Short name T529
Test name
Test status
Simulation time 245863019 ps
CPU time 1.03 seconds
Started Jun 04 12:54:26 PM PDT 24
Finished Jun 04 12:54:29 PM PDT 24
Peak memory 217968 kb
Host smart-4cb5ce39-df96-423a-a7b0-ca5433aa5239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649419557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.649419557
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1834526011
Short name T200
Test name
Test status
Simulation time 148916919 ps
CPU time 0.87 seconds
Started Jun 04 12:54:29 PM PDT 24
Finished Jun 04 12:54:31 PM PDT 24
Peak memory 200724 kb
Host smart-7d515cb5-98ea-49a0-bf71-c0f60dfc0dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834526011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1834526011
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.4168799379
Short name T418
Test name
Test status
Simulation time 917034760 ps
CPU time 5.07 seconds
Started Jun 04 12:54:27 PM PDT 24
Finished Jun 04 12:54:34 PM PDT 24
Peak memory 200940 kb
Host smart-f1c9b2f9-8516-4a84-9abf-dafa33b3ea8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168799379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.4168799379
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3680942775
Short name T464
Test name
Test status
Simulation time 158706189 ps
CPU time 1.12 seconds
Started Jun 04 12:54:53 PM PDT 24
Finished Jun 04 12:54:55 PM PDT 24
Peak memory 200840 kb
Host smart-601864b0-e633-4a8c-9f9e-707dcc4b3dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680942775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3680942775
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.285362456
Short name T203
Test name
Test status
Simulation time 122287440 ps
CPU time 1.24 seconds
Started Jun 04 12:54:32 PM PDT 24
Finished Jun 04 12:54:34 PM PDT 24
Peak memory 200980 kb
Host smart-c3427bf0-ae7b-455d-a5ec-d1bc73d9e97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285362456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.285362456
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3327110255
Short name T227
Test name
Test status
Simulation time 7352681499 ps
CPU time 32.98 seconds
Started Jun 04 12:54:26 PM PDT 24
Finished Jun 04 12:55:01 PM PDT 24
Peak memory 209356 kb
Host smart-4a0b02df-533f-4b78-99e8-dc110b0b8b2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327110255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3327110255
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.495439073
Short name T511
Test name
Test status
Simulation time 353120942 ps
CPU time 2.15 seconds
Started Jun 04 12:54:28 PM PDT 24
Finished Jun 04 12:54:31 PM PDT 24
Peak memory 209004 kb
Host smart-e8886936-5afd-49d9-9ad4-43186635ea5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495439073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.495439073
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.706694650
Short name T168
Test name
Test status
Simulation time 68946836 ps
CPU time 0.77 seconds
Started Jun 04 12:54:29 PM PDT 24
Finished Jun 04 12:54:31 PM PDT 24
Peak memory 200824 kb
Host smart-522c4d18-88b0-44db-81c4-9709009498a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706694650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.706694650
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3682270070
Short name T188
Test name
Test status
Simulation time 72539927 ps
CPU time 0.73 seconds
Started Jun 04 12:54:24 PM PDT 24
Finished Jun 04 12:54:27 PM PDT 24
Peak memory 200676 kb
Host smart-0e0c303b-51c6-414f-be3c-6450ed449f68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682270070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3682270070
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3959371748
Short name T354
Test name
Test status
Simulation time 245359294 ps
CPU time 1.05 seconds
Started Jun 04 12:54:28 PM PDT 24
Finished Jun 04 12:54:31 PM PDT 24
Peak memory 218152 kb
Host smart-c9cba764-33b1-4071-826f-30bb6403ff43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959371748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3959371748
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3640333443
Short name T393
Test name
Test status
Simulation time 142195118 ps
CPU time 0.82 seconds
Started Jun 04 12:54:30 PM PDT 24
Finished Jun 04 12:54:32 PM PDT 24
Peak memory 200656 kb
Host smart-52a10e2b-203c-4832-82c1-8f1cbe784003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640333443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3640333443
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.4215237124
Short name T109
Test name
Test status
Simulation time 1802462110 ps
CPU time 6.69 seconds
Started Jun 04 12:54:24 PM PDT 24
Finished Jun 04 12:54:32 PM PDT 24
Peak memory 200992 kb
Host smart-807b138a-4f75-40a1-abb9-1a99d2300245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215237124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.4215237124
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1834551475
Short name T13
Test name
Test status
Simulation time 108480146 ps
CPU time 1.01 seconds
Started Jun 04 12:54:25 PM PDT 24
Finished Jun 04 12:54:27 PM PDT 24
Peak memory 200784 kb
Host smart-f9b1d0c0-17d2-489f-9338-9b8088785bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834551475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1834551475
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.875655474
Short name T175
Test name
Test status
Simulation time 204791444 ps
CPU time 1.37 seconds
Started Jun 04 12:54:26 PM PDT 24
Finished Jun 04 12:54:29 PM PDT 24
Peak memory 201056 kb
Host smart-a475c145-1974-48c0-ba2a-467937631bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875655474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.875655474
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1319644227
Short name T319
Test name
Test status
Simulation time 11196125018 ps
CPU time 39.42 seconds
Started Jun 04 12:54:28 PM PDT 24
Finished Jun 04 12:55:09 PM PDT 24
Peak memory 209364 kb
Host smart-c954322a-2d23-487c-9869-729abbfb921d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319644227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1319644227
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2421591749
Short name T328
Test name
Test status
Simulation time 520413565 ps
CPU time 2.67 seconds
Started Jun 04 12:54:25 PM PDT 24
Finished Jun 04 12:54:29 PM PDT 24
Peak memory 200692 kb
Host smart-ddc17026-258f-4a7e-93ea-d17b4a27939c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421591749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2421591749
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1510824210
Short name T92
Test name
Test status
Simulation time 136360995 ps
CPU time 1.04 seconds
Started Jun 04 12:54:25 PM PDT 24
Finished Jun 04 12:54:28 PM PDT 24
Peak memory 200656 kb
Host smart-56be711c-fd4b-4ade-9207-738b9bb196be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510824210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1510824210
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1384447324
Short name T501
Test name
Test status
Simulation time 76068613 ps
CPU time 0.83 seconds
Started Jun 04 12:54:29 PM PDT 24
Finished Jun 04 12:54:31 PM PDT 24
Peak memory 200684 kb
Host smart-d20b303a-fd3a-4b9f-8d37-544db0e6d23b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384447324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1384447324
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.197693378
Short name T33
Test name
Test status
Simulation time 1226497081 ps
CPU time 5.54 seconds
Started Jun 04 12:54:46 PM PDT 24
Finished Jun 04 12:54:53 PM PDT 24
Peak memory 218348 kb
Host smart-24b96f6a-2a86-4162-b2ad-84074953b1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197693378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.197693378
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.460212373
Short name T212
Test name
Test status
Simulation time 245403659 ps
CPU time 1.05 seconds
Started Jun 04 12:54:28 PM PDT 24
Finished Jun 04 12:54:31 PM PDT 24
Peak memory 217968 kb
Host smart-8c59acec-df9f-4850-a108-2294855b3f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460212373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.460212373
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2022816954
Short name T166
Test name
Test status
Simulation time 182458616 ps
CPU time 0.98 seconds
Started Jun 04 12:54:27 PM PDT 24
Finished Jun 04 12:54:30 PM PDT 24
Peak memory 200572 kb
Host smart-2038a5e2-0a47-47e3-964d-4692eac9a6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022816954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2022816954
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2437984976
Short name T209
Test name
Test status
Simulation time 837376264 ps
CPU time 4.17 seconds
Started Jun 04 12:54:27 PM PDT 24
Finished Jun 04 12:54:33 PM PDT 24
Peak memory 200984 kb
Host smart-ea8df6ac-9711-4add-a9e6-3fc5c15af4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437984976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2437984976
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2538774484
Short name T190
Test name
Test status
Simulation time 143657630 ps
CPU time 1.08 seconds
Started Jun 04 12:54:25 PM PDT 24
Finished Jun 04 12:54:27 PM PDT 24
Peak memory 200792 kb
Host smart-6a69d7d7-495b-4dfa-87f3-ad05b4f70022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538774484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2538774484
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2228266341
Short name T96
Test name
Test status
Simulation time 248866682 ps
CPU time 1.41 seconds
Started Jun 04 12:54:26 PM PDT 24
Finished Jun 04 12:54:29 PM PDT 24
Peak memory 201072 kb
Host smart-2d2504cb-5ccf-4d60-8444-8422761f8019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228266341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2228266341
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2275992156
Short name T373
Test name
Test status
Simulation time 264532973 ps
CPU time 1.62 seconds
Started Jun 04 12:54:26 PM PDT 24
Finished Jun 04 12:54:30 PM PDT 24
Peak memory 201096 kb
Host smart-963fd09c-bcf7-40c8-925c-4cae5a391793
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275992156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2275992156
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.680299909
Short name T523
Test name
Test status
Simulation time 144985003 ps
CPU time 1.85 seconds
Started Jun 04 12:54:29 PM PDT 24
Finished Jun 04 12:54:32 PM PDT 24
Peak memory 200872 kb
Host smart-acd9f144-5258-4549-84c3-ceec94c086e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680299909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.680299909
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1954174599
Short name T434
Test name
Test status
Simulation time 75906927 ps
CPU time 0.82 seconds
Started Jun 04 12:54:26 PM PDT 24
Finished Jun 04 12:54:29 PM PDT 24
Peak memory 200732 kb
Host smart-73275394-1a2d-422a-974a-9af5ebd40268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954174599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1954174599
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3628782579
Short name T183
Test name
Test status
Simulation time 83999010 ps
CPU time 0.8 seconds
Started Jun 04 12:54:48 PM PDT 24
Finished Jun 04 12:54:50 PM PDT 24
Peak memory 200684 kb
Host smart-b2af3562-7ede-461f-be5a-94d12e5b9abc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628782579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3628782579
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2421670249
Short name T322
Test name
Test status
Simulation time 1216540127 ps
CPU time 5.6 seconds
Started Jun 04 12:54:35 PM PDT 24
Finished Jun 04 12:54:41 PM PDT 24
Peak memory 217896 kb
Host smart-ab6604d9-2dab-4ce6-b970-16cfd9cec829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421670249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2421670249
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1371084333
Short name T80
Test name
Test status
Simulation time 244165173 ps
CPU time 1.11 seconds
Started Jun 04 12:54:54 PM PDT 24
Finished Jun 04 12:54:56 PM PDT 24
Peak memory 217968 kb
Host smart-23cfc489-106e-4e33-9a7e-ee43d9c0b48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371084333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.1371084333
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.329958723
Short name T14
Test name
Test status
Simulation time 96322373 ps
CPU time 0.79 seconds
Started Jun 04 12:54:28 PM PDT 24
Finished Jun 04 12:54:31 PM PDT 24
Peak memory 200652 kb
Host smart-711f115e-73c1-49c0-9a1f-ab7f8b113ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329958723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.329958723
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1656636391
Short name T286
Test name
Test status
Simulation time 1369338706 ps
CPU time 5.19 seconds
Started Jun 04 12:54:25 PM PDT 24
Finished Jun 04 12:54:32 PM PDT 24
Peak memory 200964 kb
Host smart-3afb2db8-ed7c-4d90-9727-5dbbfa6a75b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656636391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1656636391
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2541009937
Short name T307
Test name
Test status
Simulation time 107115399 ps
CPU time 0.99 seconds
Started Jun 04 12:54:51 PM PDT 24
Finished Jun 04 12:54:52 PM PDT 24
Peak memory 200816 kb
Host smart-b55eff9e-a31e-4654-91a2-27d4894f0b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541009937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2541009937
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.3205729553
Short name T533
Test name
Test status
Simulation time 239693151 ps
CPU time 1.65 seconds
Started Jun 04 12:54:29 PM PDT 24
Finished Jun 04 12:54:32 PM PDT 24
Peak memory 201024 kb
Host smart-821d98ee-bb65-40d6-8ad5-de1f1fbddc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205729553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3205729553
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.282080653
Short name T532
Test name
Test status
Simulation time 7326972409 ps
CPU time 27.87 seconds
Started Jun 04 12:55:00 PM PDT 24
Finished Jun 04 12:55:29 PM PDT 24
Peak memory 210392 kb
Host smart-b3fcfbd1-bda8-4275-9bc4-2a2ccc8cef0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282080653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.282080653
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2099842042
Short name T463
Test name
Test status
Simulation time 384660955 ps
CPU time 2.57 seconds
Started Jun 04 12:54:39 PM PDT 24
Finished Jun 04 12:54:42 PM PDT 24
Peak memory 200788 kb
Host smart-ee1e5ee2-a66f-4081-8c7d-8ac62f845e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099842042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2099842042
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1699648581
Short name T432
Test name
Test status
Simulation time 106499594 ps
CPU time 0.99 seconds
Started Jun 04 12:54:56 PM PDT 24
Finished Jun 04 12:54:58 PM PDT 24
Peak memory 200800 kb
Host smart-af9b7c22-4206-4312-ac84-45ba8c65a3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699648581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1699648581
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1469656184
Short name T251
Test name
Test status
Simulation time 70078020 ps
CPU time 0.75 seconds
Started Jun 04 12:54:36 PM PDT 24
Finished Jun 04 12:54:37 PM PDT 24
Peak memory 200604 kb
Host smart-916ca23b-ed18-4ac8-b6a6-d921cfb14156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469656184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1469656184
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3394167070
Short name T480
Test name
Test status
Simulation time 1897122078 ps
CPU time 6.86 seconds
Started Jun 04 12:54:58 PM PDT 24
Finished Jun 04 12:55:05 PM PDT 24
Peak memory 218484 kb
Host smart-b1948820-e507-4512-9393-7309313316a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394167070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3394167070
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.669678256
Short name T309
Test name
Test status
Simulation time 243527934 ps
CPU time 1.12 seconds
Started Jun 04 12:54:41 PM PDT 24
Finished Jun 04 12:54:44 PM PDT 24
Peak memory 218084 kb
Host smart-90b177d2-e81d-4a01-9e02-9233f2b40b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669678256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.669678256
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3856453029
Short name T494
Test name
Test status
Simulation time 129165078 ps
CPU time 0.87 seconds
Started Jun 04 12:54:35 PM PDT 24
Finished Jun 04 12:54:37 PM PDT 24
Peak memory 200672 kb
Host smart-7a4895d5-8cf3-42f7-8af4-e9cc8359fb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856453029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3856453029
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.350599605
Short name T124
Test name
Test status
Simulation time 1766506187 ps
CPU time 6.31 seconds
Started Jun 04 12:54:36 PM PDT 24
Finished Jun 04 12:54:43 PM PDT 24
Peak memory 201044 kb
Host smart-b120f416-26b7-4fe9-bcc3-fac23cf014af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350599605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.350599605
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.2433903771
Short name T211
Test name
Test status
Simulation time 138791328 ps
CPU time 1.1 seconds
Started Jun 04 12:54:39 PM PDT 24
Finished Jun 04 12:54:41 PM PDT 24
Peak memory 200800 kb
Host smart-91ae0e6d-4542-45ac-8f76-692e33928a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433903771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.2433903771
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1075714451
Short name T455
Test name
Test status
Simulation time 253913462 ps
CPU time 1.72 seconds
Started Jun 04 12:54:36 PM PDT 24
Finished Jun 04 12:54:38 PM PDT 24
Peak memory 200952 kb
Host smart-778de2bc-d8b2-4601-af23-93bda502dcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075714451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1075714451
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.388976625
Short name T435
Test name
Test status
Simulation time 5541320005 ps
CPU time 19.28 seconds
Started Jun 04 12:54:41 PM PDT 24
Finished Jun 04 12:55:02 PM PDT 24
Peak memory 201232 kb
Host smart-2d951c51-c80c-4168-85b1-76908778e47a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388976625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.388976625
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2389011822
Short name T292
Test name
Test status
Simulation time 118356561 ps
CPU time 1.45 seconds
Started Jun 04 12:54:41 PM PDT 24
Finished Jun 04 12:54:44 PM PDT 24
Peak memory 200832 kb
Host smart-681231ba-e189-4147-86f1-d4f9f9f903a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389011822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2389011822
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1983439192
Short name T363
Test name
Test status
Simulation time 68575117 ps
CPU time 0.79 seconds
Started Jun 04 12:54:40 PM PDT 24
Finished Jun 04 12:54:43 PM PDT 24
Peak memory 200848 kb
Host smart-bb6fcfa9-1041-4a21-b83c-786413ae8fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983439192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1983439192
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2820880059
Short name T123
Test name
Test status
Simulation time 53605862 ps
CPU time 0.72 seconds
Started Jun 04 12:54:50 PM PDT 24
Finished Jun 04 12:54:57 PM PDT 24
Peak memory 200636 kb
Host smart-e5424417-6b25-434b-8003-1bc226e55ccf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820880059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2820880059
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1327669931
Short name T367
Test name
Test status
Simulation time 1219205778 ps
CPU time 5.62 seconds
Started Jun 04 12:54:46 PM PDT 24
Finished Jun 04 12:54:53 PM PDT 24
Peak memory 217920 kb
Host smart-839c2292-2910-43c1-93d9-5d2196025921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327669931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1327669931
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.831337865
Short name T454
Test name
Test status
Simulation time 243788785 ps
CPU time 1.06 seconds
Started Jun 04 12:54:40 PM PDT 24
Finished Jun 04 12:54:43 PM PDT 24
Peak memory 218016 kb
Host smart-690365e1-86e4-4b7e-979b-cd6b09479b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831337865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.831337865
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.44802198
Short name T170
Test name
Test status
Simulation time 192162007 ps
CPU time 0.94 seconds
Started Jun 04 12:54:49 PM PDT 24
Finished Jun 04 12:54:55 PM PDT 24
Peak memory 200540 kb
Host smart-49cc6da6-4aa0-40e3-839a-6cef5d9d738e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44802198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.44802198
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2517963438
Short name T518
Test name
Test status
Simulation time 1691717629 ps
CPU time 7.02 seconds
Started Jun 04 12:54:42 PM PDT 24
Finished Jun 04 12:54:51 PM PDT 24
Peak memory 200908 kb
Host smart-2b497f4e-8787-483f-b353-4aaea794a0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517963438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2517963438
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1035521349
Short name T35
Test name
Test status
Simulation time 172693881 ps
CPU time 1.24 seconds
Started Jun 04 12:54:48 PM PDT 24
Finished Jun 04 12:54:51 PM PDT 24
Peak memory 200824 kb
Host smart-59d6fb6e-24c4-4e93-b21e-77188cfdd202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035521349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1035521349
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2305025937
Short name T391
Test name
Test status
Simulation time 186000090 ps
CPU time 1.4 seconds
Started Jun 04 12:54:41 PM PDT 24
Finished Jun 04 12:54:44 PM PDT 24
Peak memory 200984 kb
Host smart-3d821304-e35c-4adf-a3d3-0bbbf8ead01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305025937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2305025937
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2003370700
Short name T333
Test name
Test status
Simulation time 828834820 ps
CPU time 4.16 seconds
Started Jun 04 12:54:48 PM PDT 24
Finished Jun 04 12:54:54 PM PDT 24
Peak memory 200996 kb
Host smart-6c304fe1-fbec-4f73-97d2-f0f8173cf6c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003370700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2003370700
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1593572362
Short name T543
Test name
Test status
Simulation time 386525242 ps
CPU time 2.09 seconds
Started Jun 04 12:54:35 PM PDT 24
Finished Jun 04 12:54:37 PM PDT 24
Peak memory 200808 kb
Host smart-299d3094-b523-4497-bec7-aa8188cf2f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593572362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1593572362
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3154139050
Short name T115
Test name
Test status
Simulation time 95995906 ps
CPU time 0.84 seconds
Started Jun 04 12:54:51 PM PDT 24
Finished Jun 04 12:54:53 PM PDT 24
Peak memory 200812 kb
Host smart-536d01d9-2902-4ae2-8688-afc1ec8fe7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154139050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3154139050
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.519160365
Short name T163
Test name
Test status
Simulation time 59077353 ps
CPU time 0.78 seconds
Started Jun 04 12:54:39 PM PDT 24
Finished Jun 04 12:54:41 PM PDT 24
Peak memory 200684 kb
Host smart-555f3325-cb24-4a91-a7e9-bcef8b77ed83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519160365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.519160365
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.4049350321
Short name T475
Test name
Test status
Simulation time 1225325145 ps
CPU time 5.45 seconds
Started Jun 04 12:54:42 PM PDT 24
Finished Jun 04 12:54:49 PM PDT 24
Peak memory 218388 kb
Host smart-08275baf-2335-41ad-bf23-63c7dfe3e3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049350321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.4049350321
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1365754069
Short name T347
Test name
Test status
Simulation time 245407007 ps
CPU time 1.1 seconds
Started Jun 04 12:54:39 PM PDT 24
Finished Jun 04 12:54:41 PM PDT 24
Peak memory 218152 kb
Host smart-8f5b2cbe-b8df-4d17-a27c-6d8e01f14a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365754069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1365754069
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1351520399
Short name T457
Test name
Test status
Simulation time 176235666 ps
CPU time 0.86 seconds
Started Jun 04 12:54:41 PM PDT 24
Finished Jun 04 12:54:44 PM PDT 24
Peak memory 200656 kb
Host smart-9c360145-8f1a-4e4d-90ab-546ab08d6788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351520399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1351520399
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3152728393
Short name T246
Test name
Test status
Simulation time 922495999 ps
CPU time 4.76 seconds
Started Jun 04 12:54:33 PM PDT 24
Finished Jun 04 12:54:39 PM PDT 24
Peak memory 201040 kb
Host smart-6de8c6fe-bf1e-4b72-9376-e0105776c72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152728393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3152728393
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3799146020
Short name T539
Test name
Test status
Simulation time 110163411 ps
CPU time 1.03 seconds
Started Jun 04 12:54:50 PM PDT 24
Finished Jun 04 12:54:51 PM PDT 24
Peak memory 200700 kb
Host smart-41e890f2-7403-4043-ae04-dfcb0dd63694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799146020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3799146020
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.36136344
Short name T50
Test name
Test status
Simulation time 200441314 ps
CPU time 1.46 seconds
Started Jun 04 12:54:40 PM PDT 24
Finished Jun 04 12:54:43 PM PDT 24
Peak memory 201024 kb
Host smart-cb0d0f62-8945-4d9b-8159-d4fc8230acdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36136344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.36136344
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.586842810
Short name T301
Test name
Test status
Simulation time 11671506731 ps
CPU time 42.26 seconds
Started Jun 04 12:54:35 PM PDT 24
Finished Jun 04 12:55:18 PM PDT 24
Peak memory 209380 kb
Host smart-a35caa20-95c6-4922-a016-52f9c0d91e99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586842810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.586842810
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2404215880
Short name T413
Test name
Test status
Simulation time 130454546 ps
CPU time 1.67 seconds
Started Jun 04 12:54:35 PM PDT 24
Finished Jun 04 12:54:38 PM PDT 24
Peak memory 200792 kb
Host smart-f0457495-86ac-4e18-94c3-ece409a76264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404215880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2404215880
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.219210651
Short name T206
Test name
Test status
Simulation time 91160190 ps
CPU time 0.89 seconds
Started Jun 04 12:54:40 PM PDT 24
Finished Jun 04 12:54:42 PM PDT 24
Peak memory 200824 kb
Host smart-216917d4-e4ff-4fd9-b39a-226849771280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219210651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.219210651
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2954541443
Short name T540
Test name
Test status
Simulation time 69606152 ps
CPU time 0.78 seconds
Started Jun 04 12:54:37 PM PDT 24
Finished Jun 04 12:54:39 PM PDT 24
Peak memory 200664 kb
Host smart-4ed61b25-3990-4dd1-982b-cf615e4f718e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954541443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2954541443
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1695569103
Short name T493
Test name
Test status
Simulation time 1898299857 ps
CPU time 6.81 seconds
Started Jun 04 12:54:47 PM PDT 24
Finished Jun 04 12:54:55 PM PDT 24
Peak memory 217864 kb
Host smart-fbd7906e-c7a5-4ea5-af71-a3b47ad01e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695569103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1695569103
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2382721965
Short name T406
Test name
Test status
Simulation time 244359839 ps
CPU time 1.08 seconds
Started Jun 04 12:54:36 PM PDT 24
Finished Jun 04 12:54:38 PM PDT 24
Peak memory 217964 kb
Host smart-ab339a8d-0def-459a-9b77-711eb3517e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382721965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2382721965
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.3826114535
Short name T173
Test name
Test status
Simulation time 95403725 ps
CPU time 0.81 seconds
Started Jun 04 12:54:40 PM PDT 24
Finished Jun 04 12:54:43 PM PDT 24
Peak memory 200644 kb
Host smart-5e2d541f-07b6-4ee7-bdad-f33e14b12dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826114535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3826114535
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1214292685
Short name T120
Test name
Test status
Simulation time 799795847 ps
CPU time 4.57 seconds
Started Jun 04 12:54:55 PM PDT 24
Finished Jun 04 12:55:01 PM PDT 24
Peak memory 201028 kb
Host smart-15c9cf14-e8a1-4732-af85-8345ca037512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214292685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1214292685
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1436186151
Short name T293
Test name
Test status
Simulation time 176234118 ps
CPU time 1.16 seconds
Started Jun 04 12:54:39 PM PDT 24
Finished Jun 04 12:54:41 PM PDT 24
Peak memory 200800 kb
Host smart-bb5b95bb-3ee9-41f8-87b7-a373498bde69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436186151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1436186151
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2639742168
Short name T389
Test name
Test status
Simulation time 128037178 ps
CPU time 1.15 seconds
Started Jun 04 12:54:37 PM PDT 24
Finished Jun 04 12:54:39 PM PDT 24
Peak memory 201012 kb
Host smart-871de34d-3a2f-47c6-b9d5-c50e83b56768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639742168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2639742168
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2655138100
Short name T248
Test name
Test status
Simulation time 410529227 ps
CPU time 2.28 seconds
Started Jun 04 12:54:38 PM PDT 24
Finished Jun 04 12:54:41 PM PDT 24
Peak memory 201036 kb
Host smart-c1ed7436-33a0-4c34-abb4-43ae9c77dd90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655138100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2655138100
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3329110304
Short name T466
Test name
Test status
Simulation time 150957286 ps
CPU time 1.82 seconds
Started Jun 04 12:54:59 PM PDT 24
Finished Jun 04 12:55:01 PM PDT 24
Peak memory 200896 kb
Host smart-da0ae14c-1a1c-4cd8-9f2e-229b129899ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329110304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3329110304
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2552459192
Short name T497
Test name
Test status
Simulation time 162451947 ps
CPU time 1.28 seconds
Started Jun 04 12:54:40 PM PDT 24
Finished Jun 04 12:54:43 PM PDT 24
Peak memory 201028 kb
Host smart-fa4745e2-a7d1-46a6-ab8e-c1339229424d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552459192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2552459192
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3040171732
Short name T176
Test name
Test status
Simulation time 74401187 ps
CPU time 0.82 seconds
Started Jun 04 12:54:37 PM PDT 24
Finished Jun 04 12:54:38 PM PDT 24
Peak memory 200636 kb
Host smart-341c1a09-f973-4644-82e7-1e0df7d2fbef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040171732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3040171732
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.89966260
Short name T45
Test name
Test status
Simulation time 1241368802 ps
CPU time 6.28 seconds
Started Jun 04 12:54:54 PM PDT 24
Finished Jun 04 12:55:01 PM PDT 24
Peak memory 222556 kb
Host smart-b410ccd7-ccb9-48fe-ab63-68e7a459117e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89966260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.89966260
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3202955266
Short name T372
Test name
Test status
Simulation time 244617230 ps
CPU time 1.08 seconds
Started Jun 04 12:54:40 PM PDT 24
Finished Jun 04 12:54:42 PM PDT 24
Peak memory 218092 kb
Host smart-5f0a8e63-7ced-4c92-9f5f-d3c629f946a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202955266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3202955266
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3701023241
Short name T459
Test name
Test status
Simulation time 185159290 ps
CPU time 0.85 seconds
Started Jun 04 12:54:42 PM PDT 24
Finished Jun 04 12:54:45 PM PDT 24
Peak memory 200564 kb
Host smart-be575374-3b21-4f9a-a6a9-aa9743f23da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701023241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3701023241
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1238042049
Short name T422
Test name
Test status
Simulation time 2021799306 ps
CPU time 7.44 seconds
Started Jun 04 12:54:53 PM PDT 24
Finished Jun 04 12:55:01 PM PDT 24
Peak memory 201004 kb
Host smart-80326695-0968-4ddf-8481-630e90f4a931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238042049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1238042049
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.300258295
Short name T368
Test name
Test status
Simulation time 99617669 ps
CPU time 1.06 seconds
Started Jun 04 12:54:36 PM PDT 24
Finished Jun 04 12:54:37 PM PDT 24
Peak memory 200800 kb
Host smart-88dc99f1-8743-4300-8824-365a455433a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300258295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.300258295
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.645523345
Short name T409
Test name
Test status
Simulation time 200655101 ps
CPU time 1.35 seconds
Started Jun 04 12:54:40 PM PDT 24
Finished Jun 04 12:54:42 PM PDT 24
Peak memory 200972 kb
Host smart-76334d31-833b-419d-b56b-a45cc5745581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645523345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.645523345
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1521542296
Short name T510
Test name
Test status
Simulation time 5521198352 ps
CPU time 20.24 seconds
Started Jun 04 12:54:40 PM PDT 24
Finished Jun 04 12:55:02 PM PDT 24
Peak memory 201140 kb
Host smart-96f9026f-c228-40d9-a5a9-818f7633732b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521542296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1521542296
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3944670348
Short name T295
Test name
Test status
Simulation time 375329220 ps
CPU time 2.24 seconds
Started Jun 04 12:54:39 PM PDT 24
Finished Jun 04 12:54:42 PM PDT 24
Peak memory 209060 kb
Host smart-482d6468-1045-4b81-b850-7464d86964eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944670348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3944670348
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2128581987
Short name T405
Test name
Test status
Simulation time 213703448 ps
CPU time 1.43 seconds
Started Jun 04 12:54:39 PM PDT 24
Finished Jun 04 12:54:41 PM PDT 24
Peak memory 200844 kb
Host smart-d005e8d4-1ee5-4b8d-872b-8e5c88e3acb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128581987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2128581987
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.504662454
Short name T59
Test name
Test status
Simulation time 59524559 ps
CPU time 0.79 seconds
Started Jun 04 12:54:41 PM PDT 24
Finished Jun 04 12:54:44 PM PDT 24
Peak memory 200588 kb
Host smart-ea4cd212-cd36-4846-944d-9e63a993f03c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504662454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.504662454
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1474652021
Short name T381
Test name
Test status
Simulation time 1908668403 ps
CPU time 6.9 seconds
Started Jun 04 12:54:40 PM PDT 24
Finished Jun 04 12:54:49 PM PDT 24
Peak memory 222480 kb
Host smart-26bb35fb-87c9-46ce-aaaf-9205c0221ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474652021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1474652021
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2014167866
Short name T308
Test name
Test status
Simulation time 244150490 ps
CPU time 1.07 seconds
Started Jun 04 12:54:41 PM PDT 24
Finished Jun 04 12:54:44 PM PDT 24
Peak memory 217928 kb
Host smart-dfa98ef6-338d-4837-acdc-89ac2b876c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014167866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2014167866
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3602066561
Short name T330
Test name
Test status
Simulation time 202984023 ps
CPU time 0.89 seconds
Started Jun 04 12:54:42 PM PDT 24
Finished Jun 04 12:54:45 PM PDT 24
Peak memory 200572 kb
Host smart-517f83a9-a6b4-4863-9905-d12ce1c805ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602066561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3602066561
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.1111071228
Short name T499
Test name
Test status
Simulation time 1067337663 ps
CPU time 5.13 seconds
Started Jun 04 12:54:41 PM PDT 24
Finished Jun 04 12:54:48 PM PDT 24
Peak memory 200928 kb
Host smart-42aa2f9d-982a-4fd9-b704-51284d1f6f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111071228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.1111071228
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2132024054
Short name T536
Test name
Test status
Simulation time 133773821 ps
CPU time 1.19 seconds
Started Jun 04 12:54:48 PM PDT 24
Finished Jun 04 12:54:50 PM PDT 24
Peak memory 200764 kb
Host smart-a90f18af-3565-4ef5-95da-902bdf9ef793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132024054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2132024054
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3373453089
Short name T268
Test name
Test status
Simulation time 192318618 ps
CPU time 1.4 seconds
Started Jun 04 12:54:42 PM PDT 24
Finished Jun 04 12:54:46 PM PDT 24
Peak memory 201064 kb
Host smart-a48fbadc-fcea-468d-89bd-60687aebc5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373453089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3373453089
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.650862659
Short name T505
Test name
Test status
Simulation time 5966452992 ps
CPU time 25.09 seconds
Started Jun 04 12:54:36 PM PDT 24
Finished Jun 04 12:55:02 PM PDT 24
Peak memory 201124 kb
Host smart-6770efb3-9737-442c-b12b-21015dde5d71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650862659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.650862659
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.819360112
Short name T534
Test name
Test status
Simulation time 132706456 ps
CPU time 1.61 seconds
Started Jun 04 12:54:48 PM PDT 24
Finished Jun 04 12:54:51 PM PDT 24
Peak memory 200756 kb
Host smart-62073fda-46f5-4eeb-9b19-e2d4bdaba89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819360112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.819360112
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2852298527
Short name T46
Test name
Test status
Simulation time 164445441 ps
CPU time 1.12 seconds
Started Jun 04 12:54:47 PM PDT 24
Finished Jun 04 12:54:49 PM PDT 24
Peak memory 200772 kb
Host smart-95a022c6-b2ce-4db9-88d2-0b738d40c023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852298527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2852298527
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3008636462
Short name T317
Test name
Test status
Simulation time 80355410 ps
CPU time 0.82 seconds
Started Jun 04 12:54:02 PM PDT 24
Finished Jun 04 12:54:03 PM PDT 24
Peak memory 200580 kb
Host smart-423392ab-a38b-4931-95a4-e2356736f9e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008636462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3008636462
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3025404802
Short name T44
Test name
Test status
Simulation time 2184580924 ps
CPU time 7.84 seconds
Started Jun 04 12:54:08 PM PDT 24
Finished Jun 04 12:54:17 PM PDT 24
Peak memory 218072 kb
Host smart-2308f665-c229-4c58-b513-99637207a81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025404802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3025404802
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3548034242
Short name T265
Test name
Test status
Simulation time 244083934 ps
CPU time 1.16 seconds
Started Jun 04 12:54:06 PM PDT 24
Finished Jun 04 12:54:07 PM PDT 24
Peak memory 217964 kb
Host smart-82b1187e-9924-47d1-b48b-ab661a29aa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548034242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3548034242
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1980188731
Short name T514
Test name
Test status
Simulation time 122987705 ps
CPU time 0.8 seconds
Started Jun 04 12:54:16 PM PDT 24
Finished Jun 04 12:54:17 PM PDT 24
Peak memory 200592 kb
Host smart-55d104f0-39d6-4c5c-8ba1-d664c4a8a6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980188731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1980188731
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1375171397
Short name T306
Test name
Test status
Simulation time 1976707261 ps
CPU time 7 seconds
Started Jun 04 12:54:14 PM PDT 24
Finished Jun 04 12:54:22 PM PDT 24
Peak memory 200948 kb
Host smart-a4470970-2957-4b38-8101-1fe78c4cc2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375171397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1375171397
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2030858456
Short name T76
Test name
Test status
Simulation time 16636454177 ps
CPU time 26.72 seconds
Started Jun 04 12:54:03 PM PDT 24
Finished Jun 04 12:54:31 PM PDT 24
Peak memory 217636 kb
Host smart-b9f2692a-0abb-406f-a863-d7a5483f84f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030858456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2030858456
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2571511064
Short name T12
Test name
Test status
Simulation time 169861151 ps
CPU time 1.24 seconds
Started Jun 04 12:54:01 PM PDT 24
Finished Jun 04 12:54:03 PM PDT 24
Peak memory 200788 kb
Host smart-0e461507-4f50-452f-84c8-9a60f6c1ec48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571511064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2571511064
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.13236441
Short name T172
Test name
Test status
Simulation time 114318391 ps
CPU time 1.18 seconds
Started Jun 04 12:54:01 PM PDT 24
Finished Jun 04 12:54:03 PM PDT 24
Peak memory 200944 kb
Host smart-9c92d45e-7c7a-49b4-8ee2-c0573aa8dde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13236441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.13236441
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1770288555
Short name T262
Test name
Test status
Simulation time 3624142249 ps
CPU time 13.38 seconds
Started Jun 04 12:54:15 PM PDT 24
Finished Jun 04 12:54:29 PM PDT 24
Peak memory 201152 kb
Host smart-0e6eec9e-17bb-43af-bdb5-505c55174664
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770288555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1770288555
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.554643146
Short name T415
Test name
Test status
Simulation time 293657201 ps
CPU time 1.93 seconds
Started Jun 04 12:54:16 PM PDT 24
Finished Jun 04 12:54:25 PM PDT 24
Peak memory 200720 kb
Host smart-b428f415-47aa-4ab7-ac80-96e2f14771f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554643146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.554643146
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.236016262
Short name T254
Test name
Test status
Simulation time 140402747 ps
CPU time 1.12 seconds
Started Jun 04 12:54:06 PM PDT 24
Finished Jun 04 12:54:08 PM PDT 24
Peak memory 200744 kb
Host smart-0823085d-bd76-4212-8302-41d7cf958694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236016262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.236016262
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1113630473
Short name T408
Test name
Test status
Simulation time 74230577 ps
CPU time 0.88 seconds
Started Jun 04 12:54:49 PM PDT 24
Finished Jun 04 12:54:51 PM PDT 24
Peak memory 200616 kb
Host smart-ecb6d93b-a057-412a-84e4-8b49ca8dc7a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113630473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1113630473
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3653414956
Short name T396
Test name
Test status
Simulation time 1897347149 ps
CPU time 7.38 seconds
Started Jun 04 12:55:04 PM PDT 24
Finished Jun 04 12:55:12 PM PDT 24
Peak memory 222344 kb
Host smart-61c01a6b-e2c2-4b15-ae70-afc36158a340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653414956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3653414956
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2395443663
Short name T379
Test name
Test status
Simulation time 244650547 ps
CPU time 1.07 seconds
Started Jun 04 12:54:45 PM PDT 24
Finished Jun 04 12:54:47 PM PDT 24
Peak memory 217968 kb
Host smart-ce2b9790-f9f1-4dd2-bfff-251a3a7eaa21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395443663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2395443663
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3406215713
Short name T20
Test name
Test status
Simulation time 206151625 ps
CPU time 0.95 seconds
Started Jun 04 12:54:39 PM PDT 24
Finished Jun 04 12:54:41 PM PDT 24
Peak memory 200624 kb
Host smart-dd41ce69-ec85-4b2f-91bf-668b3e470acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406215713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3406215713
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2584266341
Short name T375
Test name
Test status
Simulation time 1366830875 ps
CPU time 5.69 seconds
Started Jun 04 12:54:42 PM PDT 24
Finished Jun 04 12:54:49 PM PDT 24
Peak memory 201024 kb
Host smart-823cdbff-fde5-4334-9aad-57d3e83fdbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584266341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2584266341
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2316333024
Short name T395
Test name
Test status
Simulation time 107777336 ps
CPU time 1 seconds
Started Jun 04 12:54:41 PM PDT 24
Finished Jun 04 12:54:43 PM PDT 24
Peak memory 200776 kb
Host smart-2712ef7a-055c-41cd-b068-f93f42041dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316333024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2316333024
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.1053236564
Short name T230
Test name
Test status
Simulation time 115029245 ps
CPU time 1.22 seconds
Started Jun 04 12:54:41 PM PDT 24
Finished Jun 04 12:54:45 PM PDT 24
Peak memory 200924 kb
Host smart-5cd87eb0-9a1c-4297-974d-b00f3633a9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053236564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.1053236564
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.662922971
Short name T491
Test name
Test status
Simulation time 3988983786 ps
CPU time 19.98 seconds
Started Jun 04 12:54:51 PM PDT 24
Finished Jun 04 12:55:12 PM PDT 24
Peak memory 201112 kb
Host smart-bda23b0d-463d-453a-b3a5-aa33f4d0efb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662922971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.662922971
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3810934308
Short name T399
Test name
Test status
Simulation time 385069310 ps
CPU time 2.23 seconds
Started Jun 04 12:54:42 PM PDT 24
Finished Jun 04 12:54:46 PM PDT 24
Peak memory 200732 kb
Host smart-3ea662ce-f54e-4850-990d-f274c78dbf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810934308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3810934308
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2660512321
Short name T242
Test name
Test status
Simulation time 99315532 ps
CPU time 0.85 seconds
Started Jun 04 12:54:59 PM PDT 24
Finished Jun 04 12:55:02 PM PDT 24
Peak memory 200800 kb
Host smart-cc2b00dc-228e-4a34-88e5-c29220b44547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660512321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2660512321
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2273574136
Short name T412
Test name
Test status
Simulation time 71567589 ps
CPU time 0.79 seconds
Started Jun 04 12:54:44 PM PDT 24
Finished Jun 04 12:54:47 PM PDT 24
Peak memory 200628 kb
Host smart-b4824e38-64d9-43a2-a25d-b4710f5adde8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273574136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2273574136
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2818732647
Short name T236
Test name
Test status
Simulation time 1889051973 ps
CPU time 7.18 seconds
Started Jun 04 12:54:48 PM PDT 24
Finished Jun 04 12:55:01 PM PDT 24
Peak memory 218464 kb
Host smart-ebccdba5-c62b-4494-890c-7d71847bcdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818732647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2818732647
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.150542181
Short name T255
Test name
Test status
Simulation time 243692887 ps
CPU time 1.08 seconds
Started Jun 04 12:54:53 PM PDT 24
Finished Jun 04 12:54:55 PM PDT 24
Peak memory 218076 kb
Host smart-19a6e5ae-79b2-494d-8b57-f3b02d3d62c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150542181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.150542181
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.2958594724
Short name T335
Test name
Test status
Simulation time 209153178 ps
CPU time 0.97 seconds
Started Jun 04 12:54:40 PM PDT 24
Finished Jun 04 12:54:42 PM PDT 24
Peak memory 200632 kb
Host smart-b305af0c-b34a-4fc8-98aa-f927bd752379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958594724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2958594724
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3931308336
Short name T112
Test name
Test status
Simulation time 809995331 ps
CPU time 4.34 seconds
Started Jun 04 12:54:41 PM PDT 24
Finished Jun 04 12:54:47 PM PDT 24
Peak memory 200928 kb
Host smart-16a93890-dac6-49cb-8318-505f1e19d3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931308336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3931308336
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2254161899
Short name T228
Test name
Test status
Simulation time 146916007 ps
CPU time 1.12 seconds
Started Jun 04 12:54:56 PM PDT 24
Finished Jun 04 12:54:58 PM PDT 24
Peak memory 200800 kb
Host smart-90a0cfe2-9021-4e29-b42e-0556c961c66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254161899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2254161899
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3409012289
Short name T519
Test name
Test status
Simulation time 121707425 ps
CPU time 1.18 seconds
Started Jun 04 12:54:48 PM PDT 24
Finished Jun 04 12:54:50 PM PDT 24
Peak memory 201024 kb
Host smart-bb1dda77-0b3f-4cbc-acc6-ed4dc60608ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409012289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3409012289
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2375462947
Short name T325
Test name
Test status
Simulation time 11523752190 ps
CPU time 39.18 seconds
Started Jun 04 12:54:48 PM PDT 24
Finished Jun 04 12:55:28 PM PDT 24
Peak memory 209396 kb
Host smart-c6548e3a-9e3c-4151-8681-079ad34c6729
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375462947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2375462947
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3403073364
Short name T447
Test name
Test status
Simulation time 77276271 ps
CPU time 0.81 seconds
Started Jun 04 12:54:48 PM PDT 24
Finished Jun 04 12:54:50 PM PDT 24
Peak memory 200872 kb
Host smart-6aafab27-6cce-470c-a3da-e20d137291b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403073364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3403073364
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1870248554
Short name T400
Test name
Test status
Simulation time 83787940 ps
CPU time 0.79 seconds
Started Jun 04 12:54:59 PM PDT 24
Finished Jun 04 12:55:00 PM PDT 24
Peak memory 200656 kb
Host smart-e16c2768-54d7-4198-805c-4b7f3a51b92a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870248554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1870248554
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.3586732260
Short name T460
Test name
Test status
Simulation time 1897621432 ps
CPU time 7.12 seconds
Started Jun 04 12:54:49 PM PDT 24
Finished Jun 04 12:54:57 PM PDT 24
Peak memory 217904 kb
Host smart-8f65d837-70f5-48e0-a2b4-994b95ef78cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586732260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3586732260
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2121909131
Short name T187
Test name
Test status
Simulation time 243528781 ps
CPU time 1.14 seconds
Started Jun 04 12:54:56 PM PDT 24
Finished Jun 04 12:54:58 PM PDT 24
Peak memory 218192 kb
Host smart-cf3ccaee-81ec-40e9-bab0-f4819dc5ab9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121909131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.2121909131
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3213446646
Short name T478
Test name
Test status
Simulation time 159287830 ps
CPU time 0.9 seconds
Started Jun 04 12:54:42 PM PDT 24
Finished Jun 04 12:54:45 PM PDT 24
Peak memory 200676 kb
Host smart-c218d374-982c-4b98-9634-c6bcf49444b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213446646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3213446646
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2380463431
Short name T219
Test name
Test status
Simulation time 1077583123 ps
CPU time 4.79 seconds
Started Jun 04 12:54:48 PM PDT 24
Finished Jun 04 12:54:54 PM PDT 24
Peak memory 200872 kb
Host smart-11259596-965e-4d5c-93cf-38d0de391a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380463431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2380463431
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.784382991
Short name T280
Test name
Test status
Simulation time 164902281 ps
CPU time 1.09 seconds
Started Jun 04 12:54:40 PM PDT 24
Finished Jun 04 12:54:43 PM PDT 24
Peak memory 200860 kb
Host smart-6fe40749-aa4c-4f9c-8e6c-5d3f7a864d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784382991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.784382991
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1189378501
Short name T312
Test name
Test status
Simulation time 198277474 ps
CPU time 1.34 seconds
Started Jun 04 12:54:39 PM PDT 24
Finished Jun 04 12:54:41 PM PDT 24
Peak memory 200980 kb
Host smart-2fe20837-2829-47f9-93d1-5b45488acee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189378501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1189378501
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1661510745
Short name T544
Test name
Test status
Simulation time 2968515323 ps
CPU time 14.16 seconds
Started Jun 04 12:54:48 PM PDT 24
Finished Jun 04 12:55:03 PM PDT 24
Peak memory 201100 kb
Host smart-47dc5aa1-d273-4fef-8c24-4150c7f8d90f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661510745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1661510745
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.340817499
Short name T488
Test name
Test status
Simulation time 124454471 ps
CPU time 1.5 seconds
Started Jun 04 12:54:48 PM PDT 24
Finished Jun 04 12:54:50 PM PDT 24
Peak memory 200788 kb
Host smart-1e00f3af-6e57-40cf-a918-ce3dfdcd53fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340817499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.340817499
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.997541740
Short name T360
Test name
Test status
Simulation time 77200025 ps
CPU time 0.78 seconds
Started Jun 04 12:54:47 PM PDT 24
Finished Jun 04 12:54:48 PM PDT 24
Peak memory 200768 kb
Host smart-eaeb525f-f9b2-41a8-b48c-872564a3b73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997541740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.997541740
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.260455967
Short name T260
Test name
Test status
Simulation time 82411602 ps
CPU time 0.82 seconds
Started Jun 04 12:54:58 PM PDT 24
Finished Jun 04 12:55:00 PM PDT 24
Peak memory 200708 kb
Host smart-d6a740dd-7afd-4176-9dd1-86c77d804b1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260455967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.260455967
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.885695705
Short name T487
Test name
Test status
Simulation time 2366013709 ps
CPU time 8.03 seconds
Started Jun 04 12:54:43 PM PDT 24
Finished Jun 04 12:54:52 PM PDT 24
Peak memory 222668 kb
Host smart-4b76e979-b1cf-4c5f-a99d-6330e91295d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885695705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.885695705
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2142684529
Short name T73
Test name
Test status
Simulation time 244161794 ps
CPU time 1.11 seconds
Started Jun 04 12:54:57 PM PDT 24
Finished Jun 04 12:54:59 PM PDT 24
Peak memory 218128 kb
Host smart-77605a29-7c59-4367-b801-347b9aff4015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142684529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2142684529
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.4110149910
Short name T508
Test name
Test status
Simulation time 92205099 ps
CPU time 0.76 seconds
Started Jun 04 12:54:38 PM PDT 24
Finished Jun 04 12:54:40 PM PDT 24
Peak memory 200648 kb
Host smart-6ab63246-b370-4c9a-83ce-3df7ed4723e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110149910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.4110149910
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.2109084948
Short name T197
Test name
Test status
Simulation time 1663464670 ps
CPU time 6.47 seconds
Started Jun 04 12:54:45 PM PDT 24
Finished Jun 04 12:54:53 PM PDT 24
Peak memory 201024 kb
Host smart-ba0c9282-5ff8-4dd2-bbd7-928b09e9311c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109084948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.2109084948
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.266922302
Short name T513
Test name
Test status
Simulation time 107536097 ps
CPU time 1 seconds
Started Jun 04 12:54:53 PM PDT 24
Finished Jun 04 12:54:55 PM PDT 24
Peak memory 200840 kb
Host smart-3d29a1f9-937c-4c20-bc63-43f8e88d1d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266922302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.266922302
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.866450596
Short name T275
Test name
Test status
Simulation time 113825261 ps
CPU time 1.2 seconds
Started Jun 04 12:54:39 PM PDT 24
Finished Jun 04 12:54:41 PM PDT 24
Peak memory 201012 kb
Host smart-0f2b04a3-c204-4e43-8b51-2aec1d86e352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866450596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.866450596
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.3225786408
Short name T122
Test name
Test status
Simulation time 14338568064 ps
CPU time 45.01 seconds
Started Jun 04 12:54:45 PM PDT 24
Finished Jun 04 12:55:31 PM PDT 24
Peak memory 201192 kb
Host smart-be586535-ec59-4730-aa75-09f1e78cbd3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225786408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3225786408
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1453790607
Short name T490
Test name
Test status
Simulation time 458369854 ps
CPU time 2.47 seconds
Started Jun 04 12:54:44 PM PDT 24
Finished Jun 04 12:54:48 PM PDT 24
Peak memory 200828 kb
Host smart-9bcae726-ff67-4222-ad82-978d9a8c59e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453790607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1453790607
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.561723655
Short name T512
Test name
Test status
Simulation time 151989576 ps
CPU time 1.22 seconds
Started Jun 04 12:54:53 PM PDT 24
Finished Jun 04 12:54:55 PM PDT 24
Peak memory 200840 kb
Host smart-73abea40-83c9-4ad8-b0bf-3bcc377db430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561723655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.561723655
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.4087024622
Short name T225
Test name
Test status
Simulation time 66664157 ps
CPU time 0.84 seconds
Started Jun 04 12:54:54 PM PDT 24
Finished Jun 04 12:54:56 PM PDT 24
Peak memory 200484 kb
Host smart-e13ead1f-ef9e-47fb-8ad3-2645fec74c97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087024622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.4087024622
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3451208594
Short name T31
Test name
Test status
Simulation time 1895261072 ps
CPU time 7.6 seconds
Started Jun 04 12:54:58 PM PDT 24
Finished Jun 04 12:55:07 PM PDT 24
Peak memory 222424 kb
Host smart-e2badde3-88ea-43a6-bae6-4eb8745cb664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451208594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3451208594
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3503876691
Short name T195
Test name
Test status
Simulation time 243783444 ps
CPU time 1.13 seconds
Started Jun 04 12:55:01 PM PDT 24
Finished Jun 04 12:55:03 PM PDT 24
Peak memory 218148 kb
Host smart-3bffb23f-5dc5-46d8-a13d-e713a43d4606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503876691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3503876691
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3965651409
Short name T4
Test name
Test status
Simulation time 106608161 ps
CPU time 0.83 seconds
Started Jun 04 12:54:42 PM PDT 24
Finished Jun 04 12:54:44 PM PDT 24
Peak memory 200672 kb
Host smart-ae8bc09c-fdc8-4d30-85aa-b7a0a50bcf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965651409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3965651409
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.602802858
Short name T520
Test name
Test status
Simulation time 2068829495 ps
CPU time 7.69 seconds
Started Jun 04 12:54:55 PM PDT 24
Finished Jun 04 12:55:03 PM PDT 24
Peak memory 201044 kb
Host smart-5ae68b5a-e4b1-4175-a5bb-a3414e900381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602802858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.602802858
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1389741016
Short name T152
Test name
Test status
Simulation time 101735318 ps
CPU time 1.02 seconds
Started Jun 04 12:54:45 PM PDT 24
Finished Jun 04 12:54:47 PM PDT 24
Peak memory 200840 kb
Host smart-6e6ff53f-cfb8-4180-91e1-d60e3de011bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389741016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1389741016
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2149251099
Short name T177
Test name
Test status
Simulation time 254457713 ps
CPU time 1.45 seconds
Started Jun 04 12:55:09 PM PDT 24
Finished Jun 04 12:55:12 PM PDT 24
Peak memory 201044 kb
Host smart-2d824d1d-ae33-4dc4-ad3b-762c86fbd917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149251099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2149251099
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.2885101267
Short name T277
Test name
Test status
Simulation time 3752111860 ps
CPU time 14.56 seconds
Started Jun 04 12:54:52 PM PDT 24
Finished Jun 04 12:55:08 PM PDT 24
Peak memory 201172 kb
Host smart-72cf3f10-8f5a-45f6-a594-e5307c703f92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885101267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2885101267
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1702165284
Short name T61
Test name
Test status
Simulation time 406357594 ps
CPU time 2.14 seconds
Started Jun 04 12:54:43 PM PDT 24
Finished Jun 04 12:54:47 PM PDT 24
Peak memory 200808 kb
Host smart-2f58c339-76b3-4f65-99f5-47490155ce92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702165284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1702165284
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3675412522
Short name T149
Test name
Test status
Simulation time 105868079 ps
CPU time 0.95 seconds
Started Jun 04 12:54:50 PM PDT 24
Finished Jun 04 12:54:52 PM PDT 24
Peak memory 200852 kb
Host smart-5c1546bb-c1c5-4da1-9ffd-7ffa809caf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675412522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3675412522
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1056366604
Short name T164
Test name
Test status
Simulation time 82662734 ps
CPU time 0.77 seconds
Started Jun 04 12:55:00 PM PDT 24
Finished Jun 04 12:55:02 PM PDT 24
Peak memory 200568 kb
Host smart-a5d7e278-97b4-4cfd-bf05-b4d5402f4828
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056366604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1056366604
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3642047362
Short name T526
Test name
Test status
Simulation time 244121761 ps
CPU time 1.09 seconds
Started Jun 04 12:55:00 PM PDT 24
Finished Jun 04 12:55:03 PM PDT 24
Peak memory 217888 kb
Host smart-81a46a7a-9278-46f2-8a63-aed8662af5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642047362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3642047362
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.956748011
Short name T401
Test name
Test status
Simulation time 163074399 ps
CPU time 0.88 seconds
Started Jun 04 12:54:41 PM PDT 24
Finished Jun 04 12:54:44 PM PDT 24
Peak memory 200628 kb
Host smart-4696248b-0f2b-48eb-aa80-446c03c00fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956748011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.956748011
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1698222402
Short name T113
Test name
Test status
Simulation time 739987779 ps
CPU time 3.62 seconds
Started Jun 04 12:55:02 PM PDT 24
Finished Jun 04 12:55:07 PM PDT 24
Peak memory 201080 kb
Host smart-3a7fdfca-3d72-45fa-b9ed-7ac4195ad274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698222402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1698222402
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3870861745
Short name T153
Test name
Test status
Simulation time 101825459 ps
CPU time 0.95 seconds
Started Jun 04 12:54:50 PM PDT 24
Finished Jun 04 12:54:52 PM PDT 24
Peak memory 200852 kb
Host smart-450fcffe-5cec-4f03-93d7-d35083cc14fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870861745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3870861745
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.963070176
Short name T353
Test name
Test status
Simulation time 121906473 ps
CPU time 1.19 seconds
Started Jun 04 12:55:02 PM PDT 24
Finished Jun 04 12:55:04 PM PDT 24
Peak memory 201020 kb
Host smart-74083c43-68c1-4dce-9fed-0777471ce42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963070176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.963070176
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.278013156
Short name T476
Test name
Test status
Simulation time 10658667207 ps
CPU time 39.62 seconds
Started Jun 04 12:54:54 PM PDT 24
Finished Jun 04 12:55:34 PM PDT 24
Peak memory 209336 kb
Host smart-4ae71a79-ba28-4580-b18a-4181df91a556
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278013156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.278013156
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3133315029
Short name T421
Test name
Test status
Simulation time 127498424 ps
CPU time 1.57 seconds
Started Jun 04 12:55:00 PM PDT 24
Finished Jun 04 12:55:03 PM PDT 24
Peak memory 209052 kb
Host smart-a7c8de56-e66d-4c79-a222-804659186549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133315029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3133315029
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.176029671
Short name T489
Test name
Test status
Simulation time 79569100 ps
CPU time 0.8 seconds
Started Jun 04 12:55:00 PM PDT 24
Finished Jun 04 12:55:02 PM PDT 24
Peak memory 200728 kb
Host smart-6527ce1d-ca47-4c9c-8358-2cb37bbc3198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176029671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.176029671
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3230034736
Short name T256
Test name
Test status
Simulation time 82610704 ps
CPU time 0.89 seconds
Started Jun 04 12:54:45 PM PDT 24
Finished Jun 04 12:54:48 PM PDT 24
Peak memory 200680 kb
Host smart-9c491e79-e0a0-4549-a1c6-e48f9f1b9bb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230034736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3230034736
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2209717846
Short name T60
Test name
Test status
Simulation time 1214247793 ps
CPU time 5.59 seconds
Started Jun 04 12:55:09 PM PDT 24
Finished Jun 04 12:55:16 PM PDT 24
Peak memory 218220 kb
Host smart-dc6fa427-e441-429b-b98d-091f3a7e5946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209717846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2209717846
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.4269744179
Short name T185
Test name
Test status
Simulation time 244330857 ps
CPU time 1.03 seconds
Started Jun 04 12:54:50 PM PDT 24
Finished Jun 04 12:54:52 PM PDT 24
Peak memory 218164 kb
Host smart-4fb986d9-b2d7-443a-b337-795f13a5bb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269744179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.4269744179
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.439161694
Short name T273
Test name
Test status
Simulation time 195404518 ps
CPU time 0.95 seconds
Started Jun 04 12:55:06 PM PDT 24
Finished Jun 04 12:55:08 PM PDT 24
Peak memory 200664 kb
Host smart-78d3ceeb-4ba7-48fc-b1a4-257966d64c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439161694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.439161694
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3321745095
Short name T114
Test name
Test status
Simulation time 1462505339 ps
CPU time 6.4 seconds
Started Jun 04 12:54:47 PM PDT 24
Finished Jun 04 12:54:55 PM PDT 24
Peak memory 200944 kb
Host smart-84da10c0-e23d-4ae3-8f41-c3318a0ab665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321745095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3321745095
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1222799905
Short name T54
Test name
Test status
Simulation time 159189245 ps
CPU time 1.17 seconds
Started Jun 04 12:54:45 PM PDT 24
Finished Jun 04 12:54:47 PM PDT 24
Peak memory 200844 kb
Host smart-49498c99-d756-46d9-b60f-acd1c76494a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222799905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1222799905
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3090562184
Short name T97
Test name
Test status
Simulation time 120868919 ps
CPU time 1.21 seconds
Started Jun 04 12:54:41 PM PDT 24
Finished Jun 04 12:54:44 PM PDT 24
Peak memory 200940 kb
Host smart-8ceac999-ac81-4058-9f50-b55f08a556d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090562184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3090562184
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3806838980
Short name T288
Test name
Test status
Simulation time 255321364 ps
CPU time 1.9 seconds
Started Jun 04 12:54:58 PM PDT 24
Finished Jun 04 12:55:00 PM PDT 24
Peak memory 201076 kb
Host smart-614ebfc6-9dad-4e81-a301-99e1e718c31c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806838980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3806838980
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.128521953
Short name T180
Test name
Test status
Simulation time 115326768 ps
CPU time 1.47 seconds
Started Jun 04 12:54:55 PM PDT 24
Finished Jun 04 12:54:57 PM PDT 24
Peak memory 200752 kb
Host smart-3d07c62b-df7a-4449-855b-29da05a7fa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128521953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.128521953
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1679763085
Short name T267
Test name
Test status
Simulation time 155994912 ps
CPU time 1.23 seconds
Started Jun 04 12:55:03 PM PDT 24
Finished Jun 04 12:55:06 PM PDT 24
Peak memory 201032 kb
Host smart-2b81c2d7-6677-4e9b-9aa3-ff7782060ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679763085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1679763085
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.13863776
Short name T151
Test name
Test status
Simulation time 52120054 ps
CPU time 0.8 seconds
Started Jun 04 12:54:44 PM PDT 24
Finished Jun 04 12:54:46 PM PDT 24
Peak memory 200608 kb
Host smart-48d8d20a-a191-4f1c-8697-f4977fd54b24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13863776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.13863776
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1207514114
Short name T43
Test name
Test status
Simulation time 1226917427 ps
CPU time 5.83 seconds
Started Jun 04 12:55:07 PM PDT 24
Finished Jun 04 12:55:13 PM PDT 24
Peak memory 217312 kb
Host smart-0eff2bef-7d44-4e6a-b0f4-53939a306cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207514114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1207514114
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1030865075
Short name T430
Test name
Test status
Simulation time 244705865 ps
CPU time 1.17 seconds
Started Jun 04 12:55:00 PM PDT 24
Finished Jun 04 12:55:03 PM PDT 24
Peak memory 217940 kb
Host smart-f2af76e7-546c-4f49-95e3-3c6bcb550015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030865075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1030865075
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.662285510
Short name T19
Test name
Test status
Simulation time 219118455 ps
CPU time 1.07 seconds
Started Jun 04 12:54:56 PM PDT 24
Finished Jun 04 12:54:57 PM PDT 24
Peak memory 200540 kb
Host smart-59a1fa79-d217-4af5-947a-9ad9888b4fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662285510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.662285510
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.3871901735
Short name T88
Test name
Test status
Simulation time 1850258655 ps
CPU time 7.28 seconds
Started Jun 04 12:54:45 PM PDT 24
Finished Jun 04 12:54:54 PM PDT 24
Peak memory 200952 kb
Host smart-a0745c44-49a8-4806-9991-a077675a9ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871901735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3871901735
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3594588958
Short name T471
Test name
Test status
Simulation time 185361300 ps
CPU time 1.15 seconds
Started Jun 04 12:54:43 PM PDT 24
Finished Jun 04 12:54:46 PM PDT 24
Peak memory 200848 kb
Host smart-2e3ae370-cf15-49e9-88ea-7aa537681fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594588958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3594588958
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1584682846
Short name T81
Test name
Test status
Simulation time 192374994 ps
CPU time 1.3 seconds
Started Jun 04 12:54:43 PM PDT 24
Finished Jun 04 12:54:46 PM PDT 24
Peak memory 201032 kb
Host smart-3aaf9833-381f-4569-8286-ee7e21154bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584682846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1584682846
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3067868573
Short name T458
Test name
Test status
Simulation time 4255445605 ps
CPU time 18.94 seconds
Started Jun 04 12:54:56 PM PDT 24
Finished Jun 04 12:55:15 PM PDT 24
Peak memory 200976 kb
Host smart-ab60afb2-6a03-4550-b619-a30a6133cf16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067868573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3067868573
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3682722708
Short name T191
Test name
Test status
Simulation time 125996778 ps
CPU time 1.6 seconds
Started Jun 04 12:54:44 PM PDT 24
Finished Jun 04 12:54:46 PM PDT 24
Peak memory 209056 kb
Host smart-9ef7ebd1-1aed-494a-83d1-4ac9d020ba2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682722708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3682722708
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.442631397
Short name T247
Test name
Test status
Simulation time 222700504 ps
CPU time 1.38 seconds
Started Jun 04 12:55:03 PM PDT 24
Finished Jun 04 12:55:06 PM PDT 24
Peak memory 200784 kb
Host smart-b00f2842-7fe4-400b-8181-4f0b700ffd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442631397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.442631397
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3575927477
Short name T116
Test name
Test status
Simulation time 64206254 ps
CPU time 0.75 seconds
Started Jun 04 12:55:03 PM PDT 24
Finished Jun 04 12:55:05 PM PDT 24
Peak memory 200612 kb
Host smart-4cd0a10b-fe0d-491a-b795-306ad157e5c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575927477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3575927477
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.4046288436
Short name T27
Test name
Test status
Simulation time 2177882356 ps
CPU time 7.47 seconds
Started Jun 04 12:54:59 PM PDT 24
Finished Jun 04 12:55:08 PM PDT 24
Peak memory 222208 kb
Host smart-508a85c9-ae5d-4a57-882e-eb19bef5f9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046288436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.4046288436
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2239487352
Short name T202
Test name
Test status
Simulation time 244036883 ps
CPU time 1.14 seconds
Started Jun 04 12:54:44 PM PDT 24
Finished Jun 04 12:54:46 PM PDT 24
Peak memory 217992 kb
Host smart-25b723ed-10fa-47bf-9748-d62444cdc34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239487352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2239487352
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.1088437040
Short name T198
Test name
Test status
Simulation time 108162496 ps
CPU time 0.77 seconds
Started Jun 04 12:55:00 PM PDT 24
Finished Jun 04 12:55:02 PM PDT 24
Peak memory 200560 kb
Host smart-ff32ee04-828a-4bce-bf35-ddc5fab38e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088437040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1088437040
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2971208345
Short name T340
Test name
Test status
Simulation time 1752159882 ps
CPU time 6.77 seconds
Started Jun 04 12:55:03 PM PDT 24
Finished Jun 04 12:55:11 PM PDT 24
Peak memory 200836 kb
Host smart-e92aebb7-ea4c-4a2f-b5c0-d707521620ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971208345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2971208345
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2570527369
Short name T266
Test name
Test status
Simulation time 148032101 ps
CPU time 1.09 seconds
Started Jun 04 12:54:51 PM PDT 24
Finished Jun 04 12:54:52 PM PDT 24
Peak memory 200852 kb
Host smart-524e3449-0cd8-40bb-948c-483fe501079b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570527369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2570527369
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.4282713966
Short name T438
Test name
Test status
Simulation time 253747807 ps
CPU time 1.47 seconds
Started Jun 04 12:54:55 PM PDT 24
Finished Jun 04 12:54:57 PM PDT 24
Peak memory 200952 kb
Host smart-127cb539-6ca5-421c-9b99-058d0c295694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282713966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.4282713966
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1804724881
Short name T125
Test name
Test status
Simulation time 4009180093 ps
CPU time 13.95 seconds
Started Jun 04 12:54:52 PM PDT 24
Finished Jun 04 12:55:07 PM PDT 24
Peak memory 209380 kb
Host smart-8a25c679-2dc4-4ed2-bb81-5a4664413a34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804724881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1804724881
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1676428469
Short name T82
Test name
Test status
Simulation time 430247935 ps
CPU time 2.43 seconds
Started Jun 04 12:55:08 PM PDT 24
Finished Jun 04 12:55:11 PM PDT 24
Peak memory 200720 kb
Host smart-5bef4449-421e-4645-b6da-6b13799fcb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676428469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1676428469
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3594202305
Short name T527
Test name
Test status
Simulation time 192398515 ps
CPU time 1.25 seconds
Started Jun 04 12:54:58 PM PDT 24
Finished Jun 04 12:55:00 PM PDT 24
Peak memory 200864 kb
Host smart-db8ec95a-5154-40c5-9448-ea19f3d27b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594202305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3594202305
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1722227052
Short name T159
Test name
Test status
Simulation time 58826108 ps
CPU time 0.75 seconds
Started Jun 04 12:54:54 PM PDT 24
Finished Jun 04 12:54:56 PM PDT 24
Peak memory 200612 kb
Host smart-bad50cd5-812b-4527-8a6d-1d2a31b118d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722227052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1722227052
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.888967064
Short name T48
Test name
Test status
Simulation time 2348464764 ps
CPU time 7.92 seconds
Started Jun 04 12:54:56 PM PDT 24
Finished Jun 04 12:55:04 PM PDT 24
Peak memory 218460 kb
Host smart-17db9d33-f808-4e72-b460-ae68036784b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888967064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.888967064
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1724033587
Short name T357
Test name
Test status
Simulation time 244112517 ps
CPU time 1.14 seconds
Started Jun 04 12:54:58 PM PDT 24
Finished Jun 04 12:55:01 PM PDT 24
Peak memory 218008 kb
Host smart-187eec20-255f-43b2-a46a-bcf7f9b3c9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724033587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1724033587
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.377962382
Short name T11
Test name
Test status
Simulation time 208449871 ps
CPU time 0.92 seconds
Started Jun 04 12:55:03 PM PDT 24
Finished Jun 04 12:55:05 PM PDT 24
Peak memory 200596 kb
Host smart-a6c6f745-f132-4e32-85f9-32b949b7b1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377962382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.377962382
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.3982142662
Short name T270
Test name
Test status
Simulation time 1671870402 ps
CPU time 5.72 seconds
Started Jun 04 12:55:03 PM PDT 24
Finished Jun 04 12:55:10 PM PDT 24
Peak memory 200968 kb
Host smart-cd9abb8f-90ac-47b5-a036-1ec02dddf8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982142662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3982142662
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3327544745
Short name T257
Test name
Test status
Simulation time 154608968 ps
CPU time 1.25 seconds
Started Jun 04 12:55:05 PM PDT 24
Finished Jun 04 12:55:07 PM PDT 24
Peak memory 200856 kb
Host smart-532ed38d-02ec-44dd-a324-486c12d07159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327544745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3327544745
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3290518952
Short name T482
Test name
Test status
Simulation time 112658329 ps
CPU time 1.21 seconds
Started Jun 04 12:54:55 PM PDT 24
Finished Jun 04 12:54:57 PM PDT 24
Peak memory 200948 kb
Host smart-59c47350-bc02-4a90-843b-972a7866dba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290518952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3290518952
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2338300332
Short name T327
Test name
Test status
Simulation time 3686760693 ps
CPU time 14.04 seconds
Started Jun 04 12:54:56 PM PDT 24
Finished Jun 04 12:55:10 PM PDT 24
Peak memory 201060 kb
Host smart-529e31a3-54b1-4f5c-8e84-a45211120124
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338300332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2338300332
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2545043544
Short name T49
Test name
Test status
Simulation time 414953651 ps
CPU time 2.24 seconds
Started Jun 04 12:54:44 PM PDT 24
Finished Jun 04 12:54:48 PM PDT 24
Peak memory 209056 kb
Host smart-5b1ef198-efa8-45fa-955c-131244a09dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545043544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2545043544
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3795540234
Short name T229
Test name
Test status
Simulation time 68329641 ps
CPU time 0.78 seconds
Started Jun 04 12:54:52 PM PDT 24
Finished Jun 04 12:54:54 PM PDT 24
Peak memory 200856 kb
Host smart-8b962ba1-bffb-496c-a59d-1c2a17682d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795540234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3795540234
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.1879539704
Short name T253
Test name
Test status
Simulation time 81954178 ps
CPU time 0.82 seconds
Started Jun 04 12:54:04 PM PDT 24
Finished Jun 04 12:54:06 PM PDT 24
Peak memory 200660 kb
Host smart-38acba64-4634-4e85-af77-34540bbe7152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879539704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1879539704
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2903590486
Short name T26
Test name
Test status
Simulation time 2354929807 ps
CPU time 7.54 seconds
Started Jun 04 12:54:04 PM PDT 24
Finished Jun 04 12:54:12 PM PDT 24
Peak memory 218544 kb
Host smart-8a2fd674-9220-472f-bec7-7f8a67915b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903590486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2903590486
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2378269613
Short name T232
Test name
Test status
Simulation time 244583100 ps
CPU time 1.05 seconds
Started Jun 04 12:54:09 PM PDT 24
Finished Jun 04 12:54:12 PM PDT 24
Peak memory 217920 kb
Host smart-b5c3550e-30d1-4712-bc72-b12646ada963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378269613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2378269613
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.4080349935
Short name T392
Test name
Test status
Simulation time 189495637 ps
CPU time 0.93 seconds
Started Jun 04 12:54:02 PM PDT 24
Finished Jun 04 12:54:03 PM PDT 24
Peak memory 200568 kb
Host smart-9d70e138-f92f-4818-b0ec-d7ad2084b7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080349935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.4080349935
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2280705183
Short name T226
Test name
Test status
Simulation time 1547747768 ps
CPU time 5.97 seconds
Started Jun 04 12:54:05 PM PDT 24
Finished Jun 04 12:54:12 PM PDT 24
Peak memory 200888 kb
Host smart-21abd0d1-a12d-47a7-838e-5e3f8bdd40a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280705183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2280705183
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.2458740012
Short name T74
Test name
Test status
Simulation time 8408387759 ps
CPU time 13.24 seconds
Started Jun 04 12:54:14 PM PDT 24
Finished Jun 04 12:54:28 PM PDT 24
Peak memory 217616 kb
Host smart-372688e8-c7b0-497a-9836-4ad5f76979eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458740012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2458740012
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1968378942
Short name T178
Test name
Test status
Simulation time 173481609 ps
CPU time 1.19 seconds
Started Jun 04 12:54:06 PM PDT 24
Finished Jun 04 12:54:08 PM PDT 24
Peak memory 200860 kb
Host smart-ecff6407-092e-45cb-a073-5fbad552b0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968378942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1968378942
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1259298767
Short name T294
Test name
Test status
Simulation time 206705633 ps
CPU time 1.37 seconds
Started Jun 04 12:54:05 PM PDT 24
Finished Jun 04 12:54:07 PM PDT 24
Peak memory 200996 kb
Host smart-6da6ec84-5c6e-4df8-94d6-482d481f21a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259298767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1259298767
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3699840030
Short name T323
Test name
Test status
Simulation time 3610924892 ps
CPU time 15.4 seconds
Started Jun 04 12:54:14 PM PDT 24
Finished Jun 04 12:54:30 PM PDT 24
Peak memory 201188 kb
Host smart-e70215dd-eace-438d-8fc5-8f318fe46287
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699840030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3699840030
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2112053477
Short name T287
Test name
Test status
Simulation time 415775777 ps
CPU time 2.46 seconds
Started Jun 04 12:54:07 PM PDT 24
Finished Jun 04 12:54:10 PM PDT 24
Peak memory 208980 kb
Host smart-35629aa5-0140-4fe2-913f-adb32444ef68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112053477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2112053477
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.560251154
Short name T8
Test name
Test status
Simulation time 240833451 ps
CPU time 1.39 seconds
Started Jun 04 12:54:03 PM PDT 24
Finished Jun 04 12:54:06 PM PDT 24
Peak memory 200792 kb
Host smart-20b42828-9504-4118-a8ae-9ba3f2274d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560251154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.560251154
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3549086628
Short name T531
Test name
Test status
Simulation time 75896408 ps
CPU time 0.79 seconds
Started Jun 04 12:55:12 PM PDT 24
Finished Jun 04 12:55:15 PM PDT 24
Peak memory 200600 kb
Host smart-215b7261-de79-47b1-a09b-6e6026abb945
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549086628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3549086628
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.3723875
Short name T416
Test name
Test status
Simulation time 1232458133 ps
CPU time 5.62 seconds
Started Jun 04 12:55:01 PM PDT 24
Finished Jun 04 12:55:07 PM PDT 24
Peak memory 218428 kb
Host smart-29dd6a33-bc0b-43dc-9302-7af257449725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3723875
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.865932878
Short name T207
Test name
Test status
Simulation time 246575724 ps
CPU time 1.05 seconds
Started Jun 04 12:54:55 PM PDT 24
Finished Jun 04 12:54:57 PM PDT 24
Peak memory 217968 kb
Host smart-fb58950a-db29-4b7d-8722-7c043ec27cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865932878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.865932878
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.906562012
Short name T2
Test name
Test status
Simulation time 230239487 ps
CPU time 0.94 seconds
Started Jun 04 12:54:56 PM PDT 24
Finished Jun 04 12:54:58 PM PDT 24
Peak memory 200580 kb
Host smart-ee5c243c-37ae-48ca-933b-fdd1f2adada5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906562012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.906562012
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.780210918
Short name T117
Test name
Test status
Simulation time 827040591 ps
CPU time 4.14 seconds
Started Jun 04 12:54:59 PM PDT 24
Finished Jun 04 12:55:04 PM PDT 24
Peak memory 201036 kb
Host smart-142d4c8d-09f0-4b2c-b79b-e563923348f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780210918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.780210918
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1404186373
Short name T298
Test name
Test status
Simulation time 186950415 ps
CPU time 1.24 seconds
Started Jun 04 12:54:59 PM PDT 24
Finished Jun 04 12:55:02 PM PDT 24
Peak memory 200776 kb
Host smart-812c4606-55af-4c55-b22a-92efa23376ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404186373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1404186373
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.1965027060
Short name T184
Test name
Test status
Simulation time 112067271 ps
CPU time 1.12 seconds
Started Jun 04 12:54:40 PM PDT 24
Finished Jun 04 12:54:43 PM PDT 24
Peak memory 200956 kb
Host smart-55ef0382-7279-49d8-bd06-ca8d1744dcc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965027060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1965027060
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.133249094
Short name T394
Test name
Test status
Simulation time 122494853 ps
CPU time 1.58 seconds
Started Jun 04 12:55:05 PM PDT 24
Finished Jun 04 12:55:07 PM PDT 24
Peak memory 200844 kb
Host smart-362b54c1-babd-4e48-9ff3-98207cc2b69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133249094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.133249094
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.4232029633
Short name T302
Test name
Test status
Simulation time 124290311 ps
CPU time 0.9 seconds
Started Jun 04 12:54:42 PM PDT 24
Finished Jun 04 12:54:45 PM PDT 24
Peak memory 200776 kb
Host smart-7ec96f08-9b8a-483e-b0ad-59dd51cbe2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232029633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.4232029633
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3298218878
Short name T358
Test name
Test status
Simulation time 63194214 ps
CPU time 0.73 seconds
Started Jun 04 12:54:59 PM PDT 24
Finished Jun 04 12:55:01 PM PDT 24
Peak memory 200664 kb
Host smart-44aaf406-8e5a-40bb-9032-e9e7c2b1c077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298218878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3298218878
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.550919819
Short name T431
Test name
Test status
Simulation time 1889787286 ps
CPU time 7.4 seconds
Started Jun 04 12:55:09 PM PDT 24
Finished Jun 04 12:55:23 PM PDT 24
Peak memory 217956 kb
Host smart-8367bae8-0c47-445e-bd70-70102b3a3bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550919819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.550919819
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.950880554
Short name T479
Test name
Test status
Simulation time 243403653 ps
CPU time 1.1 seconds
Started Jun 04 12:54:52 PM PDT 24
Finished Jun 04 12:54:55 PM PDT 24
Peak memory 218132 kb
Host smart-3579fa7a-6ce9-41ae-a502-16503a08d6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950880554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.950880554
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.3349397146
Short name T370
Test name
Test status
Simulation time 112858615 ps
CPU time 0.77 seconds
Started Jun 04 12:54:59 PM PDT 24
Finished Jun 04 12:55:02 PM PDT 24
Peak memory 200560 kb
Host smart-0d2ec9c1-86fa-4899-b4be-ef510582165d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349397146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3349397146
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2734903973
Short name T506
Test name
Test status
Simulation time 1548626803 ps
CPU time 6.18 seconds
Started Jun 04 12:54:56 PM PDT 24
Finished Jun 04 12:55:03 PM PDT 24
Peak memory 201084 kb
Host smart-233ec2b6-32b4-4974-bf76-14136624cb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734903973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2734903973
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.46148411
Short name T169
Test name
Test status
Simulation time 108944637 ps
CPU time 1.04 seconds
Started Jun 04 12:54:59 PM PDT 24
Finished Jun 04 12:55:01 PM PDT 24
Peak memory 200860 kb
Host smart-13b638ca-6c1d-4115-96f4-eb7862754600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46148411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.46148411
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2504729402
Short name T433
Test name
Test status
Simulation time 209147841 ps
CPU time 1.39 seconds
Started Jun 04 12:55:13 PM PDT 24
Finished Jun 04 12:55:16 PM PDT 24
Peak memory 201024 kb
Host smart-b4b896ef-501c-459b-8ae2-ec704a52bffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504729402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2504729402
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1074071060
Short name T427
Test name
Test status
Simulation time 9408934339 ps
CPU time 31.29 seconds
Started Jun 04 12:55:13 PM PDT 24
Finished Jun 04 12:55:46 PM PDT 24
Peak memory 209340 kb
Host smart-e542cb03-5611-4eaf-b060-3aa711f38f8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074071060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1074071060
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1208669856
Short name T181
Test name
Test status
Simulation time 387614742 ps
CPU time 2.3 seconds
Started Jun 04 12:54:49 PM PDT 24
Finished Jun 04 12:54:53 PM PDT 24
Peak memory 200784 kb
Host smart-eff8064a-5ebe-43de-a79f-1d8f1d8b6783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208669856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1208669856
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1960942694
Short name T196
Test name
Test status
Simulation time 126823954 ps
CPU time 1.16 seconds
Started Jun 04 12:55:03 PM PDT 24
Finished Jun 04 12:55:05 PM PDT 24
Peak memory 200788 kb
Host smart-d9e26521-5a90-402d-a51f-5c7a915275d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960942694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1960942694
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3537093747
Short name T495
Test name
Test status
Simulation time 75491731 ps
CPU time 0.76 seconds
Started Jun 04 12:54:50 PM PDT 24
Finished Jun 04 12:54:52 PM PDT 24
Peak memory 200668 kb
Host smart-d87bbfa8-d454-41c9-b8f0-95201dc8a6a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537093747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3537093747
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2050394044
Short name T297
Test name
Test status
Simulation time 1222740039 ps
CPU time 6.17 seconds
Started Jun 04 12:54:59 PM PDT 24
Finished Jun 04 12:55:06 PM PDT 24
Peak memory 217980 kb
Host smart-dc172d70-1af2-4936-9caf-cb047deb76ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050394044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2050394044
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2199716393
Short name T1
Test name
Test status
Simulation time 244000220 ps
CPU time 1.05 seconds
Started Jun 04 12:55:10 PM PDT 24
Finished Jun 04 12:55:13 PM PDT 24
Peak memory 217960 kb
Host smart-a0c13480-16df-44a8-9ea8-36c76ae66577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199716393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2199716393
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1969144041
Short name T276
Test name
Test status
Simulation time 238912808 ps
CPU time 0.96 seconds
Started Jun 04 12:54:58 PM PDT 24
Finished Jun 04 12:54:59 PM PDT 24
Peak memory 200672 kb
Host smart-55b54417-7ebe-4181-ab5a-239aa915d247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969144041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1969144041
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.2478802747
Short name T524
Test name
Test status
Simulation time 1550588608 ps
CPU time 6.19 seconds
Started Jun 04 12:55:00 PM PDT 24
Finished Jun 04 12:55:07 PM PDT 24
Peak memory 201024 kb
Host smart-58f9a49e-cd30-430e-91ae-7f7a3f2a1be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478802747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2478802747
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1043840226
Short name T504
Test name
Test status
Simulation time 187242335 ps
CPU time 1.31 seconds
Started Jun 04 12:55:04 PM PDT 24
Finished Jun 04 12:55:06 PM PDT 24
Peak memory 200828 kb
Host smart-39d2108a-3c70-488b-b09f-9e03124dea20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043840226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1043840226
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.252782933
Short name T289
Test name
Test status
Simulation time 119860443 ps
CPU time 1.18 seconds
Started Jun 04 12:55:12 PM PDT 24
Finished Jun 04 12:55:15 PM PDT 24
Peak memory 201036 kb
Host smart-6337f7cb-251b-4415-8727-e22cedc018dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252782933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.252782933
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.318886130
Short name T467
Test name
Test status
Simulation time 3092635554 ps
CPU time 13.81 seconds
Started Jun 04 12:54:57 PM PDT 24
Finished Jun 04 12:55:12 PM PDT 24
Peak memory 201176 kb
Host smart-8fc2e44f-2379-41d1-a183-c9d69a0d49d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318886130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.318886130
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.748314564
Short name T10
Test name
Test status
Simulation time 139326713 ps
CPU time 1.63 seconds
Started Jun 04 12:54:52 PM PDT 24
Finished Jun 04 12:54:55 PM PDT 24
Peak memory 200824 kb
Host smart-e60d7399-f18c-4daf-b460-e18a6c311587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748314564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.748314564
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3927223593
Short name T428
Test name
Test status
Simulation time 110190397 ps
CPU time 0.92 seconds
Started Jun 04 12:54:49 PM PDT 24
Finished Jun 04 12:54:51 PM PDT 24
Peak memory 200832 kb
Host smart-f0b95fec-3c86-46e7-b01c-80ffd43f7d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927223593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3927223593
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2072516622
Short name T361
Test name
Test status
Simulation time 63416245 ps
CPU time 0.74 seconds
Started Jun 04 12:55:11 PM PDT 24
Finished Jun 04 12:55:14 PM PDT 24
Peak memory 200672 kb
Host smart-953a7ece-3c54-49a7-a401-c5f01b773281
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072516622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2072516622
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.233275370
Short name T352
Test name
Test status
Simulation time 1229043222 ps
CPU time 5.71 seconds
Started Jun 04 12:55:09 PM PDT 24
Finished Jun 04 12:55:16 PM PDT 24
Peak memory 217216 kb
Host smart-a1492207-d19f-4928-8617-e2c36d08f97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233275370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.233275370
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.247697341
Short name T245
Test name
Test status
Simulation time 244082206 ps
CPU time 1.11 seconds
Started Jun 04 12:55:03 PM PDT 24
Finished Jun 04 12:55:05 PM PDT 24
Peak memory 217952 kb
Host smart-8ff27f71-4bf8-4515-b8d6-96748b959493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247697341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.247697341
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2156082429
Short name T324
Test name
Test status
Simulation time 109442068 ps
CPU time 0.75 seconds
Started Jun 04 12:55:09 PM PDT 24
Finished Jun 04 12:55:11 PM PDT 24
Peak memory 200600 kb
Host smart-8d85de80-904c-4a25-af36-4fe18a174aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156082429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2156082429
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.191356072
Short name T481
Test name
Test status
Simulation time 1632590653 ps
CPU time 6.41 seconds
Started Jun 04 12:54:58 PM PDT 24
Finished Jun 04 12:55:05 PM PDT 24
Peak memory 201016 kb
Host smart-8cc7c854-6ab7-4e69-9ac2-f38f41b94e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191356072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.191356072
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.625656046
Short name T145
Test name
Test status
Simulation time 95204290 ps
CPU time 0.92 seconds
Started Jun 04 12:55:08 PM PDT 24
Finished Jun 04 12:55:09 PM PDT 24
Peak memory 200828 kb
Host smart-d80ffc1d-4159-444c-87d4-554fe6bc7ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625656046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.625656046
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.525557503
Short name T69
Test name
Test status
Simulation time 113117133 ps
CPU time 1.24 seconds
Started Jun 04 12:55:01 PM PDT 24
Finished Jun 04 12:55:03 PM PDT 24
Peak memory 201028 kb
Host smart-22d3ee17-4d86-40e7-810f-a59f79c2a972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525557503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.525557503
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.835305385
Short name T182
Test name
Test status
Simulation time 131826240 ps
CPU time 1.69 seconds
Started Jun 04 12:54:57 PM PDT 24
Finished Jun 04 12:55:00 PM PDT 24
Peak memory 200852 kb
Host smart-a8fd1762-5443-4545-a0a5-536c0c9b5c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835305385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.835305385
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3237745497
Short name T259
Test name
Test status
Simulation time 64521795 ps
CPU time 0.76 seconds
Started Jun 04 12:54:59 PM PDT 24
Finished Jun 04 12:55:00 PM PDT 24
Peak memory 200428 kb
Host smart-c3e87fec-cc82-4907-b4a1-8206da01f36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237745497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3237745497
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2447276771
Short name T443
Test name
Test status
Simulation time 71454606 ps
CPU time 0.74 seconds
Started Jun 04 12:54:58 PM PDT 24
Finished Jun 04 12:55:00 PM PDT 24
Peak memory 200676 kb
Host smart-1d689463-0b42-46df-87fd-13e7e52333eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447276771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2447276771
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2624078801
Short name T30
Test name
Test status
Simulation time 2171627411 ps
CPU time 7.66 seconds
Started Jun 04 12:55:00 PM PDT 24
Finished Jun 04 12:55:09 PM PDT 24
Peak memory 218560 kb
Host smart-4acc9e5a-e1a3-49d5-8a39-3baca18bd039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624078801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2624078801
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.295836910
Short name T167
Test name
Test status
Simulation time 245029627 ps
CPU time 1.08 seconds
Started Jun 04 12:55:00 PM PDT 24
Finished Jun 04 12:55:02 PM PDT 24
Peak memory 218036 kb
Host smart-ab749d11-0256-435a-a243-d6846152e511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295836910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.295836910
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.1415799258
Short name T15
Test name
Test status
Simulation time 166369446 ps
CPU time 0.83 seconds
Started Jun 04 12:55:11 PM PDT 24
Finished Jun 04 12:55:14 PM PDT 24
Peak memory 200640 kb
Host smart-d99f382f-f904-4924-bc88-0b15ddcc0d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415799258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1415799258
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2567500871
Short name T462
Test name
Test status
Simulation time 1472377078 ps
CPU time 5.52 seconds
Started Jun 04 12:54:52 PM PDT 24
Finished Jun 04 12:54:58 PM PDT 24
Peak memory 201028 kb
Host smart-620cf32f-b876-4c84-b411-4ac376677fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567500871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2567500871
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.4126760166
Short name T469
Test name
Test status
Simulation time 186785089 ps
CPU time 1.21 seconds
Started Jun 04 12:55:14 PM PDT 24
Finished Jun 04 12:55:17 PM PDT 24
Peak memory 200764 kb
Host smart-8182b0d9-f393-4019-8415-67d52e3c74c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126760166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.4126760166
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1926985049
Short name T337
Test name
Test status
Simulation time 263691014 ps
CPU time 1.48 seconds
Started Jun 04 12:55:13 PM PDT 24
Finished Jun 04 12:55:17 PM PDT 24
Peak memory 200988 kb
Host smart-0e8e8624-03a0-417c-95c9-8fa05aab31d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926985049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1926985049
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1714241599
Short name T144
Test name
Test status
Simulation time 2514923232 ps
CPU time 8.94 seconds
Started Jun 04 12:55:07 PM PDT 24
Finished Jun 04 12:55:17 PM PDT 24
Peak memory 209268 kb
Host smart-8ffa80fd-6150-461e-a386-22e0f17da94a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714241599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1714241599
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1313945124
Short name T272
Test name
Test status
Simulation time 141904916 ps
CPU time 1.72 seconds
Started Jun 04 12:54:57 PM PDT 24
Finished Jun 04 12:55:00 PM PDT 24
Peak memory 200796 kb
Host smart-2cf3b484-8f13-4793-8464-08a0f79b917a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313945124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1313945124
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.821011588
Short name T150
Test name
Test status
Simulation time 121066721 ps
CPU time 1.06 seconds
Started Jun 04 12:54:52 PM PDT 24
Finished Jun 04 12:54:55 PM PDT 24
Peak memory 200800 kb
Host smart-a7bddb40-5644-4654-ad92-c1fed84c6db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821011588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.821011588
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.866360473
Short name T376
Test name
Test status
Simulation time 84115161 ps
CPU time 0.85 seconds
Started Jun 04 12:55:11 PM PDT 24
Finished Jun 04 12:55:13 PM PDT 24
Peak memory 200700 kb
Host smart-f584de87-4044-4f3c-99f8-6bbfb6136331
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866360473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.866360473
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.3255375978
Short name T382
Test name
Test status
Simulation time 1873494397 ps
CPU time 7.81 seconds
Started Jun 04 12:55:45 PM PDT 24
Finished Jun 04 12:55:53 PM PDT 24
Peak memory 218412 kb
Host smart-b1167704-cd33-44ec-876f-b16be6812952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255375978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.3255375978
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3445771167
Short name T36
Test name
Test status
Simulation time 244579739 ps
CPU time 1.22 seconds
Started Jun 04 12:55:06 PM PDT 24
Finished Jun 04 12:55:08 PM PDT 24
Peak memory 218036 kb
Host smart-5fdac8c7-bc74-40f5-9bb5-5e153c9a0a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445771167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3445771167
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.538733788
Short name T17
Test name
Test status
Simulation time 164241685 ps
CPU time 0.87 seconds
Started Jun 04 12:55:10 PM PDT 24
Finished Jun 04 12:55:12 PM PDT 24
Peak memory 200576 kb
Host smart-1ed5aa50-82ef-4c46-a9e3-07d2f46b9462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538733788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.538733788
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.3936450678
Short name T442
Test name
Test status
Simulation time 1873127364 ps
CPU time 7.08 seconds
Started Jun 04 12:54:57 PM PDT 24
Finished Jun 04 12:55:05 PM PDT 24
Peak memory 201028 kb
Host smart-fc018d2b-860b-4deb-899c-75ad01481ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936450678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3936450678
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1261644425
Short name T263
Test name
Test status
Simulation time 141410066 ps
CPU time 1.09 seconds
Started Jun 04 12:55:12 PM PDT 24
Finished Jun 04 12:55:16 PM PDT 24
Peak memory 200804 kb
Host smart-bb81a7b3-3608-41c9-b20b-df2f5c5f2006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261644425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1261644425
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2889342164
Short name T355
Test name
Test status
Simulation time 119702052 ps
CPU time 1.17 seconds
Started Jun 04 12:55:09 PM PDT 24
Finished Jun 04 12:55:12 PM PDT 24
Peak memory 201016 kb
Host smart-f9d298ef-ab0c-4bad-9e85-0284f2e95142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889342164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2889342164
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.2933447376
Short name T305
Test name
Test status
Simulation time 4035017718 ps
CPU time 17.66 seconds
Started Jun 04 12:55:10 PM PDT 24
Finished Jun 04 12:55:29 PM PDT 24
Peak memory 211160 kb
Host smart-1b521fca-2505-47e6-bb8c-231ae84f0133
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933447376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2933447376
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.2896445703
Short name T424
Test name
Test status
Simulation time 128982808 ps
CPU time 1.56 seconds
Started Jun 04 12:55:10 PM PDT 24
Finished Jun 04 12:55:13 PM PDT 24
Peak memory 200800 kb
Host smart-f808dc12-3d96-4949-b4bf-62cdcf6023d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896445703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2896445703
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3035854968
Short name T310
Test name
Test status
Simulation time 229871340 ps
CPU time 1.42 seconds
Started Jun 04 12:55:09 PM PDT 24
Finished Jun 04 12:55:11 PM PDT 24
Peak memory 200980 kb
Host smart-f1e4d25a-5acb-4034-8022-3f1a1e1ca621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035854968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3035854968
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.863833606
Short name T217
Test name
Test status
Simulation time 79153560 ps
CPU time 0.84 seconds
Started Jun 04 12:55:14 PM PDT 24
Finished Jun 04 12:55:17 PM PDT 24
Peak memory 200724 kb
Host smart-5c98a427-271b-4429-898d-6133fc3b5716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863833606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.863833606
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.2181470516
Short name T496
Test name
Test status
Simulation time 2166882208 ps
CPU time 7.58 seconds
Started Jun 04 12:55:14 PM PDT 24
Finished Jun 04 12:55:23 PM PDT 24
Peak memory 222700 kb
Host smart-6651fc71-9c7e-405c-b66f-3c0e7b9284e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181470516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2181470516
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2202955472
Short name T507
Test name
Test status
Simulation time 244576186 ps
CPU time 1 seconds
Started Jun 04 12:55:09 PM PDT 24
Finished Jun 04 12:55:11 PM PDT 24
Peak memory 217964 kb
Host smart-26a4a954-dfe1-4ae0-97ea-0d776ae071db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202955472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2202955472
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.4236554681
Short name T542
Test name
Test status
Simulation time 154537601 ps
CPU time 0.9 seconds
Started Jun 04 12:55:06 PM PDT 24
Finished Jun 04 12:55:08 PM PDT 24
Peak memory 200704 kb
Host smart-bd9bbdfe-dcd1-4b9f-a8a1-0812954c1463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236554681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.4236554681
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.551854585
Short name T385
Test name
Test status
Simulation time 768837433 ps
CPU time 4.12 seconds
Started Jun 04 12:55:08 PM PDT 24
Finished Jun 04 12:55:13 PM PDT 24
Peak memory 200908 kb
Host smart-b86d6296-190e-420c-b4db-f8b6b4de92c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551854585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.551854585
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1476203372
Short name T154
Test name
Test status
Simulation time 148024941 ps
CPU time 1.05 seconds
Started Jun 04 12:55:12 PM PDT 24
Finished Jun 04 12:55:15 PM PDT 24
Peak memory 200780 kb
Host smart-d9c91966-9a4c-471f-a34a-bd59c30fef05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476203372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1476203372
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.2499986083
Short name T452
Test name
Test status
Simulation time 233786919 ps
CPU time 1.43 seconds
Started Jun 04 12:55:14 PM PDT 24
Finished Jun 04 12:55:17 PM PDT 24
Peak memory 201024 kb
Host smart-40b0c222-9ba8-4e6d-a778-ad82620733fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499986083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2499986083
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.894206415
Short name T282
Test name
Test status
Simulation time 4725186390 ps
CPU time 19.89 seconds
Started Jun 04 12:55:13 PM PDT 24
Finished Jun 04 12:55:35 PM PDT 24
Peak memory 209388 kb
Host smart-8ec6458c-3198-448a-9f10-67709d1f5b66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894206415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.894206415
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.660812631
Short name T303
Test name
Test status
Simulation time 266456076 ps
CPU time 1.89 seconds
Started Jun 04 12:55:12 PM PDT 24
Finished Jun 04 12:55:20 PM PDT 24
Peak memory 200756 kb
Host smart-70eec83a-c40a-43d7-9bec-4094707786c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660812631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.660812631
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.3691754047
Short name T148
Test name
Test status
Simulation time 74867794 ps
CPU time 0.78 seconds
Started Jun 04 12:55:12 PM PDT 24
Finished Jun 04 12:55:15 PM PDT 24
Peak memory 200780 kb
Host smart-1510a927-81c5-4a57-9f04-20fe6542e05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691754047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.3691754047
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.219837289
Short name T344
Test name
Test status
Simulation time 80531205 ps
CPU time 0.86 seconds
Started Jun 04 12:55:09 PM PDT 24
Finished Jun 04 12:55:12 PM PDT 24
Peak memory 200680 kb
Host smart-97d50903-a0a6-4968-882e-594d8e62bf2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219837289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.219837289
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3197597533
Short name T32
Test name
Test status
Simulation time 1223449396 ps
CPU time 5.27 seconds
Started Jun 04 12:55:10 PM PDT 24
Finished Jun 04 12:55:18 PM PDT 24
Peak memory 218428 kb
Host smart-10a46af3-745c-4f13-98cd-2ab987d289c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197597533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3197597533
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2885028026
Short name T414
Test name
Test status
Simulation time 243773897 ps
CPU time 1.04 seconds
Started Jun 04 12:55:11 PM PDT 24
Finished Jun 04 12:55:14 PM PDT 24
Peak memory 218108 kb
Host smart-6e110d47-86ca-4e18-9ed1-0e8e655ae082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885028026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2885028026
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.4189134180
Short name T483
Test name
Test status
Simulation time 110615598 ps
CPU time 0.78 seconds
Started Jun 04 12:55:03 PM PDT 24
Finished Jun 04 12:55:05 PM PDT 24
Peak memory 200556 kb
Host smart-0914a98f-ec75-4d11-ae6a-650c8d43f7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189134180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.4189134180
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1822848569
Short name T371
Test name
Test status
Simulation time 726570314 ps
CPU time 3.61 seconds
Started Jun 04 12:55:06 PM PDT 24
Finished Jun 04 12:55:10 PM PDT 24
Peak memory 200940 kb
Host smart-93a86552-c976-472a-b720-8c7b6e6d8253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822848569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1822848569
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.4056277597
Short name T332
Test name
Test status
Simulation time 138527408 ps
CPU time 1.06 seconds
Started Jun 04 12:55:14 PM PDT 24
Finished Jun 04 12:55:17 PM PDT 24
Peak memory 200832 kb
Host smart-04b6a84c-1d04-4fb2-9279-c3f70a2d6a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056277597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.4056277597
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2081599082
Short name T369
Test name
Test status
Simulation time 187413404 ps
CPU time 1.35 seconds
Started Jun 04 12:55:11 PM PDT 24
Finished Jun 04 12:55:14 PM PDT 24
Peak memory 200708 kb
Host smart-073f39e0-d67b-4188-b83e-39ddea0aac3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081599082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2081599082
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.967751763
Short name T383
Test name
Test status
Simulation time 7048375762 ps
CPU time 29.97 seconds
Started Jun 04 12:55:11 PM PDT 24
Finished Jun 04 12:55:43 PM PDT 24
Peak memory 208956 kb
Host smart-5113ec5b-c669-4872-accb-41a5d7438025
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967751763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.967751763
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.1514833471
Short name T436
Test name
Test status
Simulation time 422285330 ps
CPU time 2.36 seconds
Started Jun 04 12:55:10 PM PDT 24
Finished Jun 04 12:55:14 PM PDT 24
Peak memory 209012 kb
Host smart-186cfea8-66e7-4ecb-bcb8-14c800803567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514833471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1514833471
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.4266088391
Short name T234
Test name
Test status
Simulation time 248363246 ps
CPU time 1.58 seconds
Started Jun 04 12:55:08 PM PDT 24
Finished Jun 04 12:55:10 PM PDT 24
Peak memory 200820 kb
Host smart-1f62f0b4-73da-4fee-9ba6-4b91be1a1751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266088391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.4266088391
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.4016755999
Short name T285
Test name
Test status
Simulation time 63830637 ps
CPU time 0.76 seconds
Started Jun 04 12:55:11 PM PDT 24
Finished Jun 04 12:55:14 PM PDT 24
Peak memory 200696 kb
Host smart-52dd730d-d393-465e-8520-3cb4553ca5d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016755999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.4016755999
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3621569058
Short name T56
Test name
Test status
Simulation time 1232032948 ps
CPU time 5.27 seconds
Started Jun 04 12:55:12 PM PDT 24
Finished Jun 04 12:55:19 PM PDT 24
Peak memory 218428 kb
Host smart-fe2aade3-74d4-4e41-a9f0-5e46f99a35a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621569058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3621569058
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2775263647
Short name T402
Test name
Test status
Simulation time 244439610 ps
CPU time 1.06 seconds
Started Jun 04 12:55:09 PM PDT 24
Finished Jun 04 12:55:12 PM PDT 24
Peak memory 218176 kb
Host smart-cf6dce95-7a5e-4e25-98d2-2e973abf0074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775263647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2775263647
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2313099120
Short name T449
Test name
Test status
Simulation time 199537103 ps
CPU time 0.86 seconds
Started Jun 04 12:55:14 PM PDT 24
Finished Jun 04 12:55:16 PM PDT 24
Peak memory 200608 kb
Host smart-bcd47259-d880-4c12-bf93-1150cc2c496a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313099120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2313099120
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1316845251
Short name T411
Test name
Test status
Simulation time 1629342761 ps
CPU time 5.91 seconds
Started Jun 04 12:55:14 PM PDT 24
Finished Jun 04 12:55:22 PM PDT 24
Peak memory 200952 kb
Host smart-a1752c86-e578-4477-b2af-f0cbe9311dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316845251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1316845251
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3701174644
Short name T388
Test name
Test status
Simulation time 113161404 ps
CPU time 1.02 seconds
Started Jun 04 12:55:07 PM PDT 24
Finished Jun 04 12:55:09 PM PDT 24
Peak memory 200820 kb
Host smart-1a0a54a9-5182-4e12-8c6b-59d8880be807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701174644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3701174644
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3399759310
Short name T220
Test name
Test status
Simulation time 200442617 ps
CPU time 1.34 seconds
Started Jun 04 12:55:12 PM PDT 24
Finished Jun 04 12:55:16 PM PDT 24
Peak memory 201036 kb
Host smart-e749ecc0-260b-4194-bcb6-9aca1ff8a96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399759310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3399759310
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.1394356296
Short name T214
Test name
Test status
Simulation time 400694872 ps
CPU time 2.31 seconds
Started Jun 04 12:55:12 PM PDT 24
Finished Jun 04 12:55:16 PM PDT 24
Peak memory 200828 kb
Host smart-ecae8923-cf1b-4465-8323-92a9f95583a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394356296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1394356296
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2968351362
Short name T162
Test name
Test status
Simulation time 131147347 ps
CPU time 1.07 seconds
Started Jun 04 12:55:09 PM PDT 24
Finished Jun 04 12:55:12 PM PDT 24
Peak memory 200784 kb
Host smart-cb1b0a65-5684-453a-bc15-6ae80497f177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968351362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2968351362
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2231899749
Short name T201
Test name
Test status
Simulation time 72166298 ps
CPU time 0.79 seconds
Started Jun 04 12:55:20 PM PDT 24
Finished Jun 04 12:55:21 PM PDT 24
Peak memory 200624 kb
Host smart-428bd272-dcc8-4780-a3f5-7263470e2c02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231899749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2231899749
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.94366420
Short name T441
Test name
Test status
Simulation time 2149177866 ps
CPU time 8.36 seconds
Started Jun 04 12:55:10 PM PDT 24
Finished Jun 04 12:55:20 PM PDT 24
Peak memory 218648 kb
Host smart-55cca5df-2d97-455d-9d09-29288232f511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94366420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.94366420
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1574253836
Short name T380
Test name
Test status
Simulation time 244998812 ps
CPU time 1.06 seconds
Started Jun 04 12:55:13 PM PDT 24
Finished Jun 04 12:55:16 PM PDT 24
Peak memory 218096 kb
Host smart-ab42cd55-6f50-4697-92ff-79be9eea04d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574253836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1574253836
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.852102009
Short name T157
Test name
Test status
Simulation time 110241284 ps
CPU time 0.76 seconds
Started Jun 04 12:55:12 PM PDT 24
Finished Jun 04 12:55:15 PM PDT 24
Peak memory 200668 kb
Host smart-c0b1625e-7103-4e8b-ae54-a19862634346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852102009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.852102009
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.699114687
Short name T444
Test name
Test status
Simulation time 933451831 ps
CPU time 4.65 seconds
Started Jun 04 12:55:00 PM PDT 24
Finished Jun 04 12:55:06 PM PDT 24
Peak memory 201060 kb
Host smart-29d9c342-9f06-482f-ad06-c6a386c3c259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699114687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.699114687
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3448079366
Short name T90
Test name
Test status
Simulation time 99525649 ps
CPU time 0.94 seconds
Started Jun 04 12:55:11 PM PDT 24
Finished Jun 04 12:55:14 PM PDT 24
Peak memory 200848 kb
Host smart-faec0c61-c154-4fcb-8c88-c4dd82caf14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448079366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3448079366
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2981099134
Short name T492
Test name
Test status
Simulation time 123415223 ps
CPU time 1.23 seconds
Started Jun 04 12:55:12 PM PDT 24
Finished Jun 04 12:55:15 PM PDT 24
Peak memory 201040 kb
Host smart-ccb3eec1-2989-4df5-9c98-b61ac58965c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981099134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2981099134
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1419083432
Short name T271
Test name
Test status
Simulation time 4218224267 ps
CPU time 18.8 seconds
Started Jun 04 12:55:17 PM PDT 24
Finished Jun 04 12:55:36 PM PDT 24
Peak memory 201180 kb
Host smart-bff62158-4925-430f-963e-ee65d8674b51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419083432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1419083432
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3797172337
Short name T93
Test name
Test status
Simulation time 289740057 ps
CPU time 1.96 seconds
Started Jun 04 12:55:12 PM PDT 24
Finished Jun 04 12:55:16 PM PDT 24
Peak memory 200812 kb
Host smart-00c85480-47d4-48a8-9f8c-7851ceb64082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797172337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3797172337
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3263984774
Short name T378
Test name
Test status
Simulation time 143328192 ps
CPU time 1.14 seconds
Started Jun 04 12:55:10 PM PDT 24
Finished Jun 04 12:55:13 PM PDT 24
Peak memory 200848 kb
Host smart-b1ebe07b-e60c-4a86-9a66-2ad3f37039df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263984774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3263984774
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3133098556
Short name T243
Test name
Test status
Simulation time 60735671 ps
CPU time 0.75 seconds
Started Jun 04 12:54:04 PM PDT 24
Finished Jun 04 12:54:06 PM PDT 24
Peak memory 200640 kb
Host smart-b09c864b-103f-4e84-8afa-2fc82272ddf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133098556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3133098556
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.265554548
Short name T503
Test name
Test status
Simulation time 1234913141 ps
CPU time 5.89 seconds
Started Jun 04 12:53:59 PM PDT 24
Finished Jun 04 12:54:06 PM PDT 24
Peak memory 222020 kb
Host smart-5d58e250-777c-40a0-b236-e3ca7d96e427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265554548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.265554548
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2131215671
Short name T320
Test name
Test status
Simulation time 244624778 ps
CPU time 1.11 seconds
Started Jun 04 12:54:12 PM PDT 24
Finished Jun 04 12:54:14 PM PDT 24
Peak memory 217876 kb
Host smart-3d565200-207f-48a5-be20-3fcc311f156a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131215671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2131215671
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.4238467478
Short name T446
Test name
Test status
Simulation time 102992790 ps
CPU time 0.82 seconds
Started Jun 04 12:54:02 PM PDT 24
Finished Jun 04 12:54:03 PM PDT 24
Peak memory 200652 kb
Host smart-53b81627-4a74-4f2a-ba0b-1a637576984a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238467478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.4238467478
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.3099973670
Short name T311
Test name
Test status
Simulation time 1373131204 ps
CPU time 5.39 seconds
Started Jun 04 12:54:07 PM PDT 24
Finished Jun 04 12:54:13 PM PDT 24
Peak memory 200944 kb
Host smart-613579da-8038-48c2-94c4-c66d33da1926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099973670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3099973670
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3699777106
Short name T193
Test name
Test status
Simulation time 101748381 ps
CPU time 1.05 seconds
Started Jun 04 12:54:01 PM PDT 24
Finished Jun 04 12:54:03 PM PDT 24
Peak memory 200784 kb
Host smart-35db0c5b-f1f9-44de-bbcc-0c23d6c47a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699777106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3699777106
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2196316898
Short name T34
Test name
Test status
Simulation time 250905177 ps
CPU time 1.4 seconds
Started Jun 04 12:54:10 PM PDT 24
Finished Jun 04 12:54:13 PM PDT 24
Peak memory 200912 kb
Host smart-a3ddd169-ee75-4045-9821-533ccd18df24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196316898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2196316898
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2670013726
Short name T258
Test name
Test status
Simulation time 120773302 ps
CPU time 1.01 seconds
Started Jun 04 12:54:13 PM PDT 24
Finished Jun 04 12:54:15 PM PDT 24
Peak memory 200796 kb
Host smart-d5209450-136b-4f81-a46a-a1f38ee257e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670013726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2670013726
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3687156579
Short name T205
Test name
Test status
Simulation time 127438491 ps
CPU time 1.67 seconds
Started Jun 04 12:54:10 PM PDT 24
Finished Jun 04 12:54:12 PM PDT 24
Peak memory 200720 kb
Host smart-74397dfa-b5c5-4f75-9dac-8c6df11a270b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687156579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3687156579
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.471178164
Short name T342
Test name
Test status
Simulation time 76568787 ps
CPU time 0.82 seconds
Started Jun 04 12:54:03 PM PDT 24
Finished Jun 04 12:54:04 PM PDT 24
Peak memory 200848 kb
Host smart-4a941fba-fe42-49a8-8842-9ad052b5a939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471178164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.471178164
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2637020518
Short name T509
Test name
Test status
Simulation time 66855800 ps
CPU time 0.72 seconds
Started Jun 04 12:54:15 PM PDT 24
Finished Jun 04 12:54:17 PM PDT 24
Peak memory 200604 kb
Host smart-d291af45-b60a-46ff-8785-f4197bbaa95f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637020518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2637020518
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3174291895
Short name T58
Test name
Test status
Simulation time 2363087716 ps
CPU time 7.91 seconds
Started Jun 04 12:54:18 PM PDT 24
Finished Jun 04 12:54:27 PM PDT 24
Peak memory 222600 kb
Host smart-2104e607-81a7-4528-84dc-e3b3e1626cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174291895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3174291895
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2681539797
Short name T451
Test name
Test status
Simulation time 244523446 ps
CPU time 1.06 seconds
Started Jun 04 12:54:07 PM PDT 24
Finished Jun 04 12:54:09 PM PDT 24
Peak memory 218140 kb
Host smart-635fb0d3-4005-4de1-8358-b7a9fe2f93de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681539797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2681539797
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2140846232
Short name T281
Test name
Test status
Simulation time 110287076 ps
CPU time 0.83 seconds
Started Jun 04 12:54:08 PM PDT 24
Finished Jun 04 12:54:09 PM PDT 24
Peak memory 200652 kb
Host smart-958543cf-5444-4735-9898-b75696213e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140846232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2140846232
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3030642884
Short name T21
Test name
Test status
Simulation time 1632579896 ps
CPU time 6.38 seconds
Started Jun 04 12:54:04 PM PDT 24
Finished Jun 04 12:54:11 PM PDT 24
Peak memory 201008 kb
Host smart-7975aeb0-6d37-499f-9e20-f7916b9b1047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030642884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3030642884
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3695066428
Short name T22
Test name
Test status
Simulation time 168950016 ps
CPU time 1.12 seconds
Started Jun 04 12:54:20 PM PDT 24
Finished Jun 04 12:54:23 PM PDT 24
Peak memory 200828 kb
Host smart-67ac7237-1dbb-4023-9c3c-d2bcb4f276cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695066428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3695066428
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.3209518600
Short name T194
Test name
Test status
Simulation time 115242966 ps
CPU time 1.28 seconds
Started Jun 04 12:54:00 PM PDT 24
Finished Jun 04 12:54:03 PM PDT 24
Peak memory 201008 kb
Host smart-44931333-e589-4c30-b733-875679d037e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209518600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3209518600
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.808326409
Short name T126
Test name
Test status
Simulation time 3502144518 ps
CPU time 16.74 seconds
Started Jun 04 12:54:10 PM PDT 24
Finished Jun 04 12:54:28 PM PDT 24
Peak memory 201156 kb
Host smart-33216a03-6b7b-4620-8acc-253a1d9b01be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808326409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.808326409
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.803299525
Short name T296
Test name
Test status
Simulation time 118321546 ps
CPU time 1.44 seconds
Started Jun 04 12:53:59 PM PDT 24
Finished Jun 04 12:54:01 PM PDT 24
Peak memory 200876 kb
Host smart-ffcdbced-c7f5-4d9d-92f3-1badfbf03bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803299525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.803299525
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3883056044
Short name T314
Test name
Test status
Simulation time 270155194 ps
CPU time 1.59 seconds
Started Jun 04 12:54:00 PM PDT 24
Finished Jun 04 12:54:03 PM PDT 24
Peak memory 200832 kb
Host smart-1b61d75f-0ffa-4e2d-98e2-0fcddbdf6cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883056044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3883056044
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.756911438
Short name T528
Test name
Test status
Simulation time 79577577 ps
CPU time 0.75 seconds
Started Jun 04 12:54:13 PM PDT 24
Finished Jun 04 12:54:15 PM PDT 24
Peak memory 200688 kb
Host smart-73414c80-43fd-4ba8-9f1b-c0f699e258a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756911438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.756911438
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3944010171
Short name T57
Test name
Test status
Simulation time 2169874827 ps
CPU time 8.51 seconds
Started Jun 04 12:54:11 PM PDT 24
Finished Jun 04 12:54:21 PM PDT 24
Peak memory 218484 kb
Host smart-17887064-60e4-4313-b0cb-483fc2f6b522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944010171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3944010171
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1571736741
Short name T470
Test name
Test status
Simulation time 244205699 ps
CPU time 1.18 seconds
Started Jun 04 12:54:19 PM PDT 24
Finished Jun 04 12:54:23 PM PDT 24
Peak memory 218084 kb
Host smart-47465fe9-e07c-4441-b871-e129d01ca25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571736741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1571736741
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.31710650
Short name T161
Test name
Test status
Simulation time 132539577 ps
CPU time 0.85 seconds
Started Jun 04 12:54:18 PM PDT 24
Finished Jun 04 12:54:20 PM PDT 24
Peak memory 200580 kb
Host smart-cf119557-d192-4851-ae5d-70e18726cdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31710650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.31710650
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.217596369
Short name T304
Test name
Test status
Simulation time 1973213729 ps
CPU time 8.09 seconds
Started Jun 04 12:54:17 PM PDT 24
Finished Jun 04 12:54:26 PM PDT 24
Peak memory 201064 kb
Host smart-58c30e52-aee1-4934-814e-2d6228817268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217596369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.217596369
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1088770801
Short name T341
Test name
Test status
Simulation time 175481506 ps
CPU time 1.2 seconds
Started Jun 04 12:54:19 PM PDT 24
Finished Jun 04 12:54:23 PM PDT 24
Peak memory 200744 kb
Host smart-14a11326-6258-4bd8-b13d-e08eee3526af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088770801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1088770801
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3475055204
Short name T39
Test name
Test status
Simulation time 205232128 ps
CPU time 1.36 seconds
Started Jun 04 12:54:20 PM PDT 24
Finished Jun 04 12:54:24 PM PDT 24
Peak memory 201044 kb
Host smart-d2d1422f-240e-4536-b352-0c60dffa0ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475055204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3475055204
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.725256945
Short name T486
Test name
Test status
Simulation time 11191780577 ps
CPU time 39.59 seconds
Started Jun 04 12:54:12 PM PDT 24
Finished Jun 04 12:54:53 PM PDT 24
Peak memory 209368 kb
Host smart-59df9fcb-dc13-448a-9a69-53c2ac78950e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725256945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.725256945
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1022448468
Short name T85
Test name
Test status
Simulation time 419245460 ps
CPU time 2.39 seconds
Started Jun 04 12:54:08 PM PDT 24
Finished Jun 04 12:54:11 PM PDT 24
Peak memory 200816 kb
Host smart-3e15aab6-53ca-4688-a4ae-acd46074b308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022448468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1022448468
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2729155001
Short name T465
Test name
Test status
Simulation time 177536056 ps
CPU time 1.07 seconds
Started Jun 04 12:54:17 PM PDT 24
Finished Jun 04 12:54:19 PM PDT 24
Peak memory 200808 kb
Host smart-0daf8637-2fb9-49e7-a362-8c34fe6e8292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729155001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2729155001
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1244350791
Short name T420
Test name
Test status
Simulation time 69660279 ps
CPU time 0.78 seconds
Started Jun 04 12:54:10 PM PDT 24
Finished Jun 04 12:54:12 PM PDT 24
Peak memory 200644 kb
Host smart-6c2ea6c5-0bc8-4f84-a0c6-5fd5affbeed0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244350791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1244350791
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3594040255
Short name T156
Test name
Test status
Simulation time 244327063 ps
CPU time 1.21 seconds
Started Jun 04 12:54:10 PM PDT 24
Finished Jun 04 12:54:12 PM PDT 24
Peak memory 217972 kb
Host smart-74ddb9e0-4873-411d-bcde-be9b342c696f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594040255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3594040255
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2356306713
Short name T291
Test name
Test status
Simulation time 134537541 ps
CPU time 0.8 seconds
Started Jun 04 12:54:09 PM PDT 24
Finished Jun 04 12:54:10 PM PDT 24
Peak memory 200620 kb
Host smart-da6a6ae8-a3de-4559-b514-8a00117ff0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356306713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2356306713
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.1696329336
Short name T119
Test name
Test status
Simulation time 881156256 ps
CPU time 4.17 seconds
Started Jun 04 12:54:16 PM PDT 24
Finished Jun 04 12:54:21 PM PDT 24
Peak memory 201028 kb
Host smart-ee0e91b5-fbdf-47e7-b452-3cad33368c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696329336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1696329336
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1654321525
Short name T252
Test name
Test status
Simulation time 107360181 ps
CPU time 1.05 seconds
Started Jun 04 12:54:09 PM PDT 24
Finished Jun 04 12:54:11 PM PDT 24
Peak memory 200860 kb
Host smart-fbfe7de9-f70a-45cf-8d0c-f562ee06dffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654321525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1654321525
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3268297887
Short name T62
Test name
Test status
Simulation time 124246269 ps
CPU time 1.22 seconds
Started Jun 04 12:54:08 PM PDT 24
Finished Jun 04 12:54:10 PM PDT 24
Peak memory 200976 kb
Host smart-49c32272-6bd2-4525-abac-27c97ecf3cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268297887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3268297887
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2678921933
Short name T537
Test name
Test status
Simulation time 7326040757 ps
CPU time 26.08 seconds
Started Jun 04 12:54:17 PM PDT 24
Finished Jun 04 12:54:45 PM PDT 24
Peak memory 201184 kb
Host smart-11b48d82-abfc-492e-9baf-50eb699d07cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678921933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2678921933
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.2357422059
Short name T346
Test name
Test status
Simulation time 258125372 ps
CPU time 1.77 seconds
Started Jun 04 12:54:07 PM PDT 24
Finished Jun 04 12:54:09 PM PDT 24
Peak memory 200844 kb
Host smart-b7680057-a66c-45d9-bc6f-5a673576973c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357422059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2357422059
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1267011451
Short name T410
Test name
Test status
Simulation time 216750664 ps
CPU time 1.37 seconds
Started Jun 04 12:54:18 PM PDT 24
Finished Jun 04 12:54:22 PM PDT 24
Peak memory 200864 kb
Host smart-56f37663-01d9-4a04-8833-a0f1af223a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267011451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1267011451
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.1545475521
Short name T77
Test name
Test status
Simulation time 83941570 ps
CPU time 0.84 seconds
Started Jun 04 12:54:12 PM PDT 24
Finished Jun 04 12:54:13 PM PDT 24
Peak memory 200592 kb
Host smart-a32dfae2-4667-477f-87ee-811261b2833f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545475521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1545475521
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1897373442
Short name T51
Test name
Test status
Simulation time 1890338780 ps
CPU time 7.38 seconds
Started Jun 04 12:54:06 PM PDT 24
Finished Jun 04 12:54:15 PM PDT 24
Peak memory 218516 kb
Host smart-757a2d5c-a430-4825-96f1-ef1ac574c102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897373442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1897373442
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3012031260
Short name T216
Test name
Test status
Simulation time 243782605 ps
CPU time 1.09 seconds
Started Jun 04 12:54:09 PM PDT 24
Finished Jun 04 12:54:12 PM PDT 24
Peak memory 217904 kb
Host smart-efcb3adc-2939-4212-b4aa-81b4bb02b88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012031260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3012031260
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.567104262
Short name T439
Test name
Test status
Simulation time 191861981 ps
CPU time 0.9 seconds
Started Jun 04 12:54:20 PM PDT 24
Finished Jun 04 12:54:23 PM PDT 24
Peak memory 200620 kb
Host smart-a9477fd3-c2c0-481b-a0ae-9c16ba02e989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567104262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.567104262
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.2572543121
Short name T111
Test name
Test status
Simulation time 1449042017 ps
CPU time 5.63 seconds
Started Jun 04 12:54:08 PM PDT 24
Finished Jun 04 12:54:14 PM PDT 24
Peak memory 200928 kb
Host smart-ad459ef5-cb33-44ec-b3f8-d25192357e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572543121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2572543121
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2389219574
Short name T321
Test name
Test status
Simulation time 99954623 ps
CPU time 0.98 seconds
Started Jun 04 12:54:15 PM PDT 24
Finished Jun 04 12:54:17 PM PDT 24
Peak memory 200864 kb
Host smart-c5ac826b-b07c-4343-878c-da42fe35b87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389219574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2389219574
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1138169049
Short name T535
Test name
Test status
Simulation time 117368396 ps
CPU time 1.1 seconds
Started Jun 04 12:54:19 PM PDT 24
Finished Jun 04 12:54:22 PM PDT 24
Peak memory 201040 kb
Host smart-bc3e069d-cfa0-4463-9c56-59edfdd73eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138169049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1138169049
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3050890102
Short name T350
Test name
Test status
Simulation time 417243589 ps
CPU time 2.33 seconds
Started Jun 04 12:54:09 PM PDT 24
Finished Jun 04 12:54:13 PM PDT 24
Peak memory 201016 kb
Host smart-1311039b-a3f7-42ac-9c8e-e39b27a1e207
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050890102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3050890102
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3042504361
Short name T525
Test name
Test status
Simulation time 143749335 ps
CPU time 1.9 seconds
Started Jun 04 12:54:09 PM PDT 24
Finished Jun 04 12:54:12 PM PDT 24
Peak memory 200772 kb
Host smart-e9aba712-92fc-4381-88e3-4468e23fd7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042504361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3042504361
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2858500765
Short name T366
Test name
Test status
Simulation time 57705043 ps
CPU time 0.72 seconds
Started Jun 04 12:54:19 PM PDT 24
Finished Jun 04 12:54:22 PM PDT 24
Peak memory 200800 kb
Host smart-e8f374cc-3999-4b35-a58a-1751cd0aeb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858500765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2858500765
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%