Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8479

1

T4

21

T5

20

T10

19

auto[1]

11197

1

T1

1

T4

80

T5

81

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6089	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6578	1			T1	1		T2	1		T3	1
reset_info_cp[2]	3003	1			T4	20		T5	16		T6	1
reset_info_cp[4]	4053	1			T4	10		T5	15		T6	1
reset_info_cp[8]	112	1			T4	2		T5	2		T10	2
reset_info_cp[16]	125	1			T4	1		T13	1		T76	2
reset_info_cp[32]	104	1			T10	1		T14	2		T33	1
reset_info_cp[64]	121	1			T4	1		T5	1		T10	1
reset_info_cp[128]	111	1			T5	2		T6	1		T10	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3181	1			T4	21		T5	20		T10	19
reset_info_cp[1]	auto[1]	2777	1			T4	5		T5	6		T6	1
reset_info_cp[2]	auto[0]	1008	1			T32	8		T34	3		T69	7
reset_info_cp[2]	auto[1]	1995	1			T4	20		T5	16		T6	1
reset_info_cp[4]	auto[0]	1483	1			T32	4		T34	5		T69	7
reset_info_cp[4]	auto[1]	2570	1			T4	10		T5	15		T6	1
reset_info_cp[8]	auto[0]	37	1			T11	1		T72	1		T83	1
reset_info_cp[8]	auto[1]	75	1			T4	2		T5	2		T10	2
reset_info_cp[16]	auto[0]	53	1			T13	1		T76	2		T70	2
reset_info_cp[16]	auto[1]	72	1			T4	1		T33	1		T70	2
reset_info_cp[32]	auto[0]	28	1			T73	1		T89	1		T90	1
reset_info_cp[32]	auto[1]	76	1			T10	1		T14	2		T33	1
reset_info_cp[64]	auto[0]	39	1			T84	1		T88	2		T128	1
reset_info_cp[64]	auto[1]	82	1			T4	1		T5	1		T10	1
reset_info_cp[128]	auto[0]	45	1			T13	1		T113	1		T72	1
reset_info_cp[128]	auto[1]	66	1			T5	2		T6	1		T10	1