Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T537 /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1848808609 Jun 05 03:53:45 PM PDT 24 Jun 05 03:53:48 PM PDT 24 243984877 ps
T538 /workspace/coverage/default/9.rstmgr_por_stretcher.1458853165 Jun 05 03:53:49 PM PDT 24 Jun 05 03:53:51 PM PDT 24 142622919 ps
T539 /workspace/coverage/default/33.rstmgr_alert_test.2914395127 Jun 05 03:54:45 PM PDT 24 Jun 05 03:54:48 PM PDT 24 60863641 ps
T540 /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1677426454 Jun 05 03:54:14 PM PDT 24 Jun 05 03:54:25 PM PDT 24 2368140869 ps
T541 /workspace/coverage/default/4.rstmgr_stress_all.5801891 Jun 05 03:53:15 PM PDT 24 Jun 05 03:53:35 PM PDT 24 4601230364 ps
T56 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.693200729 Jun 05 03:55:26 PM PDT 24 Jun 05 03:55:29 PM PDT 24 187993093 ps
T57 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3598628372 Jun 05 03:55:06 PM PDT 24 Jun 05 03:55:09 PM PDT 24 257285166 ps
T60 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3344224776 Jun 05 03:55:06 PM PDT 24 Jun 05 03:55:09 PM PDT 24 102539819 ps
T61 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.4242646664 Jun 05 03:55:09 PM PDT 24 Jun 05 03:55:13 PM PDT 24 178197590 ps
T58 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1201284212 Jun 05 03:55:08 PM PDT 24 Jun 05 03:55:10 PM PDT 24 113190863 ps
T59 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.4106340839 Jun 05 03:55:24 PM PDT 24 Jun 05 03:55:27 PM PDT 24 149578221 ps
T62 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2421350770 Jun 05 03:55:23 PM PDT 24 Jun 05 03:55:26 PM PDT 24 352125280 ps
T66 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1656637218 Jun 05 03:55:14 PM PDT 24 Jun 05 03:55:18 PM PDT 24 950464617 ps
T78 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3804138205 Jun 05 03:55:26 PM PDT 24 Jun 05 03:55:28 PM PDT 24 183666021 ps
T542 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.441855051 Jun 05 03:55:27 PM PDT 24 Jun 05 03:55:29 PM PDT 24 70730126 ps
T79 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.4206384385 Jun 05 03:55:15 PM PDT 24 Jun 05 03:55:18 PM PDT 24 136022450 ps
T80 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2490794426 Jun 05 03:55:24 PM PDT 24 Jun 05 03:55:29 PM PDT 24 543822560 ps
T81 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2802896444 Jun 05 03:55:16 PM PDT 24 Jun 05 03:55:20 PM PDT 24 199030870 ps
T543 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.937702728 Jun 05 03:55:06 PM PDT 24 Jun 05 03:55:07 PM PDT 24 74315780 ps
T125 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1263516130 Jun 05 03:55:15 PM PDT 24 Jun 05 03:55:18 PM PDT 24 78480411 ps
T82 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3869792295 Jun 05 03:55:16 PM PDT 24 Jun 05 03:55:19 PM PDT 24 224500472 ps
T126 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2808727391 Jun 05 03:55:07 PM PDT 24 Jun 05 03:55:17 PM PDT 24 1986380145 ps
T100 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1167183333 Jun 05 03:55:26 PM PDT 24 Jun 05 03:55:30 PM PDT 24 976960407 ps
T92 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2338773161 Jun 05 03:55:07 PM PDT 24 Jun 05 03:55:09 PM PDT 24 119238593 ps
T101 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3051830478 Jun 05 03:55:17 PM PDT 24 Jun 05 03:55:21 PM PDT 24 884905850 ps
T544 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.4143669954 Jun 05 03:55:17 PM PDT 24 Jun 05 03:55:20 PM PDT 24 200874018 ps
T545 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2528223735 Jun 05 03:55:09 PM PDT 24 Jun 05 03:55:12 PM PDT 24 155244826 ps
T93 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3128499925 Jun 05 03:55:14 PM PDT 24 Jun 05 03:55:16 PM PDT 24 84991924 ps
T94 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.4150184786 Jun 05 03:55:27 PM PDT 24 Jun 05 03:55:29 PM PDT 24 69357777 ps
T546 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3606331733 Jun 05 03:55:07 PM PDT 24 Jun 05 03:55:11 PM PDT 24 401364134 ps
T102 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1465904267 Jun 05 03:55:16 PM PDT 24 Jun 05 03:55:20 PM PDT 24 274792876 ps
T95 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.391503578 Jun 05 03:55:21 PM PDT 24 Jun 05 03:55:22 PM PDT 24 90401221 ps
T103 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1810938541 Jun 05 03:55:18 PM PDT 24 Jun 05 03:55:23 PM PDT 24 406236255 ps
T547 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3133105299 Jun 05 03:55:08 PM PDT 24 Jun 05 03:55:11 PM PDT 24 239358940 ps
T124 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.498721119 Jun 05 03:55:17 PM PDT 24 Jun 05 03:55:21 PM PDT 24 794073949 ps
T548 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3654869987 Jun 05 03:55:15 PM PDT 24 Jun 05 03:55:18 PM PDT 24 78784966 ps
T121 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1232477739 Jun 05 03:55:15 PM PDT 24 Jun 05 03:55:19 PM PDT 24 435942314 ps
T96 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3220443306 Jun 05 03:55:09 PM PDT 24 Jun 05 03:55:11 PM PDT 24 76531925 ps
T549 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3102016098 Jun 05 03:55:17 PM PDT 24 Jun 05 03:55:20 PM PDT 24 202232999 ps
T97 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.689596305 Jun 05 03:55:18 PM PDT 24 Jun 05 03:55:20 PM PDT 24 82699540 ps
T98 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3526233652 Jun 05 03:55:26 PM PDT 24 Jun 05 03:55:28 PM PDT 24 92522444 ps
T550 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1430301271 Jun 05 03:55:06 PM PDT 24 Jun 05 03:55:08 PM PDT 24 140375107 ps
T551 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3836273483 Jun 05 03:55:14 PM PDT 24 Jun 05 03:55:17 PM PDT 24 76956881 ps
T122 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1672128091 Jun 05 03:55:24 PM PDT 24 Jun 05 03:55:27 PM PDT 24 881796056 ps
T99 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1183127855 Jun 05 03:55:15 PM PDT 24 Jun 05 03:55:17 PM PDT 24 57648661 ps
T552 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2967696556 Jun 05 03:55:15 PM PDT 24 Jun 05 03:55:20 PM PDT 24 337917579 ps
T553 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2185376373 Jun 05 03:55:14 PM PDT 24 Jun 05 03:55:16 PM PDT 24 114322188 ps
T554 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.92219368 Jun 05 03:55:15 PM PDT 24 Jun 05 03:55:18 PM PDT 24 138277015 ps
T555 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4119663545 Jun 05 03:55:16 PM PDT 24 Jun 05 03:55:19 PM PDT 24 148576560 ps
T556 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2120228774 Jun 05 03:55:13 PM PDT 24 Jun 05 03:55:15 PM PDT 24 158165750 ps
T557 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.497788827 Jun 05 03:55:15 PM PDT 24 Jun 05 03:55:18 PM PDT 24 136749530 ps
T558 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1568304388 Jun 05 03:55:15 PM PDT 24 Jun 05 03:55:18 PM PDT 24 96662724 ps
T559 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.733720971 Jun 05 03:55:25 PM PDT 24 Jun 05 03:55:27 PM PDT 24 125831609 ps
T106 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.4191595251 Jun 05 03:55:15 PM PDT 24 Jun 05 03:55:19 PM PDT 24 460153718 ps
T560 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1372177790 Jun 05 03:55:06 PM PDT 24 Jun 05 03:55:10 PM PDT 24 204531632 ps
T561 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1284537655 Jun 05 03:55:05 PM PDT 24 Jun 05 03:55:07 PM PDT 24 193125098 ps
T107 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.901967730 Jun 05 03:55:07 PM PDT 24 Jun 05 03:55:11 PM PDT 24 892876834 ps
T562 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3646190428 Jun 05 03:55:06 PM PDT 24 Jun 05 03:55:08 PM PDT 24 140742125 ps
T563 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3538072472 Jun 05 03:55:14 PM PDT 24 Jun 05 03:55:16 PM PDT 24 81907248 ps
T564 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.684050919 Jun 05 03:55:14 PM PDT 24 Jun 05 03:55:18 PM PDT 24 420412406 ps
T565 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1657785181 Jun 05 03:55:16 PM PDT 24 Jun 05 03:55:19 PM PDT 24 157233783 ps
T566 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2341287834 Jun 05 03:55:08 PM PDT 24 Jun 05 03:55:14 PM PDT 24 1031964982 ps
T567 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3164333884 Jun 05 03:55:24 PM PDT 24 Jun 05 03:55:28 PM PDT 24 324459049 ps
T568 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4115839749 Jun 05 03:55:06 PM PDT 24 Jun 05 03:55:08 PM PDT 24 104242758 ps
T105 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2014447090 Jun 05 03:55:16 PM PDT 24 Jun 05 03:55:20 PM PDT 24 560989670 ps
T569 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.239906355 Jun 05 03:55:06 PM PDT 24 Jun 05 03:55:09 PM PDT 24 102696728 ps
T570 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4034233843 Jun 05 03:55:16 PM PDT 24 Jun 05 03:55:19 PM PDT 24 120953840 ps
T571 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3563406319 Jun 05 03:55:16 PM PDT 24 Jun 05 03:55:20 PM PDT 24 257899114 ps
T123 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2998235578 Jun 05 03:55:24 PM PDT 24 Jun 05 03:55:29 PM PDT 24 889570737 ps
T572 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2724791517 Jun 05 03:55:17 PM PDT 24 Jun 05 03:55:22 PM PDT 24 793878446 ps
T573 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2256989090 Jun 05 03:55:06 PM PDT 24 Jun 05 03:55:08 PM PDT 24 102039936 ps
T574 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1667118145 Jun 05 03:55:14 PM PDT 24 Jun 05 03:55:21 PM PDT 24 492079968 ps
T575 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3802144324 Jun 05 03:55:07 PM PDT 24 Jun 05 03:55:09 PM PDT 24 69188131 ps
T576 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1744131787 Jun 05 03:55:23 PM PDT 24 Jun 05 03:55:25 PM PDT 24 128690374 ps
T577 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3371000980 Jun 05 03:55:15 PM PDT 24 Jun 05 03:55:17 PM PDT 24 130982192 ps
T578 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.527849121 Jun 05 03:55:19 PM PDT 24 Jun 05 03:55:21 PM PDT 24 81656947 ps
T579 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3324154306 Jun 05 03:55:08 PM PDT 24 Jun 05 03:55:09 PM PDT 24 97748049 ps
T580 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3330970462 Jun 05 03:55:14 PM PDT 24 Jun 05 03:55:17 PM PDT 24 125119309 ps
T581 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1977913986 Jun 05 03:55:27 PM PDT 24 Jun 05 03:55:31 PM PDT 24 452576241 ps
T582 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2656546149 Jun 05 03:55:17 PM PDT 24 Jun 05 03:55:20 PM PDT 24 126829644 ps
T583 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.19274912 Jun 05 03:55:18 PM PDT 24 Jun 05 03:55:25 PM PDT 24 1027710704 ps
T584 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1986311050 Jun 05 03:55:25 PM PDT 24 Jun 05 03:55:27 PM PDT 24 208618141 ps
T585 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.399133829 Jun 05 03:55:18 PM PDT 24 Jun 05 03:55:21 PM PDT 24 195832879 ps
T586 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1385046513 Jun 05 03:55:17 PM PDT 24 Jun 05 03:55:23 PM PDT 24 582238301 ps
T587 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.4157892899 Jun 05 03:55:06 PM PDT 24 Jun 05 03:55:10 PM PDT 24 269117040 ps
T588 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3432790241 Jun 05 03:55:19 PM PDT 24 Jun 05 03:55:21 PM PDT 24 77535433 ps
T589 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.4076211566 Jun 05 03:55:14 PM PDT 24 Jun 05 03:55:17 PM PDT 24 111905382 ps
T590 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1910423977 Jun 05 03:55:15 PM PDT 24 Jun 05 03:55:20 PM PDT 24 883208649 ps
T591 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1736478677 Jun 05 03:55:16 PM PDT 24 Jun 05 03:55:19 PM PDT 24 95568664 ps
T592 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3145417335 Jun 05 03:55:16 PM PDT 24 Jun 05 03:55:18 PM PDT 24 78248963 ps
T593 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.251787816 Jun 05 03:55:17 PM PDT 24 Jun 05 03:55:21 PM PDT 24 153316152 ps
T594 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.981681113 Jun 05 03:55:25 PM PDT 24 Jun 05 03:55:27 PM PDT 24 151290195 ps
T595 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.585268151 Jun 05 03:55:16 PM PDT 24 Jun 05 03:55:20 PM PDT 24 469734740 ps
T596 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.626796523 Jun 05 03:55:14 PM PDT 24 Jun 05 03:55:17 PM PDT 24 94229939 ps
T597 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2104335519 Jun 05 03:55:15 PM PDT 24 Jun 05 03:55:18 PM PDT 24 141444092 ps
T598 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.719011780 Jun 05 03:55:27 PM PDT 24 Jun 05 03:55:29 PM PDT 24 124523566 ps
T599 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.642529931 Jun 05 03:55:14 PM PDT 24 Jun 05 03:55:21 PM PDT 24 626110442 ps
T600 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3100240927 Jun 05 03:55:26 PM PDT 24 Jun 05 03:55:28 PM PDT 24 58903796 ps
T601 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.411853708 Jun 05 03:55:15 PM PDT 24 Jun 05 03:55:20 PM PDT 24 900251389 ps
T602 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2185818687 Jun 05 03:55:13 PM PDT 24 Jun 05 03:55:15 PM PDT 24 121124048 ps
T603 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1743209962 Jun 05 03:55:20 PM PDT 24 Jun 05 03:55:23 PM PDT 24 325166634 ps
T604 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1784311406 Jun 05 03:55:25 PM PDT 24 Jun 05 03:55:28 PM PDT 24 120950546 ps
T605 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3109547428 Jun 05 03:55:25 PM PDT 24 Jun 05 03:55:27 PM PDT 24 139827774 ps
T606 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2566719231 Jun 05 03:55:24 PM PDT 24 Jun 05 03:55:26 PM PDT 24 123948108 ps
T607 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.277381887 Jun 05 03:55:19 PM PDT 24 Jun 05 03:55:22 PM PDT 24 182984710 ps
T608 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3582060660 Jun 05 03:55:15 PM PDT 24 Jun 05 03:55:18 PM PDT 24 124775981 ps
T609 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.960541485 Jun 05 03:55:15 PM PDT 24 Jun 05 03:55:19 PM PDT 24 949993659 ps
T610 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1517543153 Jun 05 03:55:18 PM PDT 24 Jun 05 03:55:20 PM PDT 24 75735659 ps
T611 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3827323671 Jun 05 03:55:07 PM PDT 24 Jun 05 03:55:13 PM PDT 24 1197210660 ps
T612 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.848672629 Jun 05 03:55:17 PM PDT 24 Jun 05 03:55:20 PM PDT 24 76115989 ps
T613 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2126760806 Jun 05 03:55:27 PM PDT 24 Jun 05 03:55:29 PM PDT 24 84942694 ps
T108 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2896323878 Jun 05 03:55:26 PM PDT 24 Jun 05 03:55:30 PM PDT 24 784203877 ps
T614 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2910408832 Jun 05 03:55:15 PM PDT 24 Jun 05 03:55:18 PM PDT 24 130790961 ps
T615 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.894216870 Jun 05 03:55:06 PM PDT 24 Jun 05 03:55:09 PM PDT 24 57704112 ps
T616 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2475736262 Jun 05 03:55:15 PM PDT 24 Jun 05 03:55:17 PM PDT 24 84745848 ps
T617 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2481827546 Jun 05 03:55:18 PM PDT 24 Jun 05 03:55:22 PM PDT 24 779913726 ps
T618 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2486056131 Jun 05 03:55:06 PM PDT 24 Jun 05 03:55:11 PM PDT 24 476084234 ps
T619 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2990176686 Jun 05 03:55:06 PM PDT 24 Jun 05 03:55:11 PM PDT 24 945534007 ps
T620 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2684245801 Jun 05 03:55:09 PM PDT 24 Jun 05 03:55:13 PM PDT 24 973908143 ps
T104 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1680284528 Jun 05 03:55:25 PM PDT 24 Jun 05 03:55:28 PM PDT 24 515197630 ps

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1364833005
Short name T6
Test name
Test status
Simulation time 108743000 ps
CPU time 0.99 seconds
Started Jun 05 03:54:13 PM PDT 24
Finished Jun 05 03:54:15 PM PDT 24
Peak memory 200728 kb
Host smart-3d1b8ab1-1cfa-49ce-951b-ef5a069de4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364833005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1364833005
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.820729358
Short name T2
Test name
Test status
Simulation time 127828680 ps
CPU time 1.64 seconds
Started Jun 05 03:53:38 PM PDT 24
Finished Jun 05 03:53:40 PM PDT 24
Peak memory 209000 kb
Host smart-28c747e8-a802-405b-a775-e191fb4d41db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820729358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.820729358
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1191595535
Short name T32
Test name
Test status
Simulation time 2012004404 ps
CPU time 7.19 seconds
Started Jun 05 03:53:44 PM PDT 24
Finished Jun 05 03:53:52 PM PDT 24
Peak memory 201036 kb
Host smart-d6c231de-f470-4b7c-848e-4ba14676fa96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191595535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1191595535
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.4106340839
Short name T59
Test name
Test status
Simulation time 149578221 ps
CPU time 1.27 seconds
Started Jun 05 03:55:24 PM PDT 24
Finished Jun 05 03:55:27 PM PDT 24
Peak memory 208900 kb
Host smart-03a0d66f-e802-4678-abbb-d7b58ba670ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106340839 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.4106340839
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.803297851
Short name T3
Test name
Test status
Simulation time 16515830682 ps
CPU time 28.06 seconds
Started Jun 05 03:53:12 PM PDT 24
Finished Jun 05 03:53:41 PM PDT 24
Peak memory 218588 kb
Host smart-5dba3d15-c731-48f6-ab9a-04486ab52a83
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803297851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.803297851
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2219180081
Short name T4
Test name
Test status
Simulation time 1226005561 ps
CPU time 5.55 seconds
Started Jun 05 03:54:56 PM PDT 24
Finished Jun 05 03:55:02 PM PDT 24
Peak memory 217336 kb
Host smart-816d9ab3-1660-42c4-b0ef-bb3adef1bb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219180081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2219180081
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1167183333
Short name T100
Test name
Test status
Simulation time 976960407 ps
CPU time 3.17 seconds
Started Jun 05 03:55:26 PM PDT 24
Finished Jun 05 03:55:30 PM PDT 24
Peak memory 200652 kb
Host smart-04dfa076-ba16-43bb-ab6b-7a48b8564275
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167183333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1167183333
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.644813879
Short name T89
Test name
Test status
Simulation time 11614256181 ps
CPU time 39.4 seconds
Started Jun 05 03:54:43 PM PDT 24
Finished Jun 05 03:55:23 PM PDT 24
Peak memory 209332 kb
Host smart-5d5579f5-4332-44f7-8dba-a685443a497a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644813879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.644813879
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3002035282
Short name T48
Test name
Test status
Simulation time 61157950 ps
CPU time 0.78 seconds
Started Jun 05 03:54:43 PM PDT 24
Finished Jun 05 03:54:45 PM PDT 24
Peak memory 200644 kb
Host smart-e8e6ff26-545e-4653-a476-b789c2fec86b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002035282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3002035282
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2490794426
Short name T80
Test name
Test status
Simulation time 543822560 ps
CPU time 3.72 seconds
Started Jun 05 03:55:24 PM PDT 24
Finished Jun 05 03:55:29 PM PDT 24
Peak memory 208768 kb
Host smart-3e20bf9b-9dd9-4d63-a13e-973c93f0da7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490794426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2490794426
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.902649787
Short name T36
Test name
Test status
Simulation time 1897040305 ps
CPU time 7 seconds
Started Jun 05 03:54:37 PM PDT 24
Finished Jun 05 03:54:45 PM PDT 24
Peak memory 222512 kb
Host smart-54eeb17a-a7f5-4449-b382-3603da2ce509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902649787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.902649787
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.150380725
Short name T13
Test name
Test status
Simulation time 128037736 ps
CPU time 1.15 seconds
Started Jun 05 03:53:17 PM PDT 24
Finished Jun 05 03:53:19 PM PDT 24
Peak memory 200808 kb
Host smart-063dc726-baf0-433c-bda9-d788b9f971ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150380725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.150380725
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.901967730
Short name T107
Test name
Test status
Simulation time 892876834 ps
CPU time 2.91 seconds
Started Jun 05 03:55:07 PM PDT 24
Finished Jun 05 03:55:11 PM PDT 24
Peak memory 200668 kb
Host smart-fd699f71-e580-4ed3-80ab-d46da98ad93c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901967730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
901967730
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2500976947
Short name T55
Test name
Test status
Simulation time 1213628838 ps
CPU time 5.99 seconds
Started Jun 05 03:53:59 PM PDT 24
Finished Jun 05 03:54:06 PM PDT 24
Peak memory 217608 kb
Host smart-2f27825e-40a2-4a52-b498-2f27e5dbb41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500976947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2500976947
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2338773161
Short name T92
Test name
Test status
Simulation time 119238593 ps
CPU time 1.1 seconds
Started Jun 05 03:55:07 PM PDT 24
Finished Jun 05 03:55:09 PM PDT 24
Peak memory 200336 kb
Host smart-32fc3450-4fab-44ae-b812-d0e453672d0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338773161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.2338773161
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3285912955
Short name T25
Test name
Test status
Simulation time 153452575 ps
CPU time 0.8 seconds
Started Jun 05 03:53:56 PM PDT 24
Finished Jun 05 03:53:57 PM PDT 24
Peak memory 200636 kb
Host smart-6b673a86-9f8f-485d-95dd-32c720bf1e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285912955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3285912955
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1372177790
Short name T560
Test name
Test status
Simulation time 204531632 ps
CPU time 2.06 seconds
Started Jun 05 03:55:06 PM PDT 24
Finished Jun 05 03:55:10 PM PDT 24
Peak memory 217072 kb
Host smart-96e8bd4d-ab98-47a3-91b8-8a87976aa191
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372177790 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1372177790
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1680284528
Short name T104
Test name
Test status
Simulation time 515197630 ps
CPU time 1.95 seconds
Started Jun 05 03:55:25 PM PDT 24
Finished Jun 05 03:55:28 PM PDT 24
Peak memory 200632 kb
Host smart-b7b89841-8351-466b-a4b6-31ba18bdee0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680284528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1680284528
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2896323878
Short name T108
Test name
Test status
Simulation time 784203877 ps
CPU time 2.91 seconds
Started Jun 05 03:55:26 PM PDT 24
Finished Jun 05 03:55:30 PM PDT 24
Peak memory 200596 kb
Host smart-c6424379-74a4-40d6-b7fc-d5c87d6cacaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896323878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2896323878
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3133105299
Short name T547
Test name
Test status
Simulation time 239358940 ps
CPU time 1.58 seconds
Started Jun 05 03:55:08 PM PDT 24
Finished Jun 05 03:55:11 PM PDT 24
Peak memory 200464 kb
Host smart-c755df32-af98-46bc-a99a-337d7ca70eeb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133105299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3
133105299
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2341287834
Short name T566
Test name
Test status
Simulation time 1031964982 ps
CPU time 4.73 seconds
Started Jun 05 03:55:08 PM PDT 24
Finished Jun 05 03:55:14 PM PDT 24
Peak memory 200508 kb
Host smart-55aa2649-a660-4f90-888d-de1e6ad2e39f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341287834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2
341287834
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3330970462
Short name T580
Test name
Test status
Simulation time 125119309 ps
CPU time 0.89 seconds
Started Jun 05 03:55:14 PM PDT 24
Finished Jun 05 03:55:17 PM PDT 24
Peak memory 200272 kb
Host smart-24124228-587d-4565-bbd8-ab6db6de4abc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330970462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
330970462
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3802144324
Short name T575
Test name
Test status
Simulation time 69188131 ps
CPU time 0.78 seconds
Started Jun 05 03:55:07 PM PDT 24
Finished Jun 05 03:55:09 PM PDT 24
Peak memory 200260 kb
Host smart-0e5339e4-3f7a-4216-b472-6db8f1edde22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802144324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3802144324
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.239906355
Short name T569
Test name
Test status
Simulation time 102696728 ps
CPU time 1.4 seconds
Started Jun 05 03:55:06 PM PDT 24
Finished Jun 05 03:55:09 PM PDT 24
Peak memory 208728 kb
Host smart-b8b344f3-cebd-40ac-85af-d2e22fbcb525
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239906355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.239906355
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2684245801
Short name T620
Test name
Test status
Simulation time 973908143 ps
CPU time 3.01 seconds
Started Jun 05 03:55:09 PM PDT 24
Finished Jun 05 03:55:13 PM PDT 24
Peak memory 200888 kb
Host smart-b949e59d-8878-4f68-944d-14c5ca8fabbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684245801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2684245801
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2256989090
Short name T573
Test name
Test status
Simulation time 102039936 ps
CPU time 1.33 seconds
Started Jun 05 03:55:06 PM PDT 24
Finished Jun 05 03:55:08 PM PDT 24
Peak memory 200508 kb
Host smart-db6cee65-fecc-40b2-846f-f3eb3c32cd5c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256989090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
256989090
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3827323671
Short name T611
Test name
Test status
Simulation time 1197210660 ps
CPU time 5.26 seconds
Started Jun 05 03:55:07 PM PDT 24
Finished Jun 05 03:55:13 PM PDT 24
Peak memory 200512 kb
Host smart-c7dc8424-a5c0-4ec4-9222-3901531e145b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827323671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
827323671
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4115839749
Short name T568
Test name
Test status
Simulation time 104242758 ps
CPU time 0.84 seconds
Started Jun 05 03:55:06 PM PDT 24
Finished Jun 05 03:55:08 PM PDT 24
Peak memory 200312 kb
Host smart-2963d20a-c72d-4c3d-a060-73746ead0d2d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115839749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.4
115839749
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3646190428
Short name T562
Test name
Test status
Simulation time 140742125 ps
CPU time 1.13 seconds
Started Jun 05 03:55:06 PM PDT 24
Finished Jun 05 03:55:08 PM PDT 24
Peak memory 210596 kb
Host smart-f7d5a9f7-01fd-488a-b36f-bd5b2bec1f33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646190428 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3646190428
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.937702728
Short name T543
Test name
Test status
Simulation time 74315780 ps
CPU time 0.79 seconds
Started Jun 05 03:55:06 PM PDT 24
Finished Jun 05 03:55:07 PM PDT 24
Peak memory 200328 kb
Host smart-391e3fa9-117b-4b67-974a-0c67cf6ddb58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937702728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.937702728
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1201284212
Short name T58
Test name
Test status
Simulation time 113190863 ps
CPU time 1.23 seconds
Started Jun 05 03:55:08 PM PDT 24
Finished Jun 05 03:55:10 PM PDT 24
Peak memory 200624 kb
Host smart-23eb98d3-6a2e-44dd-988c-52565c2469bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201284212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1201284212
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2486056131
Short name T618
Test name
Test status
Simulation time 476084234 ps
CPU time 3.5 seconds
Started Jun 05 03:55:06 PM PDT 24
Finished Jun 05 03:55:11 PM PDT 24
Peak memory 208712 kb
Host smart-34eeaaa4-84d4-4fd1-9706-f12f1ee6a7b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486056131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2486056131
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1656637218
Short name T66
Test name
Test status
Simulation time 950464617 ps
CPU time 3.11 seconds
Started Jun 05 03:55:14 PM PDT 24
Finished Jun 05 03:55:18 PM PDT 24
Peak memory 200644 kb
Host smart-00f9d698-c0eb-4293-9870-5045dabdf4cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656637218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1656637218
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2656546149
Short name T582
Test name
Test status
Simulation time 126829644 ps
CPU time 0.97 seconds
Started Jun 05 03:55:17 PM PDT 24
Finished Jun 05 03:55:20 PM PDT 24
Peak memory 200296 kb
Host smart-9550ce08-459e-4773-b413-c8066aafab43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656546149 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2656546149
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3654869987
Short name T548
Test name
Test status
Simulation time 78784966 ps
CPU time 0.83 seconds
Started Jun 05 03:55:15 PM PDT 24
Finished Jun 05 03:55:18 PM PDT 24
Peak memory 200336 kb
Host smart-d8fef989-901d-49ab-961b-4c5a687da56b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654869987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3654869987
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2185818687
Short name T602
Test name
Test status
Simulation time 121124048 ps
CPU time 1.22 seconds
Started Jun 05 03:55:13 PM PDT 24
Finished Jun 05 03:55:15 PM PDT 24
Peak memory 200560 kb
Host smart-b6452b05-44cc-454d-9ee6-d5e758247d33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185818687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.2185818687
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2802896444
Short name T81
Test name
Test status
Simulation time 199030870 ps
CPU time 2.98 seconds
Started Jun 05 03:55:16 PM PDT 24
Finished Jun 05 03:55:20 PM PDT 24
Peak memory 212384 kb
Host smart-68a26848-cc2a-429f-9286-912b21917e04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802896444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2802896444
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.4191595251
Short name T106
Test name
Test status
Simulation time 460153718 ps
CPU time 1.89 seconds
Started Jun 05 03:55:15 PM PDT 24
Finished Jun 05 03:55:19 PM PDT 24
Peak memory 200552 kb
Host smart-05a81228-3c65-497d-8860-6a2c0cbe3e8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191595251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.4191595251
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.4143669954
Short name T544
Test name
Test status
Simulation time 200874018 ps
CPU time 1.26 seconds
Started Jun 05 03:55:17 PM PDT 24
Finished Jun 05 03:55:20 PM PDT 24
Peak memory 208560 kb
Host smart-2c96be5b-416c-479e-9df9-8da6ed23bf4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143669954 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.4143669954
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3432790241
Short name T588
Test name
Test status
Simulation time 77535433 ps
CPU time 0.9 seconds
Started Jun 05 03:55:19 PM PDT 24
Finished Jun 05 03:55:21 PM PDT 24
Peak memory 200352 kb
Host smart-b8e039e2-9545-43aa-8d98-acd91e927f35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432790241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3432790241
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1657785181
Short name T565
Test name
Test status
Simulation time 157233783 ps
CPU time 1.16 seconds
Started Jun 05 03:55:16 PM PDT 24
Finished Jun 05 03:55:19 PM PDT 24
Peak memory 200388 kb
Host smart-95c79e5d-5738-44db-88bc-7e6b66e29fe4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657785181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1657785181
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.251787816
Short name T593
Test name
Test status
Simulation time 153316152 ps
CPU time 2.07 seconds
Started Jun 05 03:55:17 PM PDT 24
Finished Jun 05 03:55:21 PM PDT 24
Peak memory 208776 kb
Host smart-2cc8817a-0d76-48fb-9101-dd6b4839d405
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251787816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.251787816
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.411853708
Short name T601
Test name
Test status
Simulation time 900251389 ps
CPU time 3.27 seconds
Started Jun 05 03:55:15 PM PDT 24
Finished Jun 05 03:55:20 PM PDT 24
Peak memory 200592 kb
Host smart-1259471e-991c-4871-aeff-dbd2bcb1d37e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411853708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.411853708
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1736478677
Short name T591
Test name
Test status
Simulation time 95568664 ps
CPU time 0.92 seconds
Started Jun 05 03:55:16 PM PDT 24
Finished Jun 05 03:55:19 PM PDT 24
Peak memory 200456 kb
Host smart-24a325a9-2263-492c-8598-5c72f3783a6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736478677 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1736478677
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2475736262
Short name T616
Test name
Test status
Simulation time 84745848 ps
CPU time 0.84 seconds
Started Jun 05 03:55:15 PM PDT 24
Finished Jun 05 03:55:17 PM PDT 24
Peak memory 200340 kb
Host smart-ed62c097-440a-49f4-8dce-fbcce03df1c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475736262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2475736262
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.497788827
Short name T557
Test name
Test status
Simulation time 136749530 ps
CPU time 1.31 seconds
Started Jun 05 03:55:15 PM PDT 24
Finished Jun 05 03:55:18 PM PDT 24
Peak memory 200528 kb
Host smart-48c2c60c-04e9-47fa-aea2-4d70ecdc398d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497788827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.497788827
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1743209962
Short name T603
Test name
Test status
Simulation time 325166634 ps
CPU time 2.43 seconds
Started Jun 05 03:55:20 PM PDT 24
Finished Jun 05 03:55:23 PM PDT 24
Peak memory 208748 kb
Host smart-4bf1bf1c-e5a1-484f-aef2-29059cc283b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743209962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1743209962
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2481827546
Short name T617
Test name
Test status
Simulation time 779913726 ps
CPU time 2.78 seconds
Started Jun 05 03:55:18 PM PDT 24
Finished Jun 05 03:55:22 PM PDT 24
Peak memory 200596 kb
Host smart-333fd42e-eb45-4e67-8cd6-ad87d7b64441
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481827546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.2481827546
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.277381887
Short name T607
Test name
Test status
Simulation time 182984710 ps
CPU time 1.2 seconds
Started Jun 05 03:55:19 PM PDT 24
Finished Jun 05 03:55:22 PM PDT 24
Peak memory 200416 kb
Host smart-ce443ac6-1a65-43c6-b8fa-bad8b2bedffb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277381887 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.277381887
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3538072472
Short name T563
Test name
Test status
Simulation time 81907248 ps
CPU time 0.92 seconds
Started Jun 05 03:55:14 PM PDT 24
Finished Jun 05 03:55:16 PM PDT 24
Peak memory 200340 kb
Host smart-cf9294a9-3409-434c-b600-9ae7e7e9f265
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538072472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3538072472
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.527849121
Short name T578
Test name
Test status
Simulation time 81656947 ps
CPU time 1 seconds
Started Jun 05 03:55:19 PM PDT 24
Finished Jun 05 03:55:21 PM PDT 24
Peak memory 200360 kb
Host smart-d1ec0410-1918-4edb-838a-e61f131f211f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527849121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.527849121
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1385046513
Short name T586
Test name
Test status
Simulation time 582238301 ps
CPU time 3.52 seconds
Started Jun 05 03:55:17 PM PDT 24
Finished Jun 05 03:55:23 PM PDT 24
Peak memory 208788 kb
Host smart-1b2fc7d6-c2d5-4221-bccb-d8aaf94f8872
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385046513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1385046513
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1232477739
Short name T121
Test name
Test status
Simulation time 435942314 ps
CPU time 1.85 seconds
Started Jun 05 03:55:15 PM PDT 24
Finished Jun 05 03:55:19 PM PDT 24
Peak memory 200640 kb
Host smart-e769d5fe-0c3d-4994-8833-7db4328b6b7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232477739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1232477739
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3869792295
Short name T82
Test name
Test status
Simulation time 224500472 ps
CPU time 1.39 seconds
Started Jun 05 03:55:16 PM PDT 24
Finished Jun 05 03:55:19 PM PDT 24
Peak memory 208668 kb
Host smart-a528a694-30fe-4720-8212-a56fe41f778d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869792295 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3869792295
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1517543153
Short name T610
Test name
Test status
Simulation time 75735659 ps
CPU time 0.81 seconds
Started Jun 05 03:55:18 PM PDT 24
Finished Jun 05 03:55:20 PM PDT 24
Peak memory 200276 kb
Host smart-f03ae052-5952-4da4-a96a-f9f642e489d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517543153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1517543153
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.848672629
Short name T612
Test name
Test status
Simulation time 76115989 ps
CPU time 0.98 seconds
Started Jun 05 03:55:17 PM PDT 24
Finished Jun 05 03:55:20 PM PDT 24
Peak memory 200296 kb
Host smart-8c48896a-b08c-4769-82e2-f0dd97082a6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848672629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_sa
me_csr_outstanding.848672629
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1810938541
Short name T103
Test name
Test status
Simulation time 406236255 ps
CPU time 3.16 seconds
Started Jun 05 03:55:18 PM PDT 24
Finished Jun 05 03:55:23 PM PDT 24
Peak memory 208780 kb
Host smart-ba17d0b8-d9e3-4f31-b8f9-4536d4fdbab1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810938541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1810938541
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.585268151
Short name T595
Test name
Test status
Simulation time 469734740 ps
CPU time 1.95 seconds
Started Jun 05 03:55:16 PM PDT 24
Finished Jun 05 03:55:20 PM PDT 24
Peak memory 200596 kb
Host smart-aab9c418-4652-4f3f-8c22-5d442c366a2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585268151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.585268151
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3100240927
Short name T600
Test name
Test status
Simulation time 58903796 ps
CPU time 0.83 seconds
Started Jun 05 03:55:26 PM PDT 24
Finished Jun 05 03:55:28 PM PDT 24
Peak memory 200572 kb
Host smart-aa5602c3-747d-4730-adb5-24cb4ed69ffb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100240927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3100240927
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1744131787
Short name T576
Test name
Test status
Simulation time 128690374 ps
CPU time 1.07 seconds
Started Jun 05 03:55:23 PM PDT 24
Finished Jun 05 03:55:25 PM PDT 24
Peak memory 200388 kb
Host smart-4112379f-1ade-41bc-b28d-6ae050b51808
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744131787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1744131787
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1977913986
Short name T581
Test name
Test status
Simulation time 452576241 ps
CPU time 2.95 seconds
Started Jun 05 03:55:27 PM PDT 24
Finished Jun 05 03:55:31 PM PDT 24
Peak memory 208764 kb
Host smart-af698b70-3169-4dae-8d87-1250f7206930
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977913986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1977913986
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2566719231
Short name T606
Test name
Test status
Simulation time 123948108 ps
CPU time 1 seconds
Started Jun 05 03:55:24 PM PDT 24
Finished Jun 05 03:55:26 PM PDT 24
Peak memory 200468 kb
Host smart-5a0433b7-91a0-40e5-a552-578f1b989043
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566719231 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2566719231
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.4150184786
Short name T94
Test name
Test status
Simulation time 69357777 ps
CPU time 0.84 seconds
Started Jun 05 03:55:27 PM PDT 24
Finished Jun 05 03:55:29 PM PDT 24
Peak memory 200284 kb
Host smart-cc318a18-2b19-4aef-b802-cf3883cfed8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150184786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.4150184786
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.719011780
Short name T598
Test name
Test status
Simulation time 124523566 ps
CPU time 1.14 seconds
Started Jun 05 03:55:27 PM PDT 24
Finished Jun 05 03:55:29 PM PDT 24
Peak memory 200364 kb
Host smart-ea81d22f-1793-4553-8a5f-37f41eb545a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719011780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.719011780
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2421350770
Short name T62
Test name
Test status
Simulation time 352125280 ps
CPU time 2.63 seconds
Started Jun 05 03:55:23 PM PDT 24
Finished Jun 05 03:55:26 PM PDT 24
Peak memory 208768 kb
Host smart-4e36e9f8-f16b-43f3-8f03-56600f59d10b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421350770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2421350770
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3109547428
Short name T605
Test name
Test status
Simulation time 139827774 ps
CPU time 1.13 seconds
Started Jun 05 03:55:25 PM PDT 24
Finished Jun 05 03:55:27 PM PDT 24
Peak memory 200452 kb
Host smart-74b032fe-8c38-492e-882e-6ff1752d0fc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109547428 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3109547428
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3526233652
Short name T98
Test name
Test status
Simulation time 92522444 ps
CPU time 0.91 seconds
Started Jun 05 03:55:26 PM PDT 24
Finished Jun 05 03:55:28 PM PDT 24
Peak memory 200272 kb
Host smart-e5fbd4f0-3371-49a4-bf77-fb6d95853962
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526233652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3526233652
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1986311050
Short name T584
Test name
Test status
Simulation time 208618141 ps
CPU time 1.43 seconds
Started Jun 05 03:55:25 PM PDT 24
Finished Jun 05 03:55:27 PM PDT 24
Peak memory 200612 kb
Host smart-52543485-ae06-4269-b16f-dc4a59035cc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986311050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1986311050
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3804138205
Short name T78
Test name
Test status
Simulation time 183666021 ps
CPU time 1.53 seconds
Started Jun 05 03:55:26 PM PDT 24
Finished Jun 05 03:55:28 PM PDT 24
Peak memory 208496 kb
Host smart-51ef8b6a-7684-4808-846d-98da4a698067
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804138205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3804138205
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2998235578
Short name T123
Test name
Test status
Simulation time 889570737 ps
CPU time 3.7 seconds
Started Jun 05 03:55:24 PM PDT 24
Finished Jun 05 03:55:29 PM PDT 24
Peak memory 200600 kb
Host smart-13189a85-ff9d-43db-a7e5-c7ee845e38e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998235578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2998235578
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.693200729
Short name T56
Test name
Test status
Simulation time 187993093 ps
CPU time 1.72 seconds
Started Jun 05 03:55:26 PM PDT 24
Finished Jun 05 03:55:29 PM PDT 24
Peak memory 208828 kb
Host smart-aaab06d3-b295-4719-82bc-da18a4db7ebe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693200729 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.693200729
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2126760806
Short name T613
Test name
Test status
Simulation time 84942694 ps
CPU time 0.87 seconds
Started Jun 05 03:55:27 PM PDT 24
Finished Jun 05 03:55:29 PM PDT 24
Peak memory 200320 kb
Host smart-bc8b60ad-cf71-4d30-8042-e7e41324c356
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126760806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2126760806
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1784311406
Short name T604
Test name
Test status
Simulation time 120950546 ps
CPU time 1.06 seconds
Started Jun 05 03:55:25 PM PDT 24
Finished Jun 05 03:55:28 PM PDT 24
Peak memory 200388 kb
Host smart-dc7ff611-024c-481a-80a5-deba762e9e80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784311406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1784311406
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1672128091
Short name T122
Test name
Test status
Simulation time 881796056 ps
CPU time 3.09 seconds
Started Jun 05 03:55:24 PM PDT 24
Finished Jun 05 03:55:27 PM PDT 24
Peak memory 200600 kb
Host smart-9b93f295-d22c-4505-9b93-aa192e7792d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672128091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1672128091
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.733720971
Short name T559
Test name
Test status
Simulation time 125831609 ps
CPU time 0.95 seconds
Started Jun 05 03:55:25 PM PDT 24
Finished Jun 05 03:55:27 PM PDT 24
Peak memory 200452 kb
Host smart-3ab82b5f-b192-48e7-8309-94c3af9c9b54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733720971 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.733720971
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.441855051
Short name T542
Test name
Test status
Simulation time 70730126 ps
CPU time 0.82 seconds
Started Jun 05 03:55:27 PM PDT 24
Finished Jun 05 03:55:29 PM PDT 24
Peak memory 200328 kb
Host smart-eb682ad8-10d4-406d-b46e-cb026f1cefac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441855051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.441855051
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.981681113
Short name T594
Test name
Test status
Simulation time 151290195 ps
CPU time 1.15 seconds
Started Jun 05 03:55:25 PM PDT 24
Finished Jun 05 03:55:27 PM PDT 24
Peak memory 200396 kb
Host smart-441e4639-7f7d-4c47-8c6f-7fcd08eb5dc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981681113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.981681113
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3164333884
Short name T567
Test name
Test status
Simulation time 324459049 ps
CPU time 2.71 seconds
Started Jun 05 03:55:24 PM PDT 24
Finished Jun 05 03:55:28 PM PDT 24
Peak memory 208796 kb
Host smart-6cb61d4b-87df-465e-99af-d8c6f653bb50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164333884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3164333884
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2528223735
Short name T545
Test name
Test status
Simulation time 155244826 ps
CPU time 1.97 seconds
Started Jun 05 03:55:09 PM PDT 24
Finished Jun 05 03:55:12 PM PDT 24
Peak memory 208664 kb
Host smart-9d225f55-19a1-4798-ac66-12fc9fb43bb3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528223735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
528223735
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2808727391
Short name T126
Test name
Test status
Simulation time 1986380145 ps
CPU time 8.93 seconds
Started Jun 05 03:55:07 PM PDT 24
Finished Jun 05 03:55:17 PM PDT 24
Peak memory 200512 kb
Host smart-66008444-072b-49e1-86a9-05eeabf791aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808727391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
808727391
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1430301271
Short name T550
Test name
Test status
Simulation time 140375107 ps
CPU time 0.92 seconds
Started Jun 05 03:55:06 PM PDT 24
Finished Jun 05 03:55:08 PM PDT 24
Peak memory 200256 kb
Host smart-b69c0d98-308c-4113-99f2-296ece8fdc29
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430301271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
430301271
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.4076211566
Short name T589
Test name
Test status
Simulation time 111905382 ps
CPU time 0.96 seconds
Started Jun 05 03:55:14 PM PDT 24
Finished Jun 05 03:55:17 PM PDT 24
Peak memory 200388 kb
Host smart-a09145d8-d8b8-40dc-b286-cd7f1844a249
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076211566 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.4076211566
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.894216870
Short name T615
Test name
Test status
Simulation time 57704112 ps
CPU time 0.79 seconds
Started Jun 05 03:55:06 PM PDT 24
Finished Jun 05 03:55:09 PM PDT 24
Peak memory 200340 kb
Host smart-a49f5f1f-9bc5-47c5-93b1-8e26260e77c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894216870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.894216870
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1284537655
Short name T561
Test name
Test status
Simulation time 193125098 ps
CPU time 1.48 seconds
Started Jun 05 03:55:05 PM PDT 24
Finished Jun 05 03:55:07 PM PDT 24
Peak memory 200584 kb
Host smart-8b5f570d-e6ef-48da-9227-4c2c78cba663
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284537655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1284537655
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3344224776
Short name T60
Test name
Test status
Simulation time 102539819 ps
CPU time 1.41 seconds
Started Jun 05 03:55:06 PM PDT 24
Finished Jun 05 03:55:09 PM PDT 24
Peak memory 208668 kb
Host smart-4693c432-4de6-4563-9489-5deeb360ed07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344224776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3344224776
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2990176686
Short name T619
Test name
Test status
Simulation time 945534007 ps
CPU time 2.94 seconds
Started Jun 05 03:55:06 PM PDT 24
Finished Jun 05 03:55:11 PM PDT 24
Peak memory 200640 kb
Host smart-2eb409c1-e07a-4284-9b01-f30ce36429b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990176686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.2990176686
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3606331733
Short name T546
Test name
Test status
Simulation time 401364134 ps
CPU time 2.53 seconds
Started Jun 05 03:55:07 PM PDT 24
Finished Jun 05 03:55:11 PM PDT 24
Peak memory 200508 kb
Host smart-4262f7ac-a735-4ed4-9774-b10742ecffdd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606331733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
606331733
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1667118145
Short name T574
Test name
Test status
Simulation time 492079968 ps
CPU time 5.54 seconds
Started Jun 05 03:55:14 PM PDT 24
Finished Jun 05 03:55:21 PM PDT 24
Peak memory 200492 kb
Host smart-3431fb70-5977-4b63-8ace-292d49e29e3e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667118145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
667118145
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3324154306
Short name T579
Test name
Test status
Simulation time 97748049 ps
CPU time 0.78 seconds
Started Jun 05 03:55:08 PM PDT 24
Finished Jun 05 03:55:09 PM PDT 24
Peak memory 200560 kb
Host smart-64644104-edd7-47e4-bfe9-fc0082e10302
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324154306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
324154306
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2910408832
Short name T614
Test name
Test status
Simulation time 130790961 ps
CPU time 1.09 seconds
Started Jun 05 03:55:15 PM PDT 24
Finished Jun 05 03:55:18 PM PDT 24
Peak memory 208632 kb
Host smart-daecb9a9-4e07-4788-9b55-a0237c32d2e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910408832 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2910408832
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3220443306
Short name T96
Test name
Test status
Simulation time 76531925 ps
CPU time 0.77 seconds
Started Jun 05 03:55:09 PM PDT 24
Finished Jun 05 03:55:11 PM PDT 24
Peak memory 200276 kb
Host smart-1b944f01-fd6d-46b4-845b-6f1cc5506acb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220443306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3220443306
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3598628372
Short name T57
Test name
Test status
Simulation time 257285166 ps
CPU time 1.58 seconds
Started Jun 05 03:55:06 PM PDT 24
Finished Jun 05 03:55:09 PM PDT 24
Peak memory 200540 kb
Host smart-5810832e-15d3-426f-8a81-dc8aa32b6b22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598628372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3598628372
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.4157892899
Short name T587
Test name
Test status
Simulation time 269117040 ps
CPU time 2.24 seconds
Started Jun 05 03:55:06 PM PDT 24
Finished Jun 05 03:55:10 PM PDT 24
Peak memory 208780 kb
Host smart-cb41f731-02f6-4d3c-9e7a-d23ea43efeaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157892899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.4157892899
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1910423977
Short name T590
Test name
Test status
Simulation time 883208649 ps
CPU time 3.15 seconds
Started Jun 05 03:55:15 PM PDT 24
Finished Jun 05 03:55:20 PM PDT 24
Peak memory 200576 kb
Host smart-0e20f4da-fb14-4894-a6c2-f8f5700f7fd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910423977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1910423977
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.684050919
Short name T564
Test name
Test status
Simulation time 420412406 ps
CPU time 2.58 seconds
Started Jun 05 03:55:14 PM PDT 24
Finished Jun 05 03:55:18 PM PDT 24
Peak memory 200428 kb
Host smart-e3d011d8-2048-4e47-abaa-e4ce1a517679
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684050919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.684050919
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.19274912
Short name T583
Test name
Test status
Simulation time 1027710704 ps
CPU time 4.82 seconds
Started Jun 05 03:55:18 PM PDT 24
Finished Jun 05 03:55:25 PM PDT 24
Peak memory 200520 kb
Host smart-8c935a98-8ff3-4238-b3f6-145b411f5e01
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19274912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.19274912
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.92219368
Short name T554
Test name
Test status
Simulation time 138277015 ps
CPU time 0.97 seconds
Started Jun 05 03:55:15 PM PDT 24
Finished Jun 05 03:55:18 PM PDT 24
Peak memory 200328 kb
Host smart-32d0363d-3ed2-473e-b131-2e299a23ba0a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92219368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.92219368
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3102016098
Short name T549
Test name
Test status
Simulation time 202232999 ps
CPU time 1.3 seconds
Started Jun 05 03:55:17 PM PDT 24
Finished Jun 05 03:55:20 PM PDT 24
Peak memory 200452 kb
Host smart-3e988c86-90fb-4308-88b4-3767bd4a23ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102016098 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.3102016098
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3145417335
Short name T592
Test name
Test status
Simulation time 78248963 ps
CPU time 0.8 seconds
Started Jun 05 03:55:16 PM PDT 24
Finished Jun 05 03:55:18 PM PDT 24
Peak memory 200264 kb
Host smart-53ecc291-794b-45b5-9e4c-6455016d2e96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145417335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3145417335
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2120228774
Short name T556
Test name
Test status
Simulation time 158165750 ps
CPU time 1.19 seconds
Started Jun 05 03:55:13 PM PDT 24
Finished Jun 05 03:55:15 PM PDT 24
Peak memory 200384 kb
Host smart-c5868b78-cda6-4ef1-981c-191f553968ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120228774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.2120228774
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.4242646664
Short name T61
Test name
Test status
Simulation time 178197590 ps
CPU time 2.52 seconds
Started Jun 05 03:55:09 PM PDT 24
Finished Jun 05 03:55:13 PM PDT 24
Peak memory 212268 kb
Host smart-2dbe82b5-1936-415f-8247-ed922d3eb19a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242646664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.4242646664
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.4206384385
Short name T79
Test name
Test status
Simulation time 136022450 ps
CPU time 1.01 seconds
Started Jun 05 03:55:15 PM PDT 24
Finished Jun 05 03:55:18 PM PDT 24
Peak memory 200752 kb
Host smart-ff941edd-0312-4bdb-bab5-111c4b1b9472
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206384385 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.4206384385
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1263516130
Short name T125
Test name
Test status
Simulation time 78480411 ps
CPU time 0.8 seconds
Started Jun 05 03:55:15 PM PDT 24
Finished Jun 05 03:55:18 PM PDT 24
Peak memory 200332 kb
Host smart-d9923021-5929-4662-b7a0-6746bf35b0f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263516130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1263516130
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4034233843
Short name T570
Test name
Test status
Simulation time 120953840 ps
CPU time 1.08 seconds
Started Jun 05 03:55:16 PM PDT 24
Finished Jun 05 03:55:19 PM PDT 24
Peak memory 200396 kb
Host smart-9b95526d-16d7-4ce7-82b2-13bd2418842f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034233843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.4034233843
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2967696556
Short name T552
Test name
Test status
Simulation time 337917579 ps
CPU time 2.45 seconds
Started Jun 05 03:55:15 PM PDT 24
Finished Jun 05 03:55:20 PM PDT 24
Peak memory 208732 kb
Host smart-eb487576-5b12-472f-a16c-b8567a1476a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967696556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2967696556
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2014447090
Short name T105
Test name
Test status
Simulation time 560989670 ps
CPU time 2.11 seconds
Started Jun 05 03:55:16 PM PDT 24
Finished Jun 05 03:55:20 PM PDT 24
Peak memory 200624 kb
Host smart-cf4f6e26-2699-4a7b-b98e-43daf22179f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014447090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2014447090
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3371000980
Short name T577
Test name
Test status
Simulation time 130982192 ps
CPU time 1.12 seconds
Started Jun 05 03:55:15 PM PDT 24
Finished Jun 05 03:55:17 PM PDT 24
Peak memory 208552 kb
Host smart-cd4ac181-c818-4842-b785-d19429be49b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371000980 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.3371000980
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3836273483
Short name T551
Test name
Test status
Simulation time 76956881 ps
CPU time 0.88 seconds
Started Jun 05 03:55:14 PM PDT 24
Finished Jun 05 03:55:17 PM PDT 24
Peak memory 200336 kb
Host smart-814d3b51-65c3-4e13-b0a2-ca519b183143
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836273483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3836273483
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4119663545
Short name T555
Test name
Test status
Simulation time 148576560 ps
CPU time 1.15 seconds
Started Jun 05 03:55:16 PM PDT 24
Finished Jun 05 03:55:19 PM PDT 24
Peak memory 200412 kb
Host smart-3b203d52-44c5-439f-a010-a0c0b6e98327
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119663545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.4119663545
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2104335519
Short name T597
Test name
Test status
Simulation time 141444092 ps
CPU time 2.11 seconds
Started Jun 05 03:55:15 PM PDT 24
Finished Jun 05 03:55:18 PM PDT 24
Peak memory 208748 kb
Host smart-356541d9-ac5f-476e-97db-4d9365f06b87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104335519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2104335519
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3051830478
Short name T101
Test name
Test status
Simulation time 884905850 ps
CPU time 2.96 seconds
Started Jun 05 03:55:17 PM PDT 24
Finished Jun 05 03:55:21 PM PDT 24
Peak memory 200624 kb
Host smart-62f9c65e-028c-4489-a302-a1c1c3322e41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051830478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3051830478
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3582060660
Short name T608
Test name
Test status
Simulation time 124775981 ps
CPU time 1.01 seconds
Started Jun 05 03:55:15 PM PDT 24
Finished Jun 05 03:55:18 PM PDT 24
Peak memory 200700 kb
Host smart-1c971b1f-2e5a-4ebe-8a6e-7ceb349eea16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582060660 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3582060660
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.689596305
Short name T97
Test name
Test status
Simulation time 82699540 ps
CPU time 0.91 seconds
Started Jun 05 03:55:18 PM PDT 24
Finished Jun 05 03:55:20 PM PDT 24
Peak memory 200332 kb
Host smart-29bc5c3f-5a55-4f76-8d24-9cacbb8d6266
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689596305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.689596305
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3563406319
Short name T571
Test name
Test status
Simulation time 257899114 ps
CPU time 1.56 seconds
Started Jun 05 03:55:16 PM PDT 24
Finished Jun 05 03:55:20 PM PDT 24
Peak memory 200572 kb
Host smart-2c37fb48-6470-428e-8c40-da9d3b46c388
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563406319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3563406319
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2185376373
Short name T553
Test name
Test status
Simulation time 114322188 ps
CPU time 1.55 seconds
Started Jun 05 03:55:14 PM PDT 24
Finished Jun 05 03:55:16 PM PDT 24
Peak memory 208836 kb
Host smart-bba37079-170e-4646-8a98-df6097e7f78f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185376373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2185376373
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.960541485
Short name T609
Test name
Test status
Simulation time 949993659 ps
CPU time 3.14 seconds
Started Jun 05 03:55:15 PM PDT 24
Finished Jun 05 03:55:19 PM PDT 24
Peak memory 200592 kb
Host smart-b5b3b6de-8eaf-43b2-9931-66644299bc92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960541485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
960541485
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.399133829
Short name T585
Test name
Test status
Simulation time 195832879 ps
CPU time 1.27 seconds
Started Jun 05 03:55:18 PM PDT 24
Finished Jun 05 03:55:21 PM PDT 24
Peak memory 208636 kb
Host smart-a12489d9-6483-46da-94e9-d08d30b4e1e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399133829 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.399133829
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1183127855
Short name T99
Test name
Test status
Simulation time 57648661 ps
CPU time 0.82 seconds
Started Jun 05 03:55:15 PM PDT 24
Finished Jun 05 03:55:17 PM PDT 24
Peak memory 200344 kb
Host smart-8aa3e37f-551e-4f68-af24-b7866d477700
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183127855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1183127855
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1568304388
Short name T558
Test name
Test status
Simulation time 96662724 ps
CPU time 1.15 seconds
Started Jun 05 03:55:15 PM PDT 24
Finished Jun 05 03:55:18 PM PDT 24
Peak memory 200580 kb
Host smart-516a41df-3704-4d1d-82f8-ac1ddeff1c5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568304388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.1568304388
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1465904267
Short name T102
Test name
Test status
Simulation time 274792876 ps
CPU time 1.96 seconds
Started Jun 05 03:55:16 PM PDT 24
Finished Jun 05 03:55:20 PM PDT 24
Peak memory 208760 kb
Host smart-24aaca10-4e72-47cc-ac2f-e999f546cd7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465904267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1465904267
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.498721119
Short name T124
Test name
Test status
Simulation time 794073949 ps
CPU time 2.83 seconds
Started Jun 05 03:55:17 PM PDT 24
Finished Jun 05 03:55:21 PM PDT 24
Peak memory 200624 kb
Host smart-18c42408-0d62-4c66-acd3-61e6d9c510e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498721119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
498721119
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.626796523
Short name T596
Test name
Test status
Simulation time 94229939 ps
CPU time 0.9 seconds
Started Jun 05 03:55:14 PM PDT 24
Finished Jun 05 03:55:17 PM PDT 24
Peak memory 200384 kb
Host smart-5b1c6aec-1c23-4124-8856-5ead51511836
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626796523 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.626796523
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.391503578
Short name T95
Test name
Test status
Simulation time 90401221 ps
CPU time 0.88 seconds
Started Jun 05 03:55:21 PM PDT 24
Finished Jun 05 03:55:22 PM PDT 24
Peak memory 200324 kb
Host smart-4d21db51-7445-46f0-a062-952344ef0e65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391503578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.391503578
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3128499925
Short name T93
Test name
Test status
Simulation time 84991924 ps
CPU time 0.93 seconds
Started Jun 05 03:55:14 PM PDT 24
Finished Jun 05 03:55:16 PM PDT 24
Peak memory 200388 kb
Host smart-4adb4145-6041-4658-8e76-29cfb4ec6960
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128499925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3128499925
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.642529931
Short name T599
Test name
Test status
Simulation time 626110442 ps
CPU time 4.58 seconds
Started Jun 05 03:55:14 PM PDT 24
Finished Jun 05 03:55:21 PM PDT 24
Peak memory 208832 kb
Host smart-1b4d6803-3059-4d40-9be3-acc0cf769801
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642529931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.642529931
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2724791517
Short name T572
Test name
Test status
Simulation time 793878446 ps
CPU time 2.66 seconds
Started Jun 05 03:55:17 PM PDT 24
Finished Jun 05 03:55:22 PM PDT 24
Peak memory 200568 kb
Host smart-c234ef16-04ea-41d2-9a81-fd453e6449d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724791517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.2724791517
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.634817112
Short name T500
Test name
Test status
Simulation time 65066983 ps
CPU time 0.76 seconds
Started Jun 05 03:53:00 PM PDT 24
Finished Jun 05 03:53:03 PM PDT 24
Peak memory 200644 kb
Host smart-cc894c42-ed16-40aa-ad96-7038a0f1051c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634817112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.634817112
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2706896782
Short name T10
Test name
Test status
Simulation time 2361710917 ps
CPU time 7.54 seconds
Started Jun 05 03:52:55 PM PDT 24
Finished Jun 05 03:53:03 PM PDT 24
Peak memory 222568 kb
Host smart-3f386ce4-ed3d-44cc-967e-a265bb0c1bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706896782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2706896782
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3726293089
Short name T484
Test name
Test status
Simulation time 245118750 ps
CPU time 1.05 seconds
Started Jun 05 03:52:57 PM PDT 24
Finished Jun 05 03:52:59 PM PDT 24
Peak memory 217940 kb
Host smart-aac7e51e-4fb8-46b9-a79f-ac23f8e94f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726293089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3726293089
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.805958705
Short name T378
Test name
Test status
Simulation time 78453426 ps
CPU time 0.76 seconds
Started Jun 05 03:52:58 PM PDT 24
Finished Jun 05 03:53:01 PM PDT 24
Peak memory 200620 kb
Host smart-9b0f6ecc-0a90-4029-a579-d07f5c9caf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805958705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.805958705
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.875393790
Short name T483
Test name
Test status
Simulation time 1133004950 ps
CPU time 5.3 seconds
Started Jun 05 03:52:55 PM PDT 24
Finished Jun 05 03:53:01 PM PDT 24
Peak memory 200988 kb
Host smart-d5549774-3ff9-4aad-a12f-3f62c460716f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875393790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.875393790
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.7972562
Short name T67
Test name
Test status
Simulation time 17669040024 ps
CPU time 25.78 seconds
Started Jun 05 03:52:56 PM PDT 24
Finished Jun 05 03:53:23 PM PDT 24
Peak memory 218652 kb
Host smart-883be158-0202-4819-9d30-33193ecd1cbd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7972562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.7972562
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.402355764
Short name T443
Test name
Test status
Simulation time 195037947 ps
CPU time 1.22 seconds
Started Jun 05 03:52:58 PM PDT 24
Finished Jun 05 03:53:01 PM PDT 24
Peak memory 200840 kb
Host smart-9d313163-9552-4270-8621-97404e32e8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402355764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.402355764
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.3821129020
Short name T218
Test name
Test status
Simulation time 193538088 ps
CPU time 1.39 seconds
Started Jun 05 03:52:55 PM PDT 24
Finished Jun 05 03:52:57 PM PDT 24
Peak memory 200896 kb
Host smart-3e1f7f93-ab3b-4860-9bb2-0690543f0dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821129020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3821129020
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1246763433
Short name T72
Test name
Test status
Simulation time 3457223900 ps
CPU time 13.05 seconds
Started Jun 05 03:52:58 PM PDT 24
Finished Jun 05 03:53:12 PM PDT 24
Peak memory 201048 kb
Host smart-bafea913-32d6-4a4f-93da-5fe67927273b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246763433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1246763433
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.536547765
Short name T200
Test name
Test status
Simulation time 300249900 ps
CPU time 2.01 seconds
Started Jun 05 03:52:56 PM PDT 24
Finished Jun 05 03:52:59 PM PDT 24
Peak memory 209000 kb
Host smart-b97a3232-078b-454b-8230-77071db6c4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536547765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.536547765
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3625894244
Short name T192
Test name
Test status
Simulation time 91949946 ps
CPU time 0.86 seconds
Started Jun 05 03:52:56 PM PDT 24
Finished Jun 05 03:52:58 PM PDT 24
Peak memory 200716 kb
Host smart-99503788-e8c0-448a-a962-64f96c55153f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625894244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3625894244
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1876264246
Short name T268
Test name
Test status
Simulation time 67207998 ps
CPU time 0.85 seconds
Started Jun 05 03:53:04 PM PDT 24
Finished Jun 05 03:53:06 PM PDT 24
Peak memory 200652 kb
Host smart-50024989-2c14-4289-818a-1aedbe150cce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876264246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1876264246
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2937620484
Short name T441
Test name
Test status
Simulation time 2366767117 ps
CPU time 8.6 seconds
Started Jun 05 03:52:58 PM PDT 24
Finished Jun 05 03:53:08 PM PDT 24
Peak memory 221916 kb
Host smart-0aefc6d8-2bad-4f03-ba0b-abb5aae0a339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937620484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2937620484
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2094068955
Short name T398
Test name
Test status
Simulation time 246401898 ps
CPU time 1.09 seconds
Started Jun 05 03:52:59 PM PDT 24
Finished Jun 05 03:53:02 PM PDT 24
Peak memory 217844 kb
Host smart-d026874e-c228-4f14-8cae-fa5cf590c400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094068955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2094068955
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.1119316791
Short name T279
Test name
Test status
Simulation time 114123806 ps
CPU time 0.79 seconds
Started Jun 05 03:52:56 PM PDT 24
Finished Jun 05 03:52:58 PM PDT 24
Peak memory 200612 kb
Host smart-0e9dd9b6-5a2f-4272-9eaa-e5936fc1a579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119316791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.1119316791
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1659095958
Short name T530
Test name
Test status
Simulation time 1898379413 ps
CPU time 6.79 seconds
Started Jun 05 03:53:06 PM PDT 24
Finished Jun 05 03:53:14 PM PDT 24
Peak memory 200888 kb
Host smart-043370b8-441e-47e1-80ab-9ccd93fe8e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659095958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1659095958
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3221846093
Short name T63
Test name
Test status
Simulation time 16728872757 ps
CPU time 25.72 seconds
Started Jun 05 03:52:55 PM PDT 24
Finished Jun 05 03:53:22 PM PDT 24
Peak memory 217560 kb
Host smart-047d021e-7c8f-4a99-9ba8-b9e5d0533fd9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221846093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3221846093
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1581411560
Short name T396
Test name
Test status
Simulation time 138616547 ps
CPU time 1.02 seconds
Started Jun 05 03:52:55 PM PDT 24
Finished Jun 05 03:52:57 PM PDT 24
Peak memory 200828 kb
Host smart-9319299e-06dc-422a-b98a-2d3972937e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581411560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1581411560
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.182646175
Short name T153
Test name
Test status
Simulation time 202653663 ps
CPU time 1.44 seconds
Started Jun 05 03:52:58 PM PDT 24
Finished Jun 05 03:53:01 PM PDT 24
Peak memory 201056 kb
Host smart-b4daf3cc-5050-4d13-8a77-b55e73299ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182646175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.182646175
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1605173004
Short name T390
Test name
Test status
Simulation time 10504908083 ps
CPU time 40.45 seconds
Started Jun 05 03:52:58 PM PDT 24
Finished Jun 05 03:53:40 PM PDT 24
Peak memory 209380 kb
Host smart-187c43ac-26ed-44b6-89c3-6cf7f9628d35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605173004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1605173004
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.981293825
Short name T478
Test name
Test status
Simulation time 152951514 ps
CPU time 1.86 seconds
Started Jun 05 03:53:01 PM PDT 24
Finished Jun 05 03:53:04 PM PDT 24
Peak memory 200800 kb
Host smart-4d09586d-c210-4400-9cf5-fdb02d4a0eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981293825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.981293825
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.658786296
Short name T1
Test name
Test status
Simulation time 78455485 ps
CPU time 0.75 seconds
Started Jun 05 03:52:55 PM PDT 24
Finished Jun 05 03:52:57 PM PDT 24
Peak memory 200808 kb
Host smart-53495d6a-dd3e-4d91-934f-8c40465a2186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658786296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.658786296
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.675472444
Short name T494
Test name
Test status
Simulation time 72735835 ps
CPU time 0.76 seconds
Started Jun 05 03:53:45 PM PDT 24
Finished Jun 05 03:53:46 PM PDT 24
Peak memory 200644 kb
Host smart-a978050a-e3b5-4c37-949f-3e9322669a90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675472444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.675472444
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1289645966
Short name T534
Test name
Test status
Simulation time 1902719686 ps
CPU time 6.56 seconds
Started Jun 05 03:53:46 PM PDT 24
Finished Jun 05 03:53:53 PM PDT 24
Peak memory 217388 kb
Host smart-9c0234f1-d3f1-4061-aff7-211329639859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289645966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1289645966
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2546232378
Short name T525
Test name
Test status
Simulation time 244655228 ps
CPU time 1.07 seconds
Started Jun 05 03:53:45 PM PDT 24
Finished Jun 05 03:53:48 PM PDT 24
Peak memory 218016 kb
Host smart-956d073e-a7d4-4480-9f39-1136d3a8f716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546232378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2546232378
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.427760755
Short name T471
Test name
Test status
Simulation time 85032473 ps
CPU time 0.73 seconds
Started Jun 05 03:53:36 PM PDT 24
Finished Jun 05 03:53:38 PM PDT 24
Peak memory 200488 kb
Host smart-83e609cc-7a0d-40cb-8e5d-3e83bcd0e7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427760755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.427760755
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2075627504
Short name T305
Test name
Test status
Simulation time 1624800245 ps
CPU time 6.53 seconds
Started Jun 05 03:53:37 PM PDT 24
Finished Jun 05 03:53:44 PM PDT 24
Peak memory 201004 kb
Host smart-af4107a9-e2fb-42fa-8bcb-7d0b38fa5560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075627504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2075627504
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2132051876
Short name T316
Test name
Test status
Simulation time 177616717 ps
CPU time 1.15 seconds
Started Jun 05 03:53:45 PM PDT 24
Finished Jun 05 03:53:47 PM PDT 24
Peak memory 200792 kb
Host smart-9498c6b4-0b2b-460c-9e3e-eebb57d2298b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132051876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2132051876
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.3824256379
Short name T219
Test name
Test status
Simulation time 115698804 ps
CPU time 1.12 seconds
Started Jun 05 03:53:40 PM PDT 24
Finished Jun 05 03:53:42 PM PDT 24
Peak memory 201000 kb
Host smart-5571e53c-efa7-47af-872c-0979ea6346ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824256379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3824256379
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1079500720
Short name T207
Test name
Test status
Simulation time 3775680662 ps
CPU time 16.59 seconds
Started Jun 05 03:53:46 PM PDT 24
Finished Jun 05 03:54:03 PM PDT 24
Peak memory 209276 kb
Host smart-3c70c7ad-30f7-4df2-9f7b-bec43656cd23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079500720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1079500720
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2592200428
Short name T114
Test name
Test status
Simulation time 436071740 ps
CPU time 2.22 seconds
Started Jun 05 03:53:45 PM PDT 24
Finished Jun 05 03:53:48 PM PDT 24
Peak memory 208908 kb
Host smart-1b5ce4e5-95fd-4a13-af57-bbd3be7c8e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592200428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2592200428
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3615227817
Short name T133
Test name
Test status
Simulation time 108499020 ps
CPU time 0.96 seconds
Started Jun 05 03:53:45 PM PDT 24
Finished Jun 05 03:53:46 PM PDT 24
Peak memory 200808 kb
Host smart-6e33eac5-fcb0-4eea-a9aa-1c43969b26bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615227817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3615227817
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1740513487
Short name T235
Test name
Test status
Simulation time 64408498 ps
CPU time 0.79 seconds
Started Jun 05 03:53:44 PM PDT 24
Finished Jun 05 03:53:45 PM PDT 24
Peak memory 200644 kb
Host smart-639d4614-648c-4fe2-87aa-d3f206ec0ae0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740513487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1740513487
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2314277008
Short name T376
Test name
Test status
Simulation time 1228658817 ps
CPU time 5.9 seconds
Started Jun 05 03:53:45 PM PDT 24
Finished Jun 05 03:53:51 PM PDT 24
Peak memory 217868 kb
Host smart-c00c53a8-2b7a-45c3-adaf-39cbf468732f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314277008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2314277008
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.746257523
Short name T360
Test name
Test status
Simulation time 244156888 ps
CPU time 1.04 seconds
Started Jun 05 03:53:59 PM PDT 24
Finished Jun 05 03:54:01 PM PDT 24
Peak memory 217864 kb
Host smart-d809c51c-2f21-49c8-99dd-302d0c0782c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746257523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.746257523
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.186537604
Short name T386
Test name
Test status
Simulation time 80236093 ps
CPU time 0.75 seconds
Started Jun 05 03:53:46 PM PDT 24
Finished Jun 05 03:53:48 PM PDT 24
Peak memory 200608 kb
Host smart-6269bbb6-2634-4dca-ad6b-9905f1811fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186537604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.186537604
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2388340967
Short name T340
Test name
Test status
Simulation time 182873407 ps
CPU time 1.19 seconds
Started Jun 05 03:53:45 PM PDT 24
Finished Jun 05 03:53:47 PM PDT 24
Peak memory 200804 kb
Host smart-d0715ba3-e735-4439-b27b-2237d87f2368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388340967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2388340967
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1924068449
Short name T344
Test name
Test status
Simulation time 255899583 ps
CPU time 1.55 seconds
Started Jun 05 03:53:45 PM PDT 24
Finished Jun 05 03:53:47 PM PDT 24
Peak memory 200992 kb
Host smart-33df26f9-b300-4f31-adfe-bda548b114a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924068449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1924068449
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.962373731
Short name T282
Test name
Test status
Simulation time 3496014920 ps
CPU time 13.76 seconds
Started Jun 05 03:53:43 PM PDT 24
Finished Jun 05 03:53:57 PM PDT 24
Peak memory 201092 kb
Host smart-23a410f7-2b1a-4643-aa29-9c8b528d262b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962373731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.962373731
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.356843221
Short name T7
Test name
Test status
Simulation time 335833566 ps
CPU time 2.22 seconds
Started Jun 05 03:53:45 PM PDT 24
Finished Jun 05 03:53:48 PM PDT 24
Peak memory 209092 kb
Host smart-570af1ef-fa1b-4a33-9347-2b88566bff10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356843221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.356843221
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1937214062
Short name T157
Test name
Test status
Simulation time 91574563 ps
CPU time 0.88 seconds
Started Jun 05 03:53:47 PM PDT 24
Finished Jun 05 03:53:49 PM PDT 24
Peak memory 200784 kb
Host smart-c8ea2a9b-3e02-45e5-91f8-5f789462d3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937214062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1937214062
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2459352663
Short name T447
Test name
Test status
Simulation time 99027619 ps
CPU time 0.88 seconds
Started Jun 05 03:53:59 PM PDT 24
Finished Jun 05 03:54:00 PM PDT 24
Peak memory 200560 kb
Host smart-651bfe76-7cab-4386-a1ed-9c82f32b3682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459352663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2459352663
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.934209053
Short name T310
Test name
Test status
Simulation time 2360805818 ps
CPU time 8.38 seconds
Started Jun 05 03:53:47 PM PDT 24
Finished Jun 05 03:53:57 PM PDT 24
Peak memory 222292 kb
Host smart-61807583-4ba3-444b-acac-cd95db92c909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934209053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.934209053
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1848808609
Short name T537
Test name
Test status
Simulation time 243984877 ps
CPU time 1.03 seconds
Started Jun 05 03:53:45 PM PDT 24
Finished Jun 05 03:53:48 PM PDT 24
Peak memory 217968 kb
Host smart-4e65b5cc-e98f-4cd8-9897-d57dd53cc37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848808609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1848808609
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.573021128
Short name T462
Test name
Test status
Simulation time 165911779 ps
CPU time 0.83 seconds
Started Jun 05 03:53:46 PM PDT 24
Finished Jun 05 03:53:48 PM PDT 24
Peak memory 200492 kb
Host smart-599a7267-7021-4e52-9795-912edc720d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573021128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.573021128
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3687461177
Short name T446
Test name
Test status
Simulation time 1427494706 ps
CPU time 5.76 seconds
Started Jun 05 03:53:45 PM PDT 24
Finished Jun 05 03:53:52 PM PDT 24
Peak memory 200916 kb
Host smart-2bd9ed26-6a96-4ad7-b7ec-eb63570c260c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687461177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3687461177
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2722200598
Short name T295
Test name
Test status
Simulation time 102321728 ps
CPU time 0.96 seconds
Started Jun 05 03:53:59 PM PDT 24
Finished Jun 05 03:54:00 PM PDT 24
Peak memory 200720 kb
Host smart-a17b815b-7737-406c-bd48-1057f3f12306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722200598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2722200598
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2220441661
Short name T198
Test name
Test status
Simulation time 243872130 ps
CPU time 1.52 seconds
Started Jun 05 03:53:45 PM PDT 24
Finished Jun 05 03:53:48 PM PDT 24
Peak memory 200952 kb
Host smart-5ba1c36c-0f3c-4120-9e8d-321a373edcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220441661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2220441661
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2294634497
Short name T211
Test name
Test status
Simulation time 210481090 ps
CPU time 1.44 seconds
Started Jun 05 03:53:48 PM PDT 24
Finished Jun 05 03:53:51 PM PDT 24
Peak memory 201000 kb
Host smart-b94f7aa9-fd80-4582-88e3-8bb31f1f7d04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294634497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2294634497
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.3103835272
Short name T241
Test name
Test status
Simulation time 303737889 ps
CPU time 1.96 seconds
Started Jun 05 03:53:46 PM PDT 24
Finished Jun 05 03:53:49 PM PDT 24
Peak memory 208992 kb
Host smart-ae4232c6-cf57-4ab0-80db-a8024dfd80e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103835272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3103835272
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.282026448
Short name T257
Test name
Test status
Simulation time 108328588 ps
CPU time 1 seconds
Started Jun 05 03:53:59 PM PDT 24
Finished Jun 05 03:54:00 PM PDT 24
Peak memory 200724 kb
Host smart-525dd5f9-9b8e-48c4-8b2e-859b58db124f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282026448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.282026448
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1523458876
Short name T382
Test name
Test status
Simulation time 70661020 ps
CPU time 0.75 seconds
Started Jun 05 03:53:56 PM PDT 24
Finished Jun 05 03:53:57 PM PDT 24
Peak memory 200644 kb
Host smart-47909dcb-2043-44d5-83b9-5de13190f68f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523458876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1523458876
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.4017281109
Short name T442
Test name
Test status
Simulation time 244236087 ps
CPU time 1.15 seconds
Started Jun 05 03:53:45 PM PDT 24
Finished Jun 05 03:53:48 PM PDT 24
Peak memory 217860 kb
Host smart-d924507d-a219-45b7-9a90-40d7838ea882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017281109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.4017281109
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1181373246
Short name T373
Test name
Test status
Simulation time 230192088 ps
CPU time 0.93 seconds
Started Jun 05 03:53:46 PM PDT 24
Finished Jun 05 03:53:49 PM PDT 24
Peak memory 200632 kb
Host smart-ae0700b3-c881-4394-9fc7-d390859957fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181373246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1181373246
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3232936223
Short name T288
Test name
Test status
Simulation time 1607594763 ps
CPU time 5.84 seconds
Started Jun 05 03:53:47 PM PDT 24
Finished Jun 05 03:53:54 PM PDT 24
Peak memory 200996 kb
Host smart-20c955e5-9f0b-4fd2-839b-5406995a2db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232936223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3232936223
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3613257188
Short name T223
Test name
Test status
Simulation time 144900947 ps
CPU time 1.08 seconds
Started Jun 05 03:53:43 PM PDT 24
Finished Jun 05 03:53:44 PM PDT 24
Peak memory 200808 kb
Host smart-56d46d67-3d6b-4580-9a13-b78eb4db5648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613257188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3613257188
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.4071822992
Short name T208
Test name
Test status
Simulation time 192374829 ps
CPU time 1.39 seconds
Started Jun 05 03:53:44 PM PDT 24
Finished Jun 05 03:53:46 PM PDT 24
Peak memory 201036 kb
Host smart-040ce835-588a-47a4-8126-86d620974eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071822992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.4071822992
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.334802803
Short name T213
Test name
Test status
Simulation time 2707718926 ps
CPU time 9.5 seconds
Started Jun 05 03:53:47 PM PDT 24
Finished Jun 05 03:53:58 PM PDT 24
Peak memory 201108 kb
Host smart-876e0815-444a-485c-a53d-091eaacf0014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334802803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.334802803
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3596329334
Short name T134
Test name
Test status
Simulation time 135359384 ps
CPU time 1.64 seconds
Started Jun 05 03:53:46 PM PDT 24
Finished Jun 05 03:53:49 PM PDT 24
Peak memory 208964 kb
Host smart-070ed187-60b4-4648-ace9-d1a295bde9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596329334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3596329334
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3349744298
Short name T393
Test name
Test status
Simulation time 170689335 ps
CPU time 1.19 seconds
Started Jun 05 03:53:59 PM PDT 24
Finished Jun 05 03:54:00 PM PDT 24
Peak memory 200724 kb
Host smart-8202b6e5-2167-4cc8-b37d-8db9b0ae286d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349744298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3349744298
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.2024023282
Short name T165
Test name
Test status
Simulation time 71613853 ps
CPU time 0.8 seconds
Started Jun 05 03:53:52 PM PDT 24
Finished Jun 05 03:53:54 PM PDT 24
Peak memory 200644 kb
Host smart-bf4cf1c9-acb4-4e6e-ad0e-a910cf2d7b9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024023282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2024023282
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3983276912
Short name T37
Test name
Test status
Simulation time 2363220976 ps
CPU time 8.42 seconds
Started Jun 05 03:53:54 PM PDT 24
Finished Jun 05 03:54:03 PM PDT 24
Peak memory 222900 kb
Host smart-8a336af8-0cf6-46e6-9973-b1192689348a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983276912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3983276912
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.153728582
Short name T355
Test name
Test status
Simulation time 243907144 ps
CPU time 1.07 seconds
Started Jun 05 03:53:59 PM PDT 24
Finished Jun 05 03:54:00 PM PDT 24
Peak memory 217948 kb
Host smart-c173dd01-24b8-4f2c-8a3f-4501f84c4a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153728582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.153728582
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3170341496
Short name T167
Test name
Test status
Simulation time 159900556 ps
CPU time 0.91 seconds
Started Jun 05 03:53:53 PM PDT 24
Finished Jun 05 03:53:54 PM PDT 24
Peak memory 200636 kb
Host smart-a00c021a-4879-424c-8b3f-a04c87088c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170341496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3170341496
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3511369545
Short name T493
Test name
Test status
Simulation time 1976505594 ps
CPU time 7.02 seconds
Started Jun 05 03:53:55 PM PDT 24
Finished Jun 05 03:54:03 PM PDT 24
Peak memory 201004 kb
Host smart-7d5e90db-0f47-48b0-b5f5-68d3c86c6121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511369545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3511369545
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2551821980
Short name T261
Test name
Test status
Simulation time 163997357 ps
CPU time 1.17 seconds
Started Jun 05 03:53:58 PM PDT 24
Finished Jun 05 03:54:00 PM PDT 24
Peak memory 200808 kb
Host smart-822dea96-69c9-4d8c-ac37-8358d9fd311e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551821980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2551821980
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3962832351
Short name T259
Test name
Test status
Simulation time 204114902 ps
CPU time 1.39 seconds
Started Jun 05 03:53:53 PM PDT 24
Finished Jun 05 03:53:55 PM PDT 24
Peak memory 200992 kb
Host smart-3a07ba2a-4f22-48d0-98db-0a63c5d4a31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962832351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3962832351
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1018923103
Short name T335
Test name
Test status
Simulation time 4020985886 ps
CPU time 17.95 seconds
Started Jun 05 03:53:54 PM PDT 24
Finished Jun 05 03:54:12 PM PDT 24
Peak memory 210936 kb
Host smart-d1e7a08d-779d-49e9-ab37-c8cab7c846d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018923103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1018923103
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.404194542
Short name T274
Test name
Test status
Simulation time 430032900 ps
CPU time 2.29 seconds
Started Jun 05 03:53:53 PM PDT 24
Finished Jun 05 03:53:56 PM PDT 24
Peak memory 209004 kb
Host smart-9144f008-a56e-4f37-a7f7-49c93d306b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404194542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.404194542
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3828130105
Short name T535
Test name
Test status
Simulation time 286990448 ps
CPU time 1.47 seconds
Started Jun 05 03:53:50 PM PDT 24
Finished Jun 05 03:53:52 PM PDT 24
Peak memory 200728 kb
Host smart-d30eda7b-d316-49bb-b66f-09c7484aebb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828130105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3828130105
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2902426284
Short name T479
Test name
Test status
Simulation time 65157695 ps
CPU time 0.76 seconds
Started Jun 05 03:53:55 PM PDT 24
Finished Jun 05 03:53:57 PM PDT 24
Peak memory 200636 kb
Host smart-d1e7b610-3563-4a11-8209-59a99f92a9af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902426284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2902426284
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2267887555
Short name T519
Test name
Test status
Simulation time 1882421217 ps
CPU time 7.79 seconds
Started Jun 05 03:53:56 PM PDT 24
Finished Jun 05 03:54:04 PM PDT 24
Peak memory 217412 kb
Host smart-1af74275-62be-4890-af8d-01c5d4fa92f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267887555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2267887555
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2137436225
Short name T435
Test name
Test status
Simulation time 244359658 ps
CPU time 1.07 seconds
Started Jun 05 03:53:52 PM PDT 24
Finished Jun 05 03:53:54 PM PDT 24
Peak memory 218108 kb
Host smart-8ca506a7-7c88-4517-8c47-22596b1dcc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137436225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2137436225
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_reset.181810136
Short name T387
Test name
Test status
Simulation time 1863130885 ps
CPU time 6.48 seconds
Started Jun 05 03:53:52 PM PDT 24
Finished Jun 05 03:53:59 PM PDT 24
Peak memory 201024 kb
Host smart-1afc4ff0-0d90-4255-b378-a8a70a45c2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181810136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.181810136
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3492843533
Short name T271
Test name
Test status
Simulation time 112690574 ps
CPU time 1.06 seconds
Started Jun 05 03:53:55 PM PDT 24
Finished Jun 05 03:53:57 PM PDT 24
Peak memory 200740 kb
Host smart-685bc6fd-ff52-4cf7-b5f1-cc3c09bd67f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492843533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3492843533
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3911975868
Short name T359
Test name
Test status
Simulation time 108787270 ps
CPU time 1.16 seconds
Started Jun 05 03:53:54 PM PDT 24
Finished Jun 05 03:53:56 PM PDT 24
Peak memory 201256 kb
Host smart-98930091-63da-4c3e-91b5-a779e1492465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911975868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3911975868
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2514931191
Short name T512
Test name
Test status
Simulation time 3259352993 ps
CPU time 12.54 seconds
Started Jun 05 03:53:51 PM PDT 24
Finished Jun 05 03:54:04 PM PDT 24
Peak memory 209340 kb
Host smart-3e1489c7-37d7-4146-9ad5-eb9f883bfa96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514931191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2514931191
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2013786666
Short name T166
Test name
Test status
Simulation time 141081409 ps
CPU time 1.77 seconds
Started Jun 05 03:53:53 PM PDT 24
Finished Jun 05 03:53:56 PM PDT 24
Peak memory 200800 kb
Host smart-ceead616-3267-44f6-b0f0-778bc32b36aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013786666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2013786666
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.514063313
Short name T407
Test name
Test status
Simulation time 262069511 ps
CPU time 1.49 seconds
Started Jun 05 03:53:52 PM PDT 24
Finished Jun 05 03:53:55 PM PDT 24
Peak memory 200988 kb
Host smart-60336bcc-f403-4182-bacd-9e9d795e029b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514063313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.514063313
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2401897131
Short name T209
Test name
Test status
Simulation time 52774310 ps
CPU time 0.72 seconds
Started Jun 05 03:53:58 PM PDT 24
Finished Jun 05 03:53:59 PM PDT 24
Peak memory 200640 kb
Host smart-9cb2669b-4df1-4f9e-b6b3-1f59f21a0bbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401897131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2401897131
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.623203042
Short name T44
Test name
Test status
Simulation time 1221990612 ps
CPU time 5.56 seconds
Started Jun 05 03:53:53 PM PDT 24
Finished Jun 05 03:53:59 PM PDT 24
Peak memory 218420 kb
Host smart-73545356-433b-4312-af00-9608034bddd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623203042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.623203042
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2342195478
Short name T9
Test name
Test status
Simulation time 245034632 ps
CPU time 1.03 seconds
Started Jun 05 03:53:59 PM PDT 24
Finished Jun 05 03:54:00 PM PDT 24
Peak memory 217920 kb
Host smart-5cea5fe0-3d0f-4661-a439-e59ad3dcef06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342195478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2342195478
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2009022423
Short name T17
Test name
Test status
Simulation time 154320816 ps
CPU time 0.89 seconds
Started Jun 05 03:53:56 PM PDT 24
Finished Jun 05 03:53:58 PM PDT 24
Peak memory 200564 kb
Host smart-b9c17957-e840-433c-8ad5-03489bb39c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009022423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2009022423
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2463032720
Short name T474
Test name
Test status
Simulation time 986585796 ps
CPU time 4.95 seconds
Started Jun 05 03:53:53 PM PDT 24
Finished Jun 05 03:53:59 PM PDT 24
Peak memory 200996 kb
Host smart-ff03bd8e-679e-43b8-a7bf-55911c542562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463032720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2463032720
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1118717231
Short name T504
Test name
Test status
Simulation time 111022988 ps
CPU time 1.04 seconds
Started Jun 05 03:53:54 PM PDT 24
Finished Jun 05 03:53:56 PM PDT 24
Peak memory 200732 kb
Host smart-6607da2a-5f3a-4e31-8d0f-558f69822205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118717231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1118717231
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1134387297
Short name T428
Test name
Test status
Simulation time 260540755 ps
CPU time 1.51 seconds
Started Jun 05 03:53:52 PM PDT 24
Finished Jun 05 03:53:54 PM PDT 24
Peak memory 200992 kb
Host smart-2d368e95-f66b-43bf-8a11-33e5488d3900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134387297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1134387297
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1549020071
Short name T467
Test name
Test status
Simulation time 2108832330 ps
CPU time 7.43 seconds
Started Jun 05 03:53:52 PM PDT 24
Finished Jun 05 03:54:00 PM PDT 24
Peak memory 209396 kb
Host smart-cc51fc4d-08b6-4f27-abe0-6e6f22960cd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549020071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1549020071
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.741720046
Short name T422
Test name
Test status
Simulation time 123440102 ps
CPU time 1.51 seconds
Started Jun 05 03:53:52 PM PDT 24
Finished Jun 05 03:53:54 PM PDT 24
Peak memory 209060 kb
Host smart-1540a3c3-9579-42f0-9eb3-aa87a361f9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741720046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.741720046
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2872886097
Short name T427
Test name
Test status
Simulation time 150861793 ps
CPU time 1.09 seconds
Started Jun 05 03:53:55 PM PDT 24
Finished Jun 05 03:53:57 PM PDT 24
Peak memory 200784 kb
Host smart-71971d5f-ee32-4659-ad04-eb1ad7fe0d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872886097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2872886097
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2894593296
Short name T414
Test name
Test status
Simulation time 88490672 ps
CPU time 0.83 seconds
Started Jun 05 03:54:04 PM PDT 24
Finished Jun 05 03:54:06 PM PDT 24
Peak memory 200628 kb
Host smart-10813dd6-67bb-4f25-ae04-3e671ba46c7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894593296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2894593296
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3243582614
Short name T294
Test name
Test status
Simulation time 1232370564 ps
CPU time 6.17 seconds
Started Jun 05 03:54:02 PM PDT 24
Finished Jun 05 03:54:09 PM PDT 24
Peak memory 218424 kb
Host smart-30d2fcc8-eb67-4d91-9287-7c89c4dd2bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243582614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3243582614
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3036552248
Short name T523
Test name
Test status
Simulation time 245040167 ps
CPU time 1.06 seconds
Started Jun 05 03:54:01 PM PDT 24
Finished Jun 05 03:54:03 PM PDT 24
Peak memory 217944 kb
Host smart-b3e68119-2bfe-4a00-b89f-b2be2d25979b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036552248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3036552248
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3976961965
Short name T457
Test name
Test status
Simulation time 93530588 ps
CPU time 0.74 seconds
Started Jun 05 03:53:53 PM PDT 24
Finished Jun 05 03:53:55 PM PDT 24
Peak memory 200552 kb
Host smart-0ba6c94e-b942-455a-a4a6-4db60ba6011d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976961965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3976961965
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1842575789
Short name T371
Test name
Test status
Simulation time 1813791185 ps
CPU time 7.89 seconds
Started Jun 05 03:53:54 PM PDT 24
Finished Jun 05 03:54:03 PM PDT 24
Peak memory 201212 kb
Host smart-d6eadaa9-3677-4b3a-98e6-5213fd65cfff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842575789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1842575789
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.538741893
Short name T451
Test name
Test status
Simulation time 100692758 ps
CPU time 0.99 seconds
Started Jun 05 03:54:00 PM PDT 24
Finished Jun 05 03:54:02 PM PDT 24
Peak memory 200840 kb
Host smart-8ab0ac54-9b5c-462c-bd1f-ea8082d5cd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538741893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.538741893
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.121693633
Short name T327
Test name
Test status
Simulation time 231530609 ps
CPU time 1.4 seconds
Started Jun 05 03:53:55 PM PDT 24
Finished Jun 05 03:53:57 PM PDT 24
Peak memory 200944 kb
Host smart-d7b52a70-ad2d-45f3-9feb-d553e5aeb383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121693633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.121693633
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1910312929
Short name T127
Test name
Test status
Simulation time 6076034453 ps
CPU time 27.26 seconds
Started Jun 05 03:54:01 PM PDT 24
Finished Jun 05 03:54:29 PM PDT 24
Peak memory 201144 kb
Host smart-02e731d2-2a2e-4427-a7b1-ae4e77163bab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910312929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1910312929
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.254404361
Short name T30
Test name
Test status
Simulation time 130898158 ps
CPU time 1.65 seconds
Started Jun 05 03:54:06 PM PDT 24
Finished Jun 05 03:54:08 PM PDT 24
Peak memory 200848 kb
Host smart-2fbda240-292e-433d-b77d-e76a0bfe3816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254404361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.254404361
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.4283469192
Short name T146
Test name
Test status
Simulation time 140497107 ps
CPU time 1.01 seconds
Started Jun 05 03:53:50 PM PDT 24
Finished Jun 05 03:53:52 PM PDT 24
Peak memory 200824 kb
Host smart-e83d94f9-fe19-406b-80ab-b20ae63c3c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283469192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.4283469192
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1477779609
Short name T143
Test name
Test status
Simulation time 76040376 ps
CPU time 0.81 seconds
Started Jun 05 03:54:01 PM PDT 24
Finished Jun 05 03:54:03 PM PDT 24
Peak memory 200560 kb
Host smart-275a3d74-ea34-4d30-b25e-9c43b2fbbe63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477779609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1477779609
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.138819718
Short name T409
Test name
Test status
Simulation time 2357504370 ps
CPU time 7.77 seconds
Started Jun 05 03:54:03 PM PDT 24
Finished Jun 05 03:54:12 PM PDT 24
Peak memory 218248 kb
Host smart-0ee9fd67-094c-4767-999d-00b78bc19729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138819718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.138819718
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2755074140
Short name T284
Test name
Test status
Simulation time 244694740 ps
CPU time 1.05 seconds
Started Jun 05 03:54:04 PM PDT 24
Finished Jun 05 03:54:05 PM PDT 24
Peak memory 217948 kb
Host smart-e722f962-9f30-4880-996e-da771f55ddf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755074140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2755074140
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.4191761350
Short name T397
Test name
Test status
Simulation time 195029340 ps
CPU time 0.91 seconds
Started Jun 05 03:54:01 PM PDT 24
Finished Jun 05 03:54:03 PM PDT 24
Peak memory 200648 kb
Host smart-761b5439-07de-45ff-a8b8-17ca7ac44cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191761350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.4191761350
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3987033860
Short name T258
Test name
Test status
Simulation time 1671121569 ps
CPU time 6.93 seconds
Started Jun 05 03:54:02 PM PDT 24
Finished Jun 05 03:54:10 PM PDT 24
Peak memory 200992 kb
Host smart-3569eceb-2231-495c-be08-9cddd0788b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987033860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3987033860
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1181625629
Short name T138
Test name
Test status
Simulation time 105540266 ps
CPU time 1.09 seconds
Started Jun 05 03:54:06 PM PDT 24
Finished Jun 05 03:54:08 PM PDT 24
Peak memory 200816 kb
Host smart-0e6a3916-17f2-4910-9a0c-ee062b09659b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181625629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1181625629
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1926921849
Short name T147
Test name
Test status
Simulation time 116825350 ps
CPU time 1.14 seconds
Started Jun 05 03:54:03 PM PDT 24
Finished Jun 05 03:54:05 PM PDT 24
Peak memory 200984 kb
Host smart-4dc1ceb4-9b33-4b34-ac1d-9902f60b060d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926921849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1926921849
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3268010946
Short name T333
Test name
Test status
Simulation time 2408141130 ps
CPU time 8.29 seconds
Started Jun 05 03:54:01 PM PDT 24
Finished Jun 05 03:54:10 PM PDT 24
Peak memory 201140 kb
Host smart-a5c4fd4b-25f2-4e2e-aa85-c4be633e6400
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268010946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3268010946
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1337781906
Short name T507
Test name
Test status
Simulation time 452070156 ps
CPU time 2.37 seconds
Started Jun 05 03:54:05 PM PDT 24
Finished Jun 05 03:54:08 PM PDT 24
Peak memory 200804 kb
Host smart-6bbef677-b63e-4b3b-ad8e-403ed687ebfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337781906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1337781906
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.4145904697
Short name T250
Test name
Test status
Simulation time 99871790 ps
CPU time 0.87 seconds
Started Jun 05 03:54:01 PM PDT 24
Finished Jun 05 03:54:02 PM PDT 24
Peak memory 200812 kb
Host smart-d9f1fca2-0b60-4ab9-9f0a-912d8f5e78b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145904697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.4145904697
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.3525639941
Short name T400
Test name
Test status
Simulation time 60120296 ps
CPU time 0.82 seconds
Started Jun 05 03:54:02 PM PDT 24
Finished Jun 05 03:54:04 PM PDT 24
Peak memory 200572 kb
Host smart-db1d1e11-bd02-4a54-be69-f07f13cf522d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525639941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3525639941
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2888766078
Short name T14
Test name
Test status
Simulation time 1225045234 ps
CPU time 5.22 seconds
Started Jun 05 03:54:05 PM PDT 24
Finished Jun 05 03:54:11 PM PDT 24
Peak memory 230180 kb
Host smart-f21193f4-c769-4b5c-8f42-51e2fa9d478c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888766078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2888766078
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1215166191
Short name T341
Test name
Test status
Simulation time 243917732 ps
CPU time 1.11 seconds
Started Jun 05 03:54:05 PM PDT 24
Finished Jun 05 03:54:07 PM PDT 24
Peak memory 218028 kb
Host smart-2acf44bf-d2cc-40ce-aea2-070cb4856f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215166191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1215166191
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2943134174
Short name T178
Test name
Test status
Simulation time 174901861 ps
CPU time 0.9 seconds
Started Jun 05 03:54:02 PM PDT 24
Finished Jun 05 03:54:04 PM PDT 24
Peak memory 200560 kb
Host smart-d4030bc5-7304-4a65-bccd-e0b488b2e787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943134174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2943134174
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2737508485
Short name T473
Test name
Test status
Simulation time 976237047 ps
CPU time 5.22 seconds
Started Jun 05 03:54:02 PM PDT 24
Finished Jun 05 03:54:08 PM PDT 24
Peak memory 201000 kb
Host smart-17604ec4-60c5-4c08-9396-452f73bce79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737508485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2737508485
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.4243247119
Short name T132
Test name
Test status
Simulation time 180498384 ps
CPU time 1.17 seconds
Started Jun 05 03:54:03 PM PDT 24
Finished Jun 05 03:54:05 PM PDT 24
Peak memory 200832 kb
Host smart-e0daac71-8e65-42f3-b89b-80adfce30582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243247119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.4243247119
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.1168964885
Short name T417
Test name
Test status
Simulation time 247618904 ps
CPU time 1.51 seconds
Started Jun 05 03:54:04 PM PDT 24
Finished Jun 05 03:54:07 PM PDT 24
Peak memory 200924 kb
Host smart-95a2a593-32c8-43e1-b1da-c5b0ad780464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168964885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1168964885
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2290812634
Short name T234
Test name
Test status
Simulation time 2236002129 ps
CPU time 9.45 seconds
Started Jun 05 03:54:00 PM PDT 24
Finished Jun 05 03:54:11 PM PDT 24
Peak memory 201084 kb
Host smart-955f17c3-5f52-41fd-a108-6b15122a3e92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290812634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2290812634
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1056325615
Short name T314
Test name
Test status
Simulation time 122074608 ps
CPU time 1.52 seconds
Started Jun 05 03:54:03 PM PDT 24
Finished Jun 05 03:54:06 PM PDT 24
Peak memory 200792 kb
Host smart-75c2d301-12fd-46e6-92c0-90ee9fb28441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056325615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1056325615
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.4119875874
Short name T199
Test name
Test status
Simulation time 63748924 ps
CPU time 0.73 seconds
Started Jun 05 03:54:00 PM PDT 24
Finished Jun 05 03:54:02 PM PDT 24
Peak memory 200796 kb
Host smart-7d8f0a2e-5f6b-4b37-834c-021a7ebd77dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119875874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.4119875874
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.848839995
Short name T437
Test name
Test status
Simulation time 91868412 ps
CPU time 0.78 seconds
Started Jun 05 03:53:05 PM PDT 24
Finished Jun 05 03:53:06 PM PDT 24
Peak memory 200828 kb
Host smart-82672231-c809-4413-87f1-f9896376e627
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848839995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.848839995
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2817174750
Short name T52
Test name
Test status
Simulation time 2356924063 ps
CPU time 8.37 seconds
Started Jun 05 03:53:02 PM PDT 24
Finished Jun 05 03:53:12 PM PDT 24
Peak memory 217900 kb
Host smart-bd029ff2-13b3-4b35-b45f-e7368609b67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817174750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2817174750
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.47645715
Short name T8
Test name
Test status
Simulation time 243951858 ps
CPU time 1.15 seconds
Started Jun 05 03:53:05 PM PDT 24
Finished Jun 05 03:53:07 PM PDT 24
Peak memory 218188 kb
Host smart-71288e2c-f27a-4ca3-880c-622e6ac39d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47645715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.47645715
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.756980040
Short name T469
Test name
Test status
Simulation time 224905094 ps
CPU time 0.9 seconds
Started Jun 05 03:53:04 PM PDT 24
Finished Jun 05 03:53:06 PM PDT 24
Peak memory 200524 kb
Host smart-d9cb7708-f5fa-4b61-b3e4-774a3a49869f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756980040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.756980040
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2737752442
Short name T119
Test name
Test status
Simulation time 884663311 ps
CPU time 4.49 seconds
Started Jun 05 03:53:06 PM PDT 24
Finished Jun 05 03:53:11 PM PDT 24
Peak memory 200980 kb
Host smart-3c677e0f-31af-4993-924e-e8c7e62b68a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737752442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2737752442
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.147541865
Short name T64
Test name
Test status
Simulation time 16588160487 ps
CPU time 24.97 seconds
Started Jun 05 03:53:05 PM PDT 24
Finished Jun 05 03:53:31 PM PDT 24
Peak memory 217552 kb
Host smart-34feca0d-6d60-42e2-a3a8-45be07088b6a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147541865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.147541865
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3835048519
Short name T468
Test name
Test status
Simulation time 152078069 ps
CPU time 1.18 seconds
Started Jun 05 03:53:05 PM PDT 24
Finished Jun 05 03:53:07 PM PDT 24
Peak memory 200736 kb
Host smart-6db793c0-55cd-49b8-92e7-b580e5842d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835048519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3835048519
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3535141688
Short name T161
Test name
Test status
Simulation time 198949626 ps
CPU time 1.33 seconds
Started Jun 05 03:53:07 PM PDT 24
Finished Jun 05 03:53:09 PM PDT 24
Peak memory 200900 kb
Host smart-4c54beed-755a-4bd7-990a-712f8c80c72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535141688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3535141688
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.3260540496
Short name T381
Test name
Test status
Simulation time 4873359867 ps
CPU time 16.15 seconds
Started Jun 05 03:53:06 PM PDT 24
Finished Jun 05 03:53:24 PM PDT 24
Peak memory 201040 kb
Host smart-24990ded-64c0-4efe-9bf2-6365211ef379
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260540496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3260540496
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1364964244
Short name T481
Test name
Test status
Simulation time 378041076 ps
CPU time 2.35 seconds
Started Jun 05 03:53:09 PM PDT 24
Finished Jun 05 03:53:12 PM PDT 24
Peak memory 200800 kb
Host smart-b7ab7876-fce5-4759-a66c-c3fedbbd8d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364964244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1364964244
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2089070623
Short name T152
Test name
Test status
Simulation time 122488152 ps
CPU time 1.05 seconds
Started Jun 05 03:53:06 PM PDT 24
Finished Jun 05 03:53:09 PM PDT 24
Peak memory 200744 kb
Host smart-55cbcf7c-21c6-49a2-ae09-15d318badf4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089070623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2089070623
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1880883880
Short name T430
Test name
Test status
Simulation time 78242168 ps
CPU time 0.78 seconds
Started Jun 05 03:54:13 PM PDT 24
Finished Jun 05 03:54:15 PM PDT 24
Peak memory 200636 kb
Host smart-7ac6cd90-b359-4b84-b867-09f7d2cff291
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880883880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1880883880
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2802475110
Short name T513
Test name
Test status
Simulation time 1230707517 ps
CPU time 5.6 seconds
Started Jun 05 03:54:14 PM PDT 24
Finished Jun 05 03:54:21 PM PDT 24
Peak memory 218392 kb
Host smart-94f2981e-a6aa-464d-b902-39b8fc3201c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802475110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2802475110
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3133405950
Short name T238
Test name
Test status
Simulation time 245540250 ps
CPU time 1.02 seconds
Started Jun 05 03:54:17 PM PDT 24
Finished Jun 05 03:54:18 PM PDT 24
Peak memory 217888 kb
Host smart-50034725-8322-4e1e-9819-9795bb1b7e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133405950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3133405950
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3829125408
Short name T410
Test name
Test status
Simulation time 152862243 ps
CPU time 0.83 seconds
Started Jun 05 03:54:04 PM PDT 24
Finished Jun 05 03:54:06 PM PDT 24
Peak memory 200608 kb
Host smart-a23e579c-cce6-4ac4-8cd3-7b100b8e719b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829125408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3829125408
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3114480697
Short name T354
Test name
Test status
Simulation time 902123112 ps
CPU time 4.43 seconds
Started Jun 05 03:54:02 PM PDT 24
Finished Jun 05 03:54:08 PM PDT 24
Peak memory 201240 kb
Host smart-629ffe6a-0b32-4229-aab0-28467b3ede56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114480697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3114480697
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2431527611
Short name T418
Test name
Test status
Simulation time 103118678 ps
CPU time 0.97 seconds
Started Jun 05 03:54:14 PM PDT 24
Finished Jun 05 03:54:16 PM PDT 24
Peak memory 200732 kb
Host smart-e88a78fc-220a-43e2-ad7c-a4bde5361490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431527611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2431527611
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3952435895
Short name T273
Test name
Test status
Simulation time 255369871 ps
CPU time 1.45 seconds
Started Jun 05 03:54:04 PM PDT 24
Finished Jun 05 03:54:06 PM PDT 24
Peak memory 200916 kb
Host smart-3df09d3b-9531-43af-83da-2713dfa0468a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952435895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3952435895
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3384106267
Short name T137
Test name
Test status
Simulation time 196655239 ps
CPU time 1.33 seconds
Started Jun 05 03:54:16 PM PDT 24
Finished Jun 05 03:54:18 PM PDT 24
Peak memory 201024 kb
Host smart-38922382-1e76-444e-af6e-6aefbdb335ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384106267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3384106267
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.990684616
Short name T292
Test name
Test status
Simulation time 134195784 ps
CPU time 1.71 seconds
Started Jun 05 03:54:14 PM PDT 24
Finished Jun 05 03:54:17 PM PDT 24
Peak memory 208984 kb
Host smart-e06a6a26-4974-44ab-aac1-bf1a6701f541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990684616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.990684616
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1260982907
Short name T458
Test name
Test status
Simulation time 93568089 ps
CPU time 0.9 seconds
Started Jun 05 03:54:16 PM PDT 24
Finished Jun 05 03:54:18 PM PDT 24
Peak memory 200732 kb
Host smart-172e2deb-ce0a-406e-a877-858942c09cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260982907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1260982907
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2336358987
Short name T399
Test name
Test status
Simulation time 79831433 ps
CPU time 0.77 seconds
Started Jun 05 03:54:14 PM PDT 24
Finished Jun 05 03:54:16 PM PDT 24
Peak memory 200532 kb
Host smart-aa400db4-7030-401b-93c8-aee727d081ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336358987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2336358987
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2713011196
Short name T480
Test name
Test status
Simulation time 2363882668 ps
CPU time 9.06 seconds
Started Jun 05 03:54:13 PM PDT 24
Finished Jun 05 03:54:22 PM PDT 24
Peak memory 222608 kb
Host smart-cc25549d-7620-44f4-94e7-e564a236a403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713011196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2713011196
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.871920355
Short name T120
Test name
Test status
Simulation time 244084374 ps
CPU time 1.09 seconds
Started Jun 05 03:54:15 PM PDT 24
Finished Jun 05 03:54:17 PM PDT 24
Peak memory 218108 kb
Host smart-b38d37b3-4a96-4ae7-ba4f-2d8c2fb2e6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871920355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.871920355
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1797154428
Short name T353
Test name
Test status
Simulation time 135858130 ps
CPU time 0.8 seconds
Started Jun 05 03:54:13 PM PDT 24
Finished Jun 05 03:54:15 PM PDT 24
Peak memory 200632 kb
Host smart-b1591ec3-4477-48c0-92a9-cc797c8aca43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797154428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1797154428
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.1247059635
Short name T290
Test name
Test status
Simulation time 1004285395 ps
CPU time 4.92 seconds
Started Jun 05 03:54:14 PM PDT 24
Finished Jun 05 03:54:20 PM PDT 24
Peak memory 201256 kb
Host smart-23e1d392-d430-4eb7-9300-210a0fbc8cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247059635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.1247059635
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1753252323
Short name T155
Test name
Test status
Simulation time 114123611 ps
CPU time 1.13 seconds
Started Jun 05 03:54:15 PM PDT 24
Finished Jun 05 03:54:17 PM PDT 24
Peak memory 200960 kb
Host smart-9cc94fb7-6a13-448e-9443-4a21eb2f0998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753252323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1753252323
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2136995586
Short name T260
Test name
Test status
Simulation time 5293744859 ps
CPU time 25.73 seconds
Started Jun 05 03:54:14 PM PDT 24
Finished Jun 05 03:54:41 PM PDT 24
Peak memory 201380 kb
Host smart-5f85766e-778c-4f26-8486-0bd23960db95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136995586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2136995586
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.757118311
Short name T297
Test name
Test status
Simulation time 128490009 ps
CPU time 1.59 seconds
Started Jun 05 03:54:15 PM PDT 24
Finished Jun 05 03:54:18 PM PDT 24
Peak memory 209000 kb
Host smart-2a5bcb5e-a365-40a6-a9a4-7e09cae2d2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757118311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.757118311
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2141042468
Short name T247
Test name
Test status
Simulation time 150659437 ps
CPU time 1.09 seconds
Started Jun 05 03:54:13 PM PDT 24
Finished Jun 05 03:54:16 PM PDT 24
Peak memory 200736 kb
Host smart-242e9bb6-8c07-4a63-86ed-50815dbe7403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141042468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2141042468
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3947554451
Short name T237
Test name
Test status
Simulation time 69439614 ps
CPU time 0.75 seconds
Started Jun 05 03:54:13 PM PDT 24
Finished Jun 05 03:54:14 PM PDT 24
Peak memory 200644 kb
Host smart-be825524-e03d-4387-bacc-bcc0b8e75cbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947554451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3947554451
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1677426454
Short name T540
Test name
Test status
Simulation time 2368140869 ps
CPU time 8.92 seconds
Started Jun 05 03:54:14 PM PDT 24
Finished Jun 05 03:54:25 PM PDT 24
Peak memory 218516 kb
Host smart-cb828eaf-fc62-4867-8489-1571ac529f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677426454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1677426454
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2123486206
Short name T47
Test name
Test status
Simulation time 244414351 ps
CPU time 1.03 seconds
Started Jun 05 03:54:15 PM PDT 24
Finished Jun 05 03:54:17 PM PDT 24
Peak memory 217948 kb
Host smart-9e81a5c2-9225-418c-8926-b30583e07b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123486206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2123486206
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.1006417569
Short name T448
Test name
Test status
Simulation time 114567888 ps
CPU time 0.83 seconds
Started Jun 05 03:54:16 PM PDT 24
Finished Jun 05 03:54:17 PM PDT 24
Peak memory 200564 kb
Host smart-2ee44b82-182f-4b92-87a9-cb53a7b43c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006417569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1006417569
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3385317996
Short name T110
Test name
Test status
Simulation time 1448547003 ps
CPU time 5.8 seconds
Started Jun 05 03:54:13 PM PDT 24
Finished Jun 05 03:54:19 PM PDT 24
Peak memory 200864 kb
Host smart-8ccff3de-9938-4092-8993-07c80f613464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385317996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3385317996
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3222744612
Short name T278
Test name
Test status
Simulation time 175906688 ps
CPU time 1.13 seconds
Started Jun 05 03:54:13 PM PDT 24
Finished Jun 05 03:54:15 PM PDT 24
Peak memory 200816 kb
Host smart-00ca1bb3-5f81-4df6-8449-21c0d36e5af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222744612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3222744612
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.598965510
Short name T232
Test name
Test status
Simulation time 203198589 ps
CPU time 1.37 seconds
Started Jun 05 03:54:16 PM PDT 24
Finished Jun 05 03:54:18 PM PDT 24
Peak memory 200996 kb
Host smart-b07f7ce0-3efa-4977-a39d-b94fa45a7a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598965510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.598965510
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.235582557
Short name T332
Test name
Test status
Simulation time 1589961748 ps
CPU time 6.11 seconds
Started Jun 05 03:54:14 PM PDT 24
Finished Jun 05 03:54:21 PM PDT 24
Peak memory 200984 kb
Host smart-0f0f278a-d356-470a-b93b-f6f3b1f0b9f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235582557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.235582557
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2705256500
Short name T432
Test name
Test status
Simulation time 146244833 ps
CPU time 1.89 seconds
Started Jun 05 03:54:14 PM PDT 24
Finished Jun 05 03:54:17 PM PDT 24
Peak memory 200772 kb
Host smart-f67755ef-0fc3-4c01-b32b-d3839c94bd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705256500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2705256500
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1386244131
Short name T141
Test name
Test status
Simulation time 61358051 ps
CPU time 0.79 seconds
Started Jun 05 03:54:14 PM PDT 24
Finished Jun 05 03:54:16 PM PDT 24
Peak memory 200812 kb
Host smart-779b62d6-703b-4af8-a627-356c0eab5ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386244131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1386244131
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.405254695
Short name T522
Test name
Test status
Simulation time 72328917 ps
CPU time 0.85 seconds
Started Jun 05 03:54:24 PM PDT 24
Finished Jun 05 03:54:26 PM PDT 24
Peak memory 200644 kb
Host smart-b5ad5ee3-20a7-49e0-807d-fc39fbec88ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405254695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.405254695
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.359497090
Short name T226
Test name
Test status
Simulation time 1903055448 ps
CPU time 7.16 seconds
Started Jun 05 03:54:25 PM PDT 24
Finished Jun 05 03:54:33 PM PDT 24
Peak memory 218376 kb
Host smart-638d4114-2495-4226-af9f-3f6772e8e483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359497090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.359497090
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.651558888
Short name T231
Test name
Test status
Simulation time 244118131 ps
CPU time 1.04 seconds
Started Jun 05 03:54:27 PM PDT 24
Finished Jun 05 03:54:29 PM PDT 24
Peak memory 217844 kb
Host smart-24bad9ab-7791-4476-b01f-8b8c4df5013a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651558888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.651558888
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.4229952259
Short name T244
Test name
Test status
Simulation time 84745425 ps
CPU time 0.81 seconds
Started Jun 05 03:54:29 PM PDT 24
Finished Jun 05 03:54:30 PM PDT 24
Peak memory 200620 kb
Host smart-a6743467-c963-4f23-867c-6b6b89d746ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229952259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.4229952259
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.4261453539
Short name T404
Test name
Test status
Simulation time 1586456267 ps
CPU time 5.74 seconds
Started Jun 05 03:54:14 PM PDT 24
Finished Jun 05 03:54:21 PM PDT 24
Peak memory 201004 kb
Host smart-5652e1cc-121b-4615-8e85-c5de0b14287a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261453539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.4261453539
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2259944398
Short name T363
Test name
Test status
Simulation time 157650542 ps
CPU time 1.13 seconds
Started Jun 05 03:54:25 PM PDT 24
Finished Jun 05 03:54:27 PM PDT 24
Peak memory 200812 kb
Host smart-4ca897e7-192b-4398-a3ca-d774a6df80b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259944398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2259944398
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.3373737696
Short name T285
Test name
Test status
Simulation time 120580636 ps
CPU time 1.2 seconds
Started Jun 05 03:54:17 PM PDT 24
Finished Jun 05 03:54:19 PM PDT 24
Peak memory 200964 kb
Host smart-20b78808-f0ab-48ec-8a67-8de977e0d8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373737696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3373737696
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2860846834
Short name T272
Test name
Test status
Simulation time 2931686727 ps
CPU time 11.35 seconds
Started Jun 05 03:54:24 PM PDT 24
Finished Jun 05 03:54:36 PM PDT 24
Peak memory 201140 kb
Host smart-29b97e6e-cd30-4d88-8f45-2ca2bd5074c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860846834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2860846834
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1860179458
Short name T434
Test name
Test status
Simulation time 124915401 ps
CPU time 1.62 seconds
Started Jun 05 03:54:13 PM PDT 24
Finished Jun 05 03:54:16 PM PDT 24
Peak memory 208936 kb
Host smart-ceca7bc7-e0b9-4a82-b01a-852cb0fe95fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860179458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1860179458
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.4264790196
Short name T203
Test name
Test status
Simulation time 174332917 ps
CPU time 1.34 seconds
Started Jun 05 03:54:16 PM PDT 24
Finished Jun 05 03:54:18 PM PDT 24
Peak memory 201032 kb
Host smart-31e3d999-fddc-4492-b62a-c5d4bc498c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264790196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.4264790196
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.496816272
Short name T350
Test name
Test status
Simulation time 62665876 ps
CPU time 0.76 seconds
Started Jun 05 03:54:26 PM PDT 24
Finished Jun 05 03:54:28 PM PDT 24
Peak memory 200656 kb
Host smart-1e792fa7-28c0-4416-a165-4f84b760ac8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496816272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.496816272
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.961094393
Short name T33
Test name
Test status
Simulation time 2169372159 ps
CPU time 8.27 seconds
Started Jun 05 03:54:22 PM PDT 24
Finished Jun 05 03:54:31 PM PDT 24
Peak memory 218544 kb
Host smart-e77c9f95-08c1-4b85-b99b-105fedac2fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961094393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.961094393
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3990461360
Short name T277
Test name
Test status
Simulation time 245286288 ps
CPU time 1.05 seconds
Started Jun 05 03:54:27 PM PDT 24
Finished Jun 05 03:54:29 PM PDT 24
Peak memory 217864 kb
Host smart-1a0baa51-a4d8-4065-9c95-10d8f8707c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990461360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3990461360
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3506156822
Short name T158
Test name
Test status
Simulation time 109564159 ps
CPU time 0.77 seconds
Started Jun 05 03:54:27 PM PDT 24
Finished Jun 05 03:54:29 PM PDT 24
Peak memory 200652 kb
Host smart-d6294e8b-ee9d-4053-8a5a-1afd035877b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506156822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3506156822
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2143359101
Short name T302
Test name
Test status
Simulation time 1501284850 ps
CPU time 6.18 seconds
Started Jun 05 03:54:27 PM PDT 24
Finished Jun 05 03:54:35 PM PDT 24
Peak memory 200976 kb
Host smart-f66ed036-f79d-4bd3-980b-dddb9bfa82d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143359101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2143359101
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.512989529
Short name T357
Test name
Test status
Simulation time 163315359 ps
CPU time 1.21 seconds
Started Jun 05 03:54:23 PM PDT 24
Finished Jun 05 03:54:25 PM PDT 24
Peak memory 200724 kb
Host smart-191dcf77-d38b-420a-9bd7-d83f4ff82ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512989529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.512989529
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.459769327
Short name T424
Test name
Test status
Simulation time 190247065 ps
CPU time 1.3 seconds
Started Jun 05 03:54:24 PM PDT 24
Finished Jun 05 03:54:26 PM PDT 24
Peak memory 200908 kb
Host smart-94fc1d0b-fd0c-40fe-a70a-71d406a0092f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459769327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.459769327
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.470726196
Short name T90
Test name
Test status
Simulation time 8916474912 ps
CPU time 35.26 seconds
Started Jun 05 03:54:27 PM PDT 24
Finished Jun 05 03:55:03 PM PDT 24
Peak memory 209252 kb
Host smart-755246f2-d2f2-4936-a035-dc4599cb6c31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470726196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.470726196
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.3632986408
Short name T129
Test name
Test status
Simulation time 384370679 ps
CPU time 2.45 seconds
Started Jun 05 03:54:23 PM PDT 24
Finished Jun 05 03:54:26 PM PDT 24
Peak memory 201036 kb
Host smart-d6d39834-a022-4332-ad1e-829318441ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632986408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.3632986408
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1286140759
Short name T328
Test name
Test status
Simulation time 127704872 ps
CPU time 1.06 seconds
Started Jun 05 03:54:29 PM PDT 24
Finished Jun 05 03:54:31 PM PDT 24
Peak memory 200812 kb
Host smart-2f990c71-183a-430f-b442-ddf98ebd3672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286140759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1286140759
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2752909203
Short name T225
Test name
Test status
Simulation time 63526684 ps
CPU time 0.72 seconds
Started Jun 05 03:54:21 PM PDT 24
Finished Jun 05 03:54:22 PM PDT 24
Peak memory 200652 kb
Host smart-f422cade-2a9c-4fc2-bf41-a446081d7e54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752909203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2752909203
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1303487443
Short name T531
Test name
Test status
Simulation time 2340086914 ps
CPU time 8.68 seconds
Started Jun 05 03:54:27 PM PDT 24
Finished Jun 05 03:54:36 PM PDT 24
Peak memory 222584 kb
Host smart-c94c8622-46dd-43e2-a3c3-049987dd9015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303487443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1303487443
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3500776121
Short name T144
Test name
Test status
Simulation time 243776462 ps
CPU time 1.13 seconds
Started Jun 05 03:54:28 PM PDT 24
Finished Jun 05 03:54:30 PM PDT 24
Peak memory 217968 kb
Host smart-f1b7d496-0bc0-4041-9844-5c267ecef5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500776121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3500776121
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.227915667
Short name T21
Test name
Test status
Simulation time 212496098 ps
CPU time 0.95 seconds
Started Jun 05 03:54:26 PM PDT 24
Finished Jun 05 03:54:28 PM PDT 24
Peak memory 200636 kb
Host smart-8f9ffdf8-2879-469b-a598-7248524ccb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227915667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.227915667
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.3998913624
Short name T177
Test name
Test status
Simulation time 770160137 ps
CPU time 4.07 seconds
Started Jun 05 03:54:27 PM PDT 24
Finished Jun 05 03:54:32 PM PDT 24
Peak memory 200976 kb
Host smart-0195ab6c-53df-4770-9f4e-d084de4913e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998913624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3998913624
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1321531733
Short name T181
Test name
Test status
Simulation time 114540074 ps
CPU time 0.96 seconds
Started Jun 05 03:54:21 PM PDT 24
Finished Jun 05 03:54:23 PM PDT 24
Peak memory 200736 kb
Host smart-56a76ffb-7fc2-4f24-85eb-eedea9731942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321531733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1321531733
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3267051316
Short name T403
Test name
Test status
Simulation time 226666492 ps
CPU time 1.44 seconds
Started Jun 05 03:54:27 PM PDT 24
Finished Jun 05 03:54:29 PM PDT 24
Peak memory 200976 kb
Host smart-4da64b7b-e54b-4894-931a-857f4cdcc54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267051316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3267051316
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2203173098
Short name T204
Test name
Test status
Simulation time 1741329243 ps
CPU time 6.8 seconds
Started Jun 05 03:54:27 PM PDT 24
Finished Jun 05 03:54:35 PM PDT 24
Peak memory 201056 kb
Host smart-60429dd9-505d-45af-a32f-91e577882a9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203173098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2203173098
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3962030158
Short name T334
Test name
Test status
Simulation time 265078838 ps
CPU time 1.79 seconds
Started Jun 05 03:54:26 PM PDT 24
Finished Jun 05 03:54:29 PM PDT 24
Peak memory 200712 kb
Host smart-2f27c668-0782-446a-b6ec-fe285f777f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962030158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3962030158
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3199535016
Short name T411
Test name
Test status
Simulation time 227814512 ps
CPU time 1.36 seconds
Started Jun 05 03:54:26 PM PDT 24
Finished Jun 05 03:54:28 PM PDT 24
Peak memory 200776 kb
Host smart-eacee6de-dc38-461f-b26d-cb1b8513f822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199535016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3199535016
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1926842085
Short name T311
Test name
Test status
Simulation time 78194820 ps
CPU time 0.84 seconds
Started Jun 05 03:54:28 PM PDT 24
Finished Jun 05 03:54:30 PM PDT 24
Peak memory 200668 kb
Host smart-a4c3918c-9d58-4045-b10a-110446674861
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926842085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1926842085
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.358228601
Short name T42
Test name
Test status
Simulation time 1229408662 ps
CPU time 5.52 seconds
Started Jun 05 03:54:29 PM PDT 24
Finished Jun 05 03:54:35 PM PDT 24
Peak memory 221468 kb
Host smart-5a8295bb-6127-4e61-906c-e00dfad7ff39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358228601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.358228601
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3780499763
Short name T315
Test name
Test status
Simulation time 243989016 ps
CPU time 1.1 seconds
Started Jun 05 03:54:23 PM PDT 24
Finished Jun 05 03:54:25 PM PDT 24
Peak memory 218172 kb
Host smart-e8fa30a8-921e-49a7-85a8-1c92cc3583ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780499763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3780499763
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2799135943
Short name T228
Test name
Test status
Simulation time 143783170 ps
CPU time 0.81 seconds
Started Jun 05 03:54:28 PM PDT 24
Finished Jun 05 03:54:30 PM PDT 24
Peak memory 200648 kb
Host smart-b1d197e3-9fef-4e9b-8d95-caa631f57a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799135943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2799135943
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3819234217
Short name T34
Test name
Test status
Simulation time 823162151 ps
CPU time 4.12 seconds
Started Jun 05 03:54:29 PM PDT 24
Finished Jun 05 03:54:34 PM PDT 24
Peak memory 201048 kb
Host smart-8ef96e39-0b75-407d-ac2f-6e254a0da02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819234217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3819234217
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1233479703
Short name T313
Test name
Test status
Simulation time 177357203 ps
CPU time 1.2 seconds
Started Jun 05 03:54:24 PM PDT 24
Finished Jun 05 03:54:26 PM PDT 24
Peak memory 200812 kb
Host smart-64ac850a-616b-4c1a-9799-b22fe8d0d8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233479703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1233479703
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1103889687
Short name T246
Test name
Test status
Simulation time 202235388 ps
CPU time 1.67 seconds
Started Jun 05 03:54:23 PM PDT 24
Finished Jun 05 03:54:25 PM PDT 24
Peak memory 201036 kb
Host smart-b0473ea6-9fb9-4d77-9b40-8b462ead4cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103889687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1103889687
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.1438150056
Short name T86
Test name
Test status
Simulation time 1750713056 ps
CPU time 6.51 seconds
Started Jun 05 03:54:26 PM PDT 24
Finished Jun 05 03:54:33 PM PDT 24
Peak memory 201008 kb
Host smart-4ee9f801-3e01-43f5-8511-e78b69e181eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438150056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1438150056
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.539170290
Short name T74
Test name
Test status
Simulation time 154189402 ps
CPU time 1.93 seconds
Started Jun 05 03:54:28 PM PDT 24
Finished Jun 05 03:54:31 PM PDT 24
Peak memory 200808 kb
Host smart-5b0634c3-c5ba-46a2-bd50-1ecf5a6f7667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539170290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.539170290
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3871447754
Short name T276
Test name
Test status
Simulation time 98523498 ps
CPU time 0.94 seconds
Started Jun 05 03:54:29 PM PDT 24
Finished Jun 05 03:54:31 PM PDT 24
Peak memory 200808 kb
Host smart-477ee181-2dfc-4ec1-93df-1a8787480ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871447754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3871447754
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.269010399
Short name T306
Test name
Test status
Simulation time 88747905 ps
CPU time 0.8 seconds
Started Jun 05 03:54:25 PM PDT 24
Finished Jun 05 03:54:27 PM PDT 24
Peak memory 200652 kb
Host smart-06ea5448-6a23-4136-b0e2-abd23c5bca8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269010399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.269010399
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1427958428
Short name T39
Test name
Test status
Simulation time 1874339747 ps
CPU time 6.75 seconds
Started Jun 05 03:54:27 PM PDT 24
Finished Jun 05 03:54:35 PM PDT 24
Peak memory 222416 kb
Host smart-16475a14-4b47-41b4-b14d-571888c92498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427958428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1427958428
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1555337209
Short name T296
Test name
Test status
Simulation time 244912852 ps
CPU time 1.07 seconds
Started Jun 05 03:54:26 PM PDT 24
Finished Jun 05 03:54:28 PM PDT 24
Peak memory 218108 kb
Host smart-55a8f133-010c-4d23-9383-7ba3e982a46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555337209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1555337209
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.3525128204
Short name T348
Test name
Test status
Simulation time 111696860 ps
CPU time 0.79 seconds
Started Jun 05 03:54:26 PM PDT 24
Finished Jun 05 03:54:28 PM PDT 24
Peak memory 200620 kb
Host smart-96cf5e24-193c-4b55-9979-7dde529fca17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525128204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3525128204
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.3730142835
Short name T323
Test name
Test status
Simulation time 1582295576 ps
CPU time 5.93 seconds
Started Jun 05 03:54:26 PM PDT 24
Finished Jun 05 03:54:33 PM PDT 24
Peak memory 200916 kb
Host smart-1219cf73-016f-44ae-b4e8-10ddbf9697b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730142835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.3730142835
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.123856419
Short name T521
Test name
Test status
Simulation time 111745895 ps
CPU time 1.04 seconds
Started Jun 05 03:54:27 PM PDT 24
Finished Jun 05 03:54:29 PM PDT 24
Peak memory 200840 kb
Host smart-423a59e5-c638-49d0-91a4-e8ae1d650d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123856419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.123856419
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.1273884573
Short name T309
Test name
Test status
Simulation time 233609173 ps
CPU time 1.68 seconds
Started Jun 05 03:54:29 PM PDT 24
Finished Jun 05 03:54:31 PM PDT 24
Peak memory 201016 kb
Host smart-046964cc-aae0-493c-b7c6-eb886d6f9587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273884573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1273884573
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.614624057
Short name T254
Test name
Test status
Simulation time 7196207116 ps
CPU time 31.64 seconds
Started Jun 05 03:54:25 PM PDT 24
Finished Jun 05 03:54:57 PM PDT 24
Peak memory 210968 kb
Host smart-3e8611dc-33dd-45fc-ab7e-24ae0045c3f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614624057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.614624057
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.242712069
Short name T269
Test name
Test status
Simulation time 442446518 ps
CPU time 2.39 seconds
Started Jun 05 03:54:26 PM PDT 24
Finished Jun 05 03:54:29 PM PDT 24
Peak memory 200712 kb
Host smart-f57ae5b9-523d-4a66-8a09-0bf4afdb757b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242712069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.242712069
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3660159027
Short name T116
Test name
Test status
Simulation time 68615224 ps
CPU time 0.76 seconds
Started Jun 05 03:54:23 PM PDT 24
Finished Jun 05 03:54:25 PM PDT 24
Peak memory 200808 kb
Host smart-164869dc-4417-4bcf-823c-ea8467016282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660159027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3660159027
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.4263079657
Short name T351
Test name
Test status
Simulation time 78249146 ps
CPU time 0.8 seconds
Started Jun 05 03:54:34 PM PDT 24
Finished Jun 05 03:54:36 PM PDT 24
Peak memory 200516 kb
Host smart-eac8dd5e-f46c-41ed-849f-d832dc073e5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263079657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.4263079657
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.715448154
Short name T35
Test name
Test status
Simulation time 1881624672 ps
CPU time 7.2 seconds
Started Jun 05 03:54:33 PM PDT 24
Finished Jun 05 03:54:41 PM PDT 24
Peak memory 218444 kb
Host smart-39d7c6c9-4af6-4f3d-a7b2-6bd115ccbfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715448154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.715448154
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1587004852
Short name T162
Test name
Test status
Simulation time 244778504 ps
CPU time 1.07 seconds
Started Jun 05 03:54:32 PM PDT 24
Finished Jun 05 03:54:34 PM PDT 24
Peak memory 217888 kb
Host smart-1909f53a-edec-4396-9e73-e192268d1499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587004852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1587004852
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.4131269244
Short name T415
Test name
Test status
Simulation time 109828463 ps
CPU time 0.82 seconds
Started Jun 05 03:54:27 PM PDT 24
Finished Jun 05 03:54:29 PM PDT 24
Peak memory 200632 kb
Host smart-00d7edf4-5c9c-4ff3-9ca7-3b35a1a038d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131269244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.4131269244
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.4283059773
Short name T182
Test name
Test status
Simulation time 1719714538 ps
CPU time 6.14 seconds
Started Jun 05 03:54:34 PM PDT 24
Finished Jun 05 03:54:42 PM PDT 24
Peak memory 201036 kb
Host smart-19ea48f3-8824-41b0-b392-814fcdde3349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283059773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.4283059773
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.4090986529
Short name T15
Test name
Test status
Simulation time 180873675 ps
CPU time 1.25 seconds
Started Jun 05 03:54:34 PM PDT 24
Finished Jun 05 03:54:37 PM PDT 24
Peak memory 200808 kb
Host smart-1a9f3f67-d5be-4903-a4f1-a7e05db17512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090986529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.4090986529
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.842836665
Short name T256
Test name
Test status
Simulation time 251400396 ps
CPU time 1.45 seconds
Started Jun 05 03:54:24 PM PDT 24
Finished Jun 05 03:54:27 PM PDT 24
Peak memory 201012 kb
Host smart-1b8c7837-2a39-426c-9384-b92e03feecc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842836665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.842836665
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.542544847
Short name T73
Test name
Test status
Simulation time 11568049321 ps
CPU time 38.39 seconds
Started Jun 05 03:54:32 PM PDT 24
Finished Jun 05 03:55:12 PM PDT 24
Peak memory 201124 kb
Host smart-46024150-9b26-47cf-a62a-1060c91fe9f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542544847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.542544847
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2941560580
Short name T77
Test name
Test status
Simulation time 109064044 ps
CPU time 1.37 seconds
Started Jun 05 03:54:36 PM PDT 24
Finished Jun 05 03:54:38 PM PDT 24
Peak memory 200756 kb
Host smart-cb5a9cf8-d295-43fa-a56a-b3d03464e2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941560580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2941560580
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.258106133
Short name T536
Test name
Test status
Simulation time 233241013 ps
CPU time 1.34 seconds
Started Jun 05 03:54:33 PM PDT 24
Finished Jun 05 03:54:35 PM PDT 24
Peak memory 201012 kb
Host smart-73a888a0-67ba-4729-a79e-7c0ca64588ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258106133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.258106133
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.99080759
Short name T358
Test name
Test status
Simulation time 74276711 ps
CPU time 0.79 seconds
Started Jun 05 03:54:35 PM PDT 24
Finished Jun 05 03:54:37 PM PDT 24
Peak memory 200640 kb
Host smart-bfda12e1-6607-4e5b-bd4f-c7912ff1a7c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99080759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.99080759
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2830916478
Short name T406
Test name
Test status
Simulation time 1211298426 ps
CPU time 5.45 seconds
Started Jun 05 03:54:35 PM PDT 24
Finished Jun 05 03:54:42 PM PDT 24
Peak memory 218452 kb
Host smart-a4b109c9-4652-4136-a754-4def69b5fd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830916478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2830916478
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.1936174424
Short name T368
Test name
Test status
Simulation time 245234846 ps
CPU time 0.99 seconds
Started Jun 05 03:54:31 PM PDT 24
Finished Jun 05 03:54:33 PM PDT 24
Peak memory 217880 kb
Host smart-91857270-669e-483f-a4c1-efbea59e3355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936174424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.1936174424
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.304745297
Short name T163
Test name
Test status
Simulation time 102651840 ps
CPU time 0.75 seconds
Started Jun 05 03:54:33 PM PDT 24
Finished Jun 05 03:54:35 PM PDT 24
Peak memory 200612 kb
Host smart-b78c432d-c187-48c1-8cb4-f5c107c0baa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304745297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.304745297
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.70586791
Short name T217
Test name
Test status
Simulation time 1232781486 ps
CPU time 5.76 seconds
Started Jun 05 03:54:32 PM PDT 24
Finished Jun 05 03:54:39 PM PDT 24
Peak memory 201020 kb
Host smart-9fb7251f-65b7-49d0-8fe3-a2ae471f9e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70586791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.70586791
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1514066882
Short name T154
Test name
Test status
Simulation time 171107491 ps
CPU time 1.19 seconds
Started Jun 05 03:54:33 PM PDT 24
Finished Jun 05 03:54:35 PM PDT 24
Peak memory 200816 kb
Host smart-1b837c27-0154-40cf-8b02-873db18d2d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514066882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1514066882
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3109974292
Short name T528
Test name
Test status
Simulation time 233190111 ps
CPU time 1.57 seconds
Started Jun 05 03:54:33 PM PDT 24
Finished Jun 05 03:54:36 PM PDT 24
Peak memory 200988 kb
Host smart-74aad1b2-a972-4d7b-b10f-a7361254fda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109974292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3109974292
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3062459778
Short name T289
Test name
Test status
Simulation time 9360935050 ps
CPU time 34.68 seconds
Started Jun 05 03:54:41 PM PDT 24
Finished Jun 05 03:55:16 PM PDT 24
Peak memory 200832 kb
Host smart-909ff473-b54e-4a75-bca2-5fe28adbc5d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062459778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3062459778
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1822937614
Short name T54
Test name
Test status
Simulation time 156078085 ps
CPU time 1.91 seconds
Started Jun 05 03:54:35 PM PDT 24
Finished Jun 05 03:54:38 PM PDT 24
Peak memory 200796 kb
Host smart-8b2cb449-7281-4be9-b192-c6215f53588e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822937614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1822937614
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1190276030
Short name T460
Test name
Test status
Simulation time 87906142 ps
CPU time 0.88 seconds
Started Jun 05 03:54:36 PM PDT 24
Finished Jun 05 03:54:38 PM PDT 24
Peak memory 200828 kb
Host smart-0013e670-e684-4636-8ae8-6274f96724e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190276030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1190276030
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1921178900
Short name T336
Test name
Test status
Simulation time 59453542 ps
CPU time 0.74 seconds
Started Jun 05 03:53:14 PM PDT 24
Finished Jun 05 03:53:15 PM PDT 24
Peak memory 200636 kb
Host smart-08d4c2ea-1efe-42ed-8c96-2895589a2098
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921178900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1921178900
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2312550557
Short name T46
Test name
Test status
Simulation time 1226128713 ps
CPU time 5.67 seconds
Started Jun 05 03:53:15 PM PDT 24
Finished Jun 05 03:53:22 PM PDT 24
Peak memory 217852 kb
Host smart-9e8b1065-6be0-4624-93c2-f1acc7adbfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312550557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2312550557
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2161320731
Short name T331
Test name
Test status
Simulation time 244834002 ps
CPU time 1.13 seconds
Started Jun 05 03:53:15 PM PDT 24
Finished Jun 05 03:53:16 PM PDT 24
Peak memory 218200 kb
Host smart-b530eb7f-b52a-4997-86bb-08fa0ea11c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161320731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2161320731
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3737515180
Short name T426
Test name
Test status
Simulation time 170069077 ps
CPU time 0.81 seconds
Started Jun 05 03:53:04 PM PDT 24
Finished Jun 05 03:53:06 PM PDT 24
Peak memory 200632 kb
Host smart-e7ec94c0-cb2b-443e-b84a-4544b3890942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737515180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3737515180
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1849633174
Short name T438
Test name
Test status
Simulation time 2134667014 ps
CPU time 7.29 seconds
Started Jun 05 03:53:08 PM PDT 24
Finished Jun 05 03:53:16 PM PDT 24
Peak memory 200952 kb
Host smart-8b1d1495-c662-44f2-9f61-15ac0ca9bff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849633174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1849633174
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2318694852
Short name T68
Test name
Test status
Simulation time 16539377022 ps
CPU time 26.29 seconds
Started Jun 05 03:53:14 PM PDT 24
Finished Jun 05 03:53:41 PM PDT 24
Peak memory 218672 kb
Host smart-1c48570e-8be7-47b5-bb63-52cfd8a777d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318694852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2318694852
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3759800512
Short name T339
Test name
Test status
Simulation time 95540904 ps
CPU time 0.98 seconds
Started Jun 05 03:53:12 PM PDT 24
Finished Jun 05 03:53:14 PM PDT 24
Peak memory 200820 kb
Host smart-e03da7be-82c4-472b-8573-e54e43b47bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759800512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3759800512
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1778301193
Short name T440
Test name
Test status
Simulation time 237084338 ps
CPU time 1.44 seconds
Started Jun 05 03:53:08 PM PDT 24
Finished Jun 05 03:53:10 PM PDT 24
Peak memory 201036 kb
Host smart-c2b5645f-63d7-4427-91ad-2202c63408cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778301193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1778301193
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.2722645244
Short name T385
Test name
Test status
Simulation time 5302563632 ps
CPU time 18.54 seconds
Started Jun 05 03:53:13 PM PDT 24
Finished Jun 05 03:53:32 PM PDT 24
Peak memory 201176 kb
Host smart-9441612b-60db-41b8-8ade-027f993ba37b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722645244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2722645244
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3241800810
Short name T329
Test name
Test status
Simulation time 459114632 ps
CPU time 2.33 seconds
Started Jun 05 03:53:05 PM PDT 24
Finished Jun 05 03:53:08 PM PDT 24
Peak memory 200768 kb
Host smart-fd14ab1a-7abf-439a-a4a8-f8a252fa14b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241800810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3241800810
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2750434741
Short name T16
Test name
Test status
Simulation time 85405830 ps
CPU time 0.82 seconds
Started Jun 05 03:53:05 PM PDT 24
Finished Jun 05 03:53:07 PM PDT 24
Peak memory 200460 kb
Host smart-d940e88e-1a39-48aa-b925-f02ab5881e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750434741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2750434741
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1820677854
Short name T384
Test name
Test status
Simulation time 67105766 ps
CPU time 0.74 seconds
Started Jun 05 03:54:34 PM PDT 24
Finished Jun 05 03:54:36 PM PDT 24
Peak memory 200640 kb
Host smart-bc1738dd-f653-4f0a-a38d-7bd5f54c4418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820677854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1820677854
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.33237736
Short name T293
Test name
Test status
Simulation time 1906295139 ps
CPU time 7.04 seconds
Started Jun 05 03:54:33 PM PDT 24
Finished Jun 05 03:54:41 PM PDT 24
Peak memory 218412 kb
Host smart-177c674b-4a29-4b48-9907-44055181c96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33237736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.33237736
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1298320274
Short name T342
Test name
Test status
Simulation time 249498699 ps
CPU time 1.05 seconds
Started Jun 05 03:54:35 PM PDT 24
Finished Jun 05 03:54:38 PM PDT 24
Peak memory 217936 kb
Host smart-3d600f0d-68e9-4254-86b9-8652b91fc099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298320274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1298320274
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3275985027
Short name T233
Test name
Test status
Simulation time 164984447 ps
CPU time 0.83 seconds
Started Jun 05 03:54:33 PM PDT 24
Finished Jun 05 03:54:35 PM PDT 24
Peak memory 200560 kb
Host smart-646f59e3-768e-47dd-9cd3-e637d810c128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275985027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3275985027
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.961079568
Short name T69
Test name
Test status
Simulation time 1886914896 ps
CPU time 6.68 seconds
Started Jun 05 03:54:35 PM PDT 24
Finished Jun 05 03:54:43 PM PDT 24
Peak memory 201024 kb
Host smart-bf10da94-0213-43b0-8dc7-8efbb2e187f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961079568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.961079568
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3329699605
Short name T370
Test name
Test status
Simulation time 173067914 ps
CPU time 1.21 seconds
Started Jun 05 03:54:36 PM PDT 24
Finished Jun 05 03:54:38 PM PDT 24
Peak memory 200728 kb
Host smart-ee61bdc2-4b7c-43bb-b0b2-75ab65f3e274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329699605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3329699605
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.4061246454
Short name T236
Test name
Test status
Simulation time 264564644 ps
CPU time 1.69 seconds
Started Jun 05 03:54:33 PM PDT 24
Finished Jun 05 03:54:36 PM PDT 24
Peak memory 200992 kb
Host smart-f12673dd-8b1a-4566-94ab-c3c41bd075d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061246454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.4061246454
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2817818565
Short name T517
Test name
Test status
Simulation time 1292880264 ps
CPU time 7.07 seconds
Started Jun 05 03:54:33 PM PDT 24
Finished Jun 05 03:54:41 PM PDT 24
Peak memory 209212 kb
Host smart-a213a518-d181-4479-ac8c-e8db153e8f19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817818565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2817818565
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.1143658225
Short name T324
Test name
Test status
Simulation time 150523911 ps
CPU time 1.73 seconds
Started Jun 05 03:54:35 PM PDT 24
Finished Jun 05 03:54:38 PM PDT 24
Peak memory 200816 kb
Host smart-97bd3c70-be61-418a-9848-54d20004de34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143658225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1143658225
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1218395987
Short name T194
Test name
Test status
Simulation time 235957934 ps
CPU time 1.48 seconds
Started Jun 05 03:54:32 PM PDT 24
Finished Jun 05 03:54:34 PM PDT 24
Peak memory 200992 kb
Host smart-0c50f8e4-8038-4ed7-8da7-0a5ce473bab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218395987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1218395987
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2754618237
Short name T470
Test name
Test status
Simulation time 76742027 ps
CPU time 0.88 seconds
Started Jun 05 03:54:33 PM PDT 24
Finished Jun 05 03:54:35 PM PDT 24
Peak memory 200644 kb
Host smart-1f79cab9-7097-4f7e-abf5-d4feba044c2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754618237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2754618237
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.507321356
Short name T142
Test name
Test status
Simulation time 244072696 ps
CPU time 1.13 seconds
Started Jun 05 03:54:41 PM PDT 24
Finished Jun 05 03:54:43 PM PDT 24
Peak memory 217972 kb
Host smart-0098a376-6fc0-4909-a166-cc12c9226aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507321356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.507321356
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.3839371339
Short name T20
Test name
Test status
Simulation time 206666766 ps
CPU time 0.96 seconds
Started Jun 05 03:54:33 PM PDT 24
Finished Jun 05 03:54:35 PM PDT 24
Peak memory 200656 kb
Host smart-fedda79b-05b5-472c-bf6b-77db25e46455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839371339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3839371339
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.4061354757
Short name T501
Test name
Test status
Simulation time 1436877431 ps
CPU time 5.76 seconds
Started Jun 05 03:54:32 PM PDT 24
Finished Jun 05 03:54:38 PM PDT 24
Peak memory 200996 kb
Host smart-aff9d5ae-51e7-4a45-9309-e5877003230d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061354757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.4061354757
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2403175043
Short name T510
Test name
Test status
Simulation time 96322987 ps
CPU time 1 seconds
Started Jun 05 03:54:37 PM PDT 24
Finished Jun 05 03:54:39 PM PDT 24
Peak memory 200824 kb
Host smart-9c637869-9150-4d18-b297-0aaa7fac6be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403175043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2403175043
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3766011575
Short name T445
Test name
Test status
Simulation time 201860169 ps
CPU time 1.37 seconds
Started Jun 05 03:54:33 PM PDT 24
Finished Jun 05 03:54:35 PM PDT 24
Peak memory 201016 kb
Host smart-992346d7-e7d9-4ef0-b890-152cd1eb51ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766011575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3766011575
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3656926638
Short name T352
Test name
Test status
Simulation time 10608582690 ps
CPU time 42.04 seconds
Started Jun 05 03:54:31 PM PDT 24
Finished Jun 05 03:55:14 PM PDT 24
Peak memory 209304 kb
Host smart-82230c00-19f3-48fa-916f-28f59f6c365d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656926638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3656926638
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3397988381
Short name T28
Test name
Test status
Simulation time 530459774 ps
CPU time 2.83 seconds
Started Jun 05 03:54:32 PM PDT 24
Finished Jun 05 03:54:35 PM PDT 24
Peak memory 200804 kb
Host smart-3d67d15e-09c8-445d-944f-b24e910a249f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397988381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3397988381
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2964819421
Short name T216
Test name
Test status
Simulation time 166524701 ps
CPU time 1.13 seconds
Started Jun 05 03:54:33 PM PDT 24
Finished Jun 05 03:54:35 PM PDT 24
Peak memory 200784 kb
Host smart-be971fe6-c2fd-4788-a5fd-84d4bcaa2bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964819421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2964819421
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1157247829
Short name T169
Test name
Test status
Simulation time 65244485 ps
CPU time 0.76 seconds
Started Jun 05 03:54:32 PM PDT 24
Finished Jun 05 03:54:33 PM PDT 24
Peak memory 200884 kb
Host smart-6566acd2-e9a0-4696-be60-26ea8d835a4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157247829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1157247829
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.709041721
Short name T5
Test name
Test status
Simulation time 1227574085 ps
CPU time 6.26 seconds
Started Jun 05 03:54:31 PM PDT 24
Finished Jun 05 03:54:38 PM PDT 24
Peak memory 218440 kb
Host smart-ea77b2aa-e66b-4933-a6ae-e43c15f5167a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709041721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.709041721
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.19680185
Short name T115
Test name
Test status
Simulation time 244331671 ps
CPU time 1.08 seconds
Started Jun 05 03:54:35 PM PDT 24
Finished Jun 05 03:54:38 PM PDT 24
Peak memory 217984 kb
Host smart-f631d5e9-de81-429e-a4e8-4d67b6474a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19680185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.19680185
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.469088675
Short name T449
Test name
Test status
Simulation time 82272940 ps
CPU time 0.75 seconds
Started Jun 05 03:54:35 PM PDT 24
Finished Jun 05 03:54:37 PM PDT 24
Peak memory 200620 kb
Host smart-ebe0589e-5031-44df-96e7-5fef98a5dc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469088675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.469088675
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.3225991020
Short name T452
Test name
Test status
Simulation time 1684671168 ps
CPU time 5.9 seconds
Started Jun 05 03:54:34 PM PDT 24
Finished Jun 05 03:54:41 PM PDT 24
Peak memory 200972 kb
Host smart-ca7f3ba5-f170-4984-9413-c6caf421b103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225991020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3225991020
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1434121555
Short name T156
Test name
Test status
Simulation time 107205386 ps
CPU time 1.01 seconds
Started Jun 05 03:54:35 PM PDT 24
Finished Jun 05 03:54:38 PM PDT 24
Peak memory 200812 kb
Host smart-2942a0ca-225d-414e-a454-27484b4cb6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434121555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1434121555
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2316538982
Short name T413
Test name
Test status
Simulation time 113945461 ps
CPU time 1.26 seconds
Started Jun 05 03:54:31 PM PDT 24
Finished Jun 05 03:54:33 PM PDT 24
Peak memory 200908 kb
Host smart-d876737c-8f0b-4390-a33c-451f48111416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316538982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2316538982
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2421791507
Short name T347
Test name
Test status
Simulation time 10448989175 ps
CPU time 38.66 seconds
Started Jun 05 03:54:41 PM PDT 24
Finished Jun 05 03:55:20 PM PDT 24
Peak memory 200956 kb
Host smart-97391a09-9be0-4ae2-b872-9d1b8c00791e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421791507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2421791507
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3713692846
Short name T391
Test name
Test status
Simulation time 142163844 ps
CPU time 1.74 seconds
Started Jun 05 03:54:33 PM PDT 24
Finished Jun 05 03:54:36 PM PDT 24
Peak memory 200776 kb
Host smart-d7ccc326-346a-459d-9597-3f90dd6ab3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713692846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3713692846
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.3496365655
Short name T429
Test name
Test status
Simulation time 150660853 ps
CPU time 1.16 seconds
Started Jun 05 03:54:35 PM PDT 24
Finished Jun 05 03:54:38 PM PDT 24
Peak memory 200804 kb
Host smart-90f4ce4f-f56e-464d-926b-c3a1e6e9eb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496365655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3496365655
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2914395127
Short name T539
Test name
Test status
Simulation time 60863641 ps
CPU time 0.77 seconds
Started Jun 05 03:54:45 PM PDT 24
Finished Jun 05 03:54:48 PM PDT 24
Peak memory 200644 kb
Host smart-2550eeb5-aefd-4488-b3f6-0d735501ec7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914395127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2914395127
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.125859060
Short name T486
Test name
Test status
Simulation time 2163766169 ps
CPU time 7.88 seconds
Started Jun 05 03:54:44 PM PDT 24
Finished Jun 05 03:54:53 PM PDT 24
Peak memory 218556 kb
Host smart-f5a87d00-fa78-4cb6-9ad4-2a27e7d93db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125859060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.125859060
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1376085962
Short name T263
Test name
Test status
Simulation time 244582623 ps
CPU time 1.06 seconds
Started Jun 05 03:54:46 PM PDT 24
Finished Jun 05 03:54:49 PM PDT 24
Peak memory 217992 kb
Host smart-66e6d505-8e4e-4934-abb0-02724c927b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376085962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1376085962
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.159448075
Short name T464
Test name
Test status
Simulation time 168290002 ps
CPU time 0.9 seconds
Started Jun 05 03:54:35 PM PDT 24
Finished Jun 05 03:54:37 PM PDT 24
Peak memory 200616 kb
Host smart-aaf2214b-9fcf-45ac-a57e-647b90b020d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159448075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.159448075
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3073888382
Short name T491
Test name
Test status
Simulation time 1840419133 ps
CPU time 6.48 seconds
Started Jun 05 03:54:35 PM PDT 24
Finished Jun 05 03:54:43 PM PDT 24
Peak memory 200992 kb
Host smart-bc174989-c642-404c-8454-07474f606cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073888382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3073888382
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3811343804
Short name T172
Test name
Test status
Simulation time 95318992 ps
CPU time 1 seconds
Started Jun 05 03:54:47 PM PDT 24
Finished Jun 05 03:54:49 PM PDT 24
Peak memory 200792 kb
Host smart-244fc14a-78f7-406b-8a56-3b31fe4f7702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811343804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3811343804
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.1147788049
Short name T456
Test name
Test status
Simulation time 200822225 ps
CPU time 1.45 seconds
Started Jun 05 03:54:32 PM PDT 24
Finished Jun 05 03:54:35 PM PDT 24
Peak memory 201036 kb
Host smart-4d58c8e9-0ac5-4c4a-9b07-6f0c1c257298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147788049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1147788049
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2581269319
Short name T70
Test name
Test status
Simulation time 7547088409 ps
CPU time 32.87 seconds
Started Jun 05 03:54:44 PM PDT 24
Finished Jun 05 03:55:17 PM PDT 24
Peak memory 201140 kb
Host smart-363c173f-5961-4198-9853-59d7feb68f2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581269319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2581269319
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.824267964
Short name T239
Test name
Test status
Simulation time 283580545 ps
CPU time 1.81 seconds
Started Jun 05 03:54:43 PM PDT 24
Finished Jun 05 03:54:46 PM PDT 24
Peak memory 200828 kb
Host smart-87f4ad31-b03c-4929-8ea5-e4fae3ed7f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824267964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.824267964
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.4271246139
Short name T291
Test name
Test status
Simulation time 164373740 ps
CPU time 1.15 seconds
Started Jun 05 03:54:42 PM PDT 24
Finished Jun 05 03:54:45 PM PDT 24
Peak memory 200212 kb
Host smart-c308ad80-d323-4eb2-ba25-86689c09a288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271246139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.4271246139
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1032215470
Short name T45
Test name
Test status
Simulation time 1232125288 ps
CPU time 5.55 seconds
Started Jun 05 03:54:43 PM PDT 24
Finished Jun 05 03:54:50 PM PDT 24
Peak memory 222016 kb
Host smart-bbc0b9db-d106-4c97-96f3-34859f3cc4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032215470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1032215470
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.4197679549
Short name T532
Test name
Test status
Simulation time 244158019 ps
CPU time 1.05 seconds
Started Jun 05 03:54:44 PM PDT 24
Finished Jun 05 03:54:47 PM PDT 24
Peak memory 218028 kb
Host smart-4f86ebf2-a56f-46e9-b593-a23aa01732d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197679549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.4197679549
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.707487145
Short name T436
Test name
Test status
Simulation time 93364567 ps
CPU time 0.82 seconds
Started Jun 05 03:54:42 PM PDT 24
Finished Jun 05 03:54:43 PM PDT 24
Peak memory 200624 kb
Host smart-93539108-5b61-426f-b279-acc917ada790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707487145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.707487145
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.1649219134
Short name T425
Test name
Test status
Simulation time 1816663663 ps
CPU time 7.16 seconds
Started Jun 05 03:54:43 PM PDT 24
Finished Jun 05 03:54:52 PM PDT 24
Peak memory 201244 kb
Host smart-426b275e-f31e-4da3-bdcb-9c37cdba16b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649219134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1649219134
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.4250268002
Short name T511
Test name
Test status
Simulation time 188148391 ps
CPU time 1.15 seconds
Started Jun 05 03:54:41 PM PDT 24
Finished Jun 05 03:54:43 PM PDT 24
Peak memory 200812 kb
Host smart-323b82ad-3b5e-4862-9cba-85076541f02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250268002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.4250268002
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2266942867
Short name T461
Test name
Test status
Simulation time 122397106 ps
CPU time 1.16 seconds
Started Jun 05 03:54:47 PM PDT 24
Finished Jun 05 03:54:49 PM PDT 24
Peak memory 200972 kb
Host smart-3276a49d-ef21-4b97-855c-5bd28260f47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266942867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2266942867
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3891606352
Short name T408
Test name
Test status
Simulation time 539737310 ps
CPU time 3.14 seconds
Started Jun 05 03:54:44 PM PDT 24
Finished Jun 05 03:54:49 PM PDT 24
Peak memory 200808 kb
Host smart-d70fc22c-12ed-450a-ac0f-5aeab4f01c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891606352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3891606352
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3448656766
Short name T499
Test name
Test status
Simulation time 74078395 ps
CPU time 0.76 seconds
Started Jun 05 03:54:45 PM PDT 24
Finished Jun 05 03:54:47 PM PDT 24
Peak memory 200732 kb
Host smart-70bd33a1-93b4-4af3-8cb1-5942bdc4ad79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448656766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3448656766
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2608984321
Short name T518
Test name
Test status
Simulation time 68831006 ps
CPU time 0.8 seconds
Started Jun 05 03:54:43 PM PDT 24
Finished Jun 05 03:54:44 PM PDT 24
Peak memory 200660 kb
Host smart-15fb5c27-0514-4575-b221-a7bf85f0ab63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608984321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2608984321
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.635906985
Short name T389
Test name
Test status
Simulation time 2351211123 ps
CPU time 8.76 seconds
Started Jun 05 03:54:43 PM PDT 24
Finished Jun 05 03:54:53 PM PDT 24
Peak memory 222560 kb
Host smart-3426aa04-a461-4b73-bee8-0534b61453e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635906985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.635906985
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.531720057
Short name T212
Test name
Test status
Simulation time 244282723 ps
CPU time 1.07 seconds
Started Jun 05 03:54:44 PM PDT 24
Finished Jun 05 03:54:47 PM PDT 24
Peak memory 217944 kb
Host smart-bdcb5b2d-b5bf-46fd-b408-b4aec4982703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531720057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.531720057
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.709485312
Short name T374
Test name
Test status
Simulation time 97077989 ps
CPU time 0.74 seconds
Started Jun 05 03:54:47 PM PDT 24
Finished Jun 05 03:54:49 PM PDT 24
Peak memory 200832 kb
Host smart-7152bef1-de78-4399-b580-010466189dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709485312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.709485312
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.2728421584
Short name T321
Test name
Test status
Simulation time 1559951420 ps
CPU time 5.95 seconds
Started Jun 05 03:54:46 PM PDT 24
Finished Jun 05 03:54:54 PM PDT 24
Peak memory 201036 kb
Host smart-ec1182ca-3899-483b-89c3-9e118a303dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728421584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2728421584
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2481990499
Short name T450
Test name
Test status
Simulation time 171486143 ps
CPU time 1.19 seconds
Started Jun 05 03:54:40 PM PDT 24
Finished Jun 05 03:54:42 PM PDT 24
Peak memory 200728 kb
Host smart-9083a95c-fe7e-405b-80f1-40e1f1ce06b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481990499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2481990499
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1500146252
Short name T210
Test name
Test status
Simulation time 120947583 ps
CPU time 1.24 seconds
Started Jun 05 03:54:40 PM PDT 24
Finished Jun 05 03:54:42 PM PDT 24
Peak memory 200992 kb
Host smart-e69dad60-6863-46a2-a7c5-f0bbb8c91224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500146252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1500146252
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2706556261
Short name T270
Test name
Test status
Simulation time 7163084860 ps
CPU time 24.49 seconds
Started Jun 05 03:54:46 PM PDT 24
Finished Jun 05 03:55:12 PM PDT 24
Peak memory 209332 kb
Host smart-1b8eda80-e87a-4eaf-9ef1-31f767ff64ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706556261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2706556261
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3923971708
Short name T366
Test name
Test status
Simulation time 450317791 ps
CPU time 2.43 seconds
Started Jun 05 03:54:41 PM PDT 24
Finished Jun 05 03:54:44 PM PDT 24
Peak memory 200720 kb
Host smart-821779cd-3ab5-4557-bffd-48cde6d1cce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923971708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3923971708
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3729010937
Short name T503
Test name
Test status
Simulation time 266234107 ps
CPU time 1.45 seconds
Started Jun 05 03:54:44 PM PDT 24
Finished Jun 05 03:54:47 PM PDT 24
Peak memory 200852 kb
Host smart-fea0f6de-c256-4189-9285-0903f93fc0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729010937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3729010937
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3908082326
Short name T515
Test name
Test status
Simulation time 84565269 ps
CPU time 0.8 seconds
Started Jun 05 03:54:46 PM PDT 24
Finished Jun 05 03:54:49 PM PDT 24
Peak memory 200652 kb
Host smart-d41d70e9-6fe6-4131-9b87-6f7d7000476d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908082326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3908082326
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1883270230
Short name T43
Test name
Test status
Simulation time 2170505781 ps
CPU time 8.29 seconds
Started Jun 05 03:54:42 PM PDT 24
Finished Jun 05 03:54:52 PM PDT 24
Peak memory 217420 kb
Host smart-34258a26-bb83-4226-8367-4ce757049bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883270230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1883270230
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1810334133
Short name T454
Test name
Test status
Simulation time 244782291 ps
CPU time 1.07 seconds
Started Jun 05 03:54:45 PM PDT 24
Finished Jun 05 03:54:47 PM PDT 24
Peak memory 217932 kb
Host smart-412abe2f-dc47-43e6-8663-f83f07d54859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810334133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1810334133
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.4087862407
Short name T19
Test name
Test status
Simulation time 201236117 ps
CPU time 0.95 seconds
Started Jun 05 03:54:45 PM PDT 24
Finished Jun 05 03:54:47 PM PDT 24
Peak memory 200640 kb
Host smart-3823ea63-5b20-4b22-9087-710b8d98efa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087862407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.4087862407
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3105937035
Short name T369
Test name
Test status
Simulation time 1002155765 ps
CPU time 5.18 seconds
Started Jun 05 03:54:44 PM PDT 24
Finished Jun 05 03:54:51 PM PDT 24
Peak memory 200956 kb
Host smart-f539baf9-5e66-47e8-96ca-84e52e885ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105937035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3105937035
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2034202430
Short name T159
Test name
Test status
Simulation time 142071290 ps
CPU time 1.14 seconds
Started Jun 05 03:54:48 PM PDT 24
Finished Jun 05 03:54:51 PM PDT 24
Peak memory 200812 kb
Host smart-62197375-8eef-459b-b5cc-21226e813849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034202430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2034202430
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.171612717
Short name T345
Test name
Test status
Simulation time 114190755 ps
CPU time 1.15 seconds
Started Jun 05 03:54:45 PM PDT 24
Finished Jun 05 03:54:47 PM PDT 24
Peak memory 200984 kb
Host smart-2951786f-19e4-4ef9-8e42-0a420dc77cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171612717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.171612717
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1461188030
Short name T267
Test name
Test status
Simulation time 2019636892 ps
CPU time 7.51 seconds
Started Jun 05 03:54:42 PM PDT 24
Finished Jun 05 03:54:50 PM PDT 24
Peak memory 201008 kb
Host smart-d6f74953-f5ca-4a02-840c-8e90b8c057f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461188030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1461188030
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.2859729176
Short name T220
Test name
Test status
Simulation time 390998349 ps
CPU time 2.28 seconds
Started Jun 05 03:54:42 PM PDT 24
Finished Jun 05 03:54:45 PM PDT 24
Peak memory 209028 kb
Host smart-78dd29e8-e323-4ef1-a03c-07b6e137b11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859729176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2859729176
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.87176688
Short name T174
Test name
Test status
Simulation time 146240164 ps
CPU time 1.28 seconds
Started Jun 05 03:54:43 PM PDT 24
Finished Jun 05 03:54:45 PM PDT 24
Peak memory 200992 kb
Host smart-87a14552-afe3-407d-8bb9-27aa565f5152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87176688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.87176688
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3542209386
Short name T419
Test name
Test status
Simulation time 72614683 ps
CPU time 0.78 seconds
Started Jun 05 03:54:47 PM PDT 24
Finished Jun 05 03:54:50 PM PDT 24
Peak memory 200628 kb
Host smart-61173264-b380-4d22-a95c-5c42b8b058ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542209386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3542209386
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.423321771
Short name T40
Test name
Test status
Simulation time 1219916202 ps
CPU time 5.73 seconds
Started Jun 05 03:54:42 PM PDT 24
Finished Jun 05 03:54:48 PM PDT 24
Peak memory 217868 kb
Host smart-0d8cfbb6-ba64-4b59-89bc-48e9c2174841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423321771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.423321771
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3736981862
Short name T175
Test name
Test status
Simulation time 245123104 ps
CPU time 1.05 seconds
Started Jun 05 03:54:44 PM PDT 24
Finished Jun 05 03:54:47 PM PDT 24
Peak memory 217924 kb
Host smart-9515cec0-63bf-4603-bd55-2ec1d13a668c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736981862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3736981862
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.3116140631
Short name T444
Test name
Test status
Simulation time 122704168 ps
CPU time 0.78 seconds
Started Jun 05 03:54:47 PM PDT 24
Finished Jun 05 03:54:49 PM PDT 24
Peak memory 200636 kb
Host smart-3ac52005-a84e-4e37-ae61-eb9b4ee1adb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116140631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3116140631
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2102498063
Short name T188
Test name
Test status
Simulation time 1530671847 ps
CPU time 6.32 seconds
Started Jun 05 03:54:42 PM PDT 24
Finished Jun 05 03:54:50 PM PDT 24
Peak memory 200992 kb
Host smart-c5c440dd-01a2-47e1-b06b-d7f26a34d764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102498063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2102498063
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2677332775
Short name T346
Test name
Test status
Simulation time 160565869 ps
CPU time 1.11 seconds
Started Jun 05 03:54:47 PM PDT 24
Finished Jun 05 03:54:49 PM PDT 24
Peak memory 200812 kb
Host smart-f1047608-61dd-474c-bb4a-838f030f99f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677332775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2677332775
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.3385998134
Short name T375
Test name
Test status
Simulation time 119155902 ps
CPU time 1.12 seconds
Started Jun 05 03:54:46 PM PDT 24
Finished Jun 05 03:54:49 PM PDT 24
Peak memory 200996 kb
Host smart-59a11d66-cff8-4e82-82f5-99c3f0d4d620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385998134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.3385998134
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.1198629755
Short name T307
Test name
Test status
Simulation time 443153586 ps
CPU time 2.28 seconds
Started Jun 05 03:54:42 PM PDT 24
Finished Jun 05 03:54:45 PM PDT 24
Peak memory 201040 kb
Host smart-11fe2b1b-ed6d-4c62-a1f2-f8f808c29e2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198629755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1198629755
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.1109169720
Short name T242
Test name
Test status
Simulation time 155622950 ps
CPU time 1.89 seconds
Started Jun 05 03:54:41 PM PDT 24
Finished Jun 05 03:54:43 PM PDT 24
Peak memory 201064 kb
Host smart-6ace8036-6a65-40e8-b654-560617c6d353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109169720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1109169720
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.705466182
Short name T202
Test name
Test status
Simulation time 214279652 ps
CPU time 1.29 seconds
Started Jun 05 03:54:43 PM PDT 24
Finished Jun 05 03:54:45 PM PDT 24
Peak memory 200812 kb
Host smart-a759d2f8-a046-4d2d-be71-4c598f0425e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705466182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.705466182
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.1919214851
Short name T439
Test name
Test status
Simulation time 70243863 ps
CPU time 0.8 seconds
Started Jun 05 03:54:43 PM PDT 24
Finished Jun 05 03:54:45 PM PDT 24
Peak memory 200572 kb
Host smart-6beedf10-181a-44b1-ac0e-01d3ee2bc35d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919214851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1919214851
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2818309811
Short name T433
Test name
Test status
Simulation time 1222283645 ps
CPU time 5.38 seconds
Started Jun 05 03:54:45 PM PDT 24
Finished Jun 05 03:54:52 PM PDT 24
Peak memory 222460 kb
Host smart-a910c416-f236-43f2-b7ed-d7249262a536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818309811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2818309811
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.552345291
Short name T465
Test name
Test status
Simulation time 244193281 ps
CPU time 1.12 seconds
Started Jun 05 03:54:45 PM PDT 24
Finished Jun 05 03:54:48 PM PDT 24
Peak memory 218040 kb
Host smart-4d884e1c-62ad-44f1-957f-9a36b5bc639f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552345291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.552345291
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.1916850426
Short name T265
Test name
Test status
Simulation time 121443106 ps
CPU time 0.81 seconds
Started Jun 05 03:54:48 PM PDT 24
Finished Jun 05 03:54:50 PM PDT 24
Peak memory 200640 kb
Host smart-1d5ef031-6b41-4a59-afdd-2742761d20dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916850426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1916850426
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2723286648
Short name T187
Test name
Test status
Simulation time 1076447959 ps
CPU time 4.68 seconds
Started Jun 05 03:54:44 PM PDT 24
Finished Jun 05 03:54:51 PM PDT 24
Peak memory 200996 kb
Host smart-4b44c37d-7228-4747-80b6-4abf57b04891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723286648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2723286648
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1293391334
Short name T320
Test name
Test status
Simulation time 192025260 ps
CPU time 1.24 seconds
Started Jun 05 03:54:42 PM PDT 24
Finished Jun 05 03:54:44 PM PDT 24
Peak memory 200816 kb
Host smart-fadcca86-09ab-47d0-a78d-fffd6270cb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293391334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1293391334
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2844800512
Short name T130
Test name
Test status
Simulation time 198954079 ps
CPU time 1.41 seconds
Started Jun 05 03:54:42 PM PDT 24
Finished Jun 05 03:54:45 PM PDT 24
Peak memory 201024 kb
Host smart-47969bee-585f-42e8-99c8-985861fece94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844800512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2844800512
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.4138427968
Short name T189
Test name
Test status
Simulation time 3147719026 ps
CPU time 14.36 seconds
Started Jun 05 03:54:46 PM PDT 24
Finished Jun 05 03:55:02 PM PDT 24
Peak memory 201140 kb
Host smart-d41198c1-3400-4456-836e-7bde46939cb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138427968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.4138427968
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1990889813
Short name T253
Test name
Test status
Simulation time 141787677 ps
CPU time 1.73 seconds
Started Jun 05 03:54:45 PM PDT 24
Finished Jun 05 03:54:48 PM PDT 24
Peak memory 208912 kb
Host smart-1d434e7b-cc1a-467f-8750-d8735940d4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990889813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1990889813
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3031917185
Short name T312
Test name
Test status
Simulation time 144991211 ps
CPU time 1.26 seconds
Started Jun 05 03:54:43 PM PDT 24
Finished Jun 05 03:54:45 PM PDT 24
Peak memory 200792 kb
Host smart-8a53d762-7f80-4442-a139-8df03353ffed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031917185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3031917185
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1366926233
Short name T392
Test name
Test status
Simulation time 54527787 ps
CPU time 0.75 seconds
Started Jun 05 03:54:50 PM PDT 24
Finished Jun 05 03:54:51 PM PDT 24
Peak memory 200880 kb
Host smart-43e7cc6d-10c3-4bcc-8afb-541517747713
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366926233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1366926233
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1631294784
Short name T41
Test name
Test status
Simulation time 2366503763 ps
CPU time 8.22 seconds
Started Jun 05 03:55:05 PM PDT 24
Finished Jun 05 03:55:14 PM PDT 24
Peak memory 218284 kb
Host smart-50009048-50bc-49ea-985b-4e51e11d9fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631294784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1631294784
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1326547106
Short name T495
Test name
Test status
Simulation time 244577498 ps
CPU time 1.14 seconds
Started Jun 05 03:54:55 PM PDT 24
Finished Jun 05 03:54:57 PM PDT 24
Peak memory 217904 kb
Host smart-744b0d71-dad7-4e14-b3eb-d6dc876620d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326547106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1326547106
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.680622781
Short name T533
Test name
Test status
Simulation time 110195110 ps
CPU time 0.8 seconds
Started Jun 05 03:54:43 PM PDT 24
Finished Jun 05 03:54:45 PM PDT 24
Peak memory 200644 kb
Host smart-27f103b4-9d48-436f-be7d-ce7e273923f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680622781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.680622781
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1487074499
Short name T91
Test name
Test status
Simulation time 1149752680 ps
CPU time 5.53 seconds
Started Jun 05 03:54:48 PM PDT 24
Finished Jun 05 03:54:55 PM PDT 24
Peak memory 200996 kb
Host smart-f8633c16-b7c8-4533-b9eb-9968f27387e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487074499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1487074499
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1170584972
Short name T148
Test name
Test status
Simulation time 180905979 ps
CPU time 1.18 seconds
Started Jun 05 03:55:05 PM PDT 24
Finished Jun 05 03:55:07 PM PDT 24
Peak memory 200804 kb
Host smart-7a2f4227-aedb-4642-a461-bad37cf880e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170584972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1170584972
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3573948338
Short name T463
Test name
Test status
Simulation time 221275400 ps
CPU time 1.38 seconds
Started Jun 05 03:54:45 PM PDT 24
Finished Jun 05 03:54:48 PM PDT 24
Peak memory 200964 kb
Host smart-a8804a92-a41c-48d7-be37-77fab3eadb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573948338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3573948338
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2780591663
Short name T524
Test name
Test status
Simulation time 809455764 ps
CPU time 3.43 seconds
Started Jun 05 03:55:00 PM PDT 24
Finished Jun 05 03:55:05 PM PDT 24
Peak memory 201036 kb
Host smart-d556dc87-3d6a-4b6b-acc7-b1de57dbb338
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780591663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2780591663
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1100845850
Short name T362
Test name
Test status
Simulation time 439834855 ps
CPU time 2.53 seconds
Started Jun 05 03:54:44 PM PDT 24
Finished Jun 05 03:54:48 PM PDT 24
Peak memory 200812 kb
Host smart-2b156d02-8c12-4bf3-8c75-18a41118ff1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100845850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1100845850
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.272956526
Short name T506
Test name
Test status
Simulation time 287736703 ps
CPU time 1.54 seconds
Started Jun 05 03:54:45 PM PDT 24
Finished Jun 05 03:54:48 PM PDT 24
Peak memory 201052 kb
Host smart-921f36e4-4ff5-45bc-9895-c6ebeab5faac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272956526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.272956526
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.1243507954
Short name T281
Test name
Test status
Simulation time 87441230 ps
CPU time 0.82 seconds
Started Jun 05 03:53:13 PM PDT 24
Finished Jun 05 03:53:15 PM PDT 24
Peak memory 200552 kb
Host smart-497d373b-07c6-45d9-b7ab-0f1fac3c7b0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243507954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1243507954
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1990834110
Short name T423
Test name
Test status
Simulation time 1905956904 ps
CPU time 7.91 seconds
Started Jun 05 03:53:13 PM PDT 24
Finished Jun 05 03:53:22 PM PDT 24
Peak memory 218392 kb
Host smart-b99d6ce1-8e3b-4627-ab9d-9b73cfd13852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990834110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1990834110
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.597736340
Short name T243
Test name
Test status
Simulation time 244075243 ps
CPU time 1.12 seconds
Started Jun 05 03:53:17 PM PDT 24
Finished Jun 05 03:53:18 PM PDT 24
Peak memory 217936 kb
Host smart-e93e7ce8-9c24-4fbd-9cda-ceeb716479a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597736340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.597736340
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1822298319
Short name T298
Test name
Test status
Simulation time 168488203 ps
CPU time 0.94 seconds
Started Jun 05 03:53:15 PM PDT 24
Finished Jun 05 03:53:16 PM PDT 24
Peak memory 200532 kb
Host smart-8df4c4c4-11f4-4fa1-93fe-e6c1dd495501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822298319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1822298319
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2044691588
Short name T266
Test name
Test status
Simulation time 742693658 ps
CPU time 3.89 seconds
Started Jun 05 03:53:12 PM PDT 24
Finished Jun 05 03:53:16 PM PDT 24
Peak memory 200916 kb
Host smart-ed14c983-240b-4306-97e6-381aa9cc1abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044691588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2044691588
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2585497207
Short name T319
Test name
Test status
Simulation time 108189905 ps
CPU time 1.11 seconds
Started Jun 05 03:53:15 PM PDT 24
Finished Jun 05 03:53:17 PM PDT 24
Peak memory 200736 kb
Host smart-f85c2705-0e0f-4c38-b701-db000d39a8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585497207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2585497207
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3976439834
Short name T338
Test name
Test status
Simulation time 125856954 ps
CPU time 1.19 seconds
Started Jun 05 03:53:12 PM PDT 24
Finished Jun 05 03:53:13 PM PDT 24
Peak memory 200992 kb
Host smart-a46d9bf7-415b-4e57-849e-c316b9d7a8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976439834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3976439834
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.5801891
Short name T541
Test name
Test status
Simulation time 4601230364 ps
CPU time 20.13 seconds
Started Jun 05 03:53:15 PM PDT 24
Finished Jun 05 03:53:35 PM PDT 24
Peak memory 201404 kb
Host smart-354480a4-085f-410c-9187-15aa68afad0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5801891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.5801891
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3490899341
Short name T487
Test name
Test status
Simulation time 154441302 ps
CPU time 1.9 seconds
Started Jun 05 03:53:13 PM PDT 24
Finished Jun 05 03:53:16 PM PDT 24
Peak memory 200772 kb
Host smart-cf97bdf9-06bf-438f-a9c5-a702d582c4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490899341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3490899341
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.1699928315
Short name T496
Test name
Test status
Simulation time 77411395 ps
CPU time 0.77 seconds
Started Jun 05 03:55:00 PM PDT 24
Finished Jun 05 03:55:02 PM PDT 24
Peak memory 200664 kb
Host smart-ba2f6c68-a57d-4427-a9b5-6daada1ca5a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699928315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.1699928315
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.3305888858
Short name T490
Test name
Test status
Simulation time 1221341045 ps
CPU time 5.84 seconds
Started Jun 05 03:54:49 PM PDT 24
Finished Jun 05 03:54:56 PM PDT 24
Peak memory 218680 kb
Host smart-3e2d0e4e-e62e-4450-90f4-d9d11e1b2a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305888858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3305888858
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1533010443
Short name T520
Test name
Test status
Simulation time 244991416 ps
CPU time 1.04 seconds
Started Jun 05 03:54:49 PM PDT 24
Finished Jun 05 03:54:51 PM PDT 24
Peak memory 217964 kb
Host smart-dea82f4f-bd88-4b49-8f54-819687ecdeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533010443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1533010443
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.225053866
Short name T416
Test name
Test status
Simulation time 207791218 ps
CPU time 0.91 seconds
Started Jun 05 03:55:02 PM PDT 24
Finished Jun 05 03:55:04 PM PDT 24
Peak memory 200592 kb
Host smart-e39fc2b8-c812-4425-a279-87fc1f00f90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225053866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.225053866
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2948998938
Short name T286
Test name
Test status
Simulation time 1525075538 ps
CPU time 5.58 seconds
Started Jun 05 03:54:49 PM PDT 24
Finished Jun 05 03:54:56 PM PDT 24
Peak memory 201004 kb
Host smart-1ac802de-7933-43e1-aaa7-50d708983eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948998938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2948998938
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3990090275
Short name T377
Test name
Test status
Simulation time 170163305 ps
CPU time 1.35 seconds
Started Jun 05 03:54:51 PM PDT 24
Finished Jun 05 03:54:54 PM PDT 24
Peak memory 200836 kb
Host smart-35db2398-a06f-4cd9-9aa6-7c1beb35f723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990090275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3990090275
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2188149598
Short name T168
Test name
Test status
Simulation time 118366318 ps
CPU time 1.15 seconds
Started Jun 05 03:54:50 PM PDT 24
Finished Jun 05 03:54:52 PM PDT 24
Peak memory 200876 kb
Host smart-6d0430cb-aba3-4b9a-92bf-33f8d4d948f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188149598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2188149598
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3945001623
Short name T83
Test name
Test status
Simulation time 11978408607 ps
CPU time 42.21 seconds
Started Jun 05 03:54:49 PM PDT 24
Finished Jun 05 03:55:32 PM PDT 24
Peak memory 209340 kb
Host smart-1317c14c-3944-4122-a141-927f543bc6e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945001623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3945001623
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.3530445974
Short name T249
Test name
Test status
Simulation time 266413747 ps
CPU time 1.73 seconds
Started Jun 05 03:54:49 PM PDT 24
Finished Jun 05 03:54:52 PM PDT 24
Peak memory 200772 kb
Host smart-3618ba40-9cf9-4de5-8398-cf68aafec404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530445974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3530445974
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.1003300911
Short name T128
Test name
Test status
Simulation time 156788086 ps
CPU time 1.18 seconds
Started Jun 05 03:54:48 PM PDT 24
Finished Jun 05 03:54:50 PM PDT 24
Peak memory 200816 kb
Host smart-4dad18b6-8236-4fe8-890c-e59c7e0c368b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003300911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.1003300911
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1180412534
Short name T171
Test name
Test status
Simulation time 65403237 ps
CPU time 0.76 seconds
Started Jun 05 03:54:49 PM PDT 24
Finished Jun 05 03:54:51 PM PDT 24
Peak memory 200648 kb
Host smart-241bf960-aefd-4305-a2e2-c37d455525ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180412534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1180412534
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.364089517
Short name T529
Test name
Test status
Simulation time 1218449606 ps
CPU time 6.2 seconds
Started Jun 05 03:55:01 PM PDT 24
Finished Jun 05 03:55:09 PM PDT 24
Peak memory 218468 kb
Host smart-ee4c2f33-1564-4038-91d8-ca59e9de677a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364089517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.364089517
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.409592590
Short name T227
Test name
Test status
Simulation time 244456543 ps
CPU time 1.06 seconds
Started Jun 05 03:54:49 PM PDT 24
Finished Jun 05 03:54:51 PM PDT 24
Peak memory 217928 kb
Host smart-aabb5562-7926-4eac-9942-2a31e5adbf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409592590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.409592590
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1347695226
Short name T195
Test name
Test status
Simulation time 198897669 ps
CPU time 0.94 seconds
Started Jun 05 03:55:06 PM PDT 24
Finished Jun 05 03:55:08 PM PDT 24
Peak memory 200616 kb
Host smart-1b39a789-8215-4913-b9ca-eb60407aef18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347695226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1347695226
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.1906638731
Short name T326
Test name
Test status
Simulation time 926284081 ps
CPU time 4.7 seconds
Started Jun 05 03:54:56 PM PDT 24
Finished Jun 05 03:55:02 PM PDT 24
Peak memory 200936 kb
Host smart-20d8df6b-b133-4451-8c36-f070212a9d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906638731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.1906638731
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1577230130
Short name T514
Test name
Test status
Simulation time 103702444 ps
CPU time 1.04 seconds
Started Jun 05 03:54:56 PM PDT 24
Finished Jun 05 03:54:58 PM PDT 24
Peak memory 200760 kb
Host smart-1042a5d8-aab1-49fc-85e6-848bac095810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577230130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1577230130
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3374253341
Short name T300
Test name
Test status
Simulation time 196198388 ps
CPU time 1.33 seconds
Started Jun 05 03:54:50 PM PDT 24
Finished Jun 05 03:54:52 PM PDT 24
Peak memory 201036 kb
Host smart-48e36862-bab1-4b66-b807-bc0f0792dc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374253341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3374253341
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1217925859
Short name T280
Test name
Test status
Simulation time 2369177738 ps
CPU time 10.64 seconds
Started Jun 05 03:54:52 PM PDT 24
Finished Jun 05 03:55:03 PM PDT 24
Peak memory 201188 kb
Host smart-bf06f501-5dcc-448b-970b-6015a415ceb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217925859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1217925859
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3492341400
Short name T179
Test name
Test status
Simulation time 487372550 ps
CPU time 2.71 seconds
Started Jun 05 03:55:02 PM PDT 24
Finished Jun 05 03:55:06 PM PDT 24
Peak memory 200816 kb
Host smart-959c85c1-a848-4933-bc7d-2147e134d9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492341400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3492341400
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3140073115
Short name T222
Test name
Test status
Simulation time 192359139 ps
CPU time 1.31 seconds
Started Jun 05 03:55:05 PM PDT 24
Finished Jun 05 03:55:07 PM PDT 24
Peak memory 200808 kb
Host smart-7be95743-33dc-4440-9e16-1b821f9ec624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140073115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3140073115
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2580504279
Short name T401
Test name
Test status
Simulation time 55564426 ps
CPU time 0.72 seconds
Started Jun 05 03:54:48 PM PDT 24
Finished Jun 05 03:54:50 PM PDT 24
Peak memory 200656 kb
Host smart-8b764370-80e7-4db9-af3b-2fb6eacabf73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580504279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2580504279
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2609463288
Short name T497
Test name
Test status
Simulation time 2170915318 ps
CPU time 7.31 seconds
Started Jun 05 03:54:49 PM PDT 24
Finished Jun 05 03:54:58 PM PDT 24
Peak memory 222200 kb
Host smart-dcdc9cc1-3c04-42c9-82a5-f1cd2cce90dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609463288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2609463288
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1836911549
Short name T186
Test name
Test status
Simulation time 243868973 ps
CPU time 1.13 seconds
Started Jun 05 03:55:06 PM PDT 24
Finished Jun 05 03:55:08 PM PDT 24
Peak memory 217912 kb
Host smart-292d7992-9a4d-411a-8019-b1b7167d8e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836911549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1836911549
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1028010555
Short name T527
Test name
Test status
Simulation time 178625416 ps
CPU time 0.86 seconds
Started Jun 05 03:54:55 PM PDT 24
Finished Jun 05 03:54:56 PM PDT 24
Peak memory 200584 kb
Host smart-757517fe-ea24-4207-8945-5160a5df4ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028010555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1028010555
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.59081109
Short name T193
Test name
Test status
Simulation time 849253691 ps
CPU time 4.07 seconds
Started Jun 05 03:54:48 PM PDT 24
Finished Jun 05 03:54:54 PM PDT 24
Peak memory 200996 kb
Host smart-8ed0fec8-389e-4cde-a197-040520842496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59081109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.59081109
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1975764861
Short name T230
Test name
Test status
Simulation time 101316946 ps
CPU time 0.99 seconds
Started Jun 05 03:55:05 PM PDT 24
Finished Jun 05 03:55:07 PM PDT 24
Peak memory 200808 kb
Host smart-cc0fd1df-60af-4375-83bd-176fab1d074d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975764861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1975764861
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2517816147
Short name T71
Test name
Test status
Simulation time 192405108 ps
CPU time 1.38 seconds
Started Jun 05 03:54:51 PM PDT 24
Finished Jun 05 03:54:54 PM PDT 24
Peak memory 201056 kb
Host smart-9bfbb016-a66b-4386-82af-834a4a1f334b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517816147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2517816147
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2095452094
Short name T88
Test name
Test status
Simulation time 1983431194 ps
CPU time 8.88 seconds
Started Jun 05 03:54:48 PM PDT 24
Finished Jun 05 03:54:58 PM PDT 24
Peak memory 209388 kb
Host smart-a6b70dd7-7833-4294-b8e5-454b4278d1ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095452094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2095452094
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.579298171
Short name T75
Test name
Test status
Simulation time 111406884 ps
CPU time 1.43 seconds
Started Jun 05 03:54:53 PM PDT 24
Finished Jun 05 03:54:55 PM PDT 24
Peak memory 200724 kb
Host smart-4ad8f03b-8621-4462-a195-3fb5d851a406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579298171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.579298171
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.71443700
Short name T394
Test name
Test status
Simulation time 75954387 ps
CPU time 0.79 seconds
Started Jun 05 03:54:55 PM PDT 24
Finished Jun 05 03:54:57 PM PDT 24
Peak memory 200756 kb
Host smart-099a2fd6-5e42-4049-a114-ba118f6cf142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71443700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.71443700
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.1576363170
Short name T304
Test name
Test status
Simulation time 64191729 ps
CPU time 0.74 seconds
Started Jun 05 03:54:49 PM PDT 24
Finished Jun 05 03:54:51 PM PDT 24
Peak memory 200656 kb
Host smart-a4a63ec1-7455-4074-a57e-42338425e3a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576363170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1576363170
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1953048414
Short name T303
Test name
Test status
Simulation time 244285152 ps
CPU time 1.03 seconds
Started Jun 05 03:54:49 PM PDT 24
Finished Jun 05 03:54:51 PM PDT 24
Peak memory 217936 kb
Host smart-81466e3a-ce2b-4bd6-acbe-0770a334e69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953048414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1953048414
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2375445806
Short name T18
Test name
Test status
Simulation time 178454135 ps
CPU time 0.85 seconds
Started Jun 05 03:54:51 PM PDT 24
Finished Jun 05 03:54:53 PM PDT 24
Peak memory 200640 kb
Host smart-5c32dfef-f19f-4361-9d0c-4121e2941b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375445806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2375445806
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2294359350
Short name T455
Test name
Test status
Simulation time 895741086 ps
CPU time 4.47 seconds
Started Jun 05 03:54:51 PM PDT 24
Finished Jun 05 03:54:57 PM PDT 24
Peak memory 200920 kb
Host smart-b2d52186-d806-4c77-b5cf-d02be8c9dc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294359350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2294359350
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.601046752
Short name T475
Test name
Test status
Simulation time 105040047 ps
CPU time 1 seconds
Started Jun 05 03:54:51 PM PDT 24
Finished Jun 05 03:54:53 PM PDT 24
Peak memory 200820 kb
Host smart-fa5ba73f-516e-424a-bd4a-2427bca2f66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601046752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.601046752
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1678581415
Short name T136
Test name
Test status
Simulation time 198616163 ps
CPU time 1.37 seconds
Started Jun 05 03:54:50 PM PDT 24
Finished Jun 05 03:54:52 PM PDT 24
Peak memory 200996 kb
Host smart-4531e83c-12a5-40f0-b8cf-b7a5a2de5e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678581415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1678581415
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.2739061008
Short name T251
Test name
Test status
Simulation time 5215650894 ps
CPU time 22.56 seconds
Started Jun 05 03:54:52 PM PDT 24
Finished Jun 05 03:55:15 PM PDT 24
Peak memory 201140 kb
Host smart-3afd1b6a-d580-4a74-9fbf-3ebcc62da35f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739061008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2739061008
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1534510716
Short name T482
Test name
Test status
Simulation time 127535131 ps
CPU time 1.68 seconds
Started Jun 05 03:55:02 PM PDT 24
Finished Jun 05 03:55:05 PM PDT 24
Peak memory 200772 kb
Host smart-80fccfa2-e750-45c3-9373-fe634975feff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534510716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1534510716
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3646606772
Short name T150
Test name
Test status
Simulation time 142407351 ps
CPU time 1.19 seconds
Started Jun 05 03:55:06 PM PDT 24
Finished Jun 05 03:55:08 PM PDT 24
Peak memory 200804 kb
Host smart-e64f05ea-5ad1-4e4f-a3a1-260e28965c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646606772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3646606772
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2314911789
Short name T349
Test name
Test status
Simulation time 87155096 ps
CPU time 0.81 seconds
Started Jun 05 03:55:03 PM PDT 24
Finished Jun 05 03:55:05 PM PDT 24
Peak memory 200612 kb
Host smart-62e78014-c875-4cbd-b41d-c33bab86849d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314911789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2314911789
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3035817372
Short name T508
Test name
Test status
Simulation time 2160217925 ps
CPU time 8.09 seconds
Started Jun 05 03:54:59 PM PDT 24
Finished Jun 05 03:55:07 PM PDT 24
Peak memory 218584 kb
Host smart-2531b05d-854c-4536-a8bf-0da49f8b2644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035817372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3035817372
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3625136817
Short name T245
Test name
Test status
Simulation time 243940293 ps
CPU time 1.1 seconds
Started Jun 05 03:55:00 PM PDT 24
Finished Jun 05 03:55:03 PM PDT 24
Peak memory 218028 kb
Host smart-bd06347e-49cf-4233-a71a-46417e601e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625136817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3625136817
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2716567450
Short name T364
Test name
Test status
Simulation time 119997142 ps
CPU time 0.82 seconds
Started Jun 05 03:54:51 PM PDT 24
Finished Jun 05 03:54:53 PM PDT 24
Peak memory 200640 kb
Host smart-99f5bce8-bf02-4528-aed8-0cc68eb7e857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716567450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2716567450
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3389216942
Short name T85
Test name
Test status
Simulation time 808944951 ps
CPU time 4.33 seconds
Started Jun 05 03:55:02 PM PDT 24
Finished Jun 05 03:55:07 PM PDT 24
Peak memory 201000 kb
Host smart-d6dc7f20-09a8-4445-8305-8bd3192ca0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389216942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3389216942
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.337164710
Short name T476
Test name
Test status
Simulation time 107659442 ps
CPU time 1.02 seconds
Started Jun 05 03:55:03 PM PDT 24
Finished Jun 05 03:55:05 PM PDT 24
Peak memory 200808 kb
Host smart-df2656de-c42b-47da-b82d-2ea001d35881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337164710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.337164710
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.4104965626
Short name T151
Test name
Test status
Simulation time 113664974 ps
CPU time 1.15 seconds
Started Jun 05 03:54:52 PM PDT 24
Finished Jun 05 03:54:54 PM PDT 24
Peak memory 200924 kb
Host smart-86e18a16-baa9-4f54-903e-c92131235ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104965626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.4104965626
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2975008650
Short name T184
Test name
Test status
Simulation time 2935062054 ps
CPU time 12.86 seconds
Started Jun 05 03:54:59 PM PDT 24
Finished Jun 05 03:55:13 PM PDT 24
Peak memory 209400 kb
Host smart-da6c70cf-e319-4020-9296-0c861f9553fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975008650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2975008650
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.2680673623
Short name T431
Test name
Test status
Simulation time 333494305 ps
CPU time 2.05 seconds
Started Jun 05 03:55:00 PM PDT 24
Finished Jun 05 03:55:03 PM PDT 24
Peak memory 200800 kb
Host smart-b96cd0c8-76b2-4d34-814a-8f5dbd6fd28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680673623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2680673623
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1054466668
Short name T170
Test name
Test status
Simulation time 105656657 ps
CPU time 0.86 seconds
Started Jun 05 03:54:51 PM PDT 24
Finished Jun 05 03:54:53 PM PDT 24
Peak memory 200816 kb
Host smart-63aa4b12-21b1-4686-acf2-e538360eafdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054466668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1054466668
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.4208332913
Short name T492
Test name
Test status
Simulation time 72867383 ps
CPU time 0.8 seconds
Started Jun 05 03:55:06 PM PDT 24
Finished Jun 05 03:55:07 PM PDT 24
Peak memory 200524 kb
Host smart-43a36d1b-0eda-47ba-856b-99b30f293877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208332913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.4208332913
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2943075358
Short name T49
Test name
Test status
Simulation time 1227541064 ps
CPU time 5.8 seconds
Started Jun 05 03:55:02 PM PDT 24
Finished Jun 05 03:55:09 PM PDT 24
Peak memory 222380 kb
Host smart-50271acb-9075-45d4-b268-0802654ec3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943075358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2943075358
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.169374926
Short name T205
Test name
Test status
Simulation time 244276254 ps
CPU time 1.07 seconds
Started Jun 05 03:54:59 PM PDT 24
Finished Jun 05 03:55:02 PM PDT 24
Peak memory 217968 kb
Host smart-96309d25-1bfc-49b8-8bd1-97fac68204cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169374926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.169374926
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.2631540963
Short name T160
Test name
Test status
Simulation time 192452471 ps
CPU time 0.92 seconds
Started Jun 05 03:54:59 PM PDT 24
Finished Jun 05 03:55:02 PM PDT 24
Peak memory 200880 kb
Host smart-28b1f0b1-fe48-4ca5-bdc9-008274356c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631540963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2631540963
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1224115214
Short name T87
Test name
Test status
Simulation time 736242560 ps
CPU time 3.78 seconds
Started Jun 05 03:55:02 PM PDT 24
Finished Jun 05 03:55:07 PM PDT 24
Peak memory 200976 kb
Host smart-87bce504-d29c-46c2-b424-3e183f6ba8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224115214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1224115214
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1863133937
Short name T337
Test name
Test status
Simulation time 109733327 ps
CPU time 1.02 seconds
Started Jun 05 03:55:00 PM PDT 24
Finished Jun 05 03:55:02 PM PDT 24
Peak memory 200812 kb
Host smart-d07f8aed-d27d-46a4-b681-67b9139e8480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863133937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1863133937
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3566970813
Short name T343
Test name
Test status
Simulation time 111647662 ps
CPU time 1.21 seconds
Started Jun 05 03:55:03 PM PDT 24
Finished Jun 05 03:55:05 PM PDT 24
Peak memory 200964 kb
Host smart-119c8480-b042-4307-9fda-37e615a98555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566970813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3566970813
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.2137572240
Short name T111
Test name
Test status
Simulation time 14402987917 ps
CPU time 48.12 seconds
Started Jun 05 03:54:59 PM PDT 24
Finished Jun 05 03:55:48 PM PDT 24
Peak memory 201164 kb
Host smart-40682524-a03a-47e9-a435-9eb1fe410d6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137572240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2137572240
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3727297355
Short name T117
Test name
Test status
Simulation time 510369739 ps
CPU time 2.9 seconds
Started Jun 05 03:54:59 PM PDT 24
Finished Jun 05 03:55:03 PM PDT 24
Peak memory 200800 kb
Host smart-6914908c-1568-4b51-824d-26ffc0f71683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727297355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3727297355
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.506389430
Short name T402
Test name
Test status
Simulation time 227572239 ps
CPU time 1.37 seconds
Started Jun 05 03:54:59 PM PDT 24
Finished Jun 05 03:55:02 PM PDT 24
Peak memory 201044 kb
Host smart-61237cd6-09d9-477e-abbc-fa950e810bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506389430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.506389430
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2206666625
Short name T367
Test name
Test status
Simulation time 72331826 ps
CPU time 0.84 seconds
Started Jun 05 03:54:59 PM PDT 24
Finished Jun 05 03:55:01 PM PDT 24
Peak memory 200652 kb
Host smart-0aad895e-5327-4b92-9981-85919d2e1ffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206666625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2206666625
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.748355659
Short name T275
Test name
Test status
Simulation time 1225491503 ps
CPU time 5.48 seconds
Started Jun 05 03:54:58 PM PDT 24
Finished Jun 05 03:55:04 PM PDT 24
Peak memory 222508 kb
Host smart-f1f4ab8b-a3ee-4b9d-978a-402f68dd6466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748355659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.748355659
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2104229032
Short name T421
Test name
Test status
Simulation time 245409941 ps
CPU time 1.14 seconds
Started Jun 05 03:55:02 PM PDT 24
Finished Jun 05 03:55:04 PM PDT 24
Peak memory 217968 kb
Host smart-83fab441-d6a2-4d41-a98d-e00380568d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104229032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2104229032
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3074696620
Short name T22
Test name
Test status
Simulation time 180493853 ps
CPU time 0.9 seconds
Started Jun 05 03:54:58 PM PDT 24
Finished Jun 05 03:55:00 PM PDT 24
Peak memory 200644 kb
Host smart-6b7e1455-96ca-4e12-b134-e218b9977a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074696620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3074696620
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.823471340
Short name T301
Test name
Test status
Simulation time 1340581106 ps
CPU time 4.84 seconds
Started Jun 05 03:55:01 PM PDT 24
Finished Jun 05 03:55:07 PM PDT 24
Peak memory 200992 kb
Host smart-5a21a569-7173-4c39-8d9b-363573c9dddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823471340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.823471340
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1513601718
Short name T131
Test name
Test status
Simulation time 161820421 ps
CPU time 1.15 seconds
Started Jun 05 03:55:00 PM PDT 24
Finished Jun 05 03:55:02 PM PDT 24
Peak memory 200816 kb
Host smart-1e05bdc5-a5ac-4364-a635-f2e894270e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513601718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1513601718
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.2300317040
Short name T388
Test name
Test status
Simulation time 237329144 ps
CPU time 1.55 seconds
Started Jun 05 03:54:57 PM PDT 24
Finished Jun 05 03:55:00 PM PDT 24
Peak memory 201032 kb
Host smart-e20d2722-5a3e-4914-9d5c-a948b2637271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300317040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2300317040
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3589065159
Short name T109
Test name
Test status
Simulation time 8978148729 ps
CPU time 31.93 seconds
Started Jun 05 03:54:58 PM PDT 24
Finished Jun 05 03:55:31 PM PDT 24
Peak memory 209340 kb
Host smart-6681c274-f969-4cfb-80d1-7c8413b9c40b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589065159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3589065159
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.429842666
Short name T191
Test name
Test status
Simulation time 143647959 ps
CPU time 1.92 seconds
Started Jun 05 03:54:59 PM PDT 24
Finished Jun 05 03:55:03 PM PDT 24
Peak memory 200780 kb
Host smart-4dfe637e-4be0-4cd0-bdf5-55f8d234443e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429842666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.429842666
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.4115133037
Short name T379
Test name
Test status
Simulation time 165206281 ps
CPU time 1.35 seconds
Started Jun 05 03:54:59 PM PDT 24
Finished Jun 05 03:55:01 PM PDT 24
Peak memory 200992 kb
Host smart-ac3ec838-faf4-434c-879a-48bb4f38b321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115133037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.4115133037
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3101586386
Short name T65
Test name
Test status
Simulation time 73445221 ps
CPU time 0.78 seconds
Started Jun 05 03:55:00 PM PDT 24
Finished Jun 05 03:55:02 PM PDT 24
Peak memory 200576 kb
Host smart-d63aebeb-0735-4c2a-9e21-4909d216ba40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101586386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3101586386
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.4162368654
Short name T50
Test name
Test status
Simulation time 2149877666 ps
CPU time 7.24 seconds
Started Jun 05 03:54:59 PM PDT 24
Finished Jun 05 03:55:08 PM PDT 24
Peak memory 218588 kb
Host smart-80f2834c-4323-4f35-91a0-7f39c8165589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162368654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.4162368654
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3918037846
Short name T140
Test name
Test status
Simulation time 244357962 ps
CPU time 1.04 seconds
Started Jun 05 03:54:57 PM PDT 24
Finished Jun 05 03:55:00 PM PDT 24
Peak memory 217952 kb
Host smart-a075920b-d67e-49f2-aa93-d952597f7e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918037846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3918037846
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.4037791665
Short name T23
Test name
Test status
Simulation time 158902394 ps
CPU time 1.01 seconds
Started Jun 05 03:54:59 PM PDT 24
Finished Jun 05 03:55:01 PM PDT 24
Peak memory 200596 kb
Host smart-7b9683d2-d0e5-4a3a-aaaa-4c2ca1330eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037791665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.4037791665
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.4274227564
Short name T509
Test name
Test status
Simulation time 840948736 ps
CPU time 4.38 seconds
Started Jun 05 03:54:58 PM PDT 24
Finished Jun 05 03:55:03 PM PDT 24
Peak memory 201004 kb
Host smart-1f61e239-86c3-4f40-84a6-119d62a621a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274227564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.4274227564
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1662195407
Short name T420
Test name
Test status
Simulation time 106398001 ps
CPU time 0.97 seconds
Started Jun 05 03:55:02 PM PDT 24
Finished Jun 05 03:55:04 PM PDT 24
Peak memory 200812 kb
Host smart-32237ac2-1d90-4284-b6ae-4c3c429a6d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662195407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1662195407
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.3625141089
Short name T176
Test name
Test status
Simulation time 202658674 ps
CPU time 1.38 seconds
Started Jun 05 03:55:06 PM PDT 24
Finished Jun 05 03:55:08 PM PDT 24
Peak memory 200992 kb
Host smart-fbe12063-d079-4b33-a5d0-0f3652ecbc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625141089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3625141089
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2751835143
Short name T505
Test name
Test status
Simulation time 5101455360 ps
CPU time 23.31 seconds
Started Jun 05 03:55:03 PM PDT 24
Finished Jun 05 03:55:27 PM PDT 24
Peak memory 201108 kb
Host smart-293c5b50-884f-4317-b524-a59bf28ae4c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751835143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2751835143
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2081602502
Short name T255
Test name
Test status
Simulation time 359902707 ps
CPU time 2.48 seconds
Started Jun 05 03:54:59 PM PDT 24
Finished Jun 05 03:55:03 PM PDT 24
Peak memory 200820 kb
Host smart-04a777fb-02b6-463b-914c-3df0316674d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081602502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2081602502
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3616401395
Short name T453
Test name
Test status
Simulation time 123405335 ps
CPU time 0.97 seconds
Started Jun 05 03:54:57 PM PDT 24
Finished Jun 05 03:54:59 PM PDT 24
Peak memory 200796 kb
Host smart-353f5aa0-28cc-411f-97bd-eac858186138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616401395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3616401395
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.1733594451
Short name T180
Test name
Test status
Simulation time 90077359 ps
CPU time 0.87 seconds
Started Jun 05 03:54:59 PM PDT 24
Finished Jun 05 03:55:01 PM PDT 24
Peak memory 200668 kb
Host smart-28597591-ccb5-4ec4-8c12-e06150f04524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733594451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1733594451
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1311518122
Short name T287
Test name
Test status
Simulation time 1219172217 ps
CPU time 5.36 seconds
Started Jun 05 03:54:56 PM PDT 24
Finished Jun 05 03:55:02 PM PDT 24
Peak memory 222504 kb
Host smart-bd615dcd-2879-4ceb-82d3-a75ad999aad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311518122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1311518122
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3335470444
Short name T31
Test name
Test status
Simulation time 245064499 ps
CPU time 1.05 seconds
Started Jun 05 03:54:58 PM PDT 24
Finished Jun 05 03:55:00 PM PDT 24
Peak memory 218124 kb
Host smart-a13f677c-b926-4e0f-bd94-136b02517ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335470444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3335470444
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3469648601
Short name T318
Test name
Test status
Simulation time 75818578 ps
CPU time 0.72 seconds
Started Jun 05 03:55:02 PM PDT 24
Finished Jun 05 03:55:04 PM PDT 24
Peak memory 200640 kb
Host smart-bb10b377-67af-46e1-a6a7-2fe44d66f42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469648601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3469648601
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1925538066
Short name T485
Test name
Test status
Simulation time 1943133025 ps
CPU time 8.2 seconds
Started Jun 05 03:55:00 PM PDT 24
Finished Jun 05 03:55:10 PM PDT 24
Peak memory 200880 kb
Host smart-5ee6b0f2-9203-43bf-8048-8260ec4b4a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925538066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1925538066
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.4223222289
Short name T201
Test name
Test status
Simulation time 182369364 ps
CPU time 1.26 seconds
Started Jun 05 03:55:00 PM PDT 24
Finished Jun 05 03:55:02 PM PDT 24
Peak memory 200828 kb
Host smart-a3cd6970-ee30-418c-be11-03b85071d8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223222289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.4223222289
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1433300735
Short name T488
Test name
Test status
Simulation time 125106980 ps
CPU time 1.17 seconds
Started Jun 05 03:55:00 PM PDT 24
Finished Jun 05 03:55:02 PM PDT 24
Peak memory 200988 kb
Host smart-a4ebaa97-1e6f-4d71-9f54-a81fe0e66d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433300735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1433300735
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1427452930
Short name T112
Test name
Test status
Simulation time 11495667601 ps
CPU time 43.08 seconds
Started Jun 05 03:55:00 PM PDT 24
Finished Jun 05 03:55:45 PM PDT 24
Peak memory 201144 kb
Host smart-9626fc4e-0cc1-4d0f-b321-646f3c15abd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427452930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1427452930
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.198272042
Short name T299
Test name
Test status
Simulation time 133361218 ps
CPU time 1.8 seconds
Started Jun 05 03:54:58 PM PDT 24
Finished Jun 05 03:55:00 PM PDT 24
Peak memory 209004 kb
Host smart-9356f8b7-ae4e-45cc-b02b-e5c75e0fffd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198272042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.198272042
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2023089725
Short name T322
Test name
Test status
Simulation time 89401579 ps
CPU time 0.88 seconds
Started Jun 05 03:54:57 PM PDT 24
Finished Jun 05 03:54:59 PM PDT 24
Peak memory 200728 kb
Host smart-70bfc2b8-5748-400a-a41b-6ec97ac22dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023089725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2023089725
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.3435975140
Short name T197
Test name
Test status
Simulation time 76410733 ps
CPU time 0.81 seconds
Started Jun 05 03:55:07 PM PDT 24
Finished Jun 05 03:55:09 PM PDT 24
Peak memory 200644 kb
Host smart-f03f21d0-4561-4255-a9df-954ddce5a2a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435975140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3435975140
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3767549731
Short name T51
Test name
Test status
Simulation time 1233546945 ps
CPU time 6.19 seconds
Started Jun 05 03:55:05 PM PDT 24
Finished Jun 05 03:55:12 PM PDT 24
Peak memory 217860 kb
Host smart-2c36b670-0517-4d58-aa6f-ff25eff89113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767549731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3767549731
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.820380492
Short name T53
Test name
Test status
Simulation time 243698995 ps
CPU time 1.16 seconds
Started Jun 05 03:55:12 PM PDT 24
Finished Jun 05 03:55:14 PM PDT 24
Peak memory 217924 kb
Host smart-0f85f6d9-3d62-4902-bd5b-33f4b3fe0649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820380492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.820380492
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.3468717943
Short name T372
Test name
Test status
Simulation time 91447277 ps
CPU time 0.76 seconds
Started Jun 05 03:55:01 PM PDT 24
Finished Jun 05 03:55:03 PM PDT 24
Peak memory 200636 kb
Host smart-91875756-f505-44ae-903a-538441b90ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468717943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3468717943
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.1942321580
Short name T84
Test name
Test status
Simulation time 928406439 ps
CPU time 5.26 seconds
Started Jun 05 03:55:08 PM PDT 24
Finished Jun 05 03:55:14 PM PDT 24
Peak memory 200980 kb
Host smart-83f551ad-8b9e-4579-af00-ed5aae61e355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942321580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1942321580
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2605738667
Short name T459
Test name
Test status
Simulation time 137779945 ps
CPU time 1.14 seconds
Started Jun 05 03:55:08 PM PDT 24
Finished Jun 05 03:55:10 PM PDT 24
Peak memory 200816 kb
Host smart-7c7a59c3-0e56-41e3-8fdf-875f2d94bf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605738667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2605738667
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3625051462
Short name T118
Test name
Test status
Simulation time 250485600 ps
CPU time 1.52 seconds
Started Jun 05 03:55:01 PM PDT 24
Finished Jun 05 03:55:04 PM PDT 24
Peak memory 201016 kb
Host smart-8813fa26-21bf-47d0-988e-be03edf731e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625051462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3625051462
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1567364639
Short name T472
Test name
Test status
Simulation time 7354667512 ps
CPU time 34.45 seconds
Started Jun 05 03:55:05 PM PDT 24
Finished Jun 05 03:55:41 PM PDT 24
Peak memory 201156 kb
Host smart-fbbd098b-6e0c-470e-8faf-12eb34e5b8f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567364639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1567364639
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3080109299
Short name T229
Test name
Test status
Simulation time 142916818 ps
CPU time 1.89 seconds
Started Jun 05 03:55:06 PM PDT 24
Finished Jun 05 03:55:09 PM PDT 24
Peak memory 201076 kb
Host smart-f15d4617-e6ee-47a7-a0d7-64906536123c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080109299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3080109299
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3212859664
Short name T325
Test name
Test status
Simulation time 239955943 ps
CPU time 1.37 seconds
Started Jun 05 03:55:15 PM PDT 24
Finished Jun 05 03:55:18 PM PDT 24
Peak memory 200804 kb
Host smart-2c4ae1f6-6bab-4405-90d4-254a8f90fa1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212859664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3212859664
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1232956932
Short name T185
Test name
Test status
Simulation time 72323694 ps
CPU time 0.79 seconds
Started Jun 05 03:53:23 PM PDT 24
Finished Jun 05 03:53:25 PM PDT 24
Peak memory 200572 kb
Host smart-feb5a6b7-9ce8-4fea-9727-2b862d08614c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232956932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1232956932
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.4000942784
Short name T38
Test name
Test status
Simulation time 2356418469 ps
CPU time 8.64 seconds
Started Jun 05 03:53:24 PM PDT 24
Finished Jun 05 03:53:33 PM PDT 24
Peak memory 218484 kb
Host smart-af6dfa49-e3b2-4f8a-9b2e-d101ac10ab6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000942784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.4000942784
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1512484626
Short name T330
Test name
Test status
Simulation time 243526092 ps
CPU time 1.01 seconds
Started Jun 05 03:53:21 PM PDT 24
Finished Jun 05 03:53:23 PM PDT 24
Peak memory 218020 kb
Host smart-bf705cff-f587-45cd-9a05-176a90d5ec14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512484626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1512484626
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3044060961
Short name T26
Test name
Test status
Simulation time 179748175 ps
CPU time 0.85 seconds
Started Jun 05 03:53:12 PM PDT 24
Finished Jun 05 03:53:14 PM PDT 24
Peak memory 200624 kb
Host smart-a33239f7-f91b-4404-a9f7-03da2fda54e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044060961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3044060961
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.3649309782
Short name T215
Test name
Test status
Simulation time 1531797044 ps
CPU time 5.86 seconds
Started Jun 05 03:53:12 PM PDT 24
Finished Jun 05 03:53:18 PM PDT 24
Peak memory 200940 kb
Host smart-95df96ba-0921-4497-afbd-d6d868f50b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649309782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3649309782
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1910372435
Short name T27
Test name
Test status
Simulation time 108156711 ps
CPU time 1 seconds
Started Jun 05 03:53:22 PM PDT 24
Finished Jun 05 03:53:24 PM PDT 24
Peak memory 200736 kb
Host smart-57e07e1d-56a7-41b1-9e99-bee063a1b6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910372435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1910372435
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.949946896
Short name T190
Test name
Test status
Simulation time 194287561 ps
CPU time 1.31 seconds
Started Jun 05 03:53:13 PM PDT 24
Finished Jun 05 03:53:15 PM PDT 24
Peak memory 201056 kb
Host smart-459c4793-d11f-44fe-93a5-4aab23a59a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949946896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.949946896
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.239139562
Short name T214
Test name
Test status
Simulation time 11415298009 ps
CPU time 40.16 seconds
Started Jun 05 03:53:25 PM PDT 24
Finished Jun 05 03:54:06 PM PDT 24
Peak memory 201312 kb
Host smart-022a1a56-04a2-43d5-b699-40e9556d7e1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239139562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.239139562
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.4226004903
Short name T395
Test name
Test status
Simulation time 134982896 ps
CPU time 1.69 seconds
Started Jun 05 03:53:19 PM PDT 24
Finished Jun 05 03:53:22 PM PDT 24
Peak memory 200796 kb
Host smart-e725f168-e49e-49a8-8c2a-440d972338e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226004903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.4226004903
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2996332338
Short name T11
Test name
Test status
Simulation time 102654063 ps
CPU time 0.86 seconds
Started Jun 05 03:53:20 PM PDT 24
Finished Jun 05 03:53:21 PM PDT 24
Peak memory 200828 kb
Host smart-34cff4bb-6edf-4147-9561-58379e2f5478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996332338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2996332338
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2018627250
Short name T29
Test name
Test status
Simulation time 104123531 ps
CPU time 0.87 seconds
Started Jun 05 03:53:30 PM PDT 24
Finished Jun 05 03:53:31 PM PDT 24
Peak memory 200572 kb
Host smart-b122fe56-7849-474a-8f63-02af8a333357
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018627250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2018627250
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.891839668
Short name T526
Test name
Test status
Simulation time 2383085809 ps
CPU time 8.31 seconds
Started Jun 05 03:53:21 PM PDT 24
Finished Jun 05 03:53:30 PM PDT 24
Peak memory 222596 kb
Host smart-ed361c3d-6312-403d-8766-5dde400875c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891839668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.891839668
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.563606758
Short name T262
Test name
Test status
Simulation time 244859217 ps
CPU time 1.1 seconds
Started Jun 05 03:53:21 PM PDT 24
Finished Jun 05 03:53:23 PM PDT 24
Peak memory 217952 kb
Host smart-a105623e-71d8-45f9-a492-ad769b3567fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563606758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.563606758
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1317876472
Short name T365
Test name
Test status
Simulation time 132203427 ps
CPU time 0.78 seconds
Started Jun 05 03:53:25 PM PDT 24
Finished Jun 05 03:53:26 PM PDT 24
Peak memory 200624 kb
Host smart-d42a0838-e98f-4b4f-abd8-abf86031d5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317876472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1317876472
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1536709496
Short name T498
Test name
Test status
Simulation time 1398034435 ps
CPU time 5.41 seconds
Started Jun 05 03:53:21 PM PDT 24
Finished Jun 05 03:53:27 PM PDT 24
Peak memory 200988 kb
Host smart-1bda8b86-0c5c-4231-92ec-4ae9a0e07587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536709496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1536709496
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1777293093
Short name T283
Test name
Test status
Simulation time 152284909 ps
CPU time 1.16 seconds
Started Jun 05 03:53:25 PM PDT 24
Finished Jun 05 03:53:26 PM PDT 24
Peak memory 200744 kb
Host smart-840f9a4e-4100-4d9b-965f-12fd454a2fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777293093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1777293093
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.764722555
Short name T502
Test name
Test status
Simulation time 129030631 ps
CPU time 1.2 seconds
Started Jun 05 03:53:23 PM PDT 24
Finished Jun 05 03:53:24 PM PDT 24
Peak memory 200988 kb
Host smart-804d0ec6-7a8f-469f-bfdf-fd759fe2c9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764722555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.764722555
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1896880247
Short name T361
Test name
Test status
Simulation time 6455413009 ps
CPU time 23.63 seconds
Started Jun 05 03:53:28 PM PDT 24
Finished Jun 05 03:53:53 PM PDT 24
Peak memory 201032 kb
Host smart-c73c9287-258d-4c70-bed8-15af8ae6d323
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896880247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1896880247
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.267327848
Short name T248
Test name
Test status
Simulation time 120281444 ps
CPU time 1.51 seconds
Started Jun 05 03:53:25 PM PDT 24
Finished Jun 05 03:53:27 PM PDT 24
Peak memory 201000 kb
Host smart-fb90b4a6-591d-4ab9-8abd-f7abd534c8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267327848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.267327848
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3762291823
Short name T183
Test name
Test status
Simulation time 138731813 ps
CPU time 1.15 seconds
Started Jun 05 03:53:21 PM PDT 24
Finished Jun 05 03:53:23 PM PDT 24
Peak memory 200752 kb
Host smart-387e4abc-08b7-4d4f-95f4-b22e08c06da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762291823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3762291823
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.4101198251
Short name T317
Test name
Test status
Simulation time 57449319 ps
CPU time 0.72 seconds
Started Jun 05 03:53:30 PM PDT 24
Finished Jun 05 03:53:32 PM PDT 24
Peak memory 200592 kb
Host smart-19f6a09d-55e2-49a2-85fa-be90d500ce35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101198251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.4101198251
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.439552893
Short name T380
Test name
Test status
Simulation time 1901836457 ps
CPU time 7.54 seconds
Started Jun 05 03:53:31 PM PDT 24
Finished Jun 05 03:53:39 PM PDT 24
Peak memory 217424 kb
Host smart-9f9d599b-0f26-434c-a36f-7d529e0de7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439552893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.439552893
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.4153829948
Short name T221
Test name
Test status
Simulation time 244281762 ps
CPU time 1.06 seconds
Started Jun 05 03:53:29 PM PDT 24
Finished Jun 05 03:53:31 PM PDT 24
Peak memory 218100 kb
Host smart-07d14098-0b5a-4352-9686-33fd421ba632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153829948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.4153829948
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.414836389
Short name T196
Test name
Test status
Simulation time 203776332 ps
CPU time 0.85 seconds
Started Jun 05 03:53:30 PM PDT 24
Finished Jun 05 03:53:32 PM PDT 24
Peak memory 200528 kb
Host smart-649fa356-d342-4d66-b703-7c4480f47c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414836389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.414836389
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.2124738104
Short name T405
Test name
Test status
Simulation time 1820388661 ps
CPU time 6.96 seconds
Started Jun 05 03:53:29 PM PDT 24
Finished Jun 05 03:53:37 PM PDT 24
Peak memory 200976 kb
Host smart-7be5d5cd-7b64-47da-b734-6edc6ae06ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124738104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2124738104
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.360978181
Short name T308
Test name
Test status
Simulation time 159608761 ps
CPU time 1.17 seconds
Started Jun 05 03:53:30 PM PDT 24
Finished Jun 05 03:53:32 PM PDT 24
Peak memory 200836 kb
Host smart-f33bcfb4-3a62-479c-b02b-1ac91ee5d0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360978181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.360978181
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2734265089
Short name T135
Test name
Test status
Simulation time 116833321 ps
CPU time 1.17 seconds
Started Jun 05 03:53:33 PM PDT 24
Finished Jun 05 03:53:34 PM PDT 24
Peak memory 200900 kb
Host smart-34ce2159-154e-409b-9c62-cf0779dc8104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734265089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2734265089
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.758673237
Short name T383
Test name
Test status
Simulation time 7272469898 ps
CPU time 24.24 seconds
Started Jun 05 03:53:28 PM PDT 24
Finished Jun 05 03:53:53 PM PDT 24
Peak memory 209272 kb
Host smart-ff4bb6cb-f1ed-4fce-8d79-80a60a4f2ec5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758673237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.758673237
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.2479983849
Short name T489
Test name
Test status
Simulation time 484539280 ps
CPU time 2.7 seconds
Started Jun 05 03:53:30 PM PDT 24
Finished Jun 05 03:53:34 PM PDT 24
Peak memory 200800 kb
Host smart-98dfa91b-9ed0-452c-a8f5-42ec11611f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479983849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2479983849
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2561881197
Short name T477
Test name
Test status
Simulation time 158026578 ps
CPU time 1.18 seconds
Started Jun 05 03:53:31 PM PDT 24
Finished Jun 05 03:53:33 PM PDT 24
Peak memory 200928 kb
Host smart-71322b44-fd57-4b59-b516-90089fa23c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561881197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2561881197
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.865969119
Short name T164
Test name
Test status
Simulation time 66117228 ps
CPU time 0.78 seconds
Started Jun 05 03:53:37 PM PDT 24
Finished Jun 05 03:53:38 PM PDT 24
Peak memory 200576 kb
Host smart-838750e6-5468-40b8-a119-aca714d1a569
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865969119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.865969119
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1463307236
Short name T412
Test name
Test status
Simulation time 1229701045 ps
CPU time 5.36 seconds
Started Jun 05 03:53:37 PM PDT 24
Finished Jun 05 03:53:43 PM PDT 24
Peak memory 222488 kb
Host smart-df5f8ef5-b855-4f9c-81e9-988418ea0c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463307236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1463307236
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.4098349312
Short name T149
Test name
Test status
Simulation time 244206062 ps
CPU time 1.12 seconds
Started Jun 05 03:53:44 PM PDT 24
Finished Jun 05 03:53:46 PM PDT 24
Peak memory 217844 kb
Host smart-539feb22-9b9e-40f7-9855-8eaa455eca45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098349312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.4098349312
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.381590367
Short name T24
Test name
Test status
Simulation time 118826158 ps
CPU time 0.86 seconds
Started Jun 05 03:53:30 PM PDT 24
Finished Jun 05 03:53:31 PM PDT 24
Peak memory 200536 kb
Host smart-0974455f-6eb2-4c0b-a98c-e694852326dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381590367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.381590367
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3241285662
Short name T252
Test name
Test status
Simulation time 1543159373 ps
CPU time 5.78 seconds
Started Jun 05 03:53:30 PM PDT 24
Finished Jun 05 03:53:37 PM PDT 24
Peak memory 200992 kb
Host smart-e17d4d65-240a-4abc-8793-450509103f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241285662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3241285662
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2995739814
Short name T173
Test name
Test status
Simulation time 141954217 ps
CPU time 1.06 seconds
Started Jun 05 03:53:44 PM PDT 24
Finished Jun 05 03:53:46 PM PDT 24
Peak memory 200736 kb
Host smart-cfd0cda1-0c09-4146-98de-322ffbaebb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995739814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2995739814
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.4121743058
Short name T224
Test name
Test status
Simulation time 124403789 ps
CPU time 1.15 seconds
Started Jun 05 03:53:30 PM PDT 24
Finished Jun 05 03:53:31 PM PDT 24
Peak memory 200900 kb
Host smart-0de78c25-b571-46d8-97b5-42fc9cba4599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121743058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.4121743058
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2506474043
Short name T240
Test name
Test status
Simulation time 14727571807 ps
CPU time 47.54 seconds
Started Jun 05 03:53:38 PM PDT 24
Finished Jun 05 03:54:26 PM PDT 24
Peak memory 209316 kb
Host smart-8a879435-a3e9-4ae3-92d1-6e0c074bc566
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506474043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2506474043
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.983843980
Short name T264
Test name
Test status
Simulation time 145068655 ps
CPU time 1.81 seconds
Started Jun 05 03:53:30 PM PDT 24
Finished Jun 05 03:53:32 PM PDT 24
Peak memory 200800 kb
Host smart-0271774f-d8de-4076-8d50-eb2f776acfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983843980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.983843980
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.413504557
Short name T113
Test name
Test status
Simulation time 267988781 ps
CPU time 1.42 seconds
Started Jun 05 03:53:33 PM PDT 24
Finished Jun 05 03:53:35 PM PDT 24
Peak memory 200712 kb
Host smart-2ab2ed95-1dfb-48e6-9157-5af359d75f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413504557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.413504557
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2202031476
Short name T466
Test name
Test status
Simulation time 75743613 ps
CPU time 0.75 seconds
Started Jun 05 03:53:45 PM PDT 24
Finished Jun 05 03:53:47 PM PDT 24
Peak memory 200612 kb
Host smart-97af4fc8-fdc4-483b-948c-c2780feb6d13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202031476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2202031476
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.3312458868
Short name T516
Test name
Test status
Simulation time 1889052498 ps
CPU time 7.05 seconds
Started Jun 05 03:53:38 PM PDT 24
Finished Jun 05 03:53:46 PM PDT 24
Peak memory 217848 kb
Host smart-02ac7a05-e919-4d13-9100-94af6a32a7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312458868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3312458868
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.4014601781
Short name T206
Test name
Test status
Simulation time 245901977 ps
CPU time 1.02 seconds
Started Jun 05 03:53:40 PM PDT 24
Finished Jun 05 03:53:41 PM PDT 24
Peak memory 217888 kb
Host smart-31471880-e433-4642-9116-23d8258be82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014601781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.4014601781
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1458853165
Short name T538
Test name
Test status
Simulation time 142622919 ps
CPU time 0.84 seconds
Started Jun 05 03:53:49 PM PDT 24
Finished Jun 05 03:53:51 PM PDT 24
Peak memory 200536 kb
Host smart-5de410b8-4029-469b-80c4-cf9807708127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458853165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1458853165
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.2579391729
Short name T356
Test name
Test status
Simulation time 1406618285 ps
CPU time 5.62 seconds
Started Jun 05 03:53:49 PM PDT 24
Finished Jun 05 03:53:55 PM PDT 24
Peak memory 200912 kb
Host smart-2eca0424-8128-43e7-96db-2df324ba1913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579391729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2579391729
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.25971376
Short name T145
Test name
Test status
Simulation time 108369950 ps
CPU time 0.96 seconds
Started Jun 05 03:53:48 PM PDT 24
Finished Jun 05 03:53:50 PM PDT 24
Peak memory 200732 kb
Host smart-3d6a8863-f3ef-4150-a6e0-d59966d4caa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25971376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.25971376
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1489688519
Short name T139
Test name
Test status
Simulation time 119817976 ps
CPU time 1.21 seconds
Started Jun 05 03:53:49 PM PDT 24
Finished Jun 05 03:53:51 PM PDT 24
Peak memory 200908 kb
Host smart-ae0704c6-91d5-4c9e-a3d1-4543bca5d0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489688519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1489688519
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.299771699
Short name T12
Test name
Test status
Simulation time 102606249 ps
CPU time 0.83 seconds
Started Jun 05 03:53:38 PM PDT 24
Finished Jun 05 03:53:39 PM PDT 24
Peak memory 200636 kb
Host smart-354e45a5-b3bc-46c6-8881-8fcb96a39c8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299771699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.299771699
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.944954095
Short name T76
Test name
Test status
Simulation time 155664347 ps
CPU time 1 seconds
Started Jun 05 03:53:45 PM PDT 24
Finished Jun 05 03:53:47 PM PDT 24
Peak memory 200768 kb
Host smart-4768c911-ddcf-4185-8bb6-b545627937f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944954095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.944954095
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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