Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8056

1

T5

17

T7

26

T10

4

auto[1]

11021

1

T2

4

T4

4

T5

84

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5916	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6451	1			T1	1		T2	2		T3	1
reset_info_cp[2]	2935	1			T2	1		T4	1		T5	16
reset_info_cp[4]	3856	1			T2	1		T4	1		T5	18
reset_info_cp[8]	114	1			T6	1		T7	1		T11	3
reset_info_cp[16]	106	1			T10	1		T12	1		T81	1
reset_info_cp[32]	94	1			T12	2		T81	1		T48	1
reset_info_cp[64]	109	1			T11	2		T12	1		T81	1
reset_info_cp[128]	116	1			T5	1		T11	1		T81	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3091	1			T5	17		T7	6		T12	28
reset_info_cp[1]	auto[1]	2740	1			T2	1		T4	1		T5	9
reset_info_cp[2]	auto[0]	887	1			T7	5		T12	13		T13	5
reset_info_cp[2]	auto[1]	2048	1			T2	1		T4	1		T5	16
reset_info_cp[4]	auto[0]	1327	1			T7	4		T12	13		T13	9
reset_info_cp[4]	auto[1]	2529	1			T2	1		T4	1		T5	18
reset_info_cp[8]	auto[0]	50	1			T7	1		T11	3		T81	1
reset_info_cp[8]	auto[1]	64	1			T6	1		T50	2		T27	1
reset_info_cp[16]	auto[0]	42	1			T10	1		T81	1		T50	1
reset_info_cp[16]	auto[1]	64	1			T12	1		T94	2		T95	1
reset_info_cp[32]	auto[0]	42	1			T12	1		T81	1		T50	1
reset_info_cp[32]	auto[1]	52	1			T12	1		T48	1		T27	1
reset_info_cp[64]	auto[0]	41	1			T11	2		T81	1		T50	1
reset_info_cp[64]	auto[1]	68	1			T12	1		T50	1		T101	1
reset_info_cp[128]	auto[0]	45	1			T11	1		T81	1		T49	1
reset_info_cp[128]	auto[1]	71	1			T5	1		T48	1		T50	1