Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T534 /workspace/coverage/default/33.rstmgr_stress_all.789880527 Jun 06 12:29:22 PM PDT 24 Jun 06 12:29:40 PM PDT 24 4342226184 ps
T535 /workspace/coverage/default/24.rstmgr_por_stretcher.1772248240 Jun 06 12:29:12 PM PDT 24 Jun 06 12:29:15 PM PDT 24 75288159 ps
T536 /workspace/coverage/default/10.rstmgr_alert_test.3791233533 Jun 06 12:28:45 PM PDT 24 Jun 06 12:28:47 PM PDT 24 71620709 ps
T537 /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1905793767 Jun 06 12:29:27 PM PDT 24 Jun 06 12:29:30 PM PDT 24 76329028 ps
T538 /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.107228144 Jun 06 12:28:54 PM PDT 24 Jun 06 12:29:04 PM PDT 24 2345005984 ps
T62 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4092774194 Jun 06 12:28:28 PM PDT 24 Jun 06 12:28:30 PM PDT 24 101202270 ps
T59 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1716283175 Jun 06 12:28:35 PM PDT 24 Jun 06 12:28:38 PM PDT 24 508029332 ps
T60 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1836485060 Jun 06 12:25:26 PM PDT 24 Jun 06 12:25:28 PM PDT 24 91205745 ps
T61 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.4107024716 Jun 06 12:26:44 PM PDT 24 Jun 06 12:26:46 PM PDT 24 150623713 ps
T63 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2829357227 Jun 06 12:28:26 PM PDT 24 Jun 06 12:28:30 PM PDT 24 312912604 ps
T106 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2869242902 Jun 06 12:26:23 PM PDT 24 Jun 06 12:26:27 PM PDT 24 164564379 ps
T107 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1559119227 Jun 06 12:28:27 PM PDT 24 Jun 06 12:28:30 PM PDT 24 257578891 ps
T64 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1248802054 Jun 06 12:27:50 PM PDT 24 Jun 06 12:27:53 PM PDT 24 422037532 ps
T116 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2932181328 Jun 06 12:28:02 PM PDT 24 Jun 06 12:28:05 PM PDT 24 251820533 ps
T108 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3203900043 Jun 06 12:28:26 PM PDT 24 Jun 06 12:28:28 PM PDT 24 87984564 ps
T65 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.4251664312 Jun 06 12:28:16 PM PDT 24 Jun 06 12:28:19 PM PDT 24 497319406 ps
T109 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1369460733 Jun 06 12:27:13 PM PDT 24 Jun 06 12:27:15 PM PDT 24 93704903 ps
T110 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3754260255 Jun 06 12:27:59 PM PDT 24 Jun 06 12:28:02 PM PDT 24 70247215 ps
T539 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.39905605 Jun 06 12:26:17 PM PDT 24 Jun 06 12:26:20 PM PDT 24 91195479 ps
T92 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.723983922 Jun 06 12:28:22 PM PDT 24 Jun 06 12:28:25 PM PDT 24 429568195 ps
T111 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.76290330 Jun 06 12:28:13 PM PDT 24 Jun 06 12:28:15 PM PDT 24 80661651 ps
T112 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3053152155 Jun 06 12:28:26 PM PDT 24 Jun 06 12:28:28 PM PDT 24 69901574 ps
T85 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.426944892 Jun 06 12:28:24 PM PDT 24 Jun 06 12:28:27 PM PDT 24 183074664 ps
T86 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3207330367 Jun 06 12:28:24 PM PDT 24 Jun 06 12:28:28 PM PDT 24 407942733 ps
T87 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3248800410 Jun 06 12:25:36 PM PDT 24 Jun 06 12:25:40 PM PDT 24 548362817 ps
T113 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1933131902 Jun 06 12:28:14 PM PDT 24 Jun 06 12:28:15 PM PDT 24 73035675 ps
T540 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2041933901 Jun 06 12:26:21 PM PDT 24 Jun 06 12:26:25 PM PDT 24 211273945 ps
T88 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1222361959 Jun 06 12:28:28 PM PDT 24 Jun 06 12:28:32 PM PDT 24 883621626 ps
T114 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1381070598 Jun 06 12:27:57 PM PDT 24 Jun 06 12:28:00 PM PDT 24 89151389 ps
T89 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.878976750 Jun 06 12:26:25 PM PDT 24 Jun 06 12:26:29 PM PDT 24 200827147 ps
T90 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2263738059 Jun 06 12:28:31 PM PDT 24 Jun 06 12:28:34 PM PDT 24 245947206 ps
T91 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3510658687 Jun 06 12:26:24 PM PDT 24 Jun 06 12:26:29 PM PDT 24 937283539 ps
T115 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2071488659 Jun 06 12:28:35 PM PDT 24 Jun 06 12:28:37 PM PDT 24 114950589 ps
T93 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.390525881 Jun 06 12:28:16 PM PDT 24 Jun 06 12:28:19 PM PDT 24 134355556 ps
T541 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1601338480 Jun 06 12:26:19 PM PDT 24 Jun 06 12:26:26 PM PDT 24 1027710035 ps
T542 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4183324096 Jun 06 12:26:22 PM PDT 24 Jun 06 12:26:26 PM PDT 24 358065649 ps
T543 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2821201467 Jun 06 12:22:36 PM PDT 24 Jun 06 12:22:38 PM PDT 24 111857609 ps
T544 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.305395986 Jun 06 12:28:24 PM PDT 24 Jun 06 12:28:26 PM PDT 24 107032732 ps
T545 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3470628695 Jun 06 12:28:02 PM PDT 24 Jun 06 12:28:05 PM PDT 24 416818853 ps
T546 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2723797399 Jun 06 12:26:25 PM PDT 24 Jun 06 12:26:38 PM PDT 24 2297040959 ps
T547 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4066201801 Jun 06 12:25:35 PM PDT 24 Jun 06 12:25:37 PM PDT 24 102997329 ps
T548 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2343279945 Jun 06 12:28:24 PM PDT 24 Jun 06 12:28:28 PM PDT 24 932241715 ps
T549 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1468894204 Jun 06 12:28:24 PM PDT 24 Jun 06 12:28:26 PM PDT 24 144332552 ps
T121 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.484477847 Jun 06 12:28:28 PM PDT 24 Jun 06 12:28:32 PM PDT 24 441625131 ps
T550 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.445372833 Jun 06 12:27:52 PM PDT 24 Jun 06 12:27:56 PM PDT 24 120153644 ps
T551 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.242725287 Jun 06 12:28:24 PM PDT 24 Jun 06 12:28:27 PM PDT 24 224984945 ps
T552 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.267023693 Jun 06 12:28:27 PM PDT 24 Jun 06 12:28:30 PM PDT 24 178242471 ps
T553 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3314585281 Jun 06 12:27:51 PM PDT 24 Jun 06 12:27:54 PM PDT 24 182790460 ps
T554 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2876129628 Jun 06 12:28:28 PM PDT 24 Jun 06 12:28:30 PM PDT 24 199830064 ps
T555 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.262740044 Jun 06 12:26:01 PM PDT 24 Jun 06 12:26:03 PM PDT 24 167897911 ps
T556 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1810019862 Jun 06 12:28:28 PM PDT 24 Jun 06 12:28:33 PM PDT 24 232566512 ps
T557 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3995470624 Jun 06 12:28:11 PM PDT 24 Jun 06 12:28:13 PM PDT 24 90654012 ps
T117 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3509677376 Jun 06 12:28:25 PM PDT 24 Jun 06 12:28:28 PM PDT 24 461405950 ps
T558 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.813682137 Jun 06 12:28:35 PM PDT 24 Jun 06 12:28:38 PM PDT 24 191326218 ps
T559 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.211996505 Jun 06 12:27:56 PM PDT 24 Jun 06 12:27:59 PM PDT 24 135900945 ps
T560 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.720605602 Jun 06 12:28:30 PM PDT 24 Jun 06 12:28:33 PM PDT 24 264537235 ps
T561 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.4273778952 Jun 06 12:26:22 PM PDT 24 Jun 06 12:26:27 PM PDT 24 406661181 ps
T562 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.388485365 Jun 06 12:26:21 PM PDT 24 Jun 06 12:26:25 PM PDT 24 193448558 ps
T563 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3588501269 Jun 06 12:28:26 PM PDT 24 Jun 06 12:28:28 PM PDT 24 109065302 ps
T120 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2183849446 Jun 06 12:28:15 PM PDT 24 Jun 06 12:28:20 PM PDT 24 1090447173 ps
T564 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.304928118 Jun 06 12:28:27 PM PDT 24 Jun 06 12:28:29 PM PDT 24 100822945 ps
T118 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3787786858 Jun 06 12:28:29 PM PDT 24 Jun 06 12:28:34 PM PDT 24 873712218 ps
T565 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1332090885 Jun 06 12:27:58 PM PDT 24 Jun 06 12:28:01 PM PDT 24 119438759 ps
T566 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3360090358 Jun 06 12:26:34 PM PDT 24 Jun 06 12:26:38 PM PDT 24 812620876 ps
T567 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3007618302 Jun 06 12:28:15 PM PDT 24 Jun 06 12:28:17 PM PDT 24 174707430 ps
T568 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2273205873 Jun 06 12:28:25 PM PDT 24 Jun 06 12:28:27 PM PDT 24 87491597 ps
T569 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2177276400 Jun 06 12:27:49 PM PDT 24 Jun 06 12:27:59 PM PDT 24 1552635364 ps
T570 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.762903286 Jun 06 12:26:08 PM PDT 24 Jun 06 12:26:14 PM PDT 24 1160200485 ps
T571 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1264910059 Jun 06 12:28:25 PM PDT 24 Jun 06 12:28:27 PM PDT 24 199247101 ps
T572 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3833385739 Jun 06 12:28:24 PM PDT 24 Jun 06 12:28:26 PM PDT 24 62150210 ps
T573 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.750941273 Jun 06 12:28:39 PM PDT 24 Jun 06 12:28:41 PM PDT 24 123818071 ps
T574 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2477051885 Jun 06 12:26:01 PM PDT 24 Jun 06 12:26:03 PM PDT 24 162119523 ps
T575 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.4198202012 Jun 06 12:27:53 PM PDT 24 Jun 06 12:27:55 PM PDT 24 59648258 ps
T576 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1816640986 Jun 06 12:28:25 PM PDT 24 Jun 06 12:28:27 PM PDT 24 71869961 ps
T577 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2533002185 Jun 06 12:28:20 PM PDT 24 Jun 06 12:28:22 PM PDT 24 205114752 ps
T578 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4281301175 Jun 06 12:28:08 PM PDT 24 Jun 06 12:28:12 PM PDT 24 264704801 ps
T122 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3378922709 Jun 06 12:28:27 PM PDT 24 Jun 06 12:28:32 PM PDT 24 869070188 ps
T579 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2198936154 Jun 06 12:27:57 PM PDT 24 Jun 06 12:28:01 PM PDT 24 426610838 ps
T580 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2869604941 Jun 06 12:28:28 PM PDT 24 Jun 06 12:28:31 PM PDT 24 157416958 ps
T581 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1607233109 Jun 06 12:28:26 PM PDT 24 Jun 06 12:28:30 PM PDT 24 350406404 ps
T582 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1668135550 Jun 06 12:26:40 PM PDT 24 Jun 06 12:26:42 PM PDT 24 202069314 ps
T583 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1893063736 Jun 06 12:26:20 PM PDT 24 Jun 06 12:26:23 PM PDT 24 474192528 ps
T584 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3265047466 Jun 06 12:28:28 PM PDT 24 Jun 06 12:28:32 PM PDT 24 188324701 ps
T585 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.4182920749 Jun 06 12:28:09 PM PDT 24 Jun 06 12:28:12 PM PDT 24 134487958 ps
T586 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3508359336 Jun 06 12:28:23 PM PDT 24 Jun 06 12:28:25 PM PDT 24 269407200 ps
T587 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3852558001 Jun 06 12:28:24 PM PDT 24 Jun 06 12:28:28 PM PDT 24 463276756 ps
T588 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2264881851 Jun 06 12:28:30 PM PDT 24 Jun 06 12:28:33 PM PDT 24 127041275 ps
T589 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2982813700 Jun 06 12:25:12 PM PDT 24 Jun 06 12:25:14 PM PDT 24 118532694 ps
T590 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1370722475 Jun 06 12:28:26 PM PDT 24 Jun 06 12:28:28 PM PDT 24 177498775 ps
T591 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.25514589 Jun 06 12:28:11 PM PDT 24 Jun 06 12:28:15 PM PDT 24 882501377 ps
T119 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3275718308 Jun 06 12:27:34 PM PDT 24 Jun 06 12:27:39 PM PDT 24 941754811 ps
T592 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1232061964 Jun 06 12:24:54 PM PDT 24 Jun 06 12:24:55 PM PDT 24 68327874 ps
T593 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.889196683 Jun 06 12:28:31 PM PDT 24 Jun 06 12:28:33 PM PDT 24 63657200 ps
T594 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2027951781 Jun 06 12:28:22 PM PDT 24 Jun 06 12:28:23 PM PDT 24 54273786 ps
T595 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3996772272 Jun 06 12:26:02 PM PDT 24 Jun 06 12:26:04 PM PDT 24 106148448 ps
T596 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.924387694 Jun 06 12:28:35 PM PDT 24 Jun 06 12:28:38 PM PDT 24 444458631 ps
T597 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2166754617 Jun 06 12:28:13 PM PDT 24 Jun 06 12:28:15 PM PDT 24 83489836 ps
T598 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.995743998 Jun 06 12:28:22 PM PDT 24 Jun 06 12:28:24 PM PDT 24 77110006 ps
T599 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.554910102 Jun 06 12:28:09 PM PDT 24 Jun 06 12:28:11 PM PDT 24 98578105 ps
T600 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.572861622 Jun 06 12:28:08 PM PDT 24 Jun 06 12:28:11 PM PDT 24 217364301 ps
T601 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.520241782 Jun 06 12:28:31 PM PDT 24 Jun 06 12:28:34 PM PDT 24 230785774 ps
T602 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.265943470 Jun 06 12:28:26 PM PDT 24 Jun 06 12:28:29 PM PDT 24 127704478 ps
T603 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.736459805 Jun 06 12:27:52 PM PDT 24 Jun 06 12:27:55 PM PDT 24 229823177 ps
T604 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3645723637 Jun 06 12:28:21 PM PDT 24 Jun 06 12:28:23 PM PDT 24 74861334 ps
T605 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1069980762 Jun 06 12:28:28 PM PDT 24 Jun 06 12:28:30 PM PDT 24 118907778 ps
T606 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2501288535 Jun 06 12:28:24 PM PDT 24 Jun 06 12:28:26 PM PDT 24 66363564 ps
T607 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3362526718 Jun 06 12:27:58 PM PDT 24 Jun 06 12:28:02 PM PDT 24 179908094 ps
T608 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1070254894 Jun 06 12:28:13 PM PDT 24 Jun 06 12:28:15 PM PDT 24 222405741 ps
T609 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1450015355 Jun 06 12:28:12 PM PDT 24 Jun 06 12:28:15 PM PDT 24 205872231 ps
T610 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3002374154 Jun 06 12:28:20 PM PDT 24 Jun 06 12:28:22 PM PDT 24 130083138 ps
T611 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2289004617 Jun 06 12:26:38 PM PDT 24 Jun 06 12:26:40 PM PDT 24 122316879 ps
T612 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.802065246 Jun 06 12:28:29 PM PDT 24 Jun 06 12:28:31 PM PDT 24 87452740 ps
T613 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2497217931 Jun 06 12:28:10 PM PDT 24 Jun 06 12:28:13 PM PDT 24 209362067 ps
T614 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3761536808 Jun 06 12:27:51 PM PDT 24 Jun 06 12:27:56 PM PDT 24 204041200 ps
T615 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1467170441 Jun 06 12:28:29 PM PDT 24 Jun 06 12:28:31 PM PDT 24 82612480 ps
T616 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2304982008 Jun 06 12:28:13 PM PDT 24 Jun 06 12:28:17 PM PDT 24 471115883 ps
T617 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.4190556077 Jun 06 12:28:26 PM PDT 24 Jun 06 12:28:28 PM PDT 24 63744615 ps
T618 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2000669179 Jun 06 12:27:56 PM PDT 24 Jun 06 12:27:58 PM PDT 24 65233189 ps
T619 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3770633140 Jun 06 12:27:56 PM PDT 24 Jun 06 12:27:59 PM PDT 24 104397521 ps
T620 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2408683790 Jun 06 12:26:25 PM PDT 24 Jun 06 12:26:28 PM PDT 24 104833060 ps

Test location /workspace/coverage/default/0.rstmgr_reset.3689699409
Short name T7
Test name
Test status
Simulation time 1637504380 ps
CPU time 6.38 seconds
Started Jun 06 12:28:31 PM PDT 24
Finished Jun 06 12:28:39 PM PDT 24
Peak memory 200836 kb
Host smart-4f29bf88-02e0-40a1-9152-4c9451b7f8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689699409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3689699409
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2509906518
Short name T3
Test name
Test status
Simulation time 425235135 ps
CPU time 2.52 seconds
Started Jun 06 12:29:24 PM PDT 24
Finished Jun 06 12:29:29 PM PDT 24
Peak memory 209304 kb
Host smart-dc911d53-a2ce-4cbd-b69c-58578fca867f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509906518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2509906518
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1555001171
Short name T67
Test name
Test status
Simulation time 17264174576 ps
CPU time 27.39 seconds
Started Jun 06 12:28:33 PM PDT 24
Finished Jun 06 12:29:02 PM PDT 24
Peak memory 217840 kb
Host smart-aa1a335a-a4d1-4f3b-9d39-e0783db385e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555001171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1555001171
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.4107024716
Short name T61
Test name
Test status
Simulation time 150623713 ps
CPU time 1.12 seconds
Started Jun 06 12:26:44 PM PDT 24
Finished Jun 06 12:26:46 PM PDT 24
Peak memory 208016 kb
Host smart-785b3d6e-d7aa-4be3-904c-d0ea0d4af82f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107024716 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.4107024716
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2866411715
Short name T27
Test name
Test status
Simulation time 2368334372 ps
CPU time 7.63 seconds
Started Jun 06 12:29:25 PM PDT 24
Finished Jun 06 12:29:35 PM PDT 24
Peak memory 222384 kb
Host smart-fb35e3d2-8426-41d3-83a2-88e98350feb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866411715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2866411715
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.572476177
Short name T71
Test name
Test status
Simulation time 67729826 ps
CPU time 0.77 seconds
Started Jun 06 12:28:35 PM PDT 24
Finished Jun 06 12:28:37 PM PDT 24
Peak memory 200556 kb
Host smart-2f1a722d-1e8f-49db-b636-79cf177e366c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572476177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.572476177
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1222361959
Short name T88
Test name
Test status
Simulation time 883621626 ps
CPU time 2.97 seconds
Started Jun 06 12:28:28 PM PDT 24
Finished Jun 06 12:28:32 PM PDT 24
Peak memory 200660 kb
Host smart-f01dc757-64fa-406d-b47d-a0fcdb09fa05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222361959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1222361959
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3473450753
Short name T81
Test name
Test status
Simulation time 131442559 ps
CPU time 1.02 seconds
Started Jun 06 12:28:52 PM PDT 24
Finished Jun 06 12:28:54 PM PDT 24
Peak memory 200664 kb
Host smart-fa5184bd-d315-4e0c-bf11-728ca7e0666e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473450753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3473450753
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.878976750
Short name T89
Test name
Test status
Simulation time 200827147 ps
CPU time 2.79 seconds
Started Jun 06 12:26:25 PM PDT 24
Finished Jun 06 12:26:29 PM PDT 24
Peak memory 208468 kb
Host smart-f90c930a-c9cc-43b9-89a3-33b17ff32d62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878976750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.878976750
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.771574205
Short name T31
Test name
Test status
Simulation time 1228708438 ps
CPU time 5.61 seconds
Started Jun 06 12:28:45 PM PDT 24
Finished Jun 06 12:28:52 PM PDT 24
Peak memory 217776 kb
Host smart-bb0a61ad-4957-4cea-a9a2-93f5ca11e627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771574205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.771574205
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1664626885
Short name T131
Test name
Test status
Simulation time 182149597 ps
CPU time 1.3 seconds
Started Jun 06 12:28:35 PM PDT 24
Finished Jun 06 12:28:38 PM PDT 24
Peak memory 200720 kb
Host smart-b381658e-ba32-4c01-b1ef-ecaf234cb9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664626885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1664626885
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.4162449685
Short name T95
Test name
Test status
Simulation time 2950801214 ps
CPU time 9.61 seconds
Started Jun 06 12:28:55 PM PDT 24
Finished Jun 06 12:29:07 PM PDT 24
Peak memory 201068 kb
Host smart-2a6c2a09-e085-4f9e-b1bd-5c279879f4ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162449685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.4162449685
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.121170762
Short name T5
Test name
Test status
Simulation time 1890495170 ps
CPU time 6.62 seconds
Started Jun 06 12:28:48 PM PDT 24
Finished Jun 06 12:28:55 PM PDT 24
Peak memory 222324 kb
Host smart-cd34549b-59ee-47ff-9ed0-9930302bdd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121170762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.121170762
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3787786858
Short name T118
Test name
Test status
Simulation time 873712218 ps
CPU time 3.36 seconds
Started Jun 06 12:28:29 PM PDT 24
Finished Jun 06 12:28:34 PM PDT 24
Peak memory 200556 kb
Host smart-9af555f1-8803-4d63-9163-3f871273244e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787786858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3787786858
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1920283601
Short name T28
Test name
Test status
Simulation time 1224709139 ps
CPU time 4.99 seconds
Started Jun 06 12:28:53 PM PDT 24
Finished Jun 06 12:28:59 PM PDT 24
Peak memory 218272 kb
Host smart-25225b31-dead-4f7c-8416-ef370c6ed696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920283601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1920283601
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1369460733
Short name T109
Test name
Test status
Simulation time 93704903 ps
CPU time 0.9 seconds
Started Jun 06 12:27:13 PM PDT 24
Finished Jun 06 12:27:15 PM PDT 24
Peak memory 200300 kb
Host smart-c4e710eb-9eba-4854-bad3-152423272312
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369460733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1369460733
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.760959508
Short name T14
Test name
Test status
Simulation time 136023753 ps
CPU time 0.8 seconds
Started Jun 06 12:28:31 PM PDT 24
Finished Jun 06 12:28:34 PM PDT 24
Peak memory 200468 kb
Host smart-76eeeb63-a72f-4d83-8b44-b5a1cffab66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760959508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.760959508
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3378922709
Short name T122
Test name
Test status
Simulation time 869070188 ps
CPU time 3.63 seconds
Started Jun 06 12:28:27 PM PDT 24
Finished Jun 06 12:28:32 PM PDT 24
Peak memory 200432 kb
Host smart-ae1c147a-bc19-4267-875c-c9efbf3d275a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378922709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3378922709
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3509677376
Short name T117
Test name
Test status
Simulation time 461405950 ps
CPU time 2.16 seconds
Started Jun 06 12:28:25 PM PDT 24
Finished Jun 06 12:28:28 PM PDT 24
Peak memory 200500 kb
Host smart-dcdb5365-a9d6-4b04-bd00-45bc4c88f1ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509677376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3509677376
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3510658687
Short name T91
Test name
Test status
Simulation time 937283539 ps
CPU time 2.91 seconds
Started Jun 06 12:26:24 PM PDT 24
Finished Jun 06 12:26:29 PM PDT 24
Peak memory 200196 kb
Host smart-2b21f5ad-9433-41d8-93fa-eaf007f054fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510658687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3510658687
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2510467585
Short name T132
Test name
Test status
Simulation time 121287788 ps
CPU time 1.39 seconds
Started Jun 06 12:28:51 PM PDT 24
Finished Jun 06 12:28:53 PM PDT 24
Peak memory 200508 kb
Host smart-69b6c669-432a-4a48-9dcf-da31cec28e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510467585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2510467585
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4183324096
Short name T542
Test name
Test status
Simulation time 358065649 ps
CPU time 2.41 seconds
Started Jun 06 12:26:22 PM PDT 24
Finished Jun 06 12:26:26 PM PDT 24
Peak memory 200032 kb
Host smart-42fa2cd7-1e54-470d-b4e2-be3853a225ec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183324096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.4
183324096
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1601338480
Short name T541
Test name
Test status
Simulation time 1027710035 ps
CPU time 4.84 seconds
Started Jun 06 12:26:19 PM PDT 24
Finished Jun 06 12:26:26 PM PDT 24
Peak memory 198908 kb
Host smart-f0438bdd-1ee6-448f-b498-2213c963ac52
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601338480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
601338480
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2982813700
Short name T589
Test name
Test status
Simulation time 118532694 ps
CPU time 0.95 seconds
Started Jun 06 12:25:12 PM PDT 24
Finished Jun 06 12:25:14 PM PDT 24
Peak memory 200192 kb
Host smart-5668d35f-57ae-4ca9-8a41-b9e6aca28c65
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982813700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
982813700
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2821201467
Short name T543
Test name
Test status
Simulation time 111857609 ps
CPU time 0.99 seconds
Started Jun 06 12:22:36 PM PDT 24
Finished Jun 06 12:22:38 PM PDT 24
Peak memory 200176 kb
Host smart-aaef4b66-d285-4f3f-8fb8-da7ade5733c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821201467 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2821201467
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2289004617
Short name T611
Test name
Test status
Simulation time 122316879 ps
CPU time 1.1 seconds
Started Jun 06 12:26:38 PM PDT 24
Finished Jun 06 12:26:40 PM PDT 24
Peak memory 200416 kb
Host smart-e41089cf-3cf3-4da3-9e09-9540798a66bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289004617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.2289004617
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.4273778952
Short name T561
Test name
Test status
Simulation time 406661181 ps
CPU time 2.68 seconds
Started Jun 06 12:26:22 PM PDT 24
Finished Jun 06 12:26:27 PM PDT 24
Peak memory 208360 kb
Host smart-9cf09b59-973e-4437-a3d2-e8aab6b72ba4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273778952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.4273778952
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1248802054
Short name T64
Test name
Test status
Simulation time 422037532 ps
CPU time 1.77 seconds
Started Jun 06 12:27:50 PM PDT 24
Finished Jun 06 12:27:53 PM PDT 24
Peak memory 200336 kb
Host smart-dbaea799-69a6-46e6-8c8b-9cba3eb727f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248802054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1248802054
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2041933901
Short name T540
Test name
Test status
Simulation time 211273945 ps
CPU time 1.67 seconds
Started Jun 06 12:26:21 PM PDT 24
Finished Jun 06 12:26:25 PM PDT 24
Peak memory 198360 kb
Host smart-342a8a67-9e80-4d61-bde6-c4763514d733
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041933901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
041933901
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2177276400
Short name T569
Test name
Test status
Simulation time 1552635364 ps
CPU time 8.05 seconds
Started Jun 06 12:27:49 PM PDT 24
Finished Jun 06 12:27:59 PM PDT 24
Peak memory 200032 kb
Host smart-7a3f3659-16c0-4a4f-bf49-9e6d0eac5b32
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177276400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
177276400
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3996772272
Short name T595
Test name
Test status
Simulation time 106148448 ps
CPU time 0.83 seconds
Started Jun 06 12:26:02 PM PDT 24
Finished Jun 06 12:26:04 PM PDT 24
Peak memory 200256 kb
Host smart-1e243dea-7725-4483-a1b7-69e3a3d4a297
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996772272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.3
996772272
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.388485365
Short name T562
Test name
Test status
Simulation time 193448558 ps
CPU time 1.12 seconds
Started Jun 06 12:26:21 PM PDT 24
Finished Jun 06 12:26:25 PM PDT 24
Peak memory 199788 kb
Host smart-ed7f36b4-ddc5-4740-bce5-a112bd7b6972
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388485365 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.388485365
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1232061964
Short name T592
Test name
Test status
Simulation time 68327874 ps
CPU time 0.73 seconds
Started Jun 06 12:24:54 PM PDT 24
Finished Jun 06 12:24:55 PM PDT 24
Peak memory 200176 kb
Host smart-cd6439ec-2f6e-4a2b-af0f-a7944e6cf376
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232061964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1232061964
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2477051885
Short name T574
Test name
Test status
Simulation time 162119523 ps
CPU time 1.19 seconds
Started Jun 06 12:26:01 PM PDT 24
Finished Jun 06 12:26:03 PM PDT 24
Peak memory 200260 kb
Host smart-061e1866-5216-42b5-ae60-595996f588ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477051885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2477051885
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.262740044
Short name T555
Test name
Test status
Simulation time 167897911 ps
CPU time 1.33 seconds
Started Jun 06 12:26:01 PM PDT 24
Finished Jun 06 12:26:03 PM PDT 24
Peak memory 200292 kb
Host smart-550b1576-9662-4be7-afdd-78c2857de81b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262740044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.262740044
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1893063736
Short name T583
Test name
Test status
Simulation time 474192528 ps
CPU time 1.89 seconds
Started Jun 06 12:26:20 PM PDT 24
Finished Jun 06 12:26:23 PM PDT 24
Peak memory 200084 kb
Host smart-7e49bb34-a367-4c31-90fd-38179b27fda8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893063736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1893063736
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.267023693
Short name T552
Test name
Test status
Simulation time 178242471 ps
CPU time 1.71 seconds
Started Jun 06 12:28:27 PM PDT 24
Finished Jun 06 12:28:30 PM PDT 24
Peak memory 209108 kb
Host smart-37ac5f46-de14-453c-8bed-3c46492b0173
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267023693 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.267023693
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1816640986
Short name T576
Test name
Test status
Simulation time 71869961 ps
CPU time 0.84 seconds
Started Jun 06 12:28:25 PM PDT 24
Finished Jun 06 12:28:27 PM PDT 24
Peak memory 200220 kb
Host smart-b100bda1-f633-4798-b5a2-6f35bbeccac4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816640986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1816640986
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3588501269
Short name T563
Test name
Test status
Simulation time 109065302 ps
CPU time 1.26 seconds
Started Jun 06 12:28:26 PM PDT 24
Finished Jun 06 12:28:28 PM PDT 24
Peak memory 200464 kb
Host smart-0911b942-8b1e-4dc0-aa1d-ef0c3915563a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588501269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3588501269
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1607233109
Short name T581
Test name
Test status
Simulation time 350406404 ps
CPU time 2.83 seconds
Started Jun 06 12:28:26 PM PDT 24
Finished Jun 06 12:28:30 PM PDT 24
Peak memory 216868 kb
Host smart-d3cdb69d-5228-46cc-aa4f-cf1530d1d7f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607233109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1607233109
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3002374154
Short name T610
Test name
Test status
Simulation time 130083138 ps
CPU time 1.39 seconds
Started Jun 06 12:28:20 PM PDT 24
Finished Jun 06 12:28:22 PM PDT 24
Peak memory 213072 kb
Host smart-77b53e49-a7fc-4f27-8e86-2c57d6ad886a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002374154 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3002374154
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.889196683
Short name T593
Test name
Test status
Simulation time 63657200 ps
CPU time 0.75 seconds
Started Jun 06 12:28:31 PM PDT 24
Finished Jun 06 12:28:33 PM PDT 24
Peak memory 200108 kb
Host smart-adeb1fe8-c028-40aa-bd7b-1fdf2ca3175e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889196683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.889196683
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1559119227
Short name T107
Test name
Test status
Simulation time 257578891 ps
CPU time 1.79 seconds
Started Jun 06 12:28:27 PM PDT 24
Finished Jun 06 12:28:30 PM PDT 24
Peak memory 200464 kb
Host smart-e26221c8-9c99-44cc-9c45-b8f52a23620b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559119227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1559119227
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.426944892
Short name T85
Test name
Test status
Simulation time 183074664 ps
CPU time 2.43 seconds
Started Jun 06 12:28:24 PM PDT 24
Finished Jun 06 12:28:27 PM PDT 24
Peak memory 208688 kb
Host smart-32ffbe7c-ed82-4ff9-9e1d-adb87f2e2bca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426944892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.426944892
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.484477847
Short name T121
Test name
Test status
Simulation time 441625131 ps
CPU time 1.89 seconds
Started Jun 06 12:28:28 PM PDT 24
Finished Jun 06 12:28:32 PM PDT 24
Peak memory 200572 kb
Host smart-7cad9e57-21b2-4210-9c1c-824bb746eda6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484477847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.484477847
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1069980762
Short name T605
Test name
Test status
Simulation time 118907778 ps
CPU time 0.94 seconds
Started Jun 06 12:28:28 PM PDT 24
Finished Jun 06 12:28:30 PM PDT 24
Peak memory 200380 kb
Host smart-cdb701bf-fcf9-4c5d-a992-677711e8a95f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069980762 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1069980762
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3053152155
Short name T112
Test name
Test status
Simulation time 69901574 ps
CPU time 0.8 seconds
Started Jun 06 12:28:26 PM PDT 24
Finished Jun 06 12:28:28 PM PDT 24
Peak memory 200224 kb
Host smart-69adca2a-a7a0-4213-a0f3-8f123fa17ecb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053152155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3053152155
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2071488659
Short name T115
Test name
Test status
Simulation time 114950589 ps
CPU time 1.02 seconds
Started Jun 06 12:28:35 PM PDT 24
Finished Jun 06 12:28:37 PM PDT 24
Peak memory 200268 kb
Host smart-64a86434-243d-4524-902d-1a725c8b125c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071488659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.2071488659
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2829357227
Short name T63
Test name
Test status
Simulation time 312912604 ps
CPU time 2.4 seconds
Started Jun 06 12:28:26 PM PDT 24
Finished Jun 06 12:28:30 PM PDT 24
Peak memory 208824 kb
Host smart-6ed1a066-862f-4bb0-afd7-6ca02fd77573
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829357227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2829357227
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2343279945
Short name T548
Test name
Test status
Simulation time 932241715 ps
CPU time 3.1 seconds
Started Jun 06 12:28:24 PM PDT 24
Finished Jun 06 12:28:28 PM PDT 24
Peak memory 200524 kb
Host smart-eedfd95f-1978-41f7-bff1-29a3d542e098
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343279945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.2343279945
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2876129628
Short name T554
Test name
Test status
Simulation time 199830064 ps
CPU time 1.32 seconds
Started Jun 06 12:28:28 PM PDT 24
Finished Jun 06 12:28:30 PM PDT 24
Peak memory 208652 kb
Host smart-3938ddeb-1470-4095-9895-eed42cc35121
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876129628 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2876129628
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3833385739
Short name T572
Test name
Test status
Simulation time 62150210 ps
CPU time 0.78 seconds
Started Jun 06 12:28:24 PM PDT 24
Finished Jun 06 12:28:26 PM PDT 24
Peak memory 200180 kb
Host smart-d1d3dd8c-1dc1-4892-8108-5026b1057d8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833385739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3833385739
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1468894204
Short name T549
Test name
Test status
Simulation time 144332552 ps
CPU time 1.13 seconds
Started Jun 06 12:28:24 PM PDT 24
Finished Jun 06 12:28:26 PM PDT 24
Peak memory 200252 kb
Host smart-3ba716d5-cc0d-4a65-94b7-98becf8993ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468894204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1468894204
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1810019862
Short name T556
Test name
Test status
Simulation time 232566512 ps
CPU time 3.38 seconds
Started Jun 06 12:28:28 PM PDT 24
Finished Jun 06 12:28:33 PM PDT 24
Peak memory 208816 kb
Host smart-f6f247d1-20c8-423f-9df9-a3bf22ecc9d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810019862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1810019862
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2533002185
Short name T577
Test name
Test status
Simulation time 205114752 ps
CPU time 1.38 seconds
Started Jun 06 12:28:20 PM PDT 24
Finished Jun 06 12:28:22 PM PDT 24
Peak memory 216744 kb
Host smart-872392e5-9cad-4821-8323-a43e2f3ff161
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533002185 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2533002185
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2273205873
Short name T568
Test name
Test status
Simulation time 87491597 ps
CPU time 0.88 seconds
Started Jun 06 12:28:25 PM PDT 24
Finished Jun 06 12:28:27 PM PDT 24
Peak memory 200332 kb
Host smart-97b0c114-ce63-4980-84f0-6e367d832e57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273205873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2273205873
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3508359336
Short name T586
Test name
Test status
Simulation time 269407200 ps
CPU time 1.54 seconds
Started Jun 06 12:28:23 PM PDT 24
Finished Jun 06 12:28:25 PM PDT 24
Peak memory 200472 kb
Host smart-59decb69-f916-4a99-8f35-786c28543b96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508359336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3508359336
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.305395986
Short name T544
Test name
Test status
Simulation time 107032732 ps
CPU time 1.54 seconds
Started Jun 06 12:28:24 PM PDT 24
Finished Jun 06 12:28:26 PM PDT 24
Peak memory 200500 kb
Host smart-1a3c36a7-5986-44c7-aff9-6024737ab5aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305395986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.305395986
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1716283175
Short name T59
Test name
Test status
Simulation time 508029332 ps
CPU time 1.9 seconds
Started Jun 06 12:28:35 PM PDT 24
Finished Jun 06 12:28:38 PM PDT 24
Peak memory 200504 kb
Host smart-069e1598-16a1-4fdb-b72f-5047cdf3c287
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716283175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1716283175
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2869604941
Short name T580
Test name
Test status
Simulation time 157416958 ps
CPU time 1.44 seconds
Started Jun 06 12:28:28 PM PDT 24
Finished Jun 06 12:28:31 PM PDT 24
Peak memory 208740 kb
Host smart-934fb0de-1d0e-441c-ad6c-b54184b9312e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869604941 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2869604941
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2501288535
Short name T606
Test name
Test status
Simulation time 66363564 ps
CPU time 0.82 seconds
Started Jun 06 12:28:24 PM PDT 24
Finished Jun 06 12:28:26 PM PDT 24
Peak memory 200308 kb
Host smart-a1240cb0-bd79-47fd-b764-efbff277448c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501288535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2501288535
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.520241782
Short name T601
Test name
Test status
Simulation time 230785774 ps
CPU time 1.51 seconds
Started Jun 06 12:28:31 PM PDT 24
Finished Jun 06 12:28:34 PM PDT 24
Peak memory 200408 kb
Host smart-44efca31-ba1a-441d-927b-1e8a89461473
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520241782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.520241782
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4092774194
Short name T62
Test name
Test status
Simulation time 101202270 ps
CPU time 1.42 seconds
Started Jun 06 12:28:28 PM PDT 24
Finished Jun 06 12:28:30 PM PDT 24
Peak memory 208732 kb
Host smart-bd8028a7-a384-479f-aa1e-4f3762664e7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092774194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.4092774194
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.924387694
Short name T596
Test name
Test status
Simulation time 444458631 ps
CPU time 1.88 seconds
Started Jun 06 12:28:35 PM PDT 24
Finished Jun 06 12:28:38 PM PDT 24
Peak memory 200492 kb
Host smart-b654e06d-cb5d-4a23-ad6d-b21d7b3a3b20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924387694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err
.924387694
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1370722475
Short name T590
Test name
Test status
Simulation time 177498775 ps
CPU time 1.81 seconds
Started Jun 06 12:28:26 PM PDT 24
Finished Jun 06 12:28:28 PM PDT 24
Peak memory 208688 kb
Host smart-aac18aaf-e1b6-4bb8-961e-c96b9fe743ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370722475 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.1370722475
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3203900043
Short name T108
Test name
Test status
Simulation time 87984564 ps
CPU time 0.92 seconds
Started Jun 06 12:28:26 PM PDT 24
Finished Jun 06 12:28:28 PM PDT 24
Peak memory 200200 kb
Host smart-5855650a-69d3-4768-97f6-c82569d894fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203900043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3203900043
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.750941273
Short name T573
Test name
Test status
Simulation time 123818071 ps
CPU time 1.23 seconds
Started Jun 06 12:28:39 PM PDT 24
Finished Jun 06 12:28:41 PM PDT 24
Peak memory 200548 kb
Host smart-80923632-27cb-4f79-b3bf-0477b11a55ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750941273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.750941273
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3207330367
Short name T86
Test name
Test status
Simulation time 407942733 ps
CPU time 2.8 seconds
Started Jun 06 12:28:24 PM PDT 24
Finished Jun 06 12:28:28 PM PDT 24
Peak memory 208804 kb
Host smart-13ac937a-afde-41d8-a795-997e36bad6c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207330367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3207330367
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.723983922
Short name T92
Test name
Test status
Simulation time 429568195 ps
CPU time 1.78 seconds
Started Jun 06 12:28:22 PM PDT 24
Finished Jun 06 12:28:25 PM PDT 24
Peak memory 200460 kb
Host smart-6a8846df-4bf0-4b17-ac27-0450b075b910
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723983922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err
.723983922
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1264910059
Short name T571
Test name
Test status
Simulation time 199247101 ps
CPU time 1.28 seconds
Started Jun 06 12:28:25 PM PDT 24
Finished Jun 06 12:28:27 PM PDT 24
Peak memory 208792 kb
Host smart-71f6f8bc-b556-41db-93ba-580a074db5cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264910059 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.1264910059
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1467170441
Short name T615
Test name
Test status
Simulation time 82612480 ps
CPU time 0.88 seconds
Started Jun 06 12:28:29 PM PDT 24
Finished Jun 06 12:28:31 PM PDT 24
Peak memory 200296 kb
Host smart-ff1239b1-d461-4e70-91d6-d3b6c293c171
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467170441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1467170441
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.304928118
Short name T564
Test name
Test status
Simulation time 100822945 ps
CPU time 1.3 seconds
Started Jun 06 12:28:27 PM PDT 24
Finished Jun 06 12:28:29 PM PDT 24
Peak memory 200516 kb
Host smart-6a817dbd-c07a-4331-b273-b5d5d602ecfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304928118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.304928118
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.720605602
Short name T560
Test name
Test status
Simulation time 264537235 ps
CPU time 1.8 seconds
Started Jun 06 12:28:30 PM PDT 24
Finished Jun 06 12:28:33 PM PDT 24
Peak memory 200456 kb
Host smart-f9882a13-f7fa-4626-a574-dcad13741574
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720605602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.720605602
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.813682137
Short name T558
Test name
Test status
Simulation time 191326218 ps
CPU time 1.92 seconds
Started Jun 06 12:28:35 PM PDT 24
Finished Jun 06 12:28:38 PM PDT 24
Peak memory 208732 kb
Host smart-a3eb940e-c527-4efd-afec-80c6686cc228
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813682137 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.813682137
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.995743998
Short name T598
Test name
Test status
Simulation time 77110006 ps
CPU time 0.82 seconds
Started Jun 06 12:28:22 PM PDT 24
Finished Jun 06 12:28:24 PM PDT 24
Peak memory 200224 kb
Host smart-54f819c1-0269-4db5-b5d0-9d617aa5ee8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995743998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.995743998
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.242725287
Short name T551
Test name
Test status
Simulation time 224984945 ps
CPU time 1.61 seconds
Started Jun 06 12:28:24 PM PDT 24
Finished Jun 06 12:28:27 PM PDT 24
Peak memory 200532 kb
Host smart-e6ef3b0e-66a7-4c9b-9951-dcabffc96c94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242725287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.242725287
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2264881851
Short name T588
Test name
Test status
Simulation time 127041275 ps
CPU time 1.69 seconds
Started Jun 06 12:28:30 PM PDT 24
Finished Jun 06 12:28:33 PM PDT 24
Peak memory 208616 kb
Host smart-caf9ef07-909b-40a1-b581-37662f5ee573
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264881851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2264881851
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3265047466
Short name T584
Test name
Test status
Simulation time 188324701 ps
CPU time 2.05 seconds
Started Jun 06 12:28:28 PM PDT 24
Finished Jun 06 12:28:32 PM PDT 24
Peak memory 213924 kb
Host smart-f8c6e69f-2409-4302-9730-b7a318dc0931
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265047466 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3265047466
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.802065246
Short name T612
Test name
Test status
Simulation time 87452740 ps
CPU time 0.9 seconds
Started Jun 06 12:28:29 PM PDT 24
Finished Jun 06 12:28:31 PM PDT 24
Peak memory 200296 kb
Host smart-298cb887-06e0-4697-8c54-29d0ea32704a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802065246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.802065246
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.265943470
Short name T602
Test name
Test status
Simulation time 127704478 ps
CPU time 1.25 seconds
Started Jun 06 12:28:26 PM PDT 24
Finished Jun 06 12:28:29 PM PDT 24
Peak memory 200892 kb
Host smart-890ba180-c9b3-40e3-ad44-d2eaefd77cef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265943470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.265943470
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2263738059
Short name T90
Test name
Test status
Simulation time 245947206 ps
CPU time 1.75 seconds
Started Jun 06 12:28:31 PM PDT 24
Finished Jun 06 12:28:34 PM PDT 24
Peak memory 208616 kb
Host smart-182b09fb-120d-4d9d-b590-c538bf1a2682
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263738059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2263738059
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3852558001
Short name T587
Test name
Test status
Simulation time 463276756 ps
CPU time 1.92 seconds
Started Jun 06 12:28:24 PM PDT 24
Finished Jun 06 12:28:28 PM PDT 24
Peak memory 200480 kb
Host smart-943aa6a4-81a2-481c-9e92-53ebb2cb39e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852558001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3852558001
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2932181328
Short name T116
Test name
Test status
Simulation time 251820533 ps
CPU time 1.54 seconds
Started Jun 06 12:28:02 PM PDT 24
Finished Jun 06 12:28:05 PM PDT 24
Peak memory 200312 kb
Host smart-4a6a390e-8c92-4751-aede-1d620de36fae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932181328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
932181328
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2723797399
Short name T546
Test name
Test status
Simulation time 2297040959 ps
CPU time 10.27 seconds
Started Jun 06 12:26:25 PM PDT 24
Finished Jun 06 12:26:38 PM PDT 24
Peak memory 200240 kb
Host smart-9e637ae2-9172-429b-80c1-48c6a959c3a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723797399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
723797399
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1836485060
Short name T60
Test name
Test status
Simulation time 91205745 ps
CPU time 0.81 seconds
Started Jun 06 12:25:26 PM PDT 24
Finished Jun 06 12:25:28 PM PDT 24
Peak memory 200156 kb
Host smart-7c28f49c-0b52-401f-aeae-18105e987200
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836485060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
836485060
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.445372833
Short name T550
Test name
Test status
Simulation time 120153644 ps
CPU time 1.3 seconds
Started Jun 06 12:27:52 PM PDT 24
Finished Jun 06 12:27:56 PM PDT 24
Peak memory 211356 kb
Host smart-d2a8f834-0995-440e-9eb9-67eaf300e8b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445372833 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.445372833
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3754260255
Short name T110
Test name
Test status
Simulation time 70247215 ps
CPU time 0.8 seconds
Started Jun 06 12:27:59 PM PDT 24
Finished Jun 06 12:28:02 PM PDT 24
Peak memory 200156 kb
Host smart-09a04b84-339a-4098-bbd2-3eae3f291c2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754260255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3754260255
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2869242902
Short name T106
Test name
Test status
Simulation time 164564379 ps
CPU time 1.14 seconds
Started Jun 06 12:26:23 PM PDT 24
Finished Jun 06 12:26:27 PM PDT 24
Peak memory 198988 kb
Host smart-9625fa7c-9856-439b-9aea-b7a28ae8e402
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869242902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2869242902
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2408683790
Short name T620
Test name
Test status
Simulation time 104833060 ps
CPU time 1.42 seconds
Started Jun 06 12:26:25 PM PDT 24
Finished Jun 06 12:26:28 PM PDT 24
Peak memory 208404 kb
Host smart-adc6c1e7-b6bf-4355-94ce-00355f04d53d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408683790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2408683790
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3761536808
Short name T614
Test name
Test status
Simulation time 204041200 ps
CPU time 1.5 seconds
Started Jun 06 12:27:51 PM PDT 24
Finished Jun 06 12:27:56 PM PDT 24
Peak memory 199004 kb
Host smart-b3117a48-d159-4bca-8899-e733e20c0d4e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761536808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
761536808
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.762903286
Short name T570
Test name
Test status
Simulation time 1160200485 ps
CPU time 5.59 seconds
Started Jun 06 12:26:08 PM PDT 24
Finished Jun 06 12:26:14 PM PDT 24
Peak memory 216832 kb
Host smart-0181a35e-f839-4a1e-ad33-f43de4b4daea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762903286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.762903286
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.39905605
Short name T539
Test name
Test status
Simulation time 91195479 ps
CPU time 0.84 seconds
Started Jun 06 12:26:17 PM PDT 24
Finished Jun 06 12:26:20 PM PDT 24
Peak memory 198428 kb
Host smart-300ee930-9c1e-46af-9c1f-4e306cfae3bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39905605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.39905605
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1332090885
Short name T565
Test name
Test status
Simulation time 119438759 ps
CPU time 0.92 seconds
Started Jun 06 12:27:58 PM PDT 24
Finished Jun 06 12:28:01 PM PDT 24
Peak memory 200024 kb
Host smart-f28a2bb7-7fc0-42c1-b826-d0474852dc22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332090885 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1332090885
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2000669179
Short name T618
Test name
Test status
Simulation time 65233189 ps
CPU time 0.82 seconds
Started Jun 06 12:27:56 PM PDT 24
Finished Jun 06 12:27:58 PM PDT 24
Peak memory 199156 kb
Host smart-d6782ed5-04d4-41dd-aace-0885df22ef10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000669179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.2000669179
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3770633140
Short name T619
Test name
Test status
Simulation time 104397521 ps
CPU time 1.23 seconds
Started Jun 06 12:27:56 PM PDT 24
Finished Jun 06 12:27:59 PM PDT 24
Peak memory 199936 kb
Host smart-da9b9f9e-2f5a-4e64-b714-eaac047733a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770633140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3770633140
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3360090358
Short name T566
Test name
Test status
Simulation time 812620876 ps
CPU time 2.69 seconds
Started Jun 06 12:26:34 PM PDT 24
Finished Jun 06 12:26:38 PM PDT 24
Peak memory 200392 kb
Host smart-4cde2d04-a68f-4469-8baf-722cd1d29d4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360090358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3360090358
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.736459805
Short name T603
Test name
Test status
Simulation time 229823177 ps
CPU time 1.62 seconds
Started Jun 06 12:27:52 PM PDT 24
Finished Jun 06 12:27:55 PM PDT 24
Peak memory 200112 kb
Host smart-eb2c6ed0-4e2a-4786-b76e-4d9a8b06fc44
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736459805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.736459805
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4281301175
Short name T578
Test name
Test status
Simulation time 264704801 ps
CPU time 3.06 seconds
Started Jun 06 12:28:08 PM PDT 24
Finished Jun 06 12:28:12 PM PDT 24
Peak memory 200464 kb
Host smart-d1b10c1a-5db2-4723-8bb6-fbb936cf9339
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281301175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.4
281301175
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.211996505
Short name T559
Test name
Test status
Simulation time 135900945 ps
CPU time 0.89 seconds
Started Jun 06 12:27:56 PM PDT 24
Finished Jun 06 12:27:59 PM PDT 24
Peak memory 199892 kb
Host smart-99596323-bd59-44dd-8b9d-c9cadd3ed934
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211996505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.211996505
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3314585281
Short name T553
Test name
Test status
Simulation time 182790460 ps
CPU time 1.74 seconds
Started Jun 06 12:27:51 PM PDT 24
Finished Jun 06 12:27:54 PM PDT 24
Peak memory 208384 kb
Host smart-9cb225bd-2ffc-4b88-aceb-8d949821d3c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314585281 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.3314585281
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1381070598
Short name T114
Test name
Test status
Simulation time 89151389 ps
CPU time 0.85 seconds
Started Jun 06 12:27:57 PM PDT 24
Finished Jun 06 12:28:00 PM PDT 24
Peak memory 199972 kb
Host smart-26d924f2-cc43-4d2c-9c2f-457e0cd4cc48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381070598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1381070598
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4066201801
Short name T547
Test name
Test status
Simulation time 102997329 ps
CPU time 1.24 seconds
Started Jun 06 12:25:35 PM PDT 24
Finished Jun 06 12:25:37 PM PDT 24
Peak memory 198672 kb
Host smart-01da17b0-8362-4c78-ba03-4a4b64a3028a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066201801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.4066201801
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3362526718
Short name T607
Test name
Test status
Simulation time 179908094 ps
CPU time 2.35 seconds
Started Jun 06 12:27:58 PM PDT 24
Finished Jun 06 12:28:02 PM PDT 24
Peak memory 215836 kb
Host smart-12d3eb78-ddc1-4108-8a97-42243333cae7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362526718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3362526718
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2198936154
Short name T579
Test name
Test status
Simulation time 426610838 ps
CPU time 1.81 seconds
Started Jun 06 12:27:57 PM PDT 24
Finished Jun 06 12:28:01 PM PDT 24
Peak memory 200288 kb
Host smart-01fec817-9039-4bcf-b964-819b0f8a9ffe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198936154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2198936154
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2027951781
Short name T594
Test name
Test status
Simulation time 54273786 ps
CPU time 0.7 seconds
Started Jun 06 12:28:22 PM PDT 24
Finished Jun 06 12:28:23 PM PDT 24
Peak memory 200256 kb
Host smart-3b2dd246-3763-4826-bf30-ef5049994cc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027951781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2027951781
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3645723637
Short name T604
Test name
Test status
Simulation time 74861334 ps
CPU time 0.94 seconds
Started Jun 06 12:28:21 PM PDT 24
Finished Jun 06 12:28:23 PM PDT 24
Peak memory 200304 kb
Host smart-ce18c974-1d0b-4015-b351-cccade4def19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645723637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3645723637
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1668135550
Short name T582
Test name
Test status
Simulation time 202069314 ps
CPU time 1.63 seconds
Started Jun 06 12:26:40 PM PDT 24
Finished Jun 06 12:26:42 PM PDT 24
Peak memory 216872 kb
Host smart-fc1e01d3-6a6f-4ea2-906d-fbb2085890fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668135550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1668135550
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3470628695
Short name T545
Test name
Test status
Simulation time 416818853 ps
CPU time 1.79 seconds
Started Jun 06 12:28:02 PM PDT 24
Finished Jun 06 12:28:05 PM PDT 24
Peak memory 199092 kb
Host smart-9e228d3b-6d5a-4a2d-82f2-c9000dc82352
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470628695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.3470628695
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2497217931
Short name T613
Test name
Test status
Simulation time 209362067 ps
CPU time 1.39 seconds
Started Jun 06 12:28:10 PM PDT 24
Finished Jun 06 12:28:13 PM PDT 24
Peak memory 208540 kb
Host smart-fbdf15b8-b60b-401d-a4e1-6880cd69e899
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497217931 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2497217931
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.4198202012
Short name T575
Test name
Test status
Simulation time 59648258 ps
CPU time 0.71 seconds
Started Jun 06 12:27:53 PM PDT 24
Finished Jun 06 12:27:55 PM PDT 24
Peak memory 199880 kb
Host smart-bbe6ca96-5cd9-4217-8f05-031b3b2f72c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198202012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.4198202012
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1070254894
Short name T608
Test name
Test status
Simulation time 222405741 ps
CPU time 1.42 seconds
Started Jun 06 12:28:13 PM PDT 24
Finished Jun 06 12:28:15 PM PDT 24
Peak memory 200644 kb
Host smart-0f839696-cc5f-48d8-bb03-044678b191cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070254894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1070254894
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3248800410
Short name T87
Test name
Test status
Simulation time 548362817 ps
CPU time 3.29 seconds
Started Jun 06 12:25:36 PM PDT 24
Finished Jun 06 12:25:40 PM PDT 24
Peak memory 208376 kb
Host smart-fc5762b3-171e-4746-a3d0-c069aa84eae8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248800410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3248800410
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3275718308
Short name T119
Test name
Test status
Simulation time 941754811 ps
CPU time 3.04 seconds
Started Jun 06 12:27:34 PM PDT 24
Finished Jun 06 12:27:39 PM PDT 24
Peak memory 200500 kb
Host smart-36e1ece9-e3af-472e-80de-3d32e7e2056a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275718308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3275718308
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3007618302
Short name T567
Test name
Test status
Simulation time 174707430 ps
CPU time 1.32 seconds
Started Jun 06 12:28:15 PM PDT 24
Finished Jun 06 12:28:17 PM PDT 24
Peak memory 200296 kb
Host smart-f9020bce-6e3f-485b-9d44-1bcf5a0aa923
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007618302 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3007618302
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3995470624
Short name T557
Test name
Test status
Simulation time 90654012 ps
CPU time 0.85 seconds
Started Jun 06 12:28:11 PM PDT 24
Finished Jun 06 12:28:13 PM PDT 24
Peak memory 200260 kb
Host smart-b2579952-8f2f-45d2-979d-8f2a14b5bacd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995470624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.3995470624
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.76290330
Short name T111
Test name
Test status
Simulation time 80661651 ps
CPU time 1.05 seconds
Started Jun 06 12:28:13 PM PDT 24
Finished Jun 06 12:28:15 PM PDT 24
Peak memory 200312 kb
Host smart-3f0ce64d-9784-49b8-833d-58154e015029
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76290330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_same
_csr_outstanding.76290330
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2304982008
Short name T616
Test name
Test status
Simulation time 471115883 ps
CPU time 3.49 seconds
Started Jun 06 12:28:13 PM PDT 24
Finished Jun 06 12:28:17 PM PDT 24
Peak memory 208652 kb
Host smart-8e386cd5-a580-4143-836a-a0a6daf217ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304982008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2304982008
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2183849446
Short name T120
Test name
Test status
Simulation time 1090447173 ps
CPU time 3.5 seconds
Started Jun 06 12:28:15 PM PDT 24
Finished Jun 06 12:28:20 PM PDT 24
Peak memory 200508 kb
Host smart-c5af7fec-2512-43fc-9ccd-6f4d12802498
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183849446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.2183849446
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.554910102
Short name T599
Test name
Test status
Simulation time 98578105 ps
CPU time 0.92 seconds
Started Jun 06 12:28:09 PM PDT 24
Finished Jun 06 12:28:11 PM PDT 24
Peak memory 200412 kb
Host smart-cafdc50b-3eee-4eff-b053-2914069e62d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554910102 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.554910102
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1933131902
Short name T113
Test name
Test status
Simulation time 73035675 ps
CPU time 0.78 seconds
Started Jun 06 12:28:14 PM PDT 24
Finished Jun 06 12:28:15 PM PDT 24
Peak memory 200120 kb
Host smart-35e385a2-2c2c-405a-8ac2-9009fb21232c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933131902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1933131902
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2166754617
Short name T597
Test name
Test status
Simulation time 83489836 ps
CPU time 0.95 seconds
Started Jun 06 12:28:13 PM PDT 24
Finished Jun 06 12:28:15 PM PDT 24
Peak memory 200288 kb
Host smart-c5c00c4f-58f8-4ac6-adb4-2098b95a7185
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166754617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.2166754617
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1450015355
Short name T609
Test name
Test status
Simulation time 205872231 ps
CPU time 1.65 seconds
Started Jun 06 12:28:12 PM PDT 24
Finished Jun 06 12:28:15 PM PDT 24
Peak memory 208828 kb
Host smart-6dd63f2a-74a8-4f80-9490-385186e0e5f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450015355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1450015355
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.4251664312
Short name T65
Test name
Test status
Simulation time 497319406 ps
CPU time 1.9 seconds
Started Jun 06 12:28:16 PM PDT 24
Finished Jun 06 12:28:19 PM PDT 24
Peak memory 200556 kb
Host smart-db1e26aa-6592-4061-94d7-151d3c0ba5c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251664312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.4251664312
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.4182920749
Short name T585
Test name
Test status
Simulation time 134487958 ps
CPU time 1.09 seconds
Started Jun 06 12:28:09 PM PDT 24
Finished Jun 06 12:28:12 PM PDT 24
Peak memory 208628 kb
Host smart-8130e441-eaa5-4721-bd43-47bf105728ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182920749 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.4182920749
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.4190556077
Short name T617
Test name
Test status
Simulation time 63744615 ps
CPU time 0.85 seconds
Started Jun 06 12:28:26 PM PDT 24
Finished Jun 06 12:28:28 PM PDT 24
Peak memory 200288 kb
Host smart-9321b4df-62e8-46ab-8008-6dae6a43ee67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190556077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.4190556077
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.572861622
Short name T600
Test name
Test status
Simulation time 217364301 ps
CPU time 1.5 seconds
Started Jun 06 12:28:08 PM PDT 24
Finished Jun 06 12:28:11 PM PDT 24
Peak memory 200492 kb
Host smart-7fa64626-386e-4361-8b12-aa270fef71f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572861622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.572861622
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.390525881
Short name T93
Test name
Test status
Simulation time 134355556 ps
CPU time 1.77 seconds
Started Jun 06 12:28:16 PM PDT 24
Finished Jun 06 12:28:19 PM PDT 24
Peak memory 211104 kb
Host smart-4edd7b1c-5ebc-4bc1-a63a-747880ae5fa9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390525881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.390525881
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.25514589
Short name T591
Test name
Test status
Simulation time 882501377 ps
CPU time 3.39 seconds
Started Jun 06 12:28:11 PM PDT 24
Finished Jun 06 12:28:15 PM PDT 24
Peak memory 200568 kb
Host smart-1faa73f1-2c30-4a0f-97cf-4877c99e78e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25514589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.25514589
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2841591059
Short name T191
Test name
Test status
Simulation time 67947921 ps
CPU time 0.76 seconds
Started Jun 06 12:28:31 PM PDT 24
Finished Jun 06 12:28:33 PM PDT 24
Peak memory 200488 kb
Host smart-4110de85-36c0-47f4-9cd5-7ac7ccd553c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841591059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2841591059
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.4190338057
Short name T467
Test name
Test status
Simulation time 2370432769 ps
CPU time 8.08 seconds
Started Jun 06 12:28:28 PM PDT 24
Finished Jun 06 12:28:38 PM PDT 24
Peak memory 218244 kb
Host smart-dd1ce601-089f-48b5-82ee-de815c548769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190338057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.4190338057
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1155633295
Short name T474
Test name
Test status
Simulation time 244483020 ps
CPU time 1.12 seconds
Started Jun 06 12:28:28 PM PDT 24
Finished Jun 06 12:28:30 PM PDT 24
Peak memory 218088 kb
Host smart-3e14e451-5b7f-46df-b603-f84235fbc751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155633295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1155633295
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1113188613
Short name T68
Test name
Test status
Simulation time 17097088599 ps
CPU time 27.86 seconds
Started Jun 06 12:28:28 PM PDT 24
Finished Jun 06 12:28:57 PM PDT 24
Peak memory 217632 kb
Host smart-03ac3b3c-4bb4-42ac-bfd1-3bddba4c816f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113188613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1113188613
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.768862510
Short name T41
Test name
Test status
Simulation time 128912072 ps
CPU time 1.14 seconds
Started Jun 06 12:28:28 PM PDT 24
Finished Jun 06 12:28:30 PM PDT 24
Peak memory 200960 kb
Host smart-2d98f470-2f84-42c0-a177-373787526a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768862510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.768862510
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3105935796
Short name T331
Test name
Test status
Simulation time 3301133681 ps
CPU time 12.58 seconds
Started Jun 06 12:28:29 PM PDT 24
Finished Jun 06 12:28:43 PM PDT 24
Peak memory 201052 kb
Host smart-365ebb57-083a-4c0f-b797-e02919edb488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105935796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3105935796
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1739637728
Short name T329
Test name
Test status
Simulation time 455620139 ps
CPU time 2.63 seconds
Started Jun 06 12:28:28 PM PDT 24
Finished Jun 06 12:28:32 PM PDT 24
Peak memory 200740 kb
Host smart-0f21f873-5d2b-4978-95e0-6b1052c1fbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739637728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1739637728
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3945046350
Short name T436
Test name
Test status
Simulation time 93700333 ps
CPU time 0.91 seconds
Started Jun 06 12:28:26 PM PDT 24
Finished Jun 06 12:28:28 PM PDT 24
Peak memory 200748 kb
Host smart-345cd532-05d2-4153-827e-99a32e78e910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945046350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3945046350
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2331167698
Short name T160
Test name
Test status
Simulation time 83781720 ps
CPU time 0.75 seconds
Started Jun 06 12:28:41 PM PDT 24
Finished Jun 06 12:28:43 PM PDT 24
Peak memory 200648 kb
Host smart-bfa94d9d-6f0e-4237-bedc-41318ecd943e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331167698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2331167698
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3796257621
Short name T230
Test name
Test status
Simulation time 1880751258 ps
CPU time 7.33 seconds
Started Jun 06 12:28:35 PM PDT 24
Finished Jun 06 12:28:44 PM PDT 24
Peak memory 221844 kb
Host smart-50acbfcb-778c-441e-b7bc-cdfd8625f02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796257621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3796257621
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2962678571
Short name T498
Test name
Test status
Simulation time 248407617 ps
CPU time 1.1 seconds
Started Jun 06 12:28:27 PM PDT 24
Finished Jun 06 12:28:30 PM PDT 24
Peak memory 217944 kb
Host smart-21148a87-6905-483d-8304-f976315bfafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962678571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2962678571
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.894043869
Short name T371
Test name
Test status
Simulation time 193366026 ps
CPU time 0.91 seconds
Started Jun 06 12:28:26 PM PDT 24
Finished Jun 06 12:28:28 PM PDT 24
Peak memory 200496 kb
Host smart-42e2c4be-ee45-4dd4-ac0a-56997221e385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894043869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.894043869
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1673834116
Short name T418
Test name
Test status
Simulation time 1533954952 ps
CPU time 6.39 seconds
Started Jun 06 12:28:28 PM PDT 24
Finished Jun 06 12:28:36 PM PDT 24
Peak memory 200988 kb
Host smart-0f20381a-d027-4a09-aeaa-44103aa0c99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673834116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1673834116
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1926675550
Short name T142
Test name
Test status
Simulation time 143150023 ps
CPU time 1.11 seconds
Started Jun 06 12:28:23 PM PDT 24
Finished Jun 06 12:28:26 PM PDT 24
Peak memory 200752 kb
Host smart-17d050a7-1ad6-4f42-a0b8-f401146ba127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926675550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1926675550
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1843478158
Short name T206
Test name
Test status
Simulation time 252738646 ps
CPU time 1.44 seconds
Started Jun 06 12:28:27 PM PDT 24
Finished Jun 06 12:28:30 PM PDT 24
Peak memory 200940 kb
Host smart-9c39e341-3668-42fd-9b39-44173990f587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843478158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1843478158
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2328088012
Short name T281
Test name
Test status
Simulation time 2040212576 ps
CPU time 7.84 seconds
Started Jun 06 12:28:29 PM PDT 24
Finished Jun 06 12:28:38 PM PDT 24
Peak memory 200996 kb
Host smart-a5f1d3ca-147b-48cd-8243-b68e07be09cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328088012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2328088012
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.158235686
Short name T398
Test name
Test status
Simulation time 435583962 ps
CPU time 2.26 seconds
Started Jun 06 12:28:29 PM PDT 24
Finished Jun 06 12:28:33 PM PDT 24
Peak memory 200752 kb
Host smart-c7f0c844-6780-4f57-9cf8-2774b37e95d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158235686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.158235686
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3218866041
Short name T165
Test name
Test status
Simulation time 141861934 ps
CPU time 1.1 seconds
Started Jun 06 12:28:28 PM PDT 24
Finished Jun 06 12:28:30 PM PDT 24
Peak memory 200772 kb
Host smart-97ad4b43-855c-4c38-9567-f4ddac75872e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218866041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3218866041
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3791233533
Short name T536
Test name
Test status
Simulation time 71620709 ps
CPU time 0.79 seconds
Started Jun 06 12:28:45 PM PDT 24
Finished Jun 06 12:28:47 PM PDT 24
Peak memory 200640 kb
Host smart-e9a9520c-11e8-4b11-8733-d46fb96c4624
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791233533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3791233533
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1736989919
Short name T375
Test name
Test status
Simulation time 1233502873 ps
CPU time 5.42 seconds
Started Jun 06 12:28:45 PM PDT 24
Finished Jun 06 12:28:52 PM PDT 24
Peak memory 218432 kb
Host smart-87641713-edee-4f20-aa77-d976bc0b9f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736989919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1736989919
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3172049957
Short name T255
Test name
Test status
Simulation time 244197583 ps
CPU time 1.21 seconds
Started Jun 06 12:28:45 PM PDT 24
Finished Jun 06 12:28:47 PM PDT 24
Peak memory 217928 kb
Host smart-5e6e2faa-d11d-4128-810c-1ece19aca0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172049957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3172049957
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.1919403540
Short name T235
Test name
Test status
Simulation time 220495849 ps
CPU time 0.96 seconds
Started Jun 06 12:28:45 PM PDT 24
Finished Jun 06 12:28:47 PM PDT 24
Peak memory 200576 kb
Host smart-f358ff67-ba41-41b9-9f88-92090912b1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919403540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.1919403540
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2854780124
Short name T40
Test name
Test status
Simulation time 1812205823 ps
CPU time 6.83 seconds
Started Jun 06 12:28:47 PM PDT 24
Finished Jun 06 12:28:55 PM PDT 24
Peak memory 200896 kb
Host smart-01db4c9d-474c-44a9-92d4-d5f3d19756b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854780124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2854780124
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.709961568
Short name T126
Test name
Test status
Simulation time 192537948 ps
CPU time 1.27 seconds
Started Jun 06 12:28:44 PM PDT 24
Finished Jun 06 12:28:46 PM PDT 24
Peak memory 200840 kb
Host smart-ee6efe8e-9d87-4b2e-a158-6863c842dc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709961568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.709961568
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1578775426
Short name T516
Test name
Test status
Simulation time 258940376 ps
CPU time 1.52 seconds
Started Jun 06 12:28:45 PM PDT 24
Finished Jun 06 12:28:47 PM PDT 24
Peak memory 201028 kb
Host smart-b616e376-dcdb-4418-b035-36f8be41ca33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578775426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1578775426
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2070760532
Short name T12
Test name
Test status
Simulation time 4704402083 ps
CPU time 18.16 seconds
Started Jun 06 12:28:46 PM PDT 24
Finished Jun 06 12:29:06 PM PDT 24
Peak memory 209244 kb
Host smart-0d499726-8f6f-446f-9932-3abc3ffcf04f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070760532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2070760532
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1331262091
Short name T378
Test name
Test status
Simulation time 110608826 ps
CPU time 1.37 seconds
Started Jun 06 12:28:45 PM PDT 24
Finished Jun 06 12:28:48 PM PDT 24
Peak memory 200828 kb
Host smart-58bbca8b-19f3-454c-846f-64d507efb98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331262091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1331262091
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3222933077
Short name T414
Test name
Test status
Simulation time 101370633 ps
CPU time 0.88 seconds
Started Jun 06 12:28:46 PM PDT 24
Finished Jun 06 12:28:48 PM PDT 24
Peak memory 200772 kb
Host smart-5ebc3237-224a-4538-8785-a0767b0b1957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222933077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3222933077
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2107585922
Short name T472
Test name
Test status
Simulation time 66541046 ps
CPU time 0.78 seconds
Started Jun 06 12:28:52 PM PDT 24
Finished Jun 06 12:28:54 PM PDT 24
Peak memory 200640 kb
Host smart-36be641e-4892-41ab-9b88-94fb9cba32fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107585922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2107585922
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1567972230
Short name T482
Test name
Test status
Simulation time 244154235 ps
CPU time 0.98 seconds
Started Jun 06 12:28:51 PM PDT 24
Finished Jun 06 12:28:53 PM PDT 24
Peak memory 217932 kb
Host smart-2765af4e-3bc7-42c9-8d63-1314a04efbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567972230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1567972230
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.987823120
Short name T15
Test name
Test status
Simulation time 188034037 ps
CPU time 0.92 seconds
Started Jun 06 12:28:45 PM PDT 24
Finished Jun 06 12:28:47 PM PDT 24
Peak memory 200512 kb
Host smart-0be51425-fab8-4bda-aebc-ffbf097ed04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987823120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.987823120
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1567826799
Short name T407
Test name
Test status
Simulation time 835079360 ps
CPU time 3.83 seconds
Started Jun 06 12:28:50 PM PDT 24
Finished Jun 06 12:28:54 PM PDT 24
Peak memory 201040 kb
Host smart-6a45183a-443d-4cb6-9adc-78d101655741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567826799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1567826799
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.427157884
Short name T282
Test name
Test status
Simulation time 155611621 ps
CPU time 1.22 seconds
Started Jun 06 12:28:46 PM PDT 24
Finished Jun 06 12:28:49 PM PDT 24
Peak memory 200704 kb
Host smart-aa8426ae-4eee-4323-89a9-67a510edacc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427157884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.427157884
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1882078148
Short name T267
Test name
Test status
Simulation time 115481187 ps
CPU time 1.17 seconds
Started Jun 06 12:28:45 PM PDT 24
Finished Jun 06 12:28:48 PM PDT 24
Peak memory 200876 kb
Host smart-a728904c-86c5-4e9f-a633-9ef237aa2237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882078148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1882078148
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1367310197
Short name T505
Test name
Test status
Simulation time 14439555170 ps
CPU time 43.99 seconds
Started Jun 06 12:28:51 PM PDT 24
Finished Jun 06 12:29:36 PM PDT 24
Peak memory 201124 kb
Host smart-6fce18b4-61ab-48c6-988d-a7435c3faab9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367310197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1367310197
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2098661876
Short name T512
Test name
Test status
Simulation time 302699657 ps
CPU time 1.99 seconds
Started Jun 06 12:28:47 PM PDT 24
Finished Jun 06 12:28:50 PM PDT 24
Peak memory 209032 kb
Host smart-5e2b77e2-fa32-4102-9649-7ba9ba5a93e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098661876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2098661876
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.636196820
Short name T163
Test name
Test status
Simulation time 184747534 ps
CPU time 1.26 seconds
Started Jun 06 12:28:41 PM PDT 24
Finished Jun 06 12:28:44 PM PDT 24
Peak memory 200788 kb
Host smart-cd247a5c-e067-4c95-b0b7-5a8eadda2474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636196820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.636196820
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.4247283055
Short name T45
Test name
Test status
Simulation time 83320180 ps
CPU time 0.78 seconds
Started Jun 06 12:28:47 PM PDT 24
Finished Jun 06 12:28:49 PM PDT 24
Peak memory 200520 kb
Host smart-cdee78dc-5508-4ce5-aaa2-baa0e80c05ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247283055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.4247283055
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3642863382
Short name T58
Test name
Test status
Simulation time 1228293569 ps
CPU time 5.66 seconds
Started Jun 06 12:28:46 PM PDT 24
Finished Jun 06 12:28:53 PM PDT 24
Peak memory 217616 kb
Host smart-2c841a87-8aa8-4da1-b058-03e922f43f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642863382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3642863382
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1211184580
Short name T476
Test name
Test status
Simulation time 245081448 ps
CPU time 1.02 seconds
Started Jun 06 12:28:58 PM PDT 24
Finished Jun 06 12:29:01 PM PDT 24
Peak memory 217936 kb
Host smart-760496a5-91df-4e70-9286-d248012eca36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211184580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1211184580
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2794090454
Short name T501
Test name
Test status
Simulation time 147151709 ps
CPU time 0.82 seconds
Started Jun 06 12:28:45 PM PDT 24
Finished Jun 06 12:28:47 PM PDT 24
Peak memory 200316 kb
Host smart-69fd9ce0-7e27-4f5e-bddc-15ada8cf4d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794090454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2794090454
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3995617704
Short name T243
Test name
Test status
Simulation time 847113280 ps
CPU time 4.31 seconds
Started Jun 06 12:28:42 PM PDT 24
Finished Jun 06 12:28:48 PM PDT 24
Peak memory 200928 kb
Host smart-88b3b054-7d0f-439f-924d-b31e138b1ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995617704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3995617704
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3266037909
Short name T531
Test name
Test status
Simulation time 183359295 ps
CPU time 1.16 seconds
Started Jun 06 12:28:43 PM PDT 24
Finished Jun 06 12:28:45 PM PDT 24
Peak memory 200760 kb
Host smart-63f2230e-d525-4ad2-879f-5555d4418417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266037909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3266037909
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.433945467
Short name T100
Test name
Test status
Simulation time 257828826 ps
CPU time 1.43 seconds
Started Jun 06 12:28:51 PM PDT 24
Finished Jun 06 12:28:53 PM PDT 24
Peak memory 200988 kb
Host smart-5bb9a406-6f75-4efd-8756-225f883ca74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433945467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.433945467
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2097962486
Short name T204
Test name
Test status
Simulation time 3026547020 ps
CPU time 11.68 seconds
Started Jun 06 12:28:54 PM PDT 24
Finished Jun 06 12:29:07 PM PDT 24
Peak memory 209888 kb
Host smart-02b27b32-4922-449d-8c9c-ec7ce0f54102
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097962486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2097962486
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1863708943
Short name T455
Test name
Test status
Simulation time 512792140 ps
CPU time 2.5 seconds
Started Jun 06 12:28:46 PM PDT 24
Finished Jun 06 12:28:50 PM PDT 24
Peak memory 200760 kb
Host smart-97895ece-ecdf-48dd-9c11-9898fbce2543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863708943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1863708943
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.635092104
Short name T315
Test name
Test status
Simulation time 155282647 ps
CPU time 1.07 seconds
Started Jun 06 12:28:52 PM PDT 24
Finished Jun 06 12:28:54 PM PDT 24
Peak memory 200800 kb
Host smart-2a4aa1b2-24ab-40b1-bab0-0ee883fcfbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635092104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.635092104
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3906817597
Short name T208
Test name
Test status
Simulation time 98118639 ps
CPU time 0.81 seconds
Started Jun 06 12:28:47 PM PDT 24
Finished Jun 06 12:28:49 PM PDT 24
Peak memory 200512 kb
Host smart-235cb711-3cb3-4b99-b053-53a41b8d56df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906817597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3906817597
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3020887645
Short name T515
Test name
Test status
Simulation time 1217492247 ps
CPU time 5.35 seconds
Started Jun 06 12:28:52 PM PDT 24
Finished Jun 06 12:28:58 PM PDT 24
Peak memory 222324 kb
Host smart-9fe11c77-8943-4990-97eb-255a53018ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020887645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3020887645
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3579279695
Short name T217
Test name
Test status
Simulation time 245775123 ps
CPU time 1.03 seconds
Started Jun 06 12:28:47 PM PDT 24
Finished Jun 06 12:28:49 PM PDT 24
Peak memory 218100 kb
Host smart-77998e39-06ac-4ecd-b595-5658638d757d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579279695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.3579279695
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3902817056
Short name T166
Test name
Test status
Simulation time 170991905 ps
CPU time 0.84 seconds
Started Jun 06 12:28:52 PM PDT 24
Finished Jun 06 12:28:54 PM PDT 24
Peak memory 200624 kb
Host smart-3865007d-d899-4d94-903a-4437366abe37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902817056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3902817056
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.64423819
Short name T174
Test name
Test status
Simulation time 692168747 ps
CPU time 3.88 seconds
Started Jun 06 12:28:55 PM PDT 24
Finished Jun 06 12:29:01 PM PDT 24
Peak memory 200924 kb
Host smart-1e3b6e83-97b5-4738-aeb3-a4f7622328ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64423819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.64423819
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2515499268
Short name T528
Test name
Test status
Simulation time 174869261 ps
CPU time 1.15 seconds
Started Jun 06 12:28:52 PM PDT 24
Finished Jun 06 12:28:54 PM PDT 24
Peak memory 200800 kb
Host smart-358bbb9a-4d93-4aa3-8a5d-9896e1151b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515499268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2515499268
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.721641725
Short name T349
Test name
Test status
Simulation time 118235374 ps
CPU time 1.11 seconds
Started Jun 06 12:28:55 PM PDT 24
Finished Jun 06 12:28:57 PM PDT 24
Peak memory 200896 kb
Host smart-2fbf3f4d-8903-473e-b373-452ae1742db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721641725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.721641725
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1328873693
Short name T256
Test name
Test status
Simulation time 5270451360 ps
CPU time 23.98 seconds
Started Jun 06 12:28:47 PM PDT 24
Finished Jun 06 12:29:12 PM PDT 24
Peak memory 209188 kb
Host smart-387267df-2d0f-41e8-9752-8b6ab62ab193
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328873693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1328873693
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3732894484
Short name T275
Test name
Test status
Simulation time 119582276 ps
CPU time 1.52 seconds
Started Jun 06 12:28:55 PM PDT 24
Finished Jun 06 12:28:58 PM PDT 24
Peak memory 208908 kb
Host smart-420323b1-2db0-44fd-9411-68150654bae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732894484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3732894484
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2971717170
Short name T479
Test name
Test status
Simulation time 94318067 ps
CPU time 0.82 seconds
Started Jun 06 12:28:51 PM PDT 24
Finished Jun 06 12:28:53 PM PDT 24
Peak memory 200792 kb
Host smart-83686a10-ee39-42cc-af23-33dc877e80e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971717170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2971717170
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.2725482347
Short name T253
Test name
Test status
Simulation time 74123514 ps
CPU time 0.77 seconds
Started Jun 06 12:28:43 PM PDT 24
Finished Jun 06 12:28:45 PM PDT 24
Peak memory 200580 kb
Host smart-ff6c181a-16e6-4b19-85f3-1d0b71d9b9f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725482347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2725482347
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.718004299
Short name T466
Test name
Test status
Simulation time 244152973 ps
CPU time 1 seconds
Started Jun 06 12:28:50 PM PDT 24
Finished Jun 06 12:28:52 PM PDT 24
Peak memory 217952 kb
Host smart-7669f92c-43d3-4ed8-b860-de72cf719b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718004299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.718004299
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1937766112
Short name T149
Test name
Test status
Simulation time 221740642 ps
CPU time 0.96 seconds
Started Jun 06 12:28:52 PM PDT 24
Finished Jun 06 12:28:54 PM PDT 24
Peak memory 200456 kb
Host smart-a4a0bbf5-12c6-4b51-b282-0e16ee9e4219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937766112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1937766112
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.4287203348
Short name T181
Test name
Test status
Simulation time 845334076 ps
CPU time 3.76 seconds
Started Jun 06 12:28:52 PM PDT 24
Finished Jun 06 12:28:57 PM PDT 24
Peak memory 201024 kb
Host smart-8def27ff-799c-49d5-ab5f-8b85e4cc84c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287203348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.4287203348
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1473281589
Short name T405
Test name
Test status
Simulation time 106408159 ps
CPU time 0.97 seconds
Started Jun 06 12:28:49 PM PDT 24
Finished Jun 06 12:28:51 PM PDT 24
Peak memory 200772 kb
Host smart-da7bba0a-4b75-438c-bb2c-49ea4e15dc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473281589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1473281589
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.4221356737
Short name T202
Test name
Test status
Simulation time 232443371 ps
CPU time 1.38 seconds
Started Jun 06 12:28:51 PM PDT 24
Finished Jun 06 12:28:54 PM PDT 24
Peak memory 201016 kb
Host smart-ea6fd4da-55a7-4de3-a779-fdd3cc9d87cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221356737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.4221356737
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3799954587
Short name T439
Test name
Test status
Simulation time 4882192407 ps
CPU time 16.95 seconds
Started Jun 06 12:28:51 PM PDT 24
Finished Jun 06 12:29:09 PM PDT 24
Peak memory 201140 kb
Host smart-7f6ddf3b-cf13-4d4d-9439-f4efbc65ff80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799954587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3799954587
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3684976958
Short name T424
Test name
Test status
Simulation time 220404428 ps
CPU time 1.28 seconds
Started Jun 06 12:28:53 PM PDT 24
Finished Jun 06 12:28:55 PM PDT 24
Peak memory 200668 kb
Host smart-3caa6256-6bb8-4787-b9a8-64c56198302d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684976958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3684976958
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2719727833
Short name T133
Test name
Test status
Simulation time 67652546 ps
CPU time 0.77 seconds
Started Jun 06 12:29:17 PM PDT 24
Finished Jun 06 12:29:20 PM PDT 24
Peak memory 200648 kb
Host smart-c695d1ce-9c6b-4ed7-a657-1efc6b6c5912
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719727833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2719727833
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.244673842
Short name T530
Test name
Test status
Simulation time 2184212370 ps
CPU time 7.39 seconds
Started Jun 06 12:28:51 PM PDT 24
Finished Jun 06 12:28:59 PM PDT 24
Peak memory 218572 kb
Host smart-e6d2e638-ddbf-4c68-b706-a7a6ead0f2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244673842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.244673842
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1938729637
Short name T270
Test name
Test status
Simulation time 243616470 ps
CPU time 1.05 seconds
Started Jun 06 12:29:09 PM PDT 24
Finished Jun 06 12:29:11 PM PDT 24
Peak memory 218020 kb
Host smart-cda5e7cd-dea9-45c9-a7c8-04a932ab3bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938729637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1938729637
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3772909803
Short name T212
Test name
Test status
Simulation time 90240773 ps
CPU time 0.72 seconds
Started Jun 06 12:29:00 PM PDT 24
Finished Jun 06 12:29:03 PM PDT 24
Peak memory 200572 kb
Host smart-71744416-8d4c-42c0-b80f-677a11b929e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772909803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3772909803
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1618488260
Short name T413
Test name
Test status
Simulation time 1630301319 ps
CPU time 6.43 seconds
Started Jun 06 12:28:54 PM PDT 24
Finished Jun 06 12:29:02 PM PDT 24
Peak memory 200900 kb
Host smart-3ff22788-b721-4e0a-a144-3efae19458c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618488260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1618488260
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3764487233
Short name T143
Test name
Test status
Simulation time 102998536 ps
CPU time 0.95 seconds
Started Jun 06 12:29:00 PM PDT 24
Finished Jun 06 12:29:03 PM PDT 24
Peak memory 200768 kb
Host smart-f7248c9f-3dfe-4f53-96c8-b5c050d0511f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764487233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3764487233
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1184616218
Short name T508
Test name
Test status
Simulation time 117121909 ps
CPU time 1.2 seconds
Started Jun 06 12:28:46 PM PDT 24
Finished Jun 06 12:28:49 PM PDT 24
Peak memory 200988 kb
Host smart-062212ad-c3e9-430f-8c22-dddb635195d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184616218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1184616218
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.720584626
Short name T327
Test name
Test status
Simulation time 106282637 ps
CPU time 1.29 seconds
Started Jun 06 12:28:58 PM PDT 24
Finished Jun 06 12:29:01 PM PDT 24
Peak memory 200792 kb
Host smart-39037bc0-6f3c-48c8-9834-8ccb7c523fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720584626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.720584626
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2401770977
Short name T376
Test name
Test status
Simulation time 74441037 ps
CPU time 0.81 seconds
Started Jun 06 12:29:10 PM PDT 24
Finished Jun 06 12:29:13 PM PDT 24
Peak memory 200592 kb
Host smart-64914dbd-ba23-413d-8b0d-87293d77572e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401770977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2401770977
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.201375943
Short name T248
Test name
Test status
Simulation time 1907540879 ps
CPU time 7.44 seconds
Started Jun 06 12:28:58 PM PDT 24
Finished Jun 06 12:29:07 PM PDT 24
Peak memory 222440 kb
Host smart-a566f21e-00c9-48ed-8007-a5d922efbee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201375943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.201375943
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3186252851
Short name T488
Test name
Test status
Simulation time 243866965 ps
CPU time 1.01 seconds
Started Jun 06 12:28:55 PM PDT 24
Finished Jun 06 12:28:57 PM PDT 24
Peak memory 218100 kb
Host smart-606f2131-f21d-4f9f-a3ba-77c5339647ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186252851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3186252851
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1439275822
Short name T17
Test name
Test status
Simulation time 130916763 ps
CPU time 0.78 seconds
Started Jun 06 12:28:55 PM PDT 24
Finished Jun 06 12:28:58 PM PDT 24
Peak memory 200532 kb
Host smart-29ac61fd-eb3f-40d5-a118-7b57370022d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439275822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1439275822
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.4088676471
Short name T104
Test name
Test status
Simulation time 786624545 ps
CPU time 3.81 seconds
Started Jun 06 12:28:56 PM PDT 24
Finished Jun 06 12:29:02 PM PDT 24
Peak memory 200932 kb
Host smart-ecee5940-6026-4c27-a00f-0c6f68d93fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088676471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.4088676471
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3729061434
Short name T259
Test name
Test status
Simulation time 178791988 ps
CPU time 1.22 seconds
Started Jun 06 12:29:18 PM PDT 24
Finished Jun 06 12:29:21 PM PDT 24
Peak memory 200780 kb
Host smart-3814eb4d-ea3a-4481-b997-d734b0b808f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729061434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3729061434
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.4167430358
Short name T80
Test name
Test status
Simulation time 111369709 ps
CPU time 1.23 seconds
Started Jun 06 12:28:51 PM PDT 24
Finished Jun 06 12:28:54 PM PDT 24
Peak memory 200900 kb
Host smart-8ece84a6-2cbe-42c4-8531-30527a3e5ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167430358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.4167430358
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.4105170767
Short name T105
Test name
Test status
Simulation time 5627403537 ps
CPU time 20.87 seconds
Started Jun 06 12:28:59 PM PDT 24
Finished Jun 06 12:29:22 PM PDT 24
Peak memory 200956 kb
Host smart-a81c34a9-1f3a-4bf6-abce-0d75887ba312
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105170767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.4105170767
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.4028796722
Short name T190
Test name
Test status
Simulation time 252415784 ps
CPU time 1.74 seconds
Started Jun 06 12:28:55 PM PDT 24
Finished Jun 06 12:28:59 PM PDT 24
Peak memory 200692 kb
Host smart-71a849a1-8f2b-44e5-b2e7-172541f6e950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028796722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.4028796722
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2893450184
Short name T101
Test name
Test status
Simulation time 292067116 ps
CPU time 1.64 seconds
Started Jun 06 12:29:14 PM PDT 24
Finished Jun 06 12:29:18 PM PDT 24
Peak memory 200764 kb
Host smart-7fe18963-160c-4838-a16e-b99ccebf770b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893450184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2893450184
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.4210957572
Short name T338
Test name
Test status
Simulation time 77862563 ps
CPU time 0.76 seconds
Started Jun 06 12:29:10 PM PDT 24
Finished Jun 06 12:29:12 PM PDT 24
Peak memory 200584 kb
Host smart-b7fbabfe-bfe5-4ab1-ade3-71c4b8637e7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210957572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.4210957572
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.107228144
Short name T538
Test name
Test status
Simulation time 2345005984 ps
CPU time 8.47 seconds
Started Jun 06 12:28:54 PM PDT 24
Finished Jun 06 12:29:04 PM PDT 24
Peak memory 222564 kb
Host smart-dadfe688-b998-4020-8775-422c4f2033d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107228144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.107228144
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3521552770
Short name T463
Test name
Test status
Simulation time 247364551 ps
CPU time 1.05 seconds
Started Jun 06 12:28:58 PM PDT 24
Finished Jun 06 12:29:01 PM PDT 24
Peak memory 217764 kb
Host smart-81d3b4e3-2054-41b3-80cb-2dabb595d618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521552770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3521552770
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1535999434
Short name T397
Test name
Test status
Simulation time 133038310 ps
CPU time 0.79 seconds
Started Jun 06 12:28:56 PM PDT 24
Finished Jun 06 12:28:59 PM PDT 24
Peak memory 200516 kb
Host smart-ca150db3-9946-4929-9326-ef134cbda96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535999434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1535999434
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.475951175
Short name T199
Test name
Test status
Simulation time 1413549167 ps
CPU time 5.65 seconds
Started Jun 06 12:28:54 PM PDT 24
Finished Jun 06 12:29:02 PM PDT 24
Peak memory 200852 kb
Host smart-6042a87b-4e52-4677-b75d-08baa839ac94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475951175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.475951175
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2778719536
Short name T6
Test name
Test status
Simulation time 113996297 ps
CPU time 0.98 seconds
Started Jun 06 12:28:54 PM PDT 24
Finished Jun 06 12:28:57 PM PDT 24
Peak memory 200816 kb
Host smart-e872c1f4-8f31-4a6a-8e53-8ca3b7e82f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778719536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.2778719536
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1124646366
Short name T170
Test name
Test status
Simulation time 257030973 ps
CPU time 1.53 seconds
Started Jun 06 12:28:51 PM PDT 24
Finished Jun 06 12:28:54 PM PDT 24
Peak memory 200996 kb
Host smart-dafccc01-99fc-4421-99c6-c1351d86c383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124646366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1124646366
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.390406638
Short name T448
Test name
Test status
Simulation time 2802418633 ps
CPU time 11.36 seconds
Started Jun 06 12:28:55 PM PDT 24
Finished Jun 06 12:29:08 PM PDT 24
Peak memory 210644 kb
Host smart-33330e97-8d5d-4c55-8786-f32fcf893d79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390406638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.390406638
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1516849954
Short name T485
Test name
Test status
Simulation time 132955534 ps
CPU time 1.58 seconds
Started Jun 06 12:28:52 PM PDT 24
Finished Jun 06 12:28:54 PM PDT 24
Peak memory 208956 kb
Host smart-b5d4bd18-71fd-49fc-9aa7-bbfe0b9e3113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516849954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1516849954
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.992096363
Short name T396
Test name
Test status
Simulation time 114022706 ps
CPU time 0.89 seconds
Started Jun 06 12:29:01 PM PDT 24
Finished Jun 06 12:29:04 PM PDT 24
Peak memory 200748 kb
Host smart-7f0f08c0-f097-4ed0-b6a9-88f3dcf1d9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992096363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.992096363
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1005780947
Short name T74
Test name
Test status
Simulation time 79032712 ps
CPU time 0.8 seconds
Started Jun 06 12:28:59 PM PDT 24
Finished Jun 06 12:29:03 PM PDT 24
Peak memory 200588 kb
Host smart-7f422b16-943a-4a76-b58b-cf80e089fced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005780947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1005780947
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2075615760
Short name T30
Test name
Test status
Simulation time 1230297446 ps
CPU time 5.33 seconds
Started Jun 06 12:29:00 PM PDT 24
Finished Jun 06 12:29:07 PM PDT 24
Peak memory 222380 kb
Host smart-d1faf14a-d949-452e-b583-95626738805c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075615760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2075615760
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.303096740
Short name T343
Test name
Test status
Simulation time 244375727 ps
CPU time 1.18 seconds
Started Jun 06 12:28:54 PM PDT 24
Finished Jun 06 12:28:57 PM PDT 24
Peak memory 217884 kb
Host smart-b17193c9-4b30-48c3-a076-573ab2e16554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303096740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.303096740
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.28419522
Short name T408
Test name
Test status
Simulation time 96738614 ps
CPU time 0.77 seconds
Started Jun 06 12:28:55 PM PDT 24
Finished Jun 06 12:28:58 PM PDT 24
Peak memory 200588 kb
Host smart-808e3549-0bab-4950-8b07-0667eb85ecf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28419522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.28419522
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3921888169
Short name T13
Test name
Test status
Simulation time 784789914 ps
CPU time 3.91 seconds
Started Jun 06 12:28:58 PM PDT 24
Finished Jun 06 12:29:04 PM PDT 24
Peak memory 200836 kb
Host smart-2373d791-b0b2-4de1-886d-7660418e538e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921888169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3921888169
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3959925931
Short name T416
Test name
Test status
Simulation time 185956893 ps
CPU time 1.23 seconds
Started Jun 06 12:28:54 PM PDT 24
Finished Jun 06 12:28:57 PM PDT 24
Peak memory 200764 kb
Host smart-90a15ea2-0fe5-42cc-b7a1-5588537f8679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959925931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3959925931
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.3805973781
Short name T295
Test name
Test status
Simulation time 120284404 ps
CPU time 1.11 seconds
Started Jun 06 12:28:56 PM PDT 24
Finished Jun 06 12:29:00 PM PDT 24
Peak memory 200848 kb
Host smart-58ae07ee-183a-4888-a9fe-9656cd9830d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805973781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.3805973781
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2420109069
Short name T494
Test name
Test status
Simulation time 3086262878 ps
CPU time 11.64 seconds
Started Jun 06 12:29:06 PM PDT 24
Finished Jun 06 12:29:19 PM PDT 24
Peak memory 201012 kb
Host smart-ef7db9c2-e93a-4b7b-9f9b-2f15df83d673
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420109069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2420109069
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3347378575
Short name T239
Test name
Test status
Simulation time 368452974 ps
CPU time 2.29 seconds
Started Jun 06 12:28:59 PM PDT 24
Finished Jun 06 12:29:04 PM PDT 24
Peak memory 200796 kb
Host smart-2059bf91-0d4b-47d6-a6f5-9dbdb12e6df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347378575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3347378575
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.3290105392
Short name T99
Test name
Test status
Simulation time 113108818 ps
CPU time 0.92 seconds
Started Jun 06 12:28:58 PM PDT 24
Finished Jun 06 12:29:01 PM PDT 24
Peak memory 200716 kb
Host smart-3b31c367-e62f-4210-b00a-682156dacf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290105392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.3290105392
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1548053133
Short name T502
Test name
Test status
Simulation time 70232260 ps
CPU time 0.75 seconds
Started Jun 06 12:29:06 PM PDT 24
Finished Jun 06 12:29:07 PM PDT 24
Peak memory 200600 kb
Host smart-408cf4eb-fbdb-4f3f-9cf5-0161e148508d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548053133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1548053133
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3007687303
Short name T34
Test name
Test status
Simulation time 2169183012 ps
CPU time 8.22 seconds
Started Jun 06 12:29:02 PM PDT 24
Finished Jun 06 12:29:12 PM PDT 24
Peak memory 222012 kb
Host smart-19452e25-8563-4388-89be-a8a065050e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007687303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3007687303
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2616783893
Short name T400
Test name
Test status
Simulation time 243993917 ps
CPU time 1.06 seconds
Started Jun 06 12:29:17 PM PDT 24
Finished Jun 06 12:29:20 PM PDT 24
Peak memory 217892 kb
Host smart-9e1643dc-0184-412f-826a-38511754693d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616783893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2616783893
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2155678684
Short name T425
Test name
Test status
Simulation time 103790727 ps
CPU time 0.8 seconds
Started Jun 06 12:29:21 PM PDT 24
Finished Jun 06 12:29:24 PM PDT 24
Peak memory 200628 kb
Host smart-be0358c6-015d-434b-aaa2-8430202cb0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155678684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2155678684
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.4075767821
Short name T433
Test name
Test status
Simulation time 842575761 ps
CPU time 4.43 seconds
Started Jun 06 12:29:09 PM PDT 24
Finished Jun 06 12:29:15 PM PDT 24
Peak memory 201004 kb
Host smart-8634fe69-f0dd-4dc6-aead-025eaf95d498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075767821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.4075767821
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3263243162
Short name T532
Test name
Test status
Simulation time 97444455 ps
CPU time 0.96 seconds
Started Jun 06 12:28:59 PM PDT 24
Finished Jun 06 12:29:02 PM PDT 24
Peak memory 200656 kb
Host smart-3d55b73f-347c-4dc5-9047-16967d9197b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263243162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3263243162
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2135320859
Short name T196
Test name
Test status
Simulation time 232316384 ps
CPU time 1.35 seconds
Started Jun 06 12:28:59 PM PDT 24
Finished Jun 06 12:29:02 PM PDT 24
Peak memory 200828 kb
Host smart-97651bf1-d7dd-4735-9161-2776b1bfeb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135320859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2135320859
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.74588527
Short name T370
Test name
Test status
Simulation time 5695735749 ps
CPU time 25.62 seconds
Started Jun 06 12:29:02 PM PDT 24
Finished Jun 06 12:29:29 PM PDT 24
Peak memory 209308 kb
Host smart-22392ac1-c2f3-4e18-bb94-bcc71fa9aa07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74588527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.74588527
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1322693890
Short name T136
Test name
Test status
Simulation time 261119155 ps
CPU time 1.79 seconds
Started Jun 06 12:28:54 PM PDT 24
Finished Jun 06 12:28:58 PM PDT 24
Peak memory 200648 kb
Host smart-d899c1e6-4d65-45bd-a2ae-911c66f34326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322693890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1322693890
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2465138611
Short name T529
Test name
Test status
Simulation time 229162205 ps
CPU time 1.31 seconds
Started Jun 06 12:28:58 PM PDT 24
Finished Jun 06 12:29:02 PM PDT 24
Peak memory 200688 kb
Host smart-6531e60a-1479-490c-99ba-e1368694ffc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465138611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2465138611
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2609156763
Short name T218
Test name
Test status
Simulation time 73366504 ps
CPU time 0.77 seconds
Started Jun 06 12:28:31 PM PDT 24
Finished Jun 06 12:28:33 PM PDT 24
Peak memory 200600 kb
Host smart-6a4a1230-d211-46e2-9c1c-1e48a90a5cb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609156763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2609156763
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3593140989
Short name T464
Test name
Test status
Simulation time 2356015556 ps
CPU time 7.97 seconds
Started Jun 06 12:28:36 PM PDT 24
Finished Jun 06 12:28:46 PM PDT 24
Peak memory 222232 kb
Host smart-cad0e9b1-2847-43a5-86b8-32f2c2ff4bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593140989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3593140989
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2543692483
Short name T257
Test name
Test status
Simulation time 243164405 ps
CPU time 1.19 seconds
Started Jun 06 12:28:28 PM PDT 24
Finished Jun 06 12:28:31 PM PDT 24
Peak memory 218024 kb
Host smart-5bbeb3be-55fb-443c-90ca-0f9c1fd42a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543692483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2543692483
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.4083841805
Short name T490
Test name
Test status
Simulation time 99398521 ps
CPU time 0.75 seconds
Started Jun 06 12:28:37 PM PDT 24
Finished Jun 06 12:28:39 PM PDT 24
Peak memory 200520 kb
Host smart-45e4bba4-8d70-45da-a95a-136ababc97c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083841805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.4083841805
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1399943956
Short name T489
Test name
Test status
Simulation time 1023629112 ps
CPU time 5.24 seconds
Started Jun 06 12:28:35 PM PDT 24
Finished Jun 06 12:28:42 PM PDT 24
Peak memory 200940 kb
Host smart-043e2b9b-aa95-42a2-82bc-e99089fba57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399943956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1399943956
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2241024427
Short name T72
Test name
Test status
Simulation time 16848994979 ps
CPU time 25.77 seconds
Started Jun 06 12:28:34 PM PDT 24
Finished Jun 06 12:29:01 PM PDT 24
Peak memory 217524 kb
Host smart-f0fa4333-ea0f-4293-a05b-4012645277b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241024427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2241024427
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.390373106
Short name T491
Test name
Test status
Simulation time 142438897 ps
CPU time 1.06 seconds
Started Jun 06 12:28:36 PM PDT 24
Finished Jun 06 12:28:39 PM PDT 24
Peak memory 200840 kb
Host smart-ec0ef111-86e7-439f-9573-e6d9396d0269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390373106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.390373106
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.422239008
Short name T324
Test name
Test status
Simulation time 120944627 ps
CPU time 1.26 seconds
Started Jun 06 12:28:35 PM PDT 24
Finished Jun 06 12:28:38 PM PDT 24
Peak memory 200984 kb
Host smart-b4bbbc06-eacf-43fb-aca8-c69899bf3d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422239008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.422239008
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.3213802420
Short name T311
Test name
Test status
Simulation time 1228340722 ps
CPU time 6.95 seconds
Started Jun 06 12:28:36 PM PDT 24
Finished Jun 06 12:28:45 PM PDT 24
Peak memory 200552 kb
Host smart-3b9d0242-f389-4de8-86ce-0cee686300f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213802420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3213802420
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2634346102
Short name T209
Test name
Test status
Simulation time 141826696 ps
CPU time 1.73 seconds
Started Jun 06 12:28:34 PM PDT 24
Finished Jun 06 12:28:37 PM PDT 24
Peak memory 200764 kb
Host smart-eda5344d-a962-4ecb-8a8e-1dc04fd234d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634346102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2634346102
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2800001523
Short name T183
Test name
Test status
Simulation time 148398673 ps
CPU time 1.22 seconds
Started Jun 06 12:28:32 PM PDT 24
Finished Jun 06 12:28:34 PM PDT 24
Peak memory 200608 kb
Host smart-45d9ed98-e902-4932-af4f-55f311a71b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800001523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2800001523
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.737697666
Short name T167
Test name
Test status
Simulation time 77948184 ps
CPU time 0.74 seconds
Started Jun 06 12:28:57 PM PDT 24
Finished Jun 06 12:29:00 PM PDT 24
Peak memory 200552 kb
Host smart-73bcb507-b81e-4370-90ba-1c089949a447
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737697666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.737697666
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1852790601
Short name T395
Test name
Test status
Simulation time 1228508065 ps
CPU time 5.43 seconds
Started Jun 06 12:28:52 PM PDT 24
Finished Jun 06 12:28:59 PM PDT 24
Peak memory 218416 kb
Host smart-cd8ab165-f64b-40e5-8360-5300504c0206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852790601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1852790601
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3803997200
Short name T503
Test name
Test status
Simulation time 246578450 ps
CPU time 1.04 seconds
Started Jun 06 12:29:00 PM PDT 24
Finished Jun 06 12:29:03 PM PDT 24
Peak memory 217996 kb
Host smart-ecb5e056-674e-411f-9390-56f0e4823dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803997200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3803997200
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1224427022
Short name T162
Test name
Test status
Simulation time 162192626 ps
CPU time 0.86 seconds
Started Jun 06 12:29:12 PM PDT 24
Finished Jun 06 12:29:14 PM PDT 24
Peak memory 200516 kb
Host smart-c124dc98-01e0-4923-8f3b-b1ef23d9b79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224427022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1224427022
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2043279788
Short name T393
Test name
Test status
Simulation time 878326364 ps
CPU time 4.28 seconds
Started Jun 06 12:29:12 PM PDT 24
Finished Jun 06 12:29:18 PM PDT 24
Peak memory 200972 kb
Host smart-5e17757e-0d86-4a6c-b7ef-9602bcef4b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043279788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2043279788
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3535513996
Short name T294
Test name
Test status
Simulation time 108401988 ps
CPU time 1.01 seconds
Started Jun 06 12:29:09 PM PDT 24
Finished Jun 06 12:29:11 PM PDT 24
Peak memory 200712 kb
Host smart-90c55492-8d4a-453a-b192-13fa00f586da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535513996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3535513996
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.256650361
Short name T232
Test name
Test status
Simulation time 256413685 ps
CPU time 1.46 seconds
Started Jun 06 12:28:57 PM PDT 24
Finished Jun 06 12:29:01 PM PDT 24
Peak memory 200848 kb
Host smart-7a202a8c-757b-4032-9050-e496d95de6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256650361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.256650361
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.1245736262
Short name T245
Test name
Test status
Simulation time 4783143238 ps
CPU time 16.34 seconds
Started Jun 06 12:28:59 PM PDT 24
Finished Jun 06 12:29:18 PM PDT 24
Peak memory 210324 kb
Host smart-3ac701b8-350c-428d-b3b8-e98a5159e6b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245736262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1245736262
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.874595746
Short name T274
Test name
Test status
Simulation time 144956504 ps
CPU time 1.82 seconds
Started Jun 06 12:28:52 PM PDT 24
Finished Jun 06 12:28:55 PM PDT 24
Peak memory 200744 kb
Host smart-78fef1ad-f238-449e-a3c2-f978073a5a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874595746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.874595746
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.260170641
Short name T10
Test name
Test status
Simulation time 129582186 ps
CPU time 0.92 seconds
Started Jun 06 12:29:15 PM PDT 24
Finished Jun 06 12:29:17 PM PDT 24
Peak memory 200764 kb
Host smart-423da338-f21b-4b7e-acc8-ef7ac196d8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260170641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.260170641
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1162873270
Short name T426
Test name
Test status
Simulation time 65188240 ps
CPU time 0.73 seconds
Started Jun 06 12:29:13 PM PDT 24
Finished Jun 06 12:29:15 PM PDT 24
Peak memory 200500 kb
Host smart-fc61f3b3-6667-4425-8aaf-15db694edd41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162873270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1162873270
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1711070802
Short name T238
Test name
Test status
Simulation time 1228708641 ps
CPU time 5.35 seconds
Started Jun 06 12:29:15 PM PDT 24
Finished Jun 06 12:29:22 PM PDT 24
Peak memory 222448 kb
Host smart-386460b7-b4e5-4d38-a371-5e7998766ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711070802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1711070802
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3761437882
Short name T127
Test name
Test status
Simulation time 244079154 ps
CPU time 1.15 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:25 PM PDT 24
Peak memory 217936 kb
Host smart-343f5065-8f5c-4ea0-8d63-cdce0d7cdf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761437882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3761437882
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3214787041
Short name T320
Test name
Test status
Simulation time 82496354 ps
CPU time 0.76 seconds
Started Jun 06 12:29:14 PM PDT 24
Finished Jun 06 12:29:16 PM PDT 24
Peak memory 200624 kb
Host smart-39325e4d-fbc1-4e7d-9164-6ac752250bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214787041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3214787041
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.244748793
Short name T317
Test name
Test status
Simulation time 1884745452 ps
CPU time 6.54 seconds
Started Jun 06 12:28:54 PM PDT 24
Finished Jun 06 12:29:02 PM PDT 24
Peak memory 200976 kb
Host smart-2e22ba3e-d36b-4f80-b327-835763258b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244748793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.244748793
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3268460822
Short name T458
Test name
Test status
Simulation time 98276215 ps
CPU time 0.97 seconds
Started Jun 06 12:28:55 PM PDT 24
Finished Jun 06 12:28:58 PM PDT 24
Peak memory 200672 kb
Host smart-bf551753-6f2e-47b1-a701-a38df3281c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268460822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3268460822
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1400930548
Short name T412
Test name
Test status
Simulation time 235651548 ps
CPU time 1.36 seconds
Started Jun 06 12:29:00 PM PDT 24
Finished Jun 06 12:29:04 PM PDT 24
Peak memory 200980 kb
Host smart-b840bd06-5a2c-4911-a7cc-eea59d1b0128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400930548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1400930548
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2989922693
Short name T216
Test name
Test status
Simulation time 4769611415 ps
CPU time 20.83 seconds
Started Jun 06 12:28:55 PM PDT 24
Finished Jun 06 12:29:17 PM PDT 24
Peak memory 201116 kb
Host smart-ef4651d9-5974-4b35-8c27-b1149ecb676b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989922693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2989922693
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1759069142
Short name T201
Test name
Test status
Simulation time 530449585 ps
CPU time 2.58 seconds
Started Jun 06 12:29:10 PM PDT 24
Finished Jun 06 12:29:14 PM PDT 24
Peak memory 200760 kb
Host smart-f36c3a43-0db3-46a8-95ad-1a1f619dfa40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759069142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1759069142
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1461194438
Short name T175
Test name
Test status
Simulation time 295039222 ps
CPU time 1.46 seconds
Started Jun 06 12:28:54 PM PDT 24
Finished Jun 06 12:28:57 PM PDT 24
Peak memory 200960 kb
Host smart-56b48bea-7145-4070-babb-659cca935ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461194438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1461194438
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1755771385
Short name T340
Test name
Test status
Simulation time 89203034 ps
CPU time 0.83 seconds
Started Jun 06 12:29:13 PM PDT 24
Finished Jun 06 12:29:15 PM PDT 24
Peak memory 200644 kb
Host smart-9b82a7be-d846-499a-a2de-6550c4782f6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755771385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1755771385
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.7101158
Short name T36
Test name
Test status
Simulation time 1221959837 ps
CPU time 5.53 seconds
Started Jun 06 12:28:58 PM PDT 24
Finished Jun 06 12:29:06 PM PDT 24
Peak memory 218308 kb
Host smart-e8970c21-f9c3-4455-9b46-eb9620781b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7101158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.7101158
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1062452919
Short name T278
Test name
Test status
Simulation time 245957996 ps
CPU time 1.09 seconds
Started Jun 06 12:29:15 PM PDT 24
Finished Jun 06 12:29:18 PM PDT 24
Peak memory 218000 kb
Host smart-c9658ff7-9b3a-4b56-86f1-d4824025cfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062452919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1062452919
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.333741693
Short name T352
Test name
Test status
Simulation time 224997673 ps
CPU time 0.91 seconds
Started Jun 06 12:29:12 PM PDT 24
Finished Jun 06 12:29:14 PM PDT 24
Peak memory 200596 kb
Host smart-8f99c5b5-2a73-4bc7-9b45-6a44f12902e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333741693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.333741693
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.932439099
Short name T402
Test name
Test status
Simulation time 1872869604 ps
CPU time 6.38 seconds
Started Jun 06 12:28:54 PM PDT 24
Finished Jun 06 12:29:03 PM PDT 24
Peak memory 200940 kb
Host smart-71c84d8c-17f2-48eb-b20c-3970ba4cb4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932439099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.932439099
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3582565870
Short name T335
Test name
Test status
Simulation time 158152790 ps
CPU time 1.18 seconds
Started Jun 06 12:29:14 PM PDT 24
Finished Jun 06 12:29:17 PM PDT 24
Peak memory 200800 kb
Host smart-8c447334-853b-4ead-83dc-0886d64f4a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582565870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3582565870
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3454038593
Short name T362
Test name
Test status
Simulation time 114365257 ps
CPU time 1.15 seconds
Started Jun 06 12:28:54 PM PDT 24
Finished Jun 06 12:28:57 PM PDT 24
Peak memory 200924 kb
Host smart-1ae7ab1f-ab07-4c20-8f58-e7e1a329e025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454038593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3454038593
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1175160927
Short name T24
Test name
Test status
Simulation time 411239751 ps
CPU time 2.04 seconds
Started Jun 06 12:28:55 PM PDT 24
Finished Jun 06 12:28:59 PM PDT 24
Peak memory 200736 kb
Host smart-7669a277-b8eb-4cb5-9d05-64f1ebab45a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175160927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1175160927
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.511881596
Short name T411
Test name
Test status
Simulation time 342525946 ps
CPU time 2.19 seconds
Started Jun 06 12:28:54 PM PDT 24
Finished Jun 06 12:28:58 PM PDT 24
Peak memory 200648 kb
Host smart-d46c3dc9-2890-4925-b203-ecd05457dc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511881596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.511881596
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3090920771
Short name T138
Test name
Test status
Simulation time 182292195 ps
CPU time 1.17 seconds
Started Jun 06 12:29:18 PM PDT 24
Finished Jun 06 12:29:22 PM PDT 24
Peak memory 200788 kb
Host smart-b3557f92-0442-4a58-bf2e-a2a7a83024bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090920771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3090920771
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.304234009
Short name T254
Test name
Test status
Simulation time 71696281 ps
CPU time 0.81 seconds
Started Jun 06 12:29:10 PM PDT 24
Finished Jun 06 12:29:12 PM PDT 24
Peak memory 200496 kb
Host smart-977c241e-5311-4b17-b5bf-d0a116523497
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304234009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.304234009
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1966019869
Short name T54
Test name
Test status
Simulation time 1224706029 ps
CPU time 5.7 seconds
Started Jun 06 12:29:10 PM PDT 24
Finished Jun 06 12:29:17 PM PDT 24
Peak memory 218368 kb
Host smart-8dcfae8a-2b00-457b-824f-3b8719acc239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966019869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1966019869
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3154870639
Short name T265
Test name
Test status
Simulation time 244071743 ps
CPU time 1.12 seconds
Started Jun 06 12:29:21 PM PDT 24
Finished Jun 06 12:29:25 PM PDT 24
Peak memory 217856 kb
Host smart-3890b0c3-6b3f-4fe5-9005-edc09d52a427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154870639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3154870639
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.310022440
Short name T379
Test name
Test status
Simulation time 189249537 ps
CPU time 0.95 seconds
Started Jun 06 12:28:54 PM PDT 24
Finished Jun 06 12:28:57 PM PDT 24
Peak memory 200580 kb
Host smart-c5812401-dbda-49af-aea0-d3a70fa51773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310022440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.310022440
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.4271323251
Short name T98
Test name
Test status
Simulation time 972406970 ps
CPU time 4.72 seconds
Started Jun 06 12:29:15 PM PDT 24
Finished Jun 06 12:29:21 PM PDT 24
Peak memory 201020 kb
Host smart-1abe7ef2-e5bb-4c94-aa5c-ed5098eb8519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271323251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.4271323251
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.335401900
Short name T359
Test name
Test status
Simulation time 108863810 ps
CPU time 1.02 seconds
Started Jun 06 12:29:17 PM PDT 24
Finished Jun 06 12:29:20 PM PDT 24
Peak memory 200704 kb
Host smart-62fe177f-5c5c-44d2-bfd6-9605c25df499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335401900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.335401900
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.3899347637
Short name T429
Test name
Test status
Simulation time 196522527 ps
CPU time 1.36 seconds
Started Jun 06 12:29:09 PM PDT 24
Finished Jun 06 12:29:12 PM PDT 24
Peak memory 200940 kb
Host smart-5369879c-5dc2-4faa-b731-59f61b2103fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899347637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3899347637
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3533790523
Short name T155
Test name
Test status
Simulation time 6484081806 ps
CPU time 23.4 seconds
Started Jun 06 12:29:15 PM PDT 24
Finished Jun 06 12:29:40 PM PDT 24
Peak memory 209288 kb
Host smart-fe171a3a-c809-49b1-925d-0e28ecdeb0eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533790523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3533790523
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1114553647
Short name T211
Test name
Test status
Simulation time 354526999 ps
CPU time 2.32 seconds
Started Jun 06 12:28:59 PM PDT 24
Finished Jun 06 12:29:03 PM PDT 24
Peak memory 200756 kb
Host smart-ac25b66c-2c97-41df-bca6-18922774b04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114553647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1114553647
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.302677935
Short name T271
Test name
Test status
Simulation time 136107239 ps
CPU time 1.1 seconds
Started Jun 06 12:29:17 PM PDT 24
Finished Jun 06 12:29:20 PM PDT 24
Peak memory 200788 kb
Host smart-2bfaef2b-e74f-41c9-9a6c-d213f5dd9a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302677935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.302677935
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1292630866
Short name T75
Test name
Test status
Simulation time 81484653 ps
CPU time 0.75 seconds
Started Jun 06 12:28:59 PM PDT 24
Finished Jun 06 12:29:01 PM PDT 24
Peak memory 200488 kb
Host smart-b414a2f0-2225-4a7d-be5f-566381e190c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292630866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1292630866
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.86223235
Short name T492
Test name
Test status
Simulation time 1235037061 ps
CPU time 5.82 seconds
Started Jun 06 12:29:17 PM PDT 24
Finished Jun 06 12:29:25 PM PDT 24
Peak memory 218344 kb
Host smart-3d1bec09-6dda-4ccd-b7d5-9170811f6e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86223235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.86223235
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2608364960
Short name T344
Test name
Test status
Simulation time 244407985 ps
CPU time 1.14 seconds
Started Jun 06 12:29:14 PM PDT 24
Finished Jun 06 12:29:17 PM PDT 24
Peak memory 217948 kb
Host smart-0d30a446-44a2-4e8e-95ac-6cecc2a36a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608364960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2608364960
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1772248240
Short name T535
Test name
Test status
Simulation time 75288159 ps
CPU time 0.71 seconds
Started Jun 06 12:29:12 PM PDT 24
Finished Jun 06 12:29:15 PM PDT 24
Peak memory 200568 kb
Host smart-0ef9aa31-6cdc-4583-8d62-290bae7476aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772248240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1772248240
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.1390093024
Short name T357
Test name
Test status
Simulation time 2004881887 ps
CPU time 7.51 seconds
Started Jun 06 12:29:18 PM PDT 24
Finished Jun 06 12:29:27 PM PDT 24
Peak memory 200932 kb
Host smart-673a210b-2b18-49c7-8587-30c1ca2b4d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390093024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1390093024
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3013201301
Short name T195
Test name
Test status
Simulation time 167619324 ps
CPU time 1.23 seconds
Started Jun 06 12:28:57 PM PDT 24
Finished Jun 06 12:29:00 PM PDT 24
Peak memory 200664 kb
Host smart-fe31317b-56c3-47b9-8168-c0672e9099a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013201301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3013201301
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1435102824
Short name T360
Test name
Test status
Simulation time 230737313 ps
CPU time 1.4 seconds
Started Jun 06 12:29:11 PM PDT 24
Finished Jun 06 12:29:14 PM PDT 24
Peak memory 200952 kb
Host smart-36c0610e-6448-422f-8e78-69c690df87fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435102824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1435102824
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.1124801116
Short name T367
Test name
Test status
Simulation time 7786928337 ps
CPU time 29.01 seconds
Started Jun 06 12:28:57 PM PDT 24
Finished Jun 06 12:29:28 PM PDT 24
Peak memory 201180 kb
Host smart-1bd69e64-01fc-4b2b-97e3-f9ea6a24316e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124801116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1124801116
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.3998047813
Short name T350
Test name
Test status
Simulation time 275316472 ps
CPU time 1.84 seconds
Started Jun 06 12:29:10 PM PDT 24
Finished Jun 06 12:29:14 PM PDT 24
Peak memory 200720 kb
Host smart-a308fd88-4063-467e-a141-58683a207536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998047813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.3998047813
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2175863090
Short name T231
Test name
Test status
Simulation time 92328848 ps
CPU time 0.85 seconds
Started Jun 06 12:29:07 PM PDT 24
Finished Jun 06 12:29:08 PM PDT 24
Peak memory 200680 kb
Host smart-1b59d359-6546-4aeb-a523-f05faa118099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175863090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2175863090
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1477151278
Short name T128
Test name
Test status
Simulation time 76483413 ps
CPU time 0.77 seconds
Started Jun 06 12:29:04 PM PDT 24
Finished Jun 06 12:29:11 PM PDT 24
Peak memory 200556 kb
Host smart-4846f913-f18f-4888-97c3-858404455c05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477151278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1477151278
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.605762278
Short name T325
Test name
Test status
Simulation time 1216299043 ps
CPU time 5.41 seconds
Started Jun 06 12:29:01 PM PDT 24
Finished Jun 06 12:29:09 PM PDT 24
Peak memory 217856 kb
Host smart-336d9bd1-b2e5-41e3-b835-6989101cb9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605762278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.605762278
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2766902366
Short name T341
Test name
Test status
Simulation time 244371885 ps
CPU time 1.12 seconds
Started Jun 06 12:28:56 PM PDT 24
Finished Jun 06 12:28:59 PM PDT 24
Peak memory 218796 kb
Host smart-74886d07-420c-4f53-867c-d04bfc66a40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766902366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2766902366
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1765092686
Short name T308
Test name
Test status
Simulation time 78666171 ps
CPU time 0.73 seconds
Started Jun 06 12:28:59 PM PDT 24
Finished Jun 06 12:29:02 PM PDT 24
Peak memory 200600 kb
Host smart-36cc1ca3-243e-4e73-99a8-f6dc08cd8b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765092686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1765092686
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.3589441553
Short name T345
Test name
Test status
Simulation time 1842008581 ps
CPU time 7.04 seconds
Started Jun 06 12:28:56 PM PDT 24
Finished Jun 06 12:29:05 PM PDT 24
Peak memory 200932 kb
Host smart-afc2be21-7413-495e-a9b6-77258b5a7e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589441553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3589441553
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2640227240
Short name T240
Test name
Test status
Simulation time 104403989 ps
CPU time 0.98 seconds
Started Jun 06 12:29:02 PM PDT 24
Finished Jun 06 12:29:05 PM PDT 24
Peak memory 200704 kb
Host smart-a4c55e2e-539a-4e05-aa5a-7a338322218b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640227240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2640227240
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.451272032
Short name T483
Test name
Test status
Simulation time 193697699 ps
CPU time 1.43 seconds
Started Jun 06 12:28:59 PM PDT 24
Finished Jun 06 12:29:03 PM PDT 24
Peak memory 200936 kb
Host smart-352c4fa3-8abc-4b7c-b8b1-09d60523ced7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451272032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.451272032
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.254309557
Short name T469
Test name
Test status
Simulation time 3079604020 ps
CPU time 13.07 seconds
Started Jun 06 12:29:14 PM PDT 24
Finished Jun 06 12:29:29 PM PDT 24
Peak memory 209324 kb
Host smart-f285da46-f70c-4897-9e48-af3a33a85ab6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254309557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.254309557
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3354286353
Short name T135
Test name
Test status
Simulation time 105776972 ps
CPU time 1.46 seconds
Started Jun 06 12:29:14 PM PDT 24
Finished Jun 06 12:29:18 PM PDT 24
Peak memory 200796 kb
Host smart-af4cc566-6e67-4988-988f-5938f0ec5098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354286353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3354286353
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1308034256
Short name T305
Test name
Test status
Simulation time 175066295 ps
CPU time 1.33 seconds
Started Jun 06 12:28:55 PM PDT 24
Finished Jun 06 12:28:58 PM PDT 24
Peak memory 200948 kb
Host smart-5d03b795-55e1-411f-a5ed-dad41f93d882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308034256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1308034256
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.792958843
Short name T70
Test name
Test status
Simulation time 75913821 ps
CPU time 0.8 seconds
Started Jun 06 12:29:23 PM PDT 24
Finished Jun 06 12:29:26 PM PDT 24
Peak memory 200552 kb
Host smart-f25a266e-3176-4613-8eaf-0c13e9c4b70b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792958843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.792958843
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2124719126
Short name T38
Test name
Test status
Simulation time 2356502866 ps
CPU time 7.53 seconds
Started Jun 06 12:29:23 PM PDT 24
Finished Jun 06 12:29:33 PM PDT 24
Peak memory 218588 kb
Host smart-9fc8d3ef-872f-47f2-b7df-f2e6e8280693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124719126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2124719126
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1491429770
Short name T404
Test name
Test status
Simulation time 243858916 ps
CPU time 1.03 seconds
Started Jun 06 12:29:21 PM PDT 24
Finished Jun 06 12:29:24 PM PDT 24
Peak memory 217932 kb
Host smart-b2f9923a-7491-4f7f-a09d-fa9b49074ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491429770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1491429770
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3108318156
Short name T152
Test name
Test status
Simulation time 133537520 ps
CPU time 0.8 seconds
Started Jun 06 12:28:55 PM PDT 24
Finished Jun 06 12:28:58 PM PDT 24
Peak memory 200580 kb
Host smart-5b1b47cc-2361-474a-b607-17cb487d647d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108318156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3108318156
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2171200385
Short name T454
Test name
Test status
Simulation time 1355715889 ps
CPU time 5.27 seconds
Started Jun 06 12:29:03 PM PDT 24
Finished Jun 06 12:29:10 PM PDT 24
Peak memory 200880 kb
Host smart-61ecafd4-11c5-4a93-bb1a-afbc84d74c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171200385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2171200385
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.546176917
Short name T144
Test name
Test status
Simulation time 182119815 ps
CPU time 1.21 seconds
Started Jun 06 12:29:14 PM PDT 24
Finished Jun 06 12:29:17 PM PDT 24
Peak memory 200760 kb
Host smart-69e87c04-d0e9-4edc-a6a3-5a8ce0e3433c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546176917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.546176917
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.4073410034
Short name T391
Test name
Test status
Simulation time 249955259 ps
CPU time 1.47 seconds
Started Jun 06 12:29:10 PM PDT 24
Finished Jun 06 12:29:13 PM PDT 24
Peak memory 200908 kb
Host smart-f33e5471-308d-41da-ab43-cfb4b10f58cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073410034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.4073410034
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2722335659
Short name T148
Test name
Test status
Simulation time 6688968188 ps
CPU time 22.14 seconds
Started Jun 06 12:29:17 PM PDT 24
Finished Jun 06 12:29:41 PM PDT 24
Peak memory 209336 kb
Host smart-9d349c4d-9525-4e96-961d-0762bd14d269
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722335659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2722335659
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2616909143
Short name T83
Test name
Test status
Simulation time 295486911 ps
CPU time 1.86 seconds
Started Jun 06 12:29:23 PM PDT 24
Finished Jun 06 12:29:27 PM PDT 24
Peak memory 208928 kb
Host smart-319e345d-71ce-47b7-a8c7-3bb95cb5d467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616909143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2616909143
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.1241807548
Short name T11
Test name
Test status
Simulation time 235370433 ps
CPU time 1.37 seconds
Started Jun 06 12:29:15 PM PDT 24
Finished Jun 06 12:29:18 PM PDT 24
Peak memory 200976 kb
Host smart-75916199-02da-455c-9127-865496fe7718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241807548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1241807548
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2494207100
Short name T186
Test name
Test status
Simulation time 121993576 ps
CPU time 0.93 seconds
Started Jun 06 12:29:08 PM PDT 24
Finished Jun 06 12:29:10 PM PDT 24
Peak memory 200484 kb
Host smart-f2e4a113-aa86-4969-9c30-a639c00ccfe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494207100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2494207100
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3154477919
Short name T453
Test name
Test status
Simulation time 2356802353 ps
CPU time 7.98 seconds
Started Jun 06 12:29:21 PM PDT 24
Finished Jun 06 12:29:31 PM PDT 24
Peak memory 217728 kb
Host smart-b46cc9ff-a757-431b-a533-0c13bb6ad6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154477919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3154477919
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2232420143
Short name T237
Test name
Test status
Simulation time 244411684 ps
CPU time 1.16 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:26 PM PDT 24
Peak memory 217872 kb
Host smart-dbcb847a-3070-470e-a6d5-dde73354652e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232420143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2232420143
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.697301258
Short name T365
Test name
Test status
Simulation time 228868589 ps
CPU time 1 seconds
Started Jun 06 12:29:16 PM PDT 24
Finished Jun 06 12:29:18 PM PDT 24
Peak memory 200564 kb
Host smart-1de3e46c-7ca7-41d9-a641-98589d61698e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697301258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.697301258
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1875063090
Short name T441
Test name
Test status
Simulation time 1442667136 ps
CPU time 5.59 seconds
Started Jun 06 12:29:14 PM PDT 24
Finished Jun 06 12:29:21 PM PDT 24
Peak memory 200916 kb
Host smart-72412f71-b45d-4be6-b02b-f5987696e51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875063090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1875063090
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.130207106
Short name T187
Test name
Test status
Simulation time 106699916 ps
CPU time 0.98 seconds
Started Jun 06 12:29:03 PM PDT 24
Finished Jun 06 12:29:05 PM PDT 24
Peak memory 200748 kb
Host smart-432cd6ab-235c-4bfb-bf21-b554e1fc8fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130207106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.130207106
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.441291938
Short name T313
Test name
Test status
Simulation time 194697010 ps
CPU time 1.37 seconds
Started Jun 06 12:29:08 PM PDT 24
Finished Jun 06 12:29:11 PM PDT 24
Peak memory 201080 kb
Host smart-b2c4fe62-79ee-40ef-a148-f879b0ce68d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441291938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.441291938
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3997216035
Short name T356
Test name
Test status
Simulation time 5289915436 ps
CPU time 18.55 seconds
Started Jun 06 12:29:18 PM PDT 24
Finished Jun 06 12:29:39 PM PDT 24
Peak memory 201160 kb
Host smart-b4e8f4b4-8143-4163-95a1-36fb5e032380
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997216035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3997216035
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2661894570
Short name T78
Test name
Test status
Simulation time 259401913 ps
CPU time 1.82 seconds
Started Jun 06 12:29:19 PM PDT 24
Finished Jun 06 12:29:23 PM PDT 24
Peak memory 200800 kb
Host smart-ec841b56-b148-4353-8c0a-d5dd43083af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661894570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2661894570
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.279550798
Short name T207
Test name
Test status
Simulation time 85857586 ps
CPU time 0.81 seconds
Started Jun 06 12:29:20 PM PDT 24
Finished Jun 06 12:29:23 PM PDT 24
Peak memory 200808 kb
Host smart-2b3f41ce-83da-4fea-a926-380c4e0ef795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279550798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.279550798
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1489162237
Short name T258
Test name
Test status
Simulation time 62323996 ps
CPU time 0.76 seconds
Started Jun 06 12:29:08 PM PDT 24
Finished Jun 06 12:29:10 PM PDT 24
Peak memory 200640 kb
Host smart-781cd725-d36e-4301-abb0-a13300f93f7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489162237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1489162237
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1028594646
Short name T334
Test name
Test status
Simulation time 1222074590 ps
CPU time 5.19 seconds
Started Jun 06 12:29:16 PM PDT 24
Finished Jun 06 12:29:23 PM PDT 24
Peak memory 218336 kb
Host smart-89818b7e-1854-4686-a7a3-458de80c9b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028594646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1028594646
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2365085023
Short name T348
Test name
Test status
Simulation time 244704215 ps
CPU time 1.06 seconds
Started Jun 06 12:29:09 PM PDT 24
Finished Jun 06 12:29:11 PM PDT 24
Peak memory 217908 kb
Host smart-0c492b20-9746-4f41-93ba-cf4a732157f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365085023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2365085023
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.4188372589
Short name T456
Test name
Test status
Simulation time 214066466 ps
CPU time 0.91 seconds
Started Jun 06 12:29:16 PM PDT 24
Finished Jun 06 12:29:18 PM PDT 24
Peak memory 200580 kb
Host smart-f13c36a2-cfc6-4791-b240-fbcfc748c30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188372589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.4188372589
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.2520385420
Short name T330
Test name
Test status
Simulation time 1235658451 ps
CPU time 5 seconds
Started Jun 06 12:29:17 PM PDT 24
Finished Jun 06 12:29:24 PM PDT 24
Peak memory 201000 kb
Host smart-a61b20f1-3109-4a8a-8691-70bdaa61e38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520385420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.2520385420
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1759698391
Short name T499
Test name
Test status
Simulation time 189612917 ps
CPU time 1.19 seconds
Started Jun 06 12:29:23 PM PDT 24
Finished Jun 06 12:29:27 PM PDT 24
Peak memory 200792 kb
Host smart-c742183e-f70e-4cb6-9efa-2ed34b9d3454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759698391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1759698391
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.3936342077
Short name T150
Test name
Test status
Simulation time 244827405 ps
CPU time 1.57 seconds
Started Jun 06 12:29:10 PM PDT 24
Finished Jun 06 12:29:13 PM PDT 24
Peak memory 200940 kb
Host smart-365cb8f4-f46a-4059-8dd6-73db49a54384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936342077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3936342077
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2283806575
Short name T96
Test name
Test status
Simulation time 1959962550 ps
CPU time 8.94 seconds
Started Jun 06 12:29:16 PM PDT 24
Finished Jun 06 12:29:27 PM PDT 24
Peak memory 209376 kb
Host smart-26a15cb3-ae81-468c-9ee2-501931e8b1c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283806575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2283806575
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1583863348
Short name T23
Test name
Test status
Simulation time 152249016 ps
CPU time 1.74 seconds
Started Jun 06 12:29:23 PM PDT 24
Finished Jun 06 12:29:27 PM PDT 24
Peak memory 200776 kb
Host smart-dbaf24cb-cd6b-4baa-b7b8-d7180d778343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583863348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1583863348
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2412985259
Short name T368
Test name
Test status
Simulation time 86402567 ps
CPU time 0.94 seconds
Started Jun 06 12:29:09 PM PDT 24
Finished Jun 06 12:29:11 PM PDT 24
Peak memory 200784 kb
Host smart-c7b03232-bd80-4bf8-9281-df44581055dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412985259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2412985259
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3238652820
Short name T8
Test name
Test status
Simulation time 95731547 ps
CPU time 0.8 seconds
Started Jun 06 12:29:20 PM PDT 24
Finished Jun 06 12:29:23 PM PDT 24
Peak memory 200532 kb
Host smart-c9e45df4-eeb9-4571-9b2d-a073eb2c2f66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238652820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3238652820
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.314739356
Short name T29
Test name
Test status
Simulation time 1908787465 ps
CPU time 7.32 seconds
Started Jun 06 12:29:21 PM PDT 24
Finished Jun 06 12:29:31 PM PDT 24
Peak memory 218440 kb
Host smart-ed7347ad-1c7f-4fae-971b-b4ea6f820f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314739356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.314739356
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.1080350535
Short name T355
Test name
Test status
Simulation time 243908151 ps
CPU time 1.15 seconds
Started Jun 06 12:29:04 PM PDT 24
Finished Jun 06 12:29:06 PM PDT 24
Peak memory 217772 kb
Host smart-ef6887ba-90f8-4f2c-8cab-c6529585e6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080350535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.1080350535
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.836811506
Short name T288
Test name
Test status
Simulation time 90161851 ps
CPU time 0.73 seconds
Started Jun 06 12:29:23 PM PDT 24
Finished Jun 06 12:29:26 PM PDT 24
Peak memory 200568 kb
Host smart-24c2913c-692e-413e-9f81-d56766e7f1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836811506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.836811506
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3318893737
Short name T102
Test name
Test status
Simulation time 1959580316 ps
CPU time 6.54 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:31 PM PDT 24
Peak memory 201036 kb
Host smart-ca09a4f1-13a8-4b8a-8d56-b90bbd6cdc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318893737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3318893737
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2591361345
Short name T347
Test name
Test status
Simulation time 151776950 ps
CPU time 1.13 seconds
Started Jun 06 12:29:24 PM PDT 24
Finished Jun 06 12:29:27 PM PDT 24
Peak memory 200724 kb
Host smart-3cc48334-9397-48c5-8405-009e01d63058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591361345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2591361345
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.483115859
Short name T47
Test name
Test status
Simulation time 197782997 ps
CPU time 1.38 seconds
Started Jun 06 12:29:20 PM PDT 24
Finished Jun 06 12:29:24 PM PDT 24
Peak memory 201032 kb
Host smart-3da3a24e-cdf5-4edc-8d47-addb2b6a8d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483115859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.483115859
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.93756975
Short name T452
Test name
Test status
Simulation time 1847880969 ps
CPU time 7.24 seconds
Started Jun 06 12:29:21 PM PDT 24
Finished Jun 06 12:29:31 PM PDT 24
Peak memory 210372 kb
Host smart-9ca1e152-ada3-4232-afb0-73bf700f5e2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93756975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.93756975
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1051261687
Short name T384
Test name
Test status
Simulation time 549276919 ps
CPU time 2.67 seconds
Started Jun 06 12:29:17 PM PDT 24
Finished Jun 06 12:29:22 PM PDT 24
Peak memory 200560 kb
Host smart-3133c5b8-ab8d-46f6-b71c-c81669370cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051261687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1051261687
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2980699165
Short name T185
Test name
Test status
Simulation time 177579107 ps
CPU time 1.31 seconds
Started Jun 06 12:29:21 PM PDT 24
Finished Jun 06 12:29:25 PM PDT 24
Peak memory 201036 kb
Host smart-679c9d03-7505-4525-b80e-b2bbf813e3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980699165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2980699165
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1910009621
Short name T336
Test name
Test status
Simulation time 1891953133 ps
CPU time 6.85 seconds
Started Jun 06 12:28:30 PM PDT 24
Finished Jun 06 12:28:39 PM PDT 24
Peak memory 218380 kb
Host smart-49330c1b-323b-4b1a-a3fb-9d433891b70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910009621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1910009621
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2031600161
Short name T461
Test name
Test status
Simulation time 245154831 ps
CPU time 1.08 seconds
Started Jun 06 12:28:34 PM PDT 24
Finished Jun 06 12:28:36 PM PDT 24
Peak memory 218204 kb
Host smart-980c1263-98a1-4bce-b185-2f29ae3e3526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031600161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2031600161
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1364350831
Short name T176
Test name
Test status
Simulation time 123528598 ps
CPU time 0.86 seconds
Started Jun 06 12:28:31 PM PDT 24
Finished Jun 06 12:28:34 PM PDT 24
Peak memory 200492 kb
Host smart-a75d32a4-3ad0-4822-aba7-a2e113956652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364350831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1364350831
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2821095571
Short name T123
Test name
Test status
Simulation time 1572493700 ps
CPU time 5.98 seconds
Started Jun 06 12:28:33 PM PDT 24
Finished Jun 06 12:28:40 PM PDT 24
Peak memory 200964 kb
Host smart-a2fc8dca-eeb3-4d85-a88c-588a65d50cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821095571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2821095571
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.525943067
Short name T73
Test name
Test status
Simulation time 16501992123 ps
CPU time 31.33 seconds
Started Jun 06 12:28:31 PM PDT 24
Finished Jun 06 12:29:04 PM PDT 24
Peak memory 217564 kb
Host smart-4c4120fa-68e6-4f46-9959-ec46ee447803
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525943067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.525943067
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2371852367
Short name T228
Test name
Test status
Simulation time 152276478 ps
CPU time 1.19 seconds
Started Jun 06 12:28:36 PM PDT 24
Finished Jun 06 12:28:38 PM PDT 24
Peak memory 200764 kb
Host smart-5ab5bec7-bf32-44f4-aa81-d030f47f7531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371852367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2371852367
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.4258130121
Short name T527
Test name
Test status
Simulation time 258451154 ps
CPU time 1.52 seconds
Started Jun 06 12:28:36 PM PDT 24
Finished Jun 06 12:28:39 PM PDT 24
Peak memory 200968 kb
Host smart-388cad9a-6c2f-42f7-a2b1-6c32329fda28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258130121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.4258130121
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1754190288
Short name T388
Test name
Test status
Simulation time 9027349875 ps
CPU time 32.86 seconds
Started Jun 06 12:28:36 PM PDT 24
Finished Jun 06 12:29:10 PM PDT 24
Peak memory 201148 kb
Host smart-d1d0861a-59b2-4f2c-9c12-15b5277990ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754190288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1754190288
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2040061366
Short name T522
Test name
Test status
Simulation time 146916326 ps
CPU time 1.72 seconds
Started Jun 06 12:28:31 PM PDT 24
Finished Jun 06 12:28:34 PM PDT 24
Peak memory 200676 kb
Host smart-5e2d5946-3cbd-4812-b5ff-14b7022b3f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040061366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2040061366
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2340290023
Short name T276
Test name
Test status
Simulation time 165193419 ps
CPU time 1.22 seconds
Started Jun 06 12:28:39 PM PDT 24
Finished Jun 06 12:28:42 PM PDT 24
Peak memory 201008 kb
Host smart-53690ac0-d0ea-4204-acaa-30bb65500c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340290023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2340290023
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.4207112528
Short name T446
Test name
Test status
Simulation time 72444048 ps
CPU time 0.81 seconds
Started Jun 06 12:29:14 PM PDT 24
Finished Jun 06 12:29:17 PM PDT 24
Peak memory 200576 kb
Host smart-fabba8f9-44f9-439f-b5fe-f5f38afc0367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207112528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.4207112528
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.2969835844
Short name T390
Test name
Test status
Simulation time 1214589672 ps
CPU time 5.49 seconds
Started Jun 06 12:29:17 PM PDT 24
Finished Jun 06 12:29:25 PM PDT 24
Peak memory 217828 kb
Host smart-b4bec675-27ff-4b34-9d91-14ed768caa1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969835844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2969835844
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3190450138
Short name T386
Test name
Test status
Simulation time 244490586 ps
CPU time 1.02 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:26 PM PDT 24
Peak memory 217936 kb
Host smart-4516ba4c-ecc2-4805-87d4-5e07cf0a8af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190450138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3190450138
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1180722191
Short name T496
Test name
Test status
Simulation time 102540033 ps
CPU time 0.75 seconds
Started Jun 06 12:29:16 PM PDT 24
Finished Jun 06 12:29:19 PM PDT 24
Peak memory 200544 kb
Host smart-d7e0db0e-1d43-4ba4-bd26-586a4fea0c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180722191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1180722191
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2540860721
Short name T524
Test name
Test status
Simulation time 1392593529 ps
CPU time 5.32 seconds
Started Jun 06 12:29:21 PM PDT 24
Finished Jun 06 12:29:29 PM PDT 24
Peak memory 200992 kb
Host smart-07026060-d6c6-48bb-8fed-e1fa5f85d6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540860721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2540860721
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3696537915
Short name T462
Test name
Test status
Simulation time 99620757 ps
CPU time 1 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:30 PM PDT 24
Peak memory 200736 kb
Host smart-7d49f302-cda5-4aaf-a17b-4fe4e351416c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696537915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3696537915
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.650610812
Short name T486
Test name
Test status
Simulation time 251367293 ps
CPU time 1.42 seconds
Started Jun 06 12:29:19 PM PDT 24
Finished Jun 06 12:29:22 PM PDT 24
Peak memory 200988 kb
Host smart-79cd8f17-98bf-4d46-b3dc-61228e7e57cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650610812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.650610812
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.3102134932
Short name T460
Test name
Test status
Simulation time 10761207233 ps
CPU time 40 seconds
Started Jun 06 12:29:23 PM PDT 24
Finished Jun 06 12:30:06 PM PDT 24
Peak memory 201100 kb
Host smart-63bee879-7040-4d56-b92e-e9fe78ef5b2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102134932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3102134932
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.1229671484
Short name T444
Test name
Test status
Simulation time 142147332 ps
CPU time 1.66 seconds
Started Jun 06 12:29:14 PM PDT 24
Finished Jun 06 12:29:18 PM PDT 24
Peak memory 200844 kb
Host smart-64959ee8-5708-455e-afbc-008b7c994ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229671484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1229671484
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.4278872790
Short name T300
Test name
Test status
Simulation time 162457892 ps
CPU time 1.22 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:26 PM PDT 24
Peak memory 200920 kb
Host smart-a2acfccb-227b-46ad-bb1d-659c7ee508eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278872790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.4278872790
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2106730638
Short name T157
Test name
Test status
Simulation time 53868478 ps
CPU time 0.7 seconds
Started Jun 06 12:29:30 PM PDT 24
Finished Jun 06 12:29:32 PM PDT 24
Peak memory 200632 kb
Host smart-699d5c5d-13d1-4347-82ca-1c6a42042406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106730638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2106730638
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.154270560
Short name T417
Test name
Test status
Simulation time 1883163202 ps
CPU time 7.37 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:32 PM PDT 24
Peak memory 217408 kb
Host smart-c584a096-d2f2-482b-9a34-ed98d8aa5bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154270560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.154270560
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2912276377
Short name T447
Test name
Test status
Simulation time 244320796 ps
CPU time 1.12 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:26 PM PDT 24
Peak memory 217948 kb
Host smart-1886363a-e30c-46e4-9fcc-d0b7b28f5945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912276377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2912276377
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.4169103661
Short name T213
Test name
Test status
Simulation time 107117965 ps
CPU time 0.8 seconds
Started Jun 06 12:29:26 PM PDT 24
Finished Jun 06 12:29:29 PM PDT 24
Peak memory 200596 kb
Host smart-ab8d8cd3-17cd-49d7-b995-9f8a6deeaffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169103661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.4169103661
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3767772612
Short name T346
Test name
Test status
Simulation time 1524293102 ps
CPU time 5.53 seconds
Started Jun 06 12:29:21 PM PDT 24
Finished Jun 06 12:29:29 PM PDT 24
Peak memory 200864 kb
Host smart-8ef27b77-68bc-4a46-84b7-09836fd83ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767772612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3767772612
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2976428188
Short name T394
Test name
Test status
Simulation time 100785649 ps
CPU time 0.98 seconds
Started Jun 06 12:29:14 PM PDT 24
Finished Jun 06 12:29:17 PM PDT 24
Peak memory 200820 kb
Host smart-3c8e3a80-ac5d-4d22-92a1-317e58b80b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976428188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2976428188
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.4146325668
Short name T445
Test name
Test status
Simulation time 239413946 ps
CPU time 1.49 seconds
Started Jun 06 12:29:19 PM PDT 24
Finished Jun 06 12:29:22 PM PDT 24
Peak memory 200992 kb
Host smart-258e6bb0-b405-4b58-8a52-677d03edbcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146325668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.4146325668
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2480988739
Short name T43
Test name
Test status
Simulation time 4452519533 ps
CPU time 18.69 seconds
Started Jun 06 12:29:21 PM PDT 24
Finished Jun 06 12:29:42 PM PDT 24
Peak memory 209340 kb
Host smart-a8f87d06-6749-40dc-891d-ed523a763223
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480988739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2480988739
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.332669234
Short name T76
Test name
Test status
Simulation time 325202119 ps
CPU time 2.05 seconds
Started Jun 06 12:29:15 PM PDT 24
Finished Jun 06 12:29:19 PM PDT 24
Peak memory 200800 kb
Host smart-2aa11e20-2af3-496b-bcb6-cd0a8687283e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332669234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.332669234
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2193702015
Short name T399
Test name
Test status
Simulation time 160078620 ps
CPU time 1.27 seconds
Started Jun 06 12:29:25 PM PDT 24
Finished Jun 06 12:29:28 PM PDT 24
Peak memory 200948 kb
Host smart-a5acccb4-2f16-4f8b-b8d6-37bdc7df7937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193702015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2193702015
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.4044018315
Short name T241
Test name
Test status
Simulation time 65772956 ps
CPU time 0.73 seconds
Started Jun 06 12:29:20 PM PDT 24
Finished Jun 06 12:29:23 PM PDT 24
Peak memory 200532 kb
Host smart-9bf4576b-7668-4191-be58-370c25bba658
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044018315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.4044018315
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.444385700
Short name T519
Test name
Test status
Simulation time 1894706905 ps
CPU time 7.06 seconds
Started Jun 06 12:29:21 PM PDT 24
Finished Jun 06 12:29:31 PM PDT 24
Peak memory 218308 kb
Host smart-48163933-6aa5-4d94-b0fc-e76154c236bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444385700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.444385700
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.4277972029
Short name T25
Test name
Test status
Simulation time 244654727 ps
CPU time 1.07 seconds
Started Jun 06 12:29:20 PM PDT 24
Finished Jun 06 12:29:24 PM PDT 24
Peak memory 217904 kb
Host smart-6b0c86a2-f6d4-4576-a86c-60a9b6ffde22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277972029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.4277972029
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.865876071
Short name T19
Test name
Test status
Simulation time 131666245 ps
CPU time 0.82 seconds
Started Jun 06 12:29:21 PM PDT 24
Finished Jun 06 12:29:24 PM PDT 24
Peak memory 200580 kb
Host smart-dc9e40a0-c86b-4ff5-8e18-b4a5223c522d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865876071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.865876071
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.3945005046
Short name T103
Test name
Test status
Simulation time 1815969170 ps
CPU time 6.36 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:31 PM PDT 24
Peak memory 200996 kb
Host smart-e34acfa4-1c7e-4ff4-a842-45f135c94563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945005046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3945005046
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2457990051
Short name T449
Test name
Test status
Simulation time 142069726 ps
CPU time 1.04 seconds
Started Jun 06 12:29:23 PM PDT 24
Finished Jun 06 12:29:27 PM PDT 24
Peak memory 200792 kb
Host smart-f2644f91-98d8-4e67-ac40-f154407ccb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457990051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2457990051
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1880009768
Short name T223
Test name
Test status
Simulation time 233525938 ps
CPU time 1.5 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:26 PM PDT 24
Peak memory 200972 kb
Host smart-15a2baf0-46f3-4676-859a-934694ea1dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880009768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1880009768
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1373899212
Short name T423
Test name
Test status
Simulation time 3564650335 ps
CPU time 12.31 seconds
Started Jun 06 12:29:21 PM PDT 24
Finished Jun 06 12:29:35 PM PDT 24
Peak memory 209260 kb
Host smart-e0ac664a-5db1-48c4-951f-126025a1dbbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373899212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1373899212
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.2300788141
Short name T82
Test name
Test status
Simulation time 493109950 ps
CPU time 2.48 seconds
Started Jun 06 12:29:24 PM PDT 24
Finished Jun 06 12:29:29 PM PDT 24
Peak memory 200752 kb
Host smart-2b9baf05-f962-48c9-922c-2b2e94bb83be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300788141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.2300788141
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.119030010
Short name T440
Test name
Test status
Simulation time 158866448 ps
CPU time 1.17 seconds
Started Jun 06 12:29:23 PM PDT 24
Finished Jun 06 12:29:26 PM PDT 24
Peak memory 200964 kb
Host smart-2765f54e-875c-498b-a525-e7a0395f820b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119030010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.119030010
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2953316858
Short name T272
Test name
Test status
Simulation time 83110623 ps
CPU time 0.79 seconds
Started Jun 06 12:29:16 PM PDT 24
Finished Jun 06 12:29:19 PM PDT 24
Peak memory 200644 kb
Host smart-bdee771d-365e-4845-91bf-7b3b8f03e7f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953316858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2953316858
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.1856343634
Short name T364
Test name
Test status
Simulation time 2381962579 ps
CPU time 8.16 seconds
Started Jun 06 12:29:13 PM PDT 24
Finished Jun 06 12:29:22 PM PDT 24
Peak memory 217712 kb
Host smart-1927de4c-a54e-4326-b391-7dabf96b7900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856343634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.1856343634
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2165259512
Short name T146
Test name
Test status
Simulation time 244331537 ps
CPU time 1.13 seconds
Started Jun 06 12:29:21 PM PDT 24
Finished Jun 06 12:29:24 PM PDT 24
Peak memory 217876 kb
Host smart-55542629-9c5c-4edf-9ddb-95be18e56aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165259512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2165259512
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.555123283
Short name T481
Test name
Test status
Simulation time 145283426 ps
CPU time 0.81 seconds
Started Jun 06 12:29:21 PM PDT 24
Finished Jun 06 12:29:24 PM PDT 24
Peak memory 200440 kb
Host smart-1c015b04-f7de-4ec7-9c5b-56230da525f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555123283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.555123283
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.921852350
Short name T48
Test name
Test status
Simulation time 1456326354 ps
CPU time 4.85 seconds
Started Jun 06 12:29:28 PM PDT 24
Finished Jun 06 12:29:35 PM PDT 24
Peak memory 200976 kb
Host smart-5d89bfbd-9c12-43b1-a8ce-7628332ea8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921852350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.921852350
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3429657366
Short name T468
Test name
Test status
Simulation time 174162004 ps
CPU time 1.15 seconds
Started Jun 06 12:29:25 PM PDT 24
Finished Jun 06 12:29:28 PM PDT 24
Peak memory 200756 kb
Host smart-0ed99bd5-5a28-483f-945f-04a6e61a8066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429657366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3429657366
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.989815715
Short name T506
Test name
Test status
Simulation time 118646861 ps
CPU time 1.12 seconds
Started Jun 06 12:29:21 PM PDT 24
Finished Jun 06 12:29:24 PM PDT 24
Peak memory 200872 kb
Host smart-62573b83-b5f8-47f6-9b6b-3bc759b763b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989815715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.989815715
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.789880527
Short name T534
Test name
Test status
Simulation time 4342226184 ps
CPU time 16.08 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:40 PM PDT 24
Peak memory 209328 kb
Host smart-fcddf43f-2930-4cad-a3e5-e87c2c55213a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789880527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.789880527
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3045982815
Short name T377
Test name
Test status
Simulation time 132618161 ps
CPU time 1.54 seconds
Started Jun 06 12:29:31 PM PDT 24
Finished Jun 06 12:29:33 PM PDT 24
Peak memory 200788 kb
Host smart-78ad1701-6dc7-498f-bd11-303fdb194290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045982815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3045982815
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.528532100
Short name T511
Test name
Test status
Simulation time 261743296 ps
CPU time 1.38 seconds
Started Jun 06 12:29:17 PM PDT 24
Finished Jun 06 12:29:21 PM PDT 24
Peak memory 200696 kb
Host smart-ed795354-9004-4d86-811b-018f9bd5ffee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528532100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.528532100
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.184639152
Short name T339
Test name
Test status
Simulation time 81825382 ps
CPU time 0.77 seconds
Started Jun 06 12:29:28 PM PDT 24
Finished Jun 06 12:29:31 PM PDT 24
Peak memory 200572 kb
Host smart-a35d9f55-b742-4fd0-a930-4a17b7c36d57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184639152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.184639152
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.2517564207
Short name T451
Test name
Test status
Simulation time 2357335267 ps
CPU time 8.14 seconds
Started Jun 06 12:29:21 PM PDT 24
Finished Jun 06 12:29:31 PM PDT 24
Peak memory 218548 kb
Host smart-0a333730-d627-4271-9973-9c342f44b24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517564207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2517564207
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1774922387
Short name T182
Test name
Test status
Simulation time 251357725 ps
CPU time 1.08 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:26 PM PDT 24
Peak memory 217900 kb
Host smart-39f9ddf4-a6b1-4bdd-99ad-2a1d36d1895c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774922387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1774922387
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3954366820
Short name T422
Test name
Test status
Simulation time 154866116 ps
CPU time 0.82 seconds
Started Jun 06 12:29:24 PM PDT 24
Finished Jun 06 12:29:27 PM PDT 24
Peak memory 200572 kb
Host smart-cd0270b9-6e08-4c15-b772-732c3eabe75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954366820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3954366820
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.1334351165
Short name T310
Test name
Test status
Simulation time 1449964165 ps
CPU time 5.62 seconds
Started Jun 06 12:29:27 PM PDT 24
Finished Jun 06 12:29:35 PM PDT 24
Peak memory 200996 kb
Host smart-bec97ec3-14cf-443f-949d-548512403037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334351165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1334351165
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.352829007
Short name T328
Test name
Test status
Simulation time 174524420 ps
CPU time 1.16 seconds
Started Jun 06 12:29:23 PM PDT 24
Finished Jun 06 12:29:27 PM PDT 24
Peak memory 200748 kb
Host smart-1783b6a2-8d27-4fee-b822-f14b1bb98ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352829007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.352829007
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2535095558
Short name T203
Test name
Test status
Simulation time 189998932 ps
CPU time 1.33 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:31 PM PDT 24
Peak memory 200992 kb
Host smart-6344deb4-5825-4b28-aaef-6486efbd688c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535095558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2535095558
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.2764797635
Short name T49
Test name
Test status
Simulation time 6678576532 ps
CPU time 21.2 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:45 PM PDT 24
Peak memory 201068 kb
Host smart-ee3415d3-4737-4132-93a0-235ef3fce5a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764797635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2764797635
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3936340024
Short name T250
Test name
Test status
Simulation time 460366399 ps
CPU time 2.58 seconds
Started Jun 06 12:29:18 PM PDT 24
Finished Jun 06 12:29:23 PM PDT 24
Peak memory 200692 kb
Host smart-4e080f02-e1c7-4fd0-9263-632deb77b045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936340024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3936340024
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1605803013
Short name T392
Test name
Test status
Simulation time 184613272 ps
CPU time 1.13 seconds
Started Jun 06 12:29:24 PM PDT 24
Finished Jun 06 12:29:28 PM PDT 24
Peak memory 200812 kb
Host smart-ac62cc8e-fd61-432c-9db4-59eb7f0f7bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605803013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1605803013
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2624395526
Short name T523
Test name
Test status
Simulation time 73647159 ps
CPU time 0.74 seconds
Started Jun 06 12:29:27 PM PDT 24
Finished Jun 06 12:29:30 PM PDT 24
Peak memory 200612 kb
Host smart-c6af6951-f12f-4555-84c6-0eb2ce21c6a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624395526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2624395526
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3860450254
Short name T52
Test name
Test status
Simulation time 1918051152 ps
CPU time 7.03 seconds
Started Jun 06 12:29:23 PM PDT 24
Finished Jun 06 12:29:32 PM PDT 24
Peak memory 218428 kb
Host smart-b4c6ef81-d163-4a40-88e6-5b329ad703f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860450254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3860450254
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1713411266
Short name T401
Test name
Test status
Simulation time 243612292 ps
CPU time 1.1 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:25 PM PDT 24
Peak memory 218100 kb
Host smart-b4aa3e28-d33f-4efb-a9a2-5ef60a5ff11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713411266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1713411266
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.178398207
Short name T20
Test name
Test status
Simulation time 88693445 ps
CPU time 0.76 seconds
Started Jun 06 12:29:24 PM PDT 24
Finished Jun 06 12:29:27 PM PDT 24
Peak memory 200616 kb
Host smart-0b368509-41eb-40f1-98ab-180266b89a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178398207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.178398207
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1566025045
Short name T229
Test name
Test status
Simulation time 1502052154 ps
CPU time 5.73 seconds
Started Jun 06 12:29:25 PM PDT 24
Finished Jun 06 12:29:33 PM PDT 24
Peak memory 200980 kb
Host smart-cc6f12b6-0ef3-4069-beb8-f4d1defd8990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566025045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1566025045
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1915976666
Short name T387
Test name
Test status
Simulation time 109541660 ps
CPU time 0.96 seconds
Started Jun 06 12:29:24 PM PDT 24
Finished Jun 06 12:29:28 PM PDT 24
Peak memory 200756 kb
Host smart-502cc266-375d-4127-84f0-74b42343b651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915976666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1915976666
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.3994892852
Short name T438
Test name
Test status
Simulation time 123696301 ps
CPU time 1.19 seconds
Started Jun 06 12:29:35 PM PDT 24
Finished Jun 06 12:29:38 PM PDT 24
Peak memory 200960 kb
Host smart-b9b6a008-fd41-46a8-aa52-c650a87e4540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994892852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.3994892852
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.4156880387
Short name T520
Test name
Test status
Simulation time 4888023835 ps
CPU time 16.24 seconds
Started Jun 06 12:29:24 PM PDT 24
Finished Jun 06 12:29:43 PM PDT 24
Peak memory 210880 kb
Host smart-542398f5-7e61-4b13-b991-1fdae5a0012d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156880387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.4156880387
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1164153048
Short name T517
Test name
Test status
Simulation time 362947401 ps
CPU time 2.31 seconds
Started Jun 06 12:29:31 PM PDT 24
Finished Jun 06 12:29:34 PM PDT 24
Peak memory 200780 kb
Host smart-e6cd3b03-08f4-4f69-87a3-22f565335377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164153048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1164153048
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1816287881
Short name T125
Test name
Test status
Simulation time 159570681 ps
CPU time 1.05 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:26 PM PDT 24
Peak memory 200768 kb
Host smart-88955279-3dec-45d6-8234-b55c638faa42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816287881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1816287881
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2540206942
Short name T287
Test name
Test status
Simulation time 69540404 ps
CPU time 0.82 seconds
Started Jun 06 12:29:20 PM PDT 24
Finished Jun 06 12:29:23 PM PDT 24
Peak memory 200904 kb
Host smart-3c305790-f808-49b4-992c-5fe4c65c78b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540206942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2540206942
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2113595756
Short name T55
Test name
Test status
Simulation time 1888413450 ps
CPU time 6.74 seconds
Started Jun 06 12:29:24 PM PDT 24
Finished Jun 06 12:29:33 PM PDT 24
Peak memory 218292 kb
Host smart-cd2511fa-65ae-4bca-a208-65ae4f62ca00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113595756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2113595756
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3141036682
Short name T465
Test name
Test status
Simulation time 243908926 ps
CPU time 1.1 seconds
Started Jun 06 12:29:20 PM PDT 24
Finished Jun 06 12:29:24 PM PDT 24
Peak memory 217924 kb
Host smart-aa18645f-23d6-4502-b72f-787ae6fed9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141036682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3141036682
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.4183244041
Short name T18
Test name
Test status
Simulation time 143991236 ps
CPU time 0.8 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:26 PM PDT 24
Peak memory 200600 kb
Host smart-af0cf088-c46d-4227-808f-1a3f67d45cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183244041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.4183244041
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3889767767
Short name T227
Test name
Test status
Simulation time 836962749 ps
CPU time 4.02 seconds
Started Jun 06 12:29:26 PM PDT 24
Finished Jun 06 12:29:32 PM PDT 24
Peak memory 200872 kb
Host smart-7b1fee77-bbde-4a24-b079-da0ad0366fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889767767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3889767767
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2264982996
Short name T434
Test name
Test status
Simulation time 148080701 ps
CPU time 1.09 seconds
Started Jun 06 12:29:25 PM PDT 24
Finished Jun 06 12:29:28 PM PDT 24
Peak memory 200784 kb
Host smart-1e8d39d8-1735-4795-ba64-4d728514f8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264982996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2264982996
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3710770358
Short name T251
Test name
Test status
Simulation time 112371022 ps
CPU time 1.13 seconds
Started Jun 06 12:29:25 PM PDT 24
Finished Jun 06 12:29:28 PM PDT 24
Peak memory 200940 kb
Host smart-05b1812b-33e2-4d3c-b7b9-a59c8ee85803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710770358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3710770358
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3137447745
Short name T383
Test name
Test status
Simulation time 4371157189 ps
CPU time 18.14 seconds
Started Jun 06 12:29:27 PM PDT 24
Finished Jun 06 12:29:47 PM PDT 24
Peak memory 209164 kb
Host smart-08361099-63ec-4abe-b096-69ef82ab1a47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137447745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3137447745
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3309815648
Short name T432
Test name
Test status
Simulation time 485608973 ps
CPU time 2.4 seconds
Started Jun 06 12:29:24 PM PDT 24
Finished Jun 06 12:29:29 PM PDT 24
Peak memory 200788 kb
Host smart-2772542f-7075-4947-a89f-6cc49f3335e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309815648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3309815648
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.537000536
Short name T283
Test name
Test status
Simulation time 152651362 ps
CPU time 1.11 seconds
Started Jun 06 12:29:18 PM PDT 24
Finished Jun 06 12:29:21 PM PDT 24
Peak memory 200776 kb
Host smart-8fa40e75-5574-42ce-93d8-a4104436f730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537000536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.537000536
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.70365157
Short name T79
Test name
Test status
Simulation time 56163008 ps
CPU time 0.72 seconds
Started Jun 06 12:29:24 PM PDT 24
Finished Jun 06 12:29:27 PM PDT 24
Peak memory 200600 kb
Host smart-2c1b8d34-5cc2-4948-a15e-38f993de5666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70365157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.70365157
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3314288885
Short name T487
Test name
Test status
Simulation time 1903792108 ps
CPU time 6.56 seconds
Started Jun 06 12:29:24 PM PDT 24
Finished Jun 06 12:29:34 PM PDT 24
Peak memory 217316 kb
Host smart-bf411290-a70f-4b6d-9959-f2f61124c6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314288885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3314288885
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1128603603
Short name T214
Test name
Test status
Simulation time 245917714 ps
CPU time 1.04 seconds
Started Jun 06 12:29:24 PM PDT 24
Finished Jun 06 12:29:32 PM PDT 24
Peak memory 217904 kb
Host smart-51afa83b-f6b9-4ff0-a79e-9d27777486a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128603603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1128603603
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.3196634650
Short name T497
Test name
Test status
Simulation time 198491144 ps
CPU time 0.85 seconds
Started Jun 06 12:29:25 PM PDT 24
Finished Jun 06 12:29:28 PM PDT 24
Peak memory 200580 kb
Host smart-dc4662a4-4122-42e8-b127-3ccdb8fe60b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196634650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3196634650
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2134553670
Short name T337
Test name
Test status
Simulation time 1694926058 ps
CPU time 5.71 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:31 PM PDT 24
Peak memory 200960 kb
Host smart-48dbadec-7d0e-497b-ba4b-4b5b07929584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134553670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2134553670
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.326193869
Short name T510
Test name
Test status
Simulation time 95613143 ps
CPU time 0.96 seconds
Started Jun 06 12:29:23 PM PDT 24
Finished Jun 06 12:29:26 PM PDT 24
Peak memory 200788 kb
Host smart-00141b27-9138-453f-a200-64c96a4c869e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326193869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.326193869
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1161076939
Short name T296
Test name
Test status
Simulation time 115323186 ps
CPU time 1.18 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:26 PM PDT 24
Peak memory 200948 kb
Host smart-553f319a-3204-41c4-9da3-0e26461dad93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161076939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1161076939
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.377623067
Short name T428
Test name
Test status
Simulation time 5429191306 ps
CPU time 19.47 seconds
Started Jun 06 12:29:17 PM PDT 24
Finished Jun 06 12:29:39 PM PDT 24
Peak memory 201160 kb
Host smart-77c3d33b-920e-40e1-94f6-98328954dbe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377623067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.377623067
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2564166425
Short name T374
Test name
Test status
Simulation time 144198434 ps
CPU time 1.72 seconds
Started Jun 06 12:29:23 PM PDT 24
Finished Jun 06 12:29:27 PM PDT 24
Peak memory 200792 kb
Host smart-243e0b57-fb02-4916-b72d-b67541b8cce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564166425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2564166425
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.625247711
Short name T192
Test name
Test status
Simulation time 93532698 ps
CPU time 0.95 seconds
Started Jun 06 12:29:25 PM PDT 24
Finished Jun 06 12:29:28 PM PDT 24
Peak memory 200800 kb
Host smart-f017df6e-f183-445a-8863-72d6f91ef97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625247711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.625247711
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.297016077
Short name T252
Test name
Test status
Simulation time 62581883 ps
CPU time 0.71 seconds
Started Jun 06 12:29:19 PM PDT 24
Finished Jun 06 12:29:22 PM PDT 24
Peak memory 200632 kb
Host smart-bcc2892b-3fdb-4cfe-906c-95d1ffa5ed83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297016077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.297016077
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.64894586
Short name T42
Test name
Test status
Simulation time 1903923746 ps
CPU time 7.6 seconds
Started Jun 06 12:29:20 PM PDT 24
Finished Jun 06 12:29:29 PM PDT 24
Peak memory 222444 kb
Host smart-afc20e7d-e0fc-465f-a658-e282ce3db1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64894586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.64894586
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.401839386
Short name T351
Test name
Test status
Simulation time 245108973 ps
CPU time 1.03 seconds
Started Jun 06 12:29:24 PM PDT 24
Finished Jun 06 12:29:27 PM PDT 24
Peak memory 217832 kb
Host smart-b10ebd70-3cbf-4112-90e9-d35c7ca7fce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401839386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.401839386
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.4204924177
Short name T521
Test name
Test status
Simulation time 141738080 ps
CPU time 0.91 seconds
Started Jun 06 12:29:19 PM PDT 24
Finished Jun 06 12:29:22 PM PDT 24
Peak memory 200500 kb
Host smart-f6dbf4f2-008e-4e98-9c28-cbe77a3de661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204924177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.4204924177
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3825976925
Short name T415
Test name
Test status
Simulation time 1706953847 ps
CPU time 6.7 seconds
Started Jun 06 12:29:19 PM PDT 24
Finished Jun 06 12:29:28 PM PDT 24
Peak memory 200884 kb
Host smart-e0528488-0d68-4e63-8283-8e2324c28a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825976925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3825976925
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1005455964
Short name T323
Test name
Test status
Simulation time 105527346 ps
CPU time 0.96 seconds
Started Jun 06 12:29:25 PM PDT 24
Finished Jun 06 12:29:37 PM PDT 24
Peak memory 200780 kb
Host smart-46220b26-2d83-47a6-bf2b-1c701c38300a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005455964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1005455964
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.715988868
Short name T514
Test name
Test status
Simulation time 196446572 ps
CPU time 1.3 seconds
Started Jun 06 12:29:24 PM PDT 24
Finished Jun 06 12:29:28 PM PDT 24
Peak memory 200892 kb
Host smart-c286c52d-d10f-4a64-a257-109756ec29dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715988868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.715988868
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.230492056
Short name T292
Test name
Test status
Simulation time 18487470191 ps
CPU time 68.61 seconds
Started Jun 06 12:29:17 PM PDT 24
Finished Jun 06 12:30:28 PM PDT 24
Peak memory 200840 kb
Host smart-fcfb5299-7cf2-4975-a99e-7b6cf7fdc75f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230492056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.230492056
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2399907400
Short name T210
Test name
Test status
Simulation time 151372356 ps
CPU time 1.73 seconds
Started Jun 06 12:29:20 PM PDT 24
Finished Jun 06 12:29:24 PM PDT 24
Peak memory 200728 kb
Host smart-377ca81a-1e6a-4499-b7e4-0fb27cdad1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399907400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2399907400
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1545640535
Short name T268
Test name
Test status
Simulation time 71568673 ps
CPU time 0.8 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:25 PM PDT 24
Peak memory 200792 kb
Host smart-7302e0cd-87c1-4913-9f87-c3a13492670f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545640535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1545640535
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3319384603
Short name T302
Test name
Test status
Simulation time 69410887 ps
CPU time 0.76 seconds
Started Jun 06 12:29:24 PM PDT 24
Finished Jun 06 12:29:27 PM PDT 24
Peak memory 200648 kb
Host smart-8badb332-11b0-4273-8ce4-359e8da04d0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319384603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3319384603
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2153328896
Short name T33
Test name
Test status
Simulation time 1221212768 ps
CPU time 5.29 seconds
Started Jun 06 12:29:24 PM PDT 24
Finished Jun 06 12:29:32 PM PDT 24
Peak memory 218368 kb
Host smart-61a76ae2-a2b4-4c07-b949-81874275a42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153328896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2153328896
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2061558927
Short name T475
Test name
Test status
Simulation time 244499009 ps
CPU time 1.08 seconds
Started Jun 06 12:29:18 PM PDT 24
Finished Jun 06 12:29:21 PM PDT 24
Peak memory 217864 kb
Host smart-46ea0cf2-7a54-438d-ab44-6c1d19d75051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061558927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2061558927
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.4179797832
Short name T164
Test name
Test status
Simulation time 237415392 ps
CPU time 1.03 seconds
Started Jun 06 12:29:42 PM PDT 24
Finished Jun 06 12:29:44 PM PDT 24
Peak memory 200632 kb
Host smart-2b913634-4c8b-43db-a6fa-1b4a583968c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179797832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.4179797832
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.4025992967
Short name T233
Test name
Test status
Simulation time 1119123593 ps
CPU time 5.44 seconds
Started Jun 06 12:29:25 PM PDT 24
Finished Jun 06 12:29:33 PM PDT 24
Peak memory 200944 kb
Host smart-6f872cc4-6efd-462d-b80d-390a367a9e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025992967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.4025992967
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.451688609
Short name T477
Test name
Test status
Simulation time 175482470 ps
CPU time 1.13 seconds
Started Jun 06 12:29:29 PM PDT 24
Finished Jun 06 12:29:32 PM PDT 24
Peak memory 200844 kb
Host smart-33589c85-7a63-4237-befb-e30e07f1c662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451688609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.451688609
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3696618995
Short name T342
Test name
Test status
Simulation time 112279667 ps
CPU time 1.09 seconds
Started Jun 06 12:29:23 PM PDT 24
Finished Jun 06 12:29:27 PM PDT 24
Peak memory 200920 kb
Host smart-2263d8fa-6f59-4627-915a-0dde0b706833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696618995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3696618995
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.713328234
Short name T222
Test name
Test status
Simulation time 2733634331 ps
CPU time 9.56 seconds
Started Jun 06 12:29:23 PM PDT 24
Finished Jun 06 12:29:35 PM PDT 24
Peak memory 201120 kb
Host smart-7c512398-8c7a-4467-b767-d645cce7f428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713328234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.713328234
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3162826660
Short name T151
Test name
Test status
Simulation time 289024153 ps
CPU time 1.85 seconds
Started Jun 06 12:29:24 PM PDT 24
Finished Jun 06 12:29:28 PM PDT 24
Peak memory 200736 kb
Host smart-d849f682-edfc-40e9-a111-821527f537cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162826660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3162826660
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1120086041
Short name T493
Test name
Test status
Simulation time 83776387 ps
CPU time 0.8 seconds
Started Jun 06 12:29:27 PM PDT 24
Finished Jun 06 12:29:30 PM PDT 24
Peak memory 200772 kb
Host smart-fae2cd9e-ad19-4584-844b-601fbf5a370a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120086041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1120086041
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2734402910
Short name T260
Test name
Test status
Simulation time 62534668 ps
CPU time 0.73 seconds
Started Jun 06 12:28:36 PM PDT 24
Finished Jun 06 12:28:39 PM PDT 24
Peak memory 200652 kb
Host smart-50bfa71e-6351-47a4-91b1-8db721688bdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734402910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2734402910
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2875645909
Short name T39
Test name
Test status
Simulation time 1218241983 ps
CPU time 5.33 seconds
Started Jun 06 12:28:41 PM PDT 24
Finished Jun 06 12:28:48 PM PDT 24
Peak memory 217908 kb
Host smart-3706f65b-ae79-4d67-a2b5-0c2765087b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875645909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2875645909
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2119052614
Short name T326
Test name
Test status
Simulation time 244064738 ps
CPU time 1.16 seconds
Started Jun 06 12:28:33 PM PDT 24
Finished Jun 06 12:28:36 PM PDT 24
Peak memory 217940 kb
Host smart-637fe5b7-1923-47db-9f10-387619b36f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119052614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2119052614
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3556114684
Short name T226
Test name
Test status
Simulation time 226792062 ps
CPU time 1 seconds
Started Jun 06 12:28:32 PM PDT 24
Finished Jun 06 12:28:35 PM PDT 24
Peak memory 200492 kb
Host smart-b1813dfe-11c7-4643-ad9e-6d72cf8930c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556114684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3556114684
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.4068654815
Short name T406
Test name
Test status
Simulation time 1223616192 ps
CPU time 5.07 seconds
Started Jun 06 12:28:28 PM PDT 24
Finished Jun 06 12:28:35 PM PDT 24
Peak memory 200980 kb
Host smart-130e10e1-4589-4161-9d49-af44768ad181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068654815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.4068654815
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.4264599669
Short name T69
Test name
Test status
Simulation time 16546877491 ps
CPU time 28.19 seconds
Started Jun 06 12:28:33 PM PDT 24
Finished Jun 06 12:29:02 PM PDT 24
Peak memory 217620 kb
Host smart-c625157e-e82b-4413-ac43-d4fa4d7eaf9a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264599669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.4264599669
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.4042096782
Short name T137
Test name
Test status
Simulation time 101031006 ps
CPU time 0.99 seconds
Started Jun 06 12:28:32 PM PDT 24
Finished Jun 06 12:28:34 PM PDT 24
Peak memory 200772 kb
Host smart-9c13d94e-2d50-4a90-8a47-d33c3e249816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042096782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.4042096782
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1883628453
Short name T298
Test name
Test status
Simulation time 244024650 ps
CPU time 1.47 seconds
Started Jun 06 12:28:28 PM PDT 24
Finished Jun 06 12:28:31 PM PDT 24
Peak memory 200924 kb
Host smart-068724b2-482a-4ba4-ac3e-047a896d02eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883628453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1883628453
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.623591858
Short name T172
Test name
Test status
Simulation time 5605782648 ps
CPU time 19.7 seconds
Started Jun 06 12:28:32 PM PDT 24
Finished Jun 06 12:28:53 PM PDT 24
Peak memory 217200 kb
Host smart-c0fb4da1-45c2-47f4-a09d-6902271fdb16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623591858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.623591858
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.958319932
Short name T504
Test name
Test status
Simulation time 286527690 ps
CPU time 1.99 seconds
Started Jun 06 12:28:34 PM PDT 24
Finished Jun 06 12:28:37 PM PDT 24
Peak memory 208928 kb
Host smart-3fa58d95-62fd-4e6d-868b-2c7d39d706f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958319932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.958319932
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2086160773
Short name T420
Test name
Test status
Simulation time 94440445 ps
CPU time 0.93 seconds
Started Jun 06 12:28:33 PM PDT 24
Finished Jun 06 12:28:35 PM PDT 24
Peak memory 201068 kb
Host smart-ddb26efa-497a-4650-94e3-22d0fa90cc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086160773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2086160773
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3620419576
Short name T525
Test name
Test status
Simulation time 77150493 ps
CPU time 0.78 seconds
Started Jun 06 12:29:21 PM PDT 24
Finished Jun 06 12:29:24 PM PDT 24
Peak memory 200628 kb
Host smart-629d0457-f2ed-4b56-ab36-5b56d9fd068d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620419576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3620419576
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2055204299
Short name T518
Test name
Test status
Simulation time 1884578581 ps
CPU time 6.76 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:31 PM PDT 24
Peak memory 218392 kb
Host smart-23b6b76a-49f5-42f2-9068-57d6593ddbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055204299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2055204299
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.69794855
Short name T168
Test name
Test status
Simulation time 244707732 ps
CPU time 1.07 seconds
Started Jun 06 12:29:29 PM PDT 24
Finished Jun 06 12:29:32 PM PDT 24
Peak memory 217932 kb
Host smart-9804a70f-9534-4fee-94c3-6fd63809b87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69794855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.69794855
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.719962764
Short name T16
Test name
Test status
Simulation time 126273733 ps
CPU time 0.79 seconds
Started Jun 06 12:29:25 PM PDT 24
Finished Jun 06 12:29:28 PM PDT 24
Peak memory 200568 kb
Host smart-235d829b-dd5f-4086-be0f-fa360b5fabe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719962764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.719962764
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.399630892
Short name T193
Test name
Test status
Simulation time 1617701697 ps
CPU time 6.15 seconds
Started Jun 06 12:29:21 PM PDT 24
Finished Jun 06 12:29:29 PM PDT 24
Peak memory 200988 kb
Host smart-14c46ccd-fcdb-4c42-be85-ccb596d2caf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399630892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.399630892
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1951342166
Short name T215
Test name
Test status
Simulation time 141576660 ps
CPU time 1.06 seconds
Started Jun 06 12:29:27 PM PDT 24
Finished Jun 06 12:29:30 PM PDT 24
Peak memory 200772 kb
Host smart-225c5df8-13c2-4cc9-bc29-676f96566e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951342166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1951342166
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.1583087883
Short name T158
Test name
Test status
Simulation time 190857484 ps
CPU time 1.48 seconds
Started Jun 06 12:30:05 PM PDT 24
Finished Jun 06 12:30:07 PM PDT 24
Peak memory 201008 kb
Host smart-4008a563-83da-4343-9c20-d55b42ef47cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583087883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1583087883
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.1989634614
Short name T205
Test name
Test status
Simulation time 10697324271 ps
CPU time 37.18 seconds
Started Jun 06 12:29:26 PM PDT 24
Finished Jun 06 12:30:05 PM PDT 24
Peak memory 209564 kb
Host smart-8df0d75d-e1e2-4b48-a0ff-e250d3082349
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989634614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1989634614
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.3850990769
Short name T318
Test name
Test status
Simulation time 145200008 ps
CPU time 1.72 seconds
Started Jun 06 12:29:21 PM PDT 24
Finished Jun 06 12:29:25 PM PDT 24
Peak memory 200756 kb
Host smart-bb1209ee-178d-4246-8087-cb16c8cd2dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850990769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3850990769
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.614456430
Short name T141
Test name
Test status
Simulation time 108355699 ps
CPU time 0.88 seconds
Started Jun 06 12:29:47 PM PDT 24
Finished Jun 06 12:29:48 PM PDT 24
Peak memory 200788 kb
Host smart-5d1b8753-68ce-4f3e-afa7-64cfb949bf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614456430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.614456430
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1788296384
Short name T249
Test name
Test status
Simulation time 60320781 ps
CPU time 0.75 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:25 PM PDT 24
Peak memory 200604 kb
Host smart-a0546086-2c7d-4d68-b25c-238278043ce7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788296384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1788296384
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3430702986
Short name T179
Test name
Test status
Simulation time 244870888 ps
CPU time 1.07 seconds
Started Jun 06 12:29:31 PM PDT 24
Finished Jun 06 12:29:34 PM PDT 24
Peak memory 217876 kb
Host smart-5957d402-3ca0-4dbe-a29f-a927cfa62289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430702986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3430702986
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.3538200619
Short name T189
Test name
Test status
Simulation time 170855700 ps
CPU time 0.87 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:25 PM PDT 24
Peak memory 200600 kb
Host smart-a5c0808b-cd1d-47ad-a721-420070db007d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538200619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3538200619
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2507297929
Short name T471
Test name
Test status
Simulation time 1248245069 ps
CPU time 5.48 seconds
Started Jun 06 12:29:24 PM PDT 24
Finished Jun 06 12:29:33 PM PDT 24
Peak memory 200976 kb
Host smart-cdcd96b9-c6e6-463c-ad88-fc10954729b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507297929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2507297929
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.442021323
Short name T373
Test name
Test status
Simulation time 112397673 ps
CPU time 0.99 seconds
Started Jun 06 12:29:26 PM PDT 24
Finished Jun 06 12:29:29 PM PDT 24
Peak memory 200812 kb
Host smart-442d40f8-65ee-4d96-a38e-ce2bfa415fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442021323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.442021323
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1437483669
Short name T437
Test name
Test status
Simulation time 114897555 ps
CPU time 1.15 seconds
Started Jun 06 12:29:26 PM PDT 24
Finished Jun 06 12:29:29 PM PDT 24
Peak memory 200920 kb
Host smart-93e3962a-426d-45f8-9651-1f115715e0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437483669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1437483669
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.2306184446
Short name T247
Test name
Test status
Simulation time 2812433363 ps
CPU time 9.83 seconds
Started Jun 06 12:29:25 PM PDT 24
Finished Jun 06 12:29:38 PM PDT 24
Peak memory 201120 kb
Host smart-1ca202a8-50d2-4b38-96b2-1af5b0e2cc71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306184446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2306184446
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2561465583
Short name T495
Test name
Test status
Simulation time 137275945 ps
CPU time 1.55 seconds
Started Jun 06 12:29:25 PM PDT 24
Finished Jun 06 12:29:29 PM PDT 24
Peak memory 209008 kb
Host smart-535bfc13-bf36-4d81-b013-174692c474ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561465583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2561465583
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2405600074
Short name T319
Test name
Test status
Simulation time 199291588 ps
CPU time 1.22 seconds
Started Jun 06 12:29:28 PM PDT 24
Finished Jun 06 12:29:31 PM PDT 24
Peak memory 200808 kb
Host smart-7bd30ae3-c550-4738-85c6-d8dbc24a1c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405600074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2405600074
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1623655475
Short name T244
Test name
Test status
Simulation time 69239455 ps
CPU time 0.79 seconds
Started Jun 06 12:29:32 PM PDT 24
Finished Jun 06 12:29:34 PM PDT 24
Peak memory 200576 kb
Host smart-810f8805-3c42-44d9-abd4-71b741bea9f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623655475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1623655475
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1296272945
Short name T480
Test name
Test status
Simulation time 1221338065 ps
CPU time 5.31 seconds
Started Jun 06 12:29:28 PM PDT 24
Finished Jun 06 12:29:35 PM PDT 24
Peak memory 218380 kb
Host smart-47ac0e4e-ec9c-480c-8270-633854ffb7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296272945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1296272945
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.3039255141
Short name T156
Test name
Test status
Simulation time 244958347 ps
CPU time 1.04 seconds
Started Jun 06 12:29:25 PM PDT 24
Finished Jun 06 12:29:28 PM PDT 24
Peak memory 217876 kb
Host smart-8bc2217a-280c-4fb0-b9f7-b17ed99e4d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039255141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.3039255141
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1750175226
Short name T443
Test name
Test status
Simulation time 86526440 ps
CPU time 0.75 seconds
Started Jun 06 12:29:27 PM PDT 24
Finished Jun 06 12:29:30 PM PDT 24
Peak memory 200468 kb
Host smart-442a3421-96cd-4fc0-9fc5-2ad21952744e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750175226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1750175226
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3110859988
Short name T301
Test name
Test status
Simulation time 1542967634 ps
CPU time 5.7 seconds
Started Jun 06 12:29:24 PM PDT 24
Finished Jun 06 12:29:32 PM PDT 24
Peak memory 200944 kb
Host smart-a4514db3-8e31-4123-98c4-b3cd60f53c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110859988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3110859988
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.774873212
Short name T173
Test name
Test status
Simulation time 174493669 ps
CPU time 1.13 seconds
Started Jun 06 12:29:31 PM PDT 24
Finished Jun 06 12:29:34 PM PDT 24
Peak memory 200788 kb
Host smart-e6e42ca3-b02f-4b02-85f5-0c2324adf8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774873212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.774873212
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3338514555
Short name T145
Test name
Test status
Simulation time 115194807 ps
CPU time 1.11 seconds
Started Jun 06 12:29:25 PM PDT 24
Finished Jun 06 12:29:29 PM PDT 24
Peak memory 200812 kb
Host smart-68519eaf-3014-4283-953b-e8dd44b643c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338514555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3338514555
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1179014483
Short name T178
Test name
Test status
Simulation time 5321952378 ps
CPU time 18.64 seconds
Started Jun 06 12:29:39 PM PDT 24
Finished Jun 06 12:29:59 PM PDT 24
Peak memory 201112 kb
Host smart-5da29bc3-92b4-4440-9f6b-23ea085abe33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179014483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1179014483
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.2072046778
Short name T385
Test name
Test status
Simulation time 67869782 ps
CPU time 0.77 seconds
Started Jun 06 12:29:25 PM PDT 24
Finished Jun 06 12:29:28 PM PDT 24
Peak memory 200788 kb
Host smart-dd3bb70c-30d7-4a05-9b3b-c65505cf4af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072046778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2072046778
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2274557005
Short name T197
Test name
Test status
Simulation time 73608554 ps
CPU time 0.81 seconds
Started Jun 06 12:29:19 PM PDT 24
Finished Jun 06 12:29:22 PM PDT 24
Peak memory 200596 kb
Host smart-6ea8e851-bc54-4653-9622-ec7fb99ba110
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274557005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2274557005
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3781698690
Short name T37
Test name
Test status
Simulation time 2356083641 ps
CPU time 7.94 seconds
Started Jun 06 12:29:24 PM PDT 24
Finished Jun 06 12:29:35 PM PDT 24
Peak memory 218480 kb
Host smart-41e05546-b1cf-4cf4-9d43-a87e4410e83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781698690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3781698690
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1256892384
Short name T421
Test name
Test status
Simulation time 244155239 ps
CPU time 1.17 seconds
Started Jun 06 12:29:26 PM PDT 24
Finished Jun 06 12:29:29 PM PDT 24
Peak memory 218208 kb
Host smart-6dac96be-91f8-459f-aca3-3958e36bd5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256892384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1256892384
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2776973145
Short name T234
Test name
Test status
Simulation time 175026891 ps
CPU time 0.85 seconds
Started Jun 06 12:29:26 PM PDT 24
Finished Jun 06 12:29:29 PM PDT 24
Peak memory 200628 kb
Host smart-08eae1fa-0d99-4b41-bfb4-12f38c439571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776973145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2776973145
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.973245504
Short name T307
Test name
Test status
Simulation time 1521294278 ps
CPU time 5.42 seconds
Started Jun 06 12:29:27 PM PDT 24
Finished Jun 06 12:29:35 PM PDT 24
Peak memory 201040 kb
Host smart-73489d6f-afc0-4299-93a5-f3353185eeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973245504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.973245504
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1251331646
Short name T2
Test name
Test status
Simulation time 155736446 ps
CPU time 1.1 seconds
Started Jun 06 12:29:20 PM PDT 24
Finished Jun 06 12:29:23 PM PDT 24
Peak memory 200768 kb
Host smart-45e1dedb-22e0-4ff6-8224-320caf230ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251331646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1251331646
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.102169960
Short name T354
Test name
Test status
Simulation time 252537635 ps
CPU time 1.41 seconds
Started Jun 06 12:29:21 PM PDT 24
Finished Jun 06 12:29:24 PM PDT 24
Peak memory 200968 kb
Host smart-8eada3e2-5fd3-4528-acd5-1693695c01fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102169960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.102169960
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3879671095
Short name T94
Test name
Test status
Simulation time 4881823996 ps
CPU time 22.25 seconds
Started Jun 06 12:29:22 PM PDT 24
Finished Jun 06 12:29:47 PM PDT 24
Peak memory 201172 kb
Host smart-d3a505cc-7082-42df-809e-7c2e34edf175
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879671095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3879671095
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1149730078
Short name T171
Test name
Test status
Simulation time 146490382 ps
CPU time 1.92 seconds
Started Jun 06 12:29:29 PM PDT 24
Finished Jun 06 12:29:33 PM PDT 24
Peak memory 200684 kb
Host smart-53c6b516-52de-42f4-ad69-3cafc9d6d6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149730078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1149730078
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.4279733805
Short name T264
Test name
Test status
Simulation time 103453373 ps
CPU time 0.98 seconds
Started Jun 06 12:29:27 PM PDT 24
Finished Jun 06 12:29:30 PM PDT 24
Peak memory 200812 kb
Host smart-acebca27-5363-4e68-995d-e2ad4603a264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279733805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.4279733805
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.130895502
Short name T526
Test name
Test status
Simulation time 66665430 ps
CPU time 0.76 seconds
Started Jun 06 12:29:31 PM PDT 24
Finished Jun 06 12:29:33 PM PDT 24
Peak memory 200540 kb
Host smart-491c7821-1d22-47ad-a162-0871e165635f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130895502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.130895502
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3985893348
Short name T372
Test name
Test status
Simulation time 1222338225 ps
CPU time 5.08 seconds
Started Jun 06 12:29:31 PM PDT 24
Finished Jun 06 12:29:37 PM PDT 24
Peak memory 222496 kb
Host smart-4f4af4f9-c4f8-4d64-8529-3375c19d180e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985893348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3985893348
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1889285233
Short name T303
Test name
Test status
Simulation time 243699053 ps
CPU time 1.16 seconds
Started Jun 06 12:29:51 PM PDT 24
Finished Jun 06 12:29:53 PM PDT 24
Peak memory 218060 kb
Host smart-a4e978ca-fa48-4f8f-9609-5b502aa30eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889285233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1889285233
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.1054354670
Short name T321
Test name
Test status
Simulation time 192161179 ps
CPU time 0.9 seconds
Started Jun 06 12:30:11 PM PDT 24
Finished Jun 06 12:30:13 PM PDT 24
Peak memory 200624 kb
Host smart-d7890e5e-39a4-4930-85ce-4b7a786c5efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054354670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1054354670
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.4288885218
Short name T269
Test name
Test status
Simulation time 1160533853 ps
CPU time 4.81 seconds
Started Jun 06 12:30:16 PM PDT 24
Finished Jun 06 12:30:22 PM PDT 24
Peak memory 200960 kb
Host smart-fd36bda7-092b-4be0-a275-54fcad389186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288885218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.4288885218
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1487639070
Short name T130
Test name
Test status
Simulation time 109577896 ps
CPU time 1.02 seconds
Started Jun 06 12:29:26 PM PDT 24
Finished Jun 06 12:29:29 PM PDT 24
Peak memory 200816 kb
Host smart-fe5a50e0-bcb5-4229-ae7a-6ada824c03bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487639070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1487639070
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1535254459
Short name T51
Test name
Test status
Simulation time 117359131 ps
CPU time 1.11 seconds
Started Jun 06 12:29:30 PM PDT 24
Finished Jun 06 12:29:32 PM PDT 24
Peak memory 200884 kb
Host smart-85631e7f-e64e-4406-9cf0-adec441e26ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535254459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1535254459
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1661121956
Short name T457
Test name
Test status
Simulation time 3410103746 ps
CPU time 15.69 seconds
Started Jun 06 12:29:36 PM PDT 24
Finished Jun 06 12:29:53 PM PDT 24
Peak memory 209340 kb
Host smart-1ef29910-75f3-4bbd-bca1-1e6f7dde8c8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661121956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1661121956
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.152688698
Short name T1
Test name
Test status
Simulation time 135863807 ps
CPU time 1.71 seconds
Started Jun 06 12:30:12 PM PDT 24
Finished Jun 06 12:30:15 PM PDT 24
Peak memory 200768 kb
Host smart-adb40f74-40de-4360-953f-526f24ed35dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152688698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.152688698
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1389685606
Short name T194
Test name
Test status
Simulation time 83457368 ps
CPU time 0.77 seconds
Started Jun 06 12:30:10 PM PDT 24
Finished Jun 06 12:30:12 PM PDT 24
Peak memory 200788 kb
Host smart-f23097c1-ec9f-4a10-b85f-4b5b0327debb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389685606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1389685606
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3986859170
Short name T484
Test name
Test status
Simulation time 79786409 ps
CPU time 0.76 seconds
Started Jun 06 12:29:35 PM PDT 24
Finished Jun 06 12:29:37 PM PDT 24
Peak memory 200536 kb
Host smart-192dec79-8b29-4492-8dc2-90211466a3a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986859170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3986859170
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.902953024
Short name T57
Test name
Test status
Simulation time 2355456888 ps
CPU time 7.48 seconds
Started Jun 06 12:30:12 PM PDT 24
Finished Jun 06 12:30:21 PM PDT 24
Peak memory 222332 kb
Host smart-d61849b6-7f71-40db-8f07-9f0d5d7055b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902953024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.902953024
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.4183686163
Short name T66
Test name
Test status
Simulation time 248106781 ps
CPU time 1.08 seconds
Started Jun 06 12:29:31 PM PDT 24
Finished Jun 06 12:29:38 PM PDT 24
Peak memory 217920 kb
Host smart-c5871c41-fb76-4e71-883c-7351b9d4f0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183686163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.4183686163
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.4100280113
Short name T9
Test name
Test status
Simulation time 170989418 ps
CPU time 0.82 seconds
Started Jun 06 12:29:26 PM PDT 24
Finished Jun 06 12:29:29 PM PDT 24
Peak memory 200468 kb
Host smart-40426f3d-77e2-4878-a2cf-b4c6faa29937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100280113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.4100280113
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2319589607
Short name T500
Test name
Test status
Simulation time 2212552064 ps
CPU time 7.25 seconds
Started Jun 06 12:30:26 PM PDT 24
Finished Jun 06 12:30:36 PM PDT 24
Peak memory 201052 kb
Host smart-9ca886b9-ca29-4ce8-9487-0cca5b18b480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319589607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2319589607
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2603368440
Short name T198
Test name
Test status
Simulation time 154407806 ps
CPU time 1.13 seconds
Started Jun 06 12:29:37 PM PDT 24
Finished Jun 06 12:29:39 PM PDT 24
Peak memory 200796 kb
Host smart-8566c5f5-835a-41f5-baa9-5bebee393568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603368440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2603368440
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2261271884
Short name T129
Test name
Test status
Simulation time 191026682 ps
CPU time 1.28 seconds
Started Jun 06 12:29:27 PM PDT 24
Finished Jun 06 12:29:31 PM PDT 24
Peak memory 200940 kb
Host smart-6d3928cd-ea75-4b18-9853-e2aa590a5755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261271884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2261271884
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.858143982
Short name T389
Test name
Test status
Simulation time 5762127118 ps
CPU time 23.28 seconds
Started Jun 06 12:30:00 PM PDT 24
Finished Jun 06 12:30:25 PM PDT 24
Peak memory 201088 kb
Host smart-8f869d14-7199-4b58-8e80-c62ade3fe491
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858143982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.858143982
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.424144337
Short name T322
Test name
Test status
Simulation time 430042408 ps
CPU time 2.25 seconds
Started Jun 06 12:29:28 PM PDT 24
Finished Jun 06 12:29:32 PM PDT 24
Peak memory 208988 kb
Host smart-1de1ad4b-e1a9-4432-942a-50041913f532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424144337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.424144337
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.188070346
Short name T221
Test name
Test status
Simulation time 100290491 ps
CPU time 0.84 seconds
Started Jun 06 12:29:31 PM PDT 24
Finished Jun 06 12:29:33 PM PDT 24
Peak memory 200732 kb
Host smart-b90f1f28-9b02-4c6b-b8db-9945ffdb210e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188070346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.188070346
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.1709089070
Short name T410
Test name
Test status
Simulation time 75490192 ps
CPU time 0.73 seconds
Started Jun 06 12:29:46 PM PDT 24
Finished Jun 06 12:29:47 PM PDT 24
Peak memory 200544 kb
Host smart-03999668-6e8c-4284-a280-38188baf6196
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709089070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1709089070
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.103558135
Short name T53
Test name
Test status
Simulation time 2171455726 ps
CPU time 7.48 seconds
Started Jun 06 12:29:41 PM PDT 24
Finished Jun 06 12:29:49 PM PDT 24
Peak memory 218560 kb
Host smart-71531ae0-d2d2-4dfc-8c75-769fd4d13109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103558135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.103558135
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3677075142
Short name T161
Test name
Test status
Simulation time 244158505 ps
CPU time 1 seconds
Started Jun 06 12:29:30 PM PDT 24
Finished Jun 06 12:29:32 PM PDT 24
Peak memory 217936 kb
Host smart-4372052e-ddae-4240-93a3-0163933287ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677075142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3677075142
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3197709909
Short name T289
Test name
Test status
Simulation time 192605966 ps
CPU time 0.87 seconds
Started Jun 06 12:29:33 PM PDT 24
Finished Jun 06 12:29:35 PM PDT 24
Peak memory 200520 kb
Host smart-18a6b7e2-667d-4018-8ac3-4710f7be6ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197709909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3197709909
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3727704845
Short name T124
Test name
Test status
Simulation time 1935335933 ps
CPU time 7.66 seconds
Started Jun 06 12:29:49 PM PDT 24
Finished Jun 06 12:29:58 PM PDT 24
Peak memory 200948 kb
Host smart-3c08b581-cc4f-441c-8a71-0027a4d37521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727704845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3727704845
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.594952428
Short name T44
Test name
Test status
Simulation time 105404023 ps
CPU time 0.95 seconds
Started Jun 06 12:29:39 PM PDT 24
Finished Jun 06 12:29:41 PM PDT 24
Peak memory 200780 kb
Host smart-ace2acd0-32a9-4b7f-a977-4b83cc894fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594952428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.594952428
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.3221216419
Short name T224
Test name
Test status
Simulation time 196777730 ps
CPU time 1.3 seconds
Started Jun 06 12:29:35 PM PDT 24
Finished Jun 06 12:29:38 PM PDT 24
Peak memory 200860 kb
Host smart-d36b015a-a73b-413d-998a-ef965e354b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221216419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3221216419
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3758618434
Short name T279
Test name
Test status
Simulation time 4065401800 ps
CPU time 17.72 seconds
Started Jun 06 12:30:06 PM PDT 24
Finished Jun 06 12:30:25 PM PDT 24
Peak memory 209276 kb
Host smart-db0b9bc3-76ca-466c-86f6-e1bccedc0b48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758618434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3758618434
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2053712010
Short name T263
Test name
Test status
Simulation time 134830765 ps
CPU time 1.6 seconds
Started Jun 06 12:29:54 PM PDT 24
Finished Jun 06 12:29:57 PM PDT 24
Peak memory 200756 kb
Host smart-fe95d6bd-974a-41ff-8dcb-cc52e018214c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053712010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2053712010
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.98598551
Short name T358
Test name
Test status
Simulation time 167615252 ps
CPU time 1.22 seconds
Started Jun 06 12:29:57 PM PDT 24
Finished Jun 06 12:30:00 PM PDT 24
Peak memory 200988 kb
Host smart-d0b4dafc-e28b-47a7-8eca-e5b63a7a3d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98598551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.98598551
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3222204385
Short name T363
Test name
Test status
Simulation time 64358715 ps
CPU time 0.72 seconds
Started Jun 06 12:29:28 PM PDT 24
Finished Jun 06 12:29:31 PM PDT 24
Peak memory 200620 kb
Host smart-25cc63e5-c36d-454b-bc68-88a844af71f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222204385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3222204385
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3692874907
Short name T513
Test name
Test status
Simulation time 1215747739 ps
CPU time 5.55 seconds
Started Jun 06 12:29:31 PM PDT 24
Finished Jun 06 12:29:38 PM PDT 24
Peak memory 217544 kb
Host smart-aea47704-8606-4f20-b58a-51a0330ee1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692874907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3692874907
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2573600071
Short name T369
Test name
Test status
Simulation time 244655556 ps
CPU time 1.09 seconds
Started Jun 06 12:29:33 PM PDT 24
Finished Jun 06 12:29:35 PM PDT 24
Peak memory 217952 kb
Host smart-903cc0db-a846-41cf-a843-8e0888ece1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573600071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2573600071
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.1967517699
Short name T291
Test name
Test status
Simulation time 202162851 ps
CPU time 0.85 seconds
Started Jun 06 12:29:29 PM PDT 24
Finished Jun 06 12:29:31 PM PDT 24
Peak memory 200548 kb
Host smart-859bb6aa-aedd-465e-9684-691d6516e11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967517699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1967517699
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2833245001
Short name T366
Test name
Test status
Simulation time 1546081493 ps
CPU time 6 seconds
Started Jun 06 12:29:29 PM PDT 24
Finished Jun 06 12:29:37 PM PDT 24
Peak memory 200992 kb
Host smart-d084e30d-ceb9-4e4d-a196-053a5508e1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833245001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2833245001
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2401671510
Short name T435
Test name
Test status
Simulation time 96951120 ps
CPU time 0.98 seconds
Started Jun 06 12:29:27 PM PDT 24
Finished Jun 06 12:29:31 PM PDT 24
Peak memory 200760 kb
Host smart-9ec378df-6d3e-4180-8bca-c962e5cc5de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401671510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2401671510
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2138909866
Short name T280
Test name
Test status
Simulation time 121328448 ps
CPU time 1.14 seconds
Started Jun 06 12:29:27 PM PDT 24
Finished Jun 06 12:29:30 PM PDT 24
Peak memory 200836 kb
Host smart-94161aab-6995-404d-bd89-abb3b13d2b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138909866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2138909866
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.4225829340
Short name T262
Test name
Test status
Simulation time 9729480822 ps
CPU time 37.9 seconds
Started Jun 06 12:29:38 PM PDT 24
Finished Jun 06 12:30:16 PM PDT 24
Peak memory 201100 kb
Host smart-2fe36c2c-6458-4523-913e-a7994dd62b7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225829340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.4225829340
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.746258478
Short name T84
Test name
Test status
Simulation time 122776864 ps
CPU time 1.59 seconds
Started Jun 06 12:29:27 PM PDT 24
Finished Jun 06 12:29:31 PM PDT 24
Peak memory 209036 kb
Host smart-e95573c5-4555-424e-9a54-45f8d73f2d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746258478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.746258478
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1905793767
Short name T537
Test name
Test status
Simulation time 76329028 ps
CPU time 0.76 seconds
Started Jun 06 12:29:27 PM PDT 24
Finished Jun 06 12:29:30 PM PDT 24
Peak memory 200764 kb
Host smart-f8a9d7cc-5333-433d-a7d3-dfd56b861c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905793767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1905793767
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3415015701
Short name T450
Test name
Test status
Simulation time 77653530 ps
CPU time 0.78 seconds
Started Jun 06 12:30:26 PM PDT 24
Finished Jun 06 12:30:29 PM PDT 24
Peak memory 200656 kb
Host smart-470ff60f-a5dd-44b5-9fb0-0fc572d53da5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415015701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3415015701
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.226124709
Short name T273
Test name
Test status
Simulation time 1232244781 ps
CPU time 5.34 seconds
Started Jun 06 12:30:28 PM PDT 24
Finished Jun 06 12:30:36 PM PDT 24
Peak memory 222488 kb
Host smart-9969250e-1adb-4a47-8b17-87a151b4b0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226124709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.226124709
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2253215504
Short name T430
Test name
Test status
Simulation time 243783175 ps
CPU time 1.1 seconds
Started Jun 06 12:29:33 PM PDT 24
Finished Jun 06 12:29:35 PM PDT 24
Peak memory 217936 kb
Host smart-f6481d86-8101-4b0e-8352-62ae554a43d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253215504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2253215504
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.4189112673
Short name T290
Test name
Test status
Simulation time 97703749 ps
CPU time 0.75 seconds
Started Jun 06 12:29:31 PM PDT 24
Finished Jun 06 12:29:33 PM PDT 24
Peak memory 200516 kb
Host smart-51fbb2f3-9648-4a98-9392-cc52bc781a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189112673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.4189112673
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.2773836299
Short name T285
Test name
Test status
Simulation time 832244739 ps
CPU time 3.81 seconds
Started Jun 06 12:29:47 PM PDT 24
Finished Jun 06 12:29:51 PM PDT 24
Peak memory 200952 kb
Host smart-02a0b228-e842-48fb-8390-d9afff7feeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773836299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2773836299
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2620363356
Short name T140
Test name
Test status
Simulation time 104448735 ps
CPU time 0.95 seconds
Started Jun 06 12:29:29 PM PDT 24
Finished Jun 06 12:29:32 PM PDT 24
Peak memory 200740 kb
Host smart-37bd712b-e5e8-4c95-93c4-b27d7efc315b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620363356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2620363356
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.933568284
Short name T442
Test name
Test status
Simulation time 126075223 ps
CPU time 1.14 seconds
Started Jun 06 12:29:27 PM PDT 24
Finished Jun 06 12:29:30 PM PDT 24
Peak memory 200972 kb
Host smart-6da994f1-1a7b-4e1d-8fdc-3fe7fbd0cada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933568284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.933568284
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3013509547
Short name T380
Test name
Test status
Simulation time 1362795080 ps
CPU time 5.14 seconds
Started Jun 06 12:29:36 PM PDT 24
Finished Jun 06 12:29:42 PM PDT 24
Peak memory 200984 kb
Host smart-89dd9f58-8512-41c6-8ee8-49b9c78cd045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013509547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3013509547
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.4064222531
Short name T409
Test name
Test status
Simulation time 330448306 ps
CPU time 2.21 seconds
Started Jun 06 12:29:28 PM PDT 24
Finished Jun 06 12:29:32 PM PDT 24
Peak memory 200744 kb
Host smart-aae36b7e-0439-4b8a-b312-eef99ffe18e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064222531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.4064222531
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2606260142
Short name T361
Test name
Test status
Simulation time 94279351 ps
CPU time 0.87 seconds
Started Jun 06 12:30:27 PM PDT 24
Finished Jun 06 12:30:31 PM PDT 24
Peak memory 200792 kb
Host smart-3277a3c9-fbb1-47a9-adf4-8b3d8873998d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606260142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2606260142
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1726563698
Short name T147
Test name
Test status
Simulation time 64815858 ps
CPU time 0.76 seconds
Started Jun 06 12:30:10 PM PDT 24
Finished Jun 06 12:30:12 PM PDT 24
Peak memory 200612 kb
Host smart-97d9478b-6f79-40bc-bb26-6dfe7dfb95da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726563698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1726563698
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2174133694
Short name T427
Test name
Test status
Simulation time 2345709523 ps
CPU time 8.08 seconds
Started Jun 06 12:31:15 PM PDT 24
Finished Jun 06 12:31:23 PM PDT 24
Peak memory 218192 kb
Host smart-69c8c378-4444-43d9-ba1b-8a7df9917980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174133694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2174133694
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1207457280
Short name T353
Test name
Test status
Simulation time 244082451 ps
CPU time 1.13 seconds
Started Jun 06 12:29:52 PM PDT 24
Finished Jun 06 12:29:54 PM PDT 24
Peak memory 217828 kb
Host smart-cda9d374-d125-4caf-98e5-2ad36498304d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207457280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1207457280
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.3100205857
Short name T314
Test name
Test status
Simulation time 150872277 ps
CPU time 0.82 seconds
Started Jun 06 12:29:43 PM PDT 24
Finished Jun 06 12:29:45 PM PDT 24
Peak memory 200580 kb
Host smart-072a72fe-6f30-4d84-a62b-b4754018b6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100205857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3100205857
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.373894004
Short name T478
Test name
Test status
Simulation time 1738720827 ps
CPU time 6.55 seconds
Started Jun 06 12:29:41 PM PDT 24
Finished Jun 06 12:29:48 PM PDT 24
Peak memory 200976 kb
Host smart-d76c2481-83a5-40e0-9e3f-7ee02c3845f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373894004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.373894004
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3441276187
Short name T169
Test name
Test status
Simulation time 108691800 ps
CPU time 0.98 seconds
Started Jun 06 12:30:11 PM PDT 24
Finished Jun 06 12:30:13 PM PDT 24
Peak memory 200780 kb
Host smart-196a4b36-2332-409a-9b11-4f3ef28a79a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441276187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3441276187
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3332922592
Short name T225
Test name
Test status
Simulation time 117113126 ps
CPU time 1.16 seconds
Started Jun 06 12:29:35 PM PDT 24
Finished Jun 06 12:29:37 PM PDT 24
Peak memory 200876 kb
Host smart-a2a9b9a4-def5-438c-b6fb-c5fbf7ed0ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332922592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3332922592
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3873984225
Short name T236
Test name
Test status
Simulation time 1627503531 ps
CPU time 6.57 seconds
Started Jun 06 12:29:32 PM PDT 24
Finished Jun 06 12:29:40 PM PDT 24
Peak memory 200948 kb
Host smart-86701d8c-9a6d-4d5d-a081-85e7993bbaf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873984225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3873984225
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.1197237941
Short name T470
Test name
Test status
Simulation time 125241610 ps
CPU time 1.49 seconds
Started Jun 06 12:29:39 PM PDT 24
Finished Jun 06 12:29:41 PM PDT 24
Peak memory 208936 kb
Host smart-cd4b86b1-f97f-4f44-a153-615e56bd5e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197237941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1197237941
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.971271354
Short name T277
Test name
Test status
Simulation time 161661795 ps
CPU time 1.26 seconds
Started Jun 06 12:29:31 PM PDT 24
Finished Jun 06 12:29:34 PM PDT 24
Peak memory 200744 kb
Host smart-f9814545-2baa-4a6c-ad71-649b156979e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971271354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.971271354
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2153257047
Short name T200
Test name
Test status
Simulation time 83539589 ps
CPU time 0.77 seconds
Started Jun 06 12:28:38 PM PDT 24
Finished Jun 06 12:28:40 PM PDT 24
Peak memory 200628 kb
Host smart-3d4a0412-8680-43c5-a14c-f8e96797b729
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153257047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2153257047
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.452624895
Short name T35
Test name
Test status
Simulation time 2356214452 ps
CPU time 8.62 seconds
Started Jun 06 12:28:39 PM PDT 24
Finished Jun 06 12:28:49 PM PDT 24
Peak memory 218592 kb
Host smart-dd266b38-678a-4330-983f-52b92c57ea26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452624895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.452624895
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.790088004
Short name T304
Test name
Test status
Simulation time 244991775 ps
CPU time 1.14 seconds
Started Jun 06 12:28:30 PM PDT 24
Finished Jun 06 12:28:33 PM PDT 24
Peak memory 217876 kb
Host smart-0d573d2d-a021-42d1-a2de-b73b045b9a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790088004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.790088004
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3808971604
Short name T22
Test name
Test status
Simulation time 211208133 ps
CPU time 0.93 seconds
Started Jun 06 12:28:34 PM PDT 24
Finished Jun 06 12:28:36 PM PDT 24
Peak memory 200876 kb
Host smart-75468756-5e0d-40b6-8103-5fa9bb429b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808971604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3808971604
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.3864002486
Short name T139
Test name
Test status
Simulation time 1220996108 ps
CPU time 4.72 seconds
Started Jun 06 12:28:36 PM PDT 24
Finished Jun 06 12:28:43 PM PDT 24
Peak memory 200884 kb
Host smart-0747b004-e317-4d6f-94a2-6d02defd9572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864002486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3864002486
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3957511571
Short name T382
Test name
Test status
Simulation time 113451334 ps
CPU time 1.01 seconds
Started Jun 06 12:28:37 PM PDT 24
Finished Jun 06 12:28:40 PM PDT 24
Peak memory 200700 kb
Host smart-de13551a-2e3d-43b6-bc9a-a655d160431c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957511571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3957511571
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1419478289
Short name T184
Test name
Test status
Simulation time 118617706 ps
CPU time 1.21 seconds
Started Jun 06 12:28:36 PM PDT 24
Finished Jun 06 12:28:39 PM PDT 24
Peak memory 200992 kb
Host smart-b4946a6f-5dfe-4661-8324-42933deaf285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419478289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1419478289
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1016007993
Short name T431
Test name
Test status
Simulation time 3264805627 ps
CPU time 10.9 seconds
Started Jun 06 12:28:35 PM PDT 24
Finished Jun 06 12:28:47 PM PDT 24
Peak memory 201060 kb
Host smart-e5ab38be-1375-429a-918d-33d794da5198
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016007993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1016007993
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3900268173
Short name T154
Test name
Test status
Simulation time 138705736 ps
CPU time 1.75 seconds
Started Jun 06 12:28:28 PM PDT 24
Finished Jun 06 12:28:32 PM PDT 24
Peak memory 200780 kb
Host smart-6d868277-f355-4114-863a-5d3ee8619b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900268173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3900268173
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.3792517857
Short name T419
Test name
Test status
Simulation time 121327808 ps
CPU time 1.03 seconds
Started Jun 06 12:28:34 PM PDT 24
Finished Jun 06 12:28:36 PM PDT 24
Peak memory 200716 kb
Host smart-e48d962a-9c3a-45c0-a1ce-db1091f25ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792517857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3792517857
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.894866381
Short name T509
Test name
Test status
Simulation time 67165644 ps
CPU time 0.75 seconds
Started Jun 06 12:28:38 PM PDT 24
Finished Jun 06 12:28:40 PM PDT 24
Peak memory 200532 kb
Host smart-85faccaf-5c5c-4a30-af8a-10a4a9bb869b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894866381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.894866381
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3688535051
Short name T219
Test name
Test status
Simulation time 1211795536 ps
CPU time 6.25 seconds
Started Jun 06 12:28:35 PM PDT 24
Finished Jun 06 12:28:42 PM PDT 24
Peak memory 217372 kb
Host smart-5b2948a0-db23-4afe-8d68-95be096dd166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688535051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3688535051
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.821548311
Short name T299
Test name
Test status
Simulation time 244322075 ps
CPU time 1.04 seconds
Started Jun 06 12:28:39 PM PDT 24
Finished Jun 06 12:28:41 PM PDT 24
Peak memory 217904 kb
Host smart-d2f9db67-c00e-46fb-9271-e2275afcfcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821548311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.821548311
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3217440451
Short name T21
Test name
Test status
Simulation time 145786717 ps
CPU time 0.86 seconds
Started Jun 06 12:28:33 PM PDT 24
Finished Jun 06 12:28:35 PM PDT 24
Peak memory 200568 kb
Host smart-7e47a90a-6c50-49e8-9b31-bc371605f844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217440451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3217440451
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.4281500576
Short name T97
Test name
Test status
Simulation time 1757762575 ps
CPU time 6.82 seconds
Started Jun 06 12:28:33 PM PDT 24
Finished Jun 06 12:28:41 PM PDT 24
Peak memory 200936 kb
Host smart-aef3f7d1-182a-4ee5-8d4a-7acb378f4cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281500576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.4281500576
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1054162311
Short name T297
Test name
Test status
Simulation time 158416540 ps
CPU time 1.16 seconds
Started Jun 06 12:28:35 PM PDT 24
Finished Jun 06 12:28:37 PM PDT 24
Peak memory 200792 kb
Host smart-7b182435-331e-466c-bc84-817e058304b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054162311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1054162311
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.3799913967
Short name T293
Test name
Test status
Simulation time 232041679 ps
CPU time 1.58 seconds
Started Jun 06 12:28:30 PM PDT 24
Finished Jun 06 12:28:33 PM PDT 24
Peak memory 200936 kb
Host smart-8a072e0f-a5e1-4b90-aa0a-1663a6982ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799913967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3799913967
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1579669210
Short name T312
Test name
Test status
Simulation time 1165587697 ps
CPU time 5.43 seconds
Started Jun 06 12:28:32 PM PDT 24
Finished Jun 06 12:28:39 PM PDT 24
Peak memory 209208 kb
Host smart-7f95e4d5-2f86-4537-8ac8-1ee106e50cc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579669210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1579669210
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.4175945977
Short name T188
Test name
Test status
Simulation time 143774675 ps
CPU time 1.74 seconds
Started Jun 06 12:28:39 PM PDT 24
Finished Jun 06 12:28:42 PM PDT 24
Peak memory 200772 kb
Host smart-711c36b5-55ec-453f-b73d-aff3dbcb8e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175945977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.4175945977
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1566718096
Short name T533
Test name
Test status
Simulation time 212858975 ps
CPU time 1.26 seconds
Started Jun 06 12:28:32 PM PDT 24
Finished Jun 06 12:28:35 PM PDT 24
Peak memory 200776 kb
Host smart-576222a5-43be-4552-a519-3b76c61564d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566718096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1566718096
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1472568410
Short name T284
Test name
Test status
Simulation time 73066872 ps
CPU time 0.78 seconds
Started Jun 06 12:28:39 PM PDT 24
Finished Jun 06 12:28:41 PM PDT 24
Peak memory 200620 kb
Host smart-8be8a641-5acc-4148-837f-c743bab0c393
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472568410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1472568410
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2007953812
Short name T56
Test name
Test status
Simulation time 1896838423 ps
CPU time 7.01 seconds
Started Jun 06 12:28:39 PM PDT 24
Finished Jun 06 12:28:47 PM PDT 24
Peak memory 222408 kb
Host smart-87d9d972-9679-4fa2-9274-11554556cf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007953812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2007953812
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3381654789
Short name T286
Test name
Test status
Simulation time 243648972 ps
CPU time 1.03 seconds
Started Jun 06 12:28:39 PM PDT 24
Finished Jun 06 12:28:42 PM PDT 24
Peak memory 218076 kb
Host smart-74edfd2f-3b82-4cbe-ab19-824b5b3a26da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381654789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3381654789
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.160255428
Short name T332
Test name
Test status
Simulation time 185745524 ps
CPU time 0.87 seconds
Started Jun 06 12:28:37 PM PDT 24
Finished Jun 06 12:28:40 PM PDT 24
Peak memory 200512 kb
Host smart-4da6d93d-b478-4a7b-b713-ee50ad03b7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160255428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.160255428
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.1537248132
Short name T46
Test name
Test status
Simulation time 1993511430 ps
CPU time 6.87 seconds
Started Jun 06 12:28:38 PM PDT 24
Finished Jun 06 12:28:47 PM PDT 24
Peak memory 200948 kb
Host smart-8fdf1a02-3afa-4dfb-8185-5e1bd672e009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537248132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1537248132
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3305226023
Short name T316
Test name
Test status
Simulation time 148536763 ps
CPU time 1.17 seconds
Started Jun 06 12:28:37 PM PDT 24
Finished Jun 06 12:28:40 PM PDT 24
Peak memory 200728 kb
Host smart-fae647a2-b486-4675-b7b0-9029ff8d568a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305226023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3305226023
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.1594353950
Short name T134
Test name
Test status
Simulation time 127820398 ps
CPU time 1.15 seconds
Started Jun 06 12:28:36 PM PDT 24
Finished Jun 06 12:28:39 PM PDT 24
Peak memory 200976 kb
Host smart-d93ce152-0848-4062-a37f-36c2b2531a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594353950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.1594353950
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3419286242
Short name T261
Test name
Test status
Simulation time 6056574695 ps
CPU time 24.16 seconds
Started Jun 06 12:28:38 PM PDT 24
Finished Jun 06 12:29:04 PM PDT 24
Peak memory 201108 kb
Host smart-8c0c7e2c-b25f-45e4-a0a9-926dab03eba1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419286242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3419286242
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.2538859433
Short name T220
Test name
Test status
Simulation time 296660261 ps
CPU time 1.9 seconds
Started Jun 06 12:28:35 PM PDT 24
Finished Jun 06 12:28:39 PM PDT 24
Peak memory 208936 kb
Host smart-8ff34286-9ebd-4824-9163-d0266e387b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538859433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2538859433
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3003089099
Short name T159
Test name
Test status
Simulation time 98317810 ps
CPU time 0.83 seconds
Started Jun 06 12:28:36 PM PDT 24
Finished Jun 06 12:28:39 PM PDT 24
Peak memory 200712 kb
Host smart-2921b9d4-0d1d-4e04-88a0-ca3cbd82dcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003089099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3003089099
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1664374603
Short name T403
Test name
Test status
Simulation time 60369551 ps
CPU time 0.8 seconds
Started Jun 06 12:28:43 PM PDT 24
Finished Jun 06 12:28:45 PM PDT 24
Peak memory 200600 kb
Host smart-613e1911-fd7d-42ea-baf9-53ebdce74baa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664374603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1664374603
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1485145366
Short name T32
Test name
Test status
Simulation time 2359306843 ps
CPU time 7.84 seconds
Started Jun 06 12:28:45 PM PDT 24
Finished Jun 06 12:28:55 PM PDT 24
Peak memory 222444 kb
Host smart-a261758d-9025-4e2c-bcdd-27c86e9b525d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485145366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1485145366
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3332353860
Short name T177
Test name
Test status
Simulation time 245864011 ps
CPU time 1.07 seconds
Started Jun 06 12:28:44 PM PDT 24
Finished Jun 06 12:28:47 PM PDT 24
Peak memory 218088 kb
Host smart-f9cf05e8-cf05-4a85-8f4d-07e1788fa205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332353860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3332353860
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.794056445
Short name T153
Test name
Test status
Simulation time 174357509 ps
CPU time 0.83 seconds
Started Jun 06 12:28:45 PM PDT 24
Finished Jun 06 12:28:47 PM PDT 24
Peak memory 200576 kb
Host smart-fdb7acbb-67ba-45a0-92d6-879bee8914b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794056445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.794056445
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.1512573380
Short name T180
Test name
Test status
Simulation time 990333149 ps
CPU time 4.34 seconds
Started Jun 06 12:28:43 PM PDT 24
Finished Jun 06 12:28:48 PM PDT 24
Peak memory 200952 kb
Host smart-7ebc87f9-6fe0-43dc-b78a-ec48aee16e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512573380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1512573380
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1419302743
Short name T4
Test name
Test status
Simulation time 149987243 ps
CPU time 1.1 seconds
Started Jun 06 12:28:42 PM PDT 24
Finished Jun 06 12:28:44 PM PDT 24
Peak memory 200784 kb
Host smart-625adfac-130f-48eb-9c90-f6a5f01f783f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419302743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1419302743
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.4162880592
Short name T266
Test name
Test status
Simulation time 120358763 ps
CPU time 1.12 seconds
Started Jun 06 12:28:46 PM PDT 24
Finished Jun 06 12:28:48 PM PDT 24
Peak memory 200940 kb
Host smart-4156acd0-044b-4b46-a79b-d9611b6639c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162880592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.4162880592
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2839560100
Short name T50
Test name
Test status
Simulation time 9615271009 ps
CPU time 33.67 seconds
Started Jun 06 12:28:46 PM PDT 24
Finished Jun 06 12:29:21 PM PDT 24
Peak memory 201132 kb
Host smart-fd9c6749-8a08-43e9-a7dd-6eb17bf083e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839560100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2839560100
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3164929044
Short name T381
Test name
Test status
Simulation time 433572814 ps
CPU time 2.56 seconds
Started Jun 06 12:28:44 PM PDT 24
Finished Jun 06 12:28:47 PM PDT 24
Peak memory 200608 kb
Host smart-6e68c1d0-273d-4555-8b1d-cee705057072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164929044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3164929044
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2290549999
Short name T77
Test name
Test status
Simulation time 137731391 ps
CPU time 1.23 seconds
Started Jun 06 12:28:46 PM PDT 24
Finished Jun 06 12:28:49 PM PDT 24
Peak memory 200708 kb
Host smart-e37e9137-69db-4f75-974f-aec2cc8f4b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290549999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2290549999
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.391691546
Short name T246
Test name
Test status
Simulation time 124149433 ps
CPU time 0.92 seconds
Started Jun 06 12:28:45 PM PDT 24
Finished Jun 06 12:28:48 PM PDT 24
Peak memory 200640 kb
Host smart-bc13ae76-5a44-43e8-8e54-b57255d2a916
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391691546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.391691546
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2113798596
Short name T507
Test name
Test status
Simulation time 244285436 ps
CPU time 1.16 seconds
Started Jun 06 12:28:43 PM PDT 24
Finished Jun 06 12:28:46 PM PDT 24
Peak memory 218084 kb
Host smart-08c52614-8fa9-4ab2-bc66-74153107da02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113798596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2113798596
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2439800949
Short name T333
Test name
Test status
Simulation time 89316296 ps
CPU time 0.76 seconds
Started Jun 06 12:28:44 PM PDT 24
Finished Jun 06 12:28:46 PM PDT 24
Peak memory 200500 kb
Host smart-58911945-1843-4d0a-a2f4-6d6b9c19cf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439800949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2439800949
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3186565428
Short name T242
Test name
Test status
Simulation time 1284582866 ps
CPU time 5.06 seconds
Started Jun 06 12:28:51 PM PDT 24
Finished Jun 06 12:28:57 PM PDT 24
Peak memory 201024 kb
Host smart-20ecbfbe-4679-42f1-8357-4911adade84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186565428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3186565428
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2174112526
Short name T459
Test name
Test status
Simulation time 170788719 ps
CPU time 1.16 seconds
Started Jun 06 12:28:46 PM PDT 24
Finished Jun 06 12:28:48 PM PDT 24
Peak memory 200804 kb
Host smart-9090af20-b17e-42e2-8649-241da116e8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174112526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2174112526
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1966487638
Short name T26
Test name
Test status
Simulation time 123487277 ps
CPU time 1.17 seconds
Started Jun 06 12:28:44 PM PDT 24
Finished Jun 06 12:28:46 PM PDT 24
Peak memory 200828 kb
Host smart-d8b47a83-569e-47e6-b829-aaef6a639b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966487638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1966487638
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.4211331941
Short name T473
Test name
Test status
Simulation time 10188109087 ps
CPU time 43.09 seconds
Started Jun 06 12:28:48 PM PDT 24
Finished Jun 06 12:29:32 PM PDT 24
Peak memory 210956 kb
Host smart-068eb298-06ea-4696-9609-2d45db22eb06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211331941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.4211331941
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1482037811
Short name T309
Test name
Test status
Simulation time 267411873 ps
CPU time 1.94 seconds
Started Jun 06 12:28:44 PM PDT 24
Finished Jun 06 12:28:47 PM PDT 24
Peak memory 200784 kb
Host smart-76983971-8165-4739-9118-c4ae16f583a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482037811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1482037811
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2752891250
Short name T306
Test name
Test status
Simulation time 103198940 ps
CPU time 0.85 seconds
Started Jun 06 12:28:44 PM PDT 24
Finished Jun 06 12:28:45 PM PDT 24
Peak memory 200808 kb
Host smart-ab061cb0-eaad-4c10-abab-415f7a92160f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752891250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2752891250
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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