Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8495

1

T3

32

T5

14

T6

21

auto[1]

11686

1

T1

4

T3

27

T5

87

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6249	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6768	1			T1	2		T2	1		T3	16
reset_info_cp[2]	3060	1			T1	1		T3	12		T5	18
reset_info_cp[4]	4158	1			T1	1		T3	13		T5	19
reset_info_cp[8]	128	1			T1	1		T6	1		T9	1
reset_info_cp[16]	135	1			T12	3		T22	1		T23	2
reset_info_cp[32]	101	1			T3	1		T6	1		T12	2
reset_info_cp[64]	101	1			T5	1		T9	2		T12	1
reset_info_cp[128]	101	1			T9	1		T22	1		T41	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3167	1			T3	9		T5	14		T6	5
reset_info_cp[1]	auto[1]	2981	1			T1	1		T3	6		T5	12
reset_info_cp[2]	auto[0]	997	1			T3	10		T6	3		T12	11
reset_info_cp[2]	auto[1]	2063	1			T1	1		T3	2		T5	18
reset_info_cp[4]	auto[0]	1459	1			T3	1		T6	4		T12	25
reset_info_cp[4]	auto[1]	2699	1			T1	1		T3	12		T5	19
reset_info_cp[8]	auto[0]	53	1			T12	1		T138	2		T97	1
reset_info_cp[8]	auto[1]	75	1			T1	1		T6	1		T9	1
reset_info_cp[16]	auto[0]	53	1			T12	1		T22	1		T80	1
reset_info_cp[16]	auto[1]	82	1			T12	2		T23	2		T40	1
reset_info_cp[32]	auto[0]	44	1			T3	1		T6	1		T95	1
reset_info_cp[32]	auto[1]	57	1			T12	2		T23	1		T41	1
reset_info_cp[64]	auto[0]	43	1			T12	1		T22	1		T80	1
reset_info_cp[64]	auto[1]	58	1			T5	1		T9	2		T43	1
reset_info_cp[128]	auto[0]	37	1			T22	1		T83	1		T95	1
reset_info_cp[128]	auto[1]	64	1			T9	1		T41	1		T53	1