Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T541 /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2048996624 Jun 07 06:20:49 PM PDT 24 Jun 07 06:20:51 PM PDT 24 194494356 ps
T542 /workspace/coverage/default/4.rstmgr_por_stretcher.3411384391 Jun 07 06:19:31 PM PDT 24 Jun 07 06:19:32 PM PDT 24 110040970 ps
T543 /workspace/coverage/default/22.rstmgr_reset.1303465520 Jun 07 06:20:15 PM PDT 24 Jun 07 06:20:22 PM PDT 24 1715551421 ps
T544 /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2109168501 Jun 07 06:20:38 PM PDT 24 Jun 07 06:20:44 PM PDT 24 1227505953 ps
T545 /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2880827884 Jun 07 06:19:49 PM PDT 24 Jun 07 06:19:57 PM PDT 24 2374932908 ps
T57 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.972713315 Jun 07 06:19:00 PM PDT 24 Jun 07 06:19:02 PM PDT 24 65124257 ps
T58 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3240594246 Jun 07 06:18:49 PM PDT 24 Jun 07 06:18:51 PM PDT 24 198785154 ps
T59 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.4169545613 Jun 07 06:19:02 PM PDT 24 Jun 07 06:19:03 PM PDT 24 85166186 ps
T60 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3898028899 Jun 07 06:19:14 PM PDT 24 Jun 07 06:19:16 PM PDT 24 60652912 ps
T61 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.877927 Jun 07 06:19:03 PM PDT 24 Jun 07 06:19:05 PM PDT 24 189899903 ps
T104 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3997288698 Jun 07 06:19:17 PM PDT 24 Jun 07 06:19:18 PM PDT 24 141196067 ps
T113 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2509376514 Jun 07 06:18:48 PM PDT 24 Jun 07 06:18:50 PM PDT 24 110647315 ps
T105 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3165493595 Jun 07 06:18:59 PM PDT 24 Jun 07 06:19:00 PM PDT 24 64109768 ps
T62 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1258109050 Jun 07 06:19:10 PM PDT 24 Jun 07 06:19:13 PM PDT 24 791670050 ps
T106 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.476791159 Jun 07 06:19:14 PM PDT 24 Jun 07 06:19:16 PM PDT 24 293787576 ps
T63 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.528619036 Jun 07 06:19:20 PM PDT 24 Jun 07 06:19:22 PM PDT 24 171122617 ps
T64 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3971240679 Jun 07 06:19:03 PM PDT 24 Jun 07 06:19:05 PM PDT 24 449164415 ps
T107 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2309515713 Jun 07 06:19:08 PM PDT 24 Jun 07 06:19:10 PM PDT 24 88990971 ps
T87 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2385565584 Jun 07 06:18:55 PM PDT 24 Jun 07 06:18:57 PM PDT 24 195695873 ps
T108 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3332240353 Jun 07 06:19:06 PM PDT 24 Jun 07 06:19:08 PM PDT 24 96492756 ps
T112 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2124631981 Jun 07 06:19:02 PM PDT 24 Jun 07 06:19:04 PM PDT 24 420402535 ps
T88 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1599135591 Jun 07 06:19:00 PM PDT 24 Jun 07 06:19:02 PM PDT 24 108855662 ps
T89 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3756414678 Jun 07 06:19:02 PM PDT 24 Jun 07 06:19:06 PM PDT 24 502198142 ps
T90 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2430198178 Jun 07 06:18:58 PM PDT 24 Jun 07 06:19:01 PM PDT 24 186981472 ps
T93 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.458151833 Jun 07 06:19:16 PM PDT 24 Jun 07 06:19:19 PM PDT 24 793457215 ps
T546 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3188746646 Jun 07 06:19:16 PM PDT 24 Jun 07 06:19:18 PM PDT 24 85736469 ps
T91 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3394668234 Jun 07 06:19:14 PM PDT 24 Jun 07 06:19:15 PM PDT 24 192745296 ps
T92 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1673261552 Jun 07 06:19:17 PM PDT 24 Jun 07 06:19:18 PM PDT 24 132914215 ps
T109 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4148923960 Jun 07 06:18:57 PM PDT 24 Jun 07 06:18:59 PM PDT 24 105152661 ps
T137 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.845799344 Jun 07 06:19:18 PM PDT 24 Jun 07 06:19:21 PM PDT 24 512071249 ps
T125 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2187471095 Jun 07 06:19:17 PM PDT 24 Jun 07 06:19:20 PM PDT 24 121239868 ps
T114 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1821107614 Jun 07 06:19:15 PM PDT 24 Jun 07 06:19:19 PM PDT 24 598205624 ps
T121 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1629633623 Jun 07 06:18:56 PM PDT 24 Jun 07 06:18:58 PM PDT 24 562943513 ps
T115 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3240304497 Jun 07 06:18:55 PM PDT 24 Jun 07 06:18:58 PM PDT 24 166199914 ps
T547 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2151274800 Jun 07 06:18:50 PM PDT 24 Jun 07 06:18:53 PM PDT 24 359904865 ps
T110 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3083955802 Jun 07 06:18:48 PM PDT 24 Jun 07 06:18:50 PM PDT 24 216656250 ps
T548 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3472910741 Jun 07 06:18:47 PM PDT 24 Jun 07 06:18:52 PM PDT 24 816537695 ps
T116 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3117696389 Jun 07 06:19:12 PM PDT 24 Jun 07 06:19:15 PM PDT 24 168707066 ps
T111 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3162674066 Jun 07 06:19:01 PM PDT 24 Jun 07 06:19:03 PM PDT 24 83274282 ps
T549 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3249563798 Jun 07 06:19:16 PM PDT 24 Jun 07 06:19:17 PM PDT 24 200735976 ps
T550 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1867836015 Jun 07 06:19:15 PM PDT 24 Jun 07 06:19:17 PM PDT 24 113777054 ps
T551 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1151159332 Jun 07 06:19:14 PM PDT 24 Jun 07 06:19:17 PM PDT 24 343999419 ps
T135 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2755504951 Jun 07 06:19:18 PM PDT 24 Jun 07 06:19:22 PM PDT 24 961738766 ps
T123 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2683170123 Jun 07 06:18:51 PM PDT 24 Jun 07 06:18:55 PM PDT 24 878669427 ps
T118 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2867174601 Jun 07 06:19:15 PM PDT 24 Jun 07 06:19:19 PM PDT 24 879205358 ps
T552 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3501703519 Jun 07 06:19:06 PM PDT 24 Jun 07 06:19:07 PM PDT 24 126943583 ps
T117 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2367948571 Jun 07 06:19:10 PM PDT 24 Jun 07 06:19:14 PM PDT 24 547374708 ps
T119 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1098044513 Jun 07 06:19:18 PM PDT 24 Jun 07 06:19:22 PM PDT 24 937834955 ps
T124 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2577035082 Jun 07 06:19:09 PM PDT 24 Jun 07 06:19:11 PM PDT 24 489706483 ps
T553 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3757069071 Jun 07 06:19:20 PM PDT 24 Jun 07 06:19:21 PM PDT 24 184707182 ps
T554 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1519319964 Jun 07 06:19:15 PM PDT 24 Jun 07 06:19:17 PM PDT 24 225197242 ps
T555 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1694347182 Jun 07 06:18:57 PM PDT 24 Jun 07 06:18:58 PM PDT 24 60985320 ps
T556 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3893005190 Jun 07 06:19:03 PM PDT 24 Jun 07 06:19:05 PM PDT 24 119539078 ps
T557 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.4150709080 Jun 07 06:18:49 PM PDT 24 Jun 07 06:18:50 PM PDT 24 59988738 ps
T558 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2735827129 Jun 07 06:18:55 PM PDT 24 Jun 07 06:18:58 PM PDT 24 803245338 ps
T559 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1424404499 Jun 07 06:19:11 PM PDT 24 Jun 07 06:19:12 PM PDT 24 76190125 ps
T560 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4199512146 Jun 07 06:18:59 PM PDT 24 Jun 07 06:19:00 PM PDT 24 158874679 ps
T561 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1064546448 Jun 07 06:18:59 PM PDT 24 Jun 07 06:19:00 PM PDT 24 76248323 ps
T562 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1096846270 Jun 07 06:18:52 PM PDT 24 Jun 07 06:18:54 PM PDT 24 88412284 ps
T563 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.438250826 Jun 07 06:19:04 PM PDT 24 Jun 07 06:19:08 PM PDT 24 207777325 ps
T564 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.685650947 Jun 07 06:19:09 PM PDT 24 Jun 07 06:19:11 PM PDT 24 179449622 ps
T565 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2175668396 Jun 07 06:19:01 PM PDT 24 Jun 07 06:19:03 PM PDT 24 133580072 ps
T566 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2355338259 Jun 07 06:19:02 PM PDT 24 Jun 07 06:19:03 PM PDT 24 206164547 ps
T567 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2090335948 Jun 07 06:18:49 PM PDT 24 Jun 07 06:18:50 PM PDT 24 83024644 ps
T568 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3902078006 Jun 07 06:18:45 PM PDT 24 Jun 07 06:18:48 PM PDT 24 497696428 ps
T569 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1397877014 Jun 07 06:19:04 PM PDT 24 Jun 07 06:19:08 PM PDT 24 880796104 ps
T570 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1781482 Jun 07 06:18:49 PM PDT 24 Jun 07 06:18:51 PM PDT 24 75580943 ps
T571 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1957875491 Jun 07 06:18:48 PM PDT 24 Jun 07 06:18:50 PM PDT 24 199412895 ps
T572 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3256888503 Jun 07 06:18:52 PM PDT 24 Jun 07 06:18:53 PM PDT 24 82148761 ps
T573 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1054317551 Jun 07 06:18:50 PM PDT 24 Jun 07 06:18:51 PM PDT 24 77980729 ps
T574 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2880154644 Jun 07 06:18:53 PM PDT 24 Jun 07 06:18:54 PM PDT 24 96707185 ps
T575 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3415275138 Jun 07 06:19:04 PM PDT 24 Jun 07 06:19:07 PM PDT 24 193237508 ps
T576 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3446323687 Jun 07 06:19:15 PM PDT 24 Jun 07 06:19:19 PM PDT 24 482747007 ps
T577 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.4003342316 Jun 07 06:18:59 PM PDT 24 Jun 07 06:19:00 PM PDT 24 97660994 ps
T578 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.666352218 Jun 07 06:18:47 PM PDT 24 Jun 07 06:18:56 PM PDT 24 1522249463 ps
T579 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2911956782 Jun 07 06:19:17 PM PDT 24 Jun 07 06:19:19 PM PDT 24 92692146 ps
T580 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1519828133 Jun 07 06:19:14 PM PDT 24 Jun 07 06:19:15 PM PDT 24 73237381 ps
T581 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.212764368 Jun 07 06:18:44 PM PDT 24 Jun 07 06:18:47 PM PDT 24 163540046 ps
T582 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.664191805 Jun 07 06:18:57 PM PDT 24 Jun 07 06:18:58 PM PDT 24 172156971 ps
T583 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1388568933 Jun 07 06:19:09 PM PDT 24 Jun 07 06:19:11 PM PDT 24 158663665 ps
T136 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3652380201 Jun 07 06:18:51 PM PDT 24 Jun 07 06:18:54 PM PDT 24 935750921 ps
T584 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3326417866 Jun 07 06:18:59 PM PDT 24 Jun 07 06:19:01 PM PDT 24 223998137 ps
T585 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2458787005 Jun 07 06:19:10 PM PDT 24 Jun 07 06:19:13 PM PDT 24 914622883 ps
T586 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4002048639 Jun 07 06:18:57 PM PDT 24 Jun 07 06:18:59 PM PDT 24 248874574 ps
T587 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3989996700 Jun 07 06:18:54 PM PDT 24 Jun 07 06:18:56 PM PDT 24 79022583 ps
T588 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.431142365 Jun 07 06:19:16 PM PDT 24 Jun 07 06:19:19 PM PDT 24 214279919 ps
T589 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4113291059 Jun 07 06:19:10 PM PDT 24 Jun 07 06:19:11 PM PDT 24 148203131 ps
T590 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3872886811 Jun 07 06:18:48 PM PDT 24 Jun 07 06:18:50 PM PDT 24 115038480 ps
T591 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1381231219 Jun 07 06:18:57 PM PDT 24 Jun 07 06:19:00 PM PDT 24 272997062 ps
T592 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2973881716 Jun 07 06:18:51 PM PDT 24 Jun 07 06:18:53 PM PDT 24 195370660 ps
T593 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.735519084 Jun 07 06:18:51 PM PDT 24 Jun 07 06:18:52 PM PDT 24 92231421 ps
T594 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1902483598 Jun 07 06:18:46 PM PDT 24 Jun 07 06:18:48 PM PDT 24 149609010 ps
T595 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3378132200 Jun 07 06:19:01 PM PDT 24 Jun 07 06:19:04 PM PDT 24 493373462 ps
T596 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3960910777 Jun 07 06:18:59 PM PDT 24 Jun 07 06:19:02 PM PDT 24 343908218 ps
T597 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2974228903 Jun 07 06:19:07 PM PDT 24 Jun 07 06:19:09 PM PDT 24 185498952 ps
T598 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1820900753 Jun 07 06:19:18 PM PDT 24 Jun 07 06:19:19 PM PDT 24 181072260 ps
T599 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3380581012 Jun 07 06:19:09 PM PDT 24 Jun 07 06:19:10 PM PDT 24 71913418 ps
T600 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2121761627 Jun 07 06:18:55 PM PDT 24 Jun 07 06:18:56 PM PDT 24 141327763 ps
T601 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1226304616 Jun 07 06:18:48 PM PDT 24 Jun 07 06:18:51 PM PDT 24 468858830 ps
T602 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.195745592 Jun 07 06:19:18 PM PDT 24 Jun 07 06:19:19 PM PDT 24 84901240 ps
T603 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.379397241 Jun 07 06:18:47 PM PDT 24 Jun 07 06:18:49 PM PDT 24 206775092 ps
T604 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1443705967 Jun 07 06:18:50 PM PDT 24 Jun 07 06:18:51 PM PDT 24 133374617 ps
T122 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.346549433 Jun 07 06:19:12 PM PDT 24 Jun 07 06:19:15 PM PDT 24 802581464 ps
T605 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1198733183 Jun 07 06:18:51 PM PDT 24 Jun 07 06:18:56 PM PDT 24 807954348 ps
T606 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.4145627853 Jun 07 06:19:03 PM PDT 24 Jun 07 06:19:05 PM PDT 24 151898073 ps
T607 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1115182195 Jun 07 06:19:03 PM PDT 24 Jun 07 06:19:04 PM PDT 24 173788754 ps
T608 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2003538165 Jun 07 06:19:11 PM PDT 24 Jun 07 06:19:12 PM PDT 24 68702644 ps
T609 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1304328727 Jun 07 06:19:08 PM PDT 24 Jun 07 06:19:10 PM PDT 24 128237331 ps
T610 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2164078983 Jun 07 06:19:00 PM PDT 24 Jun 07 06:19:02 PM PDT 24 94403766 ps
T611 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2797652083 Jun 07 06:18:59 PM PDT 24 Jun 07 06:19:01 PM PDT 24 165703401 ps
T612 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.4171041414 Jun 07 06:19:17 PM PDT 24 Jun 07 06:19:18 PM PDT 24 88693214 ps
T613 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1708704615 Jun 07 06:18:54 PM PDT 24 Jun 07 06:18:55 PM PDT 24 66945863 ps
T614 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3277683926 Jun 07 06:19:05 PM PDT 24 Jun 07 06:19:06 PM PDT 24 62904922 ps
T120 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2203285138 Jun 07 06:18:56 PM PDT 24 Jun 07 06:18:59 PM PDT 24 968961137 ps
T615 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2514899565 Jun 07 06:19:11 PM PDT 24 Jun 07 06:19:13 PM PDT 24 130454688 ps
T616 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.135182997 Jun 07 06:18:47 PM PDT 24 Jun 07 06:18:49 PM PDT 24 163830129 ps
T617 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1503452965 Jun 07 06:19:02 PM PDT 24 Jun 07 06:19:03 PM PDT 24 80540248 ps
T618 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1736914679 Jun 07 06:18:54 PM PDT 24 Jun 07 06:19:02 PM PDT 24 1542258230 ps
T619 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2757110203 Jun 07 06:18:49 PM PDT 24 Jun 07 06:18:51 PM PDT 24 194081775 ps
T620 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3390490827 Jun 07 06:19:11 PM PDT 24 Jun 07 06:19:14 PM PDT 24 165869959 ps

Test location /workspace/coverage/default/35.rstmgr_smoke.1840412001
Short name T10
Test name
Test status
Simulation time 257448891 ps
CPU time 1.46 seconds
Started Jun 07 06:20:29 PM PDT 24
Finished Jun 07 06:20:31 PM PDT 24
Peak memory 200560 kb
Host smart-101b9f9f-ff3b-4f2d-94ee-3212283a2ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840412001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1840412001
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.891686760
Short name T12
Test name
Test status
Simulation time 8047461687 ps
CPU time 27.14 seconds
Started Jun 07 06:19:40 PM PDT 24
Finished Jun 07 06:20:07 PM PDT 24
Peak memory 208904 kb
Host smart-84b09725-9e47-4512-a560-0fd4a4201390
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891686760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.891686760
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1258109050
Short name T62
Test name
Test status
Simulation time 791670050 ps
CPU time 3 seconds
Started Jun 07 06:19:10 PM PDT 24
Finished Jun 07 06:19:13 PM PDT 24
Peak memory 200644 kb
Host smart-add71a24-a554-4a50-a09f-a2300c4f32fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258109050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1258109050
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.494913785
Short name T65
Test name
Test status
Simulation time 16508242247 ps
CPU time 28.29 seconds
Started Jun 07 06:19:21 PM PDT 24
Finished Jun 07 06:19:50 PM PDT 24
Peak memory 217756 kb
Host smart-4547f9b2-2c25-449a-b1fe-825aab3d40ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494913785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.494913785
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2945817733
Short name T9
Test name
Test status
Simulation time 2366584353 ps
CPU time 7.95 seconds
Started Jun 07 06:19:27 PM PDT 24
Finished Jun 07 06:19:35 PM PDT 24
Peak memory 218096 kb
Host smart-cad46eae-f6c4-4b96-a44e-ccdf1f40d34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945817733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2945817733
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.2209012834
Short name T37
Test name
Test status
Simulation time 118282441 ps
CPU time 1.44 seconds
Started Jun 07 06:20:31 PM PDT 24
Finished Jun 07 06:20:33 PM PDT 24
Peak memory 200368 kb
Host smart-bad4dd41-8ee3-4755-b4d7-bc17cb451e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209012834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2209012834
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2430198178
Short name T90
Test name
Test status
Simulation time 186981472 ps
CPU time 2.76 seconds
Started Jun 07 06:18:58 PM PDT 24
Finished Jun 07 06:19:01 PM PDT 24
Peak memory 208680 kb
Host smart-1bd51d8c-e2fc-4df5-923d-931d82191cb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430198178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2430198178
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1768585906
Short name T48
Test name
Test status
Simulation time 58198227 ps
CPU time 0.75 seconds
Started Jun 07 06:19:45 PM PDT 24
Finished Jun 07 06:19:46 PM PDT 24
Peak memory 200172 kb
Host smart-86fa8c5c-e925-4f5c-bb60-71272cdc2216
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768585906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1768585906
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2662210262
Short name T153
Test name
Test status
Simulation time 110234609 ps
CPU time 1.09 seconds
Started Jun 07 06:19:17 PM PDT 24
Finished Jun 07 06:19:19 PM PDT 24
Peak memory 200272 kb
Host smart-418e2047-6a55-46bc-92cc-647cee2c2331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662210262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2662210262
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.4053638890
Short name T97
Test name
Test status
Simulation time 7563468134 ps
CPU time 27.4 seconds
Started Jun 07 06:20:32 PM PDT 24
Finished Jun 07 06:21:00 PM PDT 24
Peak memory 200648 kb
Host smart-3322f0aa-8baf-436b-b6be-5de9a5f19786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053638890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.4053638890
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.1106298061
Short name T29
Test name
Test status
Simulation time 1224989039 ps
CPU time 5.72 seconds
Started Jun 07 06:19:49 PM PDT 24
Finished Jun 07 06:19:56 PM PDT 24
Peak memory 218008 kb
Host smart-f2f197d6-9df3-4e9a-9eb2-0c68edbc6226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106298061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1106298061
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3652380201
Short name T136
Test name
Test status
Simulation time 935750921 ps
CPU time 3 seconds
Started Jun 07 06:18:51 PM PDT 24
Finished Jun 07 06:18:54 PM PDT 24
Peak memory 199020 kb
Host smart-58d4e207-d4b3-4606-b5b6-c6ee7b3629ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652380201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3652380201
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3117696389
Short name T116
Test name
Test status
Simulation time 168707066 ps
CPU time 2.54 seconds
Started Jun 07 06:19:12 PM PDT 24
Finished Jun 07 06:19:15 PM PDT 24
Peak memory 208588 kb
Host smart-fe3e9e0e-d872-4839-a65a-0792c71d70b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117696389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3117696389
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1194193523
Short name T23
Test name
Test status
Simulation time 2165583421 ps
CPU time 7.58 seconds
Started Jun 07 06:20:08 PM PDT 24
Finished Jun 07 06:20:16 PM PDT 24
Peak memory 218064 kb
Host smart-e0d50a58-8f77-4c1b-b1ad-f052e08461a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194193523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1194193523
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.84284027
Short name T71
Test name
Test status
Simulation time 87232818 ps
CPU time 0.83 seconds
Started Jun 07 06:19:41 PM PDT 24
Finished Jun 07 06:19:43 PM PDT 24
Peak memory 200324 kb
Host smart-49395ee8-4a63-4398-bb28-a1f070243ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84284027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.84284027
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3083955802
Short name T110
Test name
Test status
Simulation time 216656250 ps
CPU time 1.49 seconds
Started Jun 07 06:18:48 PM PDT 24
Finished Jun 07 06:18:50 PM PDT 24
Peak memory 200448 kb
Host smart-b420d9fa-45fc-48fd-8998-f63346804fff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083955802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3083955802
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3852098066
Short name T19
Test name
Test status
Simulation time 227148374 ps
CPU time 0.93 seconds
Started Jun 07 06:19:16 PM PDT 24
Finished Jun 07 06:19:17 PM PDT 24
Peak memory 200140 kb
Host smart-44eff152-840d-4ee7-be17-ba51a1ff2717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852098066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3852098066
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3732772135
Short name T53
Test name
Test status
Simulation time 1229293359 ps
CPU time 5.46 seconds
Started Jun 07 06:19:50 PM PDT 24
Finished Jun 07 06:19:56 PM PDT 24
Peak memory 221912 kb
Host smart-8093c8d7-c04e-42fc-81cd-5076e481bba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732772135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3732772135
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3378132200
Short name T595
Test name
Test status
Simulation time 493373462 ps
CPU time 1.92 seconds
Started Jun 07 06:19:01 PM PDT 24
Finished Jun 07 06:19:04 PM PDT 24
Peak memory 200612 kb
Host smart-45d25e4e-b829-4d96-bf27-6dd3439fe1c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378132200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3378132200
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.346549433
Short name T122
Test name
Test status
Simulation time 802581464 ps
CPU time 2.76 seconds
Started Jun 07 06:19:12 PM PDT 24
Finished Jun 07 06:19:15 PM PDT 24
Peak memory 200532 kb
Host smart-46fb308b-6b0f-45e0-a0cb-7b5b68b395c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346549433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.346549433
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1098044513
Short name T119
Test name
Test status
Simulation time 937834955 ps
CPU time 3.54 seconds
Started Jun 07 06:19:18 PM PDT 24
Finished Jun 07 06:19:22 PM PDT 24
Peak memory 200484 kb
Host smart-5010ef1d-383b-4521-bf2a-67295f75ab81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098044513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1098044513
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2203285138
Short name T120
Test name
Test status
Simulation time 968961137 ps
CPU time 3.47 seconds
Started Jun 07 06:18:56 PM PDT 24
Finished Jun 07 06:18:59 PM PDT 24
Peak memory 200388 kb
Host smart-25807fe1-1ff2-4a43-b524-68c7236ca2b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203285138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.2203285138
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2151274800
Short name T547
Test name
Test status
Simulation time 359904865 ps
CPU time 2.44 seconds
Started Jun 07 06:18:50 PM PDT 24
Finished Jun 07 06:18:53 PM PDT 24
Peak memory 200536 kb
Host smart-088cc991-c5f1-481d-946a-4f657c57ee2b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151274800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
151274800
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1198733183
Short name T605
Test name
Test status
Simulation time 807954348 ps
CPU time 4.35 seconds
Started Jun 07 06:18:51 PM PDT 24
Finished Jun 07 06:18:56 PM PDT 24
Peak memory 199072 kb
Host smart-0ef6005f-b067-4693-8b20-a7e4f48fdf09
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198733183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
198733183
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1443705967
Short name T604
Test name
Test status
Simulation time 133374617 ps
CPU time 0.94 seconds
Started Jun 07 06:18:50 PM PDT 24
Finished Jun 07 06:18:51 PM PDT 24
Peak memory 200272 kb
Host smart-457da1fc-4c9c-46f4-b57a-5719b0a822fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443705967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
443705967
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.135182997
Short name T616
Test name
Test status
Simulation time 163830129 ps
CPU time 1.58 seconds
Started Jun 07 06:18:47 PM PDT 24
Finished Jun 07 06:18:49 PM PDT 24
Peak memory 208748 kb
Host smart-9cbb4332-203e-4a17-aaf2-28aded6f6ff3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135182997 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.135182997
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2090335948
Short name T567
Test name
Test status
Simulation time 83024644 ps
CPU time 0.88 seconds
Started Jun 07 06:18:49 PM PDT 24
Finished Jun 07 06:18:50 PM PDT 24
Peak memory 200156 kb
Host smart-0a864dde-78da-4079-b547-ba2e6c54ec9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090335948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2090335948
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.212764368
Short name T581
Test name
Test status
Simulation time 163540046 ps
CPU time 2.15 seconds
Started Jun 07 06:18:44 PM PDT 24
Finished Jun 07 06:18:47 PM PDT 24
Peak memory 208656 kb
Host smart-4243e613-5359-4d6d-9387-7a591644bed8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212764368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.212764368
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1226304616
Short name T601
Test name
Test status
Simulation time 468858830 ps
CPU time 2.21 seconds
Started Jun 07 06:18:48 PM PDT 24
Finished Jun 07 06:18:51 PM PDT 24
Peak memory 200412 kb
Host smart-1f93e329-6122-40d5-86fe-2caacf35bc4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226304616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1226304616
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3872886811
Short name T590
Test name
Test status
Simulation time 115038480 ps
CPU time 1.33 seconds
Started Jun 07 06:18:48 PM PDT 24
Finished Jun 07 06:18:50 PM PDT 24
Peak memory 200344 kb
Host smart-1f2a7111-93a3-4944-b448-ce54e4e48ea1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872886811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
872886811
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.666352218
Short name T578
Test name
Test status
Simulation time 1522249463 ps
CPU time 7.95 seconds
Started Jun 07 06:18:47 PM PDT 24
Finished Jun 07 06:18:56 PM PDT 24
Peak memory 200328 kb
Host smart-59a0c766-f20c-4427-b9f5-2a3219d6aad6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666352218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.666352218
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2509376514
Short name T113
Test name
Test status
Simulation time 110647315 ps
CPU time 0.85 seconds
Started Jun 07 06:18:48 PM PDT 24
Finished Jun 07 06:18:50 PM PDT 24
Peak memory 200260 kb
Host smart-33e8c676-e843-472e-8af2-163d2c2a0469
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509376514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
509376514
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3240594246
Short name T58
Test name
Test status
Simulation time 198785154 ps
CPU time 1.4 seconds
Started Jun 07 06:18:49 PM PDT 24
Finished Jun 07 06:18:51 PM PDT 24
Peak memory 208332 kb
Host smart-2b6d8cf0-a352-4e32-995a-5ae259c48374
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240594246 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3240594246
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3256888503
Short name T572
Test name
Test status
Simulation time 82148761 ps
CPU time 0.83 seconds
Started Jun 07 06:18:52 PM PDT 24
Finished Jun 07 06:18:53 PM PDT 24
Peak memory 199900 kb
Host smart-6eb0f726-53d2-408d-8037-be53018d25df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256888503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3256888503
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1781482
Short name T570
Test name
Test status
Simulation time 75580943 ps
CPU time 0.95 seconds
Started Jun 07 06:18:49 PM PDT 24
Finished Jun 07 06:18:51 PM PDT 24
Peak memory 200164 kb
Host smart-5e9da1df-6579-48ed-a4d6-bcb528a0892a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_same_
csr_outstanding.1781482
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2757110203
Short name T619
Test name
Test status
Simulation time 194081775 ps
CPU time 1.66 seconds
Started Jun 07 06:18:49 PM PDT 24
Finished Jun 07 06:18:51 PM PDT 24
Peak memory 216576 kb
Host smart-32c5499a-4b9f-41e7-be9f-b6c03d868ad4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757110203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2757110203
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3902078006
Short name T568
Test name
Test status
Simulation time 497696428 ps
CPU time 2.04 seconds
Started Jun 07 06:18:45 PM PDT 24
Finished Jun 07 06:18:48 PM PDT 24
Peak memory 200496 kb
Host smart-dfd63946-0ad2-4ca5-9e1a-93b0198b6221
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902078006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3902078006
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1388568933
Short name T583
Test name
Test status
Simulation time 158663665 ps
CPU time 1.38 seconds
Started Jun 07 06:19:09 PM PDT 24
Finished Jun 07 06:19:11 PM PDT 24
Peak memory 208480 kb
Host smart-7a420c3e-d30b-4d73-9282-4754078d04ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388568933 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1388568933
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.972713315
Short name T57
Test name
Test status
Simulation time 65124257 ps
CPU time 0.85 seconds
Started Jun 07 06:19:00 PM PDT 24
Finished Jun 07 06:19:02 PM PDT 24
Peak memory 200152 kb
Host smart-98ab5546-8d90-435d-a243-87fb27294995
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972713315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.972713315
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.4145627853
Short name T606
Test name
Test status
Simulation time 151898073 ps
CPU time 1.17 seconds
Started Jun 07 06:19:03 PM PDT 24
Finished Jun 07 06:19:05 PM PDT 24
Peak memory 200284 kb
Host smart-dd62c995-4cd8-454c-b4ec-11050429eb00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145627853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.4145627853
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.438250826
Short name T563
Test name
Test status
Simulation time 207777325 ps
CPU time 3.07 seconds
Started Jun 07 06:19:04 PM PDT 24
Finished Jun 07 06:19:08 PM PDT 24
Peak memory 208708 kb
Host smart-fd99bd7e-b18e-4664-b29a-1540c27d0127
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438250826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.438250826
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1304328727
Short name T609
Test name
Test status
Simulation time 128237331 ps
CPU time 0.97 seconds
Started Jun 07 06:19:08 PM PDT 24
Finished Jun 07 06:19:10 PM PDT 24
Peak memory 200376 kb
Host smart-516cf1e1-11e7-465d-a36a-eea68d8719a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304328727 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.1304328727
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1424404499
Short name T559
Test name
Test status
Simulation time 76190125 ps
CPU time 0.8 seconds
Started Jun 07 06:19:11 PM PDT 24
Finished Jun 07 06:19:12 PM PDT 24
Peak memory 200172 kb
Host smart-53d654e1-8c3f-4a57-898c-62656051d477
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424404499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1424404499
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3501703519
Short name T552
Test name
Test status
Simulation time 126943583 ps
CPU time 1.1 seconds
Started Jun 07 06:19:06 PM PDT 24
Finished Jun 07 06:19:07 PM PDT 24
Peak memory 200216 kb
Host smart-a1f5789b-7e1b-4dab-8fb0-60ad58702467
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501703519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.3501703519
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2514899565
Short name T615
Test name
Test status
Simulation time 130454688 ps
CPU time 1.78 seconds
Started Jun 07 06:19:11 PM PDT 24
Finished Jun 07 06:19:13 PM PDT 24
Peak memory 208676 kb
Host smart-11e50969-043a-4d3f-ad9f-062c76238c11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514899565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2514899565
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2974228903
Short name T597
Test name
Test status
Simulation time 185498952 ps
CPU time 1.23 seconds
Started Jun 07 06:19:07 PM PDT 24
Finished Jun 07 06:19:09 PM PDT 24
Peak memory 200120 kb
Host smart-8f5a4b27-3112-4a20-aa30-c873efca5938
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974228903 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2974228903
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2003538165
Short name T608
Test name
Test status
Simulation time 68702644 ps
CPU time 0.84 seconds
Started Jun 07 06:19:11 PM PDT 24
Finished Jun 07 06:19:12 PM PDT 24
Peak memory 200160 kb
Host smart-32ab4de5-9b0f-424e-a98b-4df476c5e2d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003538165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2003538165
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4113291059
Short name T589
Test name
Test status
Simulation time 148203131 ps
CPU time 1.17 seconds
Started Jun 07 06:19:10 PM PDT 24
Finished Jun 07 06:19:11 PM PDT 24
Peak memory 200188 kb
Host smart-e4682b13-ad95-472c-8d98-13858ec284c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113291059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.4113291059
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2367948571
Short name T117
Test name
Test status
Simulation time 547374708 ps
CPU time 3.38 seconds
Started Jun 07 06:19:10 PM PDT 24
Finished Jun 07 06:19:14 PM PDT 24
Peak memory 208652 kb
Host smart-e269c80f-e6c4-4d1d-9423-633363e1b525
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367948571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2367948571
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2458787005
Short name T585
Test name
Test status
Simulation time 914622883 ps
CPU time 2.96 seconds
Started Jun 07 06:19:10 PM PDT 24
Finished Jun 07 06:19:13 PM PDT 24
Peak memory 200540 kb
Host smart-cdcc6e9b-b00f-4a29-a2d6-ba2544e281df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458787005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.2458787005
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3390490827
Short name T620
Test name
Test status
Simulation time 165869959 ps
CPU time 1.58 seconds
Started Jun 07 06:19:11 PM PDT 24
Finished Jun 07 06:19:14 PM PDT 24
Peak memory 208716 kb
Host smart-6127fa15-b399-4590-b52d-c86088aadad2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390490827 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3390490827
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3277683926
Short name T614
Test name
Test status
Simulation time 62904922 ps
CPU time 0.77 seconds
Started Jun 07 06:19:05 PM PDT 24
Finished Jun 07 06:19:06 PM PDT 24
Peak memory 200144 kb
Host smart-0aa13ccd-7b08-4e43-8cf6-065b92f868cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277683926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3277683926
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3332240353
Short name T108
Test name
Test status
Simulation time 96492756 ps
CPU time 1.13 seconds
Started Jun 07 06:19:06 PM PDT 24
Finished Jun 07 06:19:08 PM PDT 24
Peak memory 200548 kb
Host smart-f57c9ecb-8309-40d2-83a2-740ebea1c9d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332240353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.3332240353
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.685650947
Short name T564
Test name
Test status
Simulation time 179449622 ps
CPU time 2.26 seconds
Started Jun 07 06:19:09 PM PDT 24
Finished Jun 07 06:19:11 PM PDT 24
Peak memory 208732 kb
Host smart-689d3495-9d31-4872-8536-caeea58d2394
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685650947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.685650947
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2577035082
Short name T124
Test name
Test status
Simulation time 489706483 ps
CPU time 1.89 seconds
Started Jun 07 06:19:09 PM PDT 24
Finished Jun 07 06:19:11 PM PDT 24
Peak memory 200504 kb
Host smart-02c5e156-6348-43ce-9718-207ec46bbaa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577035082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.2577035082
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1673261552
Short name T92
Test name
Test status
Simulation time 132914215 ps
CPU time 1.02 seconds
Started Jun 07 06:19:17 PM PDT 24
Finished Jun 07 06:19:18 PM PDT 24
Peak memory 200296 kb
Host smart-55b037df-5fcf-4979-a177-2a8d451c6a99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673261552 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.1673261552
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3380581012
Short name T599
Test name
Test status
Simulation time 71913418 ps
CPU time 0.78 seconds
Started Jun 07 06:19:09 PM PDT 24
Finished Jun 07 06:19:10 PM PDT 24
Peak memory 200124 kb
Host smart-1138fd49-8ab7-41af-bd40-33954622b449
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380581012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3380581012
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2309515713
Short name T107
Test name
Test status
Simulation time 88990971 ps
CPU time 1.02 seconds
Started Jun 07 06:19:08 PM PDT 24
Finished Jun 07 06:19:10 PM PDT 24
Peak memory 200180 kb
Host smart-ba9a13e4-8dd5-4d31-834a-01a856eefa57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309515713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2309515713
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3757069071
Short name T553
Test name
Test status
Simulation time 184707182 ps
CPU time 1.15 seconds
Started Jun 07 06:19:20 PM PDT 24
Finished Jun 07 06:19:21 PM PDT 24
Peak memory 200240 kb
Host smart-bbba0736-c623-486d-8f3c-2f42fe7547c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757069071 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3757069071
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2911956782
Short name T579
Test name
Test status
Simulation time 92692146 ps
CPU time 0.85 seconds
Started Jun 07 06:19:17 PM PDT 24
Finished Jun 07 06:19:19 PM PDT 24
Peak memory 200220 kb
Host smart-3f3fa921-863f-48e8-8700-c27ddfd5e4e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911956782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2911956782
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.476791159
Short name T106
Test name
Test status
Simulation time 293787576 ps
CPU time 1.66 seconds
Started Jun 07 06:19:14 PM PDT 24
Finished Jun 07 06:19:16 PM PDT 24
Peak memory 200416 kb
Host smart-4e6a92ff-7610-4a80-82e0-0b5b9917e338
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476791159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.476791159
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3446323687
Short name T576
Test name
Test status
Simulation time 482747007 ps
CPU time 3.11 seconds
Started Jun 07 06:19:15 PM PDT 24
Finished Jun 07 06:19:19 PM PDT 24
Peak memory 208596 kb
Host smart-7b3f5395-dbc3-40f2-9fac-369dcc5d07ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446323687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3446323687
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.458151833
Short name T93
Test name
Test status
Simulation time 793457215 ps
CPU time 2.84 seconds
Started Jun 07 06:19:16 PM PDT 24
Finished Jun 07 06:19:19 PM PDT 24
Peak memory 200488 kb
Host smart-4f7e58cf-0f71-499e-ae07-aa25ee6b2515
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458151833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err
.458151833
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1867836015
Short name T550
Test name
Test status
Simulation time 113777054 ps
CPU time 1.15 seconds
Started Jun 07 06:19:15 PM PDT 24
Finished Jun 07 06:19:17 PM PDT 24
Peak memory 200356 kb
Host smart-b8f79215-1b6a-4cbf-b67f-0ae903fabad2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867836015 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.1867836015
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3898028899
Short name T60
Test name
Test status
Simulation time 60652912 ps
CPU time 0.79 seconds
Started Jun 07 06:19:14 PM PDT 24
Finished Jun 07 06:19:16 PM PDT 24
Peak memory 200228 kb
Host smart-162c3d5f-9eb8-4ef9-b724-b99c1ba72c1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898028899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3898028899
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1519319964
Short name T554
Test name
Test status
Simulation time 225197242 ps
CPU time 1.5 seconds
Started Jun 07 06:19:15 PM PDT 24
Finished Jun 07 06:19:17 PM PDT 24
Peak memory 200376 kb
Host smart-13b92d99-db58-49b1-b4d6-41c6bf847b27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519319964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1519319964
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2187471095
Short name T125
Test name
Test status
Simulation time 121239868 ps
CPU time 1.59 seconds
Started Jun 07 06:19:17 PM PDT 24
Finished Jun 07 06:19:20 PM PDT 24
Peak memory 208648 kb
Host smart-5db10853-d565-42af-a2e6-b5d5c7e7e990
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187471095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2187471095
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1820900753
Short name T598
Test name
Test status
Simulation time 181072260 ps
CPU time 1.19 seconds
Started Jun 07 06:19:18 PM PDT 24
Finished Jun 07 06:19:19 PM PDT 24
Peak memory 200336 kb
Host smart-20095d9d-0035-49ea-a6d6-e7f54ffe3617
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820900753 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.1820900753
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.195745592
Short name T602
Test name
Test status
Simulation time 84901240 ps
CPU time 0.91 seconds
Started Jun 07 06:19:18 PM PDT 24
Finished Jun 07 06:19:19 PM PDT 24
Peak memory 200228 kb
Host smart-2cfe901f-b80b-4a3d-9bf5-e63b370c9d21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195745592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.195745592
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3997288698
Short name T104
Test name
Test status
Simulation time 141196067 ps
CPU time 1.15 seconds
Started Jun 07 06:19:17 PM PDT 24
Finished Jun 07 06:19:18 PM PDT 24
Peak memory 200244 kb
Host smart-9f1b5813-417e-4256-bd55-e4c63770b2fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997288698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.3997288698
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.431142365
Short name T588
Test name
Test status
Simulation time 214279919 ps
CPU time 3.04 seconds
Started Jun 07 06:19:16 PM PDT 24
Finished Jun 07 06:19:19 PM PDT 24
Peak memory 208684 kb
Host smart-c2dce144-431a-4398-9c12-1754b53d6c6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431142365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.431142365
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2867174601
Short name T118
Test name
Test status
Simulation time 879205358 ps
CPU time 3.23 seconds
Started Jun 07 06:19:15 PM PDT 24
Finished Jun 07 06:19:19 PM PDT 24
Peak memory 200584 kb
Host smart-2c97fb22-d9c5-414d-a57b-15a6648d3439
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867174601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2867174601
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3394668234
Short name T91
Test name
Test status
Simulation time 192745296 ps
CPU time 1.3 seconds
Started Jun 07 06:19:14 PM PDT 24
Finished Jun 07 06:19:15 PM PDT 24
Peak memory 208540 kb
Host smart-a607f9e5-0aad-49be-820e-659826e862eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394668234 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3394668234
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1519828133
Short name T580
Test name
Test status
Simulation time 73237381 ps
CPU time 0.78 seconds
Started Jun 07 06:19:14 PM PDT 24
Finished Jun 07 06:19:15 PM PDT 24
Peak memory 200180 kb
Host smart-98ded458-208e-48d5-9c11-0ecb6312efbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519828133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1519828133
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.4171041414
Short name T612
Test name
Test status
Simulation time 88693214 ps
CPU time 1.03 seconds
Started Jun 07 06:19:17 PM PDT 24
Finished Jun 07 06:19:18 PM PDT 24
Peak memory 200268 kb
Host smart-c653db41-ff72-4135-affe-b67e88184742
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171041414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.4171041414
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1151159332
Short name T551
Test name
Test status
Simulation time 343999419 ps
CPU time 2.39 seconds
Started Jun 07 06:19:14 PM PDT 24
Finished Jun 07 06:19:17 PM PDT 24
Peak memory 211464 kb
Host smart-646b1968-3de4-4dcb-a2dc-a1842f762e29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151159332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1151159332
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.845799344
Short name T137
Test name
Test status
Simulation time 512071249 ps
CPU time 1.98 seconds
Started Jun 07 06:19:18 PM PDT 24
Finished Jun 07 06:19:21 PM PDT 24
Peak memory 200476 kb
Host smart-2e34de9a-d7c5-40cf-a8fd-9394a39b27dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845799344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err
.845799344
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.528619036
Short name T63
Test name
Test status
Simulation time 171122617 ps
CPU time 1.14 seconds
Started Jun 07 06:19:20 PM PDT 24
Finished Jun 07 06:19:22 PM PDT 24
Peak memory 200244 kb
Host smart-6c381a61-a0bf-4913-b1bf-0a10a5c6cdef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528619036 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.528619036
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3188746646
Short name T546
Test name
Test status
Simulation time 85736469 ps
CPU time 0.92 seconds
Started Jun 07 06:19:16 PM PDT 24
Finished Jun 07 06:19:18 PM PDT 24
Peak memory 200208 kb
Host smart-b6987fb8-25a9-4af7-af46-c7f7e78bd73f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188746646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3188746646
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3249563798
Short name T549
Test name
Test status
Simulation time 200735976 ps
CPU time 1.43 seconds
Started Jun 07 06:19:16 PM PDT 24
Finished Jun 07 06:19:17 PM PDT 24
Peak memory 200336 kb
Host smart-a11ca548-9a4a-46e1-a473-2348d6bd9c87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249563798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3249563798
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1821107614
Short name T114
Test name
Test status
Simulation time 598205624 ps
CPU time 3.69 seconds
Started Jun 07 06:19:15 PM PDT 24
Finished Jun 07 06:19:19 PM PDT 24
Peak memory 208620 kb
Host smart-063be5e3-aae5-4cb7-86b8-c1de39a08685
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821107614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1821107614
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2755504951
Short name T135
Test name
Test status
Simulation time 961738766 ps
CPU time 3.18 seconds
Started Jun 07 06:19:18 PM PDT 24
Finished Jun 07 06:19:22 PM PDT 24
Peak memory 200480 kb
Host smart-61fa9596-0b3a-4d6b-9e32-64d8a81504e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755504951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2755504951
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1902483598
Short name T594
Test name
Test status
Simulation time 149609010 ps
CPU time 1.99 seconds
Started Jun 07 06:18:46 PM PDT 24
Finished Jun 07 06:18:48 PM PDT 24
Peak memory 200456 kb
Host smart-2487b903-7a38-4103-a729-f59b87c3f683
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902483598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1
902483598
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3472910741
Short name T548
Test name
Test status
Simulation time 816537695 ps
CPU time 4.7 seconds
Started Jun 07 06:18:47 PM PDT 24
Finished Jun 07 06:18:52 PM PDT 24
Peak memory 200496 kb
Host smart-255195ef-fe7d-452b-b1e2-3482285a18b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472910741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
472910741
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2880154644
Short name T574
Test name
Test status
Simulation time 96707185 ps
CPU time 0.87 seconds
Started Jun 07 06:18:53 PM PDT 24
Finished Jun 07 06:18:54 PM PDT 24
Peak memory 200204 kb
Host smart-0775ec0b-aa2d-4ae6-a2ef-0440866ed634
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880154644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
880154644
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2973881716
Short name T592
Test name
Test status
Simulation time 195370660 ps
CPU time 1.19 seconds
Started Jun 07 06:18:51 PM PDT 24
Finished Jun 07 06:18:53 PM PDT 24
Peak memory 207188 kb
Host smart-08ed2afe-1d74-43aa-a9d2-1c53c1b981b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973881716 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2973881716
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.4150709080
Short name T557
Test name
Test status
Simulation time 59988738 ps
CPU time 0.75 seconds
Started Jun 07 06:18:49 PM PDT 24
Finished Jun 07 06:18:50 PM PDT 24
Peak memory 200224 kb
Host smart-7425c97d-0771-4ea3-8343-a011513eaf77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150709080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.4150709080
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1054317551
Short name T573
Test name
Test status
Simulation time 77980729 ps
CPU time 0.92 seconds
Started Jun 07 06:18:50 PM PDT 24
Finished Jun 07 06:18:51 PM PDT 24
Peak memory 200260 kb
Host smart-767f2745-e7a0-4ebb-8462-27421a837b56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054317551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1054317551
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.379397241
Short name T603
Test name
Test status
Simulation time 206775092 ps
CPU time 1.86 seconds
Started Jun 07 06:18:47 PM PDT 24
Finished Jun 07 06:18:49 PM PDT 24
Peak memory 216824 kb
Host smart-a4af8380-934f-40bc-b6b2-10104a833bd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379397241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.379397241
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2683170123
Short name T123
Test name
Test status
Simulation time 878669427 ps
CPU time 2.98 seconds
Started Jun 07 06:18:51 PM PDT 24
Finished Jun 07 06:18:55 PM PDT 24
Peak memory 200016 kb
Host smart-63ba30ae-b5ce-4f7c-a728-4d8db1b51032
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683170123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.2683170123
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4002048639
Short name T586
Test name
Test status
Simulation time 248874574 ps
CPU time 1.68 seconds
Started Jun 07 06:18:57 PM PDT 24
Finished Jun 07 06:18:59 PM PDT 24
Peak memory 200548 kb
Host smart-b9d78fee-0b7c-4ac9-808e-ad221f2a8dd9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002048639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.4
002048639
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1736914679
Short name T618
Test name
Test status
Simulation time 1542258230 ps
CPU time 8.24 seconds
Started Jun 07 06:18:54 PM PDT 24
Finished Jun 07 06:19:02 PM PDT 24
Peak memory 200360 kb
Host smart-a7518b97-d477-433f-a925-38c65f77600a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736914679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
736914679
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.735519084
Short name T593
Test name
Test status
Simulation time 92231421 ps
CPU time 0.82 seconds
Started Jun 07 06:18:51 PM PDT 24
Finished Jun 07 06:18:52 PM PDT 24
Peak memory 200208 kb
Host smart-bc86756e-5deb-45ae-964e-a8149f8e9a42
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735519084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.735519084
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2385565584
Short name T87
Test name
Test status
Simulation time 195695873 ps
CPU time 1.47 seconds
Started Jun 07 06:18:55 PM PDT 24
Finished Jun 07 06:18:57 PM PDT 24
Peak memory 208532 kb
Host smart-5751632f-b8b7-4eb5-bcb9-de75cc4bc768
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385565584 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2385565584
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1694347182
Short name T555
Test name
Test status
Simulation time 60985320 ps
CPU time 0.75 seconds
Started Jun 07 06:18:57 PM PDT 24
Finished Jun 07 06:18:58 PM PDT 24
Peak memory 200132 kb
Host smart-4108518f-77f9-4a32-91dc-8669292fb570
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694347182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1694347182
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2121761627
Short name T600
Test name
Test status
Simulation time 141327763 ps
CPU time 1.27 seconds
Started Jun 07 06:18:55 PM PDT 24
Finished Jun 07 06:18:56 PM PDT 24
Peak memory 200484 kb
Host smart-9f204a88-12fb-438b-81d7-15cd7469bf58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121761627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2121761627
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1957875491
Short name T571
Test name
Test status
Simulation time 199412895 ps
CPU time 1.52 seconds
Started Jun 07 06:18:48 PM PDT 24
Finished Jun 07 06:18:50 PM PDT 24
Peak memory 208684 kb
Host smart-0f618c62-40fa-48a9-960a-da8dc92b1240
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957875491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1957875491
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3960910777
Short name T596
Test name
Test status
Simulation time 343908218 ps
CPU time 2.67 seconds
Started Jun 07 06:18:59 PM PDT 24
Finished Jun 07 06:19:02 PM PDT 24
Peak memory 200416 kb
Host smart-2fe1ac54-8267-4cc4-8884-33fcd8c5e0a4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960910777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
960910777
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1381231219
Short name T591
Test name
Test status
Simulation time 272997062 ps
CPU time 3.1 seconds
Started Jun 07 06:18:57 PM PDT 24
Finished Jun 07 06:19:00 PM PDT 24
Peak memory 200492 kb
Host smart-4fc73699-6562-487c-8cf3-d9e14d8d6c95
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381231219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
381231219
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.4003342316
Short name T577
Test name
Test status
Simulation time 97660994 ps
CPU time 0.81 seconds
Started Jun 07 06:18:59 PM PDT 24
Finished Jun 07 06:19:00 PM PDT 24
Peak memory 200288 kb
Host smart-122d6d29-0058-4523-a5bd-ee97dfec8e63
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003342316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.4
003342316
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.664191805
Short name T582
Test name
Test status
Simulation time 172156971 ps
CPU time 1.1 seconds
Started Jun 07 06:18:57 PM PDT 24
Finished Jun 07 06:18:58 PM PDT 24
Peak memory 200272 kb
Host smart-cd075ab0-4a69-4f9b-bdf1-fca0c4a168ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664191805 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.664191805
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1096846270
Short name T562
Test name
Test status
Simulation time 88412284 ps
CPU time 0.93 seconds
Started Jun 07 06:18:52 PM PDT 24
Finished Jun 07 06:18:54 PM PDT 24
Peak memory 200152 kb
Host smart-831a71a8-cf8e-4956-b4e1-1ad024d51208
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096846270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1096846270
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4199512146
Short name T560
Test name
Test status
Simulation time 158874679 ps
CPU time 1.17 seconds
Started Jun 07 06:18:59 PM PDT 24
Finished Jun 07 06:19:00 PM PDT 24
Peak memory 200280 kb
Host smart-af55a807-cd32-4f82-9bc8-3795ef70b9b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199512146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.4199512146
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3240304497
Short name T115
Test name
Test status
Simulation time 166199914 ps
CPU time 2.38 seconds
Started Jun 07 06:18:55 PM PDT 24
Finished Jun 07 06:18:58 PM PDT 24
Peak memory 208708 kb
Host smart-e7ed6775-a58d-4a26-a7af-ccf80b162591
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240304497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3240304497
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2735827129
Short name T558
Test name
Test status
Simulation time 803245338 ps
CPU time 2.71 seconds
Started Jun 07 06:18:55 PM PDT 24
Finished Jun 07 06:18:58 PM PDT 24
Peak memory 200312 kb
Host smart-c180bc6b-0327-407d-b154-f290ffcfcfdb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735827129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2735827129
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2797652083
Short name T611
Test name
Test status
Simulation time 165703401 ps
CPU time 1.4 seconds
Started Jun 07 06:18:59 PM PDT 24
Finished Jun 07 06:19:01 PM PDT 24
Peak memory 212272 kb
Host smart-d7617077-302b-4acc-897a-2532efae4d43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797652083 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2797652083
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3165493595
Short name T105
Test name
Test status
Simulation time 64109768 ps
CPU time 0.79 seconds
Started Jun 07 06:18:59 PM PDT 24
Finished Jun 07 06:19:00 PM PDT 24
Peak memory 200216 kb
Host smart-d9a51c91-ec7d-48ec-babc-463e32475b6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165493595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3165493595
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4148923960
Short name T109
Test name
Test status
Simulation time 105152661 ps
CPU time 1.26 seconds
Started Jun 07 06:18:57 PM PDT 24
Finished Jun 07 06:18:59 PM PDT 24
Peak memory 200508 kb
Host smart-7df5e5d0-a23f-41f1-9d6b-1e88f6669536
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148923960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.4148923960
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3326417866
Short name T584
Test name
Test status
Simulation time 223998137 ps
CPU time 1.68 seconds
Started Jun 07 06:18:59 PM PDT 24
Finished Jun 07 06:19:01 PM PDT 24
Peak memory 208704 kb
Host smart-9f36e9d4-803b-49c2-865f-6a12f7f770fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326417866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3326417866
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1629633623
Short name T121
Test name
Test status
Simulation time 562943513 ps
CPU time 1.99 seconds
Started Jun 07 06:18:56 PM PDT 24
Finished Jun 07 06:18:58 PM PDT 24
Peak memory 200376 kb
Host smart-ea4c77d5-902a-479d-930a-2d1e1764e899
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629633623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1629633623
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2164078983
Short name T610
Test name
Test status
Simulation time 94403766 ps
CPU time 0.97 seconds
Started Jun 07 06:19:00 PM PDT 24
Finished Jun 07 06:19:02 PM PDT 24
Peak memory 200512 kb
Host smart-bac2fbaa-6a79-4c67-be8e-0fe70e662195
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164078983 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2164078983
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1708704615
Short name T613
Test name
Test status
Simulation time 66945863 ps
CPU time 0.76 seconds
Started Jun 07 06:18:54 PM PDT 24
Finished Jun 07 06:18:55 PM PDT 24
Peak memory 200112 kb
Host smart-ffb0ab64-5fe1-4547-820b-53394bb8dde9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708704615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1708704615
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3989996700
Short name T587
Test name
Test status
Simulation time 79022583 ps
CPU time 1 seconds
Started Jun 07 06:18:54 PM PDT 24
Finished Jun 07 06:18:56 PM PDT 24
Peak memory 200244 kb
Host smart-0c58e874-9eed-4ae2-9331-09e3288a1a63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989996700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3989996700
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2355338259
Short name T566
Test name
Test status
Simulation time 206164547 ps
CPU time 1.38 seconds
Started Jun 07 06:19:02 PM PDT 24
Finished Jun 07 06:19:03 PM PDT 24
Peak memory 210572 kb
Host smart-48ed4994-81c3-4fd1-856f-2093284704ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355338259 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2355338259
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.4169545613
Short name T59
Test name
Test status
Simulation time 85166186 ps
CPU time 0.89 seconds
Started Jun 07 06:19:02 PM PDT 24
Finished Jun 07 06:19:03 PM PDT 24
Peak memory 200176 kb
Host smart-03791b4d-a965-4206-b911-32c6ef9ab604
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169545613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.4169545613
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3162674066
Short name T111
Test name
Test status
Simulation time 83274282 ps
CPU time 0.96 seconds
Started Jun 07 06:19:01 PM PDT 24
Finished Jun 07 06:19:03 PM PDT 24
Peak memory 200304 kb
Host smart-55038bcf-63b2-432e-8aab-40fc511bacbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162674066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3162674066
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3756414678
Short name T89
Test name
Test status
Simulation time 502198142 ps
CPU time 3.26 seconds
Started Jun 07 06:19:02 PM PDT 24
Finished Jun 07 06:19:06 PM PDT 24
Peak memory 216600 kb
Host smart-2fcaf357-c339-40ac-9417-9bac978fa942
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756414678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3756414678
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1397877014
Short name T569
Test name
Test status
Simulation time 880796104 ps
CPU time 2.99 seconds
Started Jun 07 06:19:04 PM PDT 24
Finished Jun 07 06:19:08 PM PDT 24
Peak memory 200692 kb
Host smart-67892266-5013-4eed-9f63-4bbf041b2d2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397877014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.1397877014
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.877927
Short name T61
Test name
Test status
Simulation time 189899903 ps
CPU time 2.03 seconds
Started Jun 07 06:19:03 PM PDT 24
Finished Jun 07 06:19:05 PM PDT 24
Peak memory 208624 kb
Host smart-37c26ed0-eb66-4f03-847c-33cee43cf38b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877927 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.877927
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1064546448
Short name T561
Test name
Test status
Simulation time 76248323 ps
CPU time 0.84 seconds
Started Jun 07 06:18:59 PM PDT 24
Finished Jun 07 06:19:00 PM PDT 24
Peak memory 200220 kb
Host smart-f5ed8378-d46d-4123-9bbd-5b577e7a8d31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064546448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1064546448
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2175668396
Short name T565
Test name
Test status
Simulation time 133580072 ps
CPU time 1.04 seconds
Started Jun 07 06:19:01 PM PDT 24
Finished Jun 07 06:19:03 PM PDT 24
Peak memory 200308 kb
Host smart-a1e5dd57-629b-4daf-ae9a-544bfc066c96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175668396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.2175668396
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3415275138
Short name T575
Test name
Test status
Simulation time 193237508 ps
CPU time 2.61 seconds
Started Jun 07 06:19:04 PM PDT 24
Finished Jun 07 06:19:07 PM PDT 24
Peak memory 216752 kb
Host smart-e4324671-61cf-4fc2-966e-1bc0fdd3bcb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415275138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3415275138
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3971240679
Short name T64
Test name
Test status
Simulation time 449164415 ps
CPU time 1.81 seconds
Started Jun 07 06:19:03 PM PDT 24
Finished Jun 07 06:19:05 PM PDT 24
Peak memory 200476 kb
Host smart-2fd2b9e0-7f18-4a6f-9d3c-cd83b74e6fbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971240679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3971240679
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1115182195
Short name T607
Test name
Test status
Simulation time 173788754 ps
CPU time 1.24 seconds
Started Jun 07 06:19:03 PM PDT 24
Finished Jun 07 06:19:04 PM PDT 24
Peak memory 210628 kb
Host smart-c0148dd2-e704-4cb6-8787-c4dcae1dd671
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115182195 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1115182195
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1503452965
Short name T617
Test name
Test status
Simulation time 80540248 ps
CPU time 0.91 seconds
Started Jun 07 06:19:02 PM PDT 24
Finished Jun 07 06:19:03 PM PDT 24
Peak memory 200228 kb
Host smart-88d6b6be-b5d9-483e-b7bf-325af465b658
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503452965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1503452965
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3893005190
Short name T556
Test name
Test status
Simulation time 119539078 ps
CPU time 1.09 seconds
Started Jun 07 06:19:03 PM PDT 24
Finished Jun 07 06:19:05 PM PDT 24
Peak memory 200240 kb
Host smart-4458bb5b-af7f-47bd-a4a4-0fd0eeb94be9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893005190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3893005190
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1599135591
Short name T88
Test name
Test status
Simulation time 108855662 ps
CPU time 1.45 seconds
Started Jun 07 06:19:00 PM PDT 24
Finished Jun 07 06:19:02 PM PDT 24
Peak memory 211500 kb
Host smart-6bf2c53e-1215-4065-9347-05102c6092e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599135591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1599135591
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2124631981
Short name T112
Test name
Test status
Simulation time 420402535 ps
CPU time 1.83 seconds
Started Jun 07 06:19:02 PM PDT 24
Finished Jun 07 06:19:04 PM PDT 24
Peak memory 200536 kb
Host smart-9600b3ba-0f46-4aa6-8ed2-df2bc3c486c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124631981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.2124631981
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3934812937
Short name T479
Test name
Test status
Simulation time 80747032 ps
CPU time 0.87 seconds
Started Jun 07 06:19:26 PM PDT 24
Finished Jun 07 06:19:27 PM PDT 24
Peak memory 200088 kb
Host smart-a160482f-ed88-497b-af9e-3a4d56673c06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934812937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3934812937
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.501152572
Short name T297
Test name
Test status
Simulation time 2360215000 ps
CPU time 8.41 seconds
Started Jun 07 06:19:16 PM PDT 24
Finished Jun 07 06:19:25 PM PDT 24
Peak memory 217924 kb
Host smart-e304fe4b-41ad-4ce2-83c1-4d4eb54e118e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501152572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.501152572
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.246851397
Short name T34
Test name
Test status
Simulation time 243733107 ps
CPU time 1.09 seconds
Started Jun 07 06:19:28 PM PDT 24
Finished Jun 07 06:19:29 PM PDT 24
Peak memory 217568 kb
Host smart-8f8d004b-d7c1-4d2d-aa13-64286f484dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246851397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.246851397
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3318552477
Short name T296
Test name
Test status
Simulation time 1592796606 ps
CPU time 6.46 seconds
Started Jun 07 06:19:17 PM PDT 24
Finished Jun 07 06:19:24 PM PDT 24
Peak memory 200512 kb
Host smart-be9f3795-9b5a-4f54-a3dc-3e634672ab72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318552477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3318552477
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1215794988
Short name T198
Test name
Test status
Simulation time 193147872 ps
CPU time 1.3 seconds
Started Jun 07 06:19:17 PM PDT 24
Finished Jun 07 06:19:19 PM PDT 24
Peak memory 200484 kb
Host smart-88a5e95b-c52b-480a-a9be-30c0f81d66d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215794988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1215794988
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3072964409
Short name T277
Test name
Test status
Simulation time 6703090656 ps
CPU time 22.14 seconds
Started Jun 07 06:19:28 PM PDT 24
Finished Jun 07 06:19:50 PM PDT 24
Peak memory 216332 kb
Host smart-dc179629-365f-4077-80e9-1a731a7721e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072964409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3072964409
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.571221222
Short name T339
Test name
Test status
Simulation time 374362826 ps
CPU time 2.07 seconds
Started Jun 07 06:19:17 PM PDT 24
Finished Jun 07 06:19:19 PM PDT 24
Peak memory 200260 kb
Host smart-65592c29-96da-4742-b7e6-71e045f7fe87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571221222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.571221222
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.99317223
Short name T492
Test name
Test status
Simulation time 109275361 ps
CPU time 0.99 seconds
Started Jun 07 06:19:16 PM PDT 24
Finished Jun 07 06:19:18 PM PDT 24
Peak memory 200280 kb
Host smart-8f317a58-b78c-4a9d-9a80-61e036b1c86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99317223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.99317223
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3216650430
Short name T226
Test name
Test status
Simulation time 74030786 ps
CPU time 0.78 seconds
Started Jun 07 06:19:26 PM PDT 24
Finished Jun 07 06:19:28 PM PDT 24
Peak memory 200156 kb
Host smart-cf33bdc0-634f-415b-bc2a-41286c8d4299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216650430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3216650430
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2450076123
Short name T33
Test name
Test status
Simulation time 2367790434 ps
CPU time 8.66 seconds
Started Jun 07 06:19:25 PM PDT 24
Finished Jun 07 06:19:34 PM PDT 24
Peak memory 217288 kb
Host smart-fc658b26-813e-4524-b5a9-99d2a05c545b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450076123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2450076123
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1004584381
Short name T274
Test name
Test status
Simulation time 244029968 ps
CPU time 1.04 seconds
Started Jun 07 06:19:19 PM PDT 24
Finished Jun 07 06:19:21 PM PDT 24
Peak memory 217540 kb
Host smart-62ee0438-a265-4dcc-b260-fa9594eded3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004584381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1004584381
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3326764239
Short name T469
Test name
Test status
Simulation time 204981680 ps
CPU time 0.9 seconds
Started Jun 07 06:19:20 PM PDT 24
Finished Jun 07 06:19:22 PM PDT 24
Peak memory 200132 kb
Host smart-b4899e86-1d40-4842-9dd8-f219b3ee5324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326764239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3326764239
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.110400897
Short name T382
Test name
Test status
Simulation time 1665416792 ps
CPU time 6.61 seconds
Started Jun 07 06:19:21 PM PDT 24
Finished Jun 07 06:19:28 PM PDT 24
Peak memory 200600 kb
Host smart-4f2a691f-9f13-4408-a7f6-634941ede3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110400897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.110400897
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1023700063
Short name T67
Test name
Test status
Simulation time 8280427271 ps
CPU time 14.63 seconds
Started Jun 07 06:19:24 PM PDT 24
Finished Jun 07 06:19:39 PM PDT 24
Peak memory 217468 kb
Host smart-c97310cf-9252-4f47-930c-c0882e5780db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023700063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1023700063
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2543476061
Short name T36
Test name
Test status
Simulation time 151665360 ps
CPU time 1.12 seconds
Started Jun 07 06:19:22 PM PDT 24
Finished Jun 07 06:19:24 PM PDT 24
Peak memory 200296 kb
Host smart-9146e298-2cab-41b3-9489-d944ff63239a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543476061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2543476061
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1281546034
Short name T160
Test name
Test status
Simulation time 194773011 ps
CPU time 1.37 seconds
Started Jun 07 06:19:21 PM PDT 24
Finished Jun 07 06:19:23 PM PDT 24
Peak memory 200464 kb
Host smart-3c0af27b-bf2c-4e87-8207-2deabe822a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281546034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1281546034
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.771308980
Short name T352
Test name
Test status
Simulation time 1265207972 ps
CPU time 6.36 seconds
Started Jun 07 06:19:26 PM PDT 24
Finished Jun 07 06:19:33 PM PDT 24
Peak memory 200696 kb
Host smart-205f9306-2e6a-410d-b3e0-9bd59acd9556
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771308980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.771308980
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3275164362
Short name T521
Test name
Test status
Simulation time 412036067 ps
CPU time 2.39 seconds
Started Jun 07 06:19:22 PM PDT 24
Finished Jun 07 06:19:25 PM PDT 24
Peak memory 208492 kb
Host smart-81298cf7-e344-48ba-ae17-ccbca5c4c025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275164362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3275164362
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.942556613
Short name T210
Test name
Test status
Simulation time 100782260 ps
CPU time 0.95 seconds
Started Jun 07 06:19:24 PM PDT 24
Finished Jun 07 06:19:25 PM PDT 24
Peak memory 200276 kb
Host smart-3db16313-b93e-4e7b-9b0e-c1702d4552c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942556613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.942556613
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.4179991019
Short name T410
Test name
Test status
Simulation time 1230331522 ps
CPU time 5.75 seconds
Started Jun 07 06:19:42 PM PDT 24
Finished Jun 07 06:19:49 PM PDT 24
Peak memory 217048 kb
Host smart-2cc8abc6-b1d4-4d2a-8b50-da6cca011c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179991019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.4179991019
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1765668898
Short name T308
Test name
Test status
Simulation time 243988754 ps
CPU time 1.17 seconds
Started Jun 07 06:19:41 PM PDT 24
Finished Jun 07 06:19:43 PM PDT 24
Peak memory 217492 kb
Host smart-d45e416f-707a-4155-bf43-e7e2b388fda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765668898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1765668898
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.4106226693
Short name T242
Test name
Test status
Simulation time 78108109 ps
CPU time 0.73 seconds
Started Jun 07 06:19:40 PM PDT 24
Finished Jun 07 06:19:41 PM PDT 24
Peak memory 200104 kb
Host smart-b89c2dba-785d-4e48-8ac2-983c1a2c6d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106226693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.4106226693
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.1319866560
Short name T183
Test name
Test status
Simulation time 1477426352 ps
CPU time 6.65 seconds
Started Jun 07 06:19:44 PM PDT 24
Finished Jun 07 06:19:52 PM PDT 24
Peak memory 200528 kb
Host smart-23b3d772-6613-4a41-bfbf-d47ff9554164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319866560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.1319866560
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.711191264
Short name T258
Test name
Test status
Simulation time 176482178 ps
CPU time 1.17 seconds
Started Jun 07 06:19:40 PM PDT 24
Finished Jun 07 06:19:42 PM PDT 24
Peak memory 200372 kb
Host smart-c36e3afd-dbd7-4e18-8f88-94c0fb36fb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711191264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.711191264
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2603737721
Short name T161
Test name
Test status
Simulation time 248663317 ps
CPU time 1.42 seconds
Started Jun 07 06:19:42 PM PDT 24
Finished Jun 07 06:19:44 PM PDT 24
Peak memory 200448 kb
Host smart-a7767b46-5d47-4954-b8d0-b1383251f0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603737721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2603737721
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2699150679
Short name T204
Test name
Test status
Simulation time 8081228989 ps
CPU time 28.24 seconds
Started Jun 07 06:19:43 PM PDT 24
Finished Jun 07 06:20:13 PM PDT 24
Peak memory 208872 kb
Host smart-93f5d4dd-9d6a-4a99-8a57-b103a96e3c21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699150679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2699150679
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2929353233
Short name T219
Test name
Test status
Simulation time 260750105 ps
CPU time 1.94 seconds
Started Jun 07 06:19:44 PM PDT 24
Finished Jun 07 06:19:47 PM PDT 24
Peak memory 200384 kb
Host smart-437e7d64-c82d-4a78-ba00-fae7826cdf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929353233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2929353233
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2504343403
Short name T346
Test name
Test status
Simulation time 79604910 ps
CPU time 0.84 seconds
Started Jun 07 06:19:44 PM PDT 24
Finished Jun 07 06:19:46 PM PDT 24
Peak memory 200164 kb
Host smart-4a0195f9-6989-417b-b611-a285f122b5a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504343403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2504343403
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.4193585680
Short name T481
Test name
Test status
Simulation time 1886672042 ps
CPU time 6.94 seconds
Started Jun 07 06:19:43 PM PDT 24
Finished Jun 07 06:19:51 PM PDT 24
Peak memory 221980 kb
Host smart-8c1235db-3116-443f-b535-354c45a5fae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193585680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.4193585680
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3236402722
Short name T394
Test name
Test status
Simulation time 244832234 ps
CPU time 1.05 seconds
Started Jun 07 06:19:41 PM PDT 24
Finished Jun 07 06:19:42 PM PDT 24
Peak memory 217508 kb
Host smart-c8ee7cc9-3e5a-41b2-a50c-1afb5c153634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236402722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3236402722
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2257003432
Short name T14
Test name
Test status
Simulation time 197831101 ps
CPU time 0.96 seconds
Started Jun 07 06:19:46 PM PDT 24
Finished Jun 07 06:19:48 PM PDT 24
Peak memory 200108 kb
Host smart-e3c91784-842a-43fe-b46d-51a2c525010e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257003432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2257003432
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.3611746261
Short name T102
Test name
Test status
Simulation time 1633551058 ps
CPU time 6.74 seconds
Started Jun 07 06:19:44 PM PDT 24
Finished Jun 07 06:19:52 PM PDT 24
Peak memory 200652 kb
Host smart-d1a14ab6-fa7d-4a5f-abc0-f0697989c3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611746261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3611746261
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1105615384
Short name T275
Test name
Test status
Simulation time 103492545 ps
CPU time 0.99 seconds
Started Jun 07 06:19:44 PM PDT 24
Finished Jun 07 06:19:46 PM PDT 24
Peak memory 200316 kb
Host smart-d477bdad-67c7-4855-86ef-8166b39f06b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105615384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1105615384
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2432227861
Short name T165
Test name
Test status
Simulation time 248652556 ps
CPU time 1.46 seconds
Started Jun 07 06:19:42 PM PDT 24
Finished Jun 07 06:19:45 PM PDT 24
Peak memory 200500 kb
Host smart-a1bf0f7c-115e-4e6f-8306-f5f108cee255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432227861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2432227861
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.370038086
Short name T435
Test name
Test status
Simulation time 253150658 ps
CPU time 1.72 seconds
Started Jun 07 06:19:42 PM PDT 24
Finished Jun 07 06:19:44 PM PDT 24
Peak memory 200308 kb
Host smart-eea1f07f-e0e1-4d10-a410-05ab0efa7613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370038086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.370038086
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3828831562
Short name T457
Test name
Test status
Simulation time 143496693 ps
CPU time 1.08 seconds
Started Jun 07 06:19:44 PM PDT 24
Finished Jun 07 06:19:46 PM PDT 24
Peak memory 200324 kb
Host smart-5edc35e1-acc6-4b64-8fed-6ca5d962c9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828831562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3828831562
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1056132649
Short name T533
Test name
Test status
Simulation time 72456612 ps
CPU time 0.77 seconds
Started Jun 07 06:19:49 PM PDT 24
Finished Jun 07 06:19:51 PM PDT 24
Peak memory 200112 kb
Host smart-08343d76-1f69-4f0c-b96c-088a119316a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056132649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1056132649
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2880827884
Short name T545
Test name
Test status
Simulation time 2374932908 ps
CPU time 8.1 seconds
Started Jun 07 06:19:49 PM PDT 24
Finished Jun 07 06:19:57 PM PDT 24
Peak memory 217992 kb
Host smart-68c9be68-5e39-49de-a200-02b5ee6b66c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880827884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2880827884
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1509167436
Short name T246
Test name
Test status
Simulation time 244789420 ps
CPU time 1.09 seconds
Started Jun 07 06:19:47 PM PDT 24
Finished Jun 07 06:19:49 PM PDT 24
Peak memory 217596 kb
Host smart-9e73f637-0be8-407d-808a-67bdce79989b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509167436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1509167436
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.606456345
Short name T438
Test name
Test status
Simulation time 206032478 ps
CPU time 0.92 seconds
Started Jun 07 06:19:43 PM PDT 24
Finished Jun 07 06:19:46 PM PDT 24
Peak memory 200176 kb
Host smart-7c3c23f0-0160-406e-81de-7407bb17a1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606456345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.606456345
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.732109283
Short name T508
Test name
Test status
Simulation time 862166479 ps
CPU time 4.61 seconds
Started Jun 07 06:19:43 PM PDT 24
Finished Jun 07 06:19:49 PM PDT 24
Peak memory 200452 kb
Host smart-92674e86-b8a0-4f8f-8b8f-d60980bf3394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732109283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.732109283
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1668899048
Short name T167
Test name
Test status
Simulation time 171037051 ps
CPU time 1.24 seconds
Started Jun 07 06:19:42 PM PDT 24
Finished Jun 07 06:19:45 PM PDT 24
Peak memory 200268 kb
Host smart-f4539bc3-f977-4563-8813-028f3e18a973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668899048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1668899048
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.91576049
Short name T471
Test name
Test status
Simulation time 113859150 ps
CPU time 1.16 seconds
Started Jun 07 06:19:42 PM PDT 24
Finished Jun 07 06:19:44 PM PDT 24
Peak memory 200440 kb
Host smart-5bb19f5e-dfe0-41f5-8984-96924ab284af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91576049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.91576049
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.4179334570
Short name T480
Test name
Test status
Simulation time 6188044814 ps
CPU time 21.48 seconds
Started Jun 07 06:19:48 PM PDT 24
Finished Jun 07 06:20:10 PM PDT 24
Peak memory 200728 kb
Host smart-efea7d65-b23c-4659-b60a-d37754003410
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179334570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.4179334570
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2505011349
Short name T470
Test name
Test status
Simulation time 322160169 ps
CPU time 2.08 seconds
Started Jun 07 06:19:45 PM PDT 24
Finished Jun 07 06:19:48 PM PDT 24
Peak memory 200320 kb
Host smart-5e885a61-40db-4c3a-8c17-121b0425628c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505011349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2505011349
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2318760926
Short name T376
Test name
Test status
Simulation time 176033521 ps
CPU time 1.18 seconds
Started Jun 07 06:19:42 PM PDT 24
Finished Jun 07 06:19:44 PM PDT 24
Peak memory 200352 kb
Host smart-cc442aec-f884-408a-a5a9-c625bc8c3101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318760926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2318760926
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3535729455
Short name T140
Test name
Test status
Simulation time 72817861 ps
CPU time 0.78 seconds
Started Jun 07 06:19:51 PM PDT 24
Finished Jun 07 06:19:52 PM PDT 24
Peak memory 200144 kb
Host smart-e0ab67d5-cd27-4f0a-84dc-67addf045803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535729455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3535729455
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.811114621
Short name T241
Test name
Test status
Simulation time 244318342 ps
CPU time 1.1 seconds
Started Jun 07 06:19:48 PM PDT 24
Finished Jun 07 06:19:50 PM PDT 24
Peak memory 217556 kb
Host smart-fb2d3374-d44a-4583-b0db-5220c2361c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811114621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.811114621
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2771593516
Short name T537
Test name
Test status
Simulation time 160332485 ps
CPU time 0.86 seconds
Started Jun 07 06:19:51 PM PDT 24
Finished Jun 07 06:19:52 PM PDT 24
Peak memory 200140 kb
Host smart-eb3f03bb-4a01-4c58-aadf-fd43231560b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771593516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2771593516
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.1668878663
Short name T418
Test name
Test status
Simulation time 972070362 ps
CPU time 4.99 seconds
Started Jun 07 06:19:48 PM PDT 24
Finished Jun 07 06:19:54 PM PDT 24
Peak memory 200540 kb
Host smart-c0b77525-7242-4a45-b0f2-02321efc4ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668878663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1668878663
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.4100755019
Short name T486
Test name
Test status
Simulation time 175367904 ps
CPU time 1.19 seconds
Started Jun 07 06:19:46 PM PDT 24
Finished Jun 07 06:19:48 PM PDT 24
Peak memory 200272 kb
Host smart-221f2259-081e-404e-a7da-7238f24b152f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100755019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.4100755019
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1261016119
Short name T488
Test name
Test status
Simulation time 120997697 ps
CPU time 1.19 seconds
Started Jun 07 06:19:49 PM PDT 24
Finished Jun 07 06:19:51 PM PDT 24
Peak memory 200560 kb
Host smart-87cf74d2-9aea-4c7d-a85f-d740fc26d34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261016119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1261016119
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.757273234
Short name T536
Test name
Test status
Simulation time 1832329403 ps
CPU time 7.34 seconds
Started Jun 07 06:19:50 PM PDT 24
Finished Jun 07 06:19:58 PM PDT 24
Peak memory 200496 kb
Host smart-2dfab420-c315-486f-9492-99d35d5e2213
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757273234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.757273234
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.972503749
Short name T150
Test name
Test status
Simulation time 346868622 ps
CPU time 2.21 seconds
Started Jun 07 06:19:50 PM PDT 24
Finished Jun 07 06:19:53 PM PDT 24
Peak memory 200304 kb
Host smart-e5d7a4d8-8636-40c2-8817-6577f30bca76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972503749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.972503749
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.996264108
Short name T520
Test name
Test status
Simulation time 131457943 ps
CPU time 1.03 seconds
Started Jun 07 06:19:50 PM PDT 24
Finished Jun 07 06:19:52 PM PDT 24
Peak memory 200316 kb
Host smart-3c0d9f97-beca-4364-93b2-0419199550df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996264108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.996264108
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3859751604
Short name T52
Test name
Test status
Simulation time 90608137 ps
CPU time 0.88 seconds
Started Jun 07 06:19:49 PM PDT 24
Finished Jun 07 06:19:51 PM PDT 24
Peak memory 200164 kb
Host smart-fd149248-87cd-41b5-93cc-f6a08360dd10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859751604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3859751604
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1390235189
Short name T370
Test name
Test status
Simulation time 243570600 ps
CPU time 1.16 seconds
Started Jun 07 06:19:50 PM PDT 24
Finished Jun 07 06:19:52 PM PDT 24
Peak memory 217540 kb
Host smart-35fbb2bd-e0fb-43a8-b180-e531a3e28ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390235189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.1390235189
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3744946931
Short name T452
Test name
Test status
Simulation time 105739849 ps
CPU time 0.76 seconds
Started Jun 07 06:19:49 PM PDT 24
Finished Jun 07 06:19:51 PM PDT 24
Peak memory 200160 kb
Host smart-56ed59b2-d88c-472c-8de5-77c7003d70cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744946931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3744946931
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.1978237946
Short name T284
Test name
Test status
Simulation time 1048204125 ps
CPU time 4.83 seconds
Started Jun 07 06:19:49 PM PDT 24
Finished Jun 07 06:19:55 PM PDT 24
Peak memory 200456 kb
Host smart-f7925ca3-58c1-4abf-9cf8-53d258596d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978237946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1978237946
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1732720541
Short name T387
Test name
Test status
Simulation time 148916447 ps
CPU time 1.13 seconds
Started Jun 07 06:19:50 PM PDT 24
Finished Jun 07 06:19:51 PM PDT 24
Peak memory 200244 kb
Host smart-efddde25-173d-4ba8-8c0f-2b4aa94172c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732720541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1732720541
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.4100373739
Short name T341
Test name
Test status
Simulation time 122373513 ps
CPU time 1.21 seconds
Started Jun 07 06:19:47 PM PDT 24
Finished Jun 07 06:19:49 PM PDT 24
Peak memory 200392 kb
Host smart-414200f2-e11d-41cc-a0b0-bbc895bdb34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100373739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.4100373739
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2464392411
Short name T128
Test name
Test status
Simulation time 10638956119 ps
CPU time 36.63 seconds
Started Jun 07 06:19:47 PM PDT 24
Finished Jun 07 06:20:24 PM PDT 24
Peak memory 200608 kb
Host smart-7ecbcc18-9d2a-4054-acae-26a38cbafbf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464392411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2464392411
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2363792220
Short name T526
Test name
Test status
Simulation time 138366594 ps
CPU time 1.82 seconds
Started Jun 07 06:19:52 PM PDT 24
Finished Jun 07 06:19:54 PM PDT 24
Peak memory 200536 kb
Host smart-31ac0015-7261-4e2e-949e-8879ef3b9d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363792220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2363792220
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.886761727
Short name T197
Test name
Test status
Simulation time 72831721 ps
CPU time 0.74 seconds
Started Jun 07 06:19:49 PM PDT 24
Finished Jun 07 06:19:51 PM PDT 24
Peak memory 200260 kb
Host smart-f4e5a176-3e5a-49c5-9ba1-2f18016a7ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886761727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.886761727
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.1288413815
Short name T361
Test name
Test status
Simulation time 81116198 ps
CPU time 0.85 seconds
Started Jun 07 06:19:56 PM PDT 24
Finished Jun 07 06:19:58 PM PDT 24
Peak memory 200144 kb
Host smart-14fb3c5c-1efb-42d6-be53-9d2fa597d7be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288413815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.1288413815
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2978399453
Short name T392
Test name
Test status
Simulation time 1887513357 ps
CPU time 8.12 seconds
Started Jun 07 06:19:54 PM PDT 24
Finished Jun 07 06:20:02 PM PDT 24
Peak memory 217972 kb
Host smart-29a440be-56d2-4a94-8bd6-47c50b776d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978399453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2978399453
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1848744487
Short name T181
Test name
Test status
Simulation time 244245881 ps
CPU time 1.11 seconds
Started Jun 07 06:20:01 PM PDT 24
Finished Jun 07 06:20:02 PM PDT 24
Peak memory 217440 kb
Host smart-3688221d-c2b8-4dfc-81ef-80365da99e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848744487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1848744487
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.1642572897
Short name T347
Test name
Test status
Simulation time 134823222 ps
CPU time 0.86 seconds
Started Jun 07 06:19:46 PM PDT 24
Finished Jun 07 06:19:48 PM PDT 24
Peak memory 200048 kb
Host smart-869f4ef6-9bb7-45e7-b32a-9585c6978965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642572897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1642572897
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.304848970
Short name T493
Test name
Test status
Simulation time 958714258 ps
CPU time 4.63 seconds
Started Jun 07 06:19:49 PM PDT 24
Finished Jun 07 06:19:54 PM PDT 24
Peak memory 200540 kb
Host smart-e8ac19a7-a2c6-437d-b397-60a628b21c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304848970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.304848970
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3253328597
Short name T187
Test name
Test status
Simulation time 164856652 ps
CPU time 1.14 seconds
Started Jun 07 06:19:56 PM PDT 24
Finished Jun 07 06:19:58 PM PDT 24
Peak memory 200368 kb
Host smart-9537b5dd-87b6-47d6-9847-a32e2a1d728e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253328597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3253328597
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.258342314
Short name T460
Test name
Test status
Simulation time 198486477 ps
CPU time 1.39 seconds
Started Jun 07 06:19:49 PM PDT 24
Finished Jun 07 06:19:51 PM PDT 24
Peak memory 200492 kb
Host smart-96906b1e-f518-4e54-b6a1-c760e597554e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258342314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.258342314
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.956732373
Short name T391
Test name
Test status
Simulation time 2713844401 ps
CPU time 12.84 seconds
Started Jun 07 06:19:56 PM PDT 24
Finished Jun 07 06:20:10 PM PDT 24
Peak memory 208860 kb
Host smart-5ea7a348-db58-4aaa-9947-83feb6b24310
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956732373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.956732373
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2146396211
Short name T8
Test name
Test status
Simulation time 385527416 ps
CPU time 2.03 seconds
Started Jun 07 06:19:52 PM PDT 24
Finished Jun 07 06:19:54 PM PDT 24
Peak memory 200344 kb
Host smart-6a5dc5cc-8249-43c3-8f43-d2a1c6b4c4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146396211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2146396211
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3262615623
Short name T313
Test name
Test status
Simulation time 181576233 ps
CPU time 1.23 seconds
Started Jun 07 06:19:56 PM PDT 24
Finished Jun 07 06:19:58 PM PDT 24
Peak memory 200352 kb
Host smart-f1960a89-00e6-4c10-bbce-c63d8f35b9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262615623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3262615623
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.4206565824
Short name T152
Test name
Test status
Simulation time 90747258 ps
CPU time 0.83 seconds
Started Jun 07 06:19:56 PM PDT 24
Finished Jun 07 06:19:57 PM PDT 24
Peak memory 200124 kb
Host smart-b46e93e9-d232-461e-8121-117f7059c919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206565824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.4206565824
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1730789481
Short name T51
Test name
Test status
Simulation time 1898167517 ps
CPU time 7.22 seconds
Started Jun 07 06:19:54 PM PDT 24
Finished Jun 07 06:20:01 PM PDT 24
Peak memory 217784 kb
Host smart-01df1274-6ad4-45ba-9d94-cb986b486497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730789481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1730789481
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2302008055
Short name T291
Test name
Test status
Simulation time 244442621 ps
CPU time 1.15 seconds
Started Jun 07 06:19:56 PM PDT 24
Finished Jun 07 06:19:58 PM PDT 24
Peak memory 217588 kb
Host smart-58252b16-74ab-4fdc-aaba-a022a00e0a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302008055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2302008055
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2149308488
Short name T431
Test name
Test status
Simulation time 154916526 ps
CPU time 0.86 seconds
Started Jun 07 06:19:56 PM PDT 24
Finished Jun 07 06:19:57 PM PDT 24
Peak memory 200136 kb
Host smart-20b68899-3edc-49f9-9f4d-e217e5cfbbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149308488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2149308488
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.239888116
Short name T103
Test name
Test status
Simulation time 762947103 ps
CPU time 3.71 seconds
Started Jun 07 06:19:58 PM PDT 24
Finished Jun 07 06:20:02 PM PDT 24
Peak memory 200432 kb
Host smart-dfe68d9f-15bf-4a5a-84e0-23e2bf81a2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239888116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.239888116
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.759860510
Short name T285
Test name
Test status
Simulation time 95438683 ps
CPU time 0.97 seconds
Started Jun 07 06:19:57 PM PDT 24
Finished Jun 07 06:19:58 PM PDT 24
Peak memory 200336 kb
Host smart-8cd456c3-9fcd-4765-a751-57d5f193f4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759860510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.759860510
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1851922352
Short name T185
Test name
Test status
Simulation time 120730978 ps
CPU time 1.22 seconds
Started Jun 07 06:19:56 PM PDT 24
Finished Jun 07 06:19:58 PM PDT 24
Peak memory 200444 kb
Host smart-a363b86e-356c-448e-a393-34b641ae6791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851922352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1851922352
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2045818459
Short name T99
Test name
Test status
Simulation time 4583825967 ps
CPU time 20.21 seconds
Started Jun 07 06:19:54 PM PDT 24
Finished Jun 07 06:20:14 PM PDT 24
Peak memory 200708 kb
Host smart-7bef3191-3949-4405-9507-eec6cb049407
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045818459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2045818459
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2656771705
Short name T516
Test name
Test status
Simulation time 141485138 ps
CPU time 1.7 seconds
Started Jun 07 06:19:55 PM PDT 24
Finished Jun 07 06:19:57 PM PDT 24
Peak memory 200184 kb
Host smart-8b0af3e0-f2f4-42ef-9689-50df93213182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656771705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2656771705
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1546575392
Short name T162
Test name
Test status
Simulation time 118197151 ps
CPU time 0.95 seconds
Started Jun 07 06:19:55 PM PDT 24
Finished Jun 07 06:19:57 PM PDT 24
Peak memory 200276 kb
Host smart-8b769266-ef36-450c-b1ea-83331fce5d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546575392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1546575392
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3697981549
Short name T70
Test name
Test status
Simulation time 74571790 ps
CPU time 0.8 seconds
Started Jun 07 06:19:54 PM PDT 24
Finished Jun 07 06:19:55 PM PDT 24
Peak memory 200172 kb
Host smart-6d882a17-ff77-4498-a01f-31c8445ef532
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697981549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3697981549
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.52989642
Short name T45
Test name
Test status
Simulation time 1889874542 ps
CPU time 7.64 seconds
Started Jun 07 06:19:59 PM PDT 24
Finished Jun 07 06:20:07 PM PDT 24
Peak memory 217924 kb
Host smart-2c6ec183-f67a-47b5-96c9-1b39f07e3d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52989642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.52989642
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.969970727
Short name T390
Test name
Test status
Simulation time 245695374 ps
CPU time 1.11 seconds
Started Jun 07 06:19:56 PM PDT 24
Finished Jun 07 06:19:57 PM PDT 24
Peak memory 217284 kb
Host smart-b680739e-4a56-4564-9291-ffdf9625e4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969970727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.969970727
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.261058619
Short name T301
Test name
Test status
Simulation time 81027362 ps
CPU time 0.76 seconds
Started Jun 07 06:19:52 PM PDT 24
Finished Jun 07 06:19:54 PM PDT 24
Peak memory 200128 kb
Host smart-a74bbffb-72e6-4070-bed3-01448d13575d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261058619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.261058619
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2155884670
Short name T133
Test name
Test status
Simulation time 1244875452 ps
CPU time 5.92 seconds
Started Jun 07 06:19:56 PM PDT 24
Finished Jun 07 06:20:02 PM PDT 24
Peak memory 200540 kb
Host smart-831f3ffb-5382-492a-b3bc-083fdc5eebed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155884670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2155884670
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3873785118
Short name T193
Test name
Test status
Simulation time 181317466 ps
CPU time 1.2 seconds
Started Jun 07 06:19:57 PM PDT 24
Finished Jun 07 06:19:59 PM PDT 24
Peak memory 200328 kb
Host smart-f774ac6f-a63a-49a0-8a40-8a60e2248934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873785118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3873785118
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2434901011
Short name T260
Test name
Test status
Simulation time 125536325 ps
CPU time 1.18 seconds
Started Jun 07 06:19:57 PM PDT 24
Finished Jun 07 06:19:59 PM PDT 24
Peak memory 200496 kb
Host smart-40f207aa-9ffd-4477-8edc-0ba026574f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434901011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2434901011
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.4288602817
Short name T532
Test name
Test status
Simulation time 3953735229 ps
CPU time 17.38 seconds
Started Jun 07 06:19:58 PM PDT 24
Finished Jun 07 06:20:16 PM PDT 24
Peak memory 208860 kb
Host smart-6863bc9e-7493-413d-91fa-e033f0db5d9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288602817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.4288602817
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2350130877
Short name T47
Test name
Test status
Simulation time 134287112 ps
CPU time 1.75 seconds
Started Jun 07 06:19:55 PM PDT 24
Finished Jun 07 06:19:57 PM PDT 24
Peak memory 208484 kb
Host smart-e1c9b962-0736-4b21-a437-ad5a64766cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350130877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2350130877
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.561918677
Short name T349
Test name
Test status
Simulation time 65567112 ps
CPU time 0.76 seconds
Started Jun 07 06:19:53 PM PDT 24
Finished Jun 07 06:19:55 PM PDT 24
Peak memory 200260 kb
Host smart-0ba1bfbe-4bc6-4aa7-8faf-a8178336b008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561918677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.561918677
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2398423994
Short name T319
Test name
Test status
Simulation time 78611445 ps
CPU time 0.78 seconds
Started Jun 07 06:19:56 PM PDT 24
Finished Jun 07 06:19:58 PM PDT 24
Peak memory 200136 kb
Host smart-8fa24efa-b23d-49d5-b34c-f4f1ef790f5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398423994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2398423994
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.454742321
Short name T405
Test name
Test status
Simulation time 1897960311 ps
CPU time 6.78 seconds
Started Jun 07 06:19:55 PM PDT 24
Finished Jun 07 06:20:03 PM PDT 24
Peak memory 217864 kb
Host smart-8200a4d3-84ca-40b2-9da0-56a40915a46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454742321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.454742321
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1994186683
Short name T4
Test name
Test status
Simulation time 244148350 ps
CPU time 1.09 seconds
Started Jun 07 06:19:56 PM PDT 24
Finished Jun 07 06:19:58 PM PDT 24
Peak memory 217548 kb
Host smart-5a262863-3ea4-4e04-9527-9edc2c1541fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994186683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1994186683
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.134769329
Short name T514
Test name
Test status
Simulation time 120791197 ps
CPU time 0.79 seconds
Started Jun 07 06:19:56 PM PDT 24
Finished Jun 07 06:19:57 PM PDT 24
Peak memory 199932 kb
Host smart-c681ff42-95a7-4678-97e9-b5d25be255bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134769329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.134769329
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1920867308
Short name T406
Test name
Test status
Simulation time 829577434 ps
CPU time 4.26 seconds
Started Jun 07 06:20:00 PM PDT 24
Finished Jun 07 06:20:05 PM PDT 24
Peak memory 200464 kb
Host smart-8cba2b38-e4f2-4121-a477-42c11fc8ec8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920867308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1920867308
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3318974992
Short name T324
Test name
Test status
Simulation time 154327448 ps
CPU time 1.16 seconds
Started Jun 07 06:20:01 PM PDT 24
Finished Jun 07 06:20:03 PM PDT 24
Peak memory 200340 kb
Host smart-73d59a3a-91a3-45d0-8c75-a097dd40b255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318974992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3318974992
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.3315303716
Short name T281
Test name
Test status
Simulation time 262951738 ps
CPU time 1.53 seconds
Started Jun 07 06:19:55 PM PDT 24
Finished Jun 07 06:19:57 PM PDT 24
Peak memory 200564 kb
Host smart-d8b2b97b-97c1-4caa-86e9-4e4f4eb63962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315303716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.3315303716
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2834534416
Short name T100
Test name
Test status
Simulation time 3832845695 ps
CPU time 17.85 seconds
Started Jun 07 06:19:59 PM PDT 24
Finished Jun 07 06:20:17 PM PDT 24
Peak memory 208840 kb
Host smart-422ad50b-2927-49b6-a4ac-a46bd5d5596b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834534416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2834534416
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1660723364
Short name T427
Test name
Test status
Simulation time 444493946 ps
CPU time 2.73 seconds
Started Jun 07 06:19:56 PM PDT 24
Finished Jun 07 06:19:59 PM PDT 24
Peak memory 200340 kb
Host smart-c24c9111-8348-47e7-abd1-e61d2555691a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660723364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1660723364
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2230095023
Short name T364
Test name
Test status
Simulation time 64859621 ps
CPU time 0.77 seconds
Started Jun 07 06:19:53 PM PDT 24
Finished Jun 07 06:19:54 PM PDT 24
Peak memory 200344 kb
Host smart-2fba445a-7bd4-4d44-8c1a-a19584b44f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230095023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2230095023
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.4207133349
Short name T279
Test name
Test status
Simulation time 64735280 ps
CPU time 0.76 seconds
Started Jun 07 06:20:06 PM PDT 24
Finished Jun 07 06:20:07 PM PDT 24
Peak memory 200152 kb
Host smart-4bc42df9-68d7-4fa5-a136-838355cdbeac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207133349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.4207133349
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2719838272
Short name T379
Test name
Test status
Simulation time 1886012188 ps
CPU time 7.04 seconds
Started Jun 07 06:20:02 PM PDT 24
Finished Jun 07 06:20:09 PM PDT 24
Peak memory 218000 kb
Host smart-a68db4b3-9ba6-4cc7-bac7-610bc075cb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719838272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2719838272
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.4155636595
Short name T79
Test name
Test status
Simulation time 244542367 ps
CPU time 1.1 seconds
Started Jun 07 06:20:02 PM PDT 24
Finished Jun 07 06:20:04 PM PDT 24
Peak memory 217556 kb
Host smart-8fc6195f-da58-41f4-bf6d-c87a238f5fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155636595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.4155636595
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.4234050174
Short name T298
Test name
Test status
Simulation time 191991450 ps
CPU time 0.84 seconds
Started Jun 07 06:19:54 PM PDT 24
Finished Jun 07 06:19:55 PM PDT 24
Peak memory 200140 kb
Host smart-cb22c16b-dec0-4d4e-b0b8-892890fbcbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234050174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.4234050174
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3660270649
Short name T126
Test name
Test status
Simulation time 2156597585 ps
CPU time 8.82 seconds
Started Jun 07 06:19:55 PM PDT 24
Finished Jun 07 06:20:05 PM PDT 24
Peak memory 200648 kb
Host smart-7c61bfb1-d521-4a37-89b4-16c3e10ff6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660270649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3660270649
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.29261801
Short name T238
Test name
Test status
Simulation time 105983920 ps
CPU time 1.05 seconds
Started Jun 07 06:20:01 PM PDT 24
Finished Jun 07 06:20:02 PM PDT 24
Peak memory 200380 kb
Host smart-45b5b755-ca47-410d-81b4-e2a8502881ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29261801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.29261801
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.333059831
Short name T232
Test name
Test status
Simulation time 198443070 ps
CPU time 1.39 seconds
Started Jun 07 06:19:54 PM PDT 24
Finished Jun 07 06:19:56 PM PDT 24
Peak memory 200528 kb
Host smart-688e5293-9aab-41fa-b331-9173f530e836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333059831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.333059831
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1375465802
Short name T95
Test name
Test status
Simulation time 1897589156 ps
CPU time 6.7 seconds
Started Jun 07 06:20:04 PM PDT 24
Finished Jun 07 06:20:11 PM PDT 24
Peak memory 200536 kb
Host smart-5edb3cab-9bb8-4e96-b5f2-a2e5c505accf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375465802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1375465802
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3766323921
Short name T202
Test name
Test status
Simulation time 554991542 ps
CPU time 2.75 seconds
Started Jun 07 06:20:04 PM PDT 24
Finished Jun 07 06:20:07 PM PDT 24
Peak memory 200320 kb
Host smart-31704840-c25a-4db9-809f-d26a7f3e7e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766323921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3766323921
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.673424812
Short name T515
Test name
Test status
Simulation time 245406313 ps
CPU time 1.47 seconds
Started Jun 07 06:20:01 PM PDT 24
Finished Jun 07 06:20:02 PM PDT 24
Peak memory 200152 kb
Host smart-af8411f6-b539-442b-90c4-8f6efdd015fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673424812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.673424812
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.845744985
Short name T199
Test name
Test status
Simulation time 77369533 ps
CPU time 0.77 seconds
Started Jun 07 06:19:27 PM PDT 24
Finished Jun 07 06:19:29 PM PDT 24
Peak memory 200104 kb
Host smart-3d9f622f-2ec1-4b8c-85e8-e99202a97adf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845744985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.845744985
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.1252739349
Short name T44
Test name
Test status
Simulation time 1907622076 ps
CPU time 7.08 seconds
Started Jun 07 06:19:27 PM PDT 24
Finished Jun 07 06:19:34 PM PDT 24
Peak memory 217952 kb
Host smart-9671f98d-86a4-4b12-90bb-793b88ac606f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252739349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.1252739349
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1553242882
Short name T484
Test name
Test status
Simulation time 244708810 ps
CPU time 1.09 seconds
Started Jun 07 06:19:26 PM PDT 24
Finished Jun 07 06:19:27 PM PDT 24
Peak memory 217460 kb
Host smart-9333f847-72ef-4597-b63a-2812c9e7effb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553242882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1553242882
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.128856126
Short name T434
Test name
Test status
Simulation time 222997805 ps
CPU time 0.95 seconds
Started Jun 07 06:19:25 PM PDT 24
Finished Jun 07 06:19:26 PM PDT 24
Peak memory 200096 kb
Host smart-a68a4866-111d-4fb0-9c81-086d82fced95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128856126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.128856126
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.19233706
Short name T385
Test name
Test status
Simulation time 757860586 ps
CPU time 3.84 seconds
Started Jun 07 06:19:26 PM PDT 24
Finished Jun 07 06:19:31 PM PDT 24
Peak memory 200536 kb
Host smart-b88ecf04-864f-4e7e-a9c5-009c1287ae82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19233706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.19233706
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2104865496
Short name T66
Test name
Test status
Simulation time 16817751905 ps
CPU time 25.33 seconds
Started Jun 07 06:19:31 PM PDT 24
Finished Jun 07 06:19:57 PM PDT 24
Peak memory 218520 kb
Host smart-1e9abad6-7bf5-4b6f-9715-dc6b391fff25
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104865496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2104865496
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3099000263
Short name T539
Test name
Test status
Simulation time 180781651 ps
CPU time 1.16 seconds
Started Jun 07 06:19:27 PM PDT 24
Finished Jun 07 06:19:29 PM PDT 24
Peak memory 200348 kb
Host smart-1123e55d-3de9-4c55-9be7-9810c4bf7d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099000263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3099000263
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1587378087
Short name T81
Test name
Test status
Simulation time 120194527 ps
CPU time 1.15 seconds
Started Jun 07 06:19:24 PM PDT 24
Finished Jun 07 06:19:26 PM PDT 24
Peak memory 200420 kb
Host smart-0f301e83-9d04-4be6-898c-7ff260e0264e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587378087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1587378087
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1673775484
Short name T445
Test name
Test status
Simulation time 8875722922 ps
CPU time 30.5 seconds
Started Jun 07 06:19:25 PM PDT 24
Finished Jun 07 06:19:56 PM PDT 24
Peak memory 200616 kb
Host smart-9aa9c16d-08bc-40f4-8346-4aafdee35bb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673775484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1673775484
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.210393097
Short name T191
Test name
Test status
Simulation time 144204386 ps
CPU time 1.86 seconds
Started Jun 07 06:19:24 PM PDT 24
Finished Jun 07 06:19:26 PM PDT 24
Peak memory 200164 kb
Host smart-ef71798a-3ce1-4571-96a6-33691a331175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210393097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.210393097
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.4033480687
Short name T22
Test name
Test status
Simulation time 241731713 ps
CPU time 1.52 seconds
Started Jun 07 06:19:24 PM PDT 24
Finished Jun 07 06:19:26 PM PDT 24
Peak memory 200284 kb
Host smart-80f304c3-5b7e-4bc9-86a5-b5d941bb8d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033480687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.4033480687
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2181271752
Short name T229
Test name
Test status
Simulation time 99982407 ps
CPU time 0.82 seconds
Started Jun 07 06:20:01 PM PDT 24
Finished Jun 07 06:20:02 PM PDT 24
Peak memory 200172 kb
Host smart-0aeabd76-41af-401f-bb5d-bfd2dfe692cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181271752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2181271752
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3466560693
Short name T340
Test name
Test status
Simulation time 1231881887 ps
CPU time 5.66 seconds
Started Jun 07 06:20:04 PM PDT 24
Finished Jun 07 06:20:10 PM PDT 24
Peak memory 221904 kb
Host smart-5a32ce3c-e9ae-4b15-9d57-dbb6ca2bed99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466560693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3466560693
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.383186401
Short name T253
Test name
Test status
Simulation time 244912609 ps
CPU time 1.08 seconds
Started Jun 07 06:20:02 PM PDT 24
Finished Jun 07 06:20:03 PM PDT 24
Peak memory 217596 kb
Host smart-2230d141-4fb3-48a6-936f-5c0d3fde93b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383186401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.383186401
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.4291263115
Short name T2
Test name
Test status
Simulation time 121038421 ps
CPU time 0.82 seconds
Started Jun 07 06:20:02 PM PDT 24
Finished Jun 07 06:20:03 PM PDT 24
Peak memory 200112 kb
Host smart-0c2ed33a-7555-4ed7-8b17-1c737d7aae63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291263115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.4291263115
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3245364913
Short name T303
Test name
Test status
Simulation time 926367963 ps
CPU time 4.75 seconds
Started Jun 07 06:20:03 PM PDT 24
Finished Jun 07 06:20:08 PM PDT 24
Peak memory 200552 kb
Host smart-ace06d26-f976-49d5-a51d-44203ecfa1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245364913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3245364913
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3518966166
Short name T524
Test name
Test status
Simulation time 159375093 ps
CPU time 1.1 seconds
Started Jun 07 06:20:05 PM PDT 24
Finished Jun 07 06:20:06 PM PDT 24
Peak memory 200328 kb
Host smart-32de753f-08ba-498e-bc2f-8017702ae7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518966166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3518966166
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1091850058
Short name T35
Test name
Test status
Simulation time 260148110 ps
CPU time 1.57 seconds
Started Jun 07 06:20:02 PM PDT 24
Finished Jun 07 06:20:04 PM PDT 24
Peak memory 200600 kb
Host smart-8d25cb5f-90cc-44ce-8114-bd0e48ef2d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091850058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1091850058
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2655385671
Short name T502
Test name
Test status
Simulation time 11898200309 ps
CPU time 46.97 seconds
Started Jun 07 06:20:02 PM PDT 24
Finished Jun 07 06:20:50 PM PDT 24
Peak memory 200648 kb
Host smart-a8dd2e94-0302-48e5-a7af-93da7c8c256c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655385671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2655385671
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.568480912
Short name T409
Test name
Test status
Simulation time 142456549 ps
CPU time 1.71 seconds
Started Jun 07 06:20:01 PM PDT 24
Finished Jun 07 06:20:03 PM PDT 24
Peak memory 200296 kb
Host smart-56128116-1873-4dcb-ac10-ec8d9e6bb1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568480912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.568480912
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2458148155
Short name T138
Test name
Test status
Simulation time 152606811 ps
CPU time 1.27 seconds
Started Jun 07 06:20:03 PM PDT 24
Finished Jun 07 06:20:04 PM PDT 24
Peak memory 200496 kb
Host smart-557626b7-ca05-4cc7-b994-a1503f2dc36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458148155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2458148155
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.584055158
Short name T322
Test name
Test status
Simulation time 72031567 ps
CPU time 0.77 seconds
Started Jun 07 06:20:07 PM PDT 24
Finished Jun 07 06:20:09 PM PDT 24
Peak memory 200236 kb
Host smart-86f71dbc-508e-4663-9f2c-048de1086dc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584055158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.584055158
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2641703359
Short name T31
Test name
Test status
Simulation time 1222340936 ps
CPU time 5.57 seconds
Started Jun 07 06:20:03 PM PDT 24
Finished Jun 07 06:20:09 PM PDT 24
Peak memory 217792 kb
Host smart-eca29e97-35ea-477b-8495-427a1b497278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641703359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2641703359
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.958900151
Short name T359
Test name
Test status
Simulation time 245327001 ps
CPU time 1.02 seconds
Started Jun 07 06:20:04 PM PDT 24
Finished Jun 07 06:20:06 PM PDT 24
Peak memory 217568 kb
Host smart-5a447962-36c9-4aff-8697-2f159ce60835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958900151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.958900151
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.673888078
Short name T454
Test name
Test status
Simulation time 148195906 ps
CPU time 0.94 seconds
Started Jun 07 06:20:02 PM PDT 24
Finished Jun 07 06:20:03 PM PDT 24
Peak memory 200180 kb
Host smart-d68b21d9-f328-4a30-82bd-7ad70740ba89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673888078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.673888078
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.4264643317
Short name T512
Test name
Test status
Simulation time 900199989 ps
CPU time 4.74 seconds
Started Jun 07 06:20:01 PM PDT 24
Finished Jun 07 06:20:06 PM PDT 24
Peak memory 200492 kb
Host smart-63dd9f35-b998-492a-9e7a-bba6ba5bb801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264643317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.4264643317
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.324642311
Short name T497
Test name
Test status
Simulation time 93992772 ps
CPU time 0.98 seconds
Started Jun 07 06:20:00 PM PDT 24
Finished Jun 07 06:20:01 PM PDT 24
Peak memory 200376 kb
Host smart-285a9f0e-e67e-4853-a3bd-108e9c08e5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324642311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.324642311
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2087280202
Short name T200
Test name
Test status
Simulation time 261071895 ps
CPU time 1.63 seconds
Started Jun 07 06:20:02 PM PDT 24
Finished Jun 07 06:20:03 PM PDT 24
Peak memory 200544 kb
Host smart-ed0bafdd-e736-44b0-9ce5-3f9869b7f5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087280202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2087280202
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2445845140
Short name T307
Test name
Test status
Simulation time 4183809745 ps
CPU time 14.15 seconds
Started Jun 07 06:20:14 PM PDT 24
Finished Jun 07 06:20:29 PM PDT 24
Peak memory 200684 kb
Host smart-bcfcb623-3cd0-4265-897a-cfd0086d5dad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445845140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2445845140
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2351578276
Short name T7
Test name
Test status
Simulation time 485624731 ps
CPU time 2.63 seconds
Started Jun 07 06:20:05 PM PDT 24
Finished Jun 07 06:20:08 PM PDT 24
Peak memory 200328 kb
Host smart-d3c070d8-6dda-4d8b-acb5-22dd13b3a04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351578276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2351578276
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3734659056
Short name T365
Test name
Test status
Simulation time 132496982 ps
CPU time 0.98 seconds
Started Jun 07 06:20:04 PM PDT 24
Finished Jun 07 06:20:06 PM PDT 24
Peak memory 200312 kb
Host smart-bdb3dd85-ebf3-4a41-8b82-d9ac6e2aa179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734659056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3734659056
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2315403965
Short name T483
Test name
Test status
Simulation time 73704612 ps
CPU time 0.8 seconds
Started Jun 07 06:20:13 PM PDT 24
Finished Jun 07 06:20:15 PM PDT 24
Peak memory 200084 kb
Host smart-796a0549-0f43-42cf-af91-d23780900f9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315403965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2315403965
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1658222414
Short name T463
Test name
Test status
Simulation time 1910877800 ps
CPU time 6.88 seconds
Started Jun 07 06:20:10 PM PDT 24
Finished Jun 07 06:20:17 PM PDT 24
Peak memory 217020 kb
Host smart-7fac32d5-842f-48fe-853c-14168918e3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658222414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1658222414
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1387752127
Short name T141
Test name
Test status
Simulation time 243868624 ps
CPU time 1.07 seconds
Started Jun 07 06:20:10 PM PDT 24
Finished Jun 07 06:20:11 PM PDT 24
Peak memory 217572 kb
Host smart-ac687bdb-40af-4c2e-8e8a-214ffab37e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387752127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1387752127
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3935351453
Short name T528
Test name
Test status
Simulation time 129732427 ps
CPU time 0.87 seconds
Started Jun 07 06:20:07 PM PDT 24
Finished Jun 07 06:20:09 PM PDT 24
Peak memory 200168 kb
Host smart-43d34dab-ae26-406a-b9d7-6bc353503569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935351453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3935351453
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1303465520
Short name T543
Test name
Test status
Simulation time 1715551421 ps
CPU time 6.39 seconds
Started Jun 07 06:20:15 PM PDT 24
Finished Jun 07 06:20:22 PM PDT 24
Peak memory 200460 kb
Host smart-b0d96cb0-f544-4989-9d75-aea9547ec82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303465520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1303465520
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3641693018
Short name T142
Test name
Test status
Simulation time 99188711 ps
CPU time 0.97 seconds
Started Jun 07 06:20:07 PM PDT 24
Finished Jun 07 06:20:08 PM PDT 24
Peak memory 200280 kb
Host smart-e2f5e4be-f5e3-43c1-8ed4-507e916cfe30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641693018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3641693018
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2582264140
Short name T222
Test name
Test status
Simulation time 254326107 ps
CPU time 1.53 seconds
Started Jun 07 06:20:09 PM PDT 24
Finished Jun 07 06:20:11 PM PDT 24
Peak memory 200552 kb
Host smart-df468e8a-d142-44ae-bd11-c6f90412ba4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582264140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2582264140
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.162765550
Short name T276
Test name
Test status
Simulation time 484701460 ps
CPU time 2.49 seconds
Started Jun 07 06:20:09 PM PDT 24
Finished Jun 07 06:20:12 PM PDT 24
Peak memory 200560 kb
Host smart-80bcd839-dbb1-4fbe-bf2f-568bf56c76bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162765550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.162765550
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.1441937712
Short name T189
Test name
Test status
Simulation time 262657325 ps
CPU time 1.83 seconds
Started Jun 07 06:20:13 PM PDT 24
Finished Jun 07 06:20:15 PM PDT 24
Peak memory 200372 kb
Host smart-d7de6541-f9b7-44d7-9b56-912946ae3e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441937712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1441937712
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1949982023
Short name T266
Test name
Test status
Simulation time 106107047 ps
CPU time 0.9 seconds
Started Jun 07 06:20:15 PM PDT 24
Finished Jun 07 06:20:17 PM PDT 24
Peak memory 200268 kb
Host smart-d89f58af-26b7-44f2-8fc3-e317292db176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949982023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1949982023
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3501057593
Short name T430
Test name
Test status
Simulation time 84993984 ps
CPU time 0.81 seconds
Started Jun 07 06:20:14 PM PDT 24
Finished Jun 07 06:20:15 PM PDT 24
Peak memory 200152 kb
Host smart-8b59600a-c653-41d0-9aa4-ba6535ba8712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501057593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3501057593
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3059267664
Short name T25
Test name
Test status
Simulation time 1893471884 ps
CPU time 6.82 seconds
Started Jun 07 06:20:12 PM PDT 24
Finished Jun 07 06:20:20 PM PDT 24
Peak memory 217356 kb
Host smart-67e204e2-1ac5-46f1-89f4-6ca98d4bd4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059267664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3059267664
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.513820043
Short name T24
Test name
Test status
Simulation time 244569056 ps
CPU time 1.01 seconds
Started Jun 07 06:20:14 PM PDT 24
Finished Jun 07 06:20:15 PM PDT 24
Peak memory 217600 kb
Host smart-c2f2aa98-2196-46a8-9e6e-216f700011ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513820043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.513820043
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.285237310
Short name T408
Test name
Test status
Simulation time 127708322 ps
CPU time 0.82 seconds
Started Jun 07 06:20:10 PM PDT 24
Finished Jun 07 06:20:11 PM PDT 24
Peak memory 200180 kb
Host smart-3daee7d6-c1d3-4c79-81c0-407c843ba49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285237310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.285237310
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.570042585
Short name T310
Test name
Test status
Simulation time 1105370627 ps
CPU time 4.91 seconds
Started Jun 07 06:20:10 PM PDT 24
Finished Jun 07 06:20:15 PM PDT 24
Peak memory 200556 kb
Host smart-34f78767-74d4-4ef0-ac0c-1152cb4118a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570042585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.570042585
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1187487008
Short name T264
Test name
Test status
Simulation time 151239366 ps
CPU time 1.22 seconds
Started Jun 07 06:20:14 PM PDT 24
Finished Jun 07 06:20:16 PM PDT 24
Peak memory 200352 kb
Host smart-2708ec52-9f2e-4cde-b7a5-e3bf964b9702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187487008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1187487008
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.3401354353
Short name T72
Test name
Test status
Simulation time 116325043 ps
CPU time 1.2 seconds
Started Jun 07 06:20:08 PM PDT 24
Finished Jun 07 06:20:09 PM PDT 24
Peak memory 200540 kb
Host smart-709de96f-73fe-4bef-836e-1d0c27aa8b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401354353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3401354353
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.704023039
Short name T41
Test name
Test status
Simulation time 9108438108 ps
CPU time 32.86 seconds
Started Jun 07 06:20:09 PM PDT 24
Finished Jun 07 06:20:43 PM PDT 24
Peak memory 200640 kb
Host smart-246863a1-a51f-46fe-9d83-d30c266520c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704023039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.704023039
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1038411038
Short name T433
Test name
Test status
Simulation time 387041035 ps
CPU time 2.3 seconds
Started Jun 07 06:20:07 PM PDT 24
Finished Jun 07 06:20:10 PM PDT 24
Peak memory 200308 kb
Host smart-270da90a-f542-4b40-a4b3-c7de4a321e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038411038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1038411038
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.2395629215
Short name T504
Test name
Test status
Simulation time 226279635 ps
CPU time 1.5 seconds
Started Jun 07 06:20:13 PM PDT 24
Finished Jun 07 06:20:15 PM PDT 24
Peak memory 200520 kb
Host smart-bb356a0d-7727-4c11-b994-341ba2129fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395629215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2395629215
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3198396788
Short name T169
Test name
Test status
Simulation time 66163748 ps
CPU time 0.78 seconds
Started Jun 07 06:20:07 PM PDT 24
Finished Jun 07 06:20:09 PM PDT 24
Peak memory 200120 kb
Host smart-8f85eac8-f64d-40c2-85cb-83286d190c94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198396788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3198396788
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.4186811749
Short name T32
Test name
Test status
Simulation time 1900885507 ps
CPU time 7.44 seconds
Started Jun 07 06:20:12 PM PDT 24
Finished Jun 07 06:20:20 PM PDT 24
Peak memory 221936 kb
Host smart-55161fb2-f417-4411-979e-106e9029c6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186811749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.4186811749
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2343608834
Short name T157
Test name
Test status
Simulation time 244445384 ps
CPU time 1.13 seconds
Started Jun 07 06:20:13 PM PDT 24
Finished Jun 07 06:20:14 PM PDT 24
Peak memory 217580 kb
Host smart-67db89f1-24c6-4192-aca5-0c39a5cc3902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343608834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2343608834
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1369802139
Short name T534
Test name
Test status
Simulation time 161235862 ps
CPU time 0.81 seconds
Started Jun 07 06:20:06 PM PDT 24
Finished Jun 07 06:20:07 PM PDT 24
Peak memory 200108 kb
Host smart-31e3ea16-cbab-404b-b7a8-25a099bf2032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369802139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1369802139
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2515752598
Short name T366
Test name
Test status
Simulation time 1397964253 ps
CPU time 5.66 seconds
Started Jun 07 06:20:13 PM PDT 24
Finished Jun 07 06:20:19 PM PDT 24
Peak memory 200520 kb
Host smart-f117744d-443e-428a-9c18-3ecd82af9664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515752598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2515752598
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1260816747
Short name T182
Test name
Test status
Simulation time 105939500 ps
CPU time 0.99 seconds
Started Jun 07 06:20:09 PM PDT 24
Finished Jun 07 06:20:11 PM PDT 24
Peak memory 200324 kb
Host smart-b6003511-8db0-46b8-aa01-e1a62e6b5ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260816747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1260816747
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2062427275
Short name T214
Test name
Test status
Simulation time 255035578 ps
CPU time 1.5 seconds
Started Jun 07 06:20:09 PM PDT 24
Finished Jun 07 06:20:11 PM PDT 24
Peak memory 200540 kb
Host smart-27e29c4a-139a-4e1a-804d-31cdc162c028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062427275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2062427275
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.1096598588
Short name T413
Test name
Test status
Simulation time 7383510008 ps
CPU time 25.01 seconds
Started Jun 07 06:20:13 PM PDT 24
Finished Jun 07 06:20:39 PM PDT 24
Peak memory 200636 kb
Host smart-0e682586-e334-4709-aff8-d71b09c5bc03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096598588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1096598588
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.414716246
Short name T312
Test name
Test status
Simulation time 435125264 ps
CPU time 2.67 seconds
Started Jun 07 06:20:15 PM PDT 24
Finished Jun 07 06:20:18 PM PDT 24
Peak memory 200328 kb
Host smart-d2ed1e97-b8cf-41b3-82a2-13216de01371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414716246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.414716246
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.4014060877
Short name T154
Test name
Test status
Simulation time 64689075 ps
CPU time 0.9 seconds
Started Jun 07 06:20:11 PM PDT 24
Finished Jun 07 06:20:12 PM PDT 24
Peak memory 200352 kb
Host smart-a4c6c7a9-3f93-467a-afc3-2607a9d34bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014060877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.4014060877
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.502556220
Short name T355
Test name
Test status
Simulation time 64909106 ps
CPU time 0.77 seconds
Started Jun 07 06:20:11 PM PDT 24
Finished Jun 07 06:20:12 PM PDT 24
Peak memory 200088 kb
Host smart-0b3f82bc-a41b-4808-b66d-08cdf2fd04cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502556220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.502556220
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.4254861248
Short name T173
Test name
Test status
Simulation time 244444620 ps
CPU time 1.15 seconds
Started Jun 07 06:20:13 PM PDT 24
Finished Jun 07 06:20:14 PM PDT 24
Peak memory 217616 kb
Host smart-6ef7e13f-f493-44ef-829e-bfab544a9383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254861248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.4254861248
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.4276879319
Short name T353
Test name
Test status
Simulation time 200157792 ps
CPU time 0.95 seconds
Started Jun 07 06:20:09 PM PDT 24
Finished Jun 07 06:20:10 PM PDT 24
Peak memory 200164 kb
Host smart-ec67e45b-04bf-45c1-a44b-669106dcf451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276879319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.4276879319
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1870981670
Short name T207
Test name
Test status
Simulation time 918195025 ps
CPU time 4.5 seconds
Started Jun 07 06:20:12 PM PDT 24
Finished Jun 07 06:20:17 PM PDT 24
Peak memory 200524 kb
Host smart-58bce7b4-51b8-4034-b1e8-57048abd9357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870981670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1870981670
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3158822060
Short name T466
Test name
Test status
Simulation time 100613158 ps
CPU time 1.02 seconds
Started Jun 07 06:20:13 PM PDT 24
Finished Jun 07 06:20:14 PM PDT 24
Peak memory 200348 kb
Host smart-82dd6e78-1bb3-4e9f-8a84-ab31b4582fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158822060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3158822060
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2940534883
Short name T309
Test name
Test status
Simulation time 193113413 ps
CPU time 1.43 seconds
Started Jun 07 06:20:11 PM PDT 24
Finished Jun 07 06:20:12 PM PDT 24
Peak memory 200512 kb
Host smart-62d5bdf4-ece2-4397-8fb3-70a11affba64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940534883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2940534883
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.72403772
Short name T272
Test name
Test status
Simulation time 1879218762 ps
CPU time 9.21 seconds
Started Jun 07 06:20:14 PM PDT 24
Finished Jun 07 06:20:23 PM PDT 24
Peak memory 200520 kb
Host smart-7f5202a9-7068-4bac-ac5e-7eaaf3698f07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72403772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.72403772
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3879831873
Short name T172
Test name
Test status
Simulation time 355780548 ps
CPU time 2.58 seconds
Started Jun 07 06:20:11 PM PDT 24
Finished Jun 07 06:20:14 PM PDT 24
Peak memory 200284 kb
Host smart-bf816a47-d4e6-4e38-b0a2-ca829cb7502f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879831873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3879831873
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2047332726
Short name T325
Test name
Test status
Simulation time 250746044 ps
CPU time 1.48 seconds
Started Jun 07 06:20:10 PM PDT 24
Finished Jun 07 06:20:12 PM PDT 24
Peak memory 200532 kb
Host smart-bf93ea6d-4c3b-4e7e-8ddd-235fa80a3a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047332726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2047332726
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2404142123
Short name T491
Test name
Test status
Simulation time 71647496 ps
CPU time 0.76 seconds
Started Jun 07 06:20:17 PM PDT 24
Finished Jun 07 06:20:18 PM PDT 24
Peak memory 200084 kb
Host smart-0fd43c12-c444-489b-9ae3-b3a8e5bc27a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404142123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2404142123
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1238777004
Short name T338
Test name
Test status
Simulation time 1227082176 ps
CPU time 5.52 seconds
Started Jun 07 06:20:17 PM PDT 24
Finished Jun 07 06:20:23 PM PDT 24
Peak memory 218076 kb
Host smart-b2b2f99a-451b-4c94-ba08-6a669a3d9c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238777004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1238777004
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.182739142
Short name T195
Test name
Test status
Simulation time 243742923 ps
CPU time 1.12 seconds
Started Jun 07 06:20:18 PM PDT 24
Finished Jun 07 06:20:19 PM PDT 24
Peak memory 217576 kb
Host smart-828b6812-28c5-4729-ba2d-384349f0a7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182739142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.182739142
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2328668114
Short name T16
Test name
Test status
Simulation time 77234360 ps
CPU time 0.74 seconds
Started Jun 07 06:20:17 PM PDT 24
Finished Jun 07 06:20:18 PM PDT 24
Peak memory 200132 kb
Host smart-0e1ac9c7-233f-4cac-be14-5e092f0d8610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328668114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2328668114
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3247514032
Short name T437
Test name
Test status
Simulation time 1020791588 ps
CPU time 4.96 seconds
Started Jun 07 06:20:17 PM PDT 24
Finished Jun 07 06:20:22 PM PDT 24
Peak memory 200536 kb
Host smart-bef1abba-9509-469a-a20f-e4e6b140ed4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247514032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3247514032
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1249683347
Short name T505
Test name
Test status
Simulation time 171236238 ps
CPU time 1.14 seconds
Started Jun 07 06:20:16 PM PDT 24
Finished Jun 07 06:20:17 PM PDT 24
Peak memory 200356 kb
Host smart-36af34f4-bacb-4c35-8d52-9162597ae374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249683347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1249683347
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1580149247
Short name T82
Test name
Test status
Simulation time 246028466 ps
CPU time 1.43 seconds
Started Jun 07 06:20:12 PM PDT 24
Finished Jun 07 06:20:14 PM PDT 24
Peak memory 200560 kb
Host smart-20272ca7-2512-4ab4-9aea-344797f3a2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580149247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1580149247
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3194523159
Short name T273
Test name
Test status
Simulation time 14994570560 ps
CPU time 47.86 seconds
Started Jun 07 06:20:17 PM PDT 24
Finished Jun 07 06:21:13 PM PDT 24
Peak memory 200684 kb
Host smart-d0d3936f-542a-4fdd-a846-c82cc6810157
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194523159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3194523159
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.1035743263
Short name T212
Test name
Test status
Simulation time 119108295 ps
CPU time 1.49 seconds
Started Jun 07 06:20:16 PM PDT 24
Finished Jun 07 06:20:19 PM PDT 24
Peak memory 200284 kb
Host smart-a648373d-556d-42a0-9096-6865f0c20f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035743263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.1035743263
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2455661235
Short name T194
Test name
Test status
Simulation time 161025353 ps
CPU time 1.26 seconds
Started Jun 07 06:20:15 PM PDT 24
Finished Jun 07 06:20:17 PM PDT 24
Peak memory 200436 kb
Host smart-44244ef0-eb6c-43db-b578-9b8ba5fa5b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455661235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2455661235
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.529169847
Short name T525
Test name
Test status
Simulation time 72166348 ps
CPU time 0.78 seconds
Started Jun 07 06:20:16 PM PDT 24
Finished Jun 07 06:20:18 PM PDT 24
Peak memory 200144 kb
Host smart-df8c70ac-2285-448b-a26e-46b2b179e6f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529169847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.529169847
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1921134131
Short name T432
Test name
Test status
Simulation time 1229286678 ps
CPU time 5.53 seconds
Started Jun 07 06:20:14 PM PDT 24
Finished Jun 07 06:20:20 PM PDT 24
Peak memory 221872 kb
Host smart-5670ae44-b6d3-4e58-aa13-9e3ad3b6670f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921134131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1921134131
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.537027575
Short name T455
Test name
Test status
Simulation time 243913476 ps
CPU time 1.08 seconds
Started Jun 07 06:20:17 PM PDT 24
Finished Jun 07 06:20:19 PM PDT 24
Peak memory 217568 kb
Host smart-491aa155-0552-4ac1-8d29-fc6cf0a8bf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537027575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.537027575
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2995833897
Short name T15
Test name
Test status
Simulation time 211083740 ps
CPU time 0.97 seconds
Started Jun 07 06:20:16 PM PDT 24
Finished Jun 07 06:20:18 PM PDT 24
Peak memory 200176 kb
Host smart-07be6d52-b254-42f4-8bc8-9a92acd48174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995833897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2995833897
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2376165361
Short name T286
Test name
Test status
Simulation time 1058248996 ps
CPU time 4.92 seconds
Started Jun 07 06:20:16 PM PDT 24
Finished Jun 07 06:20:21 PM PDT 24
Peak memory 200484 kb
Host smart-5fa33f05-e286-4f5c-862a-bed820571b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376165361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2376165361
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1365790697
Short name T180
Test name
Test status
Simulation time 97950332 ps
CPU time 1.04 seconds
Started Jun 07 06:20:18 PM PDT 24
Finished Jun 07 06:20:19 PM PDT 24
Peak memory 200164 kb
Host smart-7bedacf7-f85e-475e-8380-8bdb8246a85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365790697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1365790697
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.3905065500
Short name T131
Test name
Test status
Simulation time 256280547 ps
CPU time 1.52 seconds
Started Jun 07 06:20:18 PM PDT 24
Finished Jun 07 06:20:20 PM PDT 24
Peak memory 200528 kb
Host smart-c4250fbb-8a5d-48b3-baaf-718b2126e463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905065500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3905065500
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2724021689
Short name T101
Test name
Test status
Simulation time 3217589991 ps
CPU time 11.05 seconds
Started Jun 07 06:20:19 PM PDT 24
Finished Jun 07 06:20:30 PM PDT 24
Peak memory 200680 kb
Host smart-4b2d3d27-8e7c-48dc-8cd7-616a0dae483a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724021689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2724021689
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.849477469
Short name T468
Test name
Test status
Simulation time 142908954 ps
CPU time 1.78 seconds
Started Jun 07 06:20:17 PM PDT 24
Finished Jun 07 06:20:19 PM PDT 24
Peak memory 208548 kb
Host smart-00fb908f-05e8-4eb0-97f5-f1885d812e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849477469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.849477469
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.668346427
Short name T233
Test name
Test status
Simulation time 191610071 ps
CPU time 1.26 seconds
Started Jun 07 06:20:18 PM PDT 24
Finished Jun 07 06:20:20 PM PDT 24
Peak memory 200300 kb
Host smart-b451762b-0776-465f-ac4b-306c6363a671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668346427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.668346427
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.4140993000
Short name T175
Test name
Test status
Simulation time 58821675 ps
CPU time 0.72 seconds
Started Jun 07 06:20:16 PM PDT 24
Finished Jun 07 06:20:17 PM PDT 24
Peak memory 200144 kb
Host smart-b272c95a-dde9-4670-b3ba-239557ccc91f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140993000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.4140993000
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1806734645
Short name T311
Test name
Test status
Simulation time 1226746499 ps
CPU time 5.8 seconds
Started Jun 07 06:20:16 PM PDT 24
Finished Jun 07 06:20:22 PM PDT 24
Peak memory 216940 kb
Host smart-cc94ba39-7702-4656-a9eb-e2743a410750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806734645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1806734645
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.397908925
Short name T399
Test name
Test status
Simulation time 244857624 ps
CPU time 1.15 seconds
Started Jun 07 06:20:17 PM PDT 24
Finished Jun 07 06:20:19 PM PDT 24
Peak memory 217484 kb
Host smart-59196aee-49df-4630-bbcc-08efae1988bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397908925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.397908925
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.1161053967
Short name T17
Test name
Test status
Simulation time 193112625 ps
CPU time 0.93 seconds
Started Jun 07 06:20:16 PM PDT 24
Finished Jun 07 06:20:17 PM PDT 24
Peak memory 200092 kb
Host smart-c312e4a5-73f9-489d-8d75-cd02be786295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161053967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.1161053967
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.500303834
Short name T129
Test name
Test status
Simulation time 1922912913 ps
CPU time 8.01 seconds
Started Jun 07 06:20:17 PM PDT 24
Finished Jun 07 06:20:25 PM PDT 24
Peak memory 200712 kb
Host smart-d0dcb5f0-32a9-4c3b-8e93-b69af5d5e609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500303834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.500303834
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3687159959
Short name T381
Test name
Test status
Simulation time 189778523 ps
CPU time 1.2 seconds
Started Jun 07 06:20:16 PM PDT 24
Finished Jun 07 06:20:17 PM PDT 24
Peak memory 200268 kb
Host smart-626f24bf-1461-4ddc-96af-d9cf6062b9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687159959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3687159959
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2225994559
Short name T215
Test name
Test status
Simulation time 129458132 ps
CPU time 1.19 seconds
Started Jun 07 06:20:15 PM PDT 24
Finished Jun 07 06:20:17 PM PDT 24
Peak memory 200492 kb
Host smart-2dd38812-6f78-4366-8117-75bcb845af36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225994559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2225994559
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3056347984
Short name T256
Test name
Test status
Simulation time 2303792272 ps
CPU time 12.39 seconds
Started Jun 07 06:20:18 PM PDT 24
Finished Jun 07 06:20:32 PM PDT 24
Peak memory 208860 kb
Host smart-3620855b-1212-4d6e-b61e-548d7b69d2d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056347984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3056347984
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1393336559
Short name T426
Test name
Test status
Simulation time 114783813 ps
CPU time 1.59 seconds
Started Jun 07 06:20:17 PM PDT 24
Finished Jun 07 06:20:19 PM PDT 24
Peak memory 200336 kb
Host smart-35cab76f-a6c6-4a94-8b9b-ee4f1fdee46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393336559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1393336559
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1428321306
Short name T388
Test name
Test status
Simulation time 294999045 ps
CPU time 1.5 seconds
Started Jun 07 06:20:16 PM PDT 24
Finished Jun 07 06:20:18 PM PDT 24
Peak memory 200500 kb
Host smart-879d23e7-47f0-4499-99f6-ca9b56c4236b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428321306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1428321306
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.774003291
Short name T343
Test name
Test status
Simulation time 86612600 ps
CPU time 0.86 seconds
Started Jun 07 06:20:25 PM PDT 24
Finished Jun 07 06:20:26 PM PDT 24
Peak memory 200116 kb
Host smart-8cb39e77-4d3b-48cb-9e5d-0e84164390b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774003291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.774003291
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1767494255
Short name T456
Test name
Test status
Simulation time 2187209154 ps
CPU time 8.25 seconds
Started Jun 07 06:20:19 PM PDT 24
Finished Jun 07 06:20:28 PM PDT 24
Peak memory 217084 kb
Host smart-e62afe80-f427-4c28-a06d-fdc2a60db125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767494255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1767494255
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3933545136
Short name T171
Test name
Test status
Simulation time 244157352 ps
CPU time 1.12 seconds
Started Jun 07 06:20:27 PM PDT 24
Finished Jun 07 06:20:29 PM PDT 24
Peak memory 217520 kb
Host smart-d529977c-1eb9-4ecc-9a27-c4565df8d9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933545136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3933545136
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3636972770
Short name T235
Test name
Test status
Simulation time 114328733 ps
CPU time 0.86 seconds
Started Jun 07 06:20:15 PM PDT 24
Finished Jun 07 06:20:16 PM PDT 24
Peak memory 200132 kb
Host smart-4399bb4c-a024-4930-9379-5d156cdfcba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636972770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3636972770
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.688052628
Short name T330
Test name
Test status
Simulation time 1384218526 ps
CPU time 5.32 seconds
Started Jun 07 06:20:18 PM PDT 24
Finished Jun 07 06:20:25 PM PDT 24
Peak memory 200576 kb
Host smart-366bf799-4bc6-43be-b708-d60f235ece16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688052628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.688052628
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3967845426
Short name T442
Test name
Test status
Simulation time 98398886 ps
CPU time 1.09 seconds
Started Jun 07 06:20:22 PM PDT 24
Finished Jun 07 06:20:24 PM PDT 24
Peak memory 200496 kb
Host smart-7b137670-fd26-4e13-962e-24aa3e9bbd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967845426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3967845426
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3673177528
Short name T164
Test name
Test status
Simulation time 243779540 ps
CPU time 1.47 seconds
Started Jun 07 06:20:19 PM PDT 24
Finished Jun 07 06:20:21 PM PDT 24
Peak memory 200396 kb
Host smart-ea37455e-5830-4a54-ae88-5181d65a6732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673177528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3673177528
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2351352949
Short name T130
Test name
Test status
Simulation time 5592909589 ps
CPU time 20.04 seconds
Started Jun 07 06:20:26 PM PDT 24
Finished Jun 07 06:20:47 PM PDT 24
Peak memory 210536 kb
Host smart-ba72ce33-85bc-451b-a893-405b7f777b97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351352949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2351352949
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2526873415
Short name T348
Test name
Test status
Simulation time 343334523 ps
CPU time 2.44 seconds
Started Jun 07 06:20:19 PM PDT 24
Finished Jun 07 06:20:22 PM PDT 24
Peak memory 200324 kb
Host smart-0c9f67e1-9bb9-4ee1-b2bc-4884cb1f1413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526873415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2526873415
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.4174350442
Short name T490
Test name
Test status
Simulation time 218449412 ps
CPU time 1.32 seconds
Started Jun 07 06:20:19 PM PDT 24
Finished Jun 07 06:20:21 PM PDT 24
Peak memory 200304 kb
Host smart-7dae2e91-0657-49fb-b861-829cd759e68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174350442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.4174350442
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1205127717
Short name T384
Test name
Test status
Simulation time 78313205 ps
CPU time 0.79 seconds
Started Jun 07 06:19:30 PM PDT 24
Finished Jun 07 06:19:31 PM PDT 24
Peak memory 200152 kb
Host smart-660beb7d-d6f7-4523-8490-178b17187826
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205127717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1205127717
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.804878920
Short name T269
Test name
Test status
Simulation time 245290833 ps
CPU time 1.04 seconds
Started Jun 07 06:19:32 PM PDT 24
Finished Jun 07 06:19:33 PM PDT 24
Peak memory 217464 kb
Host smart-2c1c4f1c-8b33-4752-b26b-3bb4cfec0da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804878920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.804878920
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3323032117
Short name T265
Test name
Test status
Simulation time 206820081 ps
CPU time 0.89 seconds
Started Jun 07 06:19:28 PM PDT 24
Finished Jun 07 06:19:29 PM PDT 24
Peak memory 200116 kb
Host smart-f756ce36-0aec-469d-a2b6-33e4123ee69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323032117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3323032117
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2495512576
Short name T6
Test name
Test status
Simulation time 1220535670 ps
CPU time 4.72 seconds
Started Jun 07 06:19:31 PM PDT 24
Finished Jun 07 06:19:36 PM PDT 24
Peak memory 200540 kb
Host smart-6c76470a-3829-4f1b-a0c7-0986062c0af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495512576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2495512576
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1816739528
Short name T69
Test name
Test status
Simulation time 8389254976 ps
CPU time 13.12 seconds
Started Jun 07 06:19:31 PM PDT 24
Finished Jun 07 06:19:45 PM PDT 24
Peak memory 217360 kb
Host smart-41a0c078-18ad-47e0-a490-dc98a63c9eb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816739528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1816739528
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.505657905
Short name T205
Test name
Test status
Simulation time 172292141 ps
CPU time 1.12 seconds
Started Jun 07 06:19:35 PM PDT 24
Finished Jun 07 06:19:36 PM PDT 24
Peak memory 200368 kb
Host smart-f3da7fba-33c1-4582-9bd1-af4e5d0d4152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505657905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.505657905
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.3262727746
Short name T240
Test name
Test status
Simulation time 201328854 ps
CPU time 1.39 seconds
Started Jun 07 06:19:27 PM PDT 24
Finished Jun 07 06:19:29 PM PDT 24
Peak memory 200384 kb
Host smart-3c16f57a-e958-4278-b3b1-52dc243ef5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262727746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3262727746
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3028090336
Short name T444
Test name
Test status
Simulation time 3591970296 ps
CPU time 15.39 seconds
Started Jun 07 06:19:30 PM PDT 24
Finished Jun 07 06:19:45 PM PDT 24
Peak memory 200672 kb
Host smart-56d403ad-3c67-4889-a30f-f8f1ec72e6c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028090336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3028090336
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2761843105
Short name T302
Test name
Test status
Simulation time 140165557 ps
CPU time 1.72 seconds
Started Jun 07 06:19:32 PM PDT 24
Finished Jun 07 06:19:34 PM PDT 24
Peak memory 200260 kb
Host smart-2def6e4d-ec31-42e3-a31e-9224c0aff458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761843105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2761843105
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.38424559
Short name T320
Test name
Test status
Simulation time 214245840 ps
CPU time 1.31 seconds
Started Jun 07 06:19:29 PM PDT 24
Finished Jun 07 06:19:31 PM PDT 24
Peak memory 200356 kb
Host smart-b75ca339-a431-432c-9eae-a568219c375f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38424559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.38424559
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3769541593
Short name T147
Test name
Test status
Simulation time 61704261 ps
CPU time 0.77 seconds
Started Jun 07 06:20:25 PM PDT 24
Finished Jun 07 06:20:27 PM PDT 24
Peak memory 200164 kb
Host smart-a0236968-8ea4-4655-9953-dab885e26960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769541593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3769541593
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.28836984
Short name T247
Test name
Test status
Simulation time 2337880323 ps
CPU time 8.31 seconds
Started Jun 07 06:20:26 PM PDT 24
Finished Jun 07 06:20:35 PM PDT 24
Peak memory 221880 kb
Host smart-d73429e4-95f1-4e0e-9a1a-b05310189fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28836984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.28836984
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1353284539
Short name T451
Test name
Test status
Simulation time 244318483 ps
CPU time 1.1 seconds
Started Jun 07 06:20:26 PM PDT 24
Finished Jun 07 06:20:28 PM PDT 24
Peak memory 217624 kb
Host smart-b0fa8a8b-7812-42c7-8b86-0d2aae2715e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353284539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1353284539
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2703354506
Short name T239
Test name
Test status
Simulation time 207913383 ps
CPU time 0.98 seconds
Started Jun 07 06:20:27 PM PDT 24
Finished Jun 07 06:20:29 PM PDT 24
Peak memory 200136 kb
Host smart-2646f626-1288-43e6-b625-afaeffbd6cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703354506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2703354506
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2381319337
Short name T336
Test name
Test status
Simulation time 1321868480 ps
CPU time 5.82 seconds
Started Jun 07 06:20:29 PM PDT 24
Finished Jun 07 06:20:35 PM PDT 24
Peak memory 200544 kb
Host smart-a5ab62e5-1f5b-47f0-bd6e-a40f1911def9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381319337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2381319337
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.296260285
Short name T217
Test name
Test status
Simulation time 105040891 ps
CPU time 0.97 seconds
Started Jun 07 06:20:27 PM PDT 24
Finished Jun 07 06:20:28 PM PDT 24
Peak memory 200364 kb
Host smart-3ef907ae-6d34-4c6d-a6ed-3bee9a669e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296260285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.296260285
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2669434638
Short name T407
Test name
Test status
Simulation time 124996737 ps
CPU time 1.29 seconds
Started Jun 07 06:20:25 PM PDT 24
Finished Jun 07 06:20:27 PM PDT 24
Peak memory 200528 kb
Host smart-12f825c5-7aff-445f-8f90-54d8a717fde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669434638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2669434638
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.4110650480
Short name T261
Test name
Test status
Simulation time 9399069437 ps
CPU time 46.34 seconds
Started Jun 07 06:20:27 PM PDT 24
Finished Jun 07 06:21:14 PM PDT 24
Peak memory 209008 kb
Host smart-ffdbd790-30e5-4946-a571-9e149254043f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110650480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.4110650480
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3609697463
Short name T487
Test name
Test status
Simulation time 116070133 ps
CPU time 1.52 seconds
Started Jun 07 06:20:30 PM PDT 24
Finished Jun 07 06:20:32 PM PDT 24
Peak memory 200344 kb
Host smart-e47683c3-269e-45cc-9d0c-e54cb906eed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609697463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3609697463
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3118678443
Short name T168
Test name
Test status
Simulation time 99452771 ps
CPU time 1 seconds
Started Jun 07 06:20:28 PM PDT 24
Finished Jun 07 06:20:29 PM PDT 24
Peak memory 200268 kb
Host smart-f8473519-0a81-400d-8844-70b08562ab1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118678443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3118678443
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.452639559
Short name T314
Test name
Test status
Simulation time 78525226 ps
CPU time 0.83 seconds
Started Jun 07 06:20:25 PM PDT 24
Finished Jun 07 06:20:27 PM PDT 24
Peak memory 200168 kb
Host smart-72ddba0d-bca0-4be5-90c6-4d658dc31ab0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452639559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.452639559
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1542061842
Short name T27
Test name
Test status
Simulation time 1226409694 ps
CPU time 5.3 seconds
Started Jun 07 06:20:28 PM PDT 24
Finished Jun 07 06:20:34 PM PDT 24
Peak memory 217984 kb
Host smart-ba0ee58b-5b79-4cf6-bb6a-4343099cdee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542061842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1542061842
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.548136973
Short name T151
Test name
Test status
Simulation time 243739359 ps
CPU time 1.19 seconds
Started Jun 07 06:20:41 PM PDT 24
Finished Jun 07 06:20:42 PM PDT 24
Peak memory 217576 kb
Host smart-31214025-4f7c-4984-99cd-c548bfae2356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548136973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.548136973
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.3193998139
Short name T292
Test name
Test status
Simulation time 96980804 ps
CPU time 0.75 seconds
Started Jun 07 06:20:27 PM PDT 24
Finished Jun 07 06:20:28 PM PDT 24
Peak memory 200148 kb
Host smart-5cf207ef-2e9a-43d0-9feb-79f1eb5e71ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193998139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3193998139
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3138999846
Short name T3
Test name
Test status
Simulation time 1447925985 ps
CPU time 5.96 seconds
Started Jun 07 06:20:26 PM PDT 24
Finished Jun 07 06:20:32 PM PDT 24
Peak memory 200500 kb
Host smart-efced64b-26df-4f91-912e-30fa9defa438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138999846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3138999846
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.803640887
Short name T420
Test name
Test status
Simulation time 180280594 ps
CPU time 1.18 seconds
Started Jun 07 06:20:27 PM PDT 24
Finished Jun 07 06:20:28 PM PDT 24
Peak memory 200300 kb
Host smart-6a40ec6f-f482-4e1b-a82a-50b68560d5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803640887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.803640887
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1769800331
Short name T186
Test name
Test status
Simulation time 127902479 ps
CPU time 1.19 seconds
Started Jun 07 06:20:27 PM PDT 24
Finished Jun 07 06:20:29 PM PDT 24
Peak memory 200460 kb
Host smart-d44a3a77-50fa-4a71-8dde-17cc180acb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769800331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1769800331
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3237428019
Short name T230
Test name
Test status
Simulation time 7328884038 ps
CPU time 33.48 seconds
Started Jun 07 06:20:29 PM PDT 24
Finished Jun 07 06:21:03 PM PDT 24
Peak memory 208860 kb
Host smart-edb873e6-20dd-4f51-9975-89c3a542a3f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237428019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3237428019
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2404220838
Short name T251
Test name
Test status
Simulation time 157069627 ps
CPU time 1.85 seconds
Started Jun 07 06:20:27 PM PDT 24
Finished Jun 07 06:20:30 PM PDT 24
Peak memory 200336 kb
Host smart-abf88bc4-a5c5-46a3-a971-134d4108ac6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404220838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2404220838
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.851743035
Short name T156
Test name
Test status
Simulation time 161279015 ps
CPU time 1.07 seconds
Started Jun 07 06:20:26 PM PDT 24
Finished Jun 07 06:20:28 PM PDT 24
Peak memory 200320 kb
Host smart-4a763b50-65fb-4cbd-b3c2-e4c18a773bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851743035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.851743035
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2522710122
Short name T294
Test name
Test status
Simulation time 53982109 ps
CPU time 0.72 seconds
Started Jun 07 06:20:27 PM PDT 24
Finished Jun 07 06:20:28 PM PDT 24
Peak memory 200116 kb
Host smart-dfcb14a5-9d68-47a3-a479-afbf85e6eb49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522710122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2522710122
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2959403507
Short name T54
Test name
Test status
Simulation time 1226915159 ps
CPU time 5.87 seconds
Started Jun 07 06:20:30 PM PDT 24
Finished Jun 07 06:20:36 PM PDT 24
Peak memory 217944 kb
Host smart-8fd500e4-ae6a-44e1-b061-03a5e35b026f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959403507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2959403507
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1715341716
Short name T315
Test name
Test status
Simulation time 243956877 ps
CPU time 1.13 seconds
Started Jun 07 06:20:26 PM PDT 24
Finished Jun 07 06:20:28 PM PDT 24
Peak memory 217572 kb
Host smart-f38c701a-7c5b-4113-aa17-fda870c988df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715341716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1715341716
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.683550939
Short name T403
Test name
Test status
Simulation time 154566914 ps
CPU time 0.83 seconds
Started Jun 07 06:20:24 PM PDT 24
Finished Jun 07 06:20:26 PM PDT 24
Peak memory 200180 kb
Host smart-8a7822e8-c11a-442f-b524-2ca22e05184d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683550939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.683550939
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.4204719912
Short name T224
Test name
Test status
Simulation time 876752266 ps
CPU time 4.17 seconds
Started Jun 07 06:20:26 PM PDT 24
Finished Jun 07 06:20:30 PM PDT 24
Peak memory 200540 kb
Host smart-00dc4771-fcb8-432d-ba49-adda0a0af9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204719912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.4204719912
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2121486278
Short name T40
Test name
Test status
Simulation time 160189213 ps
CPU time 1.21 seconds
Started Jun 07 06:20:25 PM PDT 24
Finished Jun 07 06:20:27 PM PDT 24
Peak memory 200440 kb
Host smart-02070257-60ac-4c8f-a1cc-8a35919f8299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121486278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2121486278
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.887929212
Short name T155
Test name
Test status
Simulation time 250704868 ps
CPU time 1.57 seconds
Started Jun 07 06:20:30 PM PDT 24
Finished Jun 07 06:20:32 PM PDT 24
Peak memory 200564 kb
Host smart-21d0570b-ac6c-4e17-b08f-d4bc535e82df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887929212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.887929212
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.55796045
Short name T415
Test name
Test status
Simulation time 8654932244 ps
CPU time 39.88 seconds
Started Jun 07 06:20:26 PM PDT 24
Finished Jun 07 06:21:07 PM PDT 24
Peak memory 200676 kb
Host smart-cef09b97-ee6d-493a-a9ff-cb2141cc736f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55796045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.55796045
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.1148968348
Short name T354
Test name
Test status
Simulation time 485044318 ps
CPU time 2.56 seconds
Started Jun 07 06:20:28 PM PDT 24
Finished Jun 07 06:20:31 PM PDT 24
Peak memory 200096 kb
Host smart-24c5c2ef-58d9-4133-b0ec-9d137cd05874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148968348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1148968348
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.376805760
Short name T540
Test name
Test status
Simulation time 150071342 ps
CPU time 1.14 seconds
Started Jun 07 06:20:30 PM PDT 24
Finished Jun 07 06:20:32 PM PDT 24
Peak memory 200348 kb
Host smart-77d09e12-87e2-46cb-8e46-ed0acd3a619a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376805760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.376805760
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2770302498
Short name T282
Test name
Test status
Simulation time 70164355 ps
CPU time 0.7 seconds
Started Jun 07 06:20:26 PM PDT 24
Finished Jun 07 06:20:27 PM PDT 24
Peak memory 200168 kb
Host smart-97188bd6-8cd1-48e2-9d2c-c4ca104731e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770302498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2770302498
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2930818612
Short name T46
Test name
Test status
Simulation time 1898467772 ps
CPU time 7.75 seconds
Started Jun 07 06:20:28 PM PDT 24
Finished Jun 07 06:20:37 PM PDT 24
Peak memory 217476 kb
Host smart-31217c00-4038-401f-b940-2d74b5756e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930818612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2930818612
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2914560560
Short name T374
Test name
Test status
Simulation time 245234533 ps
CPU time 1.13 seconds
Started Jun 07 06:20:24 PM PDT 24
Finished Jun 07 06:20:26 PM PDT 24
Peak memory 217572 kb
Host smart-25cbb62c-5ac2-41d8-a83f-42bf6217a5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914560560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2914560560
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.4155540588
Short name T419
Test name
Test status
Simulation time 91207546 ps
CPU time 0.8 seconds
Started Jun 07 06:20:24 PM PDT 24
Finished Jun 07 06:20:25 PM PDT 24
Peak memory 200148 kb
Host smart-4c16b7d6-46ff-4a71-b77c-f766e810fe17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155540588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.4155540588
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3983579053
Short name T216
Test name
Test status
Simulation time 728780780 ps
CPU time 3.65 seconds
Started Jun 07 06:20:26 PM PDT 24
Finished Jun 07 06:20:30 PM PDT 24
Peak memory 200540 kb
Host smart-4eab92d4-57bc-48c8-bf63-644965f7f3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983579053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3983579053
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1403393038
Short name T417
Test name
Test status
Simulation time 138616568 ps
CPU time 1.07 seconds
Started Jun 07 06:20:29 PM PDT 24
Finished Jun 07 06:20:31 PM PDT 24
Peak memory 200352 kb
Host smart-cb915c7f-acf3-4275-a5bb-de3074670212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403393038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1403393038
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3205726022
Short name T523
Test name
Test status
Simulation time 125153357 ps
CPU time 1.16 seconds
Started Jun 07 06:20:24 PM PDT 24
Finished Jun 07 06:20:25 PM PDT 24
Peak memory 200512 kb
Host smart-6292644d-3438-4fe5-870a-00275f70e4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205726022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3205726022
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.3551267317
Short name T538
Test name
Test status
Simulation time 6206250071 ps
CPU time 29.83 seconds
Started Jun 07 06:20:29 PM PDT 24
Finished Jun 07 06:20:59 PM PDT 24
Peak memory 208864 kb
Host smart-270b2ac7-62b6-484c-b39d-464be48b47fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551267317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3551267317
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3540897374
Short name T522
Test name
Test status
Simulation time 508449423 ps
CPU time 2.54 seconds
Started Jun 07 06:20:26 PM PDT 24
Finished Jun 07 06:20:29 PM PDT 24
Peak memory 200324 kb
Host smart-51442a52-ce40-477b-bca7-8e723e532d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540897374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3540897374
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3862491653
Short name T489
Test name
Test status
Simulation time 152405326 ps
CPU time 1.29 seconds
Started Jun 07 06:20:27 PM PDT 24
Finished Jun 07 06:20:29 PM PDT 24
Peak memory 200452 kb
Host smart-197eec0c-9c6d-4cb1-8b73-bacdfa536a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862491653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3862491653
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.1351249413
Short name T356
Test name
Test status
Simulation time 74413568 ps
CPU time 0.79 seconds
Started Jun 07 06:20:30 PM PDT 24
Finished Jun 07 06:20:31 PM PDT 24
Peak memory 200172 kb
Host smart-b8963cc2-fba9-4036-948e-e0ff4867bb13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351249413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1351249413
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.2210833843
Short name T299
Test name
Test status
Simulation time 2356591243 ps
CPU time 7.98 seconds
Started Jun 07 06:20:32 PM PDT 24
Finished Jun 07 06:20:40 PM PDT 24
Peak memory 217888 kb
Host smart-69f524df-66b1-4993-b0ef-ddec7e500478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210833843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2210833843
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.4271515953
Short name T220
Test name
Test status
Simulation time 244652793 ps
CPU time 1.1 seconds
Started Jun 07 06:20:30 PM PDT 24
Finished Jun 07 06:20:31 PM PDT 24
Peak memory 217580 kb
Host smart-034920fb-9e74-4094-8c39-f7b999641318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271515953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.4271515953
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.826630476
Short name T485
Test name
Test status
Simulation time 210705281 ps
CPU time 0.91 seconds
Started Jun 07 06:20:28 PM PDT 24
Finished Jun 07 06:20:30 PM PDT 24
Peak memory 199872 kb
Host smart-618e6f1f-faf8-465f-9e43-9ada275569d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826630476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.826630476
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3088958149
Short name T517
Test name
Test status
Simulation time 1065779709 ps
CPU time 5.18 seconds
Started Jun 07 06:20:24 PM PDT 24
Finished Jun 07 06:20:29 PM PDT 24
Peak memory 200520 kb
Host smart-f4602d60-beaf-4fe9-8f85-5ca63c66f95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088958149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3088958149
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3723640545
Short name T358
Test name
Test status
Simulation time 171150718 ps
CPU time 1.24 seconds
Started Jun 07 06:20:36 PM PDT 24
Finished Jun 07 06:20:38 PM PDT 24
Peak memory 200308 kb
Host smart-b9500578-06de-4edf-a6b4-88feae9d5fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723640545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3723640545
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.1066017472
Short name T144
Test name
Test status
Simulation time 117493306 ps
CPU time 1.27 seconds
Started Jun 07 06:20:24 PM PDT 24
Finished Jun 07 06:20:26 PM PDT 24
Peak memory 200520 kb
Host smart-4de3eda5-17a7-4a17-8c4d-f48267c2801f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066017472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1066017472
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3323371908
Short name T132
Test name
Test status
Simulation time 516370456 ps
CPU time 2.92 seconds
Started Jun 07 06:20:43 PM PDT 24
Finished Jun 07 06:20:46 PM PDT 24
Peak memory 200288 kb
Host smart-0c91f210-d7d8-4119-bdde-1c0fc1cd8fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323371908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3323371908
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3469104835
Short name T83
Test name
Test status
Simulation time 127831890 ps
CPU time 1.04 seconds
Started Jun 07 06:20:25 PM PDT 24
Finished Jun 07 06:20:27 PM PDT 24
Peak memory 200336 kb
Host smart-5bebcb1c-1a9e-4f2c-991e-0d3cac421167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469104835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3469104835
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1367390468
Short name T440
Test name
Test status
Simulation time 97907966 ps
CPU time 0.83 seconds
Started Jun 07 06:20:34 PM PDT 24
Finished Jun 07 06:20:35 PM PDT 24
Peak memory 200124 kb
Host smart-da7a831c-df58-4cd1-92d4-5931ee1fc016
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367390468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1367390468
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3719638472
Short name T5
Test name
Test status
Simulation time 1222656321 ps
CPU time 5.55 seconds
Started Jun 07 06:20:29 PM PDT 24
Finished Jun 07 06:20:35 PM PDT 24
Peak memory 217896 kb
Host smart-3d3b1d99-3515-4a3d-8eea-8ea3ffa47d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719638472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3719638472
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1990937014
Short name T393
Test name
Test status
Simulation time 244152058 ps
CPU time 1.05 seconds
Started Jun 07 06:20:29 PM PDT 24
Finished Jun 07 06:20:31 PM PDT 24
Peak memory 217556 kb
Host smart-057007e8-d4d0-402e-8d95-586577ef89a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990937014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1990937014
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1717170460
Short name T21
Test name
Test status
Simulation time 101704794 ps
CPU time 0.79 seconds
Started Jun 07 06:20:30 PM PDT 24
Finished Jun 07 06:20:32 PM PDT 24
Peak memory 200168 kb
Host smart-c5959eff-adaa-40ab-a8c4-e54a2eb522d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717170460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1717170460
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1196380662
Short name T223
Test name
Test status
Simulation time 1198922947 ps
CPU time 4.78 seconds
Started Jun 07 06:20:38 PM PDT 24
Finished Jun 07 06:20:43 PM PDT 24
Peak memory 200576 kb
Host smart-2d2581e1-8c4f-44df-9266-0ebd82563f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196380662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1196380662
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1837082580
Short name T477
Test name
Test status
Simulation time 101945582 ps
CPU time 1.01 seconds
Started Jun 07 06:20:37 PM PDT 24
Finished Jun 07 06:20:38 PM PDT 24
Peak memory 200304 kb
Host smart-8afd889f-f84b-480f-8d06-662593520ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837082580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1837082580
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.481758375
Short name T249
Test name
Test status
Simulation time 11097331127 ps
CPU time 40.01 seconds
Started Jun 07 06:20:27 PM PDT 24
Finished Jun 07 06:21:08 PM PDT 24
Peak memory 208936 kb
Host smart-44e05066-323b-467c-b933-ab20e6ac980c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481758375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.481758375
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2840841973
Short name T422
Test name
Test status
Simulation time 263860580 ps
CPU time 1.54 seconds
Started Jun 07 06:20:34 PM PDT 24
Finished Jun 07 06:20:36 PM PDT 24
Peak memory 200544 kb
Host smart-c5ff2efc-0f9d-496e-a6d8-cb7610855dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840841973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2840841973
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3497802462
Short name T231
Test name
Test status
Simulation time 75697326 ps
CPU time 0.87 seconds
Started Jun 07 06:20:36 PM PDT 24
Finished Jun 07 06:20:37 PM PDT 24
Peak memory 200120 kb
Host smart-c3aa75c2-6c56-462b-80ad-343971fcafb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497802462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3497802462
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.643119577
Short name T450
Test name
Test status
Simulation time 1889915844 ps
CPU time 7.17 seconds
Started Jun 07 06:20:32 PM PDT 24
Finished Jun 07 06:20:40 PM PDT 24
Peak memory 221812 kb
Host smart-683ebad8-4801-4a0b-a41e-59cc98474892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643119577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.643119577
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3360234385
Short name T143
Test name
Test status
Simulation time 244029143 ps
CPU time 1.04 seconds
Started Jun 07 06:20:29 PM PDT 24
Finished Jun 07 06:20:30 PM PDT 24
Peak memory 217608 kb
Host smart-c1252347-ef86-4c9f-8d13-b85994c914d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360234385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3360234385
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1142736133
Short name T18
Test name
Test status
Simulation time 157573359 ps
CPU time 0.85 seconds
Started Jun 07 06:20:30 PM PDT 24
Finished Jun 07 06:20:32 PM PDT 24
Peak memory 200108 kb
Host smart-5098d171-5b1e-458f-9b0d-6c1590c270ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142736133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1142736133
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.321767364
Short name T184
Test name
Test status
Simulation time 1512339287 ps
CPU time 6.62 seconds
Started Jun 07 06:20:36 PM PDT 24
Finished Jun 07 06:20:43 PM PDT 24
Peak memory 200536 kb
Host smart-41251340-a3a9-4867-bf3c-3beb0b51e0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321767364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.321767364
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1609926407
Short name T503
Test name
Test status
Simulation time 154333615 ps
CPU time 1.25 seconds
Started Jun 07 06:20:31 PM PDT 24
Finished Jun 07 06:20:33 PM PDT 24
Peak memory 200352 kb
Host smart-9d905dfb-976f-497b-8998-0e920aaded69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609926407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1609926407
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3452184123
Short name T159
Test name
Test status
Simulation time 194576769 ps
CPU time 1.38 seconds
Started Jun 07 06:20:38 PM PDT 24
Finished Jun 07 06:20:40 PM PDT 24
Peak memory 200536 kb
Host smart-88bafc89-8db3-4aed-bdb7-f61d8748c32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452184123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3452184123
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.952814423
Short name T398
Test name
Test status
Simulation time 200356513 ps
CPU time 1.49 seconds
Started Jun 07 06:20:28 PM PDT 24
Finished Jun 07 06:20:30 PM PDT 24
Peak memory 200424 kb
Host smart-e4b298e7-e3b9-4d0a-bca6-87951ea62fb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952814423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.952814423
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.4045033716
Short name T86
Test name
Test status
Simulation time 141374113 ps
CPU time 1.66 seconds
Started Jun 07 06:20:37 PM PDT 24
Finished Jun 07 06:20:39 PM PDT 24
Peak memory 200360 kb
Host smart-d49b7364-2597-4f24-85f4-3e21d9a8ef3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045033716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.4045033716
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3395201523
Short name T192
Test name
Test status
Simulation time 130906308 ps
CPU time 1.05 seconds
Started Jun 07 06:20:33 PM PDT 24
Finished Jun 07 06:20:34 PM PDT 24
Peak memory 200320 kb
Host smart-028a3526-d867-428c-9a2d-dced1342b42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395201523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3395201523
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.441457199
Short name T211
Test name
Test status
Simulation time 64828156 ps
CPU time 0.82 seconds
Started Jun 07 06:20:34 PM PDT 24
Finished Jun 07 06:20:35 PM PDT 24
Peak memory 200148 kb
Host smart-749b7916-89d5-479f-b09c-d5b74c653db1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441457199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.441457199
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.237492390
Short name T288
Test name
Test status
Simulation time 1227788084 ps
CPU time 5.72 seconds
Started Jun 07 06:20:34 PM PDT 24
Finished Jun 07 06:20:40 PM PDT 24
Peak memory 217980 kb
Host smart-e48ba2fc-15ef-449e-81b5-0bda7b306887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237492390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.237492390
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.26242734
Short name T372
Test name
Test status
Simulation time 243536861 ps
CPU time 1.17 seconds
Started Jun 07 06:20:29 PM PDT 24
Finished Jun 07 06:20:31 PM PDT 24
Peak memory 217608 kb
Host smart-85f555e2-934f-4bfb-9c33-e764e1d712cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26242734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.26242734
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1139619175
Short name T290
Test name
Test status
Simulation time 177621778 ps
CPU time 0.95 seconds
Started Jun 07 06:20:37 PM PDT 24
Finished Jun 07 06:20:39 PM PDT 24
Peak memory 200120 kb
Host smart-08ce1eb6-dd60-4ef2-8672-b8c6b1c51278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139619175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1139619175
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.4226381653
Short name T345
Test name
Test status
Simulation time 2229503196 ps
CPU time 7.62 seconds
Started Jun 07 06:20:31 PM PDT 24
Finished Jun 07 06:20:39 PM PDT 24
Peak memory 200652 kb
Host smart-59319947-a06a-49f4-9053-d08bb4e8a2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226381653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.4226381653
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2785677716
Short name T461
Test name
Test status
Simulation time 111285664 ps
CPU time 1.07 seconds
Started Jun 07 06:20:34 PM PDT 24
Finished Jun 07 06:20:35 PM PDT 24
Peak memory 200304 kb
Host smart-d97c1eaa-b82a-4cc6-afac-bc44f15d71d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785677716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2785677716
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1476244252
Short name T380
Test name
Test status
Simulation time 230996498 ps
CPU time 1.42 seconds
Started Jun 07 06:20:31 PM PDT 24
Finished Jun 07 06:20:33 PM PDT 24
Peak memory 200528 kb
Host smart-b256b3b6-f8dc-487e-9a7e-67e020bfba03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476244252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1476244252
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2332525799
Short name T425
Test name
Test status
Simulation time 2688431013 ps
CPU time 10.23 seconds
Started Jun 07 06:20:35 PM PDT 24
Finished Jun 07 06:20:46 PM PDT 24
Peak memory 208836 kb
Host smart-28acdc21-3b6c-41c9-8260-51adb07b9c47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332525799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2332525799
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3878017785
Short name T334
Test name
Test status
Simulation time 468658649 ps
CPU time 2.57 seconds
Started Jun 07 06:20:31 PM PDT 24
Finished Jun 07 06:20:34 PM PDT 24
Peak memory 200284 kb
Host smart-f86a50e6-e544-4156-8727-a6a3e9ee1eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878017785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3878017785
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2513769384
Short name T177
Test name
Test status
Simulation time 202606757 ps
CPU time 1.3 seconds
Started Jun 07 06:20:37 PM PDT 24
Finished Jun 07 06:20:39 PM PDT 24
Peak memory 200344 kb
Host smart-0976b328-62c8-4c55-89fc-53b8b3dbe758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513769384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2513769384
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.563829880
Short name T510
Test name
Test status
Simulation time 56656854 ps
CPU time 0.73 seconds
Started Jun 07 06:20:35 PM PDT 24
Finished Jun 07 06:20:36 PM PDT 24
Peak memory 200112 kb
Host smart-7e84f6f4-0579-4ef9-bce4-601f2331b98d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563829880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.563829880
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1962267994
Short name T368
Test name
Test status
Simulation time 2350260119 ps
CPU time 8.08 seconds
Started Jun 07 06:20:36 PM PDT 24
Finished Jun 07 06:20:45 PM PDT 24
Peak memory 218140 kb
Host smart-85d5d4ab-de46-4f2c-9a1f-eae6e6ef1f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962267994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1962267994
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.52214255
Short name T321
Test name
Test status
Simulation time 245078628 ps
CPU time 1.09 seconds
Started Jun 07 06:20:36 PM PDT 24
Finished Jun 07 06:20:37 PM PDT 24
Peak memory 217684 kb
Host smart-8b3dd3a4-da8f-4bc6-87c1-32dad9e83310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52214255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.52214255
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2538916689
Short name T443
Test name
Test status
Simulation time 222203121 ps
CPU time 0.9 seconds
Started Jun 07 06:20:34 PM PDT 24
Finished Jun 07 06:20:35 PM PDT 24
Peak memory 200132 kb
Host smart-259cf2a1-9756-4026-be8d-31513f75e2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538916689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2538916689
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3156568971
Short name T289
Test name
Test status
Simulation time 766080213 ps
CPU time 3.99 seconds
Started Jun 07 06:20:35 PM PDT 24
Finished Jun 07 06:20:39 PM PDT 24
Peak memory 200520 kb
Host smart-70af3b34-3ea8-46de-b001-89aad5eb5737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156568971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3156568971
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2845518425
Short name T363
Test name
Test status
Simulation time 180286046 ps
CPU time 1.23 seconds
Started Jun 07 06:20:34 PM PDT 24
Finished Jun 07 06:20:36 PM PDT 24
Peak memory 200332 kb
Host smart-d7c751b4-8edc-4b8a-9351-bf9221d01dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845518425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2845518425
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2134320670
Short name T498
Test name
Test status
Simulation time 119658690 ps
CPU time 1.14 seconds
Started Jun 07 06:20:32 PM PDT 24
Finished Jun 07 06:20:34 PM PDT 24
Peak memory 200464 kb
Host smart-10c5a77d-262d-4c55-bbe4-8323c93613f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134320670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2134320670
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1393303638
Short name T127
Test name
Test status
Simulation time 5562985513 ps
CPU time 19.25 seconds
Started Jun 07 06:20:40 PM PDT 24
Finished Jun 07 06:20:59 PM PDT 24
Peak memory 200568 kb
Host smart-77be924a-9c70-4571-973d-3c7c8f829418
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393303638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1393303638
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.4106010439
Short name T84
Test name
Test status
Simulation time 283481686 ps
CPU time 1.88 seconds
Started Jun 07 06:20:30 PM PDT 24
Finished Jun 07 06:20:33 PM PDT 24
Peak memory 200308 kb
Host smart-7bbc5946-5dd1-42ed-85a8-534ed7923fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106010439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.4106010439
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1553538418
Short name T335
Test name
Test status
Simulation time 65541217 ps
CPU time 0.83 seconds
Started Jun 07 06:20:38 PM PDT 24
Finished Jun 07 06:20:39 PM PDT 24
Peak memory 200332 kb
Host smart-f0571d8a-6b04-4230-96fd-17d5fb15444e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553538418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1553538418
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.2807556922
Short name T267
Test name
Test status
Simulation time 82364757 ps
CPU time 0.81 seconds
Started Jun 07 06:20:36 PM PDT 24
Finished Jun 07 06:20:37 PM PDT 24
Peak memory 200136 kb
Host smart-e2b71802-a0e3-4e48-8914-7d89e6df1ff9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807556922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2807556922
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.238153938
Short name T49
Test name
Test status
Simulation time 1881050401 ps
CPU time 6.89 seconds
Started Jun 07 06:20:38 PM PDT 24
Finished Jun 07 06:20:45 PM PDT 24
Peak memory 221984 kb
Host smart-5ef4ed8e-78f5-4226-87f5-7d583b020ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238153938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.238153938
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3069695122
Short name T218
Test name
Test status
Simulation time 243527626 ps
CPU time 1.06 seconds
Started Jun 07 06:20:36 PM PDT 24
Finished Jun 07 06:20:38 PM PDT 24
Peak memory 217556 kb
Host smart-5a8542a6-58b2-44ef-a8b0-b2f258a2af94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069695122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3069695122
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.4016240545
Short name T332
Test name
Test status
Simulation time 92491177 ps
CPU time 0.73 seconds
Started Jun 07 06:20:36 PM PDT 24
Finished Jun 07 06:20:37 PM PDT 24
Peak memory 200172 kb
Host smart-8cb9c6c5-b2be-4a2d-9bb3-168027066d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016240545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.4016240545
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2235085706
Short name T337
Test name
Test status
Simulation time 1862213058 ps
CPU time 6.6 seconds
Started Jun 07 06:20:36 PM PDT 24
Finished Jun 07 06:20:44 PM PDT 24
Peak memory 200540 kb
Host smart-e6b419d2-5dd7-44c6-87ed-260061f07e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235085706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2235085706
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.4240883303
Short name T280
Test name
Test status
Simulation time 146150488 ps
CPU time 1.15 seconds
Started Jun 07 06:20:39 PM PDT 24
Finished Jun 07 06:20:41 PM PDT 24
Peak memory 200340 kb
Host smart-bc8d59bd-b27f-4a2a-9c18-d5946db20100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240883303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.4240883303
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1672944697
Short name T201
Test name
Test status
Simulation time 110776243 ps
CPU time 1.17 seconds
Started Jun 07 06:20:36 PM PDT 24
Finished Jun 07 06:20:38 PM PDT 24
Peak memory 200528 kb
Host smart-d62871e4-4180-4822-b450-0d664912803f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672944697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1672944697
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1113913768
Short name T257
Test name
Test status
Simulation time 2753593980 ps
CPU time 11.95 seconds
Started Jun 07 06:20:35 PM PDT 24
Finished Jun 07 06:20:48 PM PDT 24
Peak memory 200676 kb
Host smart-0d41bec1-e749-45c4-97e0-1ad43ab0b12f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113913768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1113913768
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2519760118
Short name T507
Test name
Test status
Simulation time 280744686 ps
CPU time 1.89 seconds
Started Jun 07 06:20:37 PM PDT 24
Finished Jun 07 06:20:40 PM PDT 24
Peak memory 200332 kb
Host smart-4f18ec03-30ed-4f32-8e08-89f0ba988bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519760118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2519760118
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2696305972
Short name T236
Test name
Test status
Simulation time 126371706 ps
CPU time 1.08 seconds
Started Jun 07 06:20:37 PM PDT 24
Finished Jun 07 06:20:39 PM PDT 24
Peak memory 200356 kb
Host smart-dddbcf75-d37e-4f88-a2b9-205534ed3315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696305972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2696305972
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2190622153
Short name T304
Test name
Test status
Simulation time 78197955 ps
CPU time 0.82 seconds
Started Jun 07 06:19:27 PM PDT 24
Finished Jun 07 06:19:29 PM PDT 24
Peak memory 200164 kb
Host smart-2e05f1e2-f588-4dfd-b7ef-bfaa6457032d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190622153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2190622153
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1250620734
Short name T26
Test name
Test status
Simulation time 2369307557 ps
CPU time 8.53 seconds
Started Jun 07 06:19:29 PM PDT 24
Finished Jun 07 06:19:38 PM PDT 24
Peak memory 222132 kb
Host smart-a67e46c3-bae8-4d3f-9739-d5252dfb7d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250620734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1250620734
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1255375566
Short name T412
Test name
Test status
Simulation time 243789316 ps
CPU time 1.04 seconds
Started Jun 07 06:19:31 PM PDT 24
Finished Jun 07 06:19:32 PM PDT 24
Peak memory 217532 kb
Host smart-0a3f2111-3de6-4998-9c83-9d9030e7a4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255375566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1255375566
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3411384391
Short name T542
Test name
Test status
Simulation time 110040970 ps
CPU time 0.81 seconds
Started Jun 07 06:19:31 PM PDT 24
Finished Jun 07 06:19:32 PM PDT 24
Peak memory 200156 kb
Host smart-a5ee48f2-d6d4-4eca-9f16-7576434f8d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411384391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3411384391
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.3318804992
Short name T467
Test name
Test status
Simulation time 1209870194 ps
CPU time 5.02 seconds
Started Jun 07 06:19:31 PM PDT 24
Finished Jun 07 06:19:36 PM PDT 24
Peak memory 200496 kb
Host smart-5495fad4-6220-414c-8c12-b04362243af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318804992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3318804992
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.752786709
Short name T68
Test name
Test status
Simulation time 8359645847 ps
CPU time 13 seconds
Started Jun 07 06:19:26 PM PDT 24
Finished Jun 07 06:19:40 PM PDT 24
Peak memory 217496 kb
Host smart-161be980-e029-49bd-bfe7-2b291d2d5c6e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752786709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.752786709
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1410983868
Short name T134
Test name
Test status
Simulation time 179695999 ps
CPU time 1.24 seconds
Started Jun 07 06:19:32 PM PDT 24
Finished Jun 07 06:19:34 PM PDT 24
Peak memory 200248 kb
Host smart-367104c3-9aa0-4761-bd22-5f7028d8435a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410983868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1410983868
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2473487651
Short name T148
Test name
Test status
Simulation time 114024336 ps
CPU time 1.22 seconds
Started Jun 07 06:19:30 PM PDT 24
Finished Jun 07 06:19:32 PM PDT 24
Peak memory 200516 kb
Host smart-aa95bd66-d300-45f2-96f5-cc7c87c3109b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473487651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2473487651
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3057074382
Short name T462
Test name
Test status
Simulation time 8096105469 ps
CPU time 33.07 seconds
Started Jun 07 06:19:31 PM PDT 24
Finished Jun 07 06:20:05 PM PDT 24
Peak memory 210632 kb
Host smart-12b44422-c4b9-4506-ba23-a77f27ea1d89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057074382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3057074382
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1977004990
Short name T317
Test name
Test status
Simulation time 381612848 ps
CPU time 2.59 seconds
Started Jun 07 06:19:27 PM PDT 24
Finished Jun 07 06:19:30 PM PDT 24
Peak memory 200344 kb
Host smart-17f2f8cf-7997-42c1-bb2f-a424a6168513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977004990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1977004990
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.573942797
Short name T518
Test name
Test status
Simulation time 189453385 ps
CPU time 1.28 seconds
Started Jun 07 06:19:29 PM PDT 24
Finished Jun 07 06:19:31 PM PDT 24
Peak memory 200372 kb
Host smart-db4e7761-97c5-43bd-a165-6026f99c1dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573942797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.573942797
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.4259911621
Short name T149
Test name
Test status
Simulation time 75456787 ps
CPU time 0.85 seconds
Started Jun 07 06:20:42 PM PDT 24
Finished Jun 07 06:20:44 PM PDT 24
Peak memory 200168 kb
Host smart-ca024c50-71c0-4221-bda0-64a5d454df65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259911621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.4259911621
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.154819773
Short name T389
Test name
Test status
Simulation time 2359174745 ps
CPU time 8.22 seconds
Started Jun 07 06:20:41 PM PDT 24
Finished Jun 07 06:20:50 PM PDT 24
Peak memory 218132 kb
Host smart-a214a9f5-4e0c-4cd3-8d95-2cac171e3f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154819773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.154819773
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3934778983
Short name T509
Test name
Test status
Simulation time 244282108 ps
CPU time 1.07 seconds
Started Jun 07 06:20:37 PM PDT 24
Finished Jun 07 06:20:39 PM PDT 24
Peak memory 217576 kb
Host smart-9c400c04-5b0d-4553-9c03-4feed2cc1376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934778983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3934778983
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.2182100831
Short name T395
Test name
Test status
Simulation time 131315274 ps
CPU time 0.79 seconds
Started Jun 07 06:20:38 PM PDT 24
Finished Jun 07 06:20:40 PM PDT 24
Peak memory 200164 kb
Host smart-ca69ed7e-2852-46c0-acef-098cc1041bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182100831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2182100831
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.1060957895
Short name T400
Test name
Test status
Simulation time 834664906 ps
CPU time 4.4 seconds
Started Jun 07 06:20:36 PM PDT 24
Finished Jun 07 06:20:41 PM PDT 24
Peak memory 200540 kb
Host smart-8e9c099a-fd41-4a7d-bac4-f8cc1ad5b40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060957895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.1060957895
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1661118341
Short name T476
Test name
Test status
Simulation time 101165753 ps
CPU time 0.94 seconds
Started Jun 07 06:20:38 PM PDT 24
Finished Jun 07 06:20:39 PM PDT 24
Peak memory 200276 kb
Host smart-e57f68dd-031d-487a-afb0-40279ecdac29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661118341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1661118341
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2737590412
Short name T316
Test name
Test status
Simulation time 256199714 ps
CPU time 1.6 seconds
Started Jun 07 06:20:42 PM PDT 24
Finished Jun 07 06:20:44 PM PDT 24
Peak memory 200536 kb
Host smart-c7b44c31-8b46-404d-8a68-9aab1b76d5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737590412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2737590412
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2840202489
Short name T375
Test name
Test status
Simulation time 9111351902 ps
CPU time 35.8 seconds
Started Jun 07 06:20:37 PM PDT 24
Finished Jun 07 06:21:14 PM PDT 24
Peak memory 200660 kb
Host smart-9aabe8ab-f3c2-4505-ab0c-e5713e161bc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840202489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2840202489
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.429318133
Short name T473
Test name
Test status
Simulation time 356582747 ps
CPU time 2.21 seconds
Started Jun 07 06:20:40 PM PDT 24
Finished Jun 07 06:20:43 PM PDT 24
Peak memory 208468 kb
Host smart-4cd5e692-50f6-43e7-abb9-6e34523910d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429318133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.429318133
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2871170562
Short name T373
Test name
Test status
Simulation time 115539513 ps
CPU time 1.04 seconds
Started Jun 07 06:20:37 PM PDT 24
Finished Jun 07 06:20:39 PM PDT 24
Peak memory 200352 kb
Host smart-023aa3b9-4276-45d6-b8cd-5b55d5839346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871170562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2871170562
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.2582911910
Short name T270
Test name
Test status
Simulation time 54407503 ps
CPU time 0.81 seconds
Started Jun 07 06:20:41 PM PDT 24
Finished Jun 07 06:20:42 PM PDT 24
Peak memory 200052 kb
Host smart-656aae27-6b82-45a4-aa08-d125024c7abf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582911910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.2582911910
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2358632176
Short name T383
Test name
Test status
Simulation time 2170503797 ps
CPU time 8.13 seconds
Started Jun 07 06:20:38 PM PDT 24
Finished Jun 07 06:20:47 PM PDT 24
Peak memory 222016 kb
Host smart-c509df9b-f5af-4008-b848-d515cc20dc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358632176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2358632176
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3902709629
Short name T421
Test name
Test status
Simulation time 244035992 ps
CPU time 1.04 seconds
Started Jun 07 06:20:44 PM PDT 24
Finished Jun 07 06:20:45 PM PDT 24
Peak memory 217588 kb
Host smart-189af692-9503-4dc1-9a66-c034ff262778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902709629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3902709629
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.2063764387
Short name T13
Test name
Test status
Simulation time 100410174 ps
CPU time 0.77 seconds
Started Jun 07 06:20:36 PM PDT 24
Finished Jun 07 06:20:37 PM PDT 24
Peak memory 200144 kb
Host smart-d640c146-b550-431d-8a05-5dc5a9997ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063764387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2063764387
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3689160910
Short name T206
Test name
Test status
Simulation time 978580783 ps
CPU time 4.86 seconds
Started Jun 07 06:20:37 PM PDT 24
Finished Jun 07 06:20:42 PM PDT 24
Peak memory 200544 kb
Host smart-23fbcd5d-e5eb-4b58-a8bd-7ddc56bc37c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689160910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3689160910
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.453973558
Short name T11
Test name
Test status
Simulation time 173914859 ps
CPU time 1.2 seconds
Started Jun 07 06:20:42 PM PDT 24
Finished Jun 07 06:20:44 PM PDT 24
Peak memory 200372 kb
Host smart-54fdf90c-9614-49a6-b242-4f8e76fa0149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453973558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.453973558
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3084477735
Short name T225
Test name
Test status
Simulation time 118656300 ps
CPU time 1.18 seconds
Started Jun 07 06:20:40 PM PDT 24
Finished Jun 07 06:20:42 PM PDT 24
Peak memory 200344 kb
Host smart-cbff1260-2b05-476c-8497-1ac2923d296c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084477735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3084477735
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1400359018
Short name T318
Test name
Test status
Simulation time 5847249361 ps
CPU time 22.52 seconds
Started Jun 07 06:20:39 PM PDT 24
Finished Jun 07 06:21:02 PM PDT 24
Peak memory 208856 kb
Host smart-31c19b8c-eaa3-4795-ac43-1809e8b65898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400359018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1400359018
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3203526897
Short name T496
Test name
Test status
Simulation time 451586019 ps
CPU time 2.36 seconds
Started Jun 07 06:20:37 PM PDT 24
Finished Jun 07 06:20:40 PM PDT 24
Peak memory 200368 kb
Host smart-c6f47a20-f86d-4648-b862-c6f243f26375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203526897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3203526897
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1729644766
Short name T475
Test name
Test status
Simulation time 89289637 ps
CPU time 0.93 seconds
Started Jun 07 06:20:38 PM PDT 24
Finished Jun 07 06:20:40 PM PDT 24
Peak memory 200336 kb
Host smart-c181a467-88b2-41b9-a65d-8dc3020ef19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729644766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1729644766
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1876040950
Short name T42
Test name
Test status
Simulation time 70616002 ps
CPU time 0.8 seconds
Started Jun 07 06:20:44 PM PDT 24
Finished Jun 07 06:20:45 PM PDT 24
Peak memory 200152 kb
Host smart-df0cc089-6af6-4f49-ab65-7f924f0783b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876040950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1876040950
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2109168501
Short name T544
Test name
Test status
Simulation time 1227505953 ps
CPU time 5.2 seconds
Started Jun 07 06:20:38 PM PDT 24
Finished Jun 07 06:20:44 PM PDT 24
Peak memory 216792 kb
Host smart-7bb3ef50-92db-4adb-8496-8b27e3a321a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109168501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2109168501
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.277003136
Short name T367
Test name
Test status
Simulation time 253735481 ps
CPU time 1.06 seconds
Started Jun 07 06:20:41 PM PDT 24
Finished Jun 07 06:20:43 PM PDT 24
Peak memory 217564 kb
Host smart-1bf27f0b-ef19-4abb-8b3a-33866f74103f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277003136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.277003136
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1218522589
Short name T237
Test name
Test status
Simulation time 103203753 ps
CPU time 0.76 seconds
Started Jun 07 06:20:41 PM PDT 24
Finished Jun 07 06:20:42 PM PDT 24
Peak memory 200080 kb
Host smart-dfc3f67a-3a1a-4dce-97ef-cbc52d65eee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218522589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1218522589
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1524507572
Short name T350
Test name
Test status
Simulation time 927986774 ps
CPU time 4.42 seconds
Started Jun 07 06:20:43 PM PDT 24
Finished Jun 07 06:20:48 PM PDT 24
Peak memory 200524 kb
Host smart-247649ce-88c9-43e1-aa2f-c43ba7760e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524507572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1524507572
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1269177777
Short name T306
Test name
Test status
Simulation time 186609263 ps
CPU time 1.19 seconds
Started Jun 07 06:20:39 PM PDT 24
Finished Jun 07 06:20:41 PM PDT 24
Peak memory 200328 kb
Host smart-e174b16c-6a45-4ad4-83ed-5d8ad14a757f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269177777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1269177777
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.1023839153
Short name T371
Test name
Test status
Simulation time 120319733 ps
CPU time 1.2 seconds
Started Jun 07 06:20:37 PM PDT 24
Finished Jun 07 06:20:39 PM PDT 24
Peak memory 200504 kb
Host smart-607cd338-5e85-435d-a5ab-c20cd429a153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023839153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1023839153
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.3619949347
Short name T287
Test name
Test status
Simulation time 4900276470 ps
CPU time 19.18 seconds
Started Jun 07 06:20:39 PM PDT 24
Finished Jun 07 06:20:59 PM PDT 24
Peak memory 208880 kb
Host smart-3a4e017d-698f-4942-8069-8422929d37a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619949347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3619949347
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1455109696
Short name T401
Test name
Test status
Simulation time 123530812 ps
CPU time 1.45 seconds
Started Jun 07 06:20:45 PM PDT 24
Finished Jun 07 06:20:46 PM PDT 24
Peak memory 200352 kb
Host smart-f0ed8b64-26cd-4950-bcd9-9a7983b0a6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455109696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1455109696
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3103323835
Short name T482
Test name
Test status
Simulation time 153866489 ps
CPU time 1.17 seconds
Started Jun 07 06:20:47 PM PDT 24
Finished Jun 07 06:20:49 PM PDT 24
Peak memory 200572 kb
Host smart-11cf151f-bd35-4b3a-a36a-6c5ad443e870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103323835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3103323835
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2938312024
Short name T369
Test name
Test status
Simulation time 75947323 ps
CPU time 0.88 seconds
Started Jun 07 06:20:42 PM PDT 24
Finished Jun 07 06:20:44 PM PDT 24
Peak memory 200144 kb
Host smart-24df74e5-f75f-425e-9950-400327577718
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938312024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2938312024
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.574472969
Short name T527
Test name
Test status
Simulation time 1230376551 ps
CPU time 5.27 seconds
Started Jun 07 06:20:46 PM PDT 24
Finished Jun 07 06:20:52 PM PDT 24
Peak memory 217952 kb
Host smart-450fbde8-f6f5-4400-98b2-3e1755dbfab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574472969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.574472969
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3359421748
Short name T208
Test name
Test status
Simulation time 244792528 ps
CPU time 1.09 seconds
Started Jun 07 06:20:40 PM PDT 24
Finished Jun 07 06:20:42 PM PDT 24
Peak memory 217552 kb
Host smart-24066a88-6177-4ad4-b0f5-4f1b476cab60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359421748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3359421748
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.1396181246
Short name T271
Test name
Test status
Simulation time 173078946 ps
CPU time 0.84 seconds
Started Jun 07 06:20:40 PM PDT 24
Finished Jun 07 06:20:41 PM PDT 24
Peak memory 200160 kb
Host smart-a50f0ff5-7f77-4162-8747-b1012473dc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396181246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1396181246
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.3947725029
Short name T386
Test name
Test status
Simulation time 1262490227 ps
CPU time 5.81 seconds
Started Jun 07 06:20:43 PM PDT 24
Finished Jun 07 06:20:50 PM PDT 24
Peak memory 200524 kb
Host smart-ba4e5ef7-169f-4886-953c-3ba1548c60f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947725029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3947725029
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1075749743
Short name T158
Test name
Test status
Simulation time 106163762 ps
CPU time 0.94 seconds
Started Jun 07 06:20:45 PM PDT 24
Finished Jun 07 06:20:47 PM PDT 24
Peak memory 200376 kb
Host smart-2a792439-ef5c-4132-9a89-c7af0d73bbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075749743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1075749743
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3364538065
Short name T254
Test name
Test status
Simulation time 246856133 ps
CPU time 1.54 seconds
Started Jun 07 06:20:39 PM PDT 24
Finished Jun 07 06:20:41 PM PDT 24
Peak memory 200716 kb
Host smart-455fb22a-55da-4108-9bd0-fa1364f1cf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364538065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3364538065
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.4176709922
Short name T397
Test name
Test status
Simulation time 2902100689 ps
CPU time 9.98 seconds
Started Jun 07 06:20:41 PM PDT 24
Finished Jun 07 06:20:51 PM PDT 24
Peak memory 200676 kb
Host smart-81b28de1-1dba-4c5c-88bf-421f36e773d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176709922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.4176709922
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1387055606
Short name T190
Test name
Test status
Simulation time 364942450 ps
CPU time 2.49 seconds
Started Jun 07 06:20:43 PM PDT 24
Finished Jun 07 06:20:46 PM PDT 24
Peak memory 200344 kb
Host smart-6bdc5e6b-8226-4024-8687-a50e3a29185b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387055606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1387055606
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1736232726
Short name T278
Test name
Test status
Simulation time 230788460 ps
CPU time 1.32 seconds
Started Jun 07 06:20:45 PM PDT 24
Finished Jun 07 06:20:47 PM PDT 24
Peak memory 200340 kb
Host smart-2c36e77a-324c-4627-8312-f7f493850766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736232726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1736232726
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1632944829
Short name T170
Test name
Test status
Simulation time 54323660 ps
CPU time 0.73 seconds
Started Jun 07 06:20:47 PM PDT 24
Finished Jun 07 06:20:48 PM PDT 24
Peak memory 200176 kb
Host smart-6452dfa6-3b8a-49ce-9b91-27461cb36776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632944829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1632944829
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.4214946606
Short name T50
Test name
Test status
Simulation time 1227248105 ps
CPU time 5.86 seconds
Started Jun 07 06:20:41 PM PDT 24
Finished Jun 07 06:20:47 PM PDT 24
Peak memory 217440 kb
Host smart-16ca4461-3edc-4cde-9cf8-39bbfab9164c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214946606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.4214946606
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3291992598
Short name T513
Test name
Test status
Simulation time 244406656 ps
CPU time 1.06 seconds
Started Jun 07 06:20:52 PM PDT 24
Finished Jun 07 06:20:53 PM PDT 24
Peak memory 217644 kb
Host smart-5f8c956d-c2d4-4340-b007-c7d8765d6747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291992598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3291992598
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.444185398
Short name T20
Test name
Test status
Simulation time 219322427 ps
CPU time 0.95 seconds
Started Jun 07 06:20:43 PM PDT 24
Finished Jun 07 06:20:44 PM PDT 24
Peak memory 200172 kb
Host smart-26be7466-8a96-4f7c-b637-194c3094e64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444185398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.444185398
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.119515124
Short name T494
Test name
Test status
Simulation time 1400199665 ps
CPU time 5.34 seconds
Started Jun 07 06:20:52 PM PDT 24
Finished Jun 07 06:20:57 PM PDT 24
Peak memory 200580 kb
Host smart-76a059e1-9132-4924-bdb0-866c945fce8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119515124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.119515124
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1421547462
Short name T227
Test name
Test status
Simulation time 171405030 ps
CPU time 1.2 seconds
Started Jun 07 06:20:46 PM PDT 24
Finished Jun 07 06:20:48 PM PDT 24
Peak memory 200356 kb
Host smart-0d586819-50f7-4c46-9812-94082756ed70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421547462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1421547462
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3377179260
Short name T262
Test name
Test status
Simulation time 191941848 ps
CPU time 1.39 seconds
Started Jun 07 06:20:41 PM PDT 24
Finished Jun 07 06:20:43 PM PDT 24
Peak memory 200708 kb
Host smart-3dfbd2fb-513f-48fa-a4bd-0d26f47d841b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377179260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3377179260
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3410735941
Short name T396
Test name
Test status
Simulation time 4650863843 ps
CPU time 23.22 seconds
Started Jun 07 06:20:40 PM PDT 24
Finished Jun 07 06:21:04 PM PDT 24
Peak memory 208744 kb
Host smart-b71cd952-79c6-4a01-932a-02fb693b302e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410735941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3410735941
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1446559095
Short name T411
Test name
Test status
Simulation time 142618853 ps
CPU time 1.72 seconds
Started Jun 07 06:20:47 PM PDT 24
Finished Jun 07 06:20:49 PM PDT 24
Peak memory 200392 kb
Host smart-ac252474-5513-454c-b249-9f6dcf2251c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446559095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1446559095
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1747521967
Short name T213
Test name
Test status
Simulation time 264026001 ps
CPU time 1.53 seconds
Started Jun 07 06:20:39 PM PDT 24
Finished Jun 07 06:20:41 PM PDT 24
Peak memory 200336 kb
Host smart-b0c82d7c-ba2e-4c83-92dd-cb5b4f81144c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747521967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1747521967
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3169020693
Short name T73
Test name
Test status
Simulation time 74445477 ps
CPU time 0.77 seconds
Started Jun 07 06:20:41 PM PDT 24
Finished Jun 07 06:20:42 PM PDT 24
Peak memory 200144 kb
Host smart-56c9368b-c823-467a-87a5-3dced3bbaeb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169020693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3169020693
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.4038436746
Short name T478
Test name
Test status
Simulation time 1875302439 ps
CPU time 6.95 seconds
Started Jun 07 06:20:45 PM PDT 24
Finished Jun 07 06:20:52 PM PDT 24
Peak memory 217420 kb
Host smart-43ad55d0-bbd8-4a94-9363-dd06cad1bbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038436746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.4038436746
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.680666505
Short name T362
Test name
Test status
Simulation time 243700232 ps
CPU time 1.05 seconds
Started Jun 07 06:20:44 PM PDT 24
Finished Jun 07 06:20:45 PM PDT 24
Peak memory 217572 kb
Host smart-931834e0-3565-4de8-8d68-c525b427803c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680666505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.680666505
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1493040696
Short name T378
Test name
Test status
Simulation time 184915706 ps
CPU time 0.87 seconds
Started Jun 07 06:20:40 PM PDT 24
Finished Jun 07 06:20:41 PM PDT 24
Peak memory 200112 kb
Host smart-f2f7ec59-59a5-4ebe-8e74-adbf555dfa9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493040696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1493040696
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2547188309
Short name T94
Test name
Test status
Simulation time 1388377978 ps
CPU time 5.99 seconds
Started Jun 07 06:20:46 PM PDT 24
Finished Jun 07 06:20:53 PM PDT 24
Peak memory 200536 kb
Host smart-bf52d6b0-32eb-474e-a642-2586e6092b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547188309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2547188309
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3291219436
Short name T499
Test name
Test status
Simulation time 165952959 ps
CPU time 1.13 seconds
Started Jun 07 06:20:43 PM PDT 24
Finished Jun 07 06:20:45 PM PDT 24
Peak memory 200320 kb
Host smart-bdf48a0d-2089-49a9-a63b-718aa90f4b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291219436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3291219436
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2766588836
Short name T465
Test name
Test status
Simulation time 272917793 ps
CPU time 1.47 seconds
Started Jun 07 06:20:40 PM PDT 24
Finished Jun 07 06:20:42 PM PDT 24
Peak memory 200468 kb
Host smart-5407f801-3329-4993-b752-26675ecd9b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766588836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2766588836
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1114530999
Short name T377
Test name
Test status
Simulation time 1463284592 ps
CPU time 7.59 seconds
Started Jun 07 06:20:40 PM PDT 24
Finished Jun 07 06:20:48 PM PDT 24
Peak memory 209780 kb
Host smart-67b2f86c-0bfe-47c9-bb97-75a1d62fed94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114530999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1114530999
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1217925793
Short name T221
Test name
Test status
Simulation time 142236423 ps
CPU time 1.87 seconds
Started Jun 07 06:20:46 PM PDT 24
Finished Jun 07 06:20:48 PM PDT 24
Peak memory 200340 kb
Host smart-1fcb1cc3-44d5-4ac6-96ee-1dbe3035a913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217925793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1217925793
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.455200548
Short name T139
Test name
Test status
Simulation time 117573921 ps
CPU time 1.08 seconds
Started Jun 07 06:20:40 PM PDT 24
Finished Jun 07 06:20:41 PM PDT 24
Peak memory 200348 kb
Host smart-b74f7017-6ab0-4979-9284-b52e71c65b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455200548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.455200548
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.4055052468
Short name T328
Test name
Test status
Simulation time 74699969 ps
CPU time 0.78 seconds
Started Jun 07 06:20:50 PM PDT 24
Finished Jun 07 06:20:51 PM PDT 24
Peak memory 200164 kb
Host smart-e258c90e-5d04-4123-b932-771b11baf0b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055052468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.4055052468
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.2349726765
Short name T448
Test name
Test status
Simulation time 1885419106 ps
CPU time 7.03 seconds
Started Jun 07 06:20:50 PM PDT 24
Finished Jun 07 06:20:58 PM PDT 24
Peak memory 221924 kb
Host smart-c023629e-f612-40ba-841b-301cbabb5349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349726765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2349726765
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.507553309
Short name T250
Test name
Test status
Simulation time 244439853 ps
CPU time 1.08 seconds
Started Jun 07 06:20:55 PM PDT 24
Finished Jun 07 06:20:57 PM PDT 24
Peak memory 217656 kb
Host smart-0e517b93-7184-4a8f-a7c9-8f1b983a68fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507553309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.507553309
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.1609509649
Short name T283
Test name
Test status
Simulation time 196485567 ps
CPU time 0.88 seconds
Started Jun 07 06:20:49 PM PDT 24
Finished Jun 07 06:20:50 PM PDT 24
Peak memory 200144 kb
Host smart-f3905264-b2d2-4187-9f80-0f155bbf9935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609509649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1609509649
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.4212028500
Short name T98
Test name
Test status
Simulation time 1796843212 ps
CPU time 6.81 seconds
Started Jun 07 06:20:49 PM PDT 24
Finished Jun 07 06:20:56 PM PDT 24
Peak memory 200576 kb
Host smart-97636096-b89a-420f-9b01-90cd9f453b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212028500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.4212028500
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1289992366
Short name T344
Test name
Test status
Simulation time 179159627 ps
CPU time 1.24 seconds
Started Jun 07 06:20:53 PM PDT 24
Finished Jun 07 06:20:54 PM PDT 24
Peak memory 200348 kb
Host smart-eaa68de4-e6ee-4f81-b7c0-5a4ebd5d32e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289992366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1289992366
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.2905440591
Short name T441
Test name
Test status
Simulation time 191943876 ps
CPU time 1.37 seconds
Started Jun 07 06:20:42 PM PDT 24
Finished Jun 07 06:20:44 PM PDT 24
Peak memory 200544 kb
Host smart-a206a888-c375-43b6-92da-a11a71fbbb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905440591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2905440591
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2498334405
Short name T501
Test name
Test status
Simulation time 2994344822 ps
CPU time 13.69 seconds
Started Jun 07 06:20:49 PM PDT 24
Finished Jun 07 06:21:03 PM PDT 24
Peak memory 208804 kb
Host smart-b587777f-0a8a-402b-be75-1c6181dc3a17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498334405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2498334405
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3057116305
Short name T529
Test name
Test status
Simulation time 538081451 ps
CPU time 2.68 seconds
Started Jun 07 06:20:53 PM PDT 24
Finished Jun 07 06:20:57 PM PDT 24
Peak memory 200392 kb
Host smart-41a34875-10fc-46ff-a441-20ba3f9bed52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057116305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3057116305
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.4247517293
Short name T535
Test name
Test status
Simulation time 166366663 ps
CPU time 1.13 seconds
Started Jun 07 06:20:51 PM PDT 24
Finished Jun 07 06:20:53 PM PDT 24
Peak memory 200352 kb
Host smart-5b61850b-fb06-4173-bd67-400b70a0fa28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247517293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.4247517293
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1859414542
Short name T209
Test name
Test status
Simulation time 76488470 ps
CPU time 0.81 seconds
Started Jun 07 06:20:52 PM PDT 24
Finished Jun 07 06:20:53 PM PDT 24
Peak memory 200168 kb
Host smart-ea32670c-d9e3-452d-b0dd-02daaeb9da80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859414542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1859414542
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3700877255
Short name T43
Test name
Test status
Simulation time 1210546019 ps
CPU time 5.39 seconds
Started Jun 07 06:20:54 PM PDT 24
Finished Jun 07 06:21:00 PM PDT 24
Peak memory 216840 kb
Host smart-fbba25f2-24a5-4182-96b5-f13fe5ded704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700877255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3700877255
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.4192266329
Short name T495
Test name
Test status
Simulation time 244652946 ps
CPU time 1.12 seconds
Started Jun 07 06:20:49 PM PDT 24
Finished Jun 07 06:20:51 PM PDT 24
Peak memory 217552 kb
Host smart-dbdaba17-bf8c-425f-9327-83befeb0880b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192266329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.4192266329
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3822313272
Short name T531
Test name
Test status
Simulation time 172580862 ps
CPU time 0.84 seconds
Started Jun 07 06:20:50 PM PDT 24
Finished Jun 07 06:20:52 PM PDT 24
Peak memory 200116 kb
Host smart-bb9fc6db-5881-4441-af17-33fb784194e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822313272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3822313272
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.403881734
Short name T323
Test name
Test status
Simulation time 1706928454 ps
CPU time 7.12 seconds
Started Jun 07 06:20:51 PM PDT 24
Finished Jun 07 06:20:58 PM PDT 24
Peak memory 200536 kb
Host smart-9995cea7-1f5f-468e-b91f-cac53a78a18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403881734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.403881734
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.420135880
Short name T519
Test name
Test status
Simulation time 174946747 ps
CPU time 1.17 seconds
Started Jun 07 06:20:54 PM PDT 24
Finished Jun 07 06:20:56 PM PDT 24
Peak memory 200376 kb
Host smart-d904cd5c-f60e-42b1-8670-29b5e86bb6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420135880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.420135880
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1953530549
Short name T500
Test name
Test status
Simulation time 182955540 ps
CPU time 1.36 seconds
Started Jun 07 06:20:51 PM PDT 24
Finished Jun 07 06:20:53 PM PDT 24
Peak memory 200472 kb
Host smart-bd37a78d-62c8-41d0-8748-25e6681ae1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953530549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1953530549
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.3955229396
Short name T436
Test name
Test status
Simulation time 11354131459 ps
CPU time 39.47 seconds
Started Jun 07 06:20:53 PM PDT 24
Finished Jun 07 06:21:33 PM PDT 24
Peak memory 200664 kb
Host smart-28282443-4e7d-4776-ac25-edeed6bc9fd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955229396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3955229396
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3255884858
Short name T414
Test name
Test status
Simulation time 450696936 ps
CPU time 2.52 seconds
Started Jun 07 06:20:53 PM PDT 24
Finished Jun 07 06:20:56 PM PDT 24
Peak memory 200364 kb
Host smart-a93c1c06-114c-417e-aebc-6a4594886633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255884858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3255884858
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1825000382
Short name T357
Test name
Test status
Simulation time 72943156 ps
CPU time 0.78 seconds
Started Jun 07 06:20:52 PM PDT 24
Finished Jun 07 06:20:53 PM PDT 24
Peak memory 200328 kb
Host smart-ab8bb3aa-0cd8-4795-ab35-571ccbbdd062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825000382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1825000382
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.2563133690
Short name T458
Test name
Test status
Simulation time 87446662 ps
CPU time 0.83 seconds
Started Jun 07 06:20:51 PM PDT 24
Finished Jun 07 06:20:52 PM PDT 24
Peak memory 200192 kb
Host smart-d7fa9203-ba7b-4b2c-90a7-689a483dd8c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563133690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2563133690
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.164974873
Short name T55
Test name
Test status
Simulation time 1230453232 ps
CPU time 5.45 seconds
Started Jun 07 06:20:51 PM PDT 24
Finished Jun 07 06:20:57 PM PDT 24
Peak memory 217984 kb
Host smart-251df577-63d2-4409-aca1-12890b21cd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164974873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.164974873
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3759290748
Short name T176
Test name
Test status
Simulation time 244454746 ps
CPU time 1.13 seconds
Started Jun 07 06:20:54 PM PDT 24
Finished Jun 07 06:20:56 PM PDT 24
Peak memory 217652 kb
Host smart-f18898c8-e17a-4779-bad6-b1e2e8172f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759290748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3759290748
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.896011694
Short name T333
Test name
Test status
Simulation time 113749127 ps
CPU time 0.82 seconds
Started Jun 07 06:20:51 PM PDT 24
Finished Jun 07 06:20:52 PM PDT 24
Peak memory 200180 kb
Host smart-000c2602-b865-4e5d-a81c-d4ec7da53112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896011694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.896011694
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.257942584
Short name T174
Test name
Test status
Simulation time 764579969 ps
CPU time 3.86 seconds
Started Jun 07 06:20:54 PM PDT 24
Finished Jun 07 06:20:58 PM PDT 24
Peak memory 200512 kb
Host smart-2811422b-a87f-454e-8a0d-8239ce19f8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257942584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.257942584
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.424189978
Short name T166
Test name
Test status
Simulation time 172278446 ps
CPU time 1.21 seconds
Started Jun 07 06:20:53 PM PDT 24
Finished Jun 07 06:20:55 PM PDT 24
Peak memory 200360 kb
Host smart-4f3950b9-2b2e-46d8-939f-751baeb4feb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424189978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.424189978
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3533342829
Short name T453
Test name
Test status
Simulation time 109232478 ps
CPU time 1.21 seconds
Started Jun 07 06:20:51 PM PDT 24
Finished Jun 07 06:20:53 PM PDT 24
Peak memory 200516 kb
Host smart-2bc77834-e5c9-47a3-b194-0212c15c2c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533342829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3533342829
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.488243303
Short name T429
Test name
Test status
Simulation time 14016312961 ps
CPU time 50.52 seconds
Started Jun 07 06:20:53 PM PDT 24
Finished Jun 07 06:21:44 PM PDT 24
Peak memory 208864 kb
Host smart-d1e5940a-08c4-450c-a329-f113985ab9e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488243303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.488243303
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.646206988
Short name T329
Test name
Test status
Simulation time 114112470 ps
CPU time 1.75 seconds
Started Jun 07 06:20:54 PM PDT 24
Finished Jun 07 06:20:56 PM PDT 24
Peak memory 200324 kb
Host smart-e43b8801-8d6c-4c61-a9a4-7613a51e4f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646206988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.646206988
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2048996624
Short name T541
Test name
Test status
Simulation time 194494356 ps
CPU time 1.19 seconds
Started Jun 07 06:20:49 PM PDT 24
Finished Jun 07 06:20:51 PM PDT 24
Peak memory 200348 kb
Host smart-d165c2a9-1635-43bd-9f5d-08a898f304f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048996624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2048996624
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1243657963
Short name T203
Test name
Test status
Simulation time 60483499 ps
CPU time 0.7 seconds
Started Jun 07 06:20:56 PM PDT 24
Finished Jun 07 06:20:57 PM PDT 24
Peak memory 200168 kb
Host smart-85745f63-38da-4131-a248-13c98c606cf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243657963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1243657963
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.472577683
Short name T342
Test name
Test status
Simulation time 1869078618 ps
CPU time 7.21 seconds
Started Jun 07 06:20:55 PM PDT 24
Finished Jun 07 06:21:03 PM PDT 24
Peak memory 221912 kb
Host smart-afe45b34-fa88-4d88-a933-f022e17faab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472577683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.472577683
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.4276819043
Short name T39
Test name
Test status
Simulation time 244361901 ps
CPU time 1.05 seconds
Started Jun 07 06:20:58 PM PDT 24
Finished Jun 07 06:20:59 PM PDT 24
Peak memory 217628 kb
Host smart-498d18fd-201a-47ee-ab2b-01896933ca57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276819043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.4276819043
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.195936534
Short name T439
Test name
Test status
Simulation time 196244982 ps
CPU time 0.88 seconds
Started Jun 07 06:20:52 PM PDT 24
Finished Jun 07 06:20:53 PM PDT 24
Peak memory 200188 kb
Host smart-e687b197-7fd7-4c81-ae9c-eaf6c62e33ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195936534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.195936534
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.4228656030
Short name T234
Test name
Test status
Simulation time 832251770 ps
CPU time 4.04 seconds
Started Jun 07 06:20:53 PM PDT 24
Finished Jun 07 06:20:58 PM PDT 24
Peak memory 200600 kb
Host smart-f5ef7de0-8dc6-42a1-b2b1-828423a2225a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228656030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.4228656030
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3660434292
Short name T76
Test name
Test status
Simulation time 183651848 ps
CPU time 1.26 seconds
Started Jun 07 06:20:54 PM PDT 24
Finished Jun 07 06:20:56 PM PDT 24
Peak memory 200284 kb
Host smart-cc6014bd-b469-4a4b-95f3-9e3abcf9bb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660434292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3660434292
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2593237177
Short name T163
Test name
Test status
Simulation time 127368702 ps
CPU time 1.18 seconds
Started Jun 07 06:20:53 PM PDT 24
Finished Jun 07 06:20:55 PM PDT 24
Peak memory 200508 kb
Host smart-157d0d13-5b28-4f32-a642-c0636f5b54b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593237177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2593237177
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.69233228
Short name T96
Test name
Test status
Simulation time 2802517663 ps
CPU time 12.11 seconds
Started Jun 07 06:20:58 PM PDT 24
Finished Jun 07 06:21:10 PM PDT 24
Peak memory 200652 kb
Host smart-995e1580-2da9-4b6a-945b-c720dc48302e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69233228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.69233228
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3147109643
Short name T360
Test name
Test status
Simulation time 315610841 ps
CPU time 1.99 seconds
Started Jun 07 06:20:49 PM PDT 24
Finished Jun 07 06:20:51 PM PDT 24
Peak memory 200316 kb
Host smart-af565a83-f43f-4df7-b6aa-c50544f82832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147109643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3147109643
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.897195114
Short name T293
Test name
Test status
Simulation time 89285474 ps
CPU time 0.87 seconds
Started Jun 07 06:20:52 PM PDT 24
Finished Jun 07 06:20:53 PM PDT 24
Peak memory 200312 kb
Host smart-70ae63ed-832f-4f54-b730-0a87065de2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897195114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.897195114
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2182823015
Short name T228
Test name
Test status
Simulation time 96193532 ps
CPU time 0.83 seconds
Started Jun 07 06:19:32 PM PDT 24
Finished Jun 07 06:19:33 PM PDT 24
Peak memory 200120 kb
Host smart-e8ab0b6c-e752-43e4-aca0-c6ebc931130e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182823015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2182823015
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.435797771
Short name T428
Test name
Test status
Simulation time 2345753916 ps
CPU time 9.34 seconds
Started Jun 07 06:19:30 PM PDT 24
Finished Jun 07 06:19:40 PM PDT 24
Peak memory 221892 kb
Host smart-26988fb5-8961-4e94-820f-2f0707bfddf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435797771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.435797771
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3202435384
Short name T78
Test name
Test status
Simulation time 245373242 ps
CPU time 1.16 seconds
Started Jun 07 06:19:32 PM PDT 24
Finished Jun 07 06:19:34 PM PDT 24
Peak memory 217492 kb
Host smart-178f127a-5593-4dd9-a044-3f94ebe4fc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202435384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3202435384
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3158474643
Short name T424
Test name
Test status
Simulation time 103855135 ps
CPU time 0.77 seconds
Started Jun 07 06:19:32 PM PDT 24
Finished Jun 07 06:19:33 PM PDT 24
Peak memory 200144 kb
Host smart-63061962-76ba-4e68-aa31-208cac91fbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158474643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3158474643
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.3791751947
Short name T331
Test name
Test status
Simulation time 983335571 ps
CPU time 4.92 seconds
Started Jun 07 06:19:27 PM PDT 24
Finished Jun 07 06:19:33 PM PDT 24
Peak memory 200520 kb
Host smart-042a18d9-a071-425c-ab0e-94ca52ee2f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791751947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3791751947
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2464152777
Short name T404
Test name
Test status
Simulation time 155405926 ps
CPU time 1.14 seconds
Started Jun 07 06:19:32 PM PDT 24
Finished Jun 07 06:19:34 PM PDT 24
Peak memory 200304 kb
Host smart-f9dd3df5-0760-48a7-aafd-d55bcc12fa44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464152777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2464152777
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3741968557
Short name T326
Test name
Test status
Simulation time 252904237 ps
CPU time 1.49 seconds
Started Jun 07 06:19:29 PM PDT 24
Finished Jun 07 06:19:31 PM PDT 24
Peak memory 200516 kb
Host smart-79f4581b-3294-4a10-8161-20ab1c70ff59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741968557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3741968557
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2410822732
Short name T423
Test name
Test status
Simulation time 6357246544 ps
CPU time 24.7 seconds
Started Jun 07 06:19:31 PM PDT 24
Finished Jun 07 06:19:56 PM PDT 24
Peak memory 208924 kb
Host smart-27266051-bf52-4e67-8493-82f4bed90d1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410822732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2410822732
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3950101531
Short name T305
Test name
Test status
Simulation time 533990060 ps
CPU time 2.73 seconds
Started Jun 07 06:19:29 PM PDT 24
Finished Jun 07 06:19:32 PM PDT 24
Peak memory 200268 kb
Host smart-1edb4e11-c346-4243-82ab-02de70d23773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950101531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3950101531
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.3127031986
Short name T248
Test name
Test status
Simulation time 98159835 ps
CPU time 0.92 seconds
Started Jun 07 06:19:32 PM PDT 24
Finished Jun 07 06:19:33 PM PDT 24
Peak memory 200284 kb
Host smart-4f3fc798-337e-4484-8ba9-45b17777a261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127031986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3127031986
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3720360595
Short name T74
Test name
Test status
Simulation time 57276550 ps
CPU time 0.71 seconds
Started Jun 07 06:19:35 PM PDT 24
Finished Jun 07 06:19:36 PM PDT 24
Peak memory 200140 kb
Host smart-fda147d7-dcb2-4581-905d-8fc75c12fbbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720360595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3720360595
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2073945204
Short name T464
Test name
Test status
Simulation time 2167924266 ps
CPU time 8.11 seconds
Started Jun 07 06:19:35 PM PDT 24
Finished Jun 07 06:19:43 PM PDT 24
Peak memory 222004 kb
Host smart-f1eb70f2-e992-4993-bbeb-2c8410a55646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073945204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2073945204
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.120629440
Short name T145
Test name
Test status
Simulation time 244360421 ps
CPU time 1.11 seconds
Started Jun 07 06:19:39 PM PDT 24
Finished Jun 07 06:19:41 PM PDT 24
Peak memory 217536 kb
Host smart-d928ac94-6e0c-4f92-9eef-9b311e16d037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120629440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.120629440
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3385180272
Short name T268
Test name
Test status
Simulation time 115610343 ps
CPU time 0.86 seconds
Started Jun 07 06:19:29 PM PDT 24
Finished Jun 07 06:19:30 PM PDT 24
Peak memory 200076 kb
Host smart-674cf5b1-d857-4eec-b5a2-9d1e14c5444b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385180272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3385180272
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3626676968
Short name T351
Test name
Test status
Simulation time 1084365351 ps
CPU time 5.3 seconds
Started Jun 07 06:19:33 PM PDT 24
Finished Jun 07 06:19:38 PM PDT 24
Peak memory 200368 kb
Host smart-d6e947ce-7cc9-4a1f-8938-b0ac8c2dd071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626676968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3626676968
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3518014081
Short name T449
Test name
Test status
Simulation time 152361233 ps
CPU time 1.13 seconds
Started Jun 07 06:19:35 PM PDT 24
Finished Jun 07 06:19:37 PM PDT 24
Peak memory 200268 kb
Host smart-c64eb6c4-2067-4df8-8abd-0bc8aee67619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518014081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3518014081
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2427979400
Short name T179
Test name
Test status
Simulation time 241108093 ps
CPU time 1.68 seconds
Started Jun 07 06:19:31 PM PDT 24
Finished Jun 07 06:19:34 PM PDT 24
Peak memory 200396 kb
Host smart-dd3658db-920a-4c9d-bae6-7b58c89b984d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427979400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2427979400
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.249046932
Short name T447
Test name
Test status
Simulation time 11781502937 ps
CPU time 40.87 seconds
Started Jun 07 06:19:38 PM PDT 24
Finished Jun 07 06:20:19 PM PDT 24
Peak memory 208784 kb
Host smart-5e827926-e0ba-4354-b66a-7640e978010f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249046932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.249046932
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.516090800
Short name T416
Test name
Test status
Simulation time 318450685 ps
CPU time 2.12 seconds
Started Jun 07 06:19:30 PM PDT 24
Finished Jun 07 06:19:33 PM PDT 24
Peak memory 200348 kb
Host smart-53c150ab-14af-44d1-87ca-594f3e4e1e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516090800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.516090800
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.622912230
Short name T243
Test name
Test status
Simulation time 211323389 ps
CPU time 1.36 seconds
Started Jun 07 06:19:31 PM PDT 24
Finished Jun 07 06:19:33 PM PDT 24
Peak memory 200332 kb
Host smart-8b816af7-f6d5-47e4-bcfb-8bb98c44b219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622912230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.622912230
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.398838763
Short name T245
Test name
Test status
Simulation time 67403217 ps
CPU time 0.81 seconds
Started Jun 07 06:19:33 PM PDT 24
Finished Jun 07 06:19:34 PM PDT 24
Peak memory 200180 kb
Host smart-c6746b2b-1aad-4f1c-9fee-191a7e55f98b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398838763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.398838763
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.386376847
Short name T30
Test name
Test status
Simulation time 1216543899 ps
CPU time 5.91 seconds
Started Jun 07 06:19:42 PM PDT 24
Finished Jun 07 06:19:49 PM PDT 24
Peak memory 217928 kb
Host smart-e8486ef5-5ae9-4f95-82ec-3b20d43299cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386376847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.386376847
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2945600992
Short name T295
Test name
Test status
Simulation time 245198669 ps
CPU time 1.06 seconds
Started Jun 07 06:19:36 PM PDT 24
Finished Jun 07 06:19:38 PM PDT 24
Peak memory 217568 kb
Host smart-f188ae64-6ff9-41d4-b74c-392d0cee2dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945600992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2945600992
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.4116829935
Short name T402
Test name
Test status
Simulation time 197650479 ps
CPU time 0.97 seconds
Started Jun 07 06:19:36 PM PDT 24
Finished Jun 07 06:19:38 PM PDT 24
Peak memory 200004 kb
Host smart-858957df-5e5e-48bf-bae9-0441bd2d9058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116829935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.4116829935
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3837817010
Short name T472
Test name
Test status
Simulation time 2084381700 ps
CPU time 7.21 seconds
Started Jun 07 06:19:35 PM PDT 24
Finished Jun 07 06:19:43 PM PDT 24
Peak memory 200460 kb
Host smart-4c924b30-fe3a-4f2d-8f40-f822e8addfda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837817010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3837817010
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.213410593
Short name T300
Test name
Test status
Simulation time 164820346 ps
CPU time 1.15 seconds
Started Jun 07 06:19:38 PM PDT 24
Finished Jun 07 06:19:40 PM PDT 24
Peak memory 200392 kb
Host smart-90c0c195-7989-41a8-9cf0-14b478ad60f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213410593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.213410593
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.882660646
Short name T178
Test name
Test status
Simulation time 220525924 ps
CPU time 1.47 seconds
Started Jun 07 06:19:34 PM PDT 24
Finished Jun 07 06:19:35 PM PDT 24
Peak memory 200536 kb
Host smart-25c7eeba-000e-4820-9741-8df2f38338fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882660646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.882660646
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2624487882
Short name T85
Test name
Test status
Simulation time 1534082453 ps
CPU time 5.92 seconds
Started Jun 07 06:19:37 PM PDT 24
Finished Jun 07 06:19:43 PM PDT 24
Peak memory 200596 kb
Host smart-415a3a7a-22d0-4033-9b65-e4c6d735efd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624487882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2624487882
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.2891990556
Short name T75
Test name
Test status
Simulation time 557904873 ps
CPU time 2.81 seconds
Started Jun 07 06:19:43 PM PDT 24
Finished Jun 07 06:19:47 PM PDT 24
Peak memory 200300 kb
Host smart-a063382c-07ec-422a-a6cd-7c67e9e893f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891990556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2891990556
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2485614201
Short name T259
Test name
Test status
Simulation time 104863967 ps
CPU time 1.02 seconds
Started Jun 07 06:19:42 PM PDT 24
Finished Jun 07 06:19:44 PM PDT 24
Peak memory 200316 kb
Host smart-5191a5b1-2918-4644-909c-73cf6c30f9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485614201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2485614201
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.3750473494
Short name T252
Test name
Test status
Simulation time 68738648 ps
CPU time 0.76 seconds
Started Jun 07 06:19:43 PM PDT 24
Finished Jun 07 06:19:45 PM PDT 24
Peak memory 200116 kb
Host smart-3c9813ca-410d-4570-b148-499a79786d98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750473494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3750473494
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.390498105
Short name T56
Test name
Test status
Simulation time 2347043604 ps
CPU time 7.76 seconds
Started Jun 07 06:19:39 PM PDT 24
Finished Jun 07 06:19:47 PM PDT 24
Peak memory 222076 kb
Host smart-185e5f1b-158a-40ad-bae8-0de8f3c03dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390498105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.390498105
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.125880217
Short name T146
Test name
Test status
Simulation time 243857224 ps
CPU time 1.05 seconds
Started Jun 07 06:19:33 PM PDT 24
Finished Jun 07 06:19:35 PM PDT 24
Peak memory 217468 kb
Host smart-5dba5194-e1d8-4c52-b946-924fc5ebcce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125880217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.125880217
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.4104869730
Short name T506
Test name
Test status
Simulation time 134481280 ps
CPU time 0.86 seconds
Started Jun 07 06:19:34 PM PDT 24
Finished Jun 07 06:19:35 PM PDT 24
Peak memory 200032 kb
Host smart-4fa1dc0b-5058-4631-a454-dacc78a74e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104869730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.4104869730
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2702022372
Short name T511
Test name
Test status
Simulation time 1594251119 ps
CPU time 5.76 seconds
Started Jun 07 06:19:36 PM PDT 24
Finished Jun 07 06:19:43 PM PDT 24
Peak memory 200536 kb
Host smart-7ef73b4f-f63a-4fb6-a67d-4f0e76e09818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702022372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2702022372
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.172694086
Short name T327
Test name
Test status
Simulation time 111860847 ps
CPU time 1.03 seconds
Started Jun 07 06:19:37 PM PDT 24
Finished Jun 07 06:19:38 PM PDT 24
Peak memory 200296 kb
Host smart-54ebef9c-c92b-4ef9-9906-51810dd5a402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172694086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.172694086
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3570492460
Short name T196
Test name
Test status
Simulation time 200619101 ps
CPU time 1.53 seconds
Started Jun 07 06:19:43 PM PDT 24
Finished Jun 07 06:19:45 PM PDT 24
Peak memory 200504 kb
Host smart-57ae4361-ba7c-46a5-9338-9107e63a6b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570492460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3570492460
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.3351138753
Short name T80
Test name
Test status
Simulation time 1234322486 ps
CPU time 5.98 seconds
Started Jun 07 06:19:39 PM PDT 24
Finished Jun 07 06:19:46 PM PDT 24
Peak memory 200480 kb
Host smart-7645eb6d-d7d9-4db5-82f1-46787ddc39cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351138753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3351138753
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.2118411325
Short name T38
Test name
Test status
Simulation time 115408137 ps
CPU time 1.44 seconds
Started Jun 07 06:19:36 PM PDT 24
Finished Jun 07 06:19:39 PM PDT 24
Peak memory 200408 kb
Host smart-51627d9a-d57a-42f1-91b6-d8205ab81f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118411325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2118411325
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2235274661
Short name T263
Test name
Test status
Simulation time 106281912 ps
CPU time 0.97 seconds
Started Jun 07 06:19:43 PM PDT 24
Finished Jun 07 06:19:45 PM PDT 24
Peak memory 200320 kb
Host smart-70faf360-7010-4746-b349-467ca9b44db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235274661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2235274661
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.4003927273
Short name T244
Test name
Test status
Simulation time 82365107 ps
CPU time 0.77 seconds
Started Jun 07 06:19:44 PM PDT 24
Finished Jun 07 06:19:46 PM PDT 24
Peak memory 200128 kb
Host smart-214219b0-6517-40d2-8c39-0faaafd47a16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003927273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.4003927273
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.4202736148
Short name T28
Test name
Test status
Simulation time 1894381646 ps
CPU time 7.27 seconds
Started Jun 07 06:19:44 PM PDT 24
Finished Jun 07 06:19:52 PM PDT 24
Peak memory 221576 kb
Host smart-2ec032ce-9e17-4526-ab5f-9bb18f391ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202736148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.4202736148
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2121020863
Short name T446
Test name
Test status
Simulation time 244196212 ps
CPU time 1.05 seconds
Started Jun 07 06:19:43 PM PDT 24
Finished Jun 07 06:19:45 PM PDT 24
Peak memory 217444 kb
Host smart-74a69d6b-4a50-4849-b049-d3e2d2527fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121020863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2121020863
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1891575458
Short name T459
Test name
Test status
Simulation time 177750285 ps
CPU time 0.93 seconds
Started Jun 07 06:19:37 PM PDT 24
Finished Jun 07 06:19:39 PM PDT 24
Peak memory 200180 kb
Host smart-a88ead8d-aaa4-43af-8c01-bc4a3674ddcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891575458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1891575458
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.730408533
Short name T530
Test name
Test status
Simulation time 1200667674 ps
CPU time 4.67 seconds
Started Jun 07 06:19:34 PM PDT 24
Finished Jun 07 06:19:39 PM PDT 24
Peak memory 200524 kb
Host smart-9a782d40-796a-4232-a886-5ea844af7f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730408533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.730408533
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.4211045478
Short name T77
Test name
Test status
Simulation time 111370701 ps
CPU time 1.15 seconds
Started Jun 07 06:19:44 PM PDT 24
Finished Jun 07 06:19:46 PM PDT 24
Peak memory 200272 kb
Host smart-b8d02345-b4b1-4996-b259-4a1e7a182b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211045478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.4211045478
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.309698478
Short name T1
Test name
Test status
Simulation time 255745107 ps
CPU time 1.56 seconds
Started Jun 07 06:19:36 PM PDT 24
Finished Jun 07 06:19:38 PM PDT 24
Peak memory 200488 kb
Host smart-82eb32a4-95fa-43cc-9e81-f64436fb4530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309698478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.309698478
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3010405487
Short name T474
Test name
Test status
Simulation time 3317979101 ps
CPU time 15.4 seconds
Started Jun 07 06:19:44 PM PDT 24
Finished Jun 07 06:20:00 PM PDT 24
Peak memory 200656 kb
Host smart-d798c5dc-3bb5-42fd-8b1f-28b2516ef48d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010405487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3010405487
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1967352913
Short name T255
Test name
Test status
Simulation time 411874331 ps
CPU time 2.2 seconds
Started Jun 07 06:19:43 PM PDT 24
Finished Jun 07 06:19:47 PM PDT 24
Peak memory 200212 kb
Host smart-35fcfe5a-75e7-483d-9a24-c9daf99927a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967352913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1967352913
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3472334472
Short name T188
Test name
Test status
Simulation time 159162143 ps
CPU time 1.08 seconds
Started Jun 07 06:19:45 PM PDT 24
Finished Jun 07 06:19:47 PM PDT 24
Peak memory 200364 kb
Host smart-b02c6291-8fde-41b2-910b-b3dc28c2e958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472334472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3472334472
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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