Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8458

1

T1

37

T3

13

T9

15

auto[1]

11436

1

T1

26

T3

1

T5

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6040	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6748	1			T1	20		T2	1		T3	1
reset_info_cp[2]	3101	1			T1	11		T5	1		T6	1
reset_info_cp[4]	4031	1			T1	12		T5	1		T6	1
reset_info_cp[8]	126	1			T1	2		T9	1		T10	2
reset_info_cp[16]	118	1			T9	1		T12	1		T52	1
reset_info_cp[32]	118	1			T9	1		T10	2		T28	1
reset_info_cp[64]	108	1			T3	1		T52	1		T54	1
reset_info_cp[128]	124	1			T3	1		T32	1		T52	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3185	1			T1	12		T9	15		T10	17
reset_info_cp[1]	auto[1]	2943	1			T1	7		T5	1		T6	1
reset_info_cp[2]	auto[0]	941	1			T1	6		T10	7		T12	7
reset_info_cp[2]	auto[1]	2160	1			T1	5		T5	1		T6	1
reset_info_cp[4]	auto[0]	1449	1			T1	9		T10	17		T12	5
reset_info_cp[4]	auto[1]	2582	1			T1	3		T5	1		T6	1
reset_info_cp[8]	auto[0]	50	1			T1	1		T10	1		T27	1
reset_info_cp[8]	auto[1]	76	1			T1	1		T9	1		T10	1
reset_info_cp[16]	auto[0]	57	1			T12	1		T75	1		T80	2
reset_info_cp[16]	auto[1]	61	1			T9	1		T52	1		T75	2
reset_info_cp[32]	auto[0]	56	1			T10	2		T52	1		T123	1
reset_info_cp[32]	auto[1]	62	1			T9	1		T28	1		T33	1
reset_info_cp[64]	auto[0]	44	1			T3	1		T52	1		T55	1
reset_info_cp[64]	auto[1]	64	1			T54	1		T75	1		T80	1
reset_info_cp[128]	auto[0]	50	1			T3	1		T52	1		T80	1
reset_info_cp[128]	auto[1]	74	1			T32	1		T52	1		T80	1