Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T544 /workspace/coverage/default/38.rstmgr_alert_test.2522003017 Jun 09 12:34:19 PM PDT 24 Jun 09 12:34:25 PM PDT 24 72033647 ps
T545 /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1696275765 Jun 09 12:34:16 PM PDT 24 Jun 09 12:34:23 PM PDT 24 206706760 ps
T546 /workspace/coverage/default/32.rstmgr_alert_test.2057291119 Jun 09 12:34:06 PM PDT 24 Jun 09 12:34:08 PM PDT 24 70402908 ps
T547 /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3507026926 Jun 09 12:34:09 PM PDT 24 Jun 09 12:34:12 PM PDT 24 124996719 ps
T548 /workspace/coverage/default/43.rstmgr_smoke.2856618575 Jun 09 12:34:07 PM PDT 24 Jun 09 12:34:15 PM PDT 24 190284949 ps
T64 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.300555744 Jun 09 12:24:47 PM PDT 24 Jun 09 12:24:50 PM PDT 24 141407315 ps
T60 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2317385327 Jun 09 12:25:21 PM PDT 24 Jun 09 12:25:25 PM PDT 24 183451913 ps
T65 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1881313200 Jun 09 12:24:49 PM PDT 24 Jun 09 12:24:53 PM PDT 24 507154175 ps
T67 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.748870632 Jun 09 12:24:56 PM PDT 24 Jun 09 12:24:58 PM PDT 24 186118509 ps
T61 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1889556280 Jun 09 12:24:51 PM PDT 24 Jun 09 12:24:52 PM PDT 24 76288906 ps
T62 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1274453847 Jun 09 12:24:45 PM PDT 24 Jun 09 12:24:47 PM PDT 24 127456838 ps
T63 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2152444679 Jun 09 12:24:51 PM PDT 24 Jun 09 12:24:52 PM PDT 24 86325792 ps
T99 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1864739331 Jun 09 12:25:06 PM PDT 24 Jun 09 12:25:08 PM PDT 24 86581070 ps
T89 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3409497405 Jun 09 12:24:53 PM PDT 24 Jun 09 12:24:54 PM PDT 24 136360186 ps
T70 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3719924954 Jun 09 12:24:52 PM PDT 24 Jun 09 12:24:54 PM PDT 24 140203271 ps
T100 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.446194842 Jun 09 12:24:44 PM PDT 24 Jun 09 12:24:46 PM PDT 24 163485998 ps
T71 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2371722774 Jun 09 12:24:54 PM PDT 24 Jun 09 12:24:56 PM PDT 24 190860906 ps
T90 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3212211893 Jun 09 12:24:46 PM PDT 24 Jun 09 12:24:48 PM PDT 24 62816922 ps
T66 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.994647128 Jun 09 12:24:48 PM PDT 24 Jun 09 12:24:55 PM PDT 24 140583045 ps
T549 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3260976644 Jun 09 12:24:51 PM PDT 24 Jun 09 12:24:52 PM PDT 24 96780135 ps
T91 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2528522214 Jun 09 12:25:00 PM PDT 24 Jun 09 12:25:02 PM PDT 24 192122515 ps
T76 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1742969253 Jun 09 12:24:39 PM PDT 24 Jun 09 12:24:43 PM PDT 24 1097208407 ps
T550 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.4155963117 Jun 09 12:24:44 PM PDT 24 Jun 09 12:24:50 PM PDT 24 1013700706 ps
T92 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.289915553 Jun 09 12:24:58 PM PDT 24 Jun 09 12:25:00 PM PDT 24 101656482 ps
T77 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3065673152 Jun 09 12:24:41 PM PDT 24 Jun 09 12:24:48 PM PDT 24 92456661 ps
T79 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3070884719 Jun 09 12:25:02 PM PDT 24 Jun 09 12:25:06 PM PDT 24 916708951 ps
T93 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2400182747 Jun 09 12:24:51 PM PDT 24 Jun 09 12:24:52 PM PDT 24 101371345 ps
T551 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3112649224 Jun 09 12:24:42 PM PDT 24 Jun 09 12:24:43 PM PDT 24 67907232 ps
T78 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2063685926 Jun 09 12:25:03 PM PDT 24 Jun 09 12:25:05 PM PDT 24 201612383 ps
T98 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.4070872739 Jun 09 12:24:44 PM PDT 24 Jun 09 12:24:47 PM PDT 24 463782455 ps
T552 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.232721066 Jun 09 12:24:44 PM PDT 24 Jun 09 12:24:45 PM PDT 24 135617661 ps
T109 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.4222550303 Jun 09 12:24:52 PM PDT 24 Jun 09 12:24:56 PM PDT 24 914878776 ps
T101 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2743157979 Jun 09 12:25:10 PM PDT 24 Jun 09 12:25:14 PM PDT 24 917377698 ps
T102 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2820937360 Jun 09 12:25:09 PM PDT 24 Jun 09 12:25:11 PM PDT 24 146566362 ps
T110 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2645662534 Jun 09 12:24:42 PM PDT 24 Jun 09 12:24:45 PM PDT 24 415209111 ps
T94 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.351232501 Jun 09 12:24:46 PM PDT 24 Jun 09 12:24:48 PM PDT 24 244623802 ps
T553 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2316702135 Jun 09 12:24:46 PM PDT 24 Jun 09 12:24:47 PM PDT 24 73028404 ps
T112 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.385386593 Jun 09 12:25:04 PM PDT 24 Jun 09 12:25:06 PM PDT 24 145690349 ps
T103 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.289800287 Jun 09 12:25:13 PM PDT 24 Jun 09 12:25:15 PM PDT 24 231414710 ps
T95 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1115662388 Jun 09 12:24:39 PM PDT 24 Jun 09 12:24:41 PM PDT 24 130616319 ps
T96 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2872319032 Jun 09 12:25:06 PM PDT 24 Jun 09 12:25:08 PM PDT 24 62940723 ps
T97 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2097004089 Jun 09 12:25:01 PM PDT 24 Jun 09 12:25:03 PM PDT 24 217374572 ps
T554 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3771982392 Jun 09 12:24:47 PM PDT 24 Jun 09 12:24:49 PM PDT 24 61287828 ps
T555 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3579415267 Jun 09 12:24:52 PM PDT 24 Jun 09 12:24:54 PM PDT 24 102861770 ps
T108 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1333578689 Jun 09 12:24:48 PM PDT 24 Jun 09 12:24:51 PM PDT 24 442821928 ps
T556 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1609486803 Jun 09 12:24:51 PM PDT 24 Jun 09 12:24:53 PM PDT 24 94414995 ps
T557 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1660776666 Jun 09 12:25:05 PM PDT 24 Jun 09 12:25:07 PM PDT 24 89621157 ps
T113 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3358535820 Jun 09 12:25:08 PM PDT 24 Jun 09 12:25:10 PM PDT 24 124695080 ps
T558 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2242780570 Jun 09 12:25:04 PM PDT 24 Jun 09 12:25:06 PM PDT 24 76163789 ps
T105 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2032138097 Jun 09 12:24:48 PM PDT 24 Jun 09 12:24:50 PM PDT 24 184406841 ps
T559 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2781425202 Jun 09 12:25:07 PM PDT 24 Jun 09 12:25:09 PM PDT 24 122782923 ps
T560 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2317374210 Jun 09 12:24:59 PM PDT 24 Jun 09 12:25:01 PM PDT 24 158819618 ps
T561 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.280303220 Jun 09 12:25:06 PM PDT 24 Jun 09 12:25:08 PM PDT 24 160237130 ps
T562 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3143458560 Jun 09 12:24:49 PM PDT 24 Jun 09 12:24:51 PM PDT 24 84030963 ps
T104 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3224744685 Jun 09 12:24:47 PM PDT 24 Jun 09 12:24:50 PM PDT 24 262154723 ps
T563 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3363344077 Jun 09 12:24:50 PM PDT 24 Jun 09 12:24:54 PM PDT 24 399876581 ps
T564 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2854387417 Jun 09 12:25:05 PM PDT 24 Jun 09 12:25:08 PM PDT 24 355492974 ps
T565 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.565975877 Jun 09 12:24:50 PM PDT 24 Jun 09 12:24:52 PM PDT 24 204863962 ps
T107 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2963036803 Jun 09 12:25:01 PM PDT 24 Jun 09 12:25:04 PM PDT 24 877951708 ps
T566 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.4045020670 Jun 09 12:24:48 PM PDT 24 Jun 09 12:24:50 PM PDT 24 147873136 ps
T567 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3378027758 Jun 09 12:24:46 PM PDT 24 Jun 09 12:24:48 PM PDT 24 117857936 ps
T568 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1979233889 Jun 09 12:24:41 PM PDT 24 Jun 09 12:24:47 PM PDT 24 490277944 ps
T569 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.185434842 Jun 09 12:24:40 PM PDT 24 Jun 09 12:24:43 PM PDT 24 495626195 ps
T570 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2492121614 Jun 09 12:25:15 PM PDT 24 Jun 09 12:25:17 PM PDT 24 75330983 ps
T571 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3096683682 Jun 09 12:24:46 PM PDT 24 Jun 09 12:24:48 PM PDT 24 241037960 ps
T572 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2647414212 Jun 09 12:24:40 PM PDT 24 Jun 09 12:24:44 PM PDT 24 950575635 ps
T114 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3346815975 Jun 09 12:24:40 PM PDT 24 Jun 09 12:24:43 PM PDT 24 165874602 ps
T573 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.4235417822 Jun 09 12:24:52 PM PDT 24 Jun 09 12:24:53 PM PDT 24 130778195 ps
T124 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3698146688 Jun 09 12:24:50 PM PDT 24 Jun 09 12:24:53 PM PDT 24 783875357 ps
T574 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.4044571280 Jun 09 12:24:51 PM PDT 24 Jun 09 12:24:53 PM PDT 24 258749898 ps
T115 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.359779312 Jun 09 12:24:52 PM PDT 24 Jun 09 12:24:55 PM PDT 24 198995254 ps
T575 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1184865475 Jun 09 12:25:10 PM PDT 24 Jun 09 12:25:14 PM PDT 24 785991570 ps
T576 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2205065935 Jun 09 12:24:52 PM PDT 24 Jun 09 12:24:54 PM PDT 24 136788242 ps
T577 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3106396170 Jun 09 12:24:47 PM PDT 24 Jun 09 12:24:48 PM PDT 24 65575036 ps
T116 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3314491657 Jun 09 12:24:45 PM PDT 24 Jun 09 12:24:47 PM PDT 24 174732482 ps
T578 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1681252596 Jun 09 12:25:16 PM PDT 24 Jun 09 12:25:20 PM PDT 24 431080636 ps
T111 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2702374768 Jun 09 12:24:56 PM PDT 24 Jun 09 12:24:59 PM PDT 24 485786538 ps
T579 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1928826241 Jun 09 12:24:47 PM PDT 24 Jun 09 12:24:49 PM PDT 24 128114259 ps
T580 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1649430346 Jun 09 12:25:07 PM PDT 24 Jun 09 12:25:09 PM PDT 24 64855896 ps
T581 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.280325180 Jun 09 12:24:47 PM PDT 24 Jun 09 12:24:51 PM PDT 24 791159988 ps
T582 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.444355080 Jun 09 12:24:51 PM PDT 24 Jun 09 12:24:53 PM PDT 24 343608157 ps
T583 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2543285229 Jun 09 12:25:07 PM PDT 24 Jun 09 12:25:11 PM PDT 24 375708124 ps
T584 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2066222313 Jun 09 12:24:45 PM PDT 24 Jun 09 12:24:47 PM PDT 24 118409664 ps
T585 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.134846600 Jun 09 12:24:42 PM PDT 24 Jun 09 12:24:43 PM PDT 24 85148611 ps
T586 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2902062063 Jun 09 12:24:41 PM PDT 24 Jun 09 12:24:43 PM PDT 24 254081853 ps
T587 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2592743210 Jun 09 12:24:47 PM PDT 24 Jun 09 12:24:49 PM PDT 24 188198079 ps
T588 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1307410761 Jun 09 12:25:01 PM PDT 24 Jun 09 12:25:08 PM PDT 24 487988733 ps
T589 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1920788979 Jun 09 12:25:06 PM PDT 24 Jun 09 12:25:09 PM PDT 24 418663364 ps
T590 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2692035928 Jun 09 12:24:41 PM PDT 24 Jun 09 12:24:45 PM PDT 24 271535182 ps
T591 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.4235771197 Jun 09 12:24:39 PM PDT 24 Jun 09 12:24:41 PM PDT 24 59693866 ps
T592 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.385206879 Jun 09 12:25:05 PM PDT 24 Jun 09 12:25:08 PM PDT 24 470656403 ps
T593 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.533301291 Jun 09 12:24:37 PM PDT 24 Jun 09 12:24:39 PM PDT 24 179154062 ps
T594 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1326582559 Jun 09 12:24:39 PM PDT 24 Jun 09 12:24:41 PM PDT 24 59070125 ps
T595 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.492112012 Jun 09 12:24:48 PM PDT 24 Jun 09 12:24:50 PM PDT 24 145406257 ps
T596 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.949065437 Jun 09 12:24:47 PM PDT 24 Jun 09 12:24:50 PM PDT 24 232497658 ps
T597 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2245680283 Jun 09 12:25:12 PM PDT 24 Jun 09 12:25:13 PM PDT 24 81990799 ps
T598 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.4073120826 Jun 09 12:25:12 PM PDT 24 Jun 09 12:25:15 PM PDT 24 282956052 ps
T599 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.312818845 Jun 09 12:24:41 PM PDT 24 Jun 09 12:24:43 PM PDT 24 173120614 ps
T600 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.296191375 Jun 09 12:24:41 PM PDT 24 Jun 09 12:24:43 PM PDT 24 83200747 ps
T601 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3203934321 Jun 09 12:24:49 PM PDT 24 Jun 09 12:24:51 PM PDT 24 55355749 ps
T602 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.496114214 Jun 09 12:25:03 PM PDT 24 Jun 09 12:25:05 PM PDT 24 103991036 ps
T603 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2034851546 Jun 09 12:25:07 PM PDT 24 Jun 09 12:25:10 PM PDT 24 210023414 ps
T604 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.789326619 Jun 09 12:25:09 PM PDT 24 Jun 09 12:25:14 PM PDT 24 506826802 ps
T605 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.4130794460 Jun 09 12:24:53 PM PDT 24 Jun 09 12:24:54 PM PDT 24 97898776 ps
T606 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.4190032496 Jun 09 12:25:07 PM PDT 24 Jun 09 12:25:10 PM PDT 24 269869195 ps
T607 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.663639299 Jun 09 12:24:53 PM PDT 24 Jun 09 12:24:54 PM PDT 24 75290679 ps
T608 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3340216678 Jun 09 12:25:11 PM PDT 24 Jun 09 12:25:13 PM PDT 24 86366730 ps
T609 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.175462804 Jun 09 12:24:38 PM PDT 24 Jun 09 12:24:40 PM PDT 24 156083606 ps
T610 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.999598253 Jun 09 12:25:18 PM PDT 24 Jun 09 12:25:22 PM PDT 24 158653321 ps
T611 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3053533534 Jun 09 12:25:01 PM PDT 24 Jun 09 12:25:03 PM PDT 24 191745459 ps
T106 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.64939226 Jun 09 12:24:53 PM PDT 24 Jun 09 12:24:57 PM PDT 24 943085500 ps
T612 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1556885033 Jun 09 12:24:40 PM PDT 24 Jun 09 12:24:41 PM PDT 24 72240630 ps
T613 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2431750174 Jun 09 12:24:46 PM PDT 24 Jun 09 12:24:48 PM PDT 24 78606577 ps
T614 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2604589597 Jun 09 12:24:55 PM PDT 24 Jun 09 12:24:58 PM PDT 24 505277227 ps
T615 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2294909550 Jun 09 12:24:50 PM PDT 24 Jun 09 12:24:52 PM PDT 24 182541537 ps
T616 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.757639537 Jun 09 12:24:40 PM PDT 24 Jun 09 12:24:44 PM PDT 24 274792880 ps
T617 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.29718578 Jun 09 12:24:41 PM PDT 24 Jun 09 12:24:44 PM PDT 24 183203670 ps
T618 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.546133189 Jun 09 12:24:54 PM PDT 24 Jun 09 12:24:57 PM PDT 24 814828389 ps
T619 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1410299057 Jun 09 12:24:48 PM PDT 24 Jun 09 12:24:49 PM PDT 24 63078459 ps
T620 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.585958794 Jun 09 12:24:57 PM PDT 24 Jun 09 12:25:00 PM PDT 24 178780574 ps

Test location /workspace/coverage/default/36.rstmgr_stress_all.320111495
Short name T10
Test name
Test status
Simulation time 3954055630 ps
CPU time 12.87 seconds
Started Jun 09 12:34:09 PM PDT 24
Finished Jun 09 12:34:24 PM PDT 24
Peak memory 200660 kb
Host smart-186f6789-19dc-465e-97cd-29bff0e9a4f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320111495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.320111495
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1980021430
Short name T50
Test name
Test status
Simulation time 435325306 ps
CPU time 2.34 seconds
Started Jun 09 12:34:03 PM PDT 24
Finished Jun 09 12:34:07 PM PDT 24
Peak memory 200328 kb
Host smart-50d66afa-9b7a-4fed-901f-15b05bc0eacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980021430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1980021430
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2371722774
Short name T71
Test name
Test status
Simulation time 190860906 ps
CPU time 1.3 seconds
Started Jun 09 12:24:54 PM PDT 24
Finished Jun 09 12:24:56 PM PDT 24
Peak memory 208708 kb
Host smart-7d2a1a9b-2084-4906-a69f-be89ecf28dd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371722774 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2371722774
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2566755524
Short name T2
Test name
Test status
Simulation time 16622455835 ps
CPU time 25.69 seconds
Started Jun 09 12:33:23 PM PDT 24
Finished Jun 09 12:33:49 PM PDT 24
Peak memory 221684 kb
Host smart-73fd3b35-d80a-4d3e-9a94-b7f4c110bb66
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566755524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2566755524
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.4093969316
Short name T9
Test name
Test status
Simulation time 1219205333 ps
CPU time 5.25 seconds
Started Jun 09 12:33:31 PM PDT 24
Finished Jun 09 12:33:37 PM PDT 24
Peak memory 217912 kb
Host smart-9a28aab8-f0bf-43bf-a37f-0689cb4a6e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093969316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.4093969316
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2775790877
Short name T80
Test name
Test status
Simulation time 15248535407 ps
CPU time 49.97 seconds
Started Jun 09 12:34:19 PM PDT 24
Finished Jun 09 12:35:09 PM PDT 24
Peak memory 210460 kb
Host smart-87fcf39b-0f59-46b8-af7d-1ec5f2b07700
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775790877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2775790877
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2743157979
Short name T101
Test name
Test status
Simulation time 917377698 ps
CPU time 3.2 seconds
Started Jun 09 12:25:10 PM PDT 24
Finished Jun 09 12:25:14 PM PDT 24
Peak memory 200536 kb
Host smart-fe49643c-f05c-4b00-97ae-974d5c0afa92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743157979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2743157979
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2032138097
Short name T105
Test name
Test status
Simulation time 184406841 ps
CPU time 1.83 seconds
Started Jun 09 12:24:48 PM PDT 24
Finished Jun 09 12:24:50 PM PDT 24
Peak memory 208684 kb
Host smart-835ab2ef-8953-4852-ae51-2462ea33ad8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032138097 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2032138097
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1929711433
Short name T160
Test name
Test status
Simulation time 176706669 ps
CPU time 1.13 seconds
Started Jun 09 12:34:19 PM PDT 24
Finished Jun 09 12:34:20 PM PDT 24
Peak memory 200336 kb
Host smart-86d369fa-0fe7-4f2a-b34f-bfd52911e832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929711433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1929711433
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.801652756
Short name T45
Test name
Test status
Simulation time 2171042581 ps
CPU time 7.71 seconds
Started Jun 09 12:34:16 PM PDT 24
Finished Jun 09 12:34:24 PM PDT 24
Peak memory 218120 kb
Host smart-0c80f776-2e86-47e4-a448-ed898ca62dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801652756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.801652756
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.399789785
Short name T49
Test name
Test status
Simulation time 74820457 ps
CPU time 0.76 seconds
Started Jun 09 12:33:22 PM PDT 24
Finished Jun 09 12:33:28 PM PDT 24
Peak memory 200164 kb
Host smart-427f187f-7449-4aaf-8c9b-df5534ded26b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399789785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.399789785
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.385206879
Short name T592
Test name
Test status
Simulation time 470656403 ps
CPU time 2.03 seconds
Started Jun 09 12:25:05 PM PDT 24
Finished Jun 09 12:25:08 PM PDT 24
Peak memory 200452 kb
Host smart-56771f3b-6fa0-46ab-b0ba-81d94c2ed603
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385206879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.385206879
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2152444679
Short name T63
Test name
Test status
Simulation time 86325792 ps
CPU time 1 seconds
Started Jun 09 12:24:51 PM PDT 24
Finished Jun 09 12:24:52 PM PDT 24
Peak memory 200240 kb
Host smart-0e824c89-5cda-45ae-a7e5-d6974b87ca79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152444679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2152444679
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3145309719
Short name T142
Test name
Test status
Simulation time 184829807 ps
CPU time 1.28 seconds
Started Jun 09 12:33:48 PM PDT 24
Finished Jun 09 12:33:50 PM PDT 24
Peak memory 200320 kb
Host smart-83ec33ad-ba95-4134-9fd8-c7a0922326ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145309719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3145309719
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3346815975
Short name T114
Test name
Test status
Simulation time 165874602 ps
CPU time 2.28 seconds
Started Jun 09 12:24:40 PM PDT 24
Finished Jun 09 12:24:43 PM PDT 24
Peak memory 208628 kb
Host smart-be91e8a2-32bd-4241-8abb-8d6f7c549db3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346815975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3346815975
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.3754860889
Short name T313
Test name
Test status
Simulation time 1893169651 ps
CPU time 6.85 seconds
Started Jun 09 12:33:20 PM PDT 24
Finished Jun 09 12:33:27 PM PDT 24
Peak memory 217912 kb
Host smart-fdcf8d25-cf98-4b2b-ba84-0f8e56f44270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754860889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3754860889
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2811456926
Short name T23
Test name
Test status
Simulation time 76565850 ps
CPU time 0.77 seconds
Started Jun 09 12:33:54 PM PDT 24
Finished Jun 09 12:33:55 PM PDT 24
Peak memory 200156 kb
Host smart-5b1f593e-095b-4797-9f97-79848bab5fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811456926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2811456926
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2963036803
Short name T107
Test name
Test status
Simulation time 877951708 ps
CPU time 3.25 seconds
Started Jun 09 12:25:01 PM PDT 24
Finished Jun 09 12:25:04 PM PDT 24
Peak memory 200508 kb
Host smart-ac1c4f0c-eb67-4535-82f1-1bfd51485275
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963036803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2963036803
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.64939226
Short name T106
Test name
Test status
Simulation time 943085500 ps
CPU time 3.31 seconds
Started Jun 09 12:24:53 PM PDT 24
Finished Jun 09 12:24:57 PM PDT 24
Peak memory 200460 kb
Host smart-2934cd70-d646-43fc-b538-650064a1043f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64939226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.64939226
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2424052883
Short name T54
Test name
Test status
Simulation time 126580672 ps
CPU time 1.26 seconds
Started Jun 09 12:33:16 PM PDT 24
Finished Jun 09 12:33:18 PM PDT 24
Peak memory 200504 kb
Host smart-510982ae-a2ef-40a9-a770-3c205bada123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424052883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2424052883
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.999598253
Short name T610
Test name
Test status
Simulation time 158653321 ps
CPU time 1.92 seconds
Started Jun 09 12:25:18 PM PDT 24
Finished Jun 09 12:25:22 PM PDT 24
Peak memory 208496 kb
Host smart-802371e3-8ffc-4283-b875-57e50e5aa04f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999598253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.999598253
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2692035928
Short name T590
Test name
Test status
Simulation time 271535182 ps
CPU time 3.08 seconds
Started Jun 09 12:24:41 PM PDT 24
Finished Jun 09 12:24:45 PM PDT 24
Peak memory 200388 kb
Host smart-ea4781ab-5d5a-4729-b38c-d24ca39faf73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692035928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2
692035928
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3378027758
Short name T567
Test name
Test status
Simulation time 117857936 ps
CPU time 0.91 seconds
Started Jun 09 12:24:46 PM PDT 24
Finished Jun 09 12:24:48 PM PDT 24
Peak memory 200256 kb
Host smart-7f8f7d2f-ba0d-4ffa-a299-39ab683210fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378027758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
378027758
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.232721066
Short name T552
Test name
Test status
Simulation time 135617661 ps
CPU time 1.1 seconds
Started Jun 09 12:24:44 PM PDT 24
Finished Jun 09 12:24:45 PM PDT 24
Peak memory 210656 kb
Host smart-c5802762-3d97-4de6-9267-e74f4869de59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232721066 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.232721066
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.4235771197
Short name T591
Test name
Test status
Simulation time 59693866 ps
CPU time 0.8 seconds
Started Jun 09 12:24:39 PM PDT 24
Finished Jun 09 12:24:41 PM PDT 24
Peak memory 200104 kb
Host smart-b85b2dc7-b857-4839-8523-2c2c68570f2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235771197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.4235771197
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.312818845
Short name T599
Test name
Test status
Simulation time 173120614 ps
CPU time 1.32 seconds
Started Jun 09 12:24:41 PM PDT 24
Finished Jun 09 12:24:43 PM PDT 24
Peak memory 200428 kb
Host smart-cc29cfd7-d0ec-45f4-b5e5-94ff226c7c16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312818845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sam
e_csr_outstanding.312818845
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1742969253
Short name T76
Test name
Test status
Simulation time 1097208407 ps
CPU time 3.51 seconds
Started Jun 09 12:24:39 PM PDT 24
Finished Jun 09 12:24:43 PM PDT 24
Peak memory 200392 kb
Host smart-8273f923-7685-4007-87d0-f68f934d0245
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742969253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1742969253
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.949065437
Short name T596
Test name
Test status
Simulation time 232497658 ps
CPU time 1.68 seconds
Started Jun 09 12:24:47 PM PDT 24
Finished Jun 09 12:24:50 PM PDT 24
Peak memory 200356 kb
Host smart-0042e0ed-86d9-4e12-9272-2f2a67e88def
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949065437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.949065437
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.4155963117
Short name T550
Test name
Test status
Simulation time 1013700706 ps
CPU time 4.85 seconds
Started Jun 09 12:24:44 PM PDT 24
Finished Jun 09 12:24:50 PM PDT 24
Peak memory 200488 kb
Host smart-dc5fa98d-a570-478f-8825-899a94121268
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155963117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.4
155963117
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.134846600
Short name T585
Test name
Test status
Simulation time 85148611 ps
CPU time 0.8 seconds
Started Jun 09 12:24:42 PM PDT 24
Finished Jun 09 12:24:43 PM PDT 24
Peak memory 200068 kb
Host smart-b392f183-29de-4139-b464-c8565818ed14
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134846600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.134846600
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.533301291
Short name T593
Test name
Test status
Simulation time 179154062 ps
CPU time 1.73 seconds
Started Jun 09 12:24:37 PM PDT 24
Finished Jun 09 12:24:39 PM PDT 24
Peak memory 208960 kb
Host smart-f5839c4b-f628-4379-a0b3-d9649c705550
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533301291 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.533301291
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1326582559
Short name T594
Test name
Test status
Simulation time 59070125 ps
CPU time 0.83 seconds
Started Jun 09 12:24:39 PM PDT 24
Finished Jun 09 12:24:41 PM PDT 24
Peak memory 200512 kb
Host smart-c915cc87-3728-4a2a-84dd-f880413494bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326582559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1326582559
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1115662388
Short name T95
Test name
Test status
Simulation time 130616319 ps
CPU time 1.23 seconds
Started Jun 09 12:24:39 PM PDT 24
Finished Jun 09 12:24:41 PM PDT 24
Peak memory 200668 kb
Host smart-6e37a7d5-3480-43c9-a35b-5133dd6df769
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115662388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1115662388
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.29718578
Short name T617
Test name
Test status
Simulation time 183203670 ps
CPU time 2.43 seconds
Started Jun 09 12:24:41 PM PDT 24
Finished Jun 09 12:24:44 PM PDT 24
Peak memory 208584 kb
Host smart-49534426-2551-43b2-a8b7-96982261adb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29718578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.29718578
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.185434842
Short name T569
Test name
Test status
Simulation time 495626195 ps
CPU time 2.03 seconds
Started Jun 09 12:24:40 PM PDT 24
Finished Jun 09 12:24:43 PM PDT 24
Peak memory 200420 kb
Host smart-ce475430-5a6a-4868-9c95-c9ebf8d2bdaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185434842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
185434842
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2592743210
Short name T587
Test name
Test status
Simulation time 188198079 ps
CPU time 1.21 seconds
Started Jun 09 12:24:47 PM PDT 24
Finished Jun 09 12:24:49 PM PDT 24
Peak memory 208460 kb
Host smart-84251df2-c34c-4417-8d96-3c9d1fc70ee6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592743210 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2592743210
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2872319032
Short name T96
Test name
Test status
Simulation time 62940723 ps
CPU time 0.82 seconds
Started Jun 09 12:25:06 PM PDT 24
Finished Jun 09 12:25:08 PM PDT 24
Peak memory 199956 kb
Host smart-a22cc9d9-8c5c-4d3b-b964-736c1fdb25eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872319032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2872319032
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.496114214
Short name T602
Test name
Test status
Simulation time 103991036 ps
CPU time 1.21 seconds
Started Jun 09 12:25:03 PM PDT 24
Finished Jun 09 12:25:05 PM PDT 24
Peak memory 200464 kb
Host smart-1e61392b-e2fc-4d06-8468-ac424240bc3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496114214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.496114214
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3358535820
Short name T113
Test name
Test status
Simulation time 124695080 ps
CPU time 1.68 seconds
Started Jun 09 12:25:08 PM PDT 24
Finished Jun 09 12:25:10 PM PDT 24
Peak memory 216752 kb
Host smart-cf9632e0-c637-499a-883a-ae90ac3225d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358535820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3358535820
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.280303220
Short name T561
Test name
Test status
Simulation time 160237130 ps
CPU time 1.46 seconds
Started Jun 09 12:25:06 PM PDT 24
Finished Jun 09 12:25:08 PM PDT 24
Peak memory 208496 kb
Host smart-6e4dc788-bf6e-4f70-8e94-3e1acdfdc8c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280303220 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.280303220
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1410299057
Short name T619
Test name
Test status
Simulation time 63078459 ps
CPU time 0.76 seconds
Started Jun 09 12:24:48 PM PDT 24
Finished Jun 09 12:24:49 PM PDT 24
Peak memory 200116 kb
Host smart-2345a38b-7e49-4459-abca-14765c1907c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410299057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1410299057
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.492112012
Short name T595
Test name
Test status
Simulation time 145406257 ps
CPU time 1.09 seconds
Started Jun 09 12:24:48 PM PDT 24
Finished Jun 09 12:24:50 PM PDT 24
Peak memory 200184 kb
Host smart-45d43114-0e1e-44c5-aa6b-c31b97aaf28c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492112012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sa
me_csr_outstanding.492112012
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1881313200
Short name T65
Test name
Test status
Simulation time 507154175 ps
CPU time 3.66 seconds
Started Jun 09 12:24:49 PM PDT 24
Finished Jun 09 12:24:53 PM PDT 24
Peak memory 208640 kb
Host smart-188bf0c4-a261-455a-948c-f15754a38f6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881313200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1881313200
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2034851546
Short name T603
Test name
Test status
Simulation time 210023414 ps
CPU time 2.03 seconds
Started Jun 09 12:25:07 PM PDT 24
Finished Jun 09 12:25:10 PM PDT 24
Peak memory 208688 kb
Host smart-b4b3cb78-20b1-4ac4-b62a-8aaa8a6d3518
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034851546 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2034851546
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1864739331
Short name T99
Test name
Test status
Simulation time 86581070 ps
CPU time 0.85 seconds
Started Jun 09 12:25:06 PM PDT 24
Finished Jun 09 12:25:08 PM PDT 24
Peak memory 200124 kb
Host smart-170878fb-9ac9-4d6f-a601-a6694e86bf5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864739331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1864739331
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.289915553
Short name T92
Test name
Test status
Simulation time 101656482 ps
CPU time 1.23 seconds
Started Jun 09 12:24:58 PM PDT 24
Finished Jun 09 12:25:00 PM PDT 24
Peak memory 200384 kb
Host smart-739bd6d8-8b70-469d-b147-76206f86ee5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289915553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.289915553
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.4190032496
Short name T606
Test name
Test status
Simulation time 269869195 ps
CPU time 2 seconds
Started Jun 09 12:25:07 PM PDT 24
Finished Jun 09 12:25:10 PM PDT 24
Peak memory 216796 kb
Host smart-f321b664-4144-4fd1-afe4-09a775d4ab7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190032496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.4190032496
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3698146688
Short name T124
Test name
Test status
Simulation time 783875357 ps
CPU time 3.17 seconds
Started Jun 09 12:24:50 PM PDT 24
Finished Jun 09 12:24:53 PM PDT 24
Peak memory 200452 kb
Host smart-8487e579-42a9-4e26-a52f-eb14db421e52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698146688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.3698146688
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3719924954
Short name T70
Test name
Test status
Simulation time 140203271 ps
CPU time 1.07 seconds
Started Jun 09 12:24:52 PM PDT 24
Finished Jun 09 12:24:54 PM PDT 24
Peak memory 200312 kb
Host smart-b397814d-d3ae-4a41-9162-a15cf76ece16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719924954 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3719924954
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3260976644
Short name T549
Test name
Test status
Simulation time 96780135 ps
CPU time 0.9 seconds
Started Jun 09 12:24:51 PM PDT 24
Finished Jun 09 12:24:52 PM PDT 24
Peak memory 200164 kb
Host smart-cd24c7fc-e79c-4eca-88ac-fbf256933795
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260976644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3260976644
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2205065935
Short name T576
Test name
Test status
Simulation time 136788242 ps
CPU time 1.15 seconds
Started Jun 09 12:24:52 PM PDT 24
Finished Jun 09 12:24:54 PM PDT 24
Peak memory 200180 kb
Host smart-9e303013-d8e6-404f-95b9-15617400ed06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205065935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2205065935
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.444355080
Short name T582
Test name
Test status
Simulation time 343608157 ps
CPU time 2.3 seconds
Started Jun 09 12:24:51 PM PDT 24
Finished Jun 09 12:24:53 PM PDT 24
Peak memory 208940 kb
Host smart-092f46a1-d10d-42fe-94ee-0c806f45e659
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444355080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.444355080
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2702374768
Short name T111
Test name
Test status
Simulation time 485786538 ps
CPU time 1.95 seconds
Started Jun 09 12:24:56 PM PDT 24
Finished Jun 09 12:24:59 PM PDT 24
Peak memory 200484 kb
Host smart-617f4e6c-aaf0-4d7d-b424-49458f0f2991
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702374768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.2702374768
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2294909550
Short name T615
Test name
Test status
Simulation time 182541537 ps
CPU time 1.28 seconds
Started Jun 09 12:24:50 PM PDT 24
Finished Jun 09 12:24:52 PM PDT 24
Peak memory 208408 kb
Host smart-d97edc0b-73c7-4b5f-9397-f4e7e9aa5bb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294909550 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2294909550
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2245680283
Short name T597
Test name
Test status
Simulation time 81990799 ps
CPU time 0.87 seconds
Started Jun 09 12:25:12 PM PDT 24
Finished Jun 09 12:25:13 PM PDT 24
Peak memory 200112 kb
Host smart-22b099d8-c115-406b-810c-4bb073db61b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245680283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2245680283
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2543285229
Short name T583
Test name
Test status
Simulation time 375708124 ps
CPU time 3.01 seconds
Started Jun 09 12:25:07 PM PDT 24
Finished Jun 09 12:25:11 PM PDT 24
Peak memory 208588 kb
Host smart-59d2098e-bd8f-4b37-bdc2-ca001c6681bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543285229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2543285229
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.4222550303
Short name T109
Test name
Test status
Simulation time 914878776 ps
CPU time 3.21 seconds
Started Jun 09 12:24:52 PM PDT 24
Finished Jun 09 12:24:56 PM PDT 24
Peak memory 200480 kb
Host smart-b444cff4-bd6f-400f-a49a-6359d3ada3d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222550303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.4222550303
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.385386593
Short name T112
Test name
Test status
Simulation time 145690349 ps
CPU time 1.2 seconds
Started Jun 09 12:25:04 PM PDT 24
Finished Jun 09 12:25:06 PM PDT 24
Peak memory 208460 kb
Host smart-34af57bd-f645-4629-ae38-62c5a2a7450f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385386593 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.385386593
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2242780570
Short name T558
Test name
Test status
Simulation time 76163789 ps
CPU time 0.89 seconds
Started Jun 09 12:25:04 PM PDT 24
Finished Jun 09 12:25:06 PM PDT 24
Peak memory 200156 kb
Host smart-2c2340af-6f5c-434b-941e-ad4456e36d8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242780570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2242780570
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3409497405
Short name T89
Test name
Test status
Simulation time 136360186 ps
CPU time 1.12 seconds
Started Jun 09 12:24:53 PM PDT 24
Finished Jun 09 12:24:54 PM PDT 24
Peak memory 200212 kb
Host smart-d5e112b5-0e72-4c7c-9d40-80ed84b1a3a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409497405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.3409497405
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.359779312
Short name T115
Test name
Test status
Simulation time 198995254 ps
CPU time 2.77 seconds
Started Jun 09 12:24:52 PM PDT 24
Finished Jun 09 12:24:55 PM PDT 24
Peak memory 208572 kb
Host smart-621a7e6b-d1d3-4fa0-98a7-1db5ed29dedc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359779312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.359779312
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2317385327
Short name T60
Test name
Test status
Simulation time 183451913 ps
CPU time 1.17 seconds
Started Jun 09 12:25:21 PM PDT 24
Finished Jun 09 12:25:25 PM PDT 24
Peak memory 208444 kb
Host smart-f2606dd3-9344-4cd2-a57f-17dd819e1735
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317385327 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2317385327
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3340216678
Short name T608
Test name
Test status
Simulation time 86366730 ps
CPU time 0.87 seconds
Started Jun 09 12:25:11 PM PDT 24
Finished Jun 09 12:25:13 PM PDT 24
Peak memory 200172 kb
Host smart-935d2c38-5f8c-4ccb-85fa-2ff0284feb3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340216678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3340216678
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2097004089
Short name T97
Test name
Test status
Simulation time 217374572 ps
CPU time 1.46 seconds
Started Jun 09 12:25:01 PM PDT 24
Finished Jun 09 12:25:03 PM PDT 24
Peak memory 200392 kb
Host smart-4b846cea-242a-421d-98cf-bda9d9497546
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097004089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2097004089
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.4044571280
Short name T574
Test name
Test status
Simulation time 258749898 ps
CPU time 2 seconds
Started Jun 09 12:24:51 PM PDT 24
Finished Jun 09 12:24:53 PM PDT 24
Peak memory 208552 kb
Host smart-44a37ea0-76e5-4d96-a5e5-7c3e3e8f6eef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044571280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.4044571280
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1184865475
Short name T575
Test name
Test status
Simulation time 785991570 ps
CPU time 2.9 seconds
Started Jun 09 12:25:10 PM PDT 24
Finished Jun 09 12:25:14 PM PDT 24
Peak memory 200500 kb
Host smart-d0a81ca3-be30-4f35-8b10-6c5642bb2d90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184865475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1184865475
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2063685926
Short name T78
Test name
Test status
Simulation time 201612383 ps
CPU time 1.36 seconds
Started Jun 09 12:25:03 PM PDT 24
Finished Jun 09 12:25:05 PM PDT 24
Peak memory 208480 kb
Host smart-383cfcc8-d6bd-4313-8d5f-8bc5dd91b3d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063685926 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2063685926
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1889556280
Short name T61
Test name
Test status
Simulation time 76288906 ps
CPU time 0.91 seconds
Started Jun 09 12:24:51 PM PDT 24
Finished Jun 09 12:24:52 PM PDT 24
Peak memory 200184 kb
Host smart-f4766a6d-930d-42b7-b82b-ef0caece208a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889556280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1889556280
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.4235417822
Short name T573
Test name
Test status
Simulation time 130778195 ps
CPU time 1.11 seconds
Started Jun 09 12:24:52 PM PDT 24
Finished Jun 09 12:24:53 PM PDT 24
Peak memory 200192 kb
Host smart-bf1019fe-3b9a-472d-a11f-6d2277f0d9f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235417822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.4235417822
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3363344077
Short name T563
Test name
Test status
Simulation time 399876581 ps
CPU time 2.96 seconds
Started Jun 09 12:24:50 PM PDT 24
Finished Jun 09 12:24:54 PM PDT 24
Peak memory 208580 kb
Host smart-2a44767e-6575-4271-b8c0-d9af3c415284
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363344077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3363344077
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3579415267
Short name T555
Test name
Test status
Simulation time 102861770 ps
CPU time 0.92 seconds
Started Jun 09 12:24:52 PM PDT 24
Finished Jun 09 12:24:54 PM PDT 24
Peak memory 200276 kb
Host smart-44f88e0c-49af-4cd8-88e4-0b56402e1d90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579415267 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3579415267
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1649430346
Short name T580
Test name
Test status
Simulation time 64855896 ps
CPU time 0.84 seconds
Started Jun 09 12:25:07 PM PDT 24
Finished Jun 09 12:25:09 PM PDT 24
Peak memory 200168 kb
Host smart-49dca5fa-c4e3-4797-af54-9a8275be07bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649430346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1649430346
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2400182747
Short name T93
Test name
Test status
Simulation time 101371345 ps
CPU time 1.23 seconds
Started Jun 09 12:24:51 PM PDT 24
Finished Jun 09 12:24:52 PM PDT 24
Peak memory 200448 kb
Host smart-f5c6ea58-8ac0-451b-ac26-73107f55cc97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400182747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2400182747
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.748870632
Short name T67
Test name
Test status
Simulation time 186118509 ps
CPU time 1.53 seconds
Started Jun 09 12:24:56 PM PDT 24
Finished Jun 09 12:24:58 PM PDT 24
Peak memory 208568 kb
Host smart-5d122e23-d503-46eb-a410-a9c35b21ae0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748870632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.748870632
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1681252596
Short name T578
Test name
Test status
Simulation time 431080636 ps
CPU time 1.94 seconds
Started Jun 09 12:25:16 PM PDT 24
Finished Jun 09 12:25:20 PM PDT 24
Peak memory 200440 kb
Host smart-27cf291e-7a68-4d01-8583-03a2b23097b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681252596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1681252596
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1660776666
Short name T557
Test name
Test status
Simulation time 89621157 ps
CPU time 0.87 seconds
Started Jun 09 12:25:05 PM PDT 24
Finished Jun 09 12:25:07 PM PDT 24
Peak memory 200144 kb
Host smart-8b55924f-337a-4cea-8ffd-ffe951a89f7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660776666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1660776666
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2492121614
Short name T570
Test name
Test status
Simulation time 75330983 ps
CPU time 0.9 seconds
Started Jun 09 12:25:15 PM PDT 24
Finished Jun 09 12:25:17 PM PDT 24
Peak memory 200184 kb
Host smart-5da1ff23-97a7-484d-99b5-33e196947a84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492121614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.2492121614
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.289800287
Short name T103
Test name
Test status
Simulation time 231414710 ps
CPU time 1.83 seconds
Started Jun 09 12:25:13 PM PDT 24
Finished Jun 09 12:25:15 PM PDT 24
Peak memory 210744 kb
Host smart-309f2d2f-caa3-4b72-b81e-d7cd2834d91f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289800287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.289800287
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.546133189
Short name T618
Test name
Test status
Simulation time 814828389 ps
CPU time 2.81 seconds
Started Jun 09 12:24:54 PM PDT 24
Finished Jun 09 12:24:57 PM PDT 24
Peak memory 200440 kb
Host smart-c4bb9a14-2a0e-4bed-a6ab-74ea5263e8b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546133189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.546133189
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.175462804
Short name T609
Test name
Test status
Simulation time 156083606 ps
CPU time 1.98 seconds
Started Jun 09 12:24:38 PM PDT 24
Finished Jun 09 12:24:40 PM PDT 24
Peak memory 200312 kb
Host smart-72d44155-09d0-4c9f-9de1-ff1b6c6000ed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175462804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.175462804
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1979233889
Short name T568
Test name
Test status
Simulation time 490277944 ps
CPU time 5.4 seconds
Started Jun 09 12:24:41 PM PDT 24
Finished Jun 09 12:24:47 PM PDT 24
Peak memory 200380 kb
Host smart-5f0621bc-91b1-4078-bf15-8a2558385f90
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979233889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
979233889
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1274453847
Short name T62
Test name
Test status
Simulation time 127456838 ps
CPU time 0.92 seconds
Started Jun 09 12:24:45 PM PDT 24
Finished Jun 09 12:24:47 PM PDT 24
Peak memory 200236 kb
Host smart-8956ae5d-f844-4a6a-bd48-06e4b109ad98
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274453847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
274453847
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3065673152
Short name T77
Test name
Test status
Simulation time 92456661 ps
CPU time 0.89 seconds
Started Jun 09 12:24:41 PM PDT 24
Finished Jun 09 12:24:48 PM PDT 24
Peak memory 200204 kb
Host smart-ba852dd7-b400-4fba-839d-2de6707bdb68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065673152 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.3065673152
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3112649224
Short name T551
Test name
Test status
Simulation time 67907232 ps
CPU time 0.76 seconds
Started Jun 09 12:24:42 PM PDT 24
Finished Jun 09 12:24:43 PM PDT 24
Peak memory 200108 kb
Host smart-bfd996cc-e7b3-4d6b-99d4-82662e4a923e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112649224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3112649224
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.351232501
Short name T94
Test name
Test status
Simulation time 244623802 ps
CPU time 1.49 seconds
Started Jun 09 12:24:46 PM PDT 24
Finished Jun 09 12:24:48 PM PDT 24
Peak memory 200408 kb
Host smart-b6060da1-08bf-417c-861b-bdc01d7e11a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351232501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.351232501
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2902062063
Short name T586
Test name
Test status
Simulation time 254081853 ps
CPU time 2.03 seconds
Started Jun 09 12:24:41 PM PDT 24
Finished Jun 09 12:24:43 PM PDT 24
Peak memory 200424 kb
Host smart-7b7fb980-6085-4470-a04a-e605b6939c49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902062063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2902062063
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2647414212
Short name T572
Test name
Test status
Simulation time 950575635 ps
CPU time 3.38 seconds
Started Jun 09 12:24:40 PM PDT 24
Finished Jun 09 12:24:44 PM PDT 24
Peak memory 200388 kb
Host smart-93ee436b-3c8a-4df6-aecd-288965b74500
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647414212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.2647414212
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.446194842
Short name T100
Test name
Test status
Simulation time 163485998 ps
CPU time 2.07 seconds
Started Jun 09 12:24:44 PM PDT 24
Finished Jun 09 12:24:46 PM PDT 24
Peak memory 200416 kb
Host smart-15793ca9-e7f0-4077-8c76-a3c6e2d78698
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446194842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.446194842
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.757639537
Short name T616
Test name
Test status
Simulation time 274792880 ps
CPU time 3.15 seconds
Started Jun 09 12:24:40 PM PDT 24
Finished Jun 09 12:24:44 PM PDT 24
Peak memory 200408 kb
Host smart-68c7b685-b1e7-46e2-be39-c24a3968236c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757639537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.757639537
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.296191375
Short name T600
Test name
Test status
Simulation time 83200747 ps
CPU time 0.81 seconds
Started Jun 09 12:24:41 PM PDT 24
Finished Jun 09 12:24:43 PM PDT 24
Peak memory 200140 kb
Host smart-80d69f43-0543-46f8-8876-47da6b97c0bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296191375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.296191375
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2066222313
Short name T584
Test name
Test status
Simulation time 118409664 ps
CPU time 0.96 seconds
Started Jun 09 12:24:45 PM PDT 24
Finished Jun 09 12:24:47 PM PDT 24
Peak memory 200244 kb
Host smart-8e8242a5-9ec0-481c-b258-afe7e71f9c39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066222313 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2066222313
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1556885033
Short name T612
Test name
Test status
Simulation time 72240630 ps
CPU time 0.81 seconds
Started Jun 09 12:24:40 PM PDT 24
Finished Jun 09 12:24:41 PM PDT 24
Peak memory 200144 kb
Host smart-bf973712-2181-4099-8d0c-cc7eb50d204c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556885033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1556885033
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.565975877
Short name T565
Test name
Test status
Simulation time 204863962 ps
CPU time 1.56 seconds
Started Jun 09 12:24:50 PM PDT 24
Finished Jun 09 12:24:52 PM PDT 24
Peak memory 200308 kb
Host smart-cdf460f4-5a57-458f-863b-aea75d02754b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565975877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam
e_csr_outstanding.565975877
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3314491657
Short name T116
Test name
Test status
Simulation time 174732482 ps
CPU time 2.31 seconds
Started Jun 09 12:24:45 PM PDT 24
Finished Jun 09 12:24:47 PM PDT 24
Peak memory 208532 kb
Host smart-f0f90a28-73f0-4e19-b707-8f8871d301ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314491657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3314491657
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2645662534
Short name T110
Test name
Test status
Simulation time 415209111 ps
CPU time 1.95 seconds
Started Jun 09 12:24:42 PM PDT 24
Finished Jun 09 12:24:45 PM PDT 24
Peak memory 200368 kb
Host smart-9bd44289-48df-43e4-bb77-9267471a0021
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645662534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2645662534
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2854387417
Short name T564
Test name
Test status
Simulation time 355492974 ps
CPU time 2.36 seconds
Started Jun 09 12:25:05 PM PDT 24
Finished Jun 09 12:25:08 PM PDT 24
Peak memory 200456 kb
Host smart-b0081c33-c5a5-418d-be85-18ff93888406
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854387417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
854387417
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1307410761
Short name T588
Test name
Test status
Simulation time 487988733 ps
CPU time 6.07 seconds
Started Jun 09 12:25:01 PM PDT 24
Finished Jun 09 12:25:08 PM PDT 24
Peak memory 200436 kb
Host smart-c10c4f54-089b-4fca-b299-41cb076fb46b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307410761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
307410761
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.4130794460
Short name T605
Test name
Test status
Simulation time 97898776 ps
CPU time 0.81 seconds
Started Jun 09 12:24:53 PM PDT 24
Finished Jun 09 12:24:54 PM PDT 24
Peak memory 200212 kb
Host smart-b3e9fae3-4ac4-4941-9e2e-6e9f069a6d31
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130794460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.4
130794460
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.994647128
Short name T66
Test name
Test status
Simulation time 140583045 ps
CPU time 1.48 seconds
Started Jun 09 12:24:48 PM PDT 24
Finished Jun 09 12:24:55 PM PDT 24
Peak memory 208600 kb
Host smart-9156211c-94fa-4e67-84b3-4fe668f988c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994647128 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.994647128
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3106396170
Short name T577
Test name
Test status
Simulation time 65575036 ps
CPU time 0.78 seconds
Started Jun 09 12:24:47 PM PDT 24
Finished Jun 09 12:24:48 PM PDT 24
Peak memory 200180 kb
Host smart-4e1fdb37-e597-4270-a9bf-f94c7f4ac981
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106396170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3106396170
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2431750174
Short name T613
Test name
Test status
Simulation time 78606577 ps
CPU time 1.01 seconds
Started Jun 09 12:24:46 PM PDT 24
Finished Jun 09 12:24:48 PM PDT 24
Peak memory 200220 kb
Host smart-df1a7e56-49be-44d4-aa56-55bcb3fd9ad9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431750174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.2431750174
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.300555744
Short name T64
Test name
Test status
Simulation time 141407315 ps
CPU time 2.02 seconds
Started Jun 09 12:24:47 PM PDT 24
Finished Jun 09 12:24:50 PM PDT 24
Peak memory 208672 kb
Host smart-dbc62f33-5d2b-4826-9515-77da3d180aa7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300555744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.300555744
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3070884719
Short name T79
Test name
Test status
Simulation time 916708951 ps
CPU time 3.29 seconds
Started Jun 09 12:25:02 PM PDT 24
Finished Jun 09 12:25:06 PM PDT 24
Peak memory 200436 kb
Host smart-43957b24-451b-4fea-b63e-eac5c0c16934
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070884719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3070884719
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.4045020670
Short name T566
Test name
Test status
Simulation time 147873136 ps
CPU time 1.33 seconds
Started Jun 09 12:24:48 PM PDT 24
Finished Jun 09 12:24:50 PM PDT 24
Peak memory 208440 kb
Host smart-6376003a-442e-4df4-9bc8-39c85e424625
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045020670 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.4045020670
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.663639299
Short name T607
Test name
Test status
Simulation time 75290679 ps
CPU time 0.85 seconds
Started Jun 09 12:24:53 PM PDT 24
Finished Jun 09 12:24:54 PM PDT 24
Peak memory 200124 kb
Host smart-73b9834c-1b87-4d39-a9b7-e1f690f877a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663639299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.663639299
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2528522214
Short name T91
Test name
Test status
Simulation time 192122515 ps
CPU time 1.36 seconds
Started Jun 09 12:25:00 PM PDT 24
Finished Jun 09 12:25:02 PM PDT 24
Peak memory 200408 kb
Host smart-c2fa3370-80a8-4982-9d23-80005cd3adbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528522214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.2528522214
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3224744685
Short name T104
Test name
Test status
Simulation time 262154723 ps
CPU time 2.22 seconds
Started Jun 09 12:24:47 PM PDT 24
Finished Jun 09 12:24:50 PM PDT 24
Peak memory 208760 kb
Host smart-d3c608bb-975e-4cba-adcc-8135328e2237
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224744685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3224744685
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2604589597
Short name T614
Test name
Test status
Simulation time 505277227 ps
CPU time 2.1 seconds
Started Jun 09 12:24:55 PM PDT 24
Finished Jun 09 12:24:58 PM PDT 24
Peak memory 200388 kb
Host smart-fabe8c30-fc95-4859-878f-9ef6f1dd34a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604589597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2604589597
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3212211893
Short name T90
Test name
Test status
Simulation time 62816922 ps
CPU time 0.72 seconds
Started Jun 09 12:24:46 PM PDT 24
Finished Jun 09 12:24:48 PM PDT 24
Peak memory 200068 kb
Host smart-17e06d03-36b4-4b0b-bd35-af45c76ad136
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212211893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3212211893
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3096683682
Short name T571
Test name
Test status
Simulation time 241037960 ps
CPU time 1.71 seconds
Started Jun 09 12:24:46 PM PDT 24
Finished Jun 09 12:24:48 PM PDT 24
Peak memory 200360 kb
Host smart-8a5be933-d0b9-46cb-90e2-ea01e45ea985
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096683682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3096683682
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.4073120826
Short name T598
Test name
Test status
Simulation time 282956052 ps
CPU time 2.1 seconds
Started Jun 09 12:25:12 PM PDT 24
Finished Jun 09 12:25:15 PM PDT 24
Peak memory 216696 kb
Host smart-25f73a18-e179-4307-837c-20243263b98f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073120826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.4073120826
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.4070872739
Short name T98
Test name
Test status
Simulation time 463782455 ps
CPU time 1.84 seconds
Started Jun 09 12:24:44 PM PDT 24
Finished Jun 09 12:24:47 PM PDT 24
Peak memory 200392 kb
Host smart-7090a480-c741-48f2-8f8e-ee285112c9e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070872739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.4070872739
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1928826241
Short name T579
Test name
Test status
Simulation time 128114259 ps
CPU time 1.07 seconds
Started Jun 09 12:24:47 PM PDT 24
Finished Jun 09 12:24:49 PM PDT 24
Peak memory 200340 kb
Host smart-199071b1-154f-486d-ba2b-5906cc4689d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928826241 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1928826241
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2316702135
Short name T553
Test name
Test status
Simulation time 73028404 ps
CPU time 0.79 seconds
Started Jun 09 12:24:46 PM PDT 24
Finished Jun 09 12:24:47 PM PDT 24
Peak memory 200152 kb
Host smart-9759bfcf-c638-4fe0-b5df-a35c3ebc6ffe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316702135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2316702135
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3143458560
Short name T562
Test name
Test status
Simulation time 84030963 ps
CPU time 0.99 seconds
Started Jun 09 12:24:49 PM PDT 24
Finished Jun 09 12:24:51 PM PDT 24
Peak memory 200196 kb
Host smart-0ac942d1-eebe-4df2-a217-e81c0d3da850
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143458560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3143458560
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.789326619
Short name T604
Test name
Test status
Simulation time 506826802 ps
CPU time 3.09 seconds
Started Jun 09 12:25:09 PM PDT 24
Finished Jun 09 12:25:14 PM PDT 24
Peak memory 208544 kb
Host smart-0f3209cb-7afd-434f-b637-091bf3be0292
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789326619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.789326619
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.280325180
Short name T581
Test name
Test status
Simulation time 791159988 ps
CPU time 2.91 seconds
Started Jun 09 12:24:47 PM PDT 24
Finished Jun 09 12:24:51 PM PDT 24
Peak memory 200464 kb
Host smart-5cd0e526-4c02-47d5-8fc7-5acc75a43c95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280325180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
280325180
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2820937360
Short name T102
Test name
Test status
Simulation time 146566362 ps
CPU time 1.16 seconds
Started Jun 09 12:25:09 PM PDT 24
Finished Jun 09 12:25:11 PM PDT 24
Peak memory 209608 kb
Host smart-bd8bc5f0-6351-48f6-acf1-abcaa529714c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820937360 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2820937360
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3771982392
Short name T554
Test name
Test status
Simulation time 61287828 ps
CPU time 0.82 seconds
Started Jun 09 12:24:47 PM PDT 24
Finished Jun 09 12:24:49 PM PDT 24
Peak memory 200444 kb
Host smart-9aa54ec4-3863-4f5f-a86c-42f33cad0756
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771982392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3771982392
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2781425202
Short name T559
Test name
Test status
Simulation time 122782923 ps
CPU time 1.21 seconds
Started Jun 09 12:25:07 PM PDT 24
Finished Jun 09 12:25:09 PM PDT 24
Peak memory 200412 kb
Host smart-6122cfbf-6831-4449-80d4-f0499bab3f5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781425202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.2781425202
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3053533534
Short name T611
Test name
Test status
Simulation time 191745459 ps
CPU time 1.4 seconds
Started Jun 09 12:25:01 PM PDT 24
Finished Jun 09 12:25:03 PM PDT 24
Peak memory 200164 kb
Host smart-28e9c461-9fbb-4077-8a2b-7c0f259c47d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053533534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3053533534
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1333578689
Short name T108
Test name
Test status
Simulation time 442821928 ps
CPU time 1.81 seconds
Started Jun 09 12:24:48 PM PDT 24
Finished Jun 09 12:24:51 PM PDT 24
Peak memory 200428 kb
Host smart-c172ab9f-2ffb-4306-8765-d229ccf7bca2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333578689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1333578689
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2317374210
Short name T560
Test name
Test status
Simulation time 158819618 ps
CPU time 1.55 seconds
Started Jun 09 12:24:59 PM PDT 24
Finished Jun 09 12:25:01 PM PDT 24
Peak memory 208628 kb
Host smart-295ce406-4f87-4a22-9289-23ceb7349c42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317374210 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2317374210
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3203934321
Short name T601
Test name
Test status
Simulation time 55355749 ps
CPU time 0.81 seconds
Started Jun 09 12:24:49 PM PDT 24
Finished Jun 09 12:24:51 PM PDT 24
Peak memory 200156 kb
Host smart-e134c69e-aa5c-4661-b531-4e3889cbf72b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203934321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.3203934321
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1609486803
Short name T556
Test name
Test status
Simulation time 94414995 ps
CPU time 1.21 seconds
Started Jun 09 12:24:51 PM PDT 24
Finished Jun 09 12:24:53 PM PDT 24
Peak memory 200380 kb
Host smart-9583cadb-56bb-44c3-ab4d-f02266a1b923
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609486803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1609486803
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.585958794
Short name T620
Test name
Test status
Simulation time 178780574 ps
CPU time 2.76 seconds
Started Jun 09 12:24:57 PM PDT 24
Finished Jun 09 12:25:00 PM PDT 24
Peak memory 208612 kb
Host smart-e3d8a322-8896-4599-b758-98d06a140932
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585958794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.585958794
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1920788979
Short name T589
Test name
Test status
Simulation time 418663364 ps
CPU time 1.85 seconds
Started Jun 09 12:25:06 PM PDT 24
Finished Jun 09 12:25:09 PM PDT 24
Peak memory 200460 kb
Host smart-cde6645a-be87-47dd-8cc9-b68f47687899
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920788979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1920788979
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3816360814
Short name T238
Test name
Test status
Simulation time 75980721 ps
CPU time 0.76 seconds
Started Jun 09 12:33:18 PM PDT 24
Finished Jun 09 12:33:19 PM PDT 24
Peak memory 200164 kb
Host smart-477cb3c6-1d2d-4841-b442-06cf3643aa08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816360814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3816360814
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2427635923
Short name T363
Test name
Test status
Simulation time 1886206252 ps
CPU time 7.67 seconds
Started Jun 09 12:33:18 PM PDT 24
Finished Jun 09 12:33:26 PM PDT 24
Peak memory 217968 kb
Host smart-44b6d309-9ac2-4cf9-911e-69b4c535cf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427635923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2427635923
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.4216079817
Short name T463
Test name
Test status
Simulation time 244328260 ps
CPU time 1.18 seconds
Started Jun 09 12:33:20 PM PDT 24
Finished Jun 09 12:33:22 PM PDT 24
Peak memory 217608 kb
Host smart-aeaf32de-55fc-4274-a45e-1c7a56092461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216079817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.4216079817
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3405388833
Short name T377
Test name
Test status
Simulation time 123983640 ps
CPU time 0.8 seconds
Started Jun 09 12:33:22 PM PDT 24
Finished Jun 09 12:33:23 PM PDT 24
Peak memory 200140 kb
Host smart-03b0348c-b6ec-41ee-a2f0-baa3444e23fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405388833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3405388833
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.261943407
Short name T169
Test name
Test status
Simulation time 818165852 ps
CPU time 3.93 seconds
Started Jun 09 12:33:12 PM PDT 24
Finished Jun 09 12:33:16 PM PDT 24
Peak memory 200536 kb
Host smart-61e8ffff-0665-49bb-b30c-885895db53ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261943407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.261943407
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.4134364581
Short name T402
Test name
Test status
Simulation time 106230731 ps
CPU time 0.93 seconds
Started Jun 09 12:33:26 PM PDT 24
Finished Jun 09 12:33:27 PM PDT 24
Peak memory 200284 kb
Host smart-22b80f83-5636-44e8-94df-b64bd104d7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134364581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.4134364581
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.2488835811
Short name T535
Test name
Test status
Simulation time 6144403480 ps
CPU time 22.22 seconds
Started Jun 09 12:33:30 PM PDT 24
Finished Jun 09 12:33:53 PM PDT 24
Peak memory 208868 kb
Host smart-7cd81299-11c0-42b4-b2ff-66d915be0915
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488835811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2488835811
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2853297608
Short name T348
Test name
Test status
Simulation time 340916231 ps
CPU time 1.97 seconds
Started Jun 09 12:33:21 PM PDT 24
Finished Jun 09 12:33:24 PM PDT 24
Peak memory 200312 kb
Host smart-f0be7d83-c5f8-4c89-ae32-5d15742bf996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853297608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2853297608
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2357376646
Short name T231
Test name
Test status
Simulation time 83569795 ps
CPU time 0.78 seconds
Started Jun 09 12:33:20 PM PDT 24
Finished Jun 09 12:33:21 PM PDT 24
Peak memory 200348 kb
Host smart-0d6a8a08-8c22-41d3-b108-fe29ad561c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357376646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2357376646
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.4244909778
Short name T46
Test name
Test status
Simulation time 2364882250 ps
CPU time 8.24 seconds
Started Jun 09 12:33:20 PM PDT 24
Finished Jun 09 12:33:29 PM PDT 24
Peak memory 218052 kb
Host smart-15fb31f5-366a-4fcc-9fad-0bcf129ae3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244909778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.4244909778
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.255556117
Short name T342
Test name
Test status
Simulation time 243944758 ps
CPU time 1.07 seconds
Started Jun 09 12:33:41 PM PDT 24
Finished Jun 09 12:33:43 PM PDT 24
Peak memory 217600 kb
Host smart-7d8c186a-cfe9-4fe5-bb1d-ef2ad0d1c6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255556117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.255556117
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2577591214
Short name T340
Test name
Test status
Simulation time 93327731 ps
CPU time 0.75 seconds
Started Jun 09 12:33:22 PM PDT 24
Finished Jun 09 12:33:23 PM PDT 24
Peak memory 200144 kb
Host smart-27680859-7c4f-4e85-bc08-7c139089ff2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577591214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2577591214
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2435765436
Short name T454
Test name
Test status
Simulation time 1669204629 ps
CPU time 5.98 seconds
Started Jun 09 12:33:14 PM PDT 24
Finished Jun 09 12:33:21 PM PDT 24
Peak memory 200536 kb
Host smart-a712752e-2538-42d7-9203-57159488f6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435765436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2435765436
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1198882054
Short name T72
Test name
Test status
Simulation time 16532159343 ps
CPU time 30.14 seconds
Started Jun 09 12:33:19 PM PDT 24
Finished Jun 09 12:33:50 PM PDT 24
Peak memory 217664 kb
Host smart-fda3e306-c69b-42ad-9540-a7a2bad1926f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198882054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1198882054
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2213896368
Short name T295
Test name
Test status
Simulation time 178080672 ps
CPU time 1.22 seconds
Started Jun 09 12:33:17 PM PDT 24
Finished Jun 09 12:33:19 PM PDT 24
Peak memory 200348 kb
Host smart-0220ee38-540f-4853-bfd4-762e3b34882a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213896368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2213896368
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.2082012057
Short name T296
Test name
Test status
Simulation time 119499639 ps
CPU time 1.12 seconds
Started Jun 09 12:33:52 PM PDT 24
Finished Jun 09 12:33:54 PM PDT 24
Peak memory 200532 kb
Host smart-1de01528-bffc-41c5-8c7f-d5580f5342c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082012057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2082012057
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1443163886
Short name T429
Test name
Test status
Simulation time 6853579879 ps
CPU time 24.13 seconds
Started Jun 09 12:33:28 PM PDT 24
Finished Jun 09 12:33:52 PM PDT 24
Peak memory 200712 kb
Host smart-36102a8c-394c-46dc-a73e-56f29e986c9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443163886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1443163886
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3301543051
Short name T250
Test name
Test status
Simulation time 151663398 ps
CPU time 1.78 seconds
Started Jun 09 12:33:13 PM PDT 24
Finished Jun 09 12:33:16 PM PDT 24
Peak memory 200340 kb
Host smart-191969f1-2191-4d63-a3e8-45138396851c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301543051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3301543051
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.4239332254
Short name T366
Test name
Test status
Simulation time 175993254 ps
CPU time 1.21 seconds
Started Jun 09 12:33:47 PM PDT 24
Finished Jun 09 12:33:48 PM PDT 24
Peak memory 200272 kb
Host smart-be12062b-b141-45e0-82ab-e5690a68655e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239332254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.4239332254
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.83257969
Short name T399
Test name
Test status
Simulation time 62483272 ps
CPU time 0.77 seconds
Started Jun 09 12:33:54 PM PDT 24
Finished Jun 09 12:33:55 PM PDT 24
Peak memory 200128 kb
Host smart-95bee07a-7fba-487e-97d8-d16b76354a75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83257969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.83257969
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.2748222770
Short name T392
Test name
Test status
Simulation time 2357549522 ps
CPU time 9.26 seconds
Started Jun 09 12:33:43 PM PDT 24
Finished Jun 09 12:33:53 PM PDT 24
Peak memory 218160 kb
Host smart-7bca4c25-d569-412e-ad1a-a3ebeb94c718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748222770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.2748222770
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1822386578
Short name T247
Test name
Test status
Simulation time 244166618 ps
CPU time 1.17 seconds
Started Jun 09 12:33:36 PM PDT 24
Finished Jun 09 12:33:38 PM PDT 24
Peak memory 217600 kb
Host smart-375c64f3-3a67-4384-b63a-3779e5f6a3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822386578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1822386578
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2061358690
Short name T415
Test name
Test status
Simulation time 153999289 ps
CPU time 0.88 seconds
Started Jun 09 12:33:42 PM PDT 24
Finished Jun 09 12:33:43 PM PDT 24
Peak memory 200120 kb
Host smart-c83a245b-0b8d-45a4-a541-4d984610a141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061358690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2061358690
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.260708423
Short name T216
Test name
Test status
Simulation time 1179787785 ps
CPU time 5.04 seconds
Started Jun 09 12:33:35 PM PDT 24
Finished Jun 09 12:33:40 PM PDT 24
Peak memory 200508 kb
Host smart-2f3dcc0f-36b0-440d-b195-33992414f145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260708423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.260708423
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.372340211
Short name T149
Test name
Test status
Simulation time 103867963 ps
CPU time 1 seconds
Started Jun 09 12:33:44 PM PDT 24
Finished Jun 09 12:33:45 PM PDT 24
Peak memory 200412 kb
Host smart-a3f0bad4-4f65-47d4-b67f-d83ced8b2c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372340211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.372340211
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1305445373
Short name T213
Test name
Test status
Simulation time 245648716 ps
CPU time 1.42 seconds
Started Jun 09 12:33:50 PM PDT 24
Finished Jun 09 12:33:52 PM PDT 24
Peak memory 200488 kb
Host smart-b8aa5580-4a00-491d-8bed-1cc372d63e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305445373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1305445373
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.4276136332
Short name T330
Test name
Test status
Simulation time 1519215527 ps
CPU time 7.73 seconds
Started Jun 09 12:33:38 PM PDT 24
Finished Jun 09 12:33:47 PM PDT 24
Peak memory 208756 kb
Host smart-ededbe2b-e20d-4a2d-96e8-9058d74af1ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276136332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.4276136332
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.898459337
Short name T201
Test name
Test status
Simulation time 105813832 ps
CPU time 1.37 seconds
Started Jun 09 12:33:43 PM PDT 24
Finished Jun 09 12:33:45 PM PDT 24
Peak memory 200348 kb
Host smart-2f0610cf-b6a2-4ca9-8c0e-125144d0e3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898459337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.898459337
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3665607235
Short name T232
Test name
Test status
Simulation time 171693615 ps
CPU time 1.16 seconds
Started Jun 09 12:33:59 PM PDT 24
Finished Jun 09 12:34:01 PM PDT 24
Peak memory 200344 kb
Host smart-8093fc46-580e-4eb7-a9c0-4a630e158842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665607235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3665607235
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1779718316
Short name T135
Test name
Test status
Simulation time 55399612 ps
CPU time 0.78 seconds
Started Jun 09 12:33:39 PM PDT 24
Finished Jun 09 12:33:40 PM PDT 24
Peak memory 200108 kb
Host smart-79329aea-146d-4cc7-9be8-22e7c1c6aef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779718316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1779718316
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2658394818
Short name T475
Test name
Test status
Simulation time 1236215615 ps
CPU time 5.51 seconds
Started Jun 09 12:33:34 PM PDT 24
Finished Jun 09 12:33:40 PM PDT 24
Peak memory 217588 kb
Host smart-81811d03-8232-4e68-841d-f1fd74a88f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658394818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2658394818
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.4201117189
Short name T476
Test name
Test status
Simulation time 263569566 ps
CPU time 1.08 seconds
Started Jun 09 12:33:55 PM PDT 24
Finished Jun 09 12:33:57 PM PDT 24
Peak memory 217604 kb
Host smart-162e9755-ed4b-4558-a2b4-3c06c9cd5672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201117189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.4201117189
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.4174208946
Short name T497
Test name
Test status
Simulation time 179607856 ps
CPU time 0.92 seconds
Started Jun 09 12:33:58 PM PDT 24
Finished Jun 09 12:33:59 PM PDT 24
Peak memory 200156 kb
Host smart-72ad2925-90d9-42b4-856b-b3e2e81bf211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174208946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.4174208946
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.3815761109
Short name T118
Test name
Test status
Simulation time 1792960788 ps
CPU time 6.07 seconds
Started Jun 09 12:33:43 PM PDT 24
Finished Jun 09 12:33:49 PM PDT 24
Peak memory 200472 kb
Host smart-541ef4d0-56b6-4153-baac-d8c49d10f19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815761109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3815761109
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3212769767
Short name T381
Test name
Test status
Simulation time 103156832 ps
CPU time 1 seconds
Started Jun 09 12:33:47 PM PDT 24
Finished Jun 09 12:33:49 PM PDT 24
Peak memory 200332 kb
Host smart-71798627-18e1-48b2-94af-054837c24724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212769767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3212769767
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3722760772
Short name T5
Test name
Test status
Simulation time 111575800 ps
CPU time 1.19 seconds
Started Jun 09 12:33:57 PM PDT 24
Finished Jun 09 12:33:58 PM PDT 24
Peak memory 200540 kb
Host smart-75d48432-d352-4e88-a7fa-dbeebe3dc325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722760772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3722760772
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.872557891
Short name T490
Test name
Test status
Simulation time 6314827690 ps
CPU time 26.73 seconds
Started Jun 09 12:33:47 PM PDT 24
Finished Jun 09 12:34:14 PM PDT 24
Peak memory 208860 kb
Host smart-b5de9566-bfef-4925-9851-686debe1135b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872557891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.872557891
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.942374549
Short name T376
Test name
Test status
Simulation time 130527737 ps
CPU time 1.55 seconds
Started Jun 09 12:33:52 PM PDT 24
Finished Jun 09 12:33:55 PM PDT 24
Peak memory 200348 kb
Host smart-e032c86b-4c91-4511-a85b-d9e1ed6a9008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942374549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.942374549
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1184730294
Short name T279
Test name
Test status
Simulation time 219989374 ps
CPU time 1.29 seconds
Started Jun 09 12:33:40 PM PDT 24
Finished Jun 09 12:33:42 PM PDT 24
Peak memory 200240 kb
Host smart-51424f76-4e07-4f8f-850d-54809f66e904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184730294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1184730294
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1170123409
Short name T153
Test name
Test status
Simulation time 85032463 ps
CPU time 0.82 seconds
Started Jun 09 12:33:59 PM PDT 24
Finished Jun 09 12:34:00 PM PDT 24
Peak memory 200108 kb
Host smart-6f497c6a-17c9-4a38-9dc9-7111907fdeb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170123409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1170123409
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.536961143
Short name T321
Test name
Test status
Simulation time 244029522 ps
CPU time 1.02 seconds
Started Jun 09 12:33:58 PM PDT 24
Finished Jun 09 12:33:59 PM PDT 24
Peak memory 217588 kb
Host smart-e5680ad7-5609-4c69-a0d8-d4d6cf416e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536961143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.536961143
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_reset.765622991
Short name T274
Test name
Test status
Simulation time 703669089 ps
CPU time 4.12 seconds
Started Jun 09 12:33:52 PM PDT 24
Finished Jun 09 12:33:56 PM PDT 24
Peak memory 200620 kb
Host smart-183214d8-bfcb-4c18-b0f2-a726bdd4ae99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765622991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.765622991
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3255955050
Short name T255
Test name
Test status
Simulation time 143162254 ps
CPU time 1.18 seconds
Started Jun 09 12:33:46 PM PDT 24
Finished Jun 09 12:33:48 PM PDT 24
Peak memory 200352 kb
Host smart-a285588e-29c7-4902-851d-329d769d8745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255955050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3255955050
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.515580550
Short name T192
Test name
Test status
Simulation time 125779882 ps
CPU time 1.23 seconds
Started Jun 09 12:33:57 PM PDT 24
Finished Jun 09 12:33:59 PM PDT 24
Peak memory 200552 kb
Host smart-2bed407d-fe26-4a25-b07a-127994a55ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515580550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.515580550
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2836673284
Short name T505
Test name
Test status
Simulation time 5834286523 ps
CPU time 20.18 seconds
Started Jun 09 12:33:39 PM PDT 24
Finished Jun 09 12:33:59 PM PDT 24
Peak memory 208912 kb
Host smart-5a11764e-a465-4912-9376-828927dffbde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836673284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2836673284
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1124200334
Short name T356
Test name
Test status
Simulation time 531828278 ps
CPU time 2.89 seconds
Started Jun 09 12:33:36 PM PDT 24
Finished Jun 09 12:33:40 PM PDT 24
Peak memory 200532 kb
Host smart-39015707-14d6-4061-b508-ef2f28112c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124200334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1124200334
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2463107959
Short name T251
Test name
Test status
Simulation time 67865042 ps
CPU time 0.86 seconds
Started Jun 09 12:33:47 PM PDT 24
Finished Jun 09 12:33:49 PM PDT 24
Peak memory 200360 kb
Host smart-97e1dddb-5cf3-4e5e-9b67-0bf1226bb916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463107959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2463107959
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.202318606
Short name T304
Test name
Test status
Simulation time 55275583 ps
CPU time 0.7 seconds
Started Jun 09 12:33:57 PM PDT 24
Finished Jun 09 12:33:58 PM PDT 24
Peak memory 200104 kb
Host smart-77630b5b-f565-420b-9539-747c0daed612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202318606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.202318606
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.739003839
Short name T514
Test name
Test status
Simulation time 1886218615 ps
CPU time 7.15 seconds
Started Jun 09 12:33:54 PM PDT 24
Finished Jun 09 12:34:01 PM PDT 24
Peak memory 217588 kb
Host smart-9552739c-822f-4878-a0d7-978256fc41fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739003839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.739003839
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.4288297961
Short name T474
Test name
Test status
Simulation time 244121431 ps
CPU time 1.16 seconds
Started Jun 09 12:33:56 PM PDT 24
Finished Jun 09 12:34:03 PM PDT 24
Peak memory 217604 kb
Host smart-917e9f71-b5ce-43c9-88d5-96e85961fda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288297961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.4288297961
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2891046442
Short name T198
Test name
Test status
Simulation time 108981535 ps
CPU time 0.77 seconds
Started Jun 09 12:33:49 PM PDT 24
Finished Jun 09 12:33:50 PM PDT 24
Peak memory 200156 kb
Host smart-3cbf873a-a1ae-4f37-a4c6-b79ba456d340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891046442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2891046442
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2424843970
Short name T87
Test name
Test status
Simulation time 1990124730 ps
CPU time 8.01 seconds
Started Jun 09 12:33:50 PM PDT 24
Finished Jun 09 12:33:58 PM PDT 24
Peak memory 200512 kb
Host smart-53dd9c7f-86cd-458f-a45a-c7529cd53cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424843970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2424843970
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1970757961
Short name T199
Test name
Test status
Simulation time 96736498 ps
CPU time 1 seconds
Started Jun 09 12:34:00 PM PDT 24
Finished Jun 09 12:34:02 PM PDT 24
Peak memory 200304 kb
Host smart-f8834cf8-47a2-42c9-9152-7bf11e3a50a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970757961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1970757961
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3080414517
Short name T184
Test name
Test status
Simulation time 113235298 ps
CPU time 1.14 seconds
Started Jun 09 12:33:53 PM PDT 24
Finished Jun 09 12:33:55 PM PDT 24
Peak memory 200508 kb
Host smart-602cd469-04df-4766-bb29-a1a77fac662f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080414517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3080414517
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.832720882
Short name T435
Test name
Test status
Simulation time 6479662110 ps
CPU time 21.88 seconds
Started Jun 09 12:33:57 PM PDT 24
Finished Jun 09 12:34:19 PM PDT 24
Peak memory 208888 kb
Host smart-c7ce6f8e-af2c-4e08-8b0a-d8b4b5e0bdec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832720882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.832720882
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.39298647
Short name T412
Test name
Test status
Simulation time 303949938 ps
CPU time 1.92 seconds
Started Jun 09 12:33:45 PM PDT 24
Finished Jun 09 12:33:47 PM PDT 24
Peak memory 200308 kb
Host smart-c2b45e08-c2be-425a-9f5d-e3c34f66c3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39298647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.39298647
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.441385012
Short name T440
Test name
Test status
Simulation time 88112144 ps
CPU time 0.79 seconds
Started Jun 09 12:33:42 PM PDT 24
Finished Jun 09 12:33:43 PM PDT 24
Peak memory 200156 kb
Host smart-95eadf99-b0f1-4312-bc32-f1e8c681831e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441385012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.441385012
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1241118327
Short name T328
Test name
Test status
Simulation time 2168340749 ps
CPU time 8.02 seconds
Started Jun 09 12:33:55 PM PDT 24
Finished Jun 09 12:34:04 PM PDT 24
Peak memory 218056 kb
Host smart-06131222-c56e-498f-90d4-4ef6da42633b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241118327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1241118327
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2503559159
Short name T165
Test name
Test status
Simulation time 244365045 ps
CPU time 1.03 seconds
Started Jun 09 12:33:48 PM PDT 24
Finished Jun 09 12:33:50 PM PDT 24
Peak memory 217576 kb
Host smart-b97cced7-6d0f-4c16-b8f3-4a4fac6dd182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503559159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2503559159
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3715986432
Short name T285
Test name
Test status
Simulation time 156233276 ps
CPU time 0.86 seconds
Started Jun 09 12:33:36 PM PDT 24
Finished Jun 09 12:33:37 PM PDT 24
Peak memory 200132 kb
Host smart-f2ace1e7-3934-4ddb-8878-d68f80c8bce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715986432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3715986432
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3692211636
Short name T13
Test name
Test status
Simulation time 1063331835 ps
CPU time 4.91 seconds
Started Jun 09 12:33:44 PM PDT 24
Finished Jun 09 12:33:49 PM PDT 24
Peak memory 200524 kb
Host smart-8bb846c6-a31a-439e-93ba-091afd4b56ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692211636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3692211636
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2543572513
Short name T326
Test name
Test status
Simulation time 178105809 ps
CPU time 1.36 seconds
Started Jun 09 12:33:45 PM PDT 24
Finished Jun 09 12:33:47 PM PDT 24
Peak memory 200372 kb
Host smart-a9c37276-f68c-45be-8ffe-c1cc7843b5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543572513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2543572513
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3968043835
Short name T206
Test name
Test status
Simulation time 118193251 ps
CPU time 1.22 seconds
Started Jun 09 12:33:45 PM PDT 24
Finished Jun 09 12:33:46 PM PDT 24
Peak memory 200484 kb
Host smart-4aba4d85-7d16-48e9-a6db-db6469f75221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968043835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3968043835
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.775430033
Short name T52
Test name
Test status
Simulation time 8859810996 ps
CPU time 35.04 seconds
Started Jun 09 12:33:43 PM PDT 24
Finished Jun 09 12:34:18 PM PDT 24
Peak memory 200900 kb
Host smart-49ed3196-a317-45e1-86b9-7dc004ddc83c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775430033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.775430033
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.847818134
Short name T337
Test name
Test status
Simulation time 413043287 ps
CPU time 2.39 seconds
Started Jun 09 12:33:54 PM PDT 24
Finished Jun 09 12:33:57 PM PDT 24
Peak memory 200332 kb
Host smart-2f359a18-7c26-4651-9f84-3edb9b7be48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847818134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.847818134
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2121312925
Short name T414
Test name
Test status
Simulation time 167908826 ps
CPU time 1.13 seconds
Started Jun 09 12:33:46 PM PDT 24
Finished Jun 09 12:33:47 PM PDT 24
Peak memory 200304 kb
Host smart-11f7b260-91bb-471d-b012-211dd88e2db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121312925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2121312925
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.849770653
Short name T427
Test name
Test status
Simulation time 72902985 ps
CPU time 0.79 seconds
Started Jun 09 12:33:40 PM PDT 24
Finished Jun 09 12:33:41 PM PDT 24
Peak memory 200360 kb
Host smart-278a848b-35bd-466f-9d92-060150994c62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849770653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.849770653
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.4130952327
Short name T35
Test name
Test status
Simulation time 2368681526 ps
CPU time 8.55 seconds
Started Jun 09 12:33:48 PM PDT 24
Finished Jun 09 12:33:57 PM PDT 24
Peak memory 218252 kb
Host smart-712b83ef-bc18-49f8-b979-4f374e84669d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130952327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.4130952327
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3482572713
Short name T158
Test name
Test status
Simulation time 244874936 ps
CPU time 1.02 seconds
Started Jun 09 12:33:38 PM PDT 24
Finished Jun 09 12:33:39 PM PDT 24
Peak memory 217576 kb
Host smart-f74ac0a9-7ac5-4116-abf6-1e5d2b9d10e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482572713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3482572713
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2328462116
Short name T469
Test name
Test status
Simulation time 69363986 ps
CPU time 0.71 seconds
Started Jun 09 12:33:52 PM PDT 24
Finished Jun 09 12:33:53 PM PDT 24
Peak memory 200192 kb
Host smart-d98aad40-b599-46bc-b338-5a8447869715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328462116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2328462116
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1127918702
Short name T369
Test name
Test status
Simulation time 830579048 ps
CPU time 4.37 seconds
Started Jun 09 12:33:45 PM PDT 24
Finished Jun 09 12:33:50 PM PDT 24
Peak memory 200508 kb
Host smart-bf5736d8-344c-4cb0-93f0-bb6b4096dacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127918702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1127918702
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.4091882203
Short name T311
Test name
Test status
Simulation time 103109977 ps
CPU time 1.02 seconds
Started Jun 09 12:33:52 PM PDT 24
Finished Jun 09 12:33:54 PM PDT 24
Peak memory 200348 kb
Host smart-97e52480-25e2-4261-bceb-b90c9428d45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091882203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.4091882203
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1970447261
Short name T233
Test name
Test status
Simulation time 197786573 ps
CPU time 1.35 seconds
Started Jun 09 12:33:49 PM PDT 24
Finished Jun 09 12:33:51 PM PDT 24
Peak memory 200524 kb
Host smart-02b38252-734c-4a1b-8bb6-f05dd9e8938a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970447261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1970447261
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.1925298147
Short name T386
Test name
Test status
Simulation time 3394511148 ps
CPU time 11.86 seconds
Started Jun 09 12:33:53 PM PDT 24
Finished Jun 09 12:34:05 PM PDT 24
Peak memory 208820 kb
Host smart-59b385c7-bf79-470f-81ee-0202c72c8508
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925298147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1925298147
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.4080347593
Short name T459
Test name
Test status
Simulation time 337451172 ps
CPU time 2.43 seconds
Started Jun 09 12:33:47 PM PDT 24
Finished Jun 09 12:33:50 PM PDT 24
Peak memory 208628 kb
Host smart-ce683391-4a66-42d1-96d7-68c5f6f74849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080347593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.4080347593
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.598365913
Short name T292
Test name
Test status
Simulation time 175197145 ps
CPU time 1.12 seconds
Started Jun 09 12:33:45 PM PDT 24
Finished Jun 09 12:33:47 PM PDT 24
Peak memory 200352 kb
Host smart-4f265e4c-a5bc-4dcb-bb63-7da3f0044179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598365913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.598365913
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.430645457
Short name T258
Test name
Test status
Simulation time 78653737 ps
CPU time 0.75 seconds
Started Jun 09 12:33:47 PM PDT 24
Finished Jun 09 12:33:48 PM PDT 24
Peak memory 200080 kb
Host smart-8a3b5061-9fab-4131-851b-f36d4baa4ba5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430645457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.430645457
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1740114506
Short name T404
Test name
Test status
Simulation time 1219581847 ps
CPU time 5.31 seconds
Started Jun 09 12:33:55 PM PDT 24
Finished Jun 09 12:34:01 PM PDT 24
Peak memory 221716 kb
Host smart-820ecec2-b257-4abc-91d2-d9b8ab1baf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740114506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1740114506
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.849928051
Short name T496
Test name
Test status
Simulation time 244366423 ps
CPU time 1.1 seconds
Started Jun 09 12:33:52 PM PDT 24
Finished Jun 09 12:33:54 PM PDT 24
Peak memory 217800 kb
Host smart-e9230977-f3ad-464e-851e-0f9b197e9f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849928051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.849928051
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1718056077
Short name T375
Test name
Test status
Simulation time 190735375 ps
CPU time 0.93 seconds
Started Jun 09 12:33:43 PM PDT 24
Finished Jun 09 12:33:44 PM PDT 24
Peak memory 200136 kb
Host smart-4125039a-4e4e-4785-8713-0618b1847627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718056077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1718056077
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.1910405389
Short name T120
Test name
Test status
Simulation time 1777841520 ps
CPU time 6.52 seconds
Started Jun 09 12:33:51 PM PDT 24
Finished Jun 09 12:33:58 PM PDT 24
Peak memory 200476 kb
Host smart-44f97c07-ea23-4ff3-851f-4847483183ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910405389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1910405389
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.392582627
Short name T462
Test name
Test status
Simulation time 140037427 ps
CPU time 1.15 seconds
Started Jun 09 12:33:46 PM PDT 24
Finished Jun 09 12:33:53 PM PDT 24
Peak memory 200376 kb
Host smart-a994f7ab-28f1-4476-b4aa-715d73b189b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392582627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.392582627
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3005108574
Short name T121
Test name
Test status
Simulation time 255579943 ps
CPU time 1.51 seconds
Started Jun 09 12:33:46 PM PDT 24
Finished Jun 09 12:33:48 PM PDT 24
Peak memory 200532 kb
Host smart-3de99561-0a82-407b-b79c-ca0c6382383a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005108574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3005108574
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.470860463
Short name T341
Test name
Test status
Simulation time 3811437926 ps
CPU time 18.06 seconds
Started Jun 09 12:33:53 PM PDT 24
Finished Jun 09 12:34:11 PM PDT 24
Peak memory 200628 kb
Host smart-34d979e7-5e28-4b87-8d87-8a30c78e9255
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470860463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.470860463
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.1595338736
Short name T318
Test name
Test status
Simulation time 483782352 ps
CPU time 2.61 seconds
Started Jun 09 12:33:55 PM PDT 24
Finished Jun 09 12:33:58 PM PDT 24
Peak memory 208620 kb
Host smart-cfc3c746-fc39-423c-88ea-b3227d4d91f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595338736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1595338736
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.4104080992
Short name T443
Test name
Test status
Simulation time 172365049 ps
CPU time 1.14 seconds
Started Jun 09 12:33:37 PM PDT 24
Finished Jun 09 12:33:39 PM PDT 24
Peak memory 200304 kb
Host smart-d95750cd-f5a6-4f94-a838-f7451e5effad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104080992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.4104080992
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1691289116
Short name T152
Test name
Test status
Simulation time 68912269 ps
CPU time 0.75 seconds
Started Jun 09 12:33:58 PM PDT 24
Finished Jun 09 12:33:59 PM PDT 24
Peak memory 200148 kb
Host smart-5ded22cd-cfb6-408c-bb7f-8aee35bdbd1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691289116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1691289116
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3740466028
Short name T361
Test name
Test status
Simulation time 2354094077 ps
CPU time 8.52 seconds
Started Jun 09 12:33:54 PM PDT 24
Finished Jun 09 12:34:03 PM PDT 24
Peak memory 218044 kb
Host smart-8dd67005-17e2-4d3c-b66c-8d5381adaeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740466028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3740466028
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2940566569
Short name T168
Test name
Test status
Simulation time 243990494 ps
CPU time 1.22 seconds
Started Jun 09 12:34:01 PM PDT 24
Finished Jun 09 12:34:03 PM PDT 24
Peak memory 217624 kb
Host smart-e5ab33a3-b93b-428d-aa02-99d606a6dc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940566569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2940566569
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.351922731
Short name T424
Test name
Test status
Simulation time 115284569 ps
CPU time 0.79 seconds
Started Jun 09 12:33:54 PM PDT 24
Finished Jun 09 12:33:56 PM PDT 24
Peak memory 200140 kb
Host smart-7b7cbee9-580c-4f00-8b9c-b210e9715499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351922731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.351922731
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2607745389
Short name T324
Test name
Test status
Simulation time 1509004483 ps
CPU time 6.08 seconds
Started Jun 09 12:34:00 PM PDT 24
Finished Jun 09 12:34:07 PM PDT 24
Peak memory 200500 kb
Host smart-0d047707-4e6e-442a-9ba9-29ad4fc2b172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607745389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2607745389
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3304852672
Short name T498
Test name
Test status
Simulation time 105481801 ps
CPU time 1 seconds
Started Jun 09 12:33:57 PM PDT 24
Finished Jun 09 12:33:59 PM PDT 24
Peak memory 200368 kb
Host smart-d7b21b2d-8d0f-41a5-92c7-f8fabacb57e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304852672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3304852672
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.4124270211
Short name T242
Test name
Test status
Simulation time 126161141 ps
CPU time 1.16 seconds
Started Jun 09 12:34:02 PM PDT 24
Finished Jun 09 12:34:04 PM PDT 24
Peak memory 200480 kb
Host smart-b3c4c5cf-4efb-43c4-8898-9974a5168891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124270211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.4124270211
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.424503026
Short name T227
Test name
Test status
Simulation time 4966286300 ps
CPU time 23.53 seconds
Started Jun 09 12:34:09 PM PDT 24
Finished Jun 09 12:34:34 PM PDT 24
Peak memory 200700 kb
Host smart-fbbd07bb-c5f2-482b-88b9-0310eb2ea845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424503026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.424503026
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2241324455
Short name T136
Test name
Test status
Simulation time 153203975 ps
CPU time 1.83 seconds
Started Jun 09 12:34:06 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 200328 kb
Host smart-55679759-d937-4fc7-a317-1b458e072b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241324455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2241324455
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.229426617
Short name T488
Test name
Test status
Simulation time 82157191 ps
CPU time 0.89 seconds
Started Jun 09 12:34:01 PM PDT 24
Finished Jun 09 12:34:08 PM PDT 24
Peak memory 200344 kb
Host smart-dd096114-981c-451e-8cf0-b72b5b3fd2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229426617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.229426617
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2705457492
Short name T437
Test name
Test status
Simulation time 58575768 ps
CPU time 0.73 seconds
Started Jun 09 12:33:54 PM PDT 24
Finished Jun 09 12:33:55 PM PDT 24
Peak memory 200168 kb
Host smart-f6d82ada-1dc8-415e-957f-a02ebd4246c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705457492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2705457492
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.1426820103
Short name T483
Test name
Test status
Simulation time 1876465842 ps
CPU time 6.81 seconds
Started Jun 09 12:33:51 PM PDT 24
Finished Jun 09 12:33:59 PM PDT 24
Peak memory 217320 kb
Host smart-7903794e-600f-4e46-a8ad-33dc9b4f73bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426820103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1426820103
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1186039357
Short name T421
Test name
Test status
Simulation time 244570262 ps
CPU time 1.02 seconds
Started Jun 09 12:33:56 PM PDT 24
Finished Jun 09 12:33:58 PM PDT 24
Peak memory 217552 kb
Host smart-464bd30a-293b-441f-a013-7563817e40f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186039357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1186039357
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.908356664
Short name T188
Test name
Test status
Simulation time 100868702 ps
CPU time 0.78 seconds
Started Jun 09 12:34:07 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 200176 kb
Host smart-197d0e8a-ffc5-4be1-a70b-78868a8f7696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908356664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.908356664
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.61041200
Short name T442
Test name
Test status
Simulation time 965529344 ps
CPU time 4.71 seconds
Started Jun 09 12:33:59 PM PDT 24
Finished Jun 09 12:34:04 PM PDT 24
Peak memory 200516 kb
Host smart-8afa3287-16c5-4b0a-ac6d-417a68071ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61041200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.61041200
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1602309489
Short name T456
Test name
Test status
Simulation time 104690013 ps
CPU time 1.04 seconds
Started Jun 09 12:33:52 PM PDT 24
Finished Jun 09 12:33:53 PM PDT 24
Peak memory 200344 kb
Host smart-86d26573-1b12-4332-bf82-77c4a7d556c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602309489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1602309489
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1988342186
Short name T436
Test name
Test status
Simulation time 109321623 ps
CPU time 1.14 seconds
Started Jun 09 12:33:52 PM PDT 24
Finished Jun 09 12:33:54 PM PDT 24
Peak memory 200532 kb
Host smart-dfab5f7e-4395-4759-85e7-a30be0af1572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988342186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1988342186
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3227168615
Short name T200
Test name
Test status
Simulation time 1827255831 ps
CPU time 8.78 seconds
Started Jun 09 12:33:54 PM PDT 24
Finished Jun 09 12:34:03 PM PDT 24
Peak memory 209960 kb
Host smart-41aa2bdd-7ec1-4f3c-9296-17ce6801b480
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227168615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3227168615
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3936104125
Short name T53
Test name
Test status
Simulation time 129940211 ps
CPU time 1.71 seconds
Started Jun 09 12:33:50 PM PDT 24
Finished Jun 09 12:33:52 PM PDT 24
Peak memory 208832 kb
Host smart-b3049980-65a4-4b37-98c4-0334d2372f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936104125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3936104125
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.404873336
Short name T461
Test name
Test status
Simulation time 97151237 ps
CPU time 1.01 seconds
Started Jun 09 12:34:02 PM PDT 24
Finished Jun 09 12:34:04 PM PDT 24
Peak memory 200600 kb
Host smart-09767e7e-b93d-4dc3-b931-dfd4c78e45cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404873336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.404873336
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.3276765040
Short name T166
Test name
Test status
Simulation time 74872112 ps
CPU time 0.77 seconds
Started Jun 09 12:34:01 PM PDT 24
Finished Jun 09 12:34:02 PM PDT 24
Peak memory 200356 kb
Host smart-caf3817d-e25a-47ab-bc09-7459c5b69d6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276765040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3276765040
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.133459878
Short name T515
Test name
Test status
Simulation time 2169678266 ps
CPU time 7.31 seconds
Started Jun 09 12:33:56 PM PDT 24
Finished Jun 09 12:34:04 PM PDT 24
Peak memory 218116 kb
Host smart-7ef7f23d-ae64-4731-8ca0-7b3c942417d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133459878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.133459878
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3605062639
Short name T155
Test name
Test status
Simulation time 243819547 ps
CPU time 1.1 seconds
Started Jun 09 12:33:57 PM PDT 24
Finished Jun 09 12:33:58 PM PDT 24
Peak memory 217612 kb
Host smart-d94bab30-9c35-4433-a1c9-3cb3f266e1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605062639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3605062639
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.781756126
Short name T527
Test name
Test status
Simulation time 142998221 ps
CPU time 0.82 seconds
Started Jun 09 12:34:04 PM PDT 24
Finished Jun 09 12:34:06 PM PDT 24
Peak memory 200148 kb
Host smart-5658f236-b54e-4f25-9c15-23a2a1bfd6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781756126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.781756126
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.1391791676
Short name T344
Test name
Test status
Simulation time 1937680060 ps
CPU time 7.11 seconds
Started Jun 09 12:34:01 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 200540 kb
Host smart-02878a29-0c95-4326-8a3c-f880f7be2ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391791676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1391791676
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2733487483
Short name T275
Test name
Test status
Simulation time 140570841 ps
CPU time 1.06 seconds
Started Jun 09 12:33:51 PM PDT 24
Finished Jun 09 12:33:53 PM PDT 24
Peak memory 200328 kb
Host smart-0bb40242-199f-4e3b-99f6-53fd03eae233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733487483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2733487483
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.817457607
Short name T290
Test name
Test status
Simulation time 199904608 ps
CPU time 1.37 seconds
Started Jun 09 12:33:58 PM PDT 24
Finished Jun 09 12:34:00 PM PDT 24
Peak memory 200556 kb
Host smart-77f418e5-82b3-4ee5-a34c-736f6215440c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817457607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.817457607
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1915631414
Short name T422
Test name
Test status
Simulation time 6351200710 ps
CPU time 31.29 seconds
Started Jun 09 12:34:11 PM PDT 24
Finished Jun 09 12:34:44 PM PDT 24
Peak memory 209084 kb
Host smart-3509526a-9bea-4e97-b74f-46be0eb8b50a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915631414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1915631414
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1319867587
Short name T293
Test name
Test status
Simulation time 86485247 ps
CPU time 0.87 seconds
Started Jun 09 12:34:03 PM PDT 24
Finished Jun 09 12:34:05 PM PDT 24
Peak memory 200348 kb
Host smart-7c18cd0b-7239-43e7-98dc-525238cb4471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319867587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1319867587
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.417325184
Short name T7
Test name
Test status
Simulation time 71034435 ps
CPU time 0.77 seconds
Started Jun 09 12:33:24 PM PDT 24
Finished Jun 09 12:33:25 PM PDT 24
Peak memory 200060 kb
Host smart-16387e3c-2e73-4436-8cc6-ed38f9564a79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417325184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.417325184
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2402129447
Short name T41
Test name
Test status
Simulation time 2358588813 ps
CPU time 8.33 seconds
Started Jun 09 12:33:38 PM PDT 24
Finished Jun 09 12:33:46 PM PDT 24
Peak memory 217392 kb
Host smart-028a514d-869d-4221-b756-93ad06be6949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402129447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2402129447
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.421019347
Short name T140
Test name
Test status
Simulation time 244744044 ps
CPU time 1.06 seconds
Started Jun 09 12:33:38 PM PDT 24
Finished Jun 09 12:33:40 PM PDT 24
Peak memory 217536 kb
Host smart-caf371d7-2597-4c29-aa1a-7cf78d4da1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421019347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.421019347
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1879748646
Short name T19
Test name
Test status
Simulation time 113278358 ps
CPU time 0.78 seconds
Started Jun 09 12:33:37 PM PDT 24
Finished Jun 09 12:33:38 PM PDT 24
Peak memory 200104 kb
Host smart-02668a2f-54df-45ce-93c3-64d1a824fdef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879748646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1879748646
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1360695697
Short name T173
Test name
Test status
Simulation time 885999328 ps
CPU time 4.59 seconds
Started Jun 09 12:33:12 PM PDT 24
Finished Jun 09 12:33:17 PM PDT 24
Peak memory 200508 kb
Host smart-927f4192-cddb-4937-a712-196c63cca3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360695697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1360695697
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.3243031489
Short name T68
Test name
Test status
Simulation time 16528075150 ps
CPU time 26.61 seconds
Started Jun 09 12:33:34 PM PDT 24
Finished Jun 09 12:34:01 PM PDT 24
Peak memory 217552 kb
Host smart-baf69d64-b4d6-4200-b4e6-2da44b8a89e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243031489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3243031489
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2712389390
Short name T428
Test name
Test status
Simulation time 159648688 ps
CPU time 1.18 seconds
Started Jun 09 12:33:26 PM PDT 24
Finished Jun 09 12:33:28 PM PDT 24
Peak memory 200276 kb
Host smart-0303228e-94e9-4e7a-a689-67bae811b295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712389390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2712389390
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3631713706
Short name T244
Test name
Test status
Simulation time 203872790 ps
CPU time 1.33 seconds
Started Jun 09 12:33:22 PM PDT 24
Finished Jun 09 12:33:24 PM PDT 24
Peak memory 200524 kb
Host smart-2f763df7-c778-47ae-a10c-a2b22b414b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631713706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3631713706
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.757886221
Short name T423
Test name
Test status
Simulation time 2854729871 ps
CPU time 10.38 seconds
Started Jun 09 12:33:48 PM PDT 24
Finished Jun 09 12:33:58 PM PDT 24
Peak memory 200660 kb
Host smart-e1bfb58b-48e6-4d91-90ca-6396bd667f46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757886221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.757886221
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2910009582
Short name T448
Test name
Test status
Simulation time 409198064 ps
CPU time 2.19 seconds
Started Jun 09 12:33:19 PM PDT 24
Finished Jun 09 12:33:22 PM PDT 24
Peak memory 200292 kb
Host smart-ed695588-08c3-449d-b305-e06f719147eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910009582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2910009582
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.385233424
Short name T502
Test name
Test status
Simulation time 143407829 ps
CPU time 1.22 seconds
Started Jun 09 12:33:21 PM PDT 24
Finished Jun 09 12:33:23 PM PDT 24
Peak memory 200508 kb
Host smart-22ba5e02-d01d-414a-85d1-8ebb410b945f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385233424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.385233424
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1936506968
Short name T403
Test name
Test status
Simulation time 65993696 ps
CPU time 0.79 seconds
Started Jun 09 12:34:06 PM PDT 24
Finished Jun 09 12:34:08 PM PDT 24
Peak memory 200120 kb
Host smart-b0d59be6-68bc-4c02-9253-ead890f4a3f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936506968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1936506968
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.588679311
Short name T499
Test name
Test status
Simulation time 2364543111 ps
CPU time 8.06 seconds
Started Jun 09 12:33:59 PM PDT 24
Finished Jun 09 12:34:08 PM PDT 24
Peak memory 221992 kb
Host smart-182ac3e9-84f8-4be7-bff5-2c8562a6fb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588679311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.588679311
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2587689813
Short name T26
Test name
Test status
Simulation time 244916470 ps
CPU time 1.03 seconds
Started Jun 09 12:34:00 PM PDT 24
Finished Jun 09 12:34:02 PM PDT 24
Peak memory 217572 kb
Host smart-899f6309-91a3-4c9a-81df-152a0a0b254e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587689813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2587689813
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.76399270
Short name T472
Test name
Test status
Simulation time 93902977 ps
CPU time 0.76 seconds
Started Jun 09 12:34:03 PM PDT 24
Finished Jun 09 12:34:05 PM PDT 24
Peak memory 200160 kb
Host smart-19d52661-cd20-4625-b274-6cac0b6dc323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76399270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.76399270
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3055127205
Short name T185
Test name
Test status
Simulation time 888369901 ps
CPU time 4.7 seconds
Started Jun 09 12:34:02 PM PDT 24
Finished Jun 09 12:34:08 PM PDT 24
Peak memory 200580 kb
Host smart-bbf59f72-3d1d-493f-8808-e7d5058ced24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055127205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3055127205
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2660541347
Short name T513
Test name
Test status
Simulation time 145288328 ps
CPU time 1.1 seconds
Started Jun 09 12:34:02 PM PDT 24
Finished Jun 09 12:34:03 PM PDT 24
Peak memory 200316 kb
Host smart-c57ccd77-6d2d-48a0-906a-91a4924a3d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660541347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2660541347
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2041247423
Short name T161
Test name
Test status
Simulation time 198158653 ps
CPU time 1.33 seconds
Started Jun 09 12:33:59 PM PDT 24
Finished Jun 09 12:34:01 PM PDT 24
Peak memory 200544 kb
Host smart-54c3e21c-a36d-48c9-b76f-6377243dc331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041247423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2041247423
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2717407317
Short name T460
Test name
Test status
Simulation time 7751340232 ps
CPU time 28.51 seconds
Started Jun 09 12:33:54 PM PDT 24
Finished Jun 09 12:34:23 PM PDT 24
Peak memory 208868 kb
Host smart-532dc602-5608-4471-8c2b-adb911d22ec0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717407317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2717407317
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3755591195
Short name T411
Test name
Test status
Simulation time 419909670 ps
CPU time 2.33 seconds
Started Jun 09 12:33:56 PM PDT 24
Finished Jun 09 12:33:59 PM PDT 24
Peak memory 208560 kb
Host smart-3aeebc85-077b-4d05-8bc8-40ac18636ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755591195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3755591195
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1667982708
Short name T365
Test name
Test status
Simulation time 239285597 ps
CPU time 1.3 seconds
Started Jun 09 12:34:01 PM PDT 24
Finished Jun 09 12:34:03 PM PDT 24
Peak memory 200292 kb
Host smart-1534221c-d7cb-4122-9ca1-a9a3f9a47ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667982708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1667982708
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.650330745
Short name T203
Test name
Test status
Simulation time 68689503 ps
CPU time 0.76 seconds
Started Jun 09 12:34:01 PM PDT 24
Finished Jun 09 12:34:03 PM PDT 24
Peak memory 200172 kb
Host smart-6b281021-8b6f-4e97-89f1-7654128527df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650330745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.650330745
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1425746931
Short name T383
Test name
Test status
Simulation time 2177008836 ps
CPU time 8.55 seconds
Started Jun 09 12:34:01 PM PDT 24
Finished Jun 09 12:34:11 PM PDT 24
Peak memory 217616 kb
Host smart-113f0d82-0bd2-4127-93f3-125007309f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425746931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1425746931
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3191719531
Short name T215
Test name
Test status
Simulation time 245246918 ps
CPU time 1.09 seconds
Started Jun 09 12:33:57 PM PDT 24
Finished Jun 09 12:33:59 PM PDT 24
Peak memory 217500 kb
Host smart-5254b775-4509-4ffb-b098-dde5ef8debcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191719531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3191719531
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1117133329
Short name T417
Test name
Test status
Simulation time 115407383 ps
CPU time 0.78 seconds
Started Jun 09 12:34:05 PM PDT 24
Finished Jun 09 12:34:07 PM PDT 24
Peak memory 200152 kb
Host smart-dbe7fb39-2236-4c86-8496-6f965713f8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117133329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1117133329
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.510743896
Short name T240
Test name
Test status
Simulation time 1632219854 ps
CPU time 5.89 seconds
Started Jun 09 12:34:11 PM PDT 24
Finished Jun 09 12:34:19 PM PDT 24
Peak memory 200524 kb
Host smart-42a2f29a-bde3-4dc3-bfff-c335355b5890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510743896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.510743896
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.641314821
Short name T156
Test name
Test status
Simulation time 145733367 ps
CPU time 1.09 seconds
Started Jun 09 12:33:57 PM PDT 24
Finished Jun 09 12:33:59 PM PDT 24
Peak memory 200380 kb
Host smart-81233bbb-92b6-488e-987e-f3245d519606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641314821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.641314821
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2536614465
Short name T239
Test name
Test status
Simulation time 107481889 ps
CPU time 1.22 seconds
Started Jun 09 12:34:02 PM PDT 24
Finished Jun 09 12:34:04 PM PDT 24
Peak memory 200728 kb
Host smart-70b86ee2-bdea-4bfe-95a0-3a00d3a6f045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536614465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2536614465
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.4286615098
Short name T270
Test name
Test status
Simulation time 8715811476 ps
CPU time 30.3 seconds
Started Jun 09 12:33:58 PM PDT 24
Finished Jun 09 12:34:29 PM PDT 24
Peak memory 200636 kb
Host smart-a4e66b3a-602c-4578-a57a-68b6b8adce47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286615098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.4286615098
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1154105423
Short name T444
Test name
Test status
Simulation time 422782055 ps
CPU time 2.22 seconds
Started Jun 09 12:34:01 PM PDT 24
Finished Jun 09 12:34:04 PM PDT 24
Peak memory 208560 kb
Host smart-597038a8-4c65-4983-b711-952a257ab4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154105423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1154105423
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2633385963
Short name T452
Test name
Test status
Simulation time 110024304 ps
CPU time 1.02 seconds
Started Jun 09 12:33:59 PM PDT 24
Finished Jun 09 12:34:00 PM PDT 24
Peak memory 200348 kb
Host smart-64a0a74c-3fa8-4916-ae0b-27e3fbe3ea96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633385963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2633385963
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.14057412
Short name T138
Test name
Test status
Simulation time 58656678 ps
CPU time 0.73 seconds
Started Jun 09 12:34:10 PM PDT 24
Finished Jun 09 12:34:12 PM PDT 24
Peak memory 200200 kb
Host smart-c6a63ba8-6554-4a09-840f-b33d9b3d57eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14057412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.14057412
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2808302539
Short name T519
Test name
Test status
Simulation time 1223705595 ps
CPU time 5.53 seconds
Started Jun 09 12:34:08 PM PDT 24
Finished Jun 09 12:34:15 PM PDT 24
Peak memory 217444 kb
Host smart-756ee983-b78b-412a-aed0-10477fed4de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808302539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2808302539
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2731803761
Short name T193
Test name
Test status
Simulation time 244750367 ps
CPU time 1.19 seconds
Started Jun 09 12:34:00 PM PDT 24
Finished Jun 09 12:34:01 PM PDT 24
Peak memory 217604 kb
Host smart-b0d8a6ae-ed7a-4216-bacd-e70491ba4d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731803761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2731803761
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.93439751
Short name T316
Test name
Test status
Simulation time 81120053 ps
CPU time 0.76 seconds
Started Jun 09 12:34:03 PM PDT 24
Finished Jun 09 12:34:05 PM PDT 24
Peak memory 200164 kb
Host smart-8dcb9f2e-9d2d-4dad-bda3-219fc71878d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93439751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.93439751
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1205652585
Short name T12
Test name
Test status
Simulation time 873326225 ps
CPU time 4.37 seconds
Started Jun 09 12:34:03 PM PDT 24
Finished Jun 09 12:34:08 PM PDT 24
Peak memory 200540 kb
Host smart-2dee4ab7-fe61-4dc9-a824-8743bdb80945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205652585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1205652585
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3809347483
Short name T243
Test name
Test status
Simulation time 173613303 ps
CPU time 1.2 seconds
Started Jun 09 12:34:04 PM PDT 24
Finished Jun 09 12:34:06 PM PDT 24
Peak memory 200348 kb
Host smart-efdce2ad-9f33-4af7-92c3-db2cfc22f49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809347483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3809347483
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3986517325
Short name T162
Test name
Test status
Simulation time 108735086 ps
CPU time 1.18 seconds
Started Jun 09 12:33:59 PM PDT 24
Finished Jun 09 12:34:01 PM PDT 24
Peak memory 200564 kb
Host smart-9c6cd1bc-d42e-4571-9981-efe555098c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986517325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3986517325
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1802269537
Short name T537
Test name
Test status
Simulation time 3989311394 ps
CPU time 16.91 seconds
Started Jun 09 12:34:12 PM PDT 24
Finished Jun 09 12:34:30 PM PDT 24
Peak memory 200688 kb
Host smart-8a88cc51-ebf9-4253-8a7c-136ed51da414
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802269537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1802269537
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2451860783
Short name T315
Test name
Test status
Simulation time 351905366 ps
CPU time 2.28 seconds
Started Jun 09 12:34:04 PM PDT 24
Finished Jun 09 12:34:08 PM PDT 24
Peak memory 200372 kb
Host smart-863cd5ba-613e-4de4-b2dd-63e36e81e506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451860783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2451860783
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.451523858
Short name T434
Test name
Test status
Simulation time 252148826 ps
CPU time 1.35 seconds
Started Jun 09 12:34:02 PM PDT 24
Finished Jun 09 12:34:04 PM PDT 24
Peak memory 200376 kb
Host smart-bb3086b6-b1b4-49e2-8ba4-c284320913e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451523858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.451523858
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.69481532
Short name T241
Test name
Test status
Simulation time 63956955 ps
CPU time 0.74 seconds
Started Jun 09 12:34:04 PM PDT 24
Finished Jun 09 12:34:06 PM PDT 24
Peak memory 200152 kb
Host smart-6e6b5838-9827-4349-b230-393dc991676c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69481532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.69481532
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1643912234
Short name T531
Test name
Test status
Simulation time 1224583117 ps
CPU time 5.31 seconds
Started Jun 09 12:33:53 PM PDT 24
Finished Jun 09 12:33:59 PM PDT 24
Peak memory 217996 kb
Host smart-5690e3db-5644-4f02-9f81-754717e0e020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643912234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1643912234
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3192580487
Short name T453
Test name
Test status
Simulation time 243863782 ps
CPU time 1.06 seconds
Started Jun 09 12:34:03 PM PDT 24
Finished Jun 09 12:34:06 PM PDT 24
Peak memory 217628 kb
Host smart-a07078d6-a82b-47eb-beff-6a73ad00015d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192580487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3192580487
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.4061060175
Short name T288
Test name
Test status
Simulation time 210785892 ps
CPU time 0.9 seconds
Started Jun 09 12:33:52 PM PDT 24
Finished Jun 09 12:33:53 PM PDT 24
Peak memory 200156 kb
Host smart-4f7f1900-625b-40b1-a350-7bc53fb6e09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061060175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.4061060175
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.824354943
Short name T209
Test name
Test status
Simulation time 936919665 ps
CPU time 4.68 seconds
Started Jun 09 12:34:03 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 200568 kb
Host smart-8df972c6-4aa0-4b7e-8945-d2d6fe886546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824354943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.824354943
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.357253974
Short name T205
Test name
Test status
Simulation time 146446377 ps
CPU time 1.1 seconds
Started Jun 09 12:34:00 PM PDT 24
Finished Jun 09 12:34:01 PM PDT 24
Peak memory 200340 kb
Host smart-ccd819b0-9cc3-4d2b-9dea-1678ad0aa1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357253974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.357253974
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.985165217
Short name T401
Test name
Test status
Simulation time 118151498 ps
CPU time 1.14 seconds
Started Jun 09 12:33:59 PM PDT 24
Finished Jun 09 12:34:01 PM PDT 24
Peak memory 200536 kb
Host smart-3944e2f9-7620-4e8f-83b1-b71abdb6bb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985165217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.985165217
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.1199669572
Short name T84
Test name
Test status
Simulation time 5267604895 ps
CPU time 21.86 seconds
Started Jun 09 12:33:59 PM PDT 24
Finished Jun 09 12:34:21 PM PDT 24
Peak memory 208908 kb
Host smart-16195348-ab1b-4928-aaac-19a4d83a9592
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199669572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1199669572
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1293165973
Short name T297
Test name
Test status
Simulation time 122480290 ps
CPU time 1.64 seconds
Started Jun 09 12:34:03 PM PDT 24
Finished Jun 09 12:34:06 PM PDT 24
Peak memory 208980 kb
Host smart-f1afa1b3-20ac-4357-b46e-2bbdf08dde63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293165973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1293165973
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3328822474
Short name T307
Test name
Test status
Simulation time 121452335 ps
CPU time 1.14 seconds
Started Jun 09 12:33:59 PM PDT 24
Finished Jun 09 12:34:11 PM PDT 24
Peak memory 200372 kb
Host smart-8aae2e08-7433-462c-9dfe-63c6de7b34e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328822474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3328822474
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1074825744
Short name T265
Test name
Test status
Simulation time 73234581 ps
CPU time 0.81 seconds
Started Jun 09 12:34:08 PM PDT 24
Finished Jun 09 12:34:10 PM PDT 24
Peak memory 200168 kb
Host smart-f1734e5a-14d2-4162-a19b-fb132be19d0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074825744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1074825744
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1184138326
Short name T34
Test name
Test status
Simulation time 1887665428 ps
CPU time 7 seconds
Started Jun 09 12:34:03 PM PDT 24
Finished Jun 09 12:34:11 PM PDT 24
Peak memory 217564 kb
Host smart-d9138ef5-a87d-4acc-97fb-3f6fb8708960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184138326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1184138326
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.839713072
Short name T234
Test name
Test status
Simulation time 244031580 ps
CPU time 1.05 seconds
Started Jun 09 12:33:58 PM PDT 24
Finished Jun 09 12:34:00 PM PDT 24
Peak memory 217484 kb
Host smart-04984111-e918-4561-9d1e-c1c578272e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839713072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.839713072
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3779007165
Short name T543
Test name
Test status
Simulation time 134579157 ps
CPU time 0.79 seconds
Started Jun 09 12:34:00 PM PDT 24
Finished Jun 09 12:34:07 PM PDT 24
Peak memory 200188 kb
Host smart-140d5760-2913-4295-95b9-eae0b2462d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779007165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3779007165
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.1018891957
Short name T420
Test name
Test status
Simulation time 1491009499 ps
CPU time 6.08 seconds
Started Jun 09 12:34:00 PM PDT 24
Finished Jun 09 12:34:06 PM PDT 24
Peak memory 200512 kb
Host smart-9c1aed0d-5cb6-4956-95e0-ee4877e8aeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018891957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1018891957
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1812432714
Short name T278
Test name
Test status
Simulation time 152150545 ps
CPU time 1.16 seconds
Started Jun 09 12:34:01 PM PDT 24
Finished Jun 09 12:34:03 PM PDT 24
Peak memory 200292 kb
Host smart-6ccbfa70-9bd1-4f2c-b030-0270667dbce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812432714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1812432714
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.183163226
Short name T357
Test name
Test status
Simulation time 119025977 ps
CPU time 1.21 seconds
Started Jun 09 12:33:58 PM PDT 24
Finished Jun 09 12:34:00 PM PDT 24
Peak memory 200508 kb
Host smart-d2306085-d726-4b29-8fa8-7b74e529f825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183163226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.183163226
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2023355093
Short name T467
Test name
Test status
Simulation time 2779808503 ps
CPU time 11.87 seconds
Started Jun 09 12:34:01 PM PDT 24
Finished Jun 09 12:34:14 PM PDT 24
Peak memory 200708 kb
Host smart-dce0a35f-14dc-4032-8dc5-cbf743835b69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023355093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2023355093
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.3118709552
Short name T482
Test name
Test status
Simulation time 131151979 ps
CPU time 1.68 seconds
Started Jun 09 12:34:09 PM PDT 24
Finished Jun 09 12:34:13 PM PDT 24
Peak memory 208536 kb
Host smart-2ac7c482-e0ce-4edd-a4ea-118e9cbd5c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118709552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.3118709552
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.4078194425
Short name T143
Test name
Test status
Simulation time 148622952 ps
CPU time 1.15 seconds
Started Jun 09 12:33:53 PM PDT 24
Finished Jun 09 12:33:55 PM PDT 24
Peak memory 200296 kb
Host smart-d51a1ce2-4e73-42cf-a2a9-51de61ee88f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078194425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.4078194425
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3646937223
Short name T389
Test name
Test status
Simulation time 62870538 ps
CPU time 0.72 seconds
Started Jun 09 12:34:10 PM PDT 24
Finished Jun 09 12:34:13 PM PDT 24
Peak memory 200164 kb
Host smart-808aa63e-440b-44e3-a854-2e336b98623c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646937223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3646937223
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1704852430
Short name T322
Test name
Test status
Simulation time 1888053945 ps
CPU time 7.17 seconds
Started Jun 09 12:34:05 PM PDT 24
Finished Jun 09 12:34:14 PM PDT 24
Peak memory 217928 kb
Host smart-a8a6f558-e382-4688-bfb5-d75f156d3925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704852430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1704852430
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2834327268
Short name T310
Test name
Test status
Simulation time 244528254 ps
CPU time 1.07 seconds
Started Jun 09 12:34:03 PM PDT 24
Finished Jun 09 12:34:05 PM PDT 24
Peak memory 217612 kb
Host smart-bf819fc3-45fd-4a7c-94b2-eba1fed490f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834327268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2834327268
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.743653776
Short name T264
Test name
Test status
Simulation time 167272230 ps
CPU time 0.87 seconds
Started Jun 09 12:34:07 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 200124 kb
Host smart-dc45b428-86a8-451f-b783-c733fabb4b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743653776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.743653776
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1356644172
Short name T458
Test name
Test status
Simulation time 1639714136 ps
CPU time 6.43 seconds
Started Jun 09 12:34:03 PM PDT 24
Finished Jun 09 12:34:11 PM PDT 24
Peak memory 200480 kb
Host smart-02b6409e-b849-48a7-bb92-683dc141a0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356644172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1356644172
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2667019640
Short name T28
Test name
Test status
Simulation time 102954488 ps
CPU time 0.96 seconds
Started Jun 09 12:34:02 PM PDT 24
Finished Jun 09 12:34:04 PM PDT 24
Peak memory 200332 kb
Host smart-0860aa1f-3b2c-47f9-bca0-5594d341147d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667019640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2667019640
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2826897940
Short name T122
Test name
Test status
Simulation time 250206228 ps
CPU time 1.43 seconds
Started Jun 09 12:34:10 PM PDT 24
Finished Jun 09 12:34:13 PM PDT 24
Peak memory 200540 kb
Host smart-c3716e25-48cc-434f-add6-d7d44413228e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826897940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2826897940
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1457423583
Short name T302
Test name
Test status
Simulation time 7579420221 ps
CPU time 31.65 seconds
Started Jun 09 12:34:05 PM PDT 24
Finished Jun 09 12:34:38 PM PDT 24
Peak memory 210936 kb
Host smart-aa7aa87e-1339-4c4a-bf29-feb505f3040b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457423583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1457423583
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3552546971
Short name T343
Test name
Test status
Simulation time 356985684 ps
CPU time 2.03 seconds
Started Jun 09 12:34:01 PM PDT 24
Finished Jun 09 12:34:04 PM PDT 24
Peak memory 208624 kb
Host smart-2d2ca740-13da-45d7-ab0a-9608531b5b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552546971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3552546971
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.295647330
Short name T478
Test name
Test status
Simulation time 190160430 ps
CPU time 1.22 seconds
Started Jun 09 12:34:03 PM PDT 24
Finished Jun 09 12:34:05 PM PDT 24
Peak memory 200308 kb
Host smart-b4a6ce19-dec7-46a8-bcd2-a25f9bca47fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295647330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.295647330
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3509721554
Short name T273
Test name
Test status
Simulation time 79325307 ps
CPU time 0.77 seconds
Started Jun 09 12:34:14 PM PDT 24
Finished Jun 09 12:34:15 PM PDT 24
Peak memory 200156 kb
Host smart-4207956b-a399-4463-91c5-e58ec922f76e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509721554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3509721554
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.736651071
Short name T300
Test name
Test status
Simulation time 2348212777 ps
CPU time 8.13 seconds
Started Jun 09 12:34:00 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 217312 kb
Host smart-104dd3ba-5abc-4283-9864-e9d6ad1877e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736651071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.736651071
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2410017872
Short name T489
Test name
Test status
Simulation time 243743016 ps
CPU time 1.09 seconds
Started Jun 09 12:34:10 PM PDT 24
Finished Jun 09 12:34:12 PM PDT 24
Peak memory 217584 kb
Host smart-958cac8c-98d7-48d8-bc2d-3820f6cc4c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410017872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2410017872
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1547639739
Short name T252
Test name
Test status
Simulation time 163122623 ps
CPU time 0.85 seconds
Started Jun 09 12:34:04 PM PDT 24
Finished Jun 09 12:34:06 PM PDT 24
Peak memory 200160 kb
Host smart-a361c2c3-7cc3-49e8-adf9-d008eff47b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547639739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1547639739
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1725472583
Short name T511
Test name
Test status
Simulation time 806540726 ps
CPU time 4.35 seconds
Started Jun 09 12:34:13 PM PDT 24
Finished Jun 09 12:34:18 PM PDT 24
Peak memory 200548 kb
Host smart-48496a3d-bf18-41d2-bf22-7c3ea30f707e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725472583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1725472583
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2448409078
Short name T319
Test name
Test status
Simulation time 165109299 ps
CPU time 1.15 seconds
Started Jun 09 12:34:05 PM PDT 24
Finished Jun 09 12:34:08 PM PDT 24
Peak memory 200360 kb
Host smart-e3a846c3-460b-412c-9405-867e403ffcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448409078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2448409078
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.2667420187
Short name T11
Test name
Test status
Simulation time 252112854 ps
CPU time 1.38 seconds
Started Jun 09 12:34:08 PM PDT 24
Finished Jun 09 12:34:11 PM PDT 24
Peak memory 200464 kb
Host smart-808eac0c-f7f4-4ef7-ac8d-9d5e0f53502e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667420187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.2667420187
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3283115813
Short name T204
Test name
Test status
Simulation time 3882936825 ps
CPU time 18.31 seconds
Started Jun 09 12:33:58 PM PDT 24
Finished Jun 09 12:34:17 PM PDT 24
Peak memory 216564 kb
Host smart-e167d1dd-dde5-4bf1-8413-a8056fbda6f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283115813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3283115813
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.1463684863
Short name T504
Test name
Test status
Simulation time 360286637 ps
CPU time 2.29 seconds
Started Jun 09 12:34:07 PM PDT 24
Finished Jun 09 12:34:10 PM PDT 24
Peak memory 200308 kb
Host smart-d1f4b9d3-26ca-485c-85fa-60568f19a882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463684863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.1463684863
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3570338763
Short name T430
Test name
Test status
Simulation time 87621257 ps
CPU time 0.81 seconds
Started Jun 09 12:34:08 PM PDT 24
Finished Jun 09 12:34:10 PM PDT 24
Peak memory 200544 kb
Host smart-c4651825-57e4-4ac4-aaf1-8656f6e1d186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570338763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3570338763
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1559103888
Short name T529
Test name
Test status
Simulation time 64446039 ps
CPU time 0.74 seconds
Started Jun 09 12:34:03 PM PDT 24
Finished Jun 09 12:34:04 PM PDT 24
Peak memory 200164 kb
Host smart-29d6b75a-67f3-487d-9bf0-b46c0acd049f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559103888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1559103888
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1174936822
Short name T280
Test name
Test status
Simulation time 2346924229 ps
CPU time 7.63 seconds
Started Jun 09 12:34:06 PM PDT 24
Finished Jun 09 12:34:15 PM PDT 24
Peak memory 218024 kb
Host smart-c187e8e0-00b6-4e18-b079-00a860943f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174936822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1174936822
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1010677779
Short name T477
Test name
Test status
Simulation time 245033301 ps
CPU time 1.03 seconds
Started Jun 09 12:34:13 PM PDT 24
Finished Jun 09 12:34:15 PM PDT 24
Peak memory 218524 kb
Host smart-c6916257-8f5a-425f-989d-bad10385d6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010677779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1010677779
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.3890384732
Short name T283
Test name
Test status
Simulation time 206832770 ps
CPU time 0.9 seconds
Started Jun 09 12:34:13 PM PDT 24
Finished Jun 09 12:34:15 PM PDT 24
Peak memory 200160 kb
Host smart-0e1da5fb-837c-4b34-a83c-446e6564777d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890384732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3890384732
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.806568700
Short name T175
Test name
Test status
Simulation time 672575144 ps
CPU time 3.53 seconds
Started Jun 09 12:34:00 PM PDT 24
Finished Jun 09 12:34:05 PM PDT 24
Peak memory 200544 kb
Host smart-9e5e03cc-9d95-49d4-9b4d-efd094fa67ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806568700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.806568700
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3443629879
Short name T181
Test name
Test status
Simulation time 187408667 ps
CPU time 1.21 seconds
Started Jun 09 12:34:03 PM PDT 24
Finished Jun 09 12:34:06 PM PDT 24
Peak memory 200364 kb
Host smart-5fec5a55-75aa-4e47-986d-e1d1538b8ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443629879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3443629879
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.731058978
Short name T228
Test name
Test status
Simulation time 195986792 ps
CPU time 1.38 seconds
Started Jun 09 12:34:08 PM PDT 24
Finished Jun 09 12:34:11 PM PDT 24
Peak memory 200512 kb
Host smart-70821786-0117-4a96-bb9a-db91570a09de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731058978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.731058978
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3988898040
Short name T431
Test name
Test status
Simulation time 564586864 ps
CPU time 2.39 seconds
Started Jun 09 12:34:06 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 200560 kb
Host smart-976ad83a-f92b-4db9-a936-a88892dff5da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988898040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3988898040
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3353129982
Short name T449
Test name
Test status
Simulation time 119372999 ps
CPU time 1.47 seconds
Started Jun 09 12:34:06 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 200328 kb
Host smart-91cf7072-e3ff-42dc-94fb-48f743f51122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353129982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3353129982
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2918900744
Short name T327
Test name
Test status
Simulation time 93949620 ps
CPU time 0.87 seconds
Started Jun 09 12:34:01 PM PDT 24
Finished Jun 09 12:34:03 PM PDT 24
Peak memory 200272 kb
Host smart-dce4760e-b242-4335-bc3b-ebfa4d35a28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918900744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2918900744
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3990908419
Short name T48
Test name
Test status
Simulation time 75574149 ps
CPU time 0.81 seconds
Started Jun 09 12:34:10 PM PDT 24
Finished Jun 09 12:34:12 PM PDT 24
Peak memory 200108 kb
Host smart-b7156342-0451-42db-a778-f03e0f207178
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990908419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3990908419
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1562463308
Short name T36
Test name
Test status
Simulation time 1889135913 ps
CPU time 7.69 seconds
Started Jun 09 12:34:08 PM PDT 24
Finished Jun 09 12:34:17 PM PDT 24
Peak memory 217996 kb
Host smart-49a5b07a-ffe1-43c1-8b9e-3c8484f15826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562463308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1562463308
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2402126015
Short name T331
Test name
Test status
Simulation time 243998378 ps
CPU time 1.17 seconds
Started Jun 09 12:33:58 PM PDT 24
Finished Jun 09 12:34:00 PM PDT 24
Peak memory 217628 kb
Host smart-61af3146-c161-4440-b94e-141488d15474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402126015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2402126015
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3576397232
Short name T317
Test name
Test status
Simulation time 101374305 ps
CPU time 0.75 seconds
Started Jun 09 12:34:10 PM PDT 24
Finished Jun 09 12:34:12 PM PDT 24
Peak memory 200164 kb
Host smart-b878142c-d806-4c44-a668-65672a914d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576397232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3576397232
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3550892531
Short name T82
Test name
Test status
Simulation time 2114513337 ps
CPU time 7.96 seconds
Started Jun 09 12:34:06 PM PDT 24
Finished Jun 09 12:34:15 PM PDT 24
Peak memory 200568 kb
Host smart-0f4fca26-f2c0-4beb-a900-4bee3086eb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550892531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3550892531
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.555430660
Short name T388
Test name
Test status
Simulation time 175114026 ps
CPU time 1.21 seconds
Started Jun 09 12:34:01 PM PDT 24
Finished Jun 09 12:34:03 PM PDT 24
Peak memory 200376 kb
Host smart-bf4641cd-496d-4d8c-8786-16838caa01e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555430660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.555430660
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.3388913208
Short name T332
Test name
Test status
Simulation time 118401199 ps
CPU time 1.13 seconds
Started Jun 09 12:34:08 PM PDT 24
Finished Jun 09 12:34:11 PM PDT 24
Peak memory 200532 kb
Host smart-5928a74e-3b1f-498d-a658-659879732e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388913208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3388913208
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1744358753
Short name T167
Test name
Test status
Simulation time 4476848660 ps
CPU time 17.69 seconds
Started Jun 09 12:34:12 PM PDT 24
Finished Jun 09 12:34:31 PM PDT 24
Peak memory 209384 kb
Host smart-868b04d0-f1c3-43ec-b675-8b1657f8f37d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744358753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1744358753
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.4159467678
Short name T4
Test name
Test status
Simulation time 131109336 ps
CPU time 1.69 seconds
Started Jun 09 12:34:07 PM PDT 24
Finished Jun 09 12:34:10 PM PDT 24
Peak memory 200400 kb
Host smart-3824a45c-6aa6-41a5-8e0c-0b0cc1689d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159467678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.4159467678
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.88370742
Short name T191
Test name
Test status
Simulation time 77830216 ps
CPU time 0.79 seconds
Started Jun 09 12:34:13 PM PDT 24
Finished Jun 09 12:34:14 PM PDT 24
Peak memory 200372 kb
Host smart-41635a47-6b44-4ce2-92e3-88e904ba78ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88370742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.88370742
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.2030388471
Short name T174
Test name
Test status
Simulation time 62330308 ps
CPU time 0.71 seconds
Started Jun 09 12:34:08 PM PDT 24
Finished Jun 09 12:34:10 PM PDT 24
Peak memory 200112 kb
Host smart-eb8bb908-5944-4a4f-bc71-d8474d77a549
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030388471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2030388471
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1471066750
Short name T56
Test name
Test status
Simulation time 1234373602 ps
CPU time 5.2 seconds
Started Jun 09 12:34:12 PM PDT 24
Finished Jun 09 12:34:19 PM PDT 24
Peak memory 218044 kb
Host smart-f30895bc-18ed-4715-ad59-8db689524501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471066750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1471066750
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3852786009
Short name T260
Test name
Test status
Simulation time 244828152 ps
CPU time 1.17 seconds
Started Jun 09 12:34:06 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 217624 kb
Host smart-96efece9-fc7c-4f74-a763-44b383abec78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852786009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3852786009
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.284950183
Short name T394
Test name
Test status
Simulation time 87865023 ps
CPU time 0.75 seconds
Started Jun 09 12:34:08 PM PDT 24
Finished Jun 09 12:34:10 PM PDT 24
Peak memory 200156 kb
Host smart-4ef34bcc-eb49-4124-96e9-eb5e84e950d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284950183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.284950183
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.680203926
Short name T542
Test name
Test status
Simulation time 1310498403 ps
CPU time 5.07 seconds
Started Jun 09 12:34:09 PM PDT 24
Finished Jun 09 12:34:15 PM PDT 24
Peak memory 200600 kb
Host smart-7c12b645-2b63-4136-af0c-9e9a5fe52de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680203926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.680203926
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.4079119093
Short name T379
Test name
Test status
Simulation time 99576745 ps
CPU time 1 seconds
Started Jun 09 12:34:16 PM PDT 24
Finished Jun 09 12:34:17 PM PDT 24
Peak memory 200348 kb
Host smart-26449bb0-7815-49bd-a05c-39620da87bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079119093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.4079119093
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3888140567
Short name T439
Test name
Test status
Simulation time 197606350 ps
CPU time 1.41 seconds
Started Jun 09 12:34:04 PM PDT 24
Finished Jun 09 12:34:06 PM PDT 24
Peak memory 200592 kb
Host smart-f30517d8-4c1d-4e25-88dc-37e5207a4284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888140567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3888140567
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2283445097
Short name T75
Test name
Test status
Simulation time 3060385148 ps
CPU time 13.15 seconds
Started Jun 09 12:34:02 PM PDT 24
Finished Jun 09 12:34:16 PM PDT 24
Peak memory 208964 kb
Host smart-94e4aa25-8699-4214-9067-3ebcb8a64f9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283445097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2283445097
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2697470322
Short name T407
Test name
Test status
Simulation time 131397538 ps
CPU time 1.63 seconds
Started Jun 09 12:34:02 PM PDT 24
Finished Jun 09 12:34:04 PM PDT 24
Peak memory 200364 kb
Host smart-94f9bb18-d19f-4981-8a38-0a1c47cdb207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697470322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2697470322
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1657211328
Short name T378
Test name
Test status
Simulation time 92738658 ps
CPU time 0.87 seconds
Started Jun 09 12:34:09 PM PDT 24
Finished Jun 09 12:34:11 PM PDT 24
Peak memory 200296 kb
Host smart-064b329f-6ca0-4b6a-88eb-df7a397230ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657211328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1657211328
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.2408411399
Short name T219
Test name
Test status
Simulation time 58867038 ps
CPU time 0.73 seconds
Started Jun 09 12:33:44 PM PDT 24
Finished Jun 09 12:33:45 PM PDT 24
Peak memory 200128 kb
Host smart-e5481a44-1249-4bc1-851b-183affec4c00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408411399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.2408411399
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.722652682
Short name T346
Test name
Test status
Simulation time 2166969806 ps
CPU time 7.36 seconds
Started Jun 09 12:33:16 PM PDT 24
Finished Jun 09 12:33:24 PM PDT 24
Peak memory 217692 kb
Host smart-1d5c5f33-236d-4e04-ab88-05b4a70d4986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722652682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.722652682
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1921592791
Short name T506
Test name
Test status
Simulation time 243658684 ps
CPU time 1.03 seconds
Started Jun 09 12:33:52 PM PDT 24
Finished Jun 09 12:33:53 PM PDT 24
Peak memory 217532 kb
Host smart-562c62c9-6652-420d-8865-032186d4cbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921592791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1921592791
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2470494894
Short name T426
Test name
Test status
Simulation time 170734385 ps
CPU time 0.82 seconds
Started Jun 09 12:33:24 PM PDT 24
Finished Jun 09 12:33:26 PM PDT 24
Peak memory 200184 kb
Host smart-0f22c9e4-a0a2-485f-9534-2c757060a59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470494894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2470494894
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3715550975
Short name T339
Test name
Test status
Simulation time 1705251188 ps
CPU time 6.54 seconds
Started Jun 09 12:33:33 PM PDT 24
Finished Jun 09 12:33:40 PM PDT 24
Peak memory 200488 kb
Host smart-7d24377d-2708-477c-a170-928da025a28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715550975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3715550975
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1284287144
Short name T73
Test name
Test status
Simulation time 20713284388 ps
CPU time 31.28 seconds
Started Jun 09 12:33:53 PM PDT 24
Finished Jun 09 12:34:25 PM PDT 24
Peak memory 217644 kb
Host smart-b4f649af-91c3-4972-be14-981780ec0956
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284287144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1284287144
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1228932438
Short name T518
Test name
Test status
Simulation time 174774168 ps
CPU time 1.22 seconds
Started Jun 09 12:33:32 PM PDT 24
Finished Jun 09 12:33:33 PM PDT 24
Peak memory 200312 kb
Host smart-bbf6ca9d-905e-481a-8c85-04bf879cd15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228932438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1228932438
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1369289152
Short name T256
Test name
Test status
Simulation time 113613542 ps
CPU time 1.17 seconds
Started Jun 09 12:33:49 PM PDT 24
Finished Jun 09 12:33:50 PM PDT 24
Peak memory 200544 kb
Host smart-e09a5524-62ad-4670-a36c-662a6901fa75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369289152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1369289152
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.2055586442
Short name T534
Test name
Test status
Simulation time 3232642202 ps
CPU time 14.27 seconds
Started Jun 09 12:33:20 PM PDT 24
Finished Jun 09 12:33:34 PM PDT 24
Peak memory 208836 kb
Host smart-0e2982b3-7f18-44cd-9afc-b9916abc3a97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055586442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2055586442
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3904913329
Short name T253
Test name
Test status
Simulation time 537492468 ps
CPU time 2.78 seconds
Started Jun 09 12:33:40 PM PDT 24
Finished Jun 09 12:33:44 PM PDT 24
Peak memory 200320 kb
Host smart-f87d5926-c73a-414e-a972-9b8d69adbb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904913329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3904913329
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3283686012
Short name T159
Test name
Test status
Simulation time 104202744 ps
CPU time 0.88 seconds
Started Jun 09 12:33:29 PM PDT 24
Finished Jun 09 12:33:31 PM PDT 24
Peak memory 200360 kb
Host smart-fe44d89b-c375-4686-82cf-1e6c09b055f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283686012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3283686012
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3034475439
Short name T141
Test name
Test status
Simulation time 75449389 ps
CPU time 0.81 seconds
Started Jun 09 12:34:05 PM PDT 24
Finished Jun 09 12:34:07 PM PDT 24
Peak memory 200188 kb
Host smart-d8b082fd-eca0-4683-b3f7-68f4d8a59acc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034475439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3034475439
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.2784441643
Short name T43
Test name
Test status
Simulation time 1217050376 ps
CPU time 6.01 seconds
Started Jun 09 12:34:10 PM PDT 24
Finished Jun 09 12:34:17 PM PDT 24
Peak memory 221976 kb
Host smart-a6170ddb-a788-418b-adb8-c6bf60bef40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784441643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2784441643
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.829464412
Short name T245
Test name
Test status
Simulation time 244247077 ps
CPU time 1.09 seconds
Started Jun 09 12:34:08 PM PDT 24
Finished Jun 09 12:34:10 PM PDT 24
Peak memory 217516 kb
Host smart-43d19c31-aeb3-4d5f-ab46-a4d2f8baa019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829464412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.829464412
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1183105282
Short name T522
Test name
Test status
Simulation time 99866200 ps
CPU time 0.73 seconds
Started Jun 09 12:34:09 PM PDT 24
Finished Jun 09 12:34:11 PM PDT 24
Peak memory 200148 kb
Host smart-47f33fa0-ede5-421c-918b-7a0146ce68ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183105282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1183105282
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3681090589
Short name T236
Test name
Test status
Simulation time 1610260870 ps
CPU time 6.91 seconds
Started Jun 09 12:34:11 PM PDT 24
Finished Jun 09 12:34:20 PM PDT 24
Peak memory 200560 kb
Host smart-c67dc642-d211-4104-97d3-03ed24220087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681090589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3681090589
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1447392562
Short name T512
Test name
Test status
Simulation time 154731629 ps
CPU time 1.13 seconds
Started Jun 09 12:34:10 PM PDT 24
Finished Jun 09 12:34:17 PM PDT 24
Peak memory 200352 kb
Host smart-c19f8d2c-d33e-4b75-bcf1-cdfc040ea76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447392562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1447392562
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.745946532
Short name T334
Test name
Test status
Simulation time 256951984 ps
CPU time 1.51 seconds
Started Jun 09 12:33:57 PM PDT 24
Finished Jun 09 12:33:59 PM PDT 24
Peak memory 200548 kb
Host smart-e638187f-5fe3-474c-b1d7-9416d3cbf0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745946532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.745946532
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2776223200
Short name T81
Test name
Test status
Simulation time 4547061244 ps
CPU time 21.22 seconds
Started Jun 09 12:34:10 PM PDT 24
Finished Jun 09 12:34:42 PM PDT 24
Peak memory 208896 kb
Host smart-3a7ca730-d0c7-4c36-89a2-99b86fb0eda4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776223200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2776223200
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.51744233
Short name T31
Test name
Test status
Simulation time 391834111 ps
CPU time 2.1 seconds
Started Jun 09 12:34:07 PM PDT 24
Finished Jun 09 12:34:10 PM PDT 24
Peak memory 200292 kb
Host smart-3423684b-ef36-4d1c-b482-f9f8452d211e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51744233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.51744233
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.856261725
Short name T207
Test name
Test status
Simulation time 148875129 ps
CPU time 1.19 seconds
Started Jun 09 12:34:03 PM PDT 24
Finished Jun 09 12:34:05 PM PDT 24
Peak memory 200308 kb
Host smart-60f1c690-4a73-47c8-b373-566f41277845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856261725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.856261725
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.823929164
Short name T455
Test name
Test status
Simulation time 79568030 ps
CPU time 0.76 seconds
Started Jun 09 12:34:10 PM PDT 24
Finished Jun 09 12:34:12 PM PDT 24
Peak memory 200172 kb
Host smart-b7fd8e03-1a83-46cb-a4a0-19d3315baf36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823929164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.823929164
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2240769608
Short name T410
Test name
Test status
Simulation time 1895129945 ps
CPU time 6.79 seconds
Started Jun 09 12:34:10 PM PDT 24
Finished Jun 09 12:34:18 PM PDT 24
Peak memory 217040 kb
Host smart-d8d94125-e116-4bb7-bba8-9e8b632ee0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240769608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2240769608
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3185512665
Short name T133
Test name
Test status
Simulation time 244110110 ps
CPU time 1.1 seconds
Started Jun 09 12:34:07 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 217556 kb
Host smart-495b51bb-e40d-45c7-9636-8d955580ffc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185512665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3185512665
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.4130009705
Short name T214
Test name
Test status
Simulation time 172957092 ps
CPU time 0.85 seconds
Started Jun 09 12:34:02 PM PDT 24
Finished Jun 09 12:34:04 PM PDT 24
Peak memory 200188 kb
Host smart-a6b1f33a-128a-4958-b7ff-376458a768e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130009705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.4130009705
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2648587793
Short name T1
Test name
Test status
Simulation time 1015621420 ps
CPU time 4.87 seconds
Started Jun 09 12:34:04 PM PDT 24
Finished Jun 09 12:34:10 PM PDT 24
Peak memory 200568 kb
Host smart-0b4c82f7-f070-4d5b-bfd9-6d956de9f335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648587793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2648587793
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.377285000
Short name T294
Test name
Test status
Simulation time 165150398 ps
CPU time 1.15 seconds
Started Jun 09 12:34:09 PM PDT 24
Finished Jun 09 12:34:12 PM PDT 24
Peak memory 200360 kb
Host smart-08dc169f-02c0-4ee4-8bda-d21204c51784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377285000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.377285000
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.255624846
Short name T384
Test name
Test status
Simulation time 250941215 ps
CPU time 1.52 seconds
Started Jun 09 12:34:13 PM PDT 24
Finished Jun 09 12:34:15 PM PDT 24
Peak memory 200544 kb
Host smart-5e01ef38-25bf-4a9e-a9c7-abee88fe792f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255624846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.255624846
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2747661045
Short name T259
Test name
Test status
Simulation time 2846310442 ps
CPU time 10.47 seconds
Started Jun 09 12:34:03 PM PDT 24
Finished Jun 09 12:34:15 PM PDT 24
Peak memory 200688 kb
Host smart-8813c431-9b35-40f6-b91a-a7052b8fe013
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747661045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2747661045
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1812634995
Short name T516
Test name
Test status
Simulation time 386151703 ps
CPU time 2.23 seconds
Started Jun 09 12:34:15 PM PDT 24
Finished Jun 09 12:34:18 PM PDT 24
Peak memory 208564 kb
Host smart-f6df21b3-6186-48ca-9d62-5c05f80e0e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812634995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1812634995
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.294831825
Short name T145
Test name
Test status
Simulation time 73448640 ps
CPU time 0.85 seconds
Started Jun 09 12:35:07 PM PDT 24
Finished Jun 09 12:35:10 PM PDT 24
Peak memory 199428 kb
Host smart-0ac70082-2771-4231-9b69-c66af2ed523f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294831825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.294831825
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2057291119
Short name T546
Test name
Test status
Simulation time 70402908 ps
CPU time 0.76 seconds
Started Jun 09 12:34:06 PM PDT 24
Finished Jun 09 12:34:08 PM PDT 24
Peak memory 200160 kb
Host smart-d581c7ef-c3e9-46eb-9179-e577ccf6299b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057291119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2057291119
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.3458703396
Short name T325
Test name
Test status
Simulation time 1885668700 ps
CPU time 7.79 seconds
Started Jun 09 12:34:14 PM PDT 24
Finished Jun 09 12:34:23 PM PDT 24
Peak memory 230156 kb
Host smart-816bdd47-1ebb-47f3-bae1-31e0a1e1cb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458703396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3458703396
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3488852834
Short name T352
Test name
Test status
Simulation time 275623162 ps
CPU time 1.12 seconds
Started Jun 09 12:34:09 PM PDT 24
Finished Jun 09 12:34:11 PM PDT 24
Peak memory 217672 kb
Host smart-f51add97-967b-4d5b-b012-f87323fef20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488852834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3488852834
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1041434203
Short name T183
Test name
Test status
Simulation time 169276966 ps
CPU time 0.82 seconds
Started Jun 09 12:34:15 PM PDT 24
Finished Jun 09 12:34:16 PM PDT 24
Peak memory 200188 kb
Host smart-e3033eb0-dbe9-4fad-93ed-4b8e4ab91e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041434203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1041434203
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2532188090
Short name T487
Test name
Test status
Simulation time 1264630022 ps
CPU time 5.14 seconds
Started Jun 09 12:34:27 PM PDT 24
Finished Jun 09 12:34:33 PM PDT 24
Peak memory 200588 kb
Host smart-b6aaa2d2-a5ca-4f92-8286-5e7658e5165e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532188090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2532188090
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1934832226
Short name T210
Test name
Test status
Simulation time 114909983 ps
CPU time 1.13 seconds
Started Jun 09 12:34:11 PM PDT 24
Finished Jun 09 12:34:14 PM PDT 24
Peak memory 200536 kb
Host smart-6b7d7ff0-18d8-49ca-8eea-6c2d6f5cddf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934832226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1934832226
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2876745517
Short name T396
Test name
Test status
Simulation time 3132423224 ps
CPU time 11.3 seconds
Started Jun 09 12:34:14 PM PDT 24
Finished Jun 09 12:34:26 PM PDT 24
Peak memory 200820 kb
Host smart-57801398-db7f-4432-9101-ed018431a535
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876745517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2876745517
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.857698364
Short name T374
Test name
Test status
Simulation time 546623916 ps
CPU time 2.89 seconds
Started Jun 09 12:34:11 PM PDT 24
Finished Jun 09 12:34:16 PM PDT 24
Peak memory 200340 kb
Host smart-749c98d2-c4f9-4e66-8a40-dd3ff046b980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857698364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.857698364
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.3971525401
Short name T370
Test name
Test status
Simulation time 125490890 ps
CPU time 0.99 seconds
Started Jun 09 12:34:03 PM PDT 24
Finished Jun 09 12:34:05 PM PDT 24
Peak memory 200352 kb
Host smart-e4aa584d-ef00-40d3-bd50-183f1603efa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971525401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3971525401
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1294075295
Short name T441
Test name
Test status
Simulation time 70612091 ps
CPU time 0.72 seconds
Started Jun 09 12:34:05 PM PDT 24
Finished Jun 09 12:34:07 PM PDT 24
Peak memory 200172 kb
Host smart-928281ee-64a3-4b4b-8a48-c2adb2c0e72c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294075295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1294075295
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.1380059857
Short name T413
Test name
Test status
Simulation time 1879877029 ps
CPU time 7.04 seconds
Started Jun 09 12:34:00 PM PDT 24
Finished Jun 09 12:34:08 PM PDT 24
Peak memory 221764 kb
Host smart-374fd69b-bf9d-4f58-a3d1-8ef89f0bd09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380059857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.1380059857
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3875297028
Short name T272
Test name
Test status
Simulation time 246699243 ps
CPU time 1.07 seconds
Started Jun 09 12:34:10 PM PDT 24
Finished Jun 09 12:34:13 PM PDT 24
Peak memory 217548 kb
Host smart-f723f25b-7992-4604-8cf3-0dfdb6c963b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875297028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3875297028
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.3625155113
Short name T24
Test name
Test status
Simulation time 159577254 ps
CPU time 0.86 seconds
Started Jun 09 12:34:07 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 200128 kb
Host smart-41e84108-2e11-4d95-889d-2562df6b5f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625155113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3625155113
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.2236794946
Short name T525
Test name
Test status
Simulation time 1080340631 ps
CPU time 5.33 seconds
Started Jun 09 12:34:01 PM PDT 24
Finished Jun 09 12:34:07 PM PDT 24
Peak memory 200520 kb
Host smart-138d2bb7-1dca-43e0-a67d-55d0ed4dc0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236794946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.2236794946
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.570942070
Short name T262
Test name
Test status
Simulation time 145541618 ps
CPU time 1.08 seconds
Started Jun 09 12:34:03 PM PDT 24
Finished Jun 09 12:34:10 PM PDT 24
Peak memory 200368 kb
Host smart-21cf70a2-111b-4091-ba48-c6a023bc30f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570942070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.570942070
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2554858633
Short name T195
Test name
Test status
Simulation time 206661335 ps
CPU time 1.32 seconds
Started Jun 09 12:34:00 PM PDT 24
Finished Jun 09 12:34:02 PM PDT 24
Peak memory 200540 kb
Host smart-bab6099d-8809-4eb4-a936-0ee68f9c88b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554858633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2554858633
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.837238607
Short name T509
Test name
Test status
Simulation time 6017948073 ps
CPU time 21.23 seconds
Started Jun 09 12:34:08 PM PDT 24
Finished Jun 09 12:34:31 PM PDT 24
Peak memory 210808 kb
Host smart-a9e6dad4-01f8-4d3b-82ad-495c06fbd664
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837238607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.837238607
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3895897339
Short name T157
Test name
Test status
Simulation time 375694757 ps
CPU time 2.38 seconds
Started Jun 09 12:34:11 PM PDT 24
Finished Jun 09 12:34:19 PM PDT 24
Peak memory 200328 kb
Host smart-839cbd85-6ba7-42a3-9be4-52ef78986c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895897339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3895897339
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.758244419
Short name T126
Test name
Test status
Simulation time 100708055 ps
CPU time 0.93 seconds
Started Jun 09 12:34:06 PM PDT 24
Finished Jun 09 12:34:08 PM PDT 24
Peak memory 200344 kb
Host smart-b72f926f-5b0d-4973-9f7f-e785c60e3cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758244419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.758244419
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.4235987472
Short name T284
Test name
Test status
Simulation time 90824949 ps
CPU time 0.79 seconds
Started Jun 09 12:34:17 PM PDT 24
Finished Jun 09 12:34:18 PM PDT 24
Peak memory 200168 kb
Host smart-f3991050-18e5-4d14-855d-3d515fc0f757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235987472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.4235987472
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.140027848
Short name T466
Test name
Test status
Simulation time 2170675699 ps
CPU time 7.29 seconds
Started Jun 09 12:34:02 PM PDT 24
Finished Jun 09 12:34:10 PM PDT 24
Peak memory 218128 kb
Host smart-18b1b045-5dd1-4ef3-9eac-3e1640e438d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140027848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.140027848
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1109471751
Short name T8
Test name
Test status
Simulation time 245070420 ps
CPU time 1.11 seconds
Started Jun 09 12:34:01 PM PDT 24
Finished Jun 09 12:34:03 PM PDT 24
Peak memory 217628 kb
Host smart-5d8b6df7-0850-458b-af01-3d24f47dd710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109471751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1109471751
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3878666554
Short name T15
Test name
Test status
Simulation time 128291067 ps
CPU time 0.94 seconds
Started Jun 09 12:35:36 PM PDT 24
Finished Jun 09 12:35:37 PM PDT 24
Peak memory 200044 kb
Host smart-30f124f3-0694-4f9f-87ca-66258ca5fdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878666554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3878666554
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2549150197
Short name T425
Test name
Test status
Simulation time 1120076831 ps
CPU time 4.94 seconds
Started Jun 09 12:34:05 PM PDT 24
Finished Jun 09 12:34:11 PM PDT 24
Peak memory 200516 kb
Host smart-cddfd5c8-ba26-46ba-8096-9dd055e067b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549150197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2549150197
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3986110155
Short name T286
Test name
Test status
Simulation time 182943113 ps
CPU time 1.16 seconds
Started Jun 09 12:34:04 PM PDT 24
Finished Jun 09 12:34:07 PM PDT 24
Peak memory 200344 kb
Host smart-df09ff65-fb75-4094-969c-fff5248693d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986110155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3986110155
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.1568029741
Short name T358
Test name
Test status
Simulation time 114441893 ps
CPU time 1.2 seconds
Started Jun 09 12:34:04 PM PDT 24
Finished Jun 09 12:34:06 PM PDT 24
Peak memory 200536 kb
Host smart-cdc40882-7d28-4ccf-85af-6e8820a91ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568029741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1568029741
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1314344434
Short name T500
Test name
Test status
Simulation time 4764647090 ps
CPU time 17.64 seconds
Started Jun 09 12:34:08 PM PDT 24
Finished Jun 09 12:34:27 PM PDT 24
Peak memory 208824 kb
Host smart-c951fce3-e3ed-4e57-8cfe-dd4a8d591c2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314344434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1314344434
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3755851650
Short name T220
Test name
Test status
Simulation time 127492129 ps
CPU time 1.52 seconds
Started Jun 09 12:34:15 PM PDT 24
Finished Jun 09 12:34:17 PM PDT 24
Peak memory 200364 kb
Host smart-fac23d99-48e2-4c58-838a-5c633784b488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755851650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3755851650
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3377264297
Short name T235
Test name
Test status
Simulation time 254122994 ps
CPU time 1.4 seconds
Started Jun 09 12:34:03 PM PDT 24
Finished Jun 09 12:34:05 PM PDT 24
Peak memory 200468 kb
Host smart-a3b30251-78cd-4a65-8fbc-2f4b620c1e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377264297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3377264297
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3264595935
Short name T129
Test name
Test status
Simulation time 85025256 ps
CPU time 0.84 seconds
Started Jun 09 12:34:00 PM PDT 24
Finished Jun 09 12:34:01 PM PDT 24
Peak memory 200164 kb
Host smart-8264e36c-4cad-463e-84d4-6a14387eae60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264595935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3264595935
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1044281642
Short name T419
Test name
Test status
Simulation time 1224960452 ps
CPU time 5.52 seconds
Started Jun 09 12:34:11 PM PDT 24
Finished Jun 09 12:34:18 PM PDT 24
Peak memory 217996 kb
Host smart-a5cdfb02-297c-4cf7-a674-880937515c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044281642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1044281642
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3231426473
Short name T541
Test name
Test status
Simulation time 244234694 ps
CPU time 1.02 seconds
Started Jun 09 12:34:14 PM PDT 24
Finished Jun 09 12:34:16 PM PDT 24
Peak memory 217300 kb
Host smart-a0d31d31-33e4-42f5-85c0-f71ec7b23357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231426473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3231426473
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3141307902
Short name T194
Test name
Test status
Simulation time 203196662 ps
CPU time 0.89 seconds
Started Jun 09 12:34:05 PM PDT 24
Finished Jun 09 12:34:08 PM PDT 24
Peak memory 200100 kb
Host smart-9cf64d2e-8b6e-476f-9dda-bdbc26654f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141307902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3141307902
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1179139788
Short name T187
Test name
Test status
Simulation time 1188208802 ps
CPU time 4.72 seconds
Started Jun 09 12:34:02 PM PDT 24
Finished Jun 09 12:34:08 PM PDT 24
Peak memory 200512 kb
Host smart-2c3255fd-b521-4147-9cac-73762abab182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179139788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1179139788
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3110731305
Short name T308
Test name
Test status
Simulation time 109367811 ps
CPU time 0.99 seconds
Started Jun 09 12:34:03 PM PDT 24
Finished Jun 09 12:34:05 PM PDT 24
Peak memory 200348 kb
Host smart-c2f69629-0b55-4c71-b939-af47023bf5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110731305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3110731305
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2566224543
Short name T336
Test name
Test status
Simulation time 239659308 ps
CPU time 1.47 seconds
Started Jun 09 12:34:09 PM PDT 24
Finished Jun 09 12:34:12 PM PDT 24
Peak memory 200532 kb
Host smart-15a9e50b-86fa-4920-bc8a-eab0c58fe1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566224543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2566224543
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.15333341
Short name T405
Test name
Test status
Simulation time 8742644042 ps
CPU time 29.18 seconds
Started Jun 09 12:34:07 PM PDT 24
Finished Jun 09 12:34:38 PM PDT 24
Peak memory 208808 kb
Host smart-bbba68bd-c6a9-4e1c-a522-dd40ce0c114f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15333341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.15333341
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1603954479
Short name T223
Test name
Test status
Simulation time 304906327 ps
CPU time 1.91 seconds
Started Jun 09 12:34:09 PM PDT 24
Finished Jun 09 12:34:13 PM PDT 24
Peak memory 208556 kb
Host smart-3c1ca176-7feb-43b4-953e-1dca3cea8bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603954479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1603954479
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1880793581
Short name T409
Test name
Test status
Simulation time 198689180 ps
CPU time 1.2 seconds
Started Jun 09 12:34:12 PM PDT 24
Finished Jun 09 12:34:14 PM PDT 24
Peak memory 200352 kb
Host smart-a2f3f40e-ec36-4224-b68c-b7f8dfaf21cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880793581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1880793581
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1115009763
Short name T196
Test name
Test status
Simulation time 69157559 ps
CPU time 0.74 seconds
Started Jun 09 12:35:30 PM PDT 24
Finished Jun 09 12:35:31 PM PDT 24
Peak memory 200040 kb
Host smart-2992c93f-1f3f-4c41-b633-6a0364968f80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115009763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1115009763
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1241997328
Short name T406
Test name
Test status
Simulation time 1227658522 ps
CPU time 5 seconds
Started Jun 09 12:34:12 PM PDT 24
Finished Jun 09 12:34:18 PM PDT 24
Peak memory 221532 kb
Host smart-b93da8d9-db36-449d-97b3-e1acd54d8396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241997328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1241997328
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1021226534
Short name T510
Test name
Test status
Simulation time 244788617 ps
CPU time 1.07 seconds
Started Jun 09 12:35:40 PM PDT 24
Finished Jun 09 12:35:42 PM PDT 24
Peak memory 217268 kb
Host smart-81a31abc-c1ba-4bf6-8aa1-64e737a1c31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021226534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1021226534
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1425744082
Short name T299
Test name
Test status
Simulation time 127787834 ps
CPU time 0.81 seconds
Started Jun 09 12:34:01 PM PDT 24
Finished Jun 09 12:34:03 PM PDT 24
Peak memory 200132 kb
Host smart-af2228b7-ea34-403a-a2bb-45b2c2a8d7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425744082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1425744082
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.38710173
Short name T329
Test name
Test status
Simulation time 786153125 ps
CPU time 3.76 seconds
Started Jun 09 12:35:36 PM PDT 24
Finished Jun 09 12:35:40 PM PDT 24
Peak memory 200440 kb
Host smart-bc400257-6402-410d-bf4d-92b4d6db99bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38710173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.38710173
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1223666831
Short name T125
Test name
Test status
Simulation time 108902324 ps
CPU time 0.99 seconds
Started Jun 09 12:34:15 PM PDT 24
Finished Jun 09 12:34:17 PM PDT 24
Peak memory 200348 kb
Host smart-fad25f89-1504-42b9-abad-ae4ecef1f3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223666831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1223666831
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3941497729
Short name T137
Test name
Test status
Simulation time 114155618 ps
CPU time 1.11 seconds
Started Jun 09 12:34:11 PM PDT 24
Finished Jun 09 12:34:14 PM PDT 24
Peak memory 200544 kb
Host smart-ddc2527b-b31d-4ecf-be15-51123fff0481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941497729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3941497729
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.364756205
Short name T465
Test name
Test status
Simulation time 128041728 ps
CPU time 1.64 seconds
Started Jun 09 12:34:16 PM PDT 24
Finished Jun 09 12:34:18 PM PDT 24
Peak memory 200344 kb
Host smart-1f11fff1-a4b8-4856-b219-c9155bca7e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364756205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.364756205
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1696275765
Short name T545
Test name
Test status
Simulation time 206706760 ps
CPU time 1.23 seconds
Started Jun 09 12:34:16 PM PDT 24
Finished Jun 09 12:34:23 PM PDT 24
Peak memory 200348 kb
Host smart-6e5215a8-fc69-4daa-bbac-6a8b19a2da3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696275765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1696275765
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.4080698026
Short name T144
Test name
Test status
Simulation time 61490576 ps
CPU time 0.76 seconds
Started Jun 09 12:34:07 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 200176 kb
Host smart-d27b4ac7-a941-46a6-97c0-b7a8342417a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080698026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.4080698026
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3828458520
Short name T351
Test name
Test status
Simulation time 1226580612 ps
CPU time 5.61 seconds
Started Jun 09 12:34:00 PM PDT 24
Finished Jun 09 12:34:06 PM PDT 24
Peak memory 218048 kb
Host smart-75063468-dc62-414f-830c-eeedfb9a7a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828458520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3828458520
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3160653148
Short name T526
Test name
Test status
Simulation time 245209357 ps
CPU time 1.02 seconds
Started Jun 09 12:34:04 PM PDT 24
Finished Jun 09 12:34:06 PM PDT 24
Peak memory 217600 kb
Host smart-17aef388-a402-4a8a-904c-18560e2e5061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160653148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3160653148
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2848820933
Short name T372
Test name
Test status
Simulation time 155322502 ps
CPU time 0.85 seconds
Started Jun 09 12:35:30 PM PDT 24
Finished Jun 09 12:35:31 PM PDT 24
Peak memory 200040 kb
Host smart-3f99cd62-e037-4361-a7b2-2778668a52c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848820933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2848820933
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1717486187
Short name T393
Test name
Test status
Simulation time 1421135342 ps
CPU time 5.87 seconds
Started Jun 09 12:35:39 PM PDT 24
Finished Jun 09 12:35:45 PM PDT 24
Peak memory 200396 kb
Host smart-c952f3ae-1658-4afe-afa3-84d942cc1bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717486187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1717486187
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3639510842
Short name T320
Test name
Test status
Simulation time 143082846 ps
CPU time 1.07 seconds
Started Jun 09 12:35:40 PM PDT 24
Finished Jun 09 12:35:42 PM PDT 24
Peak memory 200216 kb
Host smart-efd0a78c-ed40-45c2-813e-1185137663b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639510842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3639510842
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2865459538
Short name T170
Test name
Test status
Simulation time 122529414 ps
CPU time 1.14 seconds
Started Jun 09 12:35:30 PM PDT 24
Finished Jun 09 12:35:31 PM PDT 24
Peak memory 200400 kb
Host smart-a36a346f-6c99-49d6-b734-54fd10e58da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865459538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2865459538
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2617842039
Short name T418
Test name
Test status
Simulation time 4812893387 ps
CPU time 15.28 seconds
Started Jun 09 12:34:09 PM PDT 24
Finished Jun 09 12:34:26 PM PDT 24
Peak memory 200628 kb
Host smart-9bf7de16-7e69-47c7-bcab-09228d47e0b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617842039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2617842039
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3507408975
Short name T517
Test name
Test status
Simulation time 149277449 ps
CPU time 1.83 seconds
Started Jun 09 12:34:08 PM PDT 24
Finished Jun 09 12:34:11 PM PDT 24
Peak memory 200364 kb
Host smart-4111b336-729a-41c3-b318-1c1e2cdef4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507408975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3507408975
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1871721444
Short name T349
Test name
Test status
Simulation time 159939706 ps
CPU time 1.05 seconds
Started Jun 09 12:34:17 PM PDT 24
Finished Jun 09 12:34:19 PM PDT 24
Peak memory 200364 kb
Host smart-83235589-9b52-471b-97db-174244887ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871721444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1871721444
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2522003017
Short name T544
Test name
Test status
Simulation time 72033647 ps
CPU time 0.79 seconds
Started Jun 09 12:34:19 PM PDT 24
Finished Jun 09 12:34:25 PM PDT 24
Peak memory 200180 kb
Host smart-5332826f-fdb4-45d9-912d-cad1019df231
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522003017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2522003017
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1403777253
Short name T536
Test name
Test status
Simulation time 2164132621 ps
CPU time 7.8 seconds
Started Jun 09 12:34:14 PM PDT 24
Finished Jun 09 12:34:23 PM PDT 24
Peak memory 222112 kb
Host smart-0d7c5cdb-6b0c-403e-ae9f-2755bd0234af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403777253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1403777253
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1744806038
Short name T364
Test name
Test status
Simulation time 243370300 ps
CPU time 1.14 seconds
Started Jun 09 12:34:09 PM PDT 24
Finished Jun 09 12:34:11 PM PDT 24
Peak memory 217628 kb
Host smart-2424ed4b-68a6-4a97-9ff6-41e5a2058a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744806038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1744806038
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2939744962
Short name T306
Test name
Test status
Simulation time 161398068 ps
CPU time 0.88 seconds
Started Jun 09 12:35:39 PM PDT 24
Finished Jun 09 12:35:40 PM PDT 24
Peak memory 200020 kb
Host smart-7d632dd7-428e-48bd-995f-049fc5d25e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939744962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2939744962
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3040253330
Short name T309
Test name
Test status
Simulation time 1134573936 ps
CPU time 4.6 seconds
Started Jun 09 12:35:31 PM PDT 24
Finished Jun 09 12:35:36 PM PDT 24
Peak memory 200400 kb
Host smart-2d96fc33-177c-45ee-8265-df6d09afa005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040253330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3040253330
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3366730417
Short name T224
Test name
Test status
Simulation time 104155246 ps
CPU time 0.95 seconds
Started Jun 09 12:34:13 PM PDT 24
Finished Jun 09 12:34:15 PM PDT 24
Peak memory 200340 kb
Host smart-4e490c1e-3d29-4ed4-8a67-8b9cf7d54067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366730417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3366730417
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.3224467939
Short name T225
Test name
Test status
Simulation time 246203415 ps
CPU time 1.53 seconds
Started Jun 09 12:35:40 PM PDT 24
Finished Jun 09 12:35:42 PM PDT 24
Peak memory 200156 kb
Host smart-9db538b2-aa02-4f35-a2bc-681164b3a843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224467939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3224467939
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3368720705
Short name T55
Test name
Test status
Simulation time 1191871242 ps
CPU time 6.76 seconds
Started Jun 09 12:34:36 PM PDT 24
Finished Jun 09 12:34:43 PM PDT 24
Peak memory 208760 kb
Host smart-2fe4ccf1-3409-4ce5-9f8f-d0b7fd1f5a2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368720705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3368720705
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1564785706
Short name T501
Test name
Test status
Simulation time 117040305 ps
CPU time 1.48 seconds
Started Jun 09 12:34:17 PM PDT 24
Finished Jun 09 12:34:19 PM PDT 24
Peak memory 200420 kb
Host smart-7584e3d9-c76a-4a2d-bfa1-1a5cf879ab04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564785706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1564785706
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.799556511
Short name T267
Test name
Test status
Simulation time 142443571 ps
CPU time 1.01 seconds
Started Jun 09 12:34:17 PM PDT 24
Finished Jun 09 12:34:18 PM PDT 24
Peak memory 200360 kb
Host smart-33356818-dbff-41fd-adba-6643113b3a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799556511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.799556511
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1413906593
Short name T289
Test name
Test status
Simulation time 60908988 ps
CPU time 0.77 seconds
Started Jun 09 12:34:14 PM PDT 24
Finished Jun 09 12:34:16 PM PDT 24
Peak memory 200180 kb
Host smart-2eeb4349-8589-4fc1-9219-7de21f88b8a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413906593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1413906593
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3317476265
Short name T44
Test name
Test status
Simulation time 1225619662 ps
CPU time 5.85 seconds
Started Jun 09 12:34:04 PM PDT 24
Finished Jun 09 12:34:11 PM PDT 24
Peak memory 217912 kb
Host smart-dfee939d-db42-4e59-89d7-18fed24cb814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317476265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3317476265
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2124122892
Short name T132
Test name
Test status
Simulation time 244565126 ps
CPU time 1.18 seconds
Started Jun 09 12:34:25 PM PDT 24
Finished Jun 09 12:34:27 PM PDT 24
Peak memory 217668 kb
Host smart-503ef19a-221d-4a1e-b5ec-22fbf60b0c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124122892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2124122892
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.129981990
Short name T530
Test name
Test status
Simulation time 230075381 ps
CPU time 0.96 seconds
Started Jun 09 12:35:29 PM PDT 24
Finished Jun 09 12:35:31 PM PDT 24
Peak memory 199996 kb
Host smart-afa2c481-db75-453e-82cd-6fe80c019e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129981990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.129981990
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.401727557
Short name T27
Test name
Test status
Simulation time 1845749412 ps
CPU time 6.26 seconds
Started Jun 09 12:34:01 PM PDT 24
Finished Jun 09 12:34:08 PM PDT 24
Peak memory 200580 kb
Host smart-811745aa-982a-458a-a7c1-40701b707bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401727557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.401727557
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3595608862
Short name T473
Test name
Test status
Simulation time 145950396 ps
CPU time 1.13 seconds
Started Jun 09 12:34:05 PM PDT 24
Finished Jun 09 12:34:07 PM PDT 24
Peak memory 200352 kb
Host smart-aa01a17f-eb6e-4e21-9276-bb01141dfa1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595608862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3595608862
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1165523612
Short name T345
Test name
Test status
Simulation time 121870766 ps
CPU time 1.2 seconds
Started Jun 09 12:34:14 PM PDT 24
Finished Jun 09 12:34:16 PM PDT 24
Peak memory 200336 kb
Host smart-e493edb1-a11b-4dec-849c-9c8658fac9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165523612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1165523612
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.4033169186
Short name T119
Test name
Test status
Simulation time 9966601594 ps
CPU time 30.9 seconds
Started Jun 09 12:35:31 PM PDT 24
Finished Jun 09 12:36:02 PM PDT 24
Peak memory 208736 kb
Host smart-5160f584-4dda-44a1-847d-cc91bd3ab8fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033169186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.4033169186
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1064860933
Short name T212
Test name
Test status
Simulation time 290414602 ps
CPU time 1.92 seconds
Started Jun 09 12:34:17 PM PDT 24
Finished Jun 09 12:34:19 PM PDT 24
Peak memory 208580 kb
Host smart-b4196789-6dba-4e1a-8b42-c77a6d7d067c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064860933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1064860933
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3400482399
Short name T391
Test name
Test status
Simulation time 102832505 ps
CPU time 0.86 seconds
Started Jun 09 12:35:08 PM PDT 24
Finished Jun 09 12:35:15 PM PDT 24
Peak memory 199688 kb
Host smart-6030f8f9-8051-4018-a928-e8fa8dfbfd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400482399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3400482399
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.575735812
Short name T30
Test name
Test status
Simulation time 72113042 ps
CPU time 0.76 seconds
Started Jun 09 12:33:37 PM PDT 24
Finished Jun 09 12:33:38 PM PDT 24
Peak memory 200060 kb
Host smart-fa107cf7-5577-4e0a-a488-dafd8a3ffa1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575735812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.575735812
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.807823634
Short name T479
Test name
Test status
Simulation time 244189522 ps
CPU time 1.14 seconds
Started Jun 09 12:33:20 PM PDT 24
Finished Jun 09 12:33:21 PM PDT 24
Peak memory 217616 kb
Host smart-124e9d7c-b477-48d4-8e4c-bd17fbe3cbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807823634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.807823634
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1326070828
Short name T21
Test name
Test status
Simulation time 122450524 ps
CPU time 0.74 seconds
Started Jun 09 12:33:38 PM PDT 24
Finished Jun 09 12:33:39 PM PDT 24
Peak memory 200096 kb
Host smart-c8de4bc6-2905-4f01-9262-be6a9c193ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326070828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1326070828
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.4283722565
Short name T230
Test name
Test status
Simulation time 898157993 ps
CPU time 4.01 seconds
Started Jun 09 12:33:26 PM PDT 24
Finished Jun 09 12:33:30 PM PDT 24
Peak memory 200472 kb
Host smart-398eb766-f1af-4abd-bbc0-d5b51de847c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283722565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.4283722565
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3697937493
Short name T69
Test name
Test status
Simulation time 8286683950 ps
CPU time 13.55 seconds
Started Jun 09 12:33:55 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 217464 kb
Host smart-dbd666d7-f8bf-443b-b352-cc49d7f7aa2d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697937493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3697937493
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.820868404
Short name T532
Test name
Test status
Simulation time 174871747 ps
CPU time 1.18 seconds
Started Jun 09 12:33:28 PM PDT 24
Finished Jun 09 12:33:29 PM PDT 24
Peak memory 200336 kb
Host smart-8800c289-4b84-417a-82da-9cd0ecf3111e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820868404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.820868404
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2282900239
Short name T451
Test name
Test status
Simulation time 192375274 ps
CPU time 1.35 seconds
Started Jun 09 12:33:21 PM PDT 24
Finished Jun 09 12:33:23 PM PDT 24
Peak memory 200520 kb
Host smart-bacd27f0-dc5f-4701-82fd-52266dce1725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282900239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2282900239
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2164501826
Short name T248
Test name
Test status
Simulation time 8503593514 ps
CPU time 29.18 seconds
Started Jun 09 12:33:39 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 200608 kb
Host smart-e2ff3a36-9c95-4ef8-9440-0841f28892cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164501826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2164501826
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1165535666
Short name T355
Test name
Test status
Simulation time 119374845 ps
CPU time 1.43 seconds
Started Jun 09 12:33:42 PM PDT 24
Finished Jun 09 12:33:44 PM PDT 24
Peak memory 200284 kb
Host smart-005a0d93-e902-4628-8ce8-0f40503911c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165535666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1165535666
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.615339651
Short name T360
Test name
Test status
Simulation time 171817854 ps
CPU time 1.21 seconds
Started Jun 09 12:33:56 PM PDT 24
Finished Jun 09 12:33:57 PM PDT 24
Peak memory 200388 kb
Host smart-69ff7b9f-56ce-41e4-b90d-5c08843cfec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615339651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.615339651
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.4035783752
Short name T177
Test name
Test status
Simulation time 65365889 ps
CPU time 0.75 seconds
Started Jun 09 12:34:05 PM PDT 24
Finished Jun 09 12:34:07 PM PDT 24
Peak memory 200172 kb
Host smart-224303de-ba58-447a-87c6-f7d149756ece
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035783752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.4035783752
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.4079083646
Short name T390
Test name
Test status
Simulation time 244193678 ps
CPU time 1.09 seconds
Started Jun 09 12:34:09 PM PDT 24
Finished Jun 09 12:34:11 PM PDT 24
Peak memory 217796 kb
Host smart-da7fca71-4fbb-462f-8490-dd4596cbfb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079083646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.4079083646
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.16017374
Short name T268
Test name
Test status
Simulation time 212374485 ps
CPU time 0.89 seconds
Started Jun 09 12:34:05 PM PDT 24
Finished Jun 09 12:34:08 PM PDT 24
Peak memory 200156 kb
Host smart-e3235a91-0dcd-4e6a-a2b9-cca9e5a0c109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16017374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.16017374
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3350825702
Short name T276
Test name
Test status
Simulation time 1810762367 ps
CPU time 6.75 seconds
Started Jun 09 12:34:04 PM PDT 24
Finished Jun 09 12:34:12 PM PDT 24
Peak memory 200544 kb
Host smart-61d1de8a-dc27-46a4-b12a-f65de8122dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350825702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3350825702
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3400908950
Short name T350
Test name
Test status
Simulation time 183743464 ps
CPU time 1.29 seconds
Started Jun 09 12:34:34 PM PDT 24
Finished Jun 09 12:34:36 PM PDT 24
Peak memory 200368 kb
Host smart-afc25b90-89c6-49ae-b958-ec41da6e9121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400908950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3400908950
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.4244735969
Short name T269
Test name
Test status
Simulation time 189239148 ps
CPU time 1.24 seconds
Started Jun 09 12:34:09 PM PDT 24
Finished Jun 09 12:34:12 PM PDT 24
Peak memory 200520 kb
Host smart-49160bd6-80d1-45b7-8509-010d2a7ed4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244735969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.4244735969
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.1110185107
Short name T508
Test name
Test status
Simulation time 10208787021 ps
CPU time 37.3 seconds
Started Jun 09 12:34:08 PM PDT 24
Finished Jun 09 12:34:46 PM PDT 24
Peak memory 208880 kb
Host smart-4c717b04-0b99-4018-8abf-1062c3d01b5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110185107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1110185107
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2335448336
Short name T371
Test name
Test status
Simulation time 501249128 ps
CPU time 2.62 seconds
Started Jun 09 12:34:06 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 200364 kb
Host smart-63374e82-20bf-4ade-900e-1237909f4138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335448336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2335448336
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2232242129
Short name T485
Test name
Test status
Simulation time 77068689 ps
CPU time 0.87 seconds
Started Jun 09 12:34:07 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 200312 kb
Host smart-cf678eb5-2191-4bcf-95dd-36ab2075983e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232242129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2232242129
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1932680336
Short name T171
Test name
Test status
Simulation time 67234657 ps
CPU time 0.77 seconds
Started Jun 09 12:34:10 PM PDT 24
Finished Jun 09 12:34:12 PM PDT 24
Peak memory 200112 kb
Host smart-e329cd7b-1ee2-4b97-bb1c-0b653beb16df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932680336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1932680336
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.4260221243
Short name T521
Test name
Test status
Simulation time 2180338287 ps
CPU time 7.51 seconds
Started Jun 09 12:34:09 PM PDT 24
Finished Jun 09 12:34:18 PM PDT 24
Peak memory 222092 kb
Host smart-e807ba3b-22e4-4fe3-ae66-04826639f4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260221243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.4260221243
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3151387908
Short name T29
Test name
Test status
Simulation time 244083392 ps
CPU time 1.11 seconds
Started Jun 09 12:34:02 PM PDT 24
Finished Jun 09 12:34:03 PM PDT 24
Peak memory 217556 kb
Host smart-dd22eee5-3101-48d2-a39e-1402d313e206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151387908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3151387908
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1487142572
Short name T17
Test name
Test status
Simulation time 116527248 ps
CPU time 0.82 seconds
Started Jun 09 12:34:11 PM PDT 24
Finished Jun 09 12:34:18 PM PDT 24
Peak memory 200172 kb
Host smart-139fa160-9632-48d7-9785-98ad71b1f11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487142572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1487142572
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.624596819
Short name T524
Test name
Test status
Simulation time 909045067 ps
CPU time 4.63 seconds
Started Jun 09 12:35:38 PM PDT 24
Finished Jun 09 12:35:43 PM PDT 24
Peak memory 200372 kb
Host smart-e81df162-6224-4358-a38e-7f7c15c8596e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624596819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.624596819
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.730008604
Short name T312
Test name
Test status
Simulation time 147907231 ps
CPU time 1.12 seconds
Started Jun 09 12:34:16 PM PDT 24
Finished Jun 09 12:34:18 PM PDT 24
Peak memory 200376 kb
Host smart-60a0980e-3c7f-456c-9ccd-545f278b319d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730008604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.730008604
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1293563387
Short name T398
Test name
Test status
Simulation time 242497717 ps
CPU time 1.55 seconds
Started Jun 09 12:34:05 PM PDT 24
Finished Jun 09 12:34:08 PM PDT 24
Peak memory 200496 kb
Host smart-368f241c-b728-43af-ba79-4aeac3668668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293563387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1293563387
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3076073315
Short name T520
Test name
Test status
Simulation time 13530763602 ps
CPU time 52.69 seconds
Started Jun 09 12:34:11 PM PDT 24
Finished Jun 09 12:35:06 PM PDT 24
Peak memory 208860 kb
Host smart-d297bad1-fb3f-4a90-a1bb-8aa9fb9b4774
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076073315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3076073315
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1863235669
Short name T495
Test name
Test status
Simulation time 355366617 ps
CPU time 2.28 seconds
Started Jun 09 12:34:03 PM PDT 24
Finished Jun 09 12:34:06 PM PDT 24
Peak memory 200392 kb
Host smart-bc9c5f8e-69ad-45dd-bab9-641b8c50f534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863235669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1863235669
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1429186328
Short name T382
Test name
Test status
Simulation time 142746559 ps
CPU time 1.06 seconds
Started Jun 09 12:34:08 PM PDT 24
Finished Jun 09 12:34:11 PM PDT 24
Peak memory 200288 kb
Host smart-8c358143-5ec5-4d69-8fc6-aba21647b251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429186328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1429186328
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2182556301
Short name T303
Test name
Test status
Simulation time 63499557 ps
CPU time 0.78 seconds
Started Jun 09 12:34:07 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 200124 kb
Host smart-a79be369-0634-401a-8e20-7349ae5f6ccb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182556301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2182556301
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1531661801
Short name T37
Test name
Test status
Simulation time 2189598549 ps
CPU time 7.33 seconds
Started Jun 09 12:34:09 PM PDT 24
Finished Jun 09 12:34:18 PM PDT 24
Peak memory 230284 kb
Host smart-53d24568-3359-40e6-9c19-d077c3458eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531661801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1531661801
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2530271847
Short name T354
Test name
Test status
Simulation time 245274041 ps
CPU time 1.02 seconds
Started Jun 09 12:34:10 PM PDT 24
Finished Jun 09 12:34:13 PM PDT 24
Peak memory 217536 kb
Host smart-787ffa25-86ef-4b6d-913c-9d7d0344d4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530271847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2530271847
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.494724108
Short name T20
Test name
Test status
Simulation time 178702297 ps
CPU time 0.86 seconds
Started Jun 09 12:34:20 PM PDT 24
Finished Jun 09 12:34:27 PM PDT 24
Peak memory 200184 kb
Host smart-9a86f629-1154-4a2d-bd2b-68cf0a3a4e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494724108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.494724108
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3141982504
Short name T493
Test name
Test status
Simulation time 1076909266 ps
CPU time 4.75 seconds
Started Jun 09 12:34:09 PM PDT 24
Finished Jun 09 12:34:16 PM PDT 24
Peak memory 200480 kb
Host smart-d698ff8b-1fae-4621-8fd6-f25ddf69d053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141982504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3141982504
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1545221038
Short name T148
Test name
Test status
Simulation time 111997784 ps
CPU time 1.04 seconds
Started Jun 09 12:34:17 PM PDT 24
Finished Jun 09 12:34:18 PM PDT 24
Peak memory 200360 kb
Host smart-5654438d-f440-418d-a1a9-70c05b380553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545221038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1545221038
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3696179809
Short name T74
Test name
Test status
Simulation time 110990883 ps
CPU time 1.2 seconds
Started Jun 09 12:34:11 PM PDT 24
Finished Jun 09 12:34:14 PM PDT 24
Peak memory 200536 kb
Host smart-61b1ed6a-fb33-4dde-a78b-7ae769f20bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696179809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3696179809
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.3645778809
Short name T202
Test name
Test status
Simulation time 14371386810 ps
CPU time 48.36 seconds
Started Jun 09 12:34:16 PM PDT 24
Finished Jun 09 12:35:09 PM PDT 24
Peak memory 208860 kb
Host smart-32947597-0e1d-4ace-bc9d-1c83d300ef18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645778809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3645778809
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2797060324
Short name T314
Test name
Test status
Simulation time 147023478 ps
CPU time 1.82 seconds
Started Jun 09 12:34:08 PM PDT 24
Finished Jun 09 12:34:12 PM PDT 24
Peak memory 200368 kb
Host smart-07c0d2de-a73d-463d-aa8d-689e480854a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797060324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2797060324
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3390706230
Short name T3
Test name
Test status
Simulation time 208167201 ps
CPU time 1.21 seconds
Started Jun 09 12:34:16 PM PDT 24
Finished Jun 09 12:34:17 PM PDT 24
Peak memory 200348 kb
Host smart-ebd16ea8-2477-4d93-aa18-4c8029415116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390706230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3390706230
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2000943794
Short name T397
Test name
Test status
Simulation time 65071146 ps
CPU time 0.71 seconds
Started Jun 09 12:34:07 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 200148 kb
Host smart-481e0329-5ba9-4bf6-ac6f-eda831edac16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000943794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2000943794
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3739759000
Short name T39
Test name
Test status
Simulation time 1214375730 ps
CPU time 5.58 seconds
Started Jun 09 12:34:10 PM PDT 24
Finished Jun 09 12:34:18 PM PDT 24
Peak memory 217724 kb
Host smart-fd215825-31d4-4de0-8ac4-278c2e82094d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739759000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3739759000
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.851691456
Short name T164
Test name
Test status
Simulation time 245077401 ps
CPU time 1.03 seconds
Started Jun 09 12:34:13 PM PDT 24
Finished Jun 09 12:34:20 PM PDT 24
Peak memory 217616 kb
Host smart-3f9de8a0-01d6-431e-a433-669bd46909c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851691456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.851691456
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2457802417
Short name T22
Test name
Test status
Simulation time 112398370 ps
CPU time 0.74 seconds
Started Jun 09 12:34:14 PM PDT 24
Finished Jun 09 12:34:15 PM PDT 24
Peak memory 200104 kb
Host smart-d716ebd0-4995-44b8-86f0-38ea1538a36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457802417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2457802417
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2389326698
Short name T86
Test name
Test status
Simulation time 1010965125 ps
CPU time 5.02 seconds
Started Jun 09 12:34:07 PM PDT 24
Finished Jun 09 12:34:13 PM PDT 24
Peak memory 200568 kb
Host smart-4d4f2130-4f68-47ed-a003-274133523978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389326698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2389326698
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.881536344
Short name T154
Test name
Test status
Simulation time 146406875 ps
CPU time 1.09 seconds
Started Jun 09 12:34:12 PM PDT 24
Finished Jun 09 12:34:14 PM PDT 24
Peak memory 200376 kb
Host smart-db24394d-1046-484c-8a7a-dfd6f39bb907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881536344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.881536344
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2856618575
Short name T548
Test name
Test status
Simulation time 190284949 ps
CPU time 1.41 seconds
Started Jun 09 12:34:07 PM PDT 24
Finished Jun 09 12:34:15 PM PDT 24
Peak memory 200584 kb
Host smart-f8a21422-7af8-43de-b3c3-c31fe4aa4786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856618575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2856618575
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.592694511
Short name T32
Test name
Test status
Simulation time 677787156 ps
CPU time 2.8 seconds
Started Jun 09 12:34:05 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 200532 kb
Host smart-3d1b69f3-ba66-451a-85c1-540482bfa7a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592694511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.592694511
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.675463095
Short name T539
Test name
Test status
Simulation time 120201455 ps
CPU time 1.5 seconds
Started Jun 09 12:34:02 PM PDT 24
Finished Jun 09 12:34:05 PM PDT 24
Peak memory 200312 kb
Host smart-9df40008-6ae1-448b-8bcc-43d40146d32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675463095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.675463095
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1274102388
Short name T134
Test name
Test status
Simulation time 55499496 ps
CPU time 0.77 seconds
Started Jun 09 12:34:06 PM PDT 24
Finished Jun 09 12:34:08 PM PDT 24
Peak memory 200308 kb
Host smart-d424c879-ed5e-4f4a-8a5f-9a0d6e725e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274102388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1274102388
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3166139754
Short name T347
Test name
Test status
Simulation time 68207232 ps
CPU time 0.84 seconds
Started Jun 09 12:35:08 PM PDT 24
Finished Jun 09 12:35:10 PM PDT 24
Peak memory 199024 kb
Host smart-116edf44-57d1-4531-baf9-275bab205aa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166139754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3166139754
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3000881036
Short name T59
Test name
Test status
Simulation time 1894537515 ps
CPU time 7.61 seconds
Started Jun 09 12:34:10 PM PDT 24
Finished Jun 09 12:34:19 PM PDT 24
Peak memory 217896 kb
Host smart-5627c82a-bf21-4a6e-9946-04bb1a2f7bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000881036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3000881036
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2099171665
Short name T533
Test name
Test status
Simulation time 244571705 ps
CPU time 1.05 seconds
Started Jun 09 12:35:42 PM PDT 24
Finished Jun 09 12:35:43 PM PDT 24
Peak memory 217444 kb
Host smart-e2c180ef-b0b3-4d05-9fa5-d8af81c20cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099171665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2099171665
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3228814542
Short name T468
Test name
Test status
Simulation time 188939452 ps
CPU time 0.85 seconds
Started Jun 09 12:34:23 PM PDT 24
Finished Jun 09 12:34:24 PM PDT 24
Peak memory 200188 kb
Host smart-27ec0186-9a4f-4131-885c-638a09dc2a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228814542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3228814542
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3230992779
Short name T117
Test name
Test status
Simulation time 1286631515 ps
CPU time 5.12 seconds
Started Jun 09 12:34:11 PM PDT 24
Finished Jun 09 12:34:18 PM PDT 24
Peak memory 200556 kb
Host smart-7bdf2887-2db5-4b7b-bc44-9ff51e4f7416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230992779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3230992779
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.311183708
Short name T287
Test name
Test status
Simulation time 96938260 ps
CPU time 0.95 seconds
Started Jun 09 12:34:07 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 200336 kb
Host smart-0203961e-32ae-4f63-97a9-3d3000f995de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311183708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.311183708
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2456452048
Short name T190
Test name
Test status
Simulation time 202028664 ps
CPU time 1.4 seconds
Started Jun 09 12:34:04 PM PDT 24
Finished Jun 09 12:34:07 PM PDT 24
Peak memory 200536 kb
Host smart-0854f63b-52d9-4890-b6da-2a989e8a59c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456452048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2456452048
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1308800495
Short name T447
Test name
Test status
Simulation time 142951593 ps
CPU time 1.77 seconds
Started Jun 09 12:34:11 PM PDT 24
Finished Jun 09 12:34:15 PM PDT 24
Peak memory 200336 kb
Host smart-2d31b9ab-a6bf-446d-ae5f-deb575c749f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308800495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1308800495
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2464293113
Short name T503
Test name
Test status
Simulation time 106539169 ps
CPU time 0.91 seconds
Started Jun 09 12:34:11 PM PDT 24
Finished Jun 09 12:34:14 PM PDT 24
Peak memory 200352 kb
Host smart-777a76af-80c5-4560-8800-2935b705a7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464293113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2464293113
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.4225827646
Short name T189
Test name
Test status
Simulation time 54565163 ps
CPU time 0.79 seconds
Started Jun 09 12:34:03 PM PDT 24
Finished Jun 09 12:34:05 PM PDT 24
Peak memory 200192 kb
Host smart-3f9c5928-7397-469c-b54e-72469de2154e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225827646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.4225827646
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2824178992
Short name T333
Test name
Test status
Simulation time 1892543178 ps
CPU time 6.85 seconds
Started Jun 09 12:34:04 PM PDT 24
Finished Jun 09 12:34:12 PM PDT 24
Peak memory 217512 kb
Host smart-a8ae0a15-395b-40ea-a0f5-740a7c961ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824178992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2824178992
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3181196190
Short name T218
Test name
Test status
Simulation time 244827370 ps
CPU time 1.03 seconds
Started Jun 09 12:34:16 PM PDT 24
Finished Jun 09 12:34:17 PM PDT 24
Peak memory 217600 kb
Host smart-3e54c52f-d526-48dc-b848-64855b89fd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181196190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3181196190
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.4194784637
Short name T271
Test name
Test status
Simulation time 148496133 ps
CPU time 0.78 seconds
Started Jun 09 12:34:07 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 200076 kb
Host smart-51515011-84a2-4a8b-b9b2-9a7dbf1d157f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194784637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.4194784637
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.573977902
Short name T480
Test name
Test status
Simulation time 949245570 ps
CPU time 4.46 seconds
Started Jun 09 12:34:04 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 200496 kb
Host smart-c28c7fbf-ebd8-4a11-b5dd-df5c69728fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573977902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.573977902
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.4116771293
Short name T432
Test name
Test status
Simulation time 107607971 ps
CPU time 0.96 seconds
Started Jun 09 12:35:28 PM PDT 24
Finished Jun 09 12:35:29 PM PDT 24
Peak memory 200192 kb
Host smart-56eca207-bfc5-494f-8956-44182d8d6039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116771293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.4116771293
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.880149522
Short name T471
Test name
Test status
Simulation time 107953727 ps
CPU time 1.1 seconds
Started Jun 09 12:35:37 PM PDT 24
Finished Jun 09 12:35:39 PM PDT 24
Peak memory 200376 kb
Host smart-809599d3-930b-46f8-a887-84d2783ea9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880149522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.880149522
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3586962777
Short name T179
Test name
Test status
Simulation time 11379865935 ps
CPU time 41.53 seconds
Started Jun 09 12:34:05 PM PDT 24
Finished Jun 09 12:34:48 PM PDT 24
Peak memory 208860 kb
Host smart-b583f8e3-6f25-43dc-acb8-fd1b476bfe42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586962777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3586962777
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3155247870
Short name T464
Test name
Test status
Simulation time 347786523 ps
CPU time 2.1 seconds
Started Jun 09 12:34:14 PM PDT 24
Finished Jun 09 12:34:17 PM PDT 24
Peak memory 208540 kb
Host smart-cb2d2530-dd11-4281-ba34-760cee04d5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155247870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3155247870
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2008502053
Short name T163
Test name
Test status
Simulation time 149125183 ps
CPU time 1.09 seconds
Started Jun 09 12:35:40 PM PDT 24
Finished Jun 09 12:35:41 PM PDT 24
Peak memory 200192 kb
Host smart-3ee87da4-7878-416a-a431-afb0a6ea1b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008502053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2008502053
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2805258324
Short name T147
Test name
Test status
Simulation time 78374215 ps
CPU time 0.8 seconds
Started Jun 09 12:34:48 PM PDT 24
Finished Jun 09 12:34:49 PM PDT 24
Peak memory 200136 kb
Host smart-e60ea5d8-f152-4173-b2ef-3fb1e0818bdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805258324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2805258324
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3110843608
Short name T38
Test name
Test status
Simulation time 1887508772 ps
CPU time 6.87 seconds
Started Jun 09 12:34:07 PM PDT 24
Finished Jun 09 12:34:15 PM PDT 24
Peak memory 221004 kb
Host smart-9e4ce40f-564f-461f-9563-a857b3d0d1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110843608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3110843608
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1238822877
Short name T128
Test name
Test status
Simulation time 244483280 ps
CPU time 1 seconds
Started Jun 09 12:34:04 PM PDT 24
Finished Jun 09 12:34:06 PM PDT 24
Peak memory 217560 kb
Host smart-6194135d-1671-4d0c-a517-69eead461704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238822877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1238822877
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.608641306
Short name T16
Test name
Test status
Simulation time 231363449 ps
CPU time 0.93 seconds
Started Jun 09 12:34:00 PM PDT 24
Finished Jun 09 12:34:02 PM PDT 24
Peak memory 200012 kb
Host smart-06e416a2-92dc-438e-b0d8-196dd4a92acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608641306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.608641306
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2048155895
Short name T131
Test name
Test status
Simulation time 1782999854 ps
CPU time 7.1 seconds
Started Jun 09 12:34:27 PM PDT 24
Finished Jun 09 12:34:35 PM PDT 24
Peak memory 200568 kb
Host smart-82f1c1e9-e1d2-45e9-aaec-bc3b24a29f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048155895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2048155895
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.4059104047
Short name T217
Test name
Test status
Simulation time 147731173 ps
CPU time 1.11 seconds
Started Jun 09 12:34:11 PM PDT 24
Finished Jun 09 12:34:14 PM PDT 24
Peak memory 200352 kb
Host smart-1aec3ecb-c73c-4de2-8629-c57b530716ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059104047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.4059104047
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1664790813
Short name T51
Test name
Test status
Simulation time 112034168 ps
CPU time 1.15 seconds
Started Jun 09 12:34:22 PM PDT 24
Finished Jun 09 12:34:24 PM PDT 24
Peak memory 200552 kb
Host smart-2808690c-87c5-4745-bf39-e039777529e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664790813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1664790813
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2477414205
Short name T221
Test name
Test status
Simulation time 3583059420 ps
CPU time 15.53 seconds
Started Jun 09 12:34:17 PM PDT 24
Finished Jun 09 12:34:33 PM PDT 24
Peak memory 200684 kb
Host smart-b585ab26-e00a-4c86-8484-4e7c4771ec27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477414205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2477414205
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3729467221
Short name T335
Test name
Test status
Simulation time 134906364 ps
CPU time 1.6 seconds
Started Jun 09 12:35:37 PM PDT 24
Finished Jun 09 12:35:39 PM PDT 24
Peak memory 208412 kb
Host smart-d7af2f36-376e-459a-8add-2549d26e4f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729467221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3729467221
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.1291444526
Short name T127
Test name
Test status
Simulation time 168499780 ps
CPU time 1.13 seconds
Started Jun 09 12:34:09 PM PDT 24
Finished Jun 09 12:34:12 PM PDT 24
Peak memory 200344 kb
Host smart-cc598768-75d6-42b8-95b9-63c30bd4315e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291444526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1291444526
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3824627011
Short name T416
Test name
Test status
Simulation time 74074023 ps
CPU time 0.76 seconds
Started Jun 09 12:34:14 PM PDT 24
Finished Jun 09 12:34:16 PM PDT 24
Peak memory 200144 kb
Host smart-020ee8e5-8495-43cc-b378-319d871a5ce8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824627011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3824627011
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2371853825
Short name T298
Test name
Test status
Simulation time 2353800584 ps
CPU time 8.64 seconds
Started Jun 09 12:34:09 PM PDT 24
Finished Jun 09 12:34:19 PM PDT 24
Peak memory 222120 kb
Host smart-f86045b3-76b4-49e7-abd3-f1fd95cd464b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371853825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2371853825
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3524032718
Short name T266
Test name
Test status
Simulation time 246368264 ps
CPU time 1.04 seconds
Started Jun 09 12:34:10 PM PDT 24
Finished Jun 09 12:34:13 PM PDT 24
Peak memory 218544 kb
Host smart-51f9c1d6-af1c-4bff-aefa-e216b6655523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524032718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3524032718
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.1322153007
Short name T263
Test name
Test status
Simulation time 118039010 ps
CPU time 0.8 seconds
Started Jun 09 12:34:05 PM PDT 24
Finished Jun 09 12:34:07 PM PDT 24
Peak memory 200164 kb
Host smart-bef01f97-f9ed-4dc1-a66a-b67ded2305ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322153007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1322153007
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.7783618
Short name T433
Test name
Test status
Simulation time 1122583711 ps
CPU time 4.64 seconds
Started Jun 09 12:34:31 PM PDT 24
Finished Jun 09 12:34:36 PM PDT 24
Peak memory 200560 kb
Host smart-cc76cf29-e7ca-4a8f-8513-9cbab3140478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7783618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.7783618
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2137054761
Short name T538
Test name
Test status
Simulation time 158490709 ps
CPU time 1.09 seconds
Started Jun 09 12:34:10 PM PDT 24
Finished Jun 09 12:34:13 PM PDT 24
Peak memory 200324 kb
Host smart-d9b8b23e-809c-49a7-a349-031ed6d9c16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137054761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2137054761
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1825287479
Short name T182
Test name
Test status
Simulation time 209690291 ps
CPU time 1.29 seconds
Started Jun 09 12:34:11 PM PDT 24
Finished Jun 09 12:34:14 PM PDT 24
Peak memory 200476 kb
Host smart-16b63c86-75d6-47a6-af03-aa14910e6841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825287479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1825287479
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1026999762
Short name T438
Test name
Test status
Simulation time 9066260112 ps
CPU time 33.02 seconds
Started Jun 09 12:34:53 PM PDT 24
Finished Jun 09 12:35:27 PM PDT 24
Peak memory 208872 kb
Host smart-5fbe5aa8-82ed-4bca-901f-bc3249fc1ed9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026999762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1026999762
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2005582861
Short name T385
Test name
Test status
Simulation time 138331851 ps
CPU time 1.6 seconds
Started Jun 09 12:34:04 PM PDT 24
Finished Jun 09 12:34:07 PM PDT 24
Peak memory 200368 kb
Host smart-390d7dbb-cf8e-42ce-a858-2e256c7634d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005582861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2005582861
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3835767965
Short name T540
Test name
Test status
Simulation time 251707296 ps
CPU time 1.35 seconds
Started Jun 09 12:34:16 PM PDT 24
Finished Jun 09 12:34:23 PM PDT 24
Peak memory 200520 kb
Host smart-a43d8509-05a1-4286-a911-940ca9b08c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835767965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3835767965
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.253772666
Short name T277
Test name
Test status
Simulation time 59540898 ps
CPU time 0.72 seconds
Started Jun 09 12:34:15 PM PDT 24
Finished Jun 09 12:34:17 PM PDT 24
Peak memory 200168 kb
Host smart-005aaa57-3e89-4866-8461-4d47201d109a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253772666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.253772666
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2324276886
Short name T450
Test name
Test status
Simulation time 1218531765 ps
CPU time 5.83 seconds
Started Jun 09 12:34:09 PM PDT 24
Finished Jun 09 12:34:16 PM PDT 24
Peak memory 217596 kb
Host smart-9fa625af-fbdf-4cea-b499-c01ce967aada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324276886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2324276886
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2773611316
Short name T222
Test name
Test status
Simulation time 244866356 ps
CPU time 1.11 seconds
Started Jun 09 12:34:07 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 217628 kb
Host smart-fb1d93af-2cb6-41d0-98e5-6ac7e74b31df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773611316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2773611316
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3570966871
Short name T281
Test name
Test status
Simulation time 176151547 ps
CPU time 0.91 seconds
Started Jun 09 12:34:18 PM PDT 24
Finished Jun 09 12:34:19 PM PDT 24
Peak memory 200168 kb
Host smart-2b48459e-f614-4fa0-a019-05ed9d70f392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570966871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3570966871
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3506129472
Short name T367
Test name
Test status
Simulation time 1461833804 ps
CPU time 6.03 seconds
Started Jun 09 12:34:36 PM PDT 24
Finished Jun 09 12:34:47 PM PDT 24
Peak memory 200508 kb
Host smart-7a7411b2-e9bb-4319-b3f8-5d077d4a8865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506129472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3506129472
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.912569384
Short name T14
Test name
Test status
Simulation time 109699997 ps
CPU time 1 seconds
Started Jun 09 12:34:33 PM PDT 24
Finished Jun 09 12:34:35 PM PDT 24
Peak memory 200400 kb
Host smart-80020839-07f8-47a7-ad21-97e708c84453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912569384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.912569384
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1719217550
Short name T6
Test name
Test status
Simulation time 115284454 ps
CPU time 1.09 seconds
Started Jun 09 12:34:10 PM PDT 24
Finished Jun 09 12:34:13 PM PDT 24
Peak memory 200460 kb
Host smart-d3dd66eb-c1ea-415f-8edb-a8204f8b51e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719217550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1719217550
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3288810605
Short name T178
Test name
Test status
Simulation time 2671850303 ps
CPU time 11.29 seconds
Started Jun 09 12:34:10 PM PDT 24
Finished Jun 09 12:34:23 PM PDT 24
Peak memory 200672 kb
Host smart-e756ba6c-73cb-4487-8396-39a6065e001c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288810605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3288810605
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2739312994
Short name T492
Test name
Test status
Simulation time 267333722 ps
CPU time 1.88 seconds
Started Jun 09 12:34:06 PM PDT 24
Finished Jun 09 12:34:09 PM PDT 24
Peak memory 200396 kb
Host smart-d3b05e27-741d-40bd-af08-7fc224306960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739312994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2739312994
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3507026926
Short name T547
Test name
Test status
Simulation time 124996719 ps
CPU time 1.12 seconds
Started Jun 09 12:34:09 PM PDT 24
Finished Jun 09 12:34:12 PM PDT 24
Peak memory 200316 kb
Host smart-a6a0b16a-88d8-4913-bb5f-ea4fd4d4cdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507026926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3507026926
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.3273136890
Short name T301
Test name
Test status
Simulation time 75942914 ps
CPU time 0.76 seconds
Started Jun 09 12:34:05 PM PDT 24
Finished Jun 09 12:34:07 PM PDT 24
Peak memory 200132 kb
Host smart-defae493-8af1-4a68-b8e5-5078a7cb63f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273136890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3273136890
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3906239187
Short name T58
Test name
Test status
Simulation time 1905169016 ps
CPU time 8.02 seconds
Started Jun 09 12:34:32 PM PDT 24
Finished Jun 09 12:34:40 PM PDT 24
Peak memory 217592 kb
Host smart-e8316d2e-ca5f-4ddc-b2b1-feaf31f96b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906239187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3906239187
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1732824745
Short name T481
Test name
Test status
Simulation time 244361398 ps
CPU time 1.09 seconds
Started Jun 09 12:34:24 PM PDT 24
Finished Jun 09 12:34:26 PM PDT 24
Peak memory 217612 kb
Host smart-fabc7658-67a6-498b-96f3-6145c14f6d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732824745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1732824745
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.4256077969
Short name T282
Test name
Test status
Simulation time 125496850 ps
CPU time 0.79 seconds
Started Jun 09 12:34:04 PM PDT 24
Finished Jun 09 12:34:06 PM PDT 24
Peak memory 200184 kb
Host smart-79e43ea9-6b79-45fd-8612-9495dea3e17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256077969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.4256077969
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.540164301
Short name T85
Test name
Test status
Simulation time 1768578145 ps
CPU time 6.39 seconds
Started Jun 09 12:34:08 PM PDT 24
Finished Jun 09 12:34:15 PM PDT 24
Peak memory 200584 kb
Host smart-d2669f97-e78f-4eeb-a5b6-eef379f01243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540164301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.540164301
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3711294847
Short name T176
Test name
Test status
Simulation time 164162580 ps
CPU time 1.16 seconds
Started Jun 09 12:34:23 PM PDT 24
Finished Jun 09 12:34:24 PM PDT 24
Peak memory 200348 kb
Host smart-622f4311-2bb0-4d4e-b2ac-48ec9a3e29be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711294847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3711294847
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2688735822
Short name T305
Test name
Test status
Simulation time 200112540 ps
CPU time 1.35 seconds
Started Jun 09 12:34:20 PM PDT 24
Finished Jun 09 12:34:21 PM PDT 24
Peak memory 200580 kb
Host smart-3dae4154-3402-473d-b96a-b866fa74faaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688735822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2688735822
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.989855775
Short name T229
Test name
Test status
Simulation time 4086695275 ps
CPU time 17.89 seconds
Started Jun 09 12:34:17 PM PDT 24
Finished Jun 09 12:34:41 PM PDT 24
Peak memory 200672 kb
Host smart-f6011848-c1cc-4e2a-8ea4-5d0c23f40220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989855775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.989855775
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.1743433658
Short name T395
Test name
Test status
Simulation time 307621153 ps
CPU time 1.88 seconds
Started Jun 09 12:34:10 PM PDT 24
Finished Jun 09 12:34:14 PM PDT 24
Peak memory 200364 kb
Host smart-41e589a0-39d4-4d65-ac76-74e96c50de47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743433658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1743433658
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.591834229
Short name T507
Test name
Test status
Simulation time 150241321 ps
CPU time 1.17 seconds
Started Jun 09 12:34:14 PM PDT 24
Finished Jun 09 12:34:16 PM PDT 24
Peak memory 200324 kb
Host smart-60dd6437-4e84-4fc6-9a27-5d39a2d9ace9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591834229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.591834229
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1499292538
Short name T151
Test name
Test status
Simulation time 56897427 ps
CPU time 0.71 seconds
Started Jun 09 12:33:23 PM PDT 24
Finished Jun 09 12:33:25 PM PDT 24
Peak memory 200168 kb
Host smart-da1bba26-4dea-4097-9705-f0456e394e07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499292538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1499292538
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2218387400
Short name T33
Test name
Test status
Simulation time 1217906799 ps
CPU time 5.49 seconds
Started Jun 09 12:33:43 PM PDT 24
Finished Jun 09 12:33:49 PM PDT 24
Peak memory 217592 kb
Host smart-f70c8e76-ce02-49a7-be8e-1a188136ca71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218387400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2218387400
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.4064053271
Short name T146
Test name
Test status
Simulation time 244442463 ps
CPU time 1.13 seconds
Started Jun 09 12:33:40 PM PDT 24
Finished Jun 09 12:33:42 PM PDT 24
Peak memory 217536 kb
Host smart-0b23df6e-e4e9-4f95-a8f9-b5400f3bedab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064053271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.4064053271
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3611949064
Short name T359
Test name
Test status
Simulation time 152779097 ps
CPU time 0.84 seconds
Started Jun 09 12:33:23 PM PDT 24
Finished Jun 09 12:33:24 PM PDT 24
Peak memory 200136 kb
Host smart-48263a0f-0449-47e8-85a1-92a403a96560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611949064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3611949064
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.764153171
Short name T486
Test name
Test status
Simulation time 1978417927 ps
CPU time 7.47 seconds
Started Jun 09 12:33:34 PM PDT 24
Finished Jun 09 12:33:41 PM PDT 24
Peak memory 200524 kb
Host smart-b2272c93-9294-46a8-8aa1-d072cbeeb393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764153171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.764153171
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.4282232269
Short name T338
Test name
Test status
Simulation time 99199612 ps
CPU time 0.99 seconds
Started Jun 09 12:33:47 PM PDT 24
Finished Jun 09 12:33:48 PM PDT 24
Peak memory 200352 kb
Host smart-42d47564-ceb2-40d2-a229-dca368e2af8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282232269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.4282232269
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2161016180
Short name T226
Test name
Test status
Simulation time 198814696 ps
CPU time 1.34 seconds
Started Jun 09 12:33:59 PM PDT 24
Finished Jun 09 12:34:01 PM PDT 24
Peak memory 200536 kb
Host smart-ddbe4316-3ae4-4f4a-b08b-434b8719d1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161016180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2161016180
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.750800031
Short name T494
Test name
Test status
Simulation time 2298914623 ps
CPU time 9.78 seconds
Started Jun 09 12:33:37 PM PDT 24
Finished Jun 09 12:33:47 PM PDT 24
Peak memory 200636 kb
Host smart-022dbc97-220f-4e6a-acbb-b47b9a8ce7b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750800031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.750800031
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.955189519
Short name T25
Test name
Test status
Simulation time 385497523 ps
CPU time 2.43 seconds
Started Jun 09 12:33:39 PM PDT 24
Finished Jun 09 12:33:42 PM PDT 24
Peak memory 200328 kb
Host smart-d2cd232d-d384-4112-85db-d3b59b5746a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955189519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.955189519
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1196658115
Short name T180
Test name
Test status
Simulation time 167458657 ps
CPU time 1.31 seconds
Started Jun 09 12:33:47 PM PDT 24
Finished Jun 09 12:33:49 PM PDT 24
Peak memory 200548 kb
Host smart-4739ba10-ae0d-495a-a78e-d249e4500f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196658115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1196658115
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2466916304
Short name T523
Test name
Test status
Simulation time 67200559 ps
CPU time 0.78 seconds
Started Jun 09 12:33:38 PM PDT 24
Finished Jun 09 12:33:39 PM PDT 24
Peak memory 200192 kb
Host smart-e42bd556-6272-49ac-8e89-f8591fc3dfe0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466916304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2466916304
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.4270047361
Short name T47
Test name
Test status
Simulation time 1869457788 ps
CPU time 7.61 seconds
Started Jun 09 12:33:35 PM PDT 24
Finished Jun 09 12:33:43 PM PDT 24
Peak memory 217888 kb
Host smart-35a4aa0b-0a3e-4e4d-90e1-4d0c8abdb4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270047361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.4270047361
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1916354391
Short name T387
Test name
Test status
Simulation time 245109514 ps
CPU time 1.1 seconds
Started Jun 09 12:33:18 PM PDT 24
Finished Jun 09 12:33:20 PM PDT 24
Peak memory 217600 kb
Host smart-723295f1-8f3e-4b73-bc46-f7c83336809d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916354391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1916354391
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1720976990
Short name T208
Test name
Test status
Simulation time 227944117 ps
CPU time 0.91 seconds
Started Jun 09 12:33:34 PM PDT 24
Finished Jun 09 12:33:35 PM PDT 24
Peak memory 200128 kb
Host smart-e6ed7685-ba3e-4dd3-a09c-51637e31655b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720976990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1720976990
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.4274119770
Short name T491
Test name
Test status
Simulation time 1490384938 ps
CPU time 6.04 seconds
Started Jun 09 12:33:41 PM PDT 24
Finished Jun 09 12:33:48 PM PDT 24
Peak memory 200576 kb
Host smart-a1bd3076-76da-46ac-a6a1-8730372d5c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274119770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.4274119770
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.347832553
Short name T291
Test name
Test status
Simulation time 104362935 ps
CPU time 1.04 seconds
Started Jun 09 12:33:52 PM PDT 24
Finished Jun 09 12:33:54 PM PDT 24
Peak memory 200316 kb
Host smart-2493f7d4-64e1-432b-abc0-fba829991a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347832553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.347832553
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.4261825025
Short name T445
Test name
Test status
Simulation time 127690950 ps
CPU time 1.17 seconds
Started Jun 09 12:33:27 PM PDT 24
Finished Jun 09 12:33:29 PM PDT 24
Peak memory 200536 kb
Host smart-d6fe251a-68ea-4086-ace0-4dae301d3a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261825025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.4261825025
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1502932937
Short name T237
Test name
Test status
Simulation time 2132887403 ps
CPU time 7.61 seconds
Started Jun 09 12:33:30 PM PDT 24
Finished Jun 09 12:33:38 PM PDT 24
Peak memory 208712 kb
Host smart-7ce82e8c-52a2-4977-8d4e-8cd20de7b415
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502932937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1502932937
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.3684769470
Short name T211
Test name
Test status
Simulation time 135537061 ps
CPU time 1.75 seconds
Started Jun 09 12:33:40 PM PDT 24
Finished Jun 09 12:33:43 PM PDT 24
Peak memory 200324 kb
Host smart-067efdce-cb65-44de-8cb2-e39d5bee6e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684769470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.3684769470
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3949161137
Short name T446
Test name
Test status
Simulation time 263161422 ps
CPU time 1.49 seconds
Started Jun 09 12:33:35 PM PDT 24
Finished Jun 09 12:33:37 PM PDT 24
Peak memory 200316 kb
Host smart-465d67b7-5384-4f1e-abf7-6fbd38057b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949161137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3949161137
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3650161240
Short name T139
Test name
Test status
Simulation time 77615319 ps
CPU time 0.74 seconds
Started Jun 09 12:33:43 PM PDT 24
Finished Jun 09 12:33:44 PM PDT 24
Peak memory 200112 kb
Host smart-7fc072ac-6b0c-425b-8c8d-1a74e4ac7532
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650161240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3650161240
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.298295613
Short name T40
Test name
Test status
Simulation time 1910717331 ps
CPU time 6.99 seconds
Started Jun 09 12:33:57 PM PDT 24
Finished Jun 09 12:34:05 PM PDT 24
Peak memory 218004 kb
Host smart-b49df1e6-a58d-4315-8401-61ded82c82e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298295613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.298295613
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.4009476876
Short name T380
Test name
Test status
Simulation time 267452267 ps
CPU time 1.05 seconds
Started Jun 09 12:33:20 PM PDT 24
Finished Jun 09 12:33:21 PM PDT 24
Peak memory 217528 kb
Host smart-53af6a3a-6537-4d75-bad7-20e503a153e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009476876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.4009476876
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.329226657
Short name T257
Test name
Test status
Simulation time 122707105 ps
CPU time 0.8 seconds
Started Jun 09 12:33:43 PM PDT 24
Finished Jun 09 12:33:44 PM PDT 24
Peak memory 200124 kb
Host smart-9e74451f-cfc5-4d09-8cd2-3940cec6f8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329226657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.329226657
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.828181989
Short name T88
Test name
Test status
Simulation time 1430046375 ps
CPU time 5.66 seconds
Started Jun 09 12:33:45 PM PDT 24
Finished Jun 09 12:33:51 PM PDT 24
Peak memory 200504 kb
Host smart-a166c008-c010-498b-8d85-7a99baece374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828181989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.828181989
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3273157141
Short name T528
Test name
Test status
Simulation time 95396720 ps
CPU time 0.96 seconds
Started Jun 09 12:33:38 PM PDT 24
Finished Jun 09 12:33:40 PM PDT 24
Peak memory 200324 kb
Host smart-12cf481c-7a71-4631-83ad-82793ec2f4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273157141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3273157141
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.1992905365
Short name T186
Test name
Test status
Simulation time 250107291 ps
CPU time 1.5 seconds
Started Jun 09 12:33:19 PM PDT 24
Finished Jun 09 12:33:21 PM PDT 24
Peak memory 200592 kb
Host smart-ad352eb6-5758-4799-af74-0c73b6d316a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992905365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.1992905365
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.684255919
Short name T123
Test name
Test status
Simulation time 8252049486 ps
CPU time 33.49 seconds
Started Jun 09 12:33:27 PM PDT 24
Finished Jun 09 12:34:00 PM PDT 24
Peak memory 209548 kb
Host smart-1ddea93c-b5e1-4f23-b2af-3b30516b6e2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684255919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.684255919
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1406761532
Short name T400
Test name
Test status
Simulation time 454291213 ps
CPU time 2.41 seconds
Started Jun 09 12:33:55 PM PDT 24
Finished Jun 09 12:33:58 PM PDT 24
Peak memory 200288 kb
Host smart-b88ece06-f359-4181-8856-176e1e9e2113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406761532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1406761532
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1833607787
Short name T353
Test name
Test status
Simulation time 255416773 ps
CPU time 1.39 seconds
Started Jun 09 12:33:56 PM PDT 24
Finished Jun 09 12:33:57 PM PDT 24
Peak memory 200548 kb
Host smart-fadd030d-e782-4fc0-bd39-0f4d5c50b9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833607787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1833607787
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.120546070
Short name T470
Test name
Test status
Simulation time 74480073 ps
CPU time 0.75 seconds
Started Jun 09 12:33:44 PM PDT 24
Finished Jun 09 12:33:45 PM PDT 24
Peak memory 200212 kb
Host smart-3bcfff06-2048-44fa-8793-0dedf46f1909
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120546070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.120546070
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2274251695
Short name T57
Test name
Test status
Simulation time 1880079723 ps
CPU time 6.57 seconds
Started Jun 09 12:33:20 PM PDT 24
Finished Jun 09 12:33:27 PM PDT 24
Peak memory 217504 kb
Host smart-6e801d41-2f08-4aaf-a47f-1c6e8c976a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274251695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2274251695
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3614778330
Short name T130
Test name
Test status
Simulation time 244693267 ps
CPU time 1.03 seconds
Started Jun 09 12:33:24 PM PDT 24
Finished Jun 09 12:33:26 PM PDT 24
Peak memory 217524 kb
Host smart-69b74991-709c-4001-acda-aca5d14c1818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614778330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3614778330
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1111564458
Short name T18
Test name
Test status
Simulation time 90106398 ps
CPU time 0.76 seconds
Started Jun 09 12:33:30 PM PDT 24
Finished Jun 09 12:33:31 PM PDT 24
Peak memory 200128 kb
Host smart-29238a03-cb80-42b9-a441-4b5eac8c3702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111564458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1111564458
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2310807889
Short name T373
Test name
Test status
Simulation time 2373797220 ps
CPU time 8.78 seconds
Started Jun 09 12:33:44 PM PDT 24
Finished Jun 09 12:33:53 PM PDT 24
Peak memory 200660 kb
Host smart-d3775c60-dfa2-41d3-b9e2-eba345e1c6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310807889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2310807889
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3843553495
Short name T197
Test name
Test status
Simulation time 160902920 ps
CPU time 1.11 seconds
Started Jun 09 12:33:30 PM PDT 24
Finished Jun 09 12:33:31 PM PDT 24
Peak memory 200240 kb
Host smart-637733d2-2e3d-42b7-8665-d550ba63a6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843553495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3843553495
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.786692220
Short name T362
Test name
Test status
Simulation time 118201488 ps
CPU time 1.18 seconds
Started Jun 09 12:33:38 PM PDT 24
Finished Jun 09 12:33:39 PM PDT 24
Peak memory 200496 kb
Host smart-a899c4d2-00ea-479a-961a-814790aa359a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786692220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.786692220
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.1568128497
Short name T323
Test name
Test status
Simulation time 791626384 ps
CPU time 4.6 seconds
Started Jun 09 12:33:38 PM PDT 24
Finished Jun 09 12:33:43 PM PDT 24
Peak memory 200560 kb
Host smart-2abe1592-d3ec-427f-9ae6-fa62ad1a5523
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568128497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.1568128497
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.1312336055
Short name T150
Test name
Test status
Simulation time 355496659 ps
CPU time 2.12 seconds
Started Jun 09 12:33:40 PM PDT 24
Finished Jun 09 12:33:43 PM PDT 24
Peak memory 208620 kb
Host smart-8075fd14-f44b-4e53-a5f6-67c1d4f6cc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312336055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1312336055
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.46599701
Short name T246
Test name
Test status
Simulation time 101411347 ps
CPU time 0.9 seconds
Started Jun 09 12:33:23 PM PDT 24
Finished Jun 09 12:33:24 PM PDT 24
Peak memory 200332 kb
Host smart-53e95910-bd0c-48f1-abb8-0eb14a10f7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46599701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.46599701
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.138378318
Short name T42
Test name
Test status
Simulation time 59904845 ps
CPU time 0.73 seconds
Started Jun 09 12:33:55 PM PDT 24
Finished Jun 09 12:33:56 PM PDT 24
Peak memory 200020 kb
Host smart-e2a65742-a10f-4dd8-9283-8d5087bc8605
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138378318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.138378318
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.3776680909
Short name T484
Test name
Test status
Simulation time 2178594187 ps
CPU time 8.51 seconds
Started Jun 09 12:33:22 PM PDT 24
Finished Jun 09 12:33:31 PM PDT 24
Peak memory 222004 kb
Host smart-02ab396f-9688-48c0-aeba-6dc6f8d6fd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776680909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3776680909
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.4266422641
Short name T249
Test name
Test status
Simulation time 244773162 ps
CPU time 1.04 seconds
Started Jun 09 12:33:57 PM PDT 24
Finished Jun 09 12:33:59 PM PDT 24
Peak memory 217604 kb
Host smart-0921ab1d-0caf-42ca-b064-abe341e42241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266422641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.4266422641
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1887428650
Short name T172
Test name
Test status
Simulation time 112569693 ps
CPU time 0.83 seconds
Started Jun 09 12:33:51 PM PDT 24
Finished Jun 09 12:33:53 PM PDT 24
Peak memory 200132 kb
Host smart-82f044ac-1da4-4f90-8a70-ccd04e14e1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887428650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1887428650
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.2367842818
Short name T457
Test name
Test status
Simulation time 1831994855 ps
CPU time 7.12 seconds
Started Jun 09 12:33:30 PM PDT 24
Finished Jun 09 12:33:37 PM PDT 24
Peak memory 200504 kb
Host smart-add0f814-be76-44cc-a98f-1cf0fc9940fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367842818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2367842818
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2637657921
Short name T408
Test name
Test status
Simulation time 160023906 ps
CPU time 1.13 seconds
Started Jun 09 12:33:55 PM PDT 24
Finished Jun 09 12:33:57 PM PDT 24
Peak memory 200292 kb
Host smart-68a8dbb1-8872-43b6-92f9-7248f741ad5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637657921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2637657921
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.925331467
Short name T261
Test name
Test status
Simulation time 186401769 ps
CPU time 1.39 seconds
Started Jun 09 12:33:45 PM PDT 24
Finished Jun 09 12:33:47 PM PDT 24
Peak memory 200524 kb
Host smart-1092e6b9-b866-4abd-bcf3-602df987247b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925331467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.925331467
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.374828564
Short name T83
Test name
Test status
Simulation time 9819284197 ps
CPU time 36.28 seconds
Started Jun 09 12:33:55 PM PDT 24
Finished Jun 09 12:34:32 PM PDT 24
Peak memory 200596 kb
Host smart-f0ae70a8-d8db-4155-aabd-7ff0131b68c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374828564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.374828564
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.4188612228
Short name T368
Test name
Test status
Simulation time 438950436 ps
CPU time 2.46 seconds
Started Jun 09 12:33:24 PM PDT 24
Finished Jun 09 12:33:27 PM PDT 24
Peak memory 208556 kb
Host smart-4f1b4459-9880-4617-877a-d8070c2fd10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188612228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.4188612228
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2156527131
Short name T254
Test name
Test status
Simulation time 151864842 ps
CPU time 1.11 seconds
Started Jun 09 12:33:46 PM PDT 24
Finished Jun 09 12:33:47 PM PDT 24
Peak memory 200368 kb
Host smart-3acfb3a7-126a-428b-92e1-6ec48513f69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156527131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2156527131
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%