Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7863

1

T1

120

T5

23

T12

32

auto[1]

10602

1

T1

159

T5

19

T7

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5769	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6207	1			T1	108		T2	1		T3	1
reset_info_cp[2]	2811	1			T1	41		T5	9		T7	1
reset_info_cp[4]	3748	1			T1	60		T5	9		T7	1
reset_info_cp[8]	127	1			T1	1		T21	1		T94	1
reset_info_cp[16]	112	1			T1	2		T21	1		T22	1
reset_info_cp[32]	108	1			T21	1		T94	2		T105	1
reset_info_cp[64]	86	1			T1	1		T44	1		T51	2
reset_info_cp[128]	116	1			T1	1		T21	1		T22	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2960	1			T1	45		T5	6		T12	8
reset_info_cp[1]	auto[1]	2628	1			T1	62		T5	9		T7	1
reset_info_cp[2]	auto[0]	884	1			T1	17		T5	5		T12	5
reset_info_cp[2]	auto[1]	1927	1			T1	24		T5	4		T7	1
reset_info_cp[4]	auto[0]	1383	1			T1	20		T5	5		T12	7
reset_info_cp[4]	auto[1]	2365	1			T1	40		T5	4		T7	1
reset_info_cp[8]	auto[0]	49	1			T54	2		T63	1		T42	2
reset_info_cp[8]	auto[1]	78	1			T1	1		T21	1		T94	1
reset_info_cp[16]	auto[0]	55	1			T1	1		T21	1		T51	2
reset_info_cp[16]	auto[1]	57	1			T1	1		T22	1		T92	1
reset_info_cp[32]	auto[0]	38	1			T21	1		T54	1		T90	1
reset_info_cp[32]	auto[1]	70	1			T94	2		T105	1		T96	1
reset_info_cp[64]	auto[0]	34	1			T51	1		T42	1		T43	1
reset_info_cp[64]	auto[1]	52	1			T1	1		T44	1		T51	1
reset_info_cp[128]	auto[0]	40	1			T1	1		T21	1		T22	2
reset_info_cp[128]	auto[1]	76	1			T94	1		T51	1		T136	1