Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 619
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T540 /workspace/coverage/default/44.rstmgr_reset.3231915232 Jun 10 05:23:43 PM PDT 24 Jun 10 05:23:48 PM PDT 24 886785434 ps
T541 /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.67915401 Jun 10 05:22:22 PM PDT 24 Jun 10 05:22:24 PM PDT 24 182483894 ps
T542 /workspace/coverage/default/29.rstmgr_smoke.2422541287 Jun 10 05:23:16 PM PDT 24 Jun 10 05:23:17 PM PDT 24 256532206 ps
T543 /workspace/coverage/default/32.rstmgr_stress_all.4246028940 Jun 10 05:23:22 PM PDT 24 Jun 10 05:23:59 PM PDT 24 9970194697 ps
T72 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.152691310 Jun 10 04:42:10 PM PDT 24 Jun 10 04:42:11 PM PDT 24 141412027 ps
T73 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2006993913 Jun 10 04:42:12 PM PDT 24 Jun 10 04:42:14 PM PDT 24 192441742 ps
T74 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.293128816 Jun 10 04:42:05 PM PDT 24 Jun 10 04:42:06 PM PDT 24 73241196 ps
T78 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.79244104 Jun 10 04:42:22 PM PDT 24 Jun 10 04:42:26 PM PDT 24 409909400 ps
T79 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1895826192 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:20 PM PDT 24 196415482 ps
T75 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1643346617 Jun 10 04:42:07 PM PDT 24 Jun 10 04:42:17 PM PDT 24 1546877868 ps
T76 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.96884815 Jun 10 04:42:09 PM PDT 24 Jun 10 04:42:11 PM PDT 24 83529005 ps
T544 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.59723000 Jun 10 04:42:07 PM PDT 24 Jun 10 04:42:08 PM PDT 24 74699194 ps
T113 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.794475242 Jun 10 04:42:10 PM PDT 24 Jun 10 04:42:12 PM PDT 24 109872976 ps
T80 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3197115838 Jun 10 04:42:14 PM PDT 24 Jun 10 04:42:17 PM PDT 24 167575091 ps
T114 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2432212362 Jun 10 04:42:15 PM PDT 24 Jun 10 04:42:16 PM PDT 24 58274845 ps
T115 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2046298149 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:19 PM PDT 24 87113391 ps
T139 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3710718880 Jun 10 04:42:04 PM PDT 24 Jun 10 04:42:14 PM PDT 24 2281137750 ps
T81 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3122584938 Jun 10 04:42:03 PM PDT 24 Jun 10 04:42:07 PM PDT 24 879946070 ps
T86 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.645425400 Jun 10 04:42:15 PM PDT 24 Jun 10 04:42:20 PM PDT 24 409449007 ps
T545 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1068408909 Jun 10 04:42:08 PM PDT 24 Jun 10 04:42:09 PM PDT 24 119781043 ps
T97 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.148089008 Jun 10 04:42:09 PM PDT 24 Jun 10 04:42:12 PM PDT 24 784254216 ps
T546 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.105797881 Jun 10 04:42:09 PM PDT 24 Jun 10 04:42:12 PM PDT 24 358950534 ps
T98 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1230540131 Jun 10 04:42:11 PM PDT 24 Jun 10 04:42:14 PM PDT 24 260615226 ps
T99 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1477865777 Jun 10 04:42:04 PM PDT 24 Jun 10 04:42:05 PM PDT 24 133039955 ps
T100 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3683768782 Jun 10 04:42:14 PM PDT 24 Jun 10 04:42:16 PM PDT 24 115371135 ps
T116 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1101643240 Jun 10 04:42:09 PM PDT 24 Jun 10 04:42:11 PM PDT 24 64367830 ps
T101 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1792090698 Jun 10 04:42:15 PM PDT 24 Jun 10 04:42:19 PM PDT 24 92650980 ps
T102 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.4203923567 Jun 10 04:42:15 PM PDT 24 Jun 10 04:42:18 PM PDT 24 170150575 ps
T103 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1781583827 Jun 10 04:42:08 PM PDT 24 Jun 10 04:42:10 PM PDT 24 121663482 ps
T117 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4091753280 Jun 10 04:42:09 PM PDT 24 Jun 10 04:42:11 PM PDT 24 143999083 ps
T130 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.431161869 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:20 PM PDT 24 783249289 ps
T131 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1976509051 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:19 PM PDT 24 512832549 ps
T547 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.238462953 Jun 10 04:42:06 PM PDT 24 Jun 10 04:42:09 PM PDT 24 400040655 ps
T118 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2585022306 Jun 10 04:42:15 PM PDT 24 Jun 10 04:42:18 PM PDT 24 130739909 ps
T119 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2857980443 Jun 10 04:42:25 PM PDT 24 Jun 10 04:42:32 PM PDT 24 206315935 ps
T120 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1233961729 Jun 10 04:42:10 PM PDT 24 Jun 10 04:42:12 PM PDT 24 121040560 ps
T121 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.285798226 Jun 10 04:42:05 PM PDT 24 Jun 10 04:42:07 PM PDT 24 131112778 ps
T548 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.266181032 Jun 10 04:42:09 PM PDT 24 Jun 10 04:42:11 PM PDT 24 359196429 ps
T549 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1049418991 Jun 10 04:42:07 PM PDT 24 Jun 10 04:42:09 PM PDT 24 213947398 ps
T104 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2365919100 Jun 10 04:42:10 PM PDT 24 Jun 10 04:42:14 PM PDT 24 810421048 ps
T550 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1494943552 Jun 10 04:42:13 PM PDT 24 Jun 10 04:42:15 PM PDT 24 83779334 ps
T129 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2752188851 Jun 10 04:42:15 PM PDT 24 Jun 10 04:42:19 PM PDT 24 942946467 ps
T551 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2231838904 Jun 10 04:42:08 PM PDT 24 Jun 10 04:42:14 PM PDT 24 67364472 ps
T122 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.130500928 Jun 10 04:42:15 PM PDT 24 Jun 10 04:42:20 PM PDT 24 508209262 ps
T124 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.768629669 Jun 10 04:42:07 PM PDT 24 Jun 10 04:42:10 PM PDT 24 889168587 ps
T552 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3542122642 Jun 10 04:42:13 PM PDT 24 Jun 10 04:42:15 PM PDT 24 55078233 ps
T553 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2097947961 Jun 10 04:42:26 PM PDT 24 Jun 10 04:42:28 PM PDT 24 121901372 ps
T123 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3113584212 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:20 PM PDT 24 472403329 ps
T554 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2992234720 Jun 10 04:42:10 PM PDT 24 Jun 10 04:42:13 PM PDT 24 423786125 ps
T555 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.383323788 Jun 10 04:42:11 PM PDT 24 Jun 10 04:42:13 PM PDT 24 62454637 ps
T556 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1648390796 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:19 PM PDT 24 93498452 ps
T557 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1657089119 Jun 10 04:42:07 PM PDT 24 Jun 10 04:42:08 PM PDT 24 66165936 ps
T558 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2713297944 Jun 10 04:42:15 PM PDT 24 Jun 10 04:42:17 PM PDT 24 97624002 ps
T559 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.71544575 Jun 10 04:42:11 PM PDT 24 Jun 10 04:42:12 PM PDT 24 134330773 ps
T560 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.583969614 Jun 10 04:42:11 PM PDT 24 Jun 10 04:42:13 PM PDT 24 123733649 ps
T561 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3806996852 Jun 10 04:42:10 PM PDT 24 Jun 10 04:42:12 PM PDT 24 117688940 ps
T562 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2529698119 Jun 10 04:42:11 PM PDT 24 Jun 10 04:42:13 PM PDT 24 128325514 ps
T563 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.292263817 Jun 10 04:42:04 PM PDT 24 Jun 10 04:42:05 PM PDT 24 125649748 ps
T564 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.4213834851 Jun 10 04:42:15 PM PDT 24 Jun 10 04:42:18 PM PDT 24 118205964 ps
T565 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3497717552 Jun 10 04:42:12 PM PDT 24 Jun 10 04:42:14 PM PDT 24 73698808 ps
T566 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2801229014 Jun 10 04:42:10 PM PDT 24 Jun 10 04:42:12 PM PDT 24 73191511 ps
T567 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2669208028 Jun 10 04:42:05 PM PDT 24 Jun 10 04:42:09 PM PDT 24 425914234 ps
T568 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.975833622 Jun 10 04:42:06 PM PDT 24 Jun 10 04:42:08 PM PDT 24 87659472 ps
T569 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3774936834 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:21 PM PDT 24 921197652 ps
T126 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3659299011 Jun 10 04:42:12 PM PDT 24 Jun 10 04:42:14 PM PDT 24 425917302 ps
T570 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2857557876 Jun 10 04:42:08 PM PDT 24 Jun 10 04:42:09 PM PDT 24 199693339 ps
T571 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3026101968 Jun 10 04:42:15 PM PDT 24 Jun 10 04:42:16 PM PDT 24 69082660 ps
T125 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3537584472 Jun 10 04:42:15 PM PDT 24 Jun 10 04:42:19 PM PDT 24 874254491 ps
T572 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1429562457 Jun 10 04:42:14 PM PDT 24 Jun 10 04:42:17 PM PDT 24 274240625 ps
T573 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1843128471 Jun 10 04:42:06 PM PDT 24 Jun 10 04:42:17 PM PDT 24 2283379486 ps
T574 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1642207519 Jun 10 04:42:11 PM PDT 24 Jun 10 04:42:12 PM PDT 24 61945711 ps
T575 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1961153374 Jun 10 04:42:06 PM PDT 24 Jun 10 04:42:08 PM PDT 24 304774360 ps
T576 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3114180261 Jun 10 04:42:05 PM PDT 24 Jun 10 04:42:08 PM PDT 24 430409969 ps
T577 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.420964836 Jun 10 04:42:11 PM PDT 24 Jun 10 04:42:14 PM PDT 24 443288667 ps
T578 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2923587846 Jun 10 04:42:17 PM PDT 24 Jun 10 04:42:20 PM PDT 24 220443600 ps
T127 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3327254701 Jun 10 04:42:23 PM PDT 24 Jun 10 04:42:25 PM PDT 24 514161190 ps
T579 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.595904486 Jun 10 04:42:09 PM PDT 24 Jun 10 04:42:11 PM PDT 24 196073626 ps
T580 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3865261336 Jun 10 04:42:14 PM PDT 24 Jun 10 04:42:16 PM PDT 24 185999160 ps
T581 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1863635805 Jun 10 04:42:11 PM PDT 24 Jun 10 04:42:13 PM PDT 24 98486136 ps
T582 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3152412417 Jun 10 04:42:11 PM PDT 24 Jun 10 04:42:13 PM PDT 24 105117714 ps
T583 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.559043385 Jun 10 04:42:05 PM PDT 24 Jun 10 04:42:09 PM PDT 24 615406421 ps
T584 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1508559453 Jun 10 04:42:10 PM PDT 24 Jun 10 04:42:14 PM PDT 24 445622567 ps
T585 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2506927374 Jun 10 04:42:05 PM PDT 24 Jun 10 04:42:06 PM PDT 24 116279290 ps
T586 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2179897988 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:22 PM PDT 24 895504298 ps
T587 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1608481480 Jun 10 04:42:10 PM PDT 24 Jun 10 04:42:15 PM PDT 24 554243683 ps
T128 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2825624146 Jun 10 04:42:06 PM PDT 24 Jun 10 04:42:10 PM PDT 24 808162329 ps
T588 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1596277989 Jun 10 04:42:04 PM PDT 24 Jun 10 04:42:06 PM PDT 24 499026366 ps
T589 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1762190444 Jun 10 04:42:03 PM PDT 24 Jun 10 04:42:05 PM PDT 24 108540025 ps
T590 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3800133635 Jun 10 04:42:11 PM PDT 24 Jun 10 04:42:13 PM PDT 24 223997049 ps
T591 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2921586253 Jun 10 04:42:03 PM PDT 24 Jun 10 04:42:05 PM PDT 24 211410805 ps
T592 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3021875870 Jun 10 04:42:06 PM PDT 24 Jun 10 04:42:08 PM PDT 24 154322979 ps
T593 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.4076696368 Jun 10 04:42:11 PM PDT 24 Jun 10 04:42:14 PM PDT 24 291365230 ps
T594 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1792752353 Jun 10 04:42:07 PM PDT 24 Jun 10 04:42:12 PM PDT 24 798833434 ps
T595 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2087809695 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:19 PM PDT 24 69860728 ps
T596 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1214882742 Jun 10 04:42:27 PM PDT 24 Jun 10 04:42:28 PM PDT 24 94992596 ps
T132 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.990054707 Jun 10 04:42:03 PM PDT 24 Jun 10 04:42:06 PM PDT 24 410746753 ps
T597 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3360767907 Jun 10 04:42:11 PM PDT 24 Jun 10 04:42:13 PM PDT 24 66114877 ps
T598 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.888445831 Jun 10 04:42:10 PM PDT 24 Jun 10 04:42:14 PM PDT 24 928542464 ps
T599 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.845232304 Jun 10 04:42:05 PM PDT 24 Jun 10 04:42:07 PM PDT 24 100402457 ps
T600 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2817624843 Jun 10 04:42:09 PM PDT 24 Jun 10 04:42:11 PM PDT 24 102271758 ps
T601 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.128105750 Jun 10 04:42:11 PM PDT 24 Jun 10 04:42:13 PM PDT 24 209201488 ps
T602 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3164065188 Jun 10 04:42:11 PM PDT 24 Jun 10 04:42:14 PM PDT 24 154439820 ps
T603 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.253785860 Jun 10 04:42:06 PM PDT 24 Jun 10 04:42:07 PM PDT 24 62443644 ps
T604 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2895083240 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:20 PM PDT 24 432744338 ps
T605 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1233511978 Jun 10 04:42:03 PM PDT 24 Jun 10 04:42:08 PM PDT 24 804212141 ps
T606 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2010870507 Jun 10 04:42:12 PM PDT 24 Jun 10 04:42:15 PM PDT 24 199792280 ps
T607 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.638154581 Jun 10 04:42:14 PM PDT 24 Jun 10 04:42:16 PM PDT 24 84230695 ps
T608 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.872534791 Jun 10 04:42:08 PM PDT 24 Jun 10 04:42:10 PM PDT 24 263358026 ps
T609 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.312739363 Jun 10 04:42:15 PM PDT 24 Jun 10 04:42:16 PM PDT 24 126497901 ps
T610 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2430631253 Jun 10 04:42:03 PM PDT 24 Jun 10 04:42:06 PM PDT 24 430998572 ps
T611 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1120060300 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:19 PM PDT 24 139777354 ps
T612 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.141544655 Jun 10 04:42:07 PM PDT 24 Jun 10 04:42:09 PM PDT 24 198239905 ps
T613 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.332886637 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:19 PM PDT 24 65907070 ps
T614 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1687546592 Jun 10 04:42:04 PM PDT 24 Jun 10 04:42:06 PM PDT 24 255582617 ps
T615 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.501675512 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:19 PM PDT 24 77983198 ps
T616 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1548432531 Jun 10 04:42:05 PM PDT 24 Jun 10 04:42:07 PM PDT 24 101445215 ps
T617 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2942446440 Jun 10 04:42:06 PM PDT 24 Jun 10 04:42:08 PM PDT 24 206074385 ps
T618 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2454902584 Jun 10 04:42:13 PM PDT 24 Jun 10 04:42:16 PM PDT 24 110122376 ps
T619 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2041188774 Jun 10 04:42:03 PM PDT 24 Jun 10 04:42:06 PM PDT 24 200607173 ps

Test location /workspace/coverage/default/6.rstmgr_stress_all.2377197361
Short name T1
Test name
Test status
Simulation time 5192740984 ps
CPU time 24.34 seconds
Started Jun 10 05:22:35 PM PDT 24
Finished Jun 10 05:23:00 PM PDT 24
Peak memory 200640 kb
Host smart-47d4f2be-dfb8-4f0a-9419-a733020dda3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377197361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2377197361
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2366248262
Short name T11
Test name
Test status
Simulation time 447617940 ps
CPU time 2.72 seconds
Started Jun 10 05:22:47 PM PDT 24
Finished Jun 10 05:22:51 PM PDT 24
Peak memory 200352 kb
Host smart-16a9eccf-8fcf-4064-885c-7107e267f023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366248262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2366248262
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.79244104
Short name T78
Test name
Test status
Simulation time 409909400 ps
CPU time 2.9 seconds
Started Jun 10 04:42:22 PM PDT 24
Finished Jun 10 04:42:26 PM PDT 24
Peak memory 212180 kb
Host smart-b02f3b53-68f4-4f7c-a35a-940d02692a6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79244104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.79244104
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.877536996
Short name T38
Test name
Test status
Simulation time 17682258941 ps
CPU time 26.39 seconds
Started Jun 10 05:22:28 PM PDT 24
Finished Jun 10 05:22:55 PM PDT 24
Peak memory 217504 kb
Host smart-9526ca8f-a73d-487e-8ebc-c78e57265077
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877536996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.877536996
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1647782677
Short name T59
Test name
Test status
Simulation time 1902296340 ps
CPU time 6.84 seconds
Started Jun 10 05:22:32 PM PDT 24
Finished Jun 10 05:22:40 PM PDT 24
Peak memory 216928 kb
Host smart-5cc02f93-0993-4bd2-b5db-5c7532b0bd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647782677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1647782677
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3122584938
Short name T81
Test name
Test status
Simulation time 879946070 ps
CPU time 2.86 seconds
Started Jun 10 04:42:03 PM PDT 24
Finished Jun 10 04:42:07 PM PDT 24
Peak memory 200252 kb
Host smart-58be90c4-ecb1-4cc1-ae51-4ab81c6e5cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122584938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3122584938
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2288996466
Short name T84
Test name
Test status
Simulation time 70025339 ps
CPU time 0.78 seconds
Started Jun 10 05:22:25 PM PDT 24
Finished Jun 10 05:22:26 PM PDT 24
Peak memory 200088 kb
Host smart-0072416f-82e4-4e50-8898-b7e33da5a33a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288996466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2288996466
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2753872506
Short name T42
Test name
Test status
Simulation time 1644088255 ps
CPU time 6.39 seconds
Started Jun 10 05:23:03 PM PDT 24
Finished Jun 10 05:23:10 PM PDT 24
Peak memory 200556 kb
Host smart-e69a3bf7-3dfb-4b87-9722-80278801eed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753872506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2753872506
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.293128816
Short name T74
Test name
Test status
Simulation time 73241196 ps
CPU time 0.82 seconds
Started Jun 10 04:42:05 PM PDT 24
Finished Jun 10 04:42:06 PM PDT 24
Peak memory 200140 kb
Host smart-bc0d623c-d10f-47ea-8b0f-f7452fd6b0d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293128816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.293128816
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.555294656
Short name T148
Test name
Test status
Simulation time 98200923 ps
CPU time 1.02 seconds
Started Jun 10 05:22:43 PM PDT 24
Finished Jun 10 05:22:45 PM PDT 24
Peak memory 200280 kb
Host smart-5bd90381-ee15-4741-b736-2dfe2817d2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555294656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.555294656
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.1825229118
Short name T21
Test name
Test status
Simulation time 160821369 ps
CPU time 1.41 seconds
Started Jun 10 05:23:45 PM PDT 24
Finished Jun 10 05:23:46 PM PDT 24
Peak memory 200576 kb
Host smart-465b27dd-fd31-4fb2-8ec1-73bf52936af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825229118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1825229118
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1866662259
Short name T46
Test name
Test status
Simulation time 1236831595 ps
CPU time 6.05 seconds
Started Jun 10 05:22:55 PM PDT 24
Finished Jun 10 05:23:02 PM PDT 24
Peak memory 216968 kb
Host smart-73c1c2b9-ff0f-4c79-9722-82bb544d70db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866662259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1866662259
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.431161869
Short name T130
Test name
Test status
Simulation time 783249289 ps
CPU time 3.05 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:20 PM PDT 24
Peak memory 200376 kb
Host smart-c261f752-900e-4c03-afeb-89977f1ff863
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431161869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.431161869
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.387176086
Short name T17
Test name
Test status
Simulation time 106994734 ps
CPU time 0.83 seconds
Started Jun 10 05:22:48 PM PDT 24
Finished Jun 10 05:22:49 PM PDT 24
Peak memory 200180 kb
Host smart-48510a01-bee8-4958-8527-9d2f5df2a49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387176086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.387176086
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1391640126
Short name T31
Test name
Test status
Simulation time 1237293732 ps
CPU time 6.24 seconds
Started Jun 10 05:23:18 PM PDT 24
Finished Jun 10 05:23:24 PM PDT 24
Peak memory 217948 kb
Host smart-4f7f2f6b-5163-45d9-a31f-2bd5a4bd05fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391640126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1391640126
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.175286718
Short name T222
Test name
Test status
Simulation time 231950222 ps
CPU time 1.49 seconds
Started Jun 10 05:22:19 PM PDT 24
Finished Jun 10 05:22:21 PM PDT 24
Peak memory 200544 kb
Host smart-7fefd7f8-15ca-4ca4-bbf1-fdcbcfb4ad96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175286718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.175286718
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2825624146
Short name T128
Test name
Test status
Simulation time 808162329 ps
CPU time 3.04 seconds
Started Jun 10 04:42:06 PM PDT 24
Finished Jun 10 04:42:10 PM PDT 24
Peak memory 200480 kb
Host smart-e63c2f82-f959-4b16-b992-fc2e409b943d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825624146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2825624146
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2669208028
Short name T567
Test name
Test status
Simulation time 425914234 ps
CPU time 3.69 seconds
Started Jun 10 04:42:05 PM PDT 24
Finished Jun 10 04:42:09 PM PDT 24
Peak memory 208776 kb
Host smart-9964d3ce-a385-4a2f-89ea-6e5bb74fd019
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669208028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2669208028
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.990054707
Short name T132
Test name
Test status
Simulation time 410746753 ps
CPU time 1.71 seconds
Started Jun 10 04:42:03 PM PDT 24
Finished Jun 10 04:42:06 PM PDT 24
Peak memory 200380 kb
Host smart-6d99e194-eb76-4364-b97c-b4beeb80aeb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990054707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.
990054707
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3841592956
Short name T195
Test name
Test status
Simulation time 126697369 ps
CPU time 1.58 seconds
Started Jun 10 05:22:19 PM PDT 24
Finished Jun 10 05:22:21 PM PDT 24
Peak memory 200236 kb
Host smart-ea865fb0-ca96-4bd5-8ff9-3707e7568d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841592956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3841592956
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2942446440
Short name T617
Test name
Test status
Simulation time 206074385 ps
CPU time 1.44 seconds
Started Jun 10 04:42:06 PM PDT 24
Finished Jun 10 04:42:08 PM PDT 24
Peak memory 200432 kb
Host smart-374146a2-bc6a-494a-9908-ecb81a78a324
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942446440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
942446440
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1792752353
Short name T594
Test name
Test status
Simulation time 798833434 ps
CPU time 4.17 seconds
Started Jun 10 04:42:07 PM PDT 24
Finished Jun 10 04:42:12 PM PDT 24
Peak memory 199872 kb
Host smart-422898e6-f8c9-4f9a-84e0-992bd92985c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792752353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
792752353
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.152691310
Short name T72
Test name
Test status
Simulation time 141412027 ps
CPU time 0.94 seconds
Started Jun 10 04:42:10 PM PDT 24
Finished Jun 10 04:42:11 PM PDT 24
Peak memory 200124 kb
Host smart-fc59a897-ceed-498d-a7dc-0480025f15fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152691310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.152691310
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.595904486
Short name T579
Test name
Test status
Simulation time 196073626 ps
CPU time 1.18 seconds
Started Jun 10 04:42:09 PM PDT 24
Finished Jun 10 04:42:11 PM PDT 24
Peak memory 208432 kb
Host smart-ed15526b-6865-4d8b-a781-ce9ee32260d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595904486 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.595904486
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1233961729
Short name T120
Test name
Test status
Simulation time 121040560 ps
CPU time 1.18 seconds
Started Jun 10 04:42:10 PM PDT 24
Finished Jun 10 04:42:12 PM PDT 24
Peak memory 200416 kb
Host smart-5edc8791-2900-4c74-a0f5-df8ff7282988
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233961729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1233961729
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.266181032
Short name T548
Test name
Test status
Simulation time 359196429 ps
CPU time 2.39 seconds
Started Jun 10 04:42:09 PM PDT 24
Finished Jun 10 04:42:11 PM PDT 24
Peak memory 200300 kb
Host smart-df6fffbb-8b76-4c2f-ba55-0b021e1304d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266181032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.266181032
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1233511978
Short name T605
Test name
Test status
Simulation time 804212141 ps
CPU time 5.36 seconds
Started Jun 10 04:42:03 PM PDT 24
Finished Jun 10 04:42:08 PM PDT 24
Peak memory 208584 kb
Host smart-c06816eb-8fd7-473f-a7a9-f37b4e7f15b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233511978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
233511978
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.292263817
Short name T563
Test name
Test status
Simulation time 125649748 ps
CPU time 0.91 seconds
Started Jun 10 04:42:04 PM PDT 24
Finished Jun 10 04:42:05 PM PDT 24
Peak memory 200184 kb
Host smart-5a98b4cc-cb76-4422-8ccb-cc36a7d1722b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292263817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.292263817
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2041188774
Short name T619
Test name
Test status
Simulation time 200607173 ps
CPU time 1.63 seconds
Started Jun 10 04:42:03 PM PDT 24
Finished Jun 10 04:42:06 PM PDT 24
Peak memory 211284 kb
Host smart-f80cf0ed-7804-49ed-bd60-2795ea374616
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041188774 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2041188774
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.975833622
Short name T568
Test name
Test status
Simulation time 87659472 ps
CPU time 0.91 seconds
Started Jun 10 04:42:06 PM PDT 24
Finished Jun 10 04:42:08 PM PDT 24
Peak memory 200240 kb
Host smart-457328c8-df9e-4be9-ac48-b6c1b6cbe30a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975833622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.975833622
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2817624843
Short name T600
Test name
Test status
Simulation time 102271758 ps
CPU time 1.36 seconds
Started Jun 10 04:42:09 PM PDT 24
Finished Jun 10 04:42:11 PM PDT 24
Peak memory 200604 kb
Host smart-0be427a5-70a6-491c-b9bb-c8136ea648b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817624843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2817624843
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.559043385
Short name T583
Test name
Test status
Simulation time 615406421 ps
CPU time 3.64 seconds
Started Jun 10 04:42:05 PM PDT 24
Finished Jun 10 04:42:09 PM PDT 24
Peak memory 208692 kb
Host smart-6a9bb50e-86ca-4003-975b-f34b0c4e0817
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559043385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.559043385
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1596277989
Short name T588
Test name
Test status
Simulation time 499026366 ps
CPU time 2.26 seconds
Started Jun 10 04:42:04 PM PDT 24
Finished Jun 10 04:42:06 PM PDT 24
Peak memory 200416 kb
Host smart-3fe1e35e-f29d-4228-8ca7-1bdfd84c45dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596277989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1596277989
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2010870507
Short name T606
Test name
Test status
Simulation time 199792280 ps
CPU time 1.27 seconds
Started Jun 10 04:42:12 PM PDT 24
Finished Jun 10 04:42:15 PM PDT 24
Peak memory 208472 kb
Host smart-e4d88c9f-3cd3-42cb-917b-c7fe30704dbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010870507 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2010870507
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3360767907
Short name T597
Test name
Test status
Simulation time 66114877 ps
CPU time 0.83 seconds
Started Jun 10 04:42:11 PM PDT 24
Finished Jun 10 04:42:13 PM PDT 24
Peak memory 200156 kb
Host smart-1e5f876d-2900-4b2e-bc42-0f23adde9620
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360767907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3360767907
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1049418991
Short name T549
Test name
Test status
Simulation time 213947398 ps
CPU time 1.5 seconds
Started Jun 10 04:42:07 PM PDT 24
Finished Jun 10 04:42:09 PM PDT 24
Peak memory 200036 kb
Host smart-252e0d97-ca77-4fa3-a17a-6321adcd858e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049418991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1049418991
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1230540131
Short name T98
Test name
Test status
Simulation time 260615226 ps
CPU time 1.82 seconds
Started Jun 10 04:42:11 PM PDT 24
Finished Jun 10 04:42:14 PM PDT 24
Peak memory 211184 kb
Host smart-42af16ec-eeea-45d6-88c7-8cef59d148f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230540131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1230540131
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2992234720
Short name T554
Test name
Test status
Simulation time 423786125 ps
CPU time 1.86 seconds
Started Jun 10 04:42:10 PM PDT 24
Finished Jun 10 04:42:13 PM PDT 24
Peak memory 200484 kb
Host smart-28c47f55-14d8-43ca-89cc-700d5151a61e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992234720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2992234720
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.128105750
Short name T601
Test name
Test status
Simulation time 209201488 ps
CPU time 1.28 seconds
Started Jun 10 04:42:11 PM PDT 24
Finished Jun 10 04:42:13 PM PDT 24
Peak memory 211340 kb
Host smart-0d007a52-66c5-4ca2-89cc-83e2b36e88ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128105750 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.128105750
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2801229014
Short name T566
Test name
Test status
Simulation time 73191511 ps
CPU time 0.83 seconds
Started Jun 10 04:42:10 PM PDT 24
Finished Jun 10 04:42:12 PM PDT 24
Peak memory 200200 kb
Host smart-f747c232-3992-4283-92ef-38e783da1bf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801229014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2801229014
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.794475242
Short name T113
Test name
Test status
Simulation time 109872976 ps
CPU time 0.95 seconds
Started Jun 10 04:42:10 PM PDT 24
Finished Jun 10 04:42:12 PM PDT 24
Peak memory 200216 kb
Host smart-9e339726-4075-4a7e-909b-bf4aebe47119
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794475242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sa
me_csr_outstanding.794475242
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1608481480
Short name T587
Test name
Test status
Simulation time 554243683 ps
CPU time 3.64 seconds
Started Jun 10 04:42:10 PM PDT 24
Finished Jun 10 04:42:15 PM PDT 24
Peak memory 216804 kb
Host smart-9683e752-c1b0-4a81-a7c9-e9f14efac1f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608481480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1608481480
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3659299011
Short name T126
Test name
Test status
Simulation time 425917302 ps
CPU time 1.85 seconds
Started Jun 10 04:42:12 PM PDT 24
Finished Jun 10 04:42:14 PM PDT 24
Peak memory 200428 kb
Host smart-6887fbbd-42ae-4fc4-ae9d-08df91513d54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659299011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.3659299011
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2006993913
Short name T73
Test name
Test status
Simulation time 192441742 ps
CPU time 1.26 seconds
Started Jun 10 04:42:12 PM PDT 24
Finished Jun 10 04:42:14 PM PDT 24
Peak memory 208448 kb
Host smart-cc1ca8df-c743-42ec-9621-4db4b1246b53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006993913 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2006993913
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3026101968
Short name T571
Test name
Test status
Simulation time 69082660 ps
CPU time 0.76 seconds
Started Jun 10 04:42:15 PM PDT 24
Finished Jun 10 04:42:16 PM PDT 24
Peak memory 200088 kb
Host smart-7ef440af-a453-4b55-9ed8-22254eb2c2cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026101968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3026101968
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2713297944
Short name T558
Test name
Test status
Simulation time 97624002 ps
CPU time 1.18 seconds
Started Jun 10 04:42:15 PM PDT 24
Finished Jun 10 04:42:17 PM PDT 24
Peak memory 200400 kb
Host smart-cd787338-562b-4e07-9518-c94000da2d9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713297944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.2713297944
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2895083240
Short name T604
Test name
Test status
Simulation time 432744338 ps
CPU time 2.71 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:20 PM PDT 24
Peak memory 200320 kb
Host smart-464af2cf-4606-48b8-bf04-b71059fdd2f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895083240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2895083240
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2179897988
Short name T586
Test name
Test status
Simulation time 895504298 ps
CPU time 3.09 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:22 PM PDT 24
Peak memory 200444 kb
Host smart-e049d59f-31a5-4011-ae0f-3dff562106f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179897988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.2179897988
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2097947961
Short name T553
Test name
Test status
Simulation time 121901372 ps
CPU time 1.28 seconds
Started Jun 10 04:42:26 PM PDT 24
Finished Jun 10 04:42:28 PM PDT 24
Peak memory 208432 kb
Host smart-db1fb8bf-ef3c-4036-8c06-66ec340d0647
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097947961 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2097947961
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3542122642
Short name T552
Test name
Test status
Simulation time 55078233 ps
CPU time 0.74 seconds
Started Jun 10 04:42:13 PM PDT 24
Finished Jun 10 04:42:15 PM PDT 24
Peak memory 200100 kb
Host smart-a9110180-e240-4872-a100-997ceda5517f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542122642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3542122642
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1494943552
Short name T550
Test name
Test status
Simulation time 83779334 ps
CPU time 0.95 seconds
Started Jun 10 04:42:13 PM PDT 24
Finished Jun 10 04:42:15 PM PDT 24
Peak memory 200168 kb
Host smart-c0f04194-974d-42ea-bc3b-10608d3aec5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494943552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1494943552
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1429562457
Short name T572
Test name
Test status
Simulation time 274240625 ps
CPU time 2.1 seconds
Started Jun 10 04:42:14 PM PDT 24
Finished Jun 10 04:42:17 PM PDT 24
Peak memory 208500 kb
Host smart-ff1b9097-670b-42ac-9d96-ffd3423451ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429562457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1429562457
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1976509051
Short name T131
Test name
Test status
Simulation time 512832549 ps
CPU time 1.93 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 200444 kb
Host smart-a5303d47-71f2-4269-9c17-0a9492131e23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976509051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1976509051
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3683768782
Short name T100
Test name
Test status
Simulation time 115371135 ps
CPU time 0.93 seconds
Started Jun 10 04:42:14 PM PDT 24
Finished Jun 10 04:42:16 PM PDT 24
Peak memory 200160 kb
Host smart-f3b37f2c-8470-4e7f-b870-c995f9e374a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683768782 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3683768782
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1214882742
Short name T596
Test name
Test status
Simulation time 94992596 ps
CPU time 0.87 seconds
Started Jun 10 04:42:27 PM PDT 24
Finished Jun 10 04:42:28 PM PDT 24
Peak memory 200100 kb
Host smart-510e1e14-904b-493a-808e-adbc0dfb2572
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214882742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1214882742
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2585022306
Short name T118
Test name
Test status
Simulation time 130739909 ps
CPU time 1.07 seconds
Started Jun 10 04:42:15 PM PDT 24
Finished Jun 10 04:42:18 PM PDT 24
Peak memory 200208 kb
Host smart-1014b713-3d08-434f-98b5-f589d0e22de9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585022306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2585022306
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3113584212
Short name T123
Test name
Test status
Simulation time 472403329 ps
CPU time 3.2 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:20 PM PDT 24
Peak memory 208548 kb
Host smart-ca15452e-d574-450d-b9b5-b5bc671a3fc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113584212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3113584212
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3774936834
Short name T569
Test name
Test status
Simulation time 921197652 ps
CPU time 3.09 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:21 PM PDT 24
Peak memory 200444 kb
Host smart-d3a5cb5a-188b-4050-8525-825304db6aba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774936834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3774936834
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3865261336
Short name T580
Test name
Test status
Simulation time 185999160 ps
CPU time 1.21 seconds
Started Jun 10 04:42:14 PM PDT 24
Finished Jun 10 04:42:16 PM PDT 24
Peak memory 200264 kb
Host smart-c418dc0f-11bd-46fb-868a-7ce8a292783a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865261336 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3865261336
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1648390796
Short name T556
Test name
Test status
Simulation time 93498452 ps
CPU time 0.89 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 200116 kb
Host smart-3a521bd5-e363-4191-b321-6983e74b00b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648390796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.1648390796
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2857980443
Short name T119
Test name
Test status
Simulation time 206315935 ps
CPU time 1.5 seconds
Started Jun 10 04:42:25 PM PDT 24
Finished Jun 10 04:42:32 PM PDT 24
Peak memory 200324 kb
Host smart-3ce8aa7b-1282-439d-9130-204da80d9ab9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857980443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2857980443
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3197115838
Short name T80
Test name
Test status
Simulation time 167575091 ps
CPU time 2.35 seconds
Started Jun 10 04:42:14 PM PDT 24
Finished Jun 10 04:42:17 PM PDT 24
Peak memory 208688 kb
Host smart-2ac50f63-172d-447e-9f5c-de9198ba7d9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197115838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3197115838
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3327254701
Short name T127
Test name
Test status
Simulation time 514161190 ps
CPU time 1.92 seconds
Started Jun 10 04:42:23 PM PDT 24
Finished Jun 10 04:42:25 PM PDT 24
Peak memory 200496 kb
Host smart-8e7fa558-e02e-4ed8-bc30-51683b8d6ef7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327254701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3327254701
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.4203923567
Short name T102
Test name
Test status
Simulation time 170150575 ps
CPU time 1.72 seconds
Started Jun 10 04:42:15 PM PDT 24
Finished Jun 10 04:42:18 PM PDT 24
Peak memory 212404 kb
Host smart-fb0ab233-79ed-4639-beb4-b0e40c20069d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203923567 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.4203923567
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.332886637
Short name T613
Test name
Test status
Simulation time 65907070 ps
CPU time 0.76 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 200192 kb
Host smart-053e5df8-5044-44f2-84cb-40216a323812
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332886637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.332886637
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2923587846
Short name T578
Test name
Test status
Simulation time 220443600 ps
CPU time 1.52 seconds
Started Jun 10 04:42:17 PM PDT 24
Finished Jun 10 04:42:20 PM PDT 24
Peak memory 200448 kb
Host smart-2a66adc4-c0be-481a-8b43-6cbc8f9a82ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923587846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2923587846
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2454902584
Short name T618
Test name
Test status
Simulation time 110122376 ps
CPU time 1.37 seconds
Started Jun 10 04:42:13 PM PDT 24
Finished Jun 10 04:42:16 PM PDT 24
Peak memory 208596 kb
Host smart-de6a3a25-a237-48d2-9d60-545232002970
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454902584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2454902584
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2752188851
Short name T129
Test name
Test status
Simulation time 942946467 ps
CPU time 3.1 seconds
Started Jun 10 04:42:15 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 200408 kb
Host smart-7b102897-d0a2-490f-a1e1-8aec2fd63efa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752188851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2752188851
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.4213834851
Short name T564
Test name
Test status
Simulation time 118205964 ps
CPU time 1.26 seconds
Started Jun 10 04:42:15 PM PDT 24
Finished Jun 10 04:42:18 PM PDT 24
Peak memory 208504 kb
Host smart-70001cbd-058b-49c0-af85-6d5197f225e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213834851 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.4213834851
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2432212362
Short name T114
Test name
Test status
Simulation time 58274845 ps
CPU time 0.74 seconds
Started Jun 10 04:42:15 PM PDT 24
Finished Jun 10 04:42:16 PM PDT 24
Peak memory 200176 kb
Host smart-8e13a473-1cd3-4deb-affb-cb966c22a24a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432212362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2432212362
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.638154581
Short name T607
Test name
Test status
Simulation time 84230695 ps
CPU time 0.97 seconds
Started Jun 10 04:42:14 PM PDT 24
Finished Jun 10 04:42:16 PM PDT 24
Peak memory 200252 kb
Host smart-1e6a587e-0ce5-48eb-a11e-b56ff899ffc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638154581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.638154581
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.645425400
Short name T86
Test name
Test status
Simulation time 409449007 ps
CPU time 1.83 seconds
Started Jun 10 04:42:15 PM PDT 24
Finished Jun 10 04:42:20 PM PDT 24
Peak memory 199364 kb
Host smart-56dfdf95-e071-4a8c-b4ce-e0402a31edb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645425400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.645425400
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1792090698
Short name T101
Test name
Test status
Simulation time 92650980 ps
CPU time 0.92 seconds
Started Jun 10 04:42:15 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 199064 kb
Host smart-f15d799b-f323-4813-849e-7a00680661ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792090698 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1792090698
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2046298149
Short name T115
Test name
Test status
Simulation time 87113391 ps
CPU time 0.84 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 200156 kb
Host smart-b5b30951-b388-4fce-8090-193d921e65cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046298149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2046298149
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.501675512
Short name T615
Test name
Test status
Simulation time 77983198 ps
CPU time 0.97 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 200172 kb
Host smart-c36e35c3-c8e2-4cd2-b643-ac08432f57c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501675512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.501675512
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.130500928
Short name T122
Test name
Test status
Simulation time 508209262 ps
CPU time 3.36 seconds
Started Jun 10 04:42:15 PM PDT 24
Finished Jun 10 04:42:20 PM PDT 24
Peak memory 208584 kb
Host smart-e5f788c8-c751-44ea-b27b-3e189e86f45d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130500928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.130500928
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3537584472
Short name T125
Test name
Test status
Simulation time 874254491 ps
CPU time 3.26 seconds
Started Jun 10 04:42:15 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 200428 kb
Host smart-9d407e0f-a759-4202-b5bf-95773584d680
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537584472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3537584472
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1120060300
Short name T611
Test name
Test status
Simulation time 139777354 ps
CPU time 1.17 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 208476 kb
Host smart-0b92a302-5fbb-4a63-83e7-28015f0f6af4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120060300 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1120060300
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2087809695
Short name T595
Test name
Test status
Simulation time 69860728 ps
CPU time 0.78 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 199664 kb
Host smart-bb40b714-ba67-4137-a1c2-50f3c19439f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087809695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2087809695
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.312739363
Short name T609
Test name
Test status
Simulation time 126497901 ps
CPU time 1.01 seconds
Started Jun 10 04:42:15 PM PDT 24
Finished Jun 10 04:42:16 PM PDT 24
Peak memory 200192 kb
Host smart-e29eb4ff-014e-4557-a1b0-50361a2a02cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312739363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.312739363
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1895826192
Short name T79
Test name
Test status
Simulation time 196415482 ps
CPU time 1.62 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:20 PM PDT 24
Peak memory 200216 kb
Host smart-5a2eac4c-5d48-46a2-9d7b-212ac830af69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895826192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1895826192
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.238462953
Short name T547
Test name
Test status
Simulation time 400040655 ps
CPU time 2.6 seconds
Started Jun 10 04:42:06 PM PDT 24
Finished Jun 10 04:42:09 PM PDT 24
Peak memory 200424 kb
Host smart-4ab6c542-7e9e-4d92-870e-c026303fc628
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238462953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.238462953
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3710718880
Short name T139
Test name
Test status
Simulation time 2281137750 ps
CPU time 9.7 seconds
Started Jun 10 04:42:04 PM PDT 24
Finished Jun 10 04:42:14 PM PDT 24
Peak memory 200416 kb
Host smart-bc27aef4-3bb7-4b1a-8f7c-9466414edcf4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710718880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
710718880
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1548432531
Short name T616
Test name
Test status
Simulation time 101445215 ps
CPU time 0.84 seconds
Started Jun 10 04:42:05 PM PDT 24
Finished Jun 10 04:42:07 PM PDT 24
Peak memory 200276 kb
Host smart-44658ec3-4962-4647-9e53-f8de2a02ef94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548432531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
548432531
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1477865777
Short name T99
Test name
Test status
Simulation time 133039955 ps
CPU time 1.06 seconds
Started Jun 10 04:42:04 PM PDT 24
Finished Jun 10 04:42:05 PM PDT 24
Peak memory 208396 kb
Host smart-ce939758-fb9c-4f6a-a09d-223f4f2d2199
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477865777 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1477865777
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1101643240
Short name T116
Test name
Test status
Simulation time 64367830 ps
CPU time 0.76 seconds
Started Jun 10 04:42:09 PM PDT 24
Finished Jun 10 04:42:11 PM PDT 24
Peak memory 200124 kb
Host smart-3d06baf1-4deb-46f0-a559-715383320fdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101643240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1101643240
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.845232304
Short name T599
Test name
Test status
Simulation time 100402457 ps
CPU time 1.26 seconds
Started Jun 10 04:42:05 PM PDT 24
Finished Jun 10 04:42:07 PM PDT 24
Peak memory 200460 kb
Host smart-4825a9b1-9c72-4b47-b2bc-9c94f83c0250
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845232304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.845232304
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1961153374
Short name T575
Test name
Test status
Simulation time 304774360 ps
CPU time 2.2 seconds
Started Jun 10 04:42:06 PM PDT 24
Finished Jun 10 04:42:08 PM PDT 24
Peak memory 208736 kb
Host smart-44af5dd3-7b9c-4ded-9dc6-2397094b7df4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961153374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1961153374
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2430631253
Short name T610
Test name
Test status
Simulation time 430998572 ps
CPU time 2.12 seconds
Started Jun 10 04:42:03 PM PDT 24
Finished Jun 10 04:42:06 PM PDT 24
Peak memory 200404 kb
Host smart-dbedccce-7680-4b73-afb9-87debeb226a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430631253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.2430631253
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.105797881
Short name T546
Test name
Test status
Simulation time 358950534 ps
CPU time 2.33 seconds
Started Jun 10 04:42:09 PM PDT 24
Finished Jun 10 04:42:12 PM PDT 24
Peak memory 208468 kb
Host smart-60f2b779-56f3-4a31-ba1e-3b715867980b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105797881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.105797881
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1643346617
Short name T75
Test name
Test status
Simulation time 1546877868 ps
CPU time 8.62 seconds
Started Jun 10 04:42:07 PM PDT 24
Finished Jun 10 04:42:17 PM PDT 24
Peak memory 216944 kb
Host smart-0624858a-618d-4041-8c24-c9d0aead83de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643346617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
643346617
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1068408909
Short name T545
Test name
Test status
Simulation time 119781043 ps
CPU time 1.07 seconds
Started Jun 10 04:42:08 PM PDT 24
Finished Jun 10 04:42:09 PM PDT 24
Peak memory 200428 kb
Host smart-2959ddb0-0b45-4483-bea2-945f2cc4ab65
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068408909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
068408909
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3021875870
Short name T592
Test name
Test status
Simulation time 154322979 ps
CPU time 1.29 seconds
Started Jun 10 04:42:06 PM PDT 24
Finished Jun 10 04:42:08 PM PDT 24
Peak memory 208732 kb
Host smart-e4cfd5a7-a3c2-478c-8402-bedd5604b543
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021875870 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3021875870
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.59723000
Short name T544
Test name
Test status
Simulation time 74699194 ps
CPU time 0.8 seconds
Started Jun 10 04:42:07 PM PDT 24
Finished Jun 10 04:42:08 PM PDT 24
Peak memory 199708 kb
Host smart-adcbf6e8-4a32-4f6e-87c6-a3766c24e1a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59723000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.59723000
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4091753280
Short name T117
Test name
Test status
Simulation time 143999083 ps
CPU time 1.11 seconds
Started Jun 10 04:42:09 PM PDT 24
Finished Jun 10 04:42:11 PM PDT 24
Peak memory 200104 kb
Host smart-38b3cdc6-3364-424b-87fe-65a9f6e2a449
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091753280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.4091753280
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2506927374
Short name T585
Test name
Test status
Simulation time 116279290 ps
CPU time 1.49 seconds
Started Jun 10 04:42:05 PM PDT 24
Finished Jun 10 04:42:06 PM PDT 24
Peak memory 208544 kb
Host smart-1163ef89-5259-4fac-a91d-69a9f648af5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506927374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2506927374
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3114180261
Short name T576
Test name
Test status
Simulation time 430409969 ps
CPU time 2.57 seconds
Started Jun 10 04:42:05 PM PDT 24
Finished Jun 10 04:42:08 PM PDT 24
Peak memory 200388 kb
Host smart-f97f8c44-de0b-40e9-92ed-ec29a044e77a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114180261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
114180261
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1843128471
Short name T573
Test name
Test status
Simulation time 2283379486 ps
CPU time 10 seconds
Started Jun 10 04:42:06 PM PDT 24
Finished Jun 10 04:42:17 PM PDT 24
Peak memory 200564 kb
Host smart-da744ef7-08dc-4dd6-b5d4-7997cb948640
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843128471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
843128471
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1762190444
Short name T589
Test name
Test status
Simulation time 108540025 ps
CPU time 0.96 seconds
Started Jun 10 04:42:03 PM PDT 24
Finished Jun 10 04:42:05 PM PDT 24
Peak memory 200224 kb
Host smart-924d9b1b-d508-4d72-8897-a45a18f1c791
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762190444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
762190444
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2921586253
Short name T591
Test name
Test status
Simulation time 211410805 ps
CPU time 1.44 seconds
Started Jun 10 04:42:03 PM PDT 24
Finished Jun 10 04:42:05 PM PDT 24
Peak memory 208464 kb
Host smart-6f904809-ab5b-4e95-852a-912163612d49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921586253 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2921586253
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.253785860
Short name T603
Test name
Test status
Simulation time 62443644 ps
CPU time 0.79 seconds
Started Jun 10 04:42:06 PM PDT 24
Finished Jun 10 04:42:07 PM PDT 24
Peak memory 200160 kb
Host smart-a3d9058c-096b-4b89-8b67-1bde0f18c9f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253785860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.253785860
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.285798226
Short name T121
Test name
Test status
Simulation time 131112778 ps
CPU time 1.48 seconds
Started Jun 10 04:42:05 PM PDT 24
Finished Jun 10 04:42:07 PM PDT 24
Peak memory 200596 kb
Host smart-7d642ee9-8bcc-4072-b488-27d6e9ea37ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285798226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.285798226
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1687546592
Short name T614
Test name
Test status
Simulation time 255582617 ps
CPU time 2.02 seconds
Started Jun 10 04:42:04 PM PDT 24
Finished Jun 10 04:42:06 PM PDT 24
Peak memory 200340 kb
Host smart-844bee20-e130-4cd5-9094-590e585e890b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687546592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.1687546592
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2529698119
Short name T562
Test name
Test status
Simulation time 128325514 ps
CPU time 1.11 seconds
Started Jun 10 04:42:11 PM PDT 24
Finished Jun 10 04:42:13 PM PDT 24
Peak memory 208464 kb
Host smart-3748904d-68f4-45c4-bc9d-45f496799989
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529698119 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2529698119
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1657089119
Short name T557
Test name
Test status
Simulation time 66165936 ps
CPU time 0.85 seconds
Started Jun 10 04:42:07 PM PDT 24
Finished Jun 10 04:42:08 PM PDT 24
Peak memory 200244 kb
Host smart-9c4e2284-c807-48bd-a1ff-6556283edc00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657089119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1657089119
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.872534791
Short name T608
Test name
Test status
Simulation time 263358026 ps
CPU time 1.6 seconds
Started Jun 10 04:42:08 PM PDT 24
Finished Jun 10 04:42:10 PM PDT 24
Peak memory 200180 kb
Host smart-9e31e88f-3e79-4178-845b-e2f2215b8dd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872534791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sam
e_csr_outstanding.872534791
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3164065188
Short name T602
Test name
Test status
Simulation time 154439820 ps
CPU time 2.07 seconds
Started Jun 10 04:42:11 PM PDT 24
Finished Jun 10 04:42:14 PM PDT 24
Peak memory 216652 kb
Host smart-25c8c6e6-2a03-4caa-92d2-fbf974056c85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164065188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3164065188
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.768629669
Short name T124
Test name
Test status
Simulation time 889168587 ps
CPU time 2.85 seconds
Started Jun 10 04:42:07 PM PDT 24
Finished Jun 10 04:42:10 PM PDT 24
Peak memory 199996 kb
Host smart-1a73f102-baad-4c24-a655-b5bae3d22f5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768629669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.
768629669
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.141544655
Short name T612
Test name
Test status
Simulation time 198239905 ps
CPU time 1.34 seconds
Started Jun 10 04:42:07 PM PDT 24
Finished Jun 10 04:42:09 PM PDT 24
Peak memory 208072 kb
Host smart-6998f200-9607-4647-ae2c-a3f4ada8069f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141544655 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.141544655
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.96884815
Short name T76
Test name
Test status
Simulation time 83529005 ps
CPU time 0.79 seconds
Started Jun 10 04:42:09 PM PDT 24
Finished Jun 10 04:42:11 PM PDT 24
Peak memory 200160 kb
Host smart-58c319a7-285e-4692-af89-ee58d7c6d56b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96884815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.96884815
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.71544575
Short name T559
Test name
Test status
Simulation time 134330773 ps
CPU time 1.27 seconds
Started Jun 10 04:42:11 PM PDT 24
Finished Jun 10 04:42:12 PM PDT 24
Peak memory 200440 kb
Host smart-d0e65eb1-db0a-4ba1-a4c4-05d3c312d7f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71544575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_same
_csr_outstanding.71544575
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1508559453
Short name T584
Test name
Test status
Simulation time 445622567 ps
CPU time 2.98 seconds
Started Jun 10 04:42:10 PM PDT 24
Finished Jun 10 04:42:14 PM PDT 24
Peak memory 216748 kb
Host smart-878644fc-b614-49f8-92cd-f906766e04d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508559453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1508559453
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.420964836
Short name T577
Test name
Test status
Simulation time 443288667 ps
CPU time 1.74 seconds
Started Jun 10 04:42:11 PM PDT 24
Finished Jun 10 04:42:14 PM PDT 24
Peak memory 200452 kb
Host smart-b00d19e4-a018-4ecb-b5eb-5fca6c721788
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420964836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
420964836
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2857557876
Short name T570
Test name
Test status
Simulation time 199693339 ps
CPU time 1.22 seconds
Started Jun 10 04:42:08 PM PDT 24
Finished Jun 10 04:42:09 PM PDT 24
Peak memory 208252 kb
Host smart-382f9156-98d7-4bdb-8724-e2a285e25cde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857557876 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2857557876
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2231838904
Short name T551
Test name
Test status
Simulation time 67364472 ps
CPU time 0.77 seconds
Started Jun 10 04:42:08 PM PDT 24
Finished Jun 10 04:42:14 PM PDT 24
Peak memory 199940 kb
Host smart-46a7ecdd-fb33-4cda-a13a-371b8b03aeeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231838904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2231838904
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.583969614
Short name T560
Test name
Test status
Simulation time 123733649 ps
CPU time 1.09 seconds
Started Jun 10 04:42:11 PM PDT 24
Finished Jun 10 04:42:13 PM PDT 24
Peak memory 200140 kb
Host smart-47165649-58b6-4b74-a740-e9f3a3f94ab1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583969614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sam
e_csr_outstanding.583969614
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3806996852
Short name T561
Test name
Test status
Simulation time 117688940 ps
CPU time 1.57 seconds
Started Jun 10 04:42:10 PM PDT 24
Finished Jun 10 04:42:12 PM PDT 24
Peak memory 210920 kb
Host smart-e5854640-2ad4-48fc-8893-8004d2090ae6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806996852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3806996852
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.148089008
Short name T97
Test name
Test status
Simulation time 784254216 ps
CPU time 2.78 seconds
Started Jun 10 04:42:09 PM PDT 24
Finished Jun 10 04:42:12 PM PDT 24
Peak memory 200404 kb
Host smart-eb97b1d4-493f-4d17-9aa9-1928345ef14f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148089008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
148089008
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3152412417
Short name T582
Test name
Test status
Simulation time 105117714 ps
CPU time 0.92 seconds
Started Jun 10 04:42:11 PM PDT 24
Finished Jun 10 04:42:13 PM PDT 24
Peak memory 200312 kb
Host smart-c54cadf7-5961-489b-b7de-8899c8c26523
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152412417 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3152412417
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.383323788
Short name T555
Test name
Test status
Simulation time 62454637 ps
CPU time 0.81 seconds
Started Jun 10 04:42:11 PM PDT 24
Finished Jun 10 04:42:13 PM PDT 24
Peak memory 200196 kb
Host smart-b7339b84-e45d-4491-9299-54e2efe1efb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383323788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.383323788
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3497717552
Short name T565
Test name
Test status
Simulation time 73698808 ps
CPU time 0.94 seconds
Started Jun 10 04:42:12 PM PDT 24
Finished Jun 10 04:42:14 PM PDT 24
Peak memory 200212 kb
Host smart-9ac22a56-57de-45df-a9e0-0a3677258a1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497717552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3497717552
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1781583827
Short name T103
Test name
Test status
Simulation time 121663482 ps
CPU time 1.47 seconds
Started Jun 10 04:42:08 PM PDT 24
Finished Jun 10 04:42:10 PM PDT 24
Peak memory 216428 kb
Host smart-ca106515-7ba8-415a-9ebf-b019f8e7d452
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781583827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1781583827
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.888445831
Short name T598
Test name
Test status
Simulation time 928542464 ps
CPU time 3.48 seconds
Started Jun 10 04:42:10 PM PDT 24
Finished Jun 10 04:42:14 PM PDT 24
Peak memory 200452 kb
Host smart-19c21f89-4273-4a07-b625-ae0b5b4961d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888445831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
888445831
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3800133635
Short name T590
Test name
Test status
Simulation time 223997049 ps
CPU time 1.5 seconds
Started Jun 10 04:42:11 PM PDT 24
Finished Jun 10 04:42:13 PM PDT 24
Peak memory 208476 kb
Host smart-c68633ec-4d36-451b-ae38-4c75c47d439c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800133635 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3800133635
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1642207519
Short name T574
Test name
Test status
Simulation time 61945711 ps
CPU time 0.81 seconds
Started Jun 10 04:42:11 PM PDT 24
Finished Jun 10 04:42:12 PM PDT 24
Peak memory 200156 kb
Host smart-0f378064-c2c8-4edd-8c92-b41385050cf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642207519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1642207519
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1863635805
Short name T581
Test name
Test status
Simulation time 98486136 ps
CPU time 1.22 seconds
Started Jun 10 04:42:11 PM PDT 24
Finished Jun 10 04:42:13 PM PDT 24
Peak memory 200496 kb
Host smart-661d5203-52a3-4ee8-bc57-db0589ddc7d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863635805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1863635805
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.4076696368
Short name T593
Test name
Test status
Simulation time 291365230 ps
CPU time 2.41 seconds
Started Jun 10 04:42:11 PM PDT 24
Finished Jun 10 04:42:14 PM PDT 24
Peak memory 208580 kb
Host smart-0bb9c4c8-5a21-452a-81be-e5515dcfddad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076696368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.4076696368
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2365919100
Short name T104
Test name
Test status
Simulation time 810421048 ps
CPU time 2.78 seconds
Started Jun 10 04:42:10 PM PDT 24
Finished Jun 10 04:42:14 PM PDT 24
Peak memory 200460 kb
Host smart-a4ed8c65-ee4b-4936-a503-2edaa3083892
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365919100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.2365919100
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3534177423
Short name T150
Test name
Test status
Simulation time 69830778 ps
CPU time 0.85 seconds
Started Jun 10 05:22:23 PM PDT 24
Finished Jun 10 05:22:24 PM PDT 24
Peak memory 200172 kb
Host smart-8165fee5-a64e-4ed7-bd9f-6c757d1dce1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534177423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3534177423
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1238481256
Short name T30
Test name
Test status
Simulation time 1218414130 ps
CPU time 5.54 seconds
Started Jun 10 05:22:24 PM PDT 24
Finished Jun 10 05:22:30 PM PDT 24
Peak memory 217920 kb
Host smart-468710df-48fb-4f53-8c1e-0cadf2808ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238481256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1238481256
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1664118530
Short name T347
Test name
Test status
Simulation time 244780882 ps
CPU time 1.12 seconds
Started Jun 10 05:22:22 PM PDT 24
Finished Jun 10 05:22:23 PM PDT 24
Peak memory 217596 kb
Host smart-52719618-bd82-4a4c-a5bd-57902fe77dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664118530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1664118530
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.2127460017
Short name T469
Test name
Test status
Simulation time 143069103 ps
CPU time 0.83 seconds
Started Jun 10 05:22:20 PM PDT 24
Finished Jun 10 05:22:21 PM PDT 24
Peak memory 200156 kb
Host smart-f92ab2c2-f891-4b92-9099-d6cbf68573c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127460017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2127460017
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1303154351
Short name T428
Test name
Test status
Simulation time 859003282 ps
CPU time 4.43 seconds
Started Jun 10 05:22:18 PM PDT 24
Finished Jun 10 05:22:22 PM PDT 24
Peak memory 200528 kb
Host smart-bedc6934-00e4-4f8c-84fc-f00b36750408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303154351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1303154351
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.3629561150
Short name T88
Test name
Test status
Simulation time 16657957534 ps
CPU time 24.56 seconds
Started Jun 10 05:22:18 PM PDT 24
Finished Jun 10 05:22:43 PM PDT 24
Peak memory 217548 kb
Host smart-da0a1b5a-3d51-49a5-89ab-cf17f9e95108
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629561150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3629561150
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.738579427
Short name T339
Test name
Test status
Simulation time 106746002 ps
CPU time 1.03 seconds
Started Jun 10 05:22:20 PM PDT 24
Finished Jun 10 05:22:21 PM PDT 24
Peak memory 200372 kb
Host smart-5859f234-ccc8-4881-b087-e426207ea196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738579427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.738579427
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1389655049
Short name T539
Test name
Test status
Simulation time 229407223 ps
CPU time 1.56 seconds
Started Jun 10 05:22:21 PM PDT 24
Finished Jun 10 05:22:23 PM PDT 24
Peak memory 200548 kb
Host smart-04c430ac-53e7-4097-a1a3-1db55250cf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389655049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1389655049
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1380339957
Short name T410
Test name
Test status
Simulation time 7414969490 ps
CPU time 35.39 seconds
Started Jun 10 05:22:17 PM PDT 24
Finished Jun 10 05:22:53 PM PDT 24
Peak memory 208844 kb
Host smart-ea01f2db-d1c8-4479-b074-fb14b2a898f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380339957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1380339957
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.4272553461
Short name T290
Test name
Test status
Simulation time 69233761 ps
CPU time 0.77 seconds
Started Jun 10 05:22:23 PM PDT 24
Finished Jun 10 05:22:24 PM PDT 24
Peak memory 200184 kb
Host smart-a9236498-bc6f-4999-aeb7-8c5cedd7d5ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272553461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.4272553461
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1177956106
Short name T68
Test name
Test status
Simulation time 1216537349 ps
CPU time 5.49 seconds
Started Jun 10 05:22:28 PM PDT 24
Finished Jun 10 05:22:35 PM PDT 24
Peak memory 217996 kb
Host smart-d9723223-8e95-4198-897b-9a04d19e2ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177956106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1177956106
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2657138100
Short name T464
Test name
Test status
Simulation time 249154505 ps
CPU time 1.07 seconds
Started Jun 10 05:22:28 PM PDT 24
Finished Jun 10 05:22:30 PM PDT 24
Peak memory 218456 kb
Host smart-16dfe338-3a88-400e-8cb6-3be8c7749b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657138100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2657138100
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.59713730
Short name T61
Test name
Test status
Simulation time 196530047 ps
CPU time 0.88 seconds
Started Jun 10 05:22:25 PM PDT 24
Finished Jun 10 05:22:26 PM PDT 24
Peak memory 200184 kb
Host smart-0b48d4db-e40f-448a-a261-d4425e3d08a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59713730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.59713730
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1157827215
Short name T250
Test name
Test status
Simulation time 853628258 ps
CPU time 4.19 seconds
Started Jun 10 05:22:23 PM PDT 24
Finished Jun 10 05:22:27 PM PDT 24
Peak memory 200536 kb
Host smart-a17a6f86-db9f-45b3-9031-daa3f3c7ed39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157827215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1157827215
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.67915401
Short name T541
Test name
Test status
Simulation time 182483894 ps
CPU time 1.25 seconds
Started Jun 10 05:22:22 PM PDT 24
Finished Jun 10 05:22:24 PM PDT 24
Peak memory 200368 kb
Host smart-9b3e78ef-3a91-4311-9fe7-91ae8c932136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67915401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.67915401
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.3502528869
Short name T181
Test name
Test status
Simulation time 251915021 ps
CPU time 1.46 seconds
Started Jun 10 05:22:20 PM PDT 24
Finished Jun 10 05:22:22 PM PDT 24
Peak memory 200436 kb
Host smart-9d1fa7fe-a457-4fc0-8b1a-8d53f489a219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502528869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3502528869
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2780236100
Short name T210
Test name
Test status
Simulation time 3766565561 ps
CPU time 16.74 seconds
Started Jun 10 05:22:20 PM PDT 24
Finished Jun 10 05:22:37 PM PDT 24
Peak memory 208884 kb
Host smart-b9543115-f5f5-4c47-9a0f-c70ddbd8bb7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780236100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2780236100
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3369278559
Short name T407
Test name
Test status
Simulation time 143997398 ps
CPU time 1.79 seconds
Started Jun 10 05:22:22 PM PDT 24
Finished Jun 10 05:22:24 PM PDT 24
Peak memory 200232 kb
Host smart-0b8493c0-4e58-4dba-8460-f107572a3693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369278559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3369278559
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.33283803
Short name T258
Test name
Test status
Simulation time 158123245 ps
CPU time 1.31 seconds
Started Jun 10 05:22:25 PM PDT 24
Finished Jun 10 05:22:26 PM PDT 24
Peak memory 200500 kb
Host smart-f91b7060-7e59-4f3c-9d4d-857ac2618ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33283803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.33283803
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3676163894
Short name T167
Test name
Test status
Simulation time 66412201 ps
CPU time 0.87 seconds
Started Jun 10 05:22:45 PM PDT 24
Finished Jun 10 05:22:47 PM PDT 24
Peak memory 200152 kb
Host smart-839046ad-9610-4844-9ddf-2052dd3912d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676163894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3676163894
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.448621898
Short name T40
Test name
Test status
Simulation time 1228989576 ps
CPU time 5.43 seconds
Started Jun 10 05:22:45 PM PDT 24
Finished Jun 10 05:22:51 PM PDT 24
Peak memory 217956 kb
Host smart-2484087b-deaf-4f49-817e-2116ba208914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448621898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.448621898
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2874371993
Short name T67
Test name
Test status
Simulation time 244523981 ps
CPU time 1.1 seconds
Started Jun 10 05:22:45 PM PDT 24
Finished Jun 10 05:22:47 PM PDT 24
Peak memory 217620 kb
Host smart-e2da4f93-0b75-4941-8da9-e914e9d7bbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874371993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2874371993
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_reset.1876454173
Short name T315
Test name
Test status
Simulation time 969945614 ps
CPU time 4.6 seconds
Started Jun 10 05:22:45 PM PDT 24
Finished Jun 10 05:22:51 PM PDT 24
Peak memory 200516 kb
Host smart-2f05e05a-e8b4-4193-9e67-9dceb706e227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876454173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.1876454173
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.425400961
Short name T329
Test name
Test status
Simulation time 155285802 ps
CPU time 1.2 seconds
Started Jun 10 05:22:48 PM PDT 24
Finished Jun 10 05:22:50 PM PDT 24
Peak memory 200368 kb
Host smart-53d8f21e-18b5-40c2-b870-ed46b1505f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425400961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.425400961
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.3690839557
Short name T194
Test name
Test status
Simulation time 250158641 ps
CPU time 1.43 seconds
Started Jun 10 05:22:42 PM PDT 24
Finished Jun 10 05:22:44 PM PDT 24
Peak memory 200580 kb
Host smart-7b14bc9b-c48b-4e85-8e35-e31542438576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690839557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3690839557
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2065044828
Short name T63
Test name
Test status
Simulation time 3431055327 ps
CPU time 13.89 seconds
Started Jun 10 05:22:47 PM PDT 24
Finished Jun 10 05:23:01 PM PDT 24
Peak memory 208880 kb
Host smart-0d07d46f-bd0d-40d0-b210-6496763c87aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065044828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2065044828
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3863070315
Short name T257
Test name
Test status
Simulation time 147574587 ps
CPU time 1.88 seconds
Started Jun 10 05:22:46 PM PDT 24
Finished Jun 10 05:22:48 PM PDT 24
Peak memory 200348 kb
Host smart-001904c7-55e5-406f-9cb7-249d461ba222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863070315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3863070315
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.4191495951
Short name T236
Test name
Test status
Simulation time 106738887 ps
CPU time 0.88 seconds
Started Jun 10 05:22:46 PM PDT 24
Finished Jun 10 05:22:48 PM PDT 24
Peak memory 200348 kb
Host smart-5362bf76-2c03-46c5-8f1b-88b909dff656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191495951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.4191495951
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2862005105
Short name T182
Test name
Test status
Simulation time 60938692 ps
CPU time 0.72 seconds
Started Jun 10 05:22:45 PM PDT 24
Finished Jun 10 05:22:47 PM PDT 24
Peak memory 200148 kb
Host smart-d0436ad5-da67-4bdd-861c-5b4629e5fd4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862005105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2862005105
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.161575157
Short name T48
Test name
Test status
Simulation time 1888371498 ps
CPU time 7.64 seconds
Started Jun 10 05:22:47 PM PDT 24
Finished Jun 10 05:22:55 PM PDT 24
Peak memory 230096 kb
Host smart-d4b69180-66ab-4050-9f4e-9a2bceff90a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161575157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.161575157
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.829222486
Short name T287
Test name
Test status
Simulation time 244112407 ps
CPU time 1.09 seconds
Started Jun 10 05:22:45 PM PDT 24
Finished Jun 10 05:22:47 PM PDT 24
Peak memory 217492 kb
Host smart-31b95d3b-30cb-4162-8ec3-83b465c1a6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829222486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.829222486
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.228922362
Short name T333
Test name
Test status
Simulation time 227994427 ps
CPU time 1.1 seconds
Started Jun 10 05:22:42 PM PDT 24
Finished Jun 10 05:22:43 PM PDT 24
Peak memory 200108 kb
Host smart-4a54bc90-3809-4695-8086-4a87ea3a726e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228922362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.228922362
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2475889438
Short name T453
Test name
Test status
Simulation time 955336766 ps
CPU time 5.01 seconds
Started Jun 10 05:22:46 PM PDT 24
Finished Jun 10 05:22:52 PM PDT 24
Peak memory 200516 kb
Host smart-28c79286-9009-4dc0-b26d-7fe5f5ef9aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475889438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2475889438
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2086670996
Short name T435
Test name
Test status
Simulation time 250649652 ps
CPU time 1.53 seconds
Started Jun 10 05:22:42 PM PDT 24
Finished Jun 10 05:22:44 PM PDT 24
Peak memory 200636 kb
Host smart-20e8217d-8ffa-4d78-b1fc-8f23b2e6229d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086670996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2086670996
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.4140521925
Short name T513
Test name
Test status
Simulation time 16167826826 ps
CPU time 59.64 seconds
Started Jun 10 05:22:43 PM PDT 24
Finished Jun 10 05:23:43 PM PDT 24
Peak memory 208920 kb
Host smart-509e604e-8083-438c-a0b2-694f9a0128f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140521925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.4140521925
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.200319984
Short name T444
Test name
Test status
Simulation time 115163764 ps
CPU time 1.56 seconds
Started Jun 10 05:22:45 PM PDT 24
Finished Jun 10 05:22:47 PM PDT 24
Peak memory 200272 kb
Host smart-60d7262e-83cd-4a0c-9cab-5aa217e28ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200319984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.200319984
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3406756873
Short name T318
Test name
Test status
Simulation time 147156713 ps
CPU time 1.12 seconds
Started Jun 10 05:22:44 PM PDT 24
Finished Jun 10 05:22:46 PM PDT 24
Peak memory 200352 kb
Host smart-a594e597-566e-411a-b79a-8ad3ebfc5bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406756873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3406756873
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.360526547
Short name T305
Test name
Test status
Simulation time 82323619 ps
CPU time 0.81 seconds
Started Jun 10 05:22:49 PM PDT 24
Finished Jun 10 05:22:50 PM PDT 24
Peak memory 200216 kb
Host smart-5e85bf8d-2eb8-4e49-a7d3-6997b1876b70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360526547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.360526547
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.1151266105
Short name T246
Test name
Test status
Simulation time 1225001669 ps
CPU time 5.55 seconds
Started Jun 10 05:22:49 PM PDT 24
Finished Jun 10 05:22:55 PM PDT 24
Peak memory 217904 kb
Host smart-c2047aef-6eb1-4917-b133-65a6c07ef0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151266105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1151266105
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1237646310
Short name T225
Test name
Test status
Simulation time 245535838 ps
CPU time 1.02 seconds
Started Jun 10 05:22:49 PM PDT 24
Finished Jun 10 05:22:50 PM PDT 24
Peak memory 217548 kb
Host smart-ab049d96-1146-40ec-b016-41a8ce7fe77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237646310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1237646310
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3071636331
Short name T378
Test name
Test status
Simulation time 143415709 ps
CPU time 0.81 seconds
Started Jun 10 05:22:47 PM PDT 24
Finished Jun 10 05:22:48 PM PDT 24
Peak memory 200160 kb
Host smart-35b2a2b1-ea7b-4d6d-b082-7eb62f30dd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071636331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3071636331
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.51991699
Short name T422
Test name
Test status
Simulation time 2015763580 ps
CPU time 7.26 seconds
Started Jun 10 05:22:51 PM PDT 24
Finished Jun 10 05:22:59 PM PDT 24
Peak memory 200476 kb
Host smart-6963b8c5-96e5-4e68-b86c-76a56256695e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51991699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.51991699
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1908381115
Short name T180
Test name
Test status
Simulation time 153036150 ps
CPU time 1.15 seconds
Started Jun 10 05:22:47 PM PDT 24
Finished Jun 10 05:22:49 PM PDT 24
Peak memory 200372 kb
Host smart-5f2cb491-4f7c-437b-90b4-8746014e044c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908381115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1908381115
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2500526186
Short name T393
Test name
Test status
Simulation time 250200445 ps
CPU time 1.48 seconds
Started Jun 10 05:22:45 PM PDT 24
Finished Jun 10 05:22:47 PM PDT 24
Peak memory 200592 kb
Host smart-1021ec63-e6f4-4b19-b017-c8f446dd4166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500526186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2500526186
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.57455386
Short name T507
Test name
Test status
Simulation time 1559757854 ps
CPU time 7.95 seconds
Started Jun 10 05:22:47 PM PDT 24
Finished Jun 10 05:22:56 PM PDT 24
Peak memory 200664 kb
Host smart-f77e0e55-e41e-4ab0-aa12-8c70a317a1ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57455386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.57455386
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.521192955
Short name T515
Test name
Test status
Simulation time 142367121 ps
CPU time 1.07 seconds
Started Jun 10 05:22:49 PM PDT 24
Finished Jun 10 05:22:51 PM PDT 24
Peak memory 200344 kb
Host smart-4d1b7fc8-2ad1-409d-90d1-4af25f946797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521192955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.521192955
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3314260751
Short name T169
Test name
Test status
Simulation time 78162018 ps
CPU time 0.82 seconds
Started Jun 10 05:22:48 PM PDT 24
Finished Jun 10 05:22:49 PM PDT 24
Peak memory 200164 kb
Host smart-72fd5d48-3061-4b8a-9269-8b3b7807f680
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314260751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3314260751
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.1009741822
Short name T500
Test name
Test status
Simulation time 1899716319 ps
CPU time 7.9 seconds
Started Jun 10 05:22:49 PM PDT 24
Finished Jun 10 05:22:58 PM PDT 24
Peak memory 217976 kb
Host smart-8edfa254-f8bc-4cd2-be39-d9de62dd1447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009741822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1009741822
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2611539226
Short name T307
Test name
Test status
Simulation time 244613812 ps
CPU time 1.13 seconds
Started Jun 10 05:22:49 PM PDT 24
Finished Jun 10 05:22:50 PM PDT 24
Peak memory 217632 kb
Host smart-1276d3fa-6cc7-40fe-aca7-bff1e23d81cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611539226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2611539226
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3703841329
Short name T298
Test name
Test status
Simulation time 91497458 ps
CPU time 0.79 seconds
Started Jun 10 05:22:49 PM PDT 24
Finished Jun 10 05:22:50 PM PDT 24
Peak memory 200180 kb
Host smart-fe13c825-afd4-48b8-950d-e66d671d4c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703841329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3703841329
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2526095570
Short name T133
Test name
Test status
Simulation time 1874845344 ps
CPU time 6.97 seconds
Started Jun 10 05:22:52 PM PDT 24
Finished Jun 10 05:22:59 PM PDT 24
Peak memory 200536 kb
Host smart-1c242fd8-7fd2-452e-8e54-926a40da8e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526095570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2526095570
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3638899109
Short name T23
Test name
Test status
Simulation time 169906985 ps
CPU time 1.25 seconds
Started Jun 10 05:22:48 PM PDT 24
Finished Jun 10 05:22:50 PM PDT 24
Peak memory 200284 kb
Host smart-8a7669a3-4499-4fda-9cbd-1602cdf1f218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638899109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3638899109
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.762890921
Short name T39
Test name
Test status
Simulation time 116568469 ps
CPU time 1.14 seconds
Started Jun 10 05:22:53 PM PDT 24
Finished Jun 10 05:22:55 PM PDT 24
Peak memory 200516 kb
Host smart-b5bbf862-6664-4145-8ced-f7339a2c06e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762890921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.762890921
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3768848197
Short name T311
Test name
Test status
Simulation time 3308594778 ps
CPU time 15.16 seconds
Started Jun 10 05:22:51 PM PDT 24
Finished Jun 10 05:23:06 PM PDT 24
Peak memory 216984 kb
Host smart-8691d77b-9e07-4c73-a1e4-dcf7a58911fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768848197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3768848197
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.55790807
Short name T431
Test name
Test status
Simulation time 141703773 ps
CPU time 1.82 seconds
Started Jun 10 05:22:48 PM PDT 24
Finished Jun 10 05:22:50 PM PDT 24
Peak memory 200356 kb
Host smart-d93de9d7-e689-47dd-946f-f3e47134a69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55790807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.55790807
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1535471946
Short name T417
Test name
Test status
Simulation time 217940529 ps
CPU time 1.3 seconds
Started Jun 10 05:22:49 PM PDT 24
Finished Jun 10 05:22:51 PM PDT 24
Peak memory 200348 kb
Host smart-ac4db70e-afee-4469-ad11-49c4f89b47d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535471946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1535471946
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.46278349
Short name T353
Test name
Test status
Simulation time 71824977 ps
CPU time 0.82 seconds
Started Jun 10 05:22:52 PM PDT 24
Finished Jun 10 05:22:53 PM PDT 24
Peak memory 200104 kb
Host smart-bf767963-4763-4bc0-8dd7-42714377b67b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46278349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.46278349
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2566032974
Short name T481
Test name
Test status
Simulation time 1898592583 ps
CPU time 6.76 seconds
Started Jun 10 05:22:52 PM PDT 24
Finished Jun 10 05:22:59 PM PDT 24
Peak memory 217384 kb
Host smart-75c35820-eac3-4e43-96c0-38581515bece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566032974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2566032974
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1766819117
Short name T208
Test name
Test status
Simulation time 244207628 ps
CPU time 1.13 seconds
Started Jun 10 05:22:56 PM PDT 24
Finished Jun 10 05:22:58 PM PDT 24
Peak memory 217520 kb
Host smart-a323a963-7def-4418-9974-137d174583ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766819117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.1766819117
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2826176929
Short name T261
Test name
Test status
Simulation time 95190784 ps
CPU time 0.77 seconds
Started Jun 10 05:22:50 PM PDT 24
Finished Jun 10 05:22:52 PM PDT 24
Peak memory 200176 kb
Host smart-e6e8dfc9-67d4-490c-9aab-b1d710c745b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826176929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2826176929
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.975621817
Short name T535
Test name
Test status
Simulation time 1734205123 ps
CPU time 6.11 seconds
Started Jun 10 05:22:50 PM PDT 24
Finished Jun 10 05:22:57 PM PDT 24
Peak memory 200536 kb
Host smart-bf3bee3d-d6b6-4d66-9812-e9152cf636a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975621817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.975621817
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3380154573
Short name T149
Test name
Test status
Simulation time 102737279 ps
CPU time 1.01 seconds
Started Jun 10 05:22:54 PM PDT 24
Finished Jun 10 05:22:55 PM PDT 24
Peak memory 200340 kb
Host smart-aba68581-7693-4f5f-a608-4d33b07a9e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380154573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3380154573
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.1848731169
Short name T354
Test name
Test status
Simulation time 120611619 ps
CPU time 1.12 seconds
Started Jun 10 05:22:50 PM PDT 24
Finished Jun 10 05:22:52 PM PDT 24
Peak memory 200540 kb
Host smart-137ff5ec-c615-4707-85f9-24da8ed5064c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848731169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.1848731169
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.4267086629
Short name T268
Test name
Test status
Simulation time 4817653373 ps
CPU time 17.46 seconds
Started Jun 10 05:22:52 PM PDT 24
Finished Jun 10 05:23:09 PM PDT 24
Peak memory 200692 kb
Host smart-600ae0a5-77a9-4589-a76d-15161fdef2ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267086629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.4267086629
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3154023048
Short name T384
Test name
Test status
Simulation time 482581611 ps
CPU time 2.69 seconds
Started Jun 10 05:22:52 PM PDT 24
Finished Jun 10 05:22:55 PM PDT 24
Peak memory 200312 kb
Host smart-eab923c4-6801-4e8d-a254-741396016b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154023048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3154023048
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1430648201
Short name T43
Test name
Test status
Simulation time 99236364 ps
CPU time 0.96 seconds
Started Jun 10 05:22:52 PM PDT 24
Finished Jun 10 05:22:54 PM PDT 24
Peak memory 200352 kb
Host smart-7d3e0681-2ddf-40ec-bd25-8bf21c220b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430648201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1430648201
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2777755871
Short name T203
Test name
Test status
Simulation time 76950722 ps
CPU time 0.84 seconds
Started Jun 10 05:22:52 PM PDT 24
Finished Jun 10 05:22:53 PM PDT 24
Peak memory 200068 kb
Host smart-8f23294a-65f9-44c3-8e17-a7d9f9f5e764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777755871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2777755871
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1501227036
Short name T229
Test name
Test status
Simulation time 244407118 ps
CPU time 1.07 seconds
Started Jun 10 05:22:52 PM PDT 24
Finished Jun 10 05:22:53 PM PDT 24
Peak memory 217500 kb
Host smart-f95364f2-d892-4fee-ada1-69d76f7c768a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501227036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1501227036
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2106005109
Short name T9
Test name
Test status
Simulation time 218031280 ps
CPU time 0.9 seconds
Started Jun 10 05:22:52 PM PDT 24
Finished Jun 10 05:22:53 PM PDT 24
Peak memory 200160 kb
Host smart-18334235-8aeb-4ba5-a9c9-d17887d0967f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106005109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2106005109
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1773211132
Short name T432
Test name
Test status
Simulation time 2033714078 ps
CPU time 7.17 seconds
Started Jun 10 05:22:55 PM PDT 24
Finished Jun 10 05:23:03 PM PDT 24
Peak memory 200520 kb
Host smart-eeef2dd3-b2a9-4a03-93a0-69ca02e4b6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773211132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1773211132
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3297373752
Short name T416
Test name
Test status
Simulation time 141946552 ps
CPU time 1.13 seconds
Started Jun 10 05:22:53 PM PDT 24
Finished Jun 10 05:22:54 PM PDT 24
Peak memory 200348 kb
Host smart-1b928495-3033-4aed-91b7-91a68e66dc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297373752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3297373752
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.229814478
Short name T95
Test name
Test status
Simulation time 105991082 ps
CPU time 1.2 seconds
Started Jun 10 05:22:52 PM PDT 24
Finished Jun 10 05:22:54 PM PDT 24
Peak memory 200548 kb
Host smart-d857f575-ab9d-4b3a-9e32-74051f45eac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229814478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.229814478
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.1053981804
Short name T356
Test name
Test status
Simulation time 675822675 ps
CPU time 3.13 seconds
Started Jun 10 05:22:56 PM PDT 24
Finished Jun 10 05:22:59 PM PDT 24
Peak memory 200344 kb
Host smart-1cb9ff27-add8-4466-ac17-b6264c749390
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053981804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1053981804
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.705078828
Short name T70
Test name
Test status
Simulation time 140746584 ps
CPU time 1.72 seconds
Started Jun 10 05:22:54 PM PDT 24
Finished Jun 10 05:22:56 PM PDT 24
Peak memory 200344 kb
Host smart-aa39e009-e268-443d-a6e4-30cc0ed68d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705078828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.705078828
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3492097789
Short name T338
Test name
Test status
Simulation time 92945801 ps
CPU time 0.92 seconds
Started Jun 10 05:22:54 PM PDT 24
Finished Jun 10 05:22:55 PM PDT 24
Peak memory 200432 kb
Host smart-a968bf48-2c81-4a85-8adc-c9c15f79385f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492097789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3492097789
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.4090798817
Short name T401
Test name
Test status
Simulation time 76860386 ps
CPU time 0.8 seconds
Started Jun 10 05:23:00 PM PDT 24
Finished Jun 10 05:23:01 PM PDT 24
Peak memory 200180 kb
Host smart-2f5e7767-525a-4863-ac17-bc436ac0652b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090798817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.4090798817
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1549613512
Short name T65
Test name
Test status
Simulation time 1892964690 ps
CPU time 7.29 seconds
Started Jun 10 05:22:57 PM PDT 24
Finished Jun 10 05:23:05 PM PDT 24
Peak memory 217920 kb
Host smart-924a6563-7816-4a62-9034-516ff45488c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549613512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1549613512
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.749313856
Short name T207
Test name
Test status
Simulation time 244195037 ps
CPU time 1.05 seconds
Started Jun 10 05:22:56 PM PDT 24
Finished Jun 10 05:22:57 PM PDT 24
Peak memory 217552 kb
Host smart-16a497a4-190f-4bf1-bf37-4c9972885838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749313856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.749313856
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.4066202892
Short name T503
Test name
Test status
Simulation time 90368121 ps
CPU time 0.75 seconds
Started Jun 10 05:22:52 PM PDT 24
Finished Jun 10 05:22:53 PM PDT 24
Peak memory 200172 kb
Host smart-7fe2c988-6af9-43b8-9330-a15306efe90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066202892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.4066202892
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2505736584
Short name T351
Test name
Test status
Simulation time 1066214514 ps
CPU time 5.03 seconds
Started Jun 10 05:22:54 PM PDT 24
Finished Jun 10 05:23:00 PM PDT 24
Peak memory 200536 kb
Host smart-bdb4a124-4c0b-47b1-85bd-982f8b26cb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505736584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2505736584
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2076487897
Short name T154
Test name
Test status
Simulation time 179287999 ps
CPU time 1.14 seconds
Started Jun 10 05:23:07 PM PDT 24
Finished Jun 10 05:23:09 PM PDT 24
Peak memory 200344 kb
Host smart-aebc36bb-fff8-4bfe-8cdd-81449d8775d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076487897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2076487897
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1096691671
Short name T166
Test name
Test status
Simulation time 112029203 ps
CPU time 1.25 seconds
Started Jun 10 05:22:53 PM PDT 24
Finished Jun 10 05:22:55 PM PDT 24
Peak memory 200552 kb
Host smart-cd2221cc-70c8-4f9f-bfe6-58fe65ead356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096691671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1096691671
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.3165979455
Short name T135
Test name
Test status
Simulation time 8246681997 ps
CPU time 30.29 seconds
Started Jun 10 05:22:56 PM PDT 24
Finished Jun 10 05:23:27 PM PDT 24
Peak memory 208920 kb
Host smart-ed3ab247-90bd-4333-ab7d-e83bc65d2a28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165979455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3165979455
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2816272994
Short name T171
Test name
Test status
Simulation time 340113527 ps
CPU time 2.19 seconds
Started Jun 10 05:22:57 PM PDT 24
Finished Jun 10 05:23:00 PM PDT 24
Peak memory 208460 kb
Host smart-6b12987b-dfc5-4ad2-96b6-8d2141265d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816272994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2816272994
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.627394140
Short name T494
Test name
Test status
Simulation time 101915391 ps
CPU time 0.9 seconds
Started Jun 10 05:23:01 PM PDT 24
Finished Jun 10 05:23:02 PM PDT 24
Peak memory 200288 kb
Host smart-e3976e91-300e-4715-bced-fa2c2f078c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627394140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.627394140
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2907358652
Short name T405
Test name
Test status
Simulation time 72624620 ps
CPU time 0.77 seconds
Started Jun 10 05:23:01 PM PDT 24
Finished Jun 10 05:23:02 PM PDT 24
Peak memory 200112 kb
Host smart-6ab4d1c9-7970-40bd-a036-cad145406b1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907358652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2907358652
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1083459883
Short name T34
Test name
Test status
Simulation time 1906711861 ps
CPU time 8.04 seconds
Started Jun 10 05:23:06 PM PDT 24
Finished Jun 10 05:23:15 PM PDT 24
Peak memory 216960 kb
Host smart-2bc24b88-f323-4b2f-b534-6524e5676b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083459883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1083459883
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2556285681
Short name T25
Test name
Test status
Simulation time 244790077 ps
CPU time 1.03 seconds
Started Jun 10 05:22:55 PM PDT 24
Finished Jun 10 05:22:57 PM PDT 24
Peak memory 217612 kb
Host smart-c9f80cef-4d94-46af-89f1-068d7b2a222c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556285681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2556285681
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2022214485
Short name T363
Test name
Test status
Simulation time 159412573 ps
CPU time 0.88 seconds
Started Jun 10 05:22:57 PM PDT 24
Finished Jun 10 05:22:59 PM PDT 24
Peak memory 200104 kb
Host smart-c00d468e-c247-4f68-a262-ab4eaf285903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022214485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2022214485
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1633625345
Short name T443
Test name
Test status
Simulation time 747542669 ps
CPU time 4.18 seconds
Started Jun 10 05:22:59 PM PDT 24
Finished Jun 10 05:23:04 PM PDT 24
Peak memory 200540 kb
Host smart-1428dc2a-3a63-4ecc-9a02-7cdd063e8277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633625345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1633625345
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.628215212
Short name T438
Test name
Test status
Simulation time 173980527 ps
CPU time 1.19 seconds
Started Jun 10 05:22:57 PM PDT 24
Finished Jun 10 05:22:59 PM PDT 24
Peak memory 200356 kb
Host smart-098f8a6a-d4d7-41e8-a212-b6f118ceb38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628215212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.628215212
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3471326642
Short name T375
Test name
Test status
Simulation time 200083637 ps
CPU time 1.39 seconds
Started Jun 10 05:22:58 PM PDT 24
Finished Jun 10 05:23:00 PM PDT 24
Peak memory 200448 kb
Host smart-05828d9d-a961-453c-8e25-99511af18379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471326642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3471326642
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3700892765
Short name T394
Test name
Test status
Simulation time 3199685903 ps
CPU time 16.18 seconds
Started Jun 10 05:22:57 PM PDT 24
Finished Jun 10 05:23:13 PM PDT 24
Peak memory 210776 kb
Host smart-af554fb0-1011-41f4-b90a-a93ffa4313c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700892765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3700892765
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2145516536
Short name T299
Test name
Test status
Simulation time 139077880 ps
CPU time 1.87 seconds
Started Jun 10 05:22:58 PM PDT 24
Finished Jun 10 05:23:00 PM PDT 24
Peak memory 200384 kb
Host smart-dc81bd41-981c-4777-b395-07900b6742d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145516536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2145516536
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.129413376
Short name T366
Test name
Test status
Simulation time 133533538 ps
CPU time 1 seconds
Started Jun 10 05:22:57 PM PDT 24
Finished Jun 10 05:22:59 PM PDT 24
Peak memory 200360 kb
Host smart-d47b90e3-5bec-45c9-bde2-3e5a9d15857a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129413376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.129413376
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.4279465359
Short name T379
Test name
Test status
Simulation time 71149976 ps
CPU time 0.82 seconds
Started Jun 10 05:23:00 PM PDT 24
Finished Jun 10 05:23:02 PM PDT 24
Peak memory 200112 kb
Host smart-b8924654-52a7-4f48-b1bf-168b80df00fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279465359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.4279465359
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2454945935
Short name T522
Test name
Test status
Simulation time 1225906645 ps
CPU time 5.5 seconds
Started Jun 10 05:22:57 PM PDT 24
Finished Jun 10 05:23:03 PM PDT 24
Peak memory 221984 kb
Host smart-aec812a0-45be-43d1-a873-3530e1a81a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454945935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2454945935
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1382012917
Short name T496
Test name
Test status
Simulation time 244782002 ps
CPU time 1.05 seconds
Started Jun 10 05:23:07 PM PDT 24
Finished Jun 10 05:23:08 PM PDT 24
Peak memory 217596 kb
Host smart-dc36bb6c-d180-4fcb-b993-994245a173ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382012917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1382012917
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3196359447
Short name T3
Test name
Test status
Simulation time 130272737 ps
CPU time 0.86 seconds
Started Jun 10 05:23:07 PM PDT 24
Finished Jun 10 05:23:09 PM PDT 24
Peak memory 200164 kb
Host smart-a34fa551-d4c4-4800-a2b4-6e8ce06618a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196359447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3196359447
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1057583006
Short name T197
Test name
Test status
Simulation time 1242793209 ps
CPU time 5.05 seconds
Started Jun 10 05:22:59 PM PDT 24
Finished Jun 10 05:23:04 PM PDT 24
Peak memory 200476 kb
Host smart-edfb9898-717b-4b5c-84e2-d2b321d146db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057583006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1057583006
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2470965368
Short name T185
Test name
Test status
Simulation time 179577305 ps
CPU time 1.25 seconds
Started Jun 10 05:22:57 PM PDT 24
Finished Jun 10 05:22:58 PM PDT 24
Peak memory 200360 kb
Host smart-90f2d423-2606-422f-84c9-dbaa40aba43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470965368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2470965368
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.2540037560
Short name T62
Test name
Test status
Simulation time 236659131 ps
CPU time 1.44 seconds
Started Jun 10 05:23:00 PM PDT 24
Finished Jun 10 05:23:01 PM PDT 24
Peak memory 200536 kb
Host smart-f89daad4-8302-44d5-93be-fffee9d7318e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540037560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2540037560
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.4054909236
Short name T112
Test name
Test status
Simulation time 4543653415 ps
CPU time 20.27 seconds
Started Jun 10 05:22:57 PM PDT 24
Finished Jun 10 05:23:18 PM PDT 24
Peak memory 208804 kb
Host smart-224e97fc-f0a4-488e-a25c-6a0e277f4286
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054909236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.4054909236
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.237677957
Short name T450
Test name
Test status
Simulation time 385115396 ps
CPU time 2.5 seconds
Started Jun 10 05:22:59 PM PDT 24
Finished Jun 10 05:23:02 PM PDT 24
Peak memory 200352 kb
Host smart-d5428b6a-0ac0-48e5-a0db-132c635a30f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237677957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.237677957
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.3016964191
Short name T215
Test name
Test status
Simulation time 181831904 ps
CPU time 1.21 seconds
Started Jun 10 05:23:07 PM PDT 24
Finished Jun 10 05:23:08 PM PDT 24
Peak memory 200344 kb
Host smart-325b6b20-8edd-4c3c-9910-f033a8a292ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016964191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.3016964191
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.430334647
Short name T523
Test name
Test status
Simulation time 77611894 ps
CPU time 0.84 seconds
Started Jun 10 05:23:02 PM PDT 24
Finished Jun 10 05:23:03 PM PDT 24
Peak memory 200164 kb
Host smart-d31466ec-3a92-4ef1-895d-54fabf2a733a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430334647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.430334647
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.688843223
Short name T326
Test name
Test status
Simulation time 1236532327 ps
CPU time 5.92 seconds
Started Jun 10 05:23:04 PM PDT 24
Finished Jun 10 05:23:10 PM PDT 24
Peak memory 217960 kb
Host smart-4cab2a35-568b-4c17-8350-8f289e1d9b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688843223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.688843223
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.926218583
Short name T350
Test name
Test status
Simulation time 243409911 ps
CPU time 1.14 seconds
Started Jun 10 05:23:05 PM PDT 24
Finished Jun 10 05:23:07 PM PDT 24
Peak memory 217500 kb
Host smart-4584521a-a771-4388-a440-040d6ca0cd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926218583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.926218583
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1424239261
Short name T292
Test name
Test status
Simulation time 100612591 ps
CPU time 0.79 seconds
Started Jun 10 05:23:04 PM PDT 24
Finished Jun 10 05:23:05 PM PDT 24
Peak memory 200152 kb
Host smart-0a49bab6-a350-4d5d-a63f-649af57d9774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424239261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1424239261
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1925402502
Short name T452
Test name
Test status
Simulation time 184164556 ps
CPU time 1.2 seconds
Started Jun 10 05:23:06 PM PDT 24
Finished Jun 10 05:23:07 PM PDT 24
Peak memory 200364 kb
Host smart-c7cd258d-946b-4786-b346-5b53740a9823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925402502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1925402502
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3317200
Short name T168
Test name
Test status
Simulation time 245657151 ps
CPU time 1.64 seconds
Started Jun 10 05:22:55 PM PDT 24
Finished Jun 10 05:22:57 PM PDT 24
Peak memory 200608 kb
Host smart-b9eb4393-042a-4a66-8091-8a728d67346f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3317200
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.4073903904
Short name T286
Test name
Test status
Simulation time 4902773990 ps
CPU time 22.18 seconds
Started Jun 10 05:23:04 PM PDT 24
Finished Jun 10 05:23:27 PM PDT 24
Peak memory 210280 kb
Host smart-2382dea7-ce75-4a00-8138-78a6d760ff59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073903904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.4073903904
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.2780476341
Short name T332
Test name
Test status
Simulation time 254372812 ps
CPU time 1.71 seconds
Started Jun 10 05:23:02 PM PDT 24
Finished Jun 10 05:23:04 PM PDT 24
Peak memory 200316 kb
Host smart-42144c9a-cbf2-4ac6-b14c-804c0eb399ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780476341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.2780476341
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3316185525
Short name T294
Test name
Test status
Simulation time 91576091 ps
CPU time 0.91 seconds
Started Jun 10 05:23:03 PM PDT 24
Finished Jun 10 05:23:04 PM PDT 24
Peak memory 200356 kb
Host smart-b6846c09-7a50-446f-99b9-dd58fd1be95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316185525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3316185525
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2558309703
Short name T538
Test name
Test status
Simulation time 1899419007 ps
CPU time 7.6 seconds
Started Jun 10 05:22:26 PM PDT 24
Finished Jun 10 05:22:34 PM PDT 24
Peak memory 217260 kb
Host smart-da8117c5-2e49-4ddd-a671-5c6e9d7c638d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558309703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2558309703
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3612315784
Short name T529
Test name
Test status
Simulation time 243656523 ps
CPU time 1.19 seconds
Started Jun 10 05:22:24 PM PDT 24
Finished Jun 10 05:22:26 PM PDT 24
Peak memory 217728 kb
Host smart-9f09facd-be41-4a6b-a810-b79e17abc520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612315784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3612315784
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3428774655
Short name T324
Test name
Test status
Simulation time 195413163 ps
CPU time 0.9 seconds
Started Jun 10 05:22:27 PM PDT 24
Finished Jun 10 05:22:28 PM PDT 24
Peak memory 200076 kb
Host smart-a71d5fb2-a82b-4fac-83d7-cc85697075e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428774655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3428774655
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1637550805
Short name T486
Test name
Test status
Simulation time 1590592971 ps
CPU time 6.45 seconds
Started Jun 10 05:22:22 PM PDT 24
Finished Jun 10 05:22:29 PM PDT 24
Peak memory 200536 kb
Host smart-03277299-790a-48a2-9105-e7f5f8ccbbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637550805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1637550805
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1880114022
Short name T83
Test name
Test status
Simulation time 16603823029 ps
CPU time 26.05 seconds
Started Jun 10 05:22:25 PM PDT 24
Finished Jun 10 05:22:51 PM PDT 24
Peak memory 217576 kb
Host smart-bfeb5d2f-da44-43e4-9826-657aa3fdc164
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880114022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1880114022
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2207396157
Short name T426
Test name
Test status
Simulation time 146458111 ps
CPU time 1.12 seconds
Started Jun 10 05:22:26 PM PDT 24
Finished Jun 10 05:22:28 PM PDT 24
Peak memory 200348 kb
Host smart-0a7e793a-8f84-4870-926a-c029fe8c9ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207396157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2207396157
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.299073302
Short name T492
Test name
Test status
Simulation time 120236374 ps
CPU time 1.16 seconds
Started Jun 10 05:22:24 PM PDT 24
Finished Jun 10 05:22:25 PM PDT 24
Peak memory 200516 kb
Host smart-8430f9ce-f910-4b98-a58b-d737cf5de769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299073302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.299073302
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1021762325
Short name T314
Test name
Test status
Simulation time 10116028629 ps
CPU time 36.54 seconds
Started Jun 10 05:22:26 PM PDT 24
Finished Jun 10 05:23:03 PM PDT 24
Peak memory 200688 kb
Host smart-a61f81b4-d962-453f-b9cd-115c2335a465
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021762325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1021762325
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2879632905
Short name T483
Test name
Test status
Simulation time 416912249 ps
CPU time 2.22 seconds
Started Jun 10 05:22:24 PM PDT 24
Finished Jun 10 05:22:27 PM PDT 24
Peak memory 208444 kb
Host smart-fc2d9fbd-9c81-4b29-ab14-37cf021f3505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879632905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2879632905
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1045422952
Short name T252
Test name
Test status
Simulation time 196535573 ps
CPU time 1.35 seconds
Started Jun 10 05:22:22 PM PDT 24
Finished Jun 10 05:22:24 PM PDT 24
Peak memory 200300 kb
Host smart-c0bb5fb3-b2c8-4083-b8d3-bd8f70c6f9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045422952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1045422952
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.34959750
Short name T362
Test name
Test status
Simulation time 71983379 ps
CPU time 0.78 seconds
Started Jun 10 05:23:02 PM PDT 24
Finished Jun 10 05:23:03 PM PDT 24
Peak memory 200168 kb
Host smart-7a3075cd-6c20-4179-a0c7-0a0e6dda76e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34959750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.34959750
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2483644978
Short name T388
Test name
Test status
Simulation time 2395971556 ps
CPU time 8.03 seconds
Started Jun 10 05:23:02 PM PDT 24
Finished Jun 10 05:23:10 PM PDT 24
Peak memory 218016 kb
Host smart-e47761e5-1d91-4300-ad08-00287fb8e2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483644978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2483644978
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2205428589
Short name T173
Test name
Test status
Simulation time 243775736 ps
CPU time 1.14 seconds
Started Jun 10 05:23:00 PM PDT 24
Finished Jun 10 05:23:02 PM PDT 24
Peak memory 217560 kb
Host smart-75f12ee4-9781-4e05-82c0-67c29383d517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205428589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2205428589
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.413786292
Short name T233
Test name
Test status
Simulation time 186202400 ps
CPU time 0.93 seconds
Started Jun 10 05:23:05 PM PDT 24
Finished Jun 10 05:23:07 PM PDT 24
Peak memory 200124 kb
Host smart-54db0d02-d3fa-4ee1-9bd6-5e887b7a1d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413786292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.413786292
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2224980775
Short name T323
Test name
Test status
Simulation time 834242913 ps
CPU time 4.16 seconds
Started Jun 10 05:23:01 PM PDT 24
Finished Jun 10 05:23:05 PM PDT 24
Peak memory 200536 kb
Host smart-7739a7f6-6223-45b2-9af2-7f653536e503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224980775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2224980775
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.108898142
Short name T383
Test name
Test status
Simulation time 152480598 ps
CPU time 1.15 seconds
Started Jun 10 05:23:08 PM PDT 24
Finished Jun 10 05:23:10 PM PDT 24
Peak memory 200376 kb
Host smart-1295b2be-3d36-46d3-8723-12da32ed6315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108898142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.108898142
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2320307758
Short name T340
Test name
Test status
Simulation time 248573117 ps
CPU time 1.65 seconds
Started Jun 10 05:23:03 PM PDT 24
Finished Jun 10 05:23:05 PM PDT 24
Peak memory 200516 kb
Host smart-d917c3b0-a307-4212-aab7-83c0f25c88ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320307758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2320307758
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3463542175
Short name T445
Test name
Test status
Simulation time 7558758843 ps
CPU time 33.07 seconds
Started Jun 10 05:23:06 PM PDT 24
Finished Jun 10 05:23:39 PM PDT 24
Peak memory 200676 kb
Host smart-e97adb6f-c100-46ad-b441-25ecffa2a7a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463542175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3463542175
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.1594168186
Short name T498
Test name
Test status
Simulation time 305158728 ps
CPU time 2.1 seconds
Started Jun 10 05:23:01 PM PDT 24
Finished Jun 10 05:23:03 PM PDT 24
Peak memory 208600 kb
Host smart-2efeb695-5051-4629-929e-96adc0723cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594168186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.1594168186
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.4044540265
Short name T230
Test name
Test status
Simulation time 101525262 ps
CPU time 0.96 seconds
Started Jun 10 05:23:08 PM PDT 24
Finished Jun 10 05:23:10 PM PDT 24
Peak memory 200348 kb
Host smart-3c029ae4-0d8a-472a-abac-ec391859a736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044540265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.4044540265
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3696419581
Short name T475
Test name
Test status
Simulation time 71111118 ps
CPU time 0.78 seconds
Started Jun 10 05:23:03 PM PDT 24
Finished Jun 10 05:23:05 PM PDT 24
Peak memory 200180 kb
Host smart-e78765f1-92a5-44de-8006-f0eddb566409
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696419581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3696419581
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1342347931
Short name T520
Test name
Test status
Simulation time 2359414924 ps
CPU time 8.39 seconds
Started Jun 10 05:23:04 PM PDT 24
Finished Jun 10 05:23:13 PM PDT 24
Peak memory 221840 kb
Host smart-a7fc3095-3eca-43b4-a17a-10a455e61adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342347931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1342347931
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3738533423
Short name T334
Test name
Test status
Simulation time 243537203 ps
CPU time 1.18 seconds
Started Jun 10 05:23:01 PM PDT 24
Finished Jun 10 05:23:02 PM PDT 24
Peak memory 217608 kb
Host smart-70af8ef3-66e6-424a-97ef-74618fbf0a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738533423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3738533423
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1689451600
Short name T270
Test name
Test status
Simulation time 107243322 ps
CPU time 0.77 seconds
Started Jun 10 05:23:04 PM PDT 24
Finished Jun 10 05:23:05 PM PDT 24
Peak memory 200244 kb
Host smart-a17879e8-f0dd-4d78-8e32-994d67da8ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689451600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1689451600
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.1104546850
Short name T110
Test name
Test status
Simulation time 915779079 ps
CPU time 4.6 seconds
Started Jun 10 05:23:03 PM PDT 24
Finished Jun 10 05:23:08 PM PDT 24
Peak memory 200464 kb
Host smart-d56edbf2-b3c5-4964-8c1e-5c79b255bd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104546850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.1104546850
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3789253689
Short name T161
Test name
Test status
Simulation time 150243098 ps
CPU time 1.1 seconds
Started Jun 10 05:23:00 PM PDT 24
Finished Jun 10 05:23:01 PM PDT 24
Peak memory 200384 kb
Host smart-877c06a6-e7f9-43c8-98f5-f53dccc9ea30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789253689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3789253689
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2871959003
Short name T226
Test name
Test status
Simulation time 253522878 ps
CPU time 1.46 seconds
Started Jun 10 05:23:03 PM PDT 24
Finished Jun 10 05:23:05 PM PDT 24
Peak memory 200532 kb
Host smart-1f42df9b-0807-43d2-8e33-253ebc789183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871959003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2871959003
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.4209108602
Short name T497
Test name
Test status
Simulation time 14421069527 ps
CPU time 52.61 seconds
Started Jun 10 05:23:03 PM PDT 24
Finished Jun 10 05:23:56 PM PDT 24
Peak memory 208832 kb
Host smart-191e7b61-e829-4f37-a0bb-69c1b0651c77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209108602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.4209108602
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.4244657942
Short name T179
Test name
Test status
Simulation time 346163308 ps
CPU time 2.26 seconds
Started Jun 10 05:23:07 PM PDT 24
Finished Jun 10 05:23:09 PM PDT 24
Peak memory 200360 kb
Host smart-fde11f46-5018-46fa-836e-f7063b825987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244657942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.4244657942
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.679399200
Short name T399
Test name
Test status
Simulation time 82316828 ps
CPU time 0.85 seconds
Started Jun 10 05:23:05 PM PDT 24
Finished Jun 10 05:23:06 PM PDT 24
Peak memory 200348 kb
Host smart-05a000dd-5a4b-4554-ba06-8b04adadb3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679399200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.679399200
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1271064153
Short name T476
Test name
Test status
Simulation time 57772561 ps
CPU time 0.76 seconds
Started Jun 10 05:23:05 PM PDT 24
Finished Jun 10 05:23:06 PM PDT 24
Peak memory 200312 kb
Host smart-b74828a3-cebf-4373-9529-44c8f1cf2a50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271064153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1271064153
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1183470065
Short name T468
Test name
Test status
Simulation time 1219214990 ps
CPU time 5.83 seconds
Started Jun 10 05:23:08 PM PDT 24
Finished Jun 10 05:23:14 PM PDT 24
Peak memory 217984 kb
Host smart-5a00a460-106e-473c-bbe5-4fb9ca5aac63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183470065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1183470065
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3078096420
Short name T190
Test name
Test status
Simulation time 244416798 ps
CPU time 1.13 seconds
Started Jun 10 05:23:06 PM PDT 24
Finished Jun 10 05:23:08 PM PDT 24
Peak memory 217604 kb
Host smart-a6170b52-65d4-46e6-ac41-cd5d7d94da0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078096420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3078096420
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.1117420457
Short name T158
Test name
Test status
Simulation time 84916325 ps
CPU time 0.75 seconds
Started Jun 10 05:23:03 PM PDT 24
Finished Jun 10 05:23:04 PM PDT 24
Peak memory 200168 kb
Host smart-cffd6153-dbb9-45f9-9578-daea0d73d21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117420457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1117420457
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2546768303
Short name T134
Test name
Test status
Simulation time 1702161417 ps
CPU time 6.07 seconds
Started Jun 10 05:23:04 PM PDT 24
Finished Jun 10 05:23:10 PM PDT 24
Peak memory 200536 kb
Host smart-c2dc2b55-c6a5-46a3-af8e-06dbe96d34a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546768303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2546768303
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.4017734507
Short name T155
Test name
Test status
Simulation time 147197334 ps
CPU time 1.19 seconds
Started Jun 10 05:23:07 PM PDT 24
Finished Jun 10 05:23:09 PM PDT 24
Peak memory 200432 kb
Host smart-8e89d61e-c70d-4d65-b9b0-cb0708e6225e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017734507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.4017734507
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2965896667
Short name T77
Test name
Test status
Simulation time 247610061 ps
CPU time 1.45 seconds
Started Jun 10 05:23:02 PM PDT 24
Finished Jun 10 05:23:04 PM PDT 24
Peak memory 200564 kb
Host smart-89af9c90-7369-4fa5-9a20-b1084c985562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965896667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2965896667
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2764806690
Short name T413
Test name
Test status
Simulation time 5832860617 ps
CPU time 22.03 seconds
Started Jun 10 05:23:06 PM PDT 24
Finished Jun 10 05:23:28 PM PDT 24
Peak memory 200716 kb
Host smart-23b6034c-8acc-41ca-848f-ad960ec203d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764806690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2764806690
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.927375581
Short name T390
Test name
Test status
Simulation time 318992960 ps
CPU time 1.99 seconds
Started Jun 10 05:23:07 PM PDT 24
Finished Jun 10 05:23:09 PM PDT 24
Peak memory 200268 kb
Host smart-0580b73c-eb33-4dcd-bf01-f317f5f03015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927375581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.927375581
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.77103640
Short name T341
Test name
Test status
Simulation time 109037491 ps
CPU time 1.04 seconds
Started Jun 10 05:23:03 PM PDT 24
Finished Jun 10 05:23:04 PM PDT 24
Peak memory 200320 kb
Host smart-3c247e88-55a8-4405-80e9-3e56a8ee4e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77103640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.77103640
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3601701103
Short name T160
Test name
Test status
Simulation time 70735236 ps
CPU time 0.82 seconds
Started Jun 10 05:23:08 PM PDT 24
Finished Jun 10 05:23:09 PM PDT 24
Peak memory 200172 kb
Host smart-56e1e039-da54-45f1-b00f-acb7aa53ee85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601701103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3601701103
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2935111248
Short name T27
Test name
Test status
Simulation time 2349097244 ps
CPU time 8.24 seconds
Started Jun 10 05:23:09 PM PDT 24
Finished Jun 10 05:23:18 PM PDT 24
Peak memory 218152 kb
Host smart-ad35e46a-f3fa-4cd7-a73e-b154eb769ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935111248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2935111248
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1845532665
Short name T237
Test name
Test status
Simulation time 244078672 ps
CPU time 1.08 seconds
Started Jun 10 05:23:04 PM PDT 24
Finished Jun 10 05:23:05 PM PDT 24
Peak memory 217612 kb
Host smart-3a4ec907-0762-4f51-b5ac-dabb77cd419e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845532665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.1845532665
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.3480718278
Short name T14
Test name
Test status
Simulation time 130985254 ps
CPU time 0.88 seconds
Started Jun 10 05:23:08 PM PDT 24
Finished Jun 10 05:23:09 PM PDT 24
Peak memory 200176 kb
Host smart-951aab9f-f000-47ee-bc53-b515d7cc8af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480718278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.3480718278
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1634462619
Short name T107
Test name
Test status
Simulation time 1653084836 ps
CPU time 6.22 seconds
Started Jun 10 05:23:07 PM PDT 24
Finished Jun 10 05:23:13 PM PDT 24
Peak memory 200556 kb
Host smart-cca2ddaa-a654-4a4a-9c94-635399d01af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634462619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1634462619
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.4083761488
Short name T361
Test name
Test status
Simulation time 107609240 ps
CPU time 1.01 seconds
Started Jun 10 05:23:07 PM PDT 24
Finished Jun 10 05:23:09 PM PDT 24
Peak memory 200324 kb
Host smart-719e05c4-75f9-4915-9bfa-e6971d78ab98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083761488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.4083761488
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2475298478
Short name T285
Test name
Test status
Simulation time 115996290 ps
CPU time 1.23 seconds
Started Jun 10 05:23:09 PM PDT 24
Finished Jun 10 05:23:11 PM PDT 24
Peak memory 200536 kb
Host smart-fedbbb4c-e8ba-419f-935d-de8e3fd361eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475298478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2475298478
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2143442285
Short name T109
Test name
Test status
Simulation time 8233849958 ps
CPU time 31.09 seconds
Started Jun 10 05:23:07 PM PDT 24
Finished Jun 10 05:23:38 PM PDT 24
Peak memory 208888 kb
Host smart-1a04cf5f-fd4d-40af-a510-1d234036c027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143442285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2143442285
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.67969830
Short name T66
Test name
Test status
Simulation time 298778872 ps
CPU time 2.03 seconds
Started Jun 10 05:23:06 PM PDT 24
Finished Jun 10 05:23:09 PM PDT 24
Peak memory 200344 kb
Host smart-3314d3b8-818f-4bcf-b094-c0db25de52a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67969830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.67969830
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1527030444
Short name T269
Test name
Test status
Simulation time 108985691 ps
CPU time 1 seconds
Started Jun 10 05:23:06 PM PDT 24
Finished Jun 10 05:23:07 PM PDT 24
Peak memory 200360 kb
Host smart-969f5fc2-d348-4932-9627-4b21f91e5d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527030444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1527030444
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3605884702
Short name T146
Test name
Test status
Simulation time 82736740 ps
CPU time 0.89 seconds
Started Jun 10 05:23:06 PM PDT 24
Finished Jun 10 05:23:08 PM PDT 24
Peak memory 200164 kb
Host smart-f1bc6d23-d8d4-4332-a5c7-e3e84d51912f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605884702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3605884702
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2362952618
Short name T465
Test name
Test status
Simulation time 1218258445 ps
CPU time 5.53 seconds
Started Jun 10 05:23:05 PM PDT 24
Finished Jun 10 05:23:11 PM PDT 24
Peak memory 217004 kb
Host smart-4ccb4a14-1055-4da0-a3ea-8168b49a9c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362952618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2362952618
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.822537593
Short name T325
Test name
Test status
Simulation time 244153558 ps
CPU time 1.11 seconds
Started Jun 10 05:23:09 PM PDT 24
Finished Jun 10 05:23:11 PM PDT 24
Peak memory 217564 kb
Host smart-8ebb70db-f643-4e26-bac4-53381568d738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822537593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.822537593
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3160103163
Short name T223
Test name
Test status
Simulation time 81941232 ps
CPU time 0.76 seconds
Started Jun 10 05:23:11 PM PDT 24
Finished Jun 10 05:23:12 PM PDT 24
Peak memory 200156 kb
Host smart-25a16b6f-4bb0-4251-911a-5cc00ad2500a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160103163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3160103163
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.1552746928
Short name T304
Test name
Test status
Simulation time 941197258 ps
CPU time 4.77 seconds
Started Jun 10 05:23:08 PM PDT 24
Finished Jun 10 05:23:14 PM PDT 24
Peak memory 200616 kb
Host smart-50a1fdf7-1980-4f7c-b402-c3c4142f8c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552746928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1552746928
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.4100518014
Short name T472
Test name
Test status
Simulation time 177905251 ps
CPU time 1.17 seconds
Started Jun 10 05:23:07 PM PDT 24
Finished Jun 10 05:23:09 PM PDT 24
Peak memory 200356 kb
Host smart-fa641ef4-ea4d-4ada-b932-99050f257e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100518014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.4100518014
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1593332785
Short name T485
Test name
Test status
Simulation time 192451314 ps
CPU time 1.34 seconds
Started Jun 10 05:23:06 PM PDT 24
Finished Jun 10 05:23:07 PM PDT 24
Peak memory 200544 kb
Host smart-e0580d6b-3172-450f-a853-e0dc3a82e3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593332785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1593332785
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.961997044
Short name T512
Test name
Test status
Simulation time 2773210854 ps
CPU time 12.02 seconds
Started Jun 10 05:23:12 PM PDT 24
Finished Jun 10 05:23:24 PM PDT 24
Peak memory 208888 kb
Host smart-1dadd09b-b09e-4658-bd92-de55a7c91bb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961997044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.961997044
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.4251424154
Short name T456
Test name
Test status
Simulation time 265448313 ps
CPU time 1.82 seconds
Started Jun 10 05:23:09 PM PDT 24
Finished Jun 10 05:23:11 PM PDT 24
Peak memory 200364 kb
Host smart-863c1b7d-0861-4f49-a0cd-c824d9ef2535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251424154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.4251424154
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1176545009
Short name T505
Test name
Test status
Simulation time 114291559 ps
CPU time 1.04 seconds
Started Jun 10 05:23:07 PM PDT 24
Finished Jun 10 05:23:09 PM PDT 24
Peak memory 200348 kb
Host smart-9f35a2c5-4dff-4ecf-bb1f-40f47f825746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176545009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1176545009
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3101192030
Short name T232
Test name
Test status
Simulation time 64777375 ps
CPU time 0.78 seconds
Started Jun 10 05:23:15 PM PDT 24
Finished Jun 10 05:23:16 PM PDT 24
Peak memory 200204 kb
Host smart-566a8344-e8ca-4402-94c0-64a2dbd074a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101192030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3101192030
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3246112944
Short name T28
Test name
Test status
Simulation time 1889503994 ps
CPU time 7.17 seconds
Started Jun 10 05:23:16 PM PDT 24
Finished Jun 10 05:23:24 PM PDT 24
Peak memory 221948 kb
Host smart-601d146c-86f2-41e9-a8ef-ad253d272705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246112944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3246112944
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.4283400757
Short name T58
Test name
Test status
Simulation time 243778192 ps
CPU time 1.17 seconds
Started Jun 10 05:23:23 PM PDT 24
Finished Jun 10 05:23:24 PM PDT 24
Peak memory 217644 kb
Host smart-7504b31e-0b5f-4b7f-8404-9599bd4979d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283400757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.4283400757
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.4212015635
Short name T449
Test name
Test status
Simulation time 105037675 ps
CPU time 0.82 seconds
Started Jun 10 05:23:08 PM PDT 24
Finished Jun 10 05:23:09 PM PDT 24
Peak memory 200164 kb
Host smart-e9f0781e-40c4-465a-ad1a-30174778411a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212015635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.4212015635
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.3434037366
Short name T412
Test name
Test status
Simulation time 1687286984 ps
CPU time 6.72 seconds
Started Jun 10 05:23:09 PM PDT 24
Finished Jun 10 05:23:16 PM PDT 24
Peak memory 200520 kb
Host smart-602ab581-27eb-4d74-9436-3cb9aea90357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434037366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3434037366
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2771778222
Short name T467
Test name
Test status
Simulation time 107072845 ps
CPU time 1.08 seconds
Started Jun 10 05:23:16 PM PDT 24
Finished Jun 10 05:23:17 PM PDT 24
Peak memory 200320 kb
Host smart-b9381f8b-3d34-4bc1-a4fa-5d712ce68aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771778222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2771778222
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2479389691
Short name T279
Test name
Test status
Simulation time 238986890 ps
CPU time 1.47 seconds
Started Jun 10 05:23:07 PM PDT 24
Finished Jun 10 05:23:09 PM PDT 24
Peak memory 200496 kb
Host smart-16149559-b9fe-4174-a51c-3f04a44e27a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479389691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2479389691
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3284946668
Short name T429
Test name
Test status
Simulation time 6250530331 ps
CPU time 23.19 seconds
Started Jun 10 05:23:17 PM PDT 24
Finished Jun 10 05:23:41 PM PDT 24
Peak memory 208940 kb
Host smart-54afec75-e25d-4849-8b60-aba1bea6db77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284946668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3284946668
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1092792015
Short name T309
Test name
Test status
Simulation time 126286671 ps
CPU time 1.56 seconds
Started Jun 10 05:23:08 PM PDT 24
Finished Jun 10 05:23:10 PM PDT 24
Peak memory 208504 kb
Host smart-29075f8d-c104-4874-a9ac-223351f8eea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092792015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1092792015
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3782558343
Short name T477
Test name
Test status
Simulation time 222038392 ps
CPU time 1.28 seconds
Started Jun 10 05:23:09 PM PDT 24
Finished Jun 10 05:23:11 PM PDT 24
Peak memory 200356 kb
Host smart-5ab38803-7652-4bd1-9fd4-4e31c655370f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782558343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3782558343
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3082003987
Short name T192
Test name
Test status
Simulation time 72118602 ps
CPU time 0.76 seconds
Started Jun 10 05:23:17 PM PDT 24
Finished Jun 10 05:23:18 PM PDT 24
Peak memory 200168 kb
Host smart-22014ee6-2cf9-4d67-afed-69990c6fb107
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082003987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3082003987
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.58722782
Short name T374
Test name
Test status
Simulation time 1889086325 ps
CPU time 6.88 seconds
Started Jun 10 05:23:18 PM PDT 24
Finished Jun 10 05:23:25 PM PDT 24
Peak memory 221936 kb
Host smart-49efe206-5379-4515-b980-9d0e281b5a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58722782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.58722782
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2269405273
Short name T386
Test name
Test status
Simulation time 244530728 ps
CPU time 1.14 seconds
Started Jun 10 05:23:16 PM PDT 24
Finished Jun 10 05:23:18 PM PDT 24
Peak memory 217620 kb
Host smart-9fd87587-9fd6-4e38-ae4e-db6dea003c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269405273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2269405273
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.323562176
Short name T19
Test name
Test status
Simulation time 232123920 ps
CPU time 1.12 seconds
Started Jun 10 05:23:11 PM PDT 24
Finished Jun 10 05:23:13 PM PDT 24
Peak memory 200232 kb
Host smart-3237eae6-1486-4248-a70e-6d3bd69c0fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323562176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.323562176
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.226397286
Short name T55
Test name
Test status
Simulation time 1526965589 ps
CPU time 6.38 seconds
Started Jun 10 05:23:14 PM PDT 24
Finished Jun 10 05:23:21 PM PDT 24
Peak memory 200576 kb
Host smart-5dfdaca6-5b3a-40a3-8b7d-6181fc771199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226397286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.226397286
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.4199277177
Short name T247
Test name
Test status
Simulation time 145820250 ps
CPU time 1.17 seconds
Started Jun 10 05:23:18 PM PDT 24
Finished Jun 10 05:23:20 PM PDT 24
Peak memory 200324 kb
Host smart-38b40035-07d2-47ca-a4e0-f53654db8319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199277177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.4199277177
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.312241150
Short name T504
Test name
Test status
Simulation time 209373794 ps
CPU time 1.47 seconds
Started Jun 10 05:23:17 PM PDT 24
Finished Jun 10 05:23:19 PM PDT 24
Peak memory 200536 kb
Host smart-10dd1af3-085a-4d18-9948-00babdc50077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312241150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.312241150
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2093159416
Short name T471
Test name
Test status
Simulation time 8591023693 ps
CPU time 30.7 seconds
Started Jun 10 05:23:15 PM PDT 24
Finished Jun 10 05:23:46 PM PDT 24
Peak memory 209444 kb
Host smart-76927908-c53a-4b52-832c-a6bdea138dfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093159416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2093159416
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2999683892
Short name T484
Test name
Test status
Simulation time 315357484 ps
CPU time 2.14 seconds
Started Jun 10 05:23:19 PM PDT 24
Finished Jun 10 05:23:21 PM PDT 24
Peak memory 200416 kb
Host smart-eea8f7dd-8561-4d8d-a3d1-db77973eae07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999683892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2999683892
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.913514099
Short name T228
Test name
Test status
Simulation time 124363828 ps
CPU time 1.1 seconds
Started Jun 10 05:23:19 PM PDT 24
Finished Jun 10 05:23:21 PM PDT 24
Peak memory 200344 kb
Host smart-688ac6f2-7338-4da8-adc1-b9f04e72dc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913514099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.913514099
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2213135895
Short name T316
Test name
Test status
Simulation time 65237910 ps
CPU time 0.77 seconds
Started Jun 10 05:23:17 PM PDT 24
Finished Jun 10 05:23:18 PM PDT 24
Peak memory 200228 kb
Host smart-b2c6679c-dfab-4435-bf20-562db20e09c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213135895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2213135895
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2390343883
Short name T526
Test name
Test status
Simulation time 1893679462 ps
CPU time 6.85 seconds
Started Jun 10 05:23:14 PM PDT 24
Finished Jun 10 05:23:21 PM PDT 24
Peak memory 217468 kb
Host smart-e6a6f707-783d-4121-9841-a9f7010c1705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390343883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2390343883
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1682238275
Short name T282
Test name
Test status
Simulation time 244068286 ps
CPU time 1.1 seconds
Started Jun 10 05:23:16 PM PDT 24
Finished Jun 10 05:23:18 PM PDT 24
Peak memory 217576 kb
Host smart-3699c89c-e22f-4cd9-abf8-d163b2e3081d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682238275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1682238275
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.365090412
Short name T239
Test name
Test status
Simulation time 193487519 ps
CPU time 0.91 seconds
Started Jun 10 05:23:18 PM PDT 24
Finished Jun 10 05:23:20 PM PDT 24
Peak memory 200180 kb
Host smart-e67a64de-f074-44d3-994f-fc2e129d79e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365090412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.365090412
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1074542485
Short name T5
Test name
Test status
Simulation time 710782850 ps
CPU time 3.66 seconds
Started Jun 10 05:23:19 PM PDT 24
Finished Jun 10 05:23:23 PM PDT 24
Peak memory 200540 kb
Host smart-496c1351-ade9-4bcf-bcf1-7bddfb164f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074542485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1074542485
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2569943939
Short name T162
Test name
Test status
Simulation time 161997880 ps
CPU time 1.21 seconds
Started Jun 10 05:23:21 PM PDT 24
Finished Jun 10 05:23:23 PM PDT 24
Peak memory 199768 kb
Host smart-e1c27930-8e8a-448e-8ba3-e38fb8fe3231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569943939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2569943939
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2715313886
Short name T455
Test name
Test status
Simulation time 209958819 ps
CPU time 1.41 seconds
Started Jun 10 05:23:15 PM PDT 24
Finished Jun 10 05:23:17 PM PDT 24
Peak memory 200552 kb
Host smart-a2c42196-4d3c-45f6-bc61-653a6ed1a4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715313886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2715313886
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2240829211
Short name T343
Test name
Test status
Simulation time 3982941173 ps
CPU time 14.06 seconds
Started Jun 10 05:23:16 PM PDT 24
Finished Jun 10 05:23:31 PM PDT 24
Peak memory 209460 kb
Host smart-55b39eb7-cab0-4980-8f2c-247631f2b9e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240829211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2240829211
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3465485247
Short name T183
Test name
Test status
Simulation time 120992746 ps
CPU time 1.47 seconds
Started Jun 10 05:23:23 PM PDT 24
Finished Jun 10 05:23:25 PM PDT 24
Peak memory 200372 kb
Host smart-18cb959d-2ae3-4972-9ae8-ed0a5ecbb672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465485247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3465485247
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1262385853
Short name T387
Test name
Test status
Simulation time 126361725 ps
CPU time 1.08 seconds
Started Jun 10 05:23:17 PM PDT 24
Finished Jun 10 05:23:19 PM PDT 24
Peak memory 200356 kb
Host smart-77a805b7-3fda-4032-af14-017145b4fbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262385853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1262385853
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.2363129826
Short name T64
Test name
Test status
Simulation time 79907150 ps
CPU time 0.83 seconds
Started Jun 10 05:23:17 PM PDT 24
Finished Jun 10 05:23:19 PM PDT 24
Peak memory 200088 kb
Host smart-6f4c528b-43d3-4e08-9706-335957128617
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363129826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2363129826
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.4031564516
Short name T191
Test name
Test status
Simulation time 243483579 ps
CPU time 1.06 seconds
Started Jun 10 05:23:17 PM PDT 24
Finished Jun 10 05:23:18 PM PDT 24
Peak memory 217604 kb
Host smart-f1461e62-ba68-4734-bd3a-03aad204f2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031564516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.4031564516
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.1535173261
Short name T487
Test name
Test status
Simulation time 149749526 ps
CPU time 0.92 seconds
Started Jun 10 05:23:16 PM PDT 24
Finished Jun 10 05:23:18 PM PDT 24
Peak memory 200212 kb
Host smart-bda9ea80-3ab7-4317-88ef-074bcdbd970b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535173261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.1535173261
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.2883164657
Short name T436
Test name
Test status
Simulation time 1621836572 ps
CPU time 6.36 seconds
Started Jun 10 05:23:23 PM PDT 24
Finished Jun 10 05:23:30 PM PDT 24
Peak memory 200480 kb
Host smart-78d58790-99ae-421d-95c3-fc4bed90349b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883164657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.2883164657
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.508049818
Short name T392
Test name
Test status
Simulation time 183448584 ps
CPU time 1.26 seconds
Started Jun 10 05:23:18 PM PDT 24
Finished Jun 10 05:23:19 PM PDT 24
Peak memory 200388 kb
Host smart-cc09663d-e7d8-4007-a120-b1e23034d93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508049818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.508049818
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.504890046
Short name T370
Test name
Test status
Simulation time 249826766 ps
CPU time 1.5 seconds
Started Jun 10 05:23:20 PM PDT 24
Finished Jun 10 05:23:22 PM PDT 24
Peak memory 200540 kb
Host smart-11a397ae-f543-4f2d-8cac-3eeb764855c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504890046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.504890046
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3387497808
Short name T349
Test name
Test status
Simulation time 879782671 ps
CPU time 4.34 seconds
Started Jun 10 05:23:17 PM PDT 24
Finished Jun 10 05:23:21 PM PDT 24
Peak memory 200552 kb
Host smart-c33ba6db-f23e-4b34-9f58-065260cf83ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387497808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3387497808
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2883990323
Short name T358
Test name
Test status
Simulation time 136652154 ps
CPU time 1.75 seconds
Started Jun 10 05:23:18 PM PDT 24
Finished Jun 10 05:23:20 PM PDT 24
Peak memory 200424 kb
Host smart-c8458ad8-a33c-4159-8a34-705c79b4a112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883990323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2883990323
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1034948031
Short name T262
Test name
Test status
Simulation time 270491805 ps
CPU time 1.51 seconds
Started Jun 10 05:23:19 PM PDT 24
Finished Jun 10 05:23:21 PM PDT 24
Peak memory 200328 kb
Host smart-654c52ee-2e63-4d6b-a12e-c957362f15b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034948031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1034948031
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3515492059
Short name T274
Test name
Test status
Simulation time 68903546 ps
CPU time 0.81 seconds
Started Jun 10 05:23:21 PM PDT 24
Finished Jun 10 05:23:23 PM PDT 24
Peak memory 199472 kb
Host smart-e3965c1d-1b1b-4715-b2bb-c870b2e6b9fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515492059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3515492059
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2512732641
Short name T490
Test name
Test status
Simulation time 1221786785 ps
CPU time 5.9 seconds
Started Jun 10 05:23:18 PM PDT 24
Finished Jun 10 05:23:25 PM PDT 24
Peak memory 217948 kb
Host smart-4cdc6f78-6735-415a-b612-f16587e95d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512732641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2512732641
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.920239325
Short name T454
Test name
Test status
Simulation time 244488920 ps
CPU time 1.1 seconds
Started Jun 10 05:23:19 PM PDT 24
Finished Jun 10 05:23:21 PM PDT 24
Peak memory 217608 kb
Host smart-6f515d4e-5e71-4474-938d-c8772149eaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920239325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.920239325
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2606746237
Short name T303
Test name
Test status
Simulation time 152856587 ps
CPU time 0.84 seconds
Started Jun 10 05:23:18 PM PDT 24
Finished Jun 10 05:23:19 PM PDT 24
Peak memory 200112 kb
Host smart-a4468247-c074-4d9a-a07a-9cc9e14d0c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606746237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2606746237
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2046542795
Short name T242
Test name
Test status
Simulation time 1381877276 ps
CPU time 5.53 seconds
Started Jun 10 05:23:17 PM PDT 24
Finished Jun 10 05:23:22 PM PDT 24
Peak memory 200504 kb
Host smart-601efef9-3ef4-4f6b-b588-e6ff132e3382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046542795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2046542795
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2245560233
Short name T460
Test name
Test status
Simulation time 180288039 ps
CPU time 1.22 seconds
Started Jun 10 05:23:18 PM PDT 24
Finished Jun 10 05:23:19 PM PDT 24
Peak memory 200344 kb
Host smart-e00a9136-effe-4cd6-b2cf-2fbbdf8f3834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245560233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2245560233
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2422541287
Short name T542
Test name
Test status
Simulation time 256532206 ps
CPU time 1.52 seconds
Started Jun 10 05:23:16 PM PDT 24
Finished Jun 10 05:23:17 PM PDT 24
Peak memory 200616 kb
Host smart-cc9526e5-652e-4291-9b81-948f363830b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422541287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2422541287
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.4162982857
Short name T382
Test name
Test status
Simulation time 10475239211 ps
CPU time 36.64 seconds
Started Jun 10 05:23:14 PM PDT 24
Finished Jun 10 05:23:51 PM PDT 24
Peak memory 210608 kb
Host smart-25b5ef0a-d495-43ad-ac14-7183551a3d7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162982857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.4162982857
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2395119555
Short name T369
Test name
Test status
Simulation time 542960296 ps
CPU time 2.72 seconds
Started Jun 10 05:23:16 PM PDT 24
Finished Jun 10 05:23:19 PM PDT 24
Peak memory 200292 kb
Host smart-5b211b97-54f3-43ac-b226-53c203a2e087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395119555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2395119555
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1582389469
Short name T206
Test name
Test status
Simulation time 141325569 ps
CPU time 1.22 seconds
Started Jun 10 05:23:19 PM PDT 24
Finished Jun 10 05:23:20 PM PDT 24
Peak memory 200548 kb
Host smart-c886c1d4-1ac5-497b-8d8e-6232feb514bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582389469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1582389469
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1490749691
Short name T205
Test name
Test status
Simulation time 71355332 ps
CPU time 0.86 seconds
Started Jun 10 05:22:27 PM PDT 24
Finished Jun 10 05:22:29 PM PDT 24
Peak memory 200160 kb
Host smart-52f2690c-ec9e-4585-8873-d1aeebaf5f8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490749691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1490749691
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.646964051
Short name T439
Test name
Test status
Simulation time 2364642240 ps
CPU time 8.28 seconds
Started Jun 10 05:22:30 PM PDT 24
Finished Jun 10 05:22:39 PM PDT 24
Peak memory 217888 kb
Host smart-d0d7a7ef-ecab-4c09-9290-0c147ba1e9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646964051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.646964051
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2482542646
Short name T461
Test name
Test status
Simulation time 243372407 ps
CPU time 1.16 seconds
Started Jun 10 05:22:32 PM PDT 24
Finished Jun 10 05:22:33 PM PDT 24
Peak memory 217612 kb
Host smart-60fc44ee-de46-4a0c-90f3-1580699c5c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482542646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2482542646
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2996951864
Short name T493
Test name
Test status
Simulation time 145242043 ps
CPU time 0.87 seconds
Started Jun 10 05:22:30 PM PDT 24
Finished Jun 10 05:22:31 PM PDT 24
Peak memory 200176 kb
Host smart-9f6e9fb1-d007-414a-b8cf-8699e78bcc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996951864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2996951864
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1350395912
Short name T12
Test name
Test status
Simulation time 1804133340 ps
CPU time 6.7 seconds
Started Jun 10 05:22:27 PM PDT 24
Finished Jun 10 05:22:35 PM PDT 24
Peak memory 200536 kb
Host smart-a4beeaa5-a7f0-4c77-9cd1-7ed3123ea25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350395912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1350395912
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1940326491
Short name T87
Test name
Test status
Simulation time 16708613817 ps
CPU time 25.95 seconds
Started Jun 10 05:22:31 PM PDT 24
Finished Jun 10 05:22:58 PM PDT 24
Peak memory 218568 kb
Host smart-d6e7a650-4871-4705-b1ba-66516a3c46b9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940326491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1940326491
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3336446352
Short name T152
Test name
Test status
Simulation time 185830312 ps
CPU time 1.18 seconds
Started Jun 10 05:22:28 PM PDT 24
Finished Jun 10 05:22:30 PM PDT 24
Peak memory 200260 kb
Host smart-e6fbf342-7323-4d66-b8fc-c2231298e17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336446352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3336446352
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.731539426
Short name T404
Test name
Test status
Simulation time 192817342 ps
CPU time 1.36 seconds
Started Jun 10 05:22:25 PM PDT 24
Finished Jun 10 05:22:26 PM PDT 24
Peak memory 200504 kb
Host smart-ad78f9e7-2751-44f9-b445-c9ea1f9edac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731539426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.731539426
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1927523166
Short name T189
Test name
Test status
Simulation time 565333740 ps
CPU time 2.63 seconds
Started Jun 10 05:22:30 PM PDT 24
Finished Jun 10 05:22:33 PM PDT 24
Peak memory 200568 kb
Host smart-21be122d-2af1-440b-bdec-b954f91920a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927523166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1927523166
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.131584486
Short name T409
Test name
Test status
Simulation time 300991424 ps
CPU time 2 seconds
Started Jun 10 05:22:31 PM PDT 24
Finished Jun 10 05:22:34 PM PDT 24
Peak memory 208512 kb
Host smart-013c166d-3ce0-48bd-8c8a-7a2ea15c16e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131584486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.131584486
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2919557220
Short name T36
Test name
Test status
Simulation time 139498576 ps
CPU time 1.25 seconds
Started Jun 10 05:22:24 PM PDT 24
Finished Jun 10 05:22:26 PM PDT 24
Peak memory 200484 kb
Host smart-93ac9502-e534-45be-b19a-9f3886eef798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919557220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2919557220
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3176144052
Short name T446
Test name
Test status
Simulation time 68994879 ps
CPU time 0.76 seconds
Started Jun 10 05:23:18 PM PDT 24
Finished Jun 10 05:23:19 PM PDT 24
Peak memory 200124 kb
Host smart-eb5239be-eca7-4cdf-b309-4b24aea09dcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176144052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3176144052
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1210071018
Short name T342
Test name
Test status
Simulation time 2192384224 ps
CPU time 7.79 seconds
Started Jun 10 05:23:21 PM PDT 24
Finished Jun 10 05:23:30 PM PDT 24
Peak memory 218264 kb
Host smart-1501a1c1-96d8-4126-a8af-3db7540ca0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210071018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1210071018
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.4016699753
Short name T451
Test name
Test status
Simulation time 244248229 ps
CPU time 1.15 seconds
Started Jun 10 05:23:22 PM PDT 24
Finished Jun 10 05:23:23 PM PDT 24
Peak memory 217652 kb
Host smart-60e48ef9-168b-445a-bb81-5b68549be0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016699753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.4016699753
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2335039939
Short name T221
Test name
Test status
Simulation time 225243465 ps
CPU time 0.94 seconds
Started Jun 10 05:23:20 PM PDT 24
Finished Jun 10 05:23:21 PM PDT 24
Peak memory 200156 kb
Host smart-a92f49d9-8252-4e33-821d-4fc116723413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335039939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2335039939
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.4000472239
Short name T140
Test name
Test status
Simulation time 962835816 ps
CPU time 4.78 seconds
Started Jun 10 05:23:19 PM PDT 24
Finished Jun 10 05:23:24 PM PDT 24
Peak memory 200540 kb
Host smart-cb8996fa-f5ca-4fcf-b60f-ccb2c62891fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000472239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.4000472239
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3981144368
Short name T204
Test name
Test status
Simulation time 176982143 ps
CPU time 1.3 seconds
Started Jun 10 05:23:18 PM PDT 24
Finished Jun 10 05:23:20 PM PDT 24
Peak memory 200300 kb
Host smart-bdf94f3b-5570-42c1-abae-62078185e94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981144368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3981144368
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.150359446
Short name T525
Test name
Test status
Simulation time 119650603 ps
CPU time 1.25 seconds
Started Jun 10 05:23:18 PM PDT 24
Finished Jun 10 05:23:19 PM PDT 24
Peak memory 200556 kb
Host smart-e531cf0b-1959-4854-8299-e9bee8a190ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150359446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.150359446
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2525817852
Short name T108
Test name
Test status
Simulation time 4930990000 ps
CPU time 21.75 seconds
Started Jun 10 05:23:18 PM PDT 24
Finished Jun 10 05:23:40 PM PDT 24
Peak memory 208880 kb
Host smart-318861e0-4324-49ff-aeda-279ca477057f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525817852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2525817852
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.1167733820
Short name T218
Test name
Test status
Simulation time 123160983 ps
CPU time 1.56 seconds
Started Jun 10 05:23:24 PM PDT 24
Finished Jun 10 05:23:26 PM PDT 24
Peak memory 208616 kb
Host smart-ebc9d1ce-b340-4c93-a241-6d43f9d59659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167733820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1167733820
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1548456663
Short name T272
Test name
Test status
Simulation time 131064124 ps
CPU time 1.11 seconds
Started Jun 10 05:23:18 PM PDT 24
Finished Jun 10 05:23:20 PM PDT 24
Peak memory 200344 kb
Host smart-462f1f8d-10e8-4a48-bd10-d1c2a8d2d2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548456663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1548456663
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.3426808163
Short name T389
Test name
Test status
Simulation time 72912821 ps
CPU time 0.81 seconds
Started Jun 10 05:23:23 PM PDT 24
Finished Jun 10 05:23:25 PM PDT 24
Peak memory 200148 kb
Host smart-fee9300a-c99d-43c8-8384-998264bd5fe1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426808163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3426808163
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.530837153
Short name T29
Test name
Test status
Simulation time 2353932857 ps
CPU time 8.04 seconds
Started Jun 10 05:23:20 PM PDT 24
Finished Jun 10 05:23:29 PM PDT 24
Peak memory 217940 kb
Host smart-a3eb82aa-e534-4b3c-aad7-c096544f9f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530837153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.530837153
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1041513798
Short name T278
Test name
Test status
Simulation time 243412068 ps
CPU time 1.13 seconds
Started Jun 10 05:23:23 PM PDT 24
Finished Jun 10 05:23:24 PM PDT 24
Peak memory 217584 kb
Host smart-9bd90802-7e7d-4c2f-a2bb-e61f40167364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041513798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1041513798
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1007570910
Short name T528
Test name
Test status
Simulation time 200372764 ps
CPU time 0.9 seconds
Started Jun 10 05:23:19 PM PDT 24
Finished Jun 10 05:23:20 PM PDT 24
Peak memory 200176 kb
Host smart-7ab0af45-fef7-485e-bb62-0587133ffb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007570910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1007570910
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2354631334
Short name T510
Test name
Test status
Simulation time 1552678120 ps
CPU time 6.42 seconds
Started Jun 10 05:23:21 PM PDT 24
Finished Jun 10 05:23:28 PM PDT 24
Peak memory 200496 kb
Host smart-f04116ed-c569-470a-8a28-2a78e8b7d3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354631334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2354631334
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.353339773
Short name T153
Test name
Test status
Simulation time 107663674 ps
CPU time 1.01 seconds
Started Jun 10 05:23:21 PM PDT 24
Finished Jun 10 05:23:22 PM PDT 24
Peak memory 200364 kb
Host smart-9a321f66-cbb9-44ee-955a-07ee352c3fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353339773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.353339773
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1899659483
Short name T198
Test name
Test status
Simulation time 193696607 ps
CPU time 1.47 seconds
Started Jun 10 05:23:20 PM PDT 24
Finished Jun 10 05:23:22 PM PDT 24
Peak memory 200700 kb
Host smart-0d12e356-d61e-4e85-8295-8e28d0f9b7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899659483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1899659483
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.1122439290
Short name T434
Test name
Test status
Simulation time 5592579472 ps
CPU time 21.01 seconds
Started Jun 10 05:23:20 PM PDT 24
Finished Jun 10 05:23:41 PM PDT 24
Peak memory 200608 kb
Host smart-774773a7-b930-4856-a99c-8efbc9e8648a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122439290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.1122439290
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.558091385
Short name T52
Test name
Test status
Simulation time 153898517 ps
CPU time 1.82 seconds
Started Jun 10 05:23:21 PM PDT 24
Finished Jun 10 05:23:24 PM PDT 24
Peak memory 200212 kb
Host smart-84fc62f4-d0af-4488-ad07-d81f9901db65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558091385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.558091385
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2580598506
Short name T448
Test name
Test status
Simulation time 101321014 ps
CPU time 0.98 seconds
Started Jun 10 05:23:22 PM PDT 24
Finished Jun 10 05:23:24 PM PDT 24
Peak memory 200356 kb
Host smart-35903da6-70b7-4c65-91e8-6410bb1fa152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580598506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2580598506
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2712723141
Short name T482
Test name
Test status
Simulation time 71867720 ps
CPU time 0.84 seconds
Started Jun 10 05:23:24 PM PDT 24
Finished Jun 10 05:23:25 PM PDT 24
Peak memory 200084 kb
Host smart-dbc0a1be-40c5-4d29-84ac-10a704a86673
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712723141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2712723141
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2598721621
Short name T488
Test name
Test status
Simulation time 1227504376 ps
CPU time 5.75 seconds
Started Jun 10 05:23:21 PM PDT 24
Finished Jun 10 05:23:27 PM PDT 24
Peak memory 217960 kb
Host smart-10a872f0-0ac6-409e-af54-a0931af646b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598721621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2598721621
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2753356151
Short name T142
Test name
Test status
Simulation time 244607527 ps
CPU time 1.08 seconds
Started Jun 10 05:23:23 PM PDT 24
Finished Jun 10 05:23:25 PM PDT 24
Peak memory 217668 kb
Host smart-847b2b1c-c297-43f0-817b-97c2485f0f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753356151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.2753356151
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1392285109
Short name T391
Test name
Test status
Simulation time 182121939 ps
CPU time 0.86 seconds
Started Jun 10 05:23:23 PM PDT 24
Finished Jun 10 05:23:25 PM PDT 24
Peak memory 200164 kb
Host smart-0d78298c-476f-4c9a-a47f-b8d55fc95ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392285109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1392285109
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.3997431380
Short name T424
Test name
Test status
Simulation time 780832896 ps
CPU time 3.87 seconds
Started Jun 10 05:23:22 PM PDT 24
Finished Jun 10 05:23:26 PM PDT 24
Peak memory 200536 kb
Host smart-c1703853-d8b3-429f-a5db-441bc3bd302e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997431380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3997431380
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3399029548
Short name T245
Test name
Test status
Simulation time 144619964 ps
CPU time 1.09 seconds
Started Jun 10 05:23:22 PM PDT 24
Finished Jun 10 05:23:23 PM PDT 24
Peak memory 200352 kb
Host smart-9a924ebc-12f3-43f3-b47c-60853dfe56ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399029548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3399029548
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2254750265
Short name T530
Test name
Test status
Simulation time 254660491 ps
CPU time 1.55 seconds
Started Jun 10 05:23:21 PM PDT 24
Finished Jun 10 05:23:23 PM PDT 24
Peak memory 200592 kb
Host smart-54a2243d-9022-478b-903b-ea62ad81fc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254750265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2254750265
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.4246028940
Short name T543
Test name
Test status
Simulation time 9970194697 ps
CPU time 36.5 seconds
Started Jun 10 05:23:22 PM PDT 24
Finished Jun 10 05:23:59 PM PDT 24
Peak memory 209008 kb
Host smart-b5a1ad14-f339-46ee-b856-713974c3e4a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246028940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.4246028940
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.2912990064
Short name T395
Test name
Test status
Simulation time 351708891 ps
CPU time 2.12 seconds
Started Jun 10 05:23:22 PM PDT 24
Finished Jun 10 05:23:24 PM PDT 24
Peak memory 200380 kb
Host smart-a6fb0a2c-1b3c-4456-a57e-39e35f91ac29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912990064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.2912990064
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.3509127979
Short name T234
Test name
Test status
Simulation time 191742552 ps
CPU time 1.24 seconds
Started Jun 10 05:23:21 PM PDT 24
Finished Jun 10 05:23:23 PM PDT 24
Peak memory 200348 kb
Host smart-e47916ec-2189-4909-8f2d-1876924fe8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509127979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3509127979
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1427531652
Short name T365
Test name
Test status
Simulation time 87907061 ps
CPU time 0.81 seconds
Started Jun 10 05:23:22 PM PDT 24
Finished Jun 10 05:23:23 PM PDT 24
Peak memory 200144 kb
Host smart-80020077-7b24-464b-9d56-20d902a4a1f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427531652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1427531652
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2935541613
Short name T372
Test name
Test status
Simulation time 1215365336 ps
CPU time 6.15 seconds
Started Jun 10 05:23:24 PM PDT 24
Finished Jun 10 05:23:31 PM PDT 24
Peak memory 217996 kb
Host smart-0a2806df-4c05-4275-81f2-c263ab019c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935541613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2935541613
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.578580325
Short name T345
Test name
Test status
Simulation time 243985393 ps
CPU time 1.04 seconds
Started Jun 10 05:23:22 PM PDT 24
Finished Jun 10 05:23:23 PM PDT 24
Peak memory 217568 kb
Host smart-625d73fc-1aba-4312-9a2e-9ac627b6569b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578580325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.578580325
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.3785998853
Short name T337
Test name
Test status
Simulation time 144233865 ps
CPU time 0.82 seconds
Started Jun 10 05:23:20 PM PDT 24
Finished Jun 10 05:23:21 PM PDT 24
Peak memory 200172 kb
Host smart-f3a62f53-00a2-4d48-a8b8-b64377ba8b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785998853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3785998853
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3559629678
Short name T328
Test name
Test status
Simulation time 1482631486 ps
CPU time 6.08 seconds
Started Jun 10 05:23:23 PM PDT 24
Finished Jun 10 05:23:30 PM PDT 24
Peak memory 200588 kb
Host smart-ebf322fb-8675-4e40-83ae-bacfb9a66056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559629678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3559629678
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.4203399335
Short name T359
Test name
Test status
Simulation time 189417204 ps
CPU time 1.2 seconds
Started Jun 10 05:23:20 PM PDT 24
Finished Jun 10 05:23:22 PM PDT 24
Peak memory 200324 kb
Host smart-d85b068f-fa77-414a-a513-bda36290f3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203399335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.4203399335
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2096144182
Short name T276
Test name
Test status
Simulation time 251367490 ps
CPU time 1.45 seconds
Started Jun 10 05:23:24 PM PDT 24
Finished Jun 10 05:23:26 PM PDT 24
Peak memory 200592 kb
Host smart-5227500e-fb6f-4dcf-986b-929a6538da4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096144182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2096144182
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.4277937600
Short name T423
Test name
Test status
Simulation time 6537831896 ps
CPU time 23.92 seconds
Started Jun 10 05:23:23 PM PDT 24
Finished Jun 10 05:23:48 PM PDT 24
Peak memory 200640 kb
Host smart-fcec6112-2da5-422e-8048-7c0e5fbeef55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277937600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.4277937600
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3112217554
Short name T216
Test name
Test status
Simulation time 147416372 ps
CPU time 1.78 seconds
Started Jun 10 05:23:24 PM PDT 24
Finished Jun 10 05:23:26 PM PDT 24
Peak memory 200248 kb
Host smart-bd1d9fb8-51c3-4bcc-b895-6b0155de620a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112217554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3112217554
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.914612469
Short name T509
Test name
Test status
Simulation time 73994027 ps
CPU time 0.84 seconds
Started Jun 10 05:23:27 PM PDT 24
Finished Jun 10 05:23:28 PM PDT 24
Peak memory 200348 kb
Host smart-fbdb995f-a905-4567-b117-593616b00f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914612469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.914612469
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2806018764
Short name T527
Test name
Test status
Simulation time 74039957 ps
CPU time 0.74 seconds
Started Jun 10 05:23:26 PM PDT 24
Finished Jun 10 05:23:27 PM PDT 24
Peak memory 200164 kb
Host smart-8e2dc577-9b4a-4750-99d4-b4f87b932191
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806018764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2806018764
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.2811143624
Short name T47
Test name
Test status
Simulation time 1890461263 ps
CPU time 7.26 seconds
Started Jun 10 05:23:28 PM PDT 24
Finished Jun 10 05:23:36 PM PDT 24
Peak memory 230160 kb
Host smart-69f59b1c-72ba-4187-9957-21b7565a4464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811143624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2811143624
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.874213625
Short name T532
Test name
Test status
Simulation time 244654045 ps
CPU time 1.22 seconds
Started Jun 10 05:23:28 PM PDT 24
Finished Jun 10 05:23:29 PM PDT 24
Peak memory 217600 kb
Host smart-7d4a8d15-0336-44eb-829d-01d3c6234f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874213625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.874213625
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.303571678
Short name T322
Test name
Test status
Simulation time 122489364 ps
CPU time 0.8 seconds
Started Jun 10 05:23:20 PM PDT 24
Finished Jun 10 05:23:21 PM PDT 24
Peak memory 200176 kb
Host smart-ac86ff77-56b1-4e62-97f6-847019e3cc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303571678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.303571678
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.327121748
Short name T463
Test name
Test status
Simulation time 986870638 ps
CPU time 4.88 seconds
Started Jun 10 05:23:28 PM PDT 24
Finished Jun 10 05:23:34 PM PDT 24
Peak memory 200540 kb
Host smart-a946fd72-8454-4daf-922e-f711db343f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327121748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.327121748
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.293263146
Short name T254
Test name
Test status
Simulation time 152863323 ps
CPU time 1.24 seconds
Started Jun 10 05:23:30 PM PDT 24
Finished Jun 10 05:23:31 PM PDT 24
Peak memory 200368 kb
Host smart-37d6df72-ae6a-4e33-a9dd-6e5e16d6a70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293263146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.293263146
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3127427941
Short name T312
Test name
Test status
Simulation time 246697422 ps
CPU time 1.44 seconds
Started Jun 10 05:23:23 PM PDT 24
Finished Jun 10 05:23:25 PM PDT 24
Peak memory 200592 kb
Host smart-e2497e8f-5bfb-4c75-81f0-a21bd9ebacfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127427941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3127427941
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3382914853
Short name T163
Test name
Test status
Simulation time 440457640 ps
CPU time 2.13 seconds
Started Jun 10 05:23:30 PM PDT 24
Finished Jun 10 05:23:32 PM PDT 24
Peak memory 200560 kb
Host smart-b516e37c-3a1e-4bd3-ad44-d6baca91886f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382914853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3382914853
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.311132846
Short name T402
Test name
Test status
Simulation time 139524949 ps
CPU time 1.86 seconds
Started Jun 10 05:23:31 PM PDT 24
Finished Jun 10 05:23:34 PM PDT 24
Peak memory 200340 kb
Host smart-1fb905bd-1a30-48e1-92f2-ae13b5e93836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311132846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.311132846
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.2126424815
Short name T381
Test name
Test status
Simulation time 220332383 ps
CPU time 1.33 seconds
Started Jun 10 05:23:24 PM PDT 24
Finished Jun 10 05:23:26 PM PDT 24
Peak memory 200268 kb
Host smart-ce37eed9-76cf-400e-9959-574a78a6fb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126424815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2126424815
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.384924438
Short name T244
Test name
Test status
Simulation time 85706889 ps
CPU time 0.88 seconds
Started Jun 10 05:23:26 PM PDT 24
Finished Jun 10 05:23:27 PM PDT 24
Peak memory 200160 kb
Host smart-5e555877-a28f-4b08-b6fb-bf117159d232
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384924438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.384924438
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.901724972
Short name T45
Test name
Test status
Simulation time 2360962116 ps
CPU time 8.3 seconds
Started Jun 10 05:23:28 PM PDT 24
Finished Jun 10 05:23:37 PM PDT 24
Peak memory 222096 kb
Host smart-5a265cdb-c7da-48ea-ac5e-a26f8668ef91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901724972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.901724972
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.517953252
Short name T302
Test name
Test status
Simulation time 243482938 ps
CPU time 1.11 seconds
Started Jun 10 05:23:26 PM PDT 24
Finished Jun 10 05:23:28 PM PDT 24
Peak memory 217596 kb
Host smart-5b656669-b6a0-4421-86fa-4176668f574f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517953252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.517953252
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1221413676
Short name T251
Test name
Test status
Simulation time 185447174 ps
CPU time 0.88 seconds
Started Jun 10 05:23:27 PM PDT 24
Finished Jun 10 05:23:29 PM PDT 24
Peak memory 200176 kb
Host smart-e3cdaf35-11f6-4344-bb16-1675ebbcaebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221413676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1221413676
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.4025766765
Short name T433
Test name
Test status
Simulation time 761713468 ps
CPU time 4.16 seconds
Started Jun 10 05:23:25 PM PDT 24
Finished Jun 10 05:23:29 PM PDT 24
Peak memory 200516 kb
Host smart-f70abe2d-152c-4206-bcc8-437dea684ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025766765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.4025766765
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.4179290825
Short name T346
Test name
Test status
Simulation time 103408141 ps
CPU time 1.02 seconds
Started Jun 10 05:23:26 PM PDT 24
Finished Jun 10 05:23:28 PM PDT 24
Peak memory 200384 kb
Host smart-a9ab3123-a694-4167-b2e6-2607e770c47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179290825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.4179290825
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1408191484
Short name T283
Test name
Test status
Simulation time 112747363 ps
CPU time 1.18 seconds
Started Jun 10 05:23:27 PM PDT 24
Finished Jun 10 05:23:28 PM PDT 24
Peak memory 200540 kb
Host smart-2ed48361-2787-43a7-bc4b-77536577b7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408191484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1408191484
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1774401586
Short name T37
Test name
Test status
Simulation time 536822693 ps
CPU time 2.5 seconds
Started Jun 10 05:23:27 PM PDT 24
Finished Jun 10 05:23:30 PM PDT 24
Peak memory 200592 kb
Host smart-c23af949-c9a2-449c-a618-1072bc230ba8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774401586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1774401586
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.152089892
Short name T385
Test name
Test status
Simulation time 145491072 ps
CPU time 1.91 seconds
Started Jun 10 05:23:26 PM PDT 24
Finished Jun 10 05:23:28 PM PDT 24
Peak memory 200332 kb
Host smart-00c2fef4-095b-411c-ba4d-baffabc5fdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152089892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.152089892
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2216787009
Short name T310
Test name
Test status
Simulation time 126404749 ps
CPU time 1.04 seconds
Started Jun 10 05:23:27 PM PDT 24
Finished Jun 10 05:23:29 PM PDT 24
Peak memory 200400 kb
Host smart-5e6be467-7be5-4733-97c3-c207a855c981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216787009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2216787009
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.125685242
Short name T331
Test name
Test status
Simulation time 59279071 ps
CPU time 0.76 seconds
Started Jun 10 05:23:27 PM PDT 24
Finished Jun 10 05:23:29 PM PDT 24
Peak memory 200176 kb
Host smart-786d2fc8-a5cb-4f5e-b0a7-f5098d916576
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125685242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.125685242
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.920474038
Short name T430
Test name
Test status
Simulation time 1219285091 ps
CPU time 5.61 seconds
Started Jun 10 05:23:29 PM PDT 24
Finished Jun 10 05:23:35 PM PDT 24
Peak memory 216980 kb
Host smart-b3b73fcd-ce1c-4819-8331-f771fdff6632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920474038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.920474038
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2363898718
Short name T377
Test name
Test status
Simulation time 244208335 ps
CPU time 1.1 seconds
Started Jun 10 05:23:26 PM PDT 24
Finished Jun 10 05:23:27 PM PDT 24
Peak memory 217640 kb
Host smart-0f32cc43-7a29-4a77-a817-dd707d3d1876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363898718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2363898718
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.45818183
Short name T364
Test name
Test status
Simulation time 169737618 ps
CPU time 0.85 seconds
Started Jun 10 05:23:27 PM PDT 24
Finished Jun 10 05:23:28 PM PDT 24
Peak memory 200176 kb
Host smart-49e79c9f-bd9a-4986-90ed-965fbd41e83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45818183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.45818183
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.398265240
Short name T57
Test name
Test status
Simulation time 1715833757 ps
CPU time 6.63 seconds
Started Jun 10 05:23:28 PM PDT 24
Finished Jun 10 05:23:35 PM PDT 24
Peak memory 200544 kb
Host smart-89c15724-88b0-4f95-aaac-9dc986bb3afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398265240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.398265240
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2595243004
Short name T501
Test name
Test status
Simulation time 135828493 ps
CPU time 1.11 seconds
Started Jun 10 05:23:29 PM PDT 24
Finished Jun 10 05:23:31 PM PDT 24
Peak memory 200348 kb
Host smart-e2deec27-2148-4f77-bb5f-16883e8cc1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595243004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2595243004
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.1101046070
Short name T418
Test name
Test status
Simulation time 123781595 ps
CPU time 1.18 seconds
Started Jun 10 05:23:25 PM PDT 24
Finished Jun 10 05:23:27 PM PDT 24
Peak memory 200544 kb
Host smart-575fb109-fe73-4a5a-9adc-f7523087f5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101046070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1101046070
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3659687304
Short name T508
Test name
Test status
Simulation time 8002970348 ps
CPU time 27.68 seconds
Started Jun 10 05:23:30 PM PDT 24
Finished Jun 10 05:23:58 PM PDT 24
Peak memory 208880 kb
Host smart-81a52b7e-8d13-422c-948d-3bc12f3c839b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659687304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3659687304
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1156660105
Short name T170
Test name
Test status
Simulation time 121445927 ps
CPU time 1.42 seconds
Started Jun 10 05:23:27 PM PDT 24
Finished Jun 10 05:23:29 PM PDT 24
Peak memory 200420 kb
Host smart-22170cea-a929-40a2-af13-d7980f319391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156660105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1156660105
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3400605584
Short name T175
Test name
Test status
Simulation time 241945563 ps
CPU time 1.4 seconds
Started Jun 10 05:23:29 PM PDT 24
Finished Jun 10 05:23:31 PM PDT 24
Peak memory 200548 kb
Host smart-d1ba18f7-40f8-404f-bb2b-458717323c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400605584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3400605584
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1844341042
Short name T10
Test name
Test status
Simulation time 75063972 ps
CPU time 0.83 seconds
Started Jun 10 05:23:32 PM PDT 24
Finished Jun 10 05:23:33 PM PDT 24
Peak memory 200088 kb
Host smart-0448f160-cf79-4507-abb5-f17c8d4bfe3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844341042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1844341042
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3916708897
Short name T462
Test name
Test status
Simulation time 1229000067 ps
CPU time 5.42 seconds
Started Jun 10 05:23:34 PM PDT 24
Finished Jun 10 05:23:40 PM PDT 24
Peak memory 217956 kb
Host smart-0c51b372-7c7d-4883-b884-15031dd8d8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916708897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3916708897
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3745381298
Short name T371
Test name
Test status
Simulation time 243792695 ps
CPU time 1.13 seconds
Started Jun 10 05:23:35 PM PDT 24
Finished Jun 10 05:23:36 PM PDT 24
Peak memory 217652 kb
Host smart-f99106f4-b6c2-4642-84a1-6127e3e50e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745381298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3745381298
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1353343528
Short name T212
Test name
Test status
Simulation time 124077595 ps
CPU time 0.82 seconds
Started Jun 10 05:23:28 PM PDT 24
Finished Jun 10 05:23:29 PM PDT 24
Peak memory 200144 kb
Host smart-9856f391-e936-4f80-a0a0-50ee1cb6d81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353343528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1353343528
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.3333413814
Short name T106
Test name
Test status
Simulation time 1602627205 ps
CPU time 5.78 seconds
Started Jun 10 05:23:29 PM PDT 24
Finished Jun 10 05:23:35 PM PDT 24
Peak memory 200512 kb
Host smart-b2121f61-07ea-402e-aa71-eded4ffeb2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333413814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3333413814
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.1059165362
Short name T13
Test name
Test status
Simulation time 149613319 ps
CPU time 1.11 seconds
Started Jun 10 05:23:30 PM PDT 24
Finished Jun 10 05:23:32 PM PDT 24
Peak memory 200360 kb
Host smart-9fa0dfd3-8155-4641-bc9e-f06b9e0fe284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059165362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.1059165362
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.328557089
Short name T241
Test name
Test status
Simulation time 130236616 ps
CPU time 1.22 seconds
Started Jun 10 05:23:30 PM PDT 24
Finished Jun 10 05:23:31 PM PDT 24
Peak memory 200512 kb
Host smart-95532ab7-2153-4971-937e-ae354d3f2c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328557089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.328557089
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2916684444
Short name T293
Test name
Test status
Simulation time 1999337049 ps
CPU time 7.8 seconds
Started Jun 10 05:23:32 PM PDT 24
Finished Jun 10 05:23:41 PM PDT 24
Peak memory 200600 kb
Host smart-492df46f-2f11-40dc-a7fc-a07566b9e3d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916684444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2916684444
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2701801682
Short name T137
Test name
Test status
Simulation time 384951093 ps
CPU time 2.2 seconds
Started Jun 10 05:23:30 PM PDT 24
Finished Jun 10 05:23:32 PM PDT 24
Peak memory 208512 kb
Host smart-89e37e66-09cf-483b-b6da-0ee651d93051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701801682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2701801682
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2445423154
Short name T267
Test name
Test status
Simulation time 244650673 ps
CPU time 1.48 seconds
Started Jun 10 05:23:32 PM PDT 24
Finished Jun 10 05:23:34 PM PDT 24
Peak memory 200540 kb
Host smart-cd30fb41-fff9-4463-9a20-4d212b23b2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445423154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2445423154
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3218224103
Short name T411
Test name
Test status
Simulation time 60360366 ps
CPU time 0.74 seconds
Started Jun 10 05:23:28 PM PDT 24
Finished Jun 10 05:23:30 PM PDT 24
Peak memory 200180 kb
Host smart-701ea8bc-1cb5-4f93-937c-0d6759260df7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218224103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3218224103
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3478965167
Short name T33
Test name
Test status
Simulation time 2335165536 ps
CPU time 8.41 seconds
Started Jun 10 05:23:31 PM PDT 24
Finished Jun 10 05:23:40 PM PDT 24
Peak memory 218076 kb
Host smart-a8de6207-b03f-46d4-a610-1adebaaf1314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478965167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3478965167
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2715754861
Short name T144
Test name
Test status
Simulation time 245653585 ps
CPU time 1.07 seconds
Started Jun 10 05:23:34 PM PDT 24
Finished Jun 10 05:23:36 PM PDT 24
Peak memory 217608 kb
Host smart-8cf968aa-f2da-468a-ba9f-b17f274a8128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715754861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2715754861
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.4117532856
Short name T447
Test name
Test status
Simulation time 84617191 ps
CPU time 0.72 seconds
Started Jun 10 05:23:36 PM PDT 24
Finished Jun 10 05:23:37 PM PDT 24
Peak memory 200136 kb
Host smart-c6b22bb4-351a-4825-8150-87a117c2a114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117532856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.4117532856
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1221560740
Short name T105
Test name
Test status
Simulation time 1633470265 ps
CPU time 6.22 seconds
Started Jun 10 05:23:32 PM PDT 24
Finished Jun 10 05:23:39 PM PDT 24
Peak memory 200540 kb
Host smart-b98f2532-8125-4c7a-af29-7ca324a9f06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221560740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1221560740
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.462248878
Short name T141
Test name
Test status
Simulation time 102288222 ps
CPU time 1 seconds
Started Jun 10 05:23:31 PM PDT 24
Finished Jun 10 05:23:33 PM PDT 24
Peak memory 200332 kb
Host smart-0fc949a7-20fe-4f04-8e56-e19aa5591e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462248878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.462248878
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2701593891
Short name T93
Test name
Test status
Simulation time 238455321 ps
CPU time 1.5 seconds
Started Jun 10 05:23:30 PM PDT 24
Finished Jun 10 05:23:32 PM PDT 24
Peak memory 200596 kb
Host smart-1f844567-0dd8-4608-a7ee-256e81caf751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701593891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2701593891
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3325503570
Short name T313
Test name
Test status
Simulation time 1544170177 ps
CPU time 7.91 seconds
Started Jun 10 05:23:31 PM PDT 24
Finished Jun 10 05:23:40 PM PDT 24
Peak memory 208740 kb
Host smart-d219bc99-5987-4abc-83b4-b8cb8e3cc68c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325503570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3325503570
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1350965562
Short name T219
Test name
Test status
Simulation time 430001843 ps
CPU time 2.46 seconds
Started Jun 10 05:23:33 PM PDT 24
Finished Jun 10 05:23:36 PM PDT 24
Peak memory 200416 kb
Host smart-cddcdb3a-57c8-420c-91b9-fc699f47611f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350965562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1350965562
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1038925664
Short name T355
Test name
Test status
Simulation time 184693624 ps
CPU time 1.21 seconds
Started Jun 10 05:23:31 PM PDT 24
Finished Jun 10 05:23:33 PM PDT 24
Peak memory 200344 kb
Host smart-9ae49713-cd04-4adc-a52b-82863dd035d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038925664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1038925664
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3372130258
Short name T335
Test name
Test status
Simulation time 59410240 ps
CPU time 0.75 seconds
Started Jun 10 05:23:31 PM PDT 24
Finished Jun 10 05:23:32 PM PDT 24
Peak memory 200160 kb
Host smart-c75fa493-9fbe-46bd-9d2e-fc7cb2682f60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372130258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3372130258
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.4069702098
Short name T260
Test name
Test status
Simulation time 1225030635 ps
CPU time 5.4 seconds
Started Jun 10 05:23:33 PM PDT 24
Finished Jun 10 05:23:39 PM PDT 24
Peak memory 217948 kb
Host smart-b0edcebb-d5ef-4a95-b66d-776b3dcc9417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069702098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.4069702098
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1010680776
Short name T517
Test name
Test status
Simulation time 244708976 ps
CPU time 1.16 seconds
Started Jun 10 05:23:33 PM PDT 24
Finished Jun 10 05:23:35 PM PDT 24
Peak memory 217492 kb
Host smart-4426e02e-072f-49cd-a353-c466bf6a809b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010680776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1010680776
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2363983463
Short name T255
Test name
Test status
Simulation time 93193967 ps
CPU time 0.76 seconds
Started Jun 10 05:23:31 PM PDT 24
Finished Jun 10 05:23:32 PM PDT 24
Peak memory 200192 kb
Host smart-301f507b-d12b-4984-b699-774483b8182e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363983463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2363983463
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.108905405
Short name T289
Test name
Test status
Simulation time 1291004701 ps
CPU time 5.49 seconds
Started Jun 10 05:23:32 PM PDT 24
Finished Jun 10 05:23:38 PM PDT 24
Peak memory 200528 kb
Host smart-f9d5e8db-c602-4f99-b604-930c1b815e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108905405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.108905405
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1737107284
Short name T537
Test name
Test status
Simulation time 108605146 ps
CPU time 0.99 seconds
Started Jun 10 05:23:31 PM PDT 24
Finished Jun 10 05:23:32 PM PDT 24
Peak memory 200368 kb
Host smart-51c988e1-a9a3-4b6b-8849-f4bb1fe0a7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737107284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1737107284
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3497938726
Short name T200
Test name
Test status
Simulation time 256982754 ps
CPU time 1.6 seconds
Started Jun 10 05:23:31 PM PDT 24
Finished Jun 10 05:23:33 PM PDT 24
Peak memory 200540 kb
Host smart-27db8c7f-a43c-4181-af4e-736752e41293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497938726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3497938726
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.570877288
Short name T281
Test name
Test status
Simulation time 8048891373 ps
CPU time 31.83 seconds
Started Jun 10 05:23:34 PM PDT 24
Finished Jun 10 05:24:07 PM PDT 24
Peak memory 208888 kb
Host smart-a93a643c-34b0-40a2-b16a-4ff8c0e75ea4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570877288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.570877288
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3844181018
Short name T71
Test name
Test status
Simulation time 153410440 ps
CPU time 1.89 seconds
Started Jun 10 05:23:33 PM PDT 24
Finished Jun 10 05:23:35 PM PDT 24
Peak memory 200348 kb
Host smart-ef73c334-0c57-4da8-80e3-8aef85b7a80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844181018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3844181018
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1683626365
Short name T284
Test name
Test status
Simulation time 234693319 ps
CPU time 1.33 seconds
Started Jun 10 05:23:31 PM PDT 24
Finished Jun 10 05:23:33 PM PDT 24
Peak memory 200308 kb
Host smart-e64ff40b-868d-40ee-9649-935bccbd67a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683626365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1683626365
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2279018058
Short name T441
Test name
Test status
Simulation time 62576548 ps
CPU time 0.8 seconds
Started Jun 10 05:22:29 PM PDT 24
Finished Jun 10 05:22:31 PM PDT 24
Peak memory 200172 kb
Host smart-17eafb0d-f824-4e33-abfd-c9a0b5515854
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279018058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2279018058
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.304807560
Short name T32
Test name
Test status
Simulation time 2350889326 ps
CPU time 9.13 seconds
Started Jun 10 05:22:26 PM PDT 24
Finished Jun 10 05:22:35 PM PDT 24
Peak memory 217884 kb
Host smart-b161aef9-6180-4b06-a287-8c1c2b6564aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304807560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.304807560
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1051827773
Short name T403
Test name
Test status
Simulation time 246781975 ps
CPU time 1.05 seconds
Started Jun 10 05:22:29 PM PDT 24
Finished Jun 10 05:22:30 PM PDT 24
Peak memory 217580 kb
Host smart-4ca1b1a1-79c0-4de0-8599-2894fbd54b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051827773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1051827773
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.4282951408
Short name T352
Test name
Test status
Simulation time 127857629 ps
CPU time 0.84 seconds
Started Jun 10 05:22:28 PM PDT 24
Finished Jun 10 05:22:29 PM PDT 24
Peak memory 200160 kb
Host smart-54ecb41e-7082-4707-ad77-d3b795fa9764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282951408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.4282951408
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2540774759
Short name T264
Test name
Test status
Simulation time 1606886038 ps
CPU time 6.38 seconds
Started Jun 10 05:22:27 PM PDT 24
Finished Jun 10 05:22:34 PM PDT 24
Peak memory 200540 kb
Host smart-0fcbc5c4-179d-4442-867a-35e4beec0981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540774759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2540774759
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.1210978638
Short name T82
Test name
Test status
Simulation time 14639439018 ps
CPU time 24.6 seconds
Started Jun 10 05:22:29 PM PDT 24
Finished Jun 10 05:22:54 PM PDT 24
Peak memory 217660 kb
Host smart-43b1b560-6868-485a-bc29-3f9eb63959fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210978638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1210978638
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.504570123
Short name T20
Test name
Test status
Simulation time 101827992 ps
CPU time 1.01 seconds
Started Jun 10 05:22:31 PM PDT 24
Finished Jun 10 05:22:33 PM PDT 24
Peak memory 200360 kb
Host smart-3970d187-e8f3-41ea-acaa-3e48e0a0be81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504570123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.504570123
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.780704575
Short name T7
Test name
Test status
Simulation time 249111705 ps
CPU time 1.52 seconds
Started Jun 10 05:22:29 PM PDT 24
Finished Jun 10 05:22:31 PM PDT 24
Peak memory 200552 kb
Host smart-60d83689-2311-4420-9d74-85b1c94456e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780704575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.780704575
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.364159973
Short name T202
Test name
Test status
Simulation time 1282707893 ps
CPU time 5.37 seconds
Started Jun 10 05:22:28 PM PDT 24
Finished Jun 10 05:22:34 PM PDT 24
Peak memory 200536 kb
Host smart-934a9c9e-9284-4e6f-85d3-a1c1ecfbbb1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364159973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.364159973
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2669262608
Short name T415
Test name
Test status
Simulation time 125788812 ps
CPU time 1.52 seconds
Started Jun 10 05:22:28 PM PDT 24
Finished Jun 10 05:22:30 PM PDT 24
Peak memory 200364 kb
Host smart-ce12e97d-57dc-4a98-ad34-025a15a7bc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669262608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2669262608
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1704395579
Short name T336
Test name
Test status
Simulation time 63579909 ps
CPU time 0.78 seconds
Started Jun 10 05:22:31 PM PDT 24
Finished Jun 10 05:22:32 PM PDT 24
Peak memory 200360 kb
Host smart-31360421-f89e-45cc-8377-dee63235956e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704395579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1704395579
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2476661862
Short name T184
Test name
Test status
Simulation time 94533804 ps
CPU time 0.87 seconds
Started Jun 10 05:23:36 PM PDT 24
Finished Jun 10 05:23:37 PM PDT 24
Peak memory 200172 kb
Host smart-6646d380-53d2-4dc2-a917-647c865108f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476661862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2476661862
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1241380103
Short name T360
Test name
Test status
Simulation time 1869665936 ps
CPU time 7.53 seconds
Started Jun 10 05:23:39 PM PDT 24
Finished Jun 10 05:23:47 PM PDT 24
Peak memory 218044 kb
Host smart-0f206eeb-f1f0-4e80-8b19-a0cc7c20038f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241380103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1241380103
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.387561031
Short name T506
Test name
Test status
Simulation time 244579917 ps
CPU time 1.11 seconds
Started Jun 10 05:23:37 PM PDT 24
Finished Jun 10 05:23:39 PM PDT 24
Peak memory 217564 kb
Host smart-b1a2b2e0-7649-4576-ba8e-0563388281c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387561031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.387561031
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3084609223
Short name T275
Test name
Test status
Simulation time 198232012 ps
CPU time 0.91 seconds
Started Jun 10 05:23:32 PM PDT 24
Finished Jun 10 05:23:33 PM PDT 24
Peak memory 200184 kb
Host smart-f850e95e-3ec2-4b14-8ff3-1d80cf53ce86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084609223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3084609223
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3862549982
Short name T518
Test name
Test status
Simulation time 1581791456 ps
CPU time 5.51 seconds
Started Jun 10 05:23:32 PM PDT 24
Finished Jun 10 05:23:38 PM PDT 24
Peak memory 200540 kb
Host smart-05a509e6-146c-44be-ba46-2259997806dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862549982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3862549982
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1909131237
Short name T499
Test name
Test status
Simulation time 102818985 ps
CPU time 1.04 seconds
Started Jun 10 05:23:34 PM PDT 24
Finished Jun 10 05:23:35 PM PDT 24
Peak memory 200360 kb
Host smart-b1691670-870a-428d-aa10-efc103fb6348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909131237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1909131237
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.1916047274
Short name T373
Test name
Test status
Simulation time 248400403 ps
CPU time 1.51 seconds
Started Jun 10 05:23:32 PM PDT 24
Finished Jun 10 05:23:34 PM PDT 24
Peak memory 200552 kb
Host smart-d44091aa-9972-4d73-ab72-c863fcffec0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916047274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1916047274
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2268789623
Short name T92
Test name
Test status
Simulation time 2214378272 ps
CPU time 8.04 seconds
Started Jun 10 05:23:36 PM PDT 24
Finished Jun 10 05:23:44 PM PDT 24
Peak memory 200748 kb
Host smart-cb73a54d-1533-4357-91b1-6e2a64b3472c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268789623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2268789623
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.3695260002
Short name T466
Test name
Test status
Simulation time 111078794 ps
CPU time 1.45 seconds
Started Jun 10 05:23:38 PM PDT 24
Finished Jun 10 05:23:39 PM PDT 24
Peak memory 200364 kb
Host smart-b87c7888-e658-476c-ac7e-105ae0c44663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695260002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3695260002
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2037838087
Short name T178
Test name
Test status
Simulation time 179232381 ps
CPU time 1.15 seconds
Started Jun 10 05:23:39 PM PDT 24
Finished Jun 10 05:23:40 PM PDT 24
Peak memory 200364 kb
Host smart-4e83faf5-7c6f-4d3a-b0a6-4c01337a3ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037838087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2037838087
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.620775049
Short name T220
Test name
Test status
Simulation time 58563057 ps
CPU time 0.69 seconds
Started Jun 10 05:23:54 PM PDT 24
Finished Jun 10 05:23:55 PM PDT 24
Peak memory 200104 kb
Host smart-5af650dc-2026-4485-bbb6-b106a139b417
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620775049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.620775049
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.4254387853
Short name T49
Test name
Test status
Simulation time 2370336563 ps
CPU time 8.17 seconds
Started Jun 10 05:23:36 PM PDT 24
Finished Jun 10 05:23:44 PM PDT 24
Peak memory 218012 kb
Host smart-c8fa038b-bda7-40dc-8d5f-6a3369651fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254387853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.4254387853
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2275671319
Short name T147
Test name
Test status
Simulation time 244583529 ps
CPU time 1.05 seconds
Started Jun 10 05:23:38 PM PDT 24
Finished Jun 10 05:23:39 PM PDT 24
Peak memory 217604 kb
Host smart-7251cfc2-36c8-49d3-9f9a-5ad2b088e12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275671319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2275671319
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1856754465
Short name T15
Test name
Test status
Simulation time 194110834 ps
CPU time 0.99 seconds
Started Jun 10 05:23:54 PM PDT 24
Finished Jun 10 05:23:56 PM PDT 24
Peak memory 199976 kb
Host smart-fef793c3-b98c-459c-b3a7-5ab9665411b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856754465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1856754465
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.1787559527
Short name T224
Test name
Test status
Simulation time 1382579287 ps
CPU time 5.3 seconds
Started Jun 10 05:23:35 PM PDT 24
Finished Jun 10 05:23:41 PM PDT 24
Peak memory 200560 kb
Host smart-59490a98-c13d-4dcf-a737-88e87d61b49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787559527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.1787559527
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3139294815
Short name T271
Test name
Test status
Simulation time 106984166 ps
CPU time 0.99 seconds
Started Jun 10 05:23:45 PM PDT 24
Finished Jun 10 05:23:47 PM PDT 24
Peak memory 200248 kb
Host smart-d427c2d4-0f58-4a9a-b8c7-5b427fa3ea7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139294815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3139294815
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3053179472
Short name T533
Test name
Test status
Simulation time 248333924 ps
CPU time 1.59 seconds
Started Jun 10 05:23:37 PM PDT 24
Finished Jun 10 05:23:39 PM PDT 24
Peak memory 200620 kb
Host smart-16e2c954-370a-44a1-a1f4-be5750c2bd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053179472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3053179472
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.754862388
Short name T211
Test name
Test status
Simulation time 4269058963 ps
CPU time 15.71 seconds
Started Jun 10 05:23:34 PM PDT 24
Finished Jun 10 05:23:50 PM PDT 24
Peak memory 210380 kb
Host smart-431cb420-8d7b-4b78-9782-2dad47c38e88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754862388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.754862388
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1599369496
Short name T368
Test name
Test status
Simulation time 147566513 ps
CPU time 1.92 seconds
Started Jun 10 05:23:37 PM PDT 24
Finished Jun 10 05:23:39 PM PDT 24
Peak memory 200320 kb
Host smart-c0c35177-20e7-49b7-a108-9c96b07b9dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599369496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1599369496
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3250819973
Short name T295
Test name
Test status
Simulation time 125773703 ps
CPU time 1.11 seconds
Started Jun 10 05:23:34 PM PDT 24
Finished Jun 10 05:23:36 PM PDT 24
Peak memory 200348 kb
Host smart-208684be-62e1-4a21-a923-ab0d8c2e472b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250819973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3250819973
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3316182791
Short name T277
Test name
Test status
Simulation time 76525364 ps
CPU time 0.78 seconds
Started Jun 10 05:23:33 PM PDT 24
Finished Jun 10 05:23:34 PM PDT 24
Peak memory 200312 kb
Host smart-c2f2cb93-8a04-4c33-896b-d69c7496a96d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316182791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3316182791
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.927284425
Short name T470
Test name
Test status
Simulation time 244081438 ps
CPU time 1.07 seconds
Started Jun 10 05:23:54 PM PDT 24
Finished Jun 10 05:23:55 PM PDT 24
Peak memory 217496 kb
Host smart-833eb9dc-f4d6-43e0-b969-75fc159d6240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927284425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.927284425
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.507730166
Short name T253
Test name
Test status
Simulation time 231245279 ps
CPU time 0.95 seconds
Started Jun 10 05:23:34 PM PDT 24
Finished Jun 10 05:23:35 PM PDT 24
Peak memory 200180 kb
Host smart-b43b5bb9-8799-4234-8a2a-34bea4a81b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507730166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.507730166
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.4092637081
Short name T479
Test name
Test status
Simulation time 1377543964 ps
CPU time 5.85 seconds
Started Jun 10 05:23:35 PM PDT 24
Finished Jun 10 05:23:41 PM PDT 24
Peak memory 200468 kb
Host smart-12d7ee94-7ec6-4c82-8f14-cc49c831d779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092637081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.4092637081
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3654707495
Short name T138
Test name
Test status
Simulation time 151703747 ps
CPU time 1.17 seconds
Started Jun 10 05:23:39 PM PDT 24
Finished Jun 10 05:23:40 PM PDT 24
Peak memory 200384 kb
Host smart-b6d9ba09-15d4-4ecc-89ab-1701e369bb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654707495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3654707495
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3126895861
Short name T209
Test name
Test status
Simulation time 225203152 ps
CPU time 1.53 seconds
Started Jun 10 05:23:37 PM PDT 24
Finished Jun 10 05:23:39 PM PDT 24
Peak memory 200664 kb
Host smart-e92fcde6-1cba-4678-9003-b1eb72cc8402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126895861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3126895861
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2666658583
Short name T151
Test name
Test status
Simulation time 267074836 ps
CPU time 1.61 seconds
Started Jun 10 05:23:35 PM PDT 24
Finished Jun 10 05:23:37 PM PDT 24
Peak memory 200444 kb
Host smart-13f89d7b-18e3-4e4a-8820-36ffd4aac551
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666658583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2666658583
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3249969923
Short name T511
Test name
Test status
Simulation time 110403699 ps
CPU time 1.42 seconds
Started Jun 10 05:23:40 PM PDT 24
Finished Jun 10 05:23:42 PM PDT 24
Peak memory 200412 kb
Host smart-2cfe1e63-2a59-40de-9365-ce40266cd318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249969923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3249969923
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3082376431
Short name T531
Test name
Test status
Simulation time 135647843 ps
CPU time 1.11 seconds
Started Jun 10 05:23:36 PM PDT 24
Finished Jun 10 05:23:37 PM PDT 24
Peak memory 200348 kb
Host smart-70b74864-4ce8-4c1f-9499-fedd0fa95995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082376431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3082376431
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.283982803
Short name T536
Test name
Test status
Simulation time 68037667 ps
CPU time 0.8 seconds
Started Jun 10 05:23:40 PM PDT 24
Finished Jun 10 05:23:42 PM PDT 24
Peak memory 200168 kb
Host smart-b5a20b24-2d75-4f26-b51d-51e6e2d0bee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283982803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.283982803
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1552846098
Short name T69
Test name
Test status
Simulation time 1899748407 ps
CPU time 7.01 seconds
Started Jun 10 05:23:43 PM PDT 24
Finished Jun 10 05:23:51 PM PDT 24
Peak memory 217968 kb
Host smart-c4b07a99-deea-4c55-ab26-8310de96e5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552846098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1552846098
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2061913245
Short name T327
Test name
Test status
Simulation time 243665242 ps
CPU time 1.09 seconds
Started Jun 10 05:23:39 PM PDT 24
Finished Jun 10 05:23:41 PM PDT 24
Peak memory 217608 kb
Host smart-7960e00b-bd1a-456f-8c78-003c5f79b059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061913245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2061913245
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.605229934
Short name T321
Test name
Test status
Simulation time 134189914 ps
CPU time 0.88 seconds
Started Jun 10 05:23:43 PM PDT 24
Finished Jun 10 05:23:44 PM PDT 24
Peak memory 200136 kb
Host smart-d1265c3d-1ee2-4247-88fb-1ac47f13b1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605229934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.605229934
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1568973379
Short name T111
Test name
Test status
Simulation time 1550825493 ps
CPU time 5.55 seconds
Started Jun 10 05:23:55 PM PDT 24
Finished Jun 10 05:24:01 PM PDT 24
Peak memory 200544 kb
Host smart-ab3d9e09-a23b-4ee8-a87c-01b895f82aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568973379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1568973379
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2010980394
Short name T308
Test name
Test status
Simulation time 176653745 ps
CPU time 1.25 seconds
Started Jun 10 05:23:54 PM PDT 24
Finished Jun 10 05:23:56 PM PDT 24
Peak memory 200316 kb
Host smart-27c58b07-e11d-4211-a31e-f97101d2e227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010980394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2010980394
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1298751946
Short name T502
Test name
Test status
Simulation time 259453748 ps
CPU time 1.47 seconds
Started Jun 10 05:23:45 PM PDT 24
Finished Jun 10 05:23:46 PM PDT 24
Peak memory 200524 kb
Host smart-23a867e2-eadf-4bb8-a351-926927e1dc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298751946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1298751946
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3957719224
Short name T94
Test name
Test status
Simulation time 5009870309 ps
CPU time 17.79 seconds
Started Jun 10 05:23:44 PM PDT 24
Finished Jun 10 05:24:02 PM PDT 24
Peak memory 200628 kb
Host smart-21408c25-ec45-4439-ba61-de639fcb52c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957719224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3957719224
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3467828939
Short name T524
Test name
Test status
Simulation time 383484852 ps
CPU time 2.58 seconds
Started Jun 10 05:23:43 PM PDT 24
Finished Jun 10 05:23:46 PM PDT 24
Peak memory 200380 kb
Host smart-e5c77ecc-8ff1-42f9-852f-e8f550446b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467828939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3467828939
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1396515423
Short name T214
Test name
Test status
Simulation time 144739470 ps
CPU time 1.17 seconds
Started Jun 10 05:23:43 PM PDT 24
Finished Jun 10 05:23:44 PM PDT 24
Peak memory 200304 kb
Host smart-78b9ee7d-d5c4-4654-990c-1b51c6edb6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396515423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1396515423
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.4266857093
Short name T243
Test name
Test status
Simulation time 60063650 ps
CPU time 0.82 seconds
Started Jun 10 05:23:40 PM PDT 24
Finished Jun 10 05:23:41 PM PDT 24
Peak memory 200180 kb
Host smart-5f8f35e3-6b66-4dc9-9fa8-009a7f43c756
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266857093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.4266857093
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1580720799
Short name T414
Test name
Test status
Simulation time 2352751762 ps
CPU time 8.34 seconds
Started Jun 10 05:23:42 PM PDT 24
Finished Jun 10 05:23:50 PM PDT 24
Peak memory 218148 kb
Host smart-8d48718d-4912-4d27-8aac-9aa07aeb3674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580720799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1580720799
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.77968769
Short name T164
Test name
Test status
Simulation time 243999763 ps
CPU time 1.17 seconds
Started Jun 10 05:23:44 PM PDT 24
Finished Jun 10 05:23:45 PM PDT 24
Peak memory 217580 kb
Host smart-9e40834e-e946-4263-b806-0b734afea38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77968769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.77968769
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.1615629177
Short name T317
Test name
Test status
Simulation time 170910838 ps
CPU time 0.88 seconds
Started Jun 10 05:23:46 PM PDT 24
Finished Jun 10 05:23:48 PM PDT 24
Peak memory 200176 kb
Host smart-b2281065-84d4-4a7b-a83e-caf52c87bf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615629177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1615629177
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3231915232
Short name T540
Test name
Test status
Simulation time 886785434 ps
CPU time 4.76 seconds
Started Jun 10 05:23:43 PM PDT 24
Finished Jun 10 05:23:48 PM PDT 24
Peak memory 200488 kb
Host smart-d6b513f1-abc6-4c15-89cb-21f18f1ad2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231915232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3231915232
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.46810537
Short name T408
Test name
Test status
Simulation time 96281952 ps
CPU time 0.98 seconds
Started Jun 10 05:23:42 PM PDT 24
Finished Jun 10 05:23:43 PM PDT 24
Peak memory 200392 kb
Host smart-578a3486-578d-49f0-aa6c-ec3c8902fdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46810537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.46810537
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1871584896
Short name T227
Test name
Test status
Simulation time 189246467 ps
CPU time 1.3 seconds
Started Jun 10 05:23:42 PM PDT 24
Finished Jun 10 05:23:44 PM PDT 24
Peak memory 200596 kb
Host smart-236d5acd-d91f-4c45-accf-dc6ade8084dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871584896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1871584896
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2160471090
Short name T396
Test name
Test status
Simulation time 1204589673 ps
CPU time 4.97 seconds
Started Jun 10 05:23:42 PM PDT 24
Finished Jun 10 05:23:47 PM PDT 24
Peak memory 200560 kb
Host smart-df136a6c-83ca-486c-8af2-8d04a829da21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160471090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2160471090
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3583547463
Short name T256
Test name
Test status
Simulation time 461748464 ps
CPU time 2.7 seconds
Started Jun 10 05:23:41 PM PDT 24
Finished Jun 10 05:23:44 PM PDT 24
Peak memory 200404 kb
Host smart-7f1107e0-5e61-4535-9cdb-5a5f512e125b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583547463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3583547463
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2012432645
Short name T231
Test name
Test status
Simulation time 170908575 ps
CPU time 1.36 seconds
Started Jun 10 05:23:41 PM PDT 24
Finished Jun 10 05:23:43 PM PDT 24
Peak memory 200524 kb
Host smart-cf2b7932-730c-4d2c-bce6-016326a2aab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012432645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2012432645
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3209175007
Short name T41
Test name
Test status
Simulation time 69653625 ps
CPU time 0.79 seconds
Started Jun 10 05:23:41 PM PDT 24
Finished Jun 10 05:23:42 PM PDT 24
Peak memory 200204 kb
Host smart-15e4ede4-e814-4da2-991b-897468775f29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209175007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3209175007
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.330108568
Short name T26
Test name
Test status
Simulation time 2356724076 ps
CPU time 8.14 seconds
Started Jun 10 05:23:43 PM PDT 24
Finished Jun 10 05:23:51 PM PDT 24
Peak memory 217912 kb
Host smart-ed01525a-e9ca-4147-b1b8-9508400dbbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330108568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.330108568
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2624011307
Short name T217
Test name
Test status
Simulation time 244415603 ps
CPU time 1.07 seconds
Started Jun 10 05:23:45 PM PDT 24
Finished Jun 10 05:23:47 PM PDT 24
Peak memory 217580 kb
Host smart-9d517143-1760-42dd-adb4-f6acfa2b67fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624011307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2624011307
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.840152233
Short name T2
Test name
Test status
Simulation time 158744256 ps
CPU time 0.96 seconds
Started Jun 10 05:23:44 PM PDT 24
Finished Jun 10 05:23:45 PM PDT 24
Peak memory 200180 kb
Host smart-1563d68d-6641-41c9-9b19-82e3717dccc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840152233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.840152233
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.3264537829
Short name T348
Test name
Test status
Simulation time 1300201089 ps
CPU time 5.58 seconds
Started Jun 10 05:23:55 PM PDT 24
Finished Jun 10 05:24:01 PM PDT 24
Peak memory 200504 kb
Host smart-be1ad2ea-e8c3-47a5-a12c-96206dfd0d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264537829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3264537829
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.4255405697
Short name T196
Test name
Test status
Simulation time 151781246 ps
CPU time 1.12 seconds
Started Jun 10 05:23:54 PM PDT 24
Finished Jun 10 05:23:56 PM PDT 24
Peak memory 200116 kb
Host smart-7a458db2-194c-49d3-add6-54e26d382605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255405697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.4255405697
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1423666365
Short name T265
Test name
Test status
Simulation time 124622088 ps
CPU time 1.19 seconds
Started Jun 10 05:23:42 PM PDT 24
Finished Jun 10 05:23:43 PM PDT 24
Peak memory 200568 kb
Host smart-7fab3749-b55f-4e18-8d0d-0c2098b9e59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423666365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1423666365
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.472909416
Short name T96
Test name
Test status
Simulation time 2366668837 ps
CPU time 11.71 seconds
Started Jun 10 05:23:45 PM PDT 24
Finished Jun 10 05:23:57 PM PDT 24
Peak memory 208880 kb
Host smart-659cd81b-b5fe-4649-a6b2-7e2c8efee6b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472909416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.472909416
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1581704878
Short name T320
Test name
Test status
Simulation time 136532512 ps
CPU time 1.71 seconds
Started Jun 10 05:23:42 PM PDT 24
Finished Jun 10 05:23:44 PM PDT 24
Peak memory 200380 kb
Host smart-8cd38a61-4353-4df7-867d-6e3d76be4471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581704878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1581704878
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.359251407
Short name T273
Test name
Test status
Simulation time 103326432 ps
CPU time 1.04 seconds
Started Jun 10 05:23:44 PM PDT 24
Finished Jun 10 05:23:46 PM PDT 24
Peak memory 200396 kb
Host smart-7b130037-c7d6-4901-8e50-a54b26895b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359251407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.359251407
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.1740875175
Short name T398
Test name
Test status
Simulation time 73607704 ps
CPU time 0.77 seconds
Started Jun 10 05:23:55 PM PDT 24
Finished Jun 10 05:23:56 PM PDT 24
Peak memory 200136 kb
Host smart-a3f92bf0-dca1-4e0a-8f62-2914ed35834f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740875175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1740875175
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.2985141138
Short name T495
Test name
Test status
Simulation time 1216754281 ps
CPU time 5.54 seconds
Started Jun 10 05:23:49 PM PDT 24
Finished Jun 10 05:23:55 PM PDT 24
Peak memory 217072 kb
Host smart-54298e46-d534-424c-8763-a0233c0768ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985141138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2985141138
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2247905956
Short name T6
Test name
Test status
Simulation time 245581175 ps
CPU time 1.02 seconds
Started Jun 10 05:23:54 PM PDT 24
Finished Jun 10 05:23:56 PM PDT 24
Peak memory 217552 kb
Host smart-017e4c2e-d8e7-4cd6-8e0d-6b8c58c6f80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247905956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2247905956
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.4086490552
Short name T16
Test name
Test status
Simulation time 221040104 ps
CPU time 0.98 seconds
Started Jun 10 05:23:44 PM PDT 24
Finished Jun 10 05:23:45 PM PDT 24
Peak memory 200164 kb
Host smart-1ae46f2d-2795-4e9c-87c5-9d900bb7aa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086490552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.4086490552
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2116360275
Short name T478
Test name
Test status
Simulation time 835957938 ps
CPU time 4.47 seconds
Started Jun 10 05:23:40 PM PDT 24
Finished Jun 10 05:23:45 PM PDT 24
Peak memory 200464 kb
Host smart-ece16340-ece8-4a56-99c3-d9b7fecdde94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116360275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2116360275
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3990733237
Short name T516
Test name
Test status
Simulation time 147873613 ps
CPU time 1.19 seconds
Started Jun 10 05:23:45 PM PDT 24
Finished Jun 10 05:23:46 PM PDT 24
Peak memory 200348 kb
Host smart-e46e1be9-4b1f-4a7f-af4e-8ebf0bd31ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990733237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3990733237
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.2627452442
Short name T50
Test name
Test status
Simulation time 123484387 ps
CPU time 1.23 seconds
Started Jun 10 05:23:54 PM PDT 24
Finished Jun 10 05:23:56 PM PDT 24
Peak memory 200504 kb
Host smart-486605f6-3d69-453f-b75a-7812983fd65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627452442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2627452442
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.815064380
Short name T521
Test name
Test status
Simulation time 5092530491 ps
CPU time 16.65 seconds
Started Jun 10 05:23:41 PM PDT 24
Finished Jun 10 05:23:58 PM PDT 24
Peak memory 209740 kb
Host smart-e06c071c-1e97-48ca-9518-0815ec26afce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815064380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.815064380
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3056879200
Short name T459
Test name
Test status
Simulation time 380867859 ps
CPU time 2.58 seconds
Started Jun 10 05:23:46 PM PDT 24
Finished Jun 10 05:23:49 PM PDT 24
Peak memory 200368 kb
Host smart-64657958-cd94-4b0f-9745-33258357a104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056879200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3056879200
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.26381893
Short name T53
Test name
Test status
Simulation time 52650273 ps
CPU time 0.71 seconds
Started Jun 10 05:23:49 PM PDT 24
Finished Jun 10 05:23:51 PM PDT 24
Peak memory 200184 kb
Host smart-7d9a78cf-aed3-4a28-ac39-879231156731
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26381893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.26381893
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2430740711
Short name T44
Test name
Test status
Simulation time 1884674749 ps
CPU time 8.09 seconds
Started Jun 10 05:23:44 PM PDT 24
Finished Jun 10 05:23:53 PM PDT 24
Peak memory 217952 kb
Host smart-f190833f-3386-4ef2-bd2e-e1cd3c3b68a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430740711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2430740711
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1936699233
Short name T489
Test name
Test status
Simulation time 245237199 ps
CPU time 1.01 seconds
Started Jun 10 05:23:48 PM PDT 24
Finished Jun 10 05:23:50 PM PDT 24
Peak memory 217604 kb
Host smart-dd347567-e991-4ab7-aa39-4cca69cbc6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936699233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1936699233
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2662394854
Short name T18
Test name
Test status
Simulation time 213081228 ps
CPU time 1 seconds
Started Jun 10 05:23:42 PM PDT 24
Finished Jun 10 05:23:43 PM PDT 24
Peak memory 200152 kb
Host smart-d2aa2660-59c5-45c1-b81f-b1326a361149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662394854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2662394854
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.4212405571
Short name T259
Test name
Test status
Simulation time 1518800525 ps
CPU time 5.83 seconds
Started Jun 10 05:23:41 PM PDT 24
Finished Jun 10 05:23:48 PM PDT 24
Peak memory 200592 kb
Host smart-ae14c12a-ca86-422c-9adc-2f88bb88006b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212405571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.4212405571
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.707902456
Short name T419
Test name
Test status
Simulation time 96200157 ps
CPU time 1.02 seconds
Started Jun 10 05:23:46 PM PDT 24
Finished Jun 10 05:23:47 PM PDT 24
Peak memory 200364 kb
Host smart-4b84ba1a-4f57-4837-8e89-d74722916f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707902456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.707902456
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.457470393
Short name T380
Test name
Test status
Simulation time 115449788 ps
CPU time 1.17 seconds
Started Jun 10 05:23:41 PM PDT 24
Finished Jun 10 05:23:42 PM PDT 24
Peak memory 200524 kb
Host smart-55d5da10-e5da-40cb-b5ef-592b5e9eebd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457470393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.457470393
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1709360264
Short name T51
Test name
Test status
Simulation time 3812854056 ps
CPU time 14.05 seconds
Started Jun 10 05:23:47 PM PDT 24
Finished Jun 10 05:24:02 PM PDT 24
Peak memory 200736 kb
Host smart-489951c9-f544-424d-b8f4-84216b127455
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709360264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1709360264
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3819331639
Short name T280
Test name
Test status
Simulation time 285580167 ps
CPU time 1.91 seconds
Started Jun 10 05:23:45 PM PDT 24
Finished Jun 10 05:23:48 PM PDT 24
Peak memory 200316 kb
Host smart-6d206426-1ce1-4eea-87a0-19d7ac676b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819331639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3819331639
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.805232669
Short name T288
Test name
Test status
Simulation time 148205402 ps
CPU time 1.1 seconds
Started Jun 10 05:23:46 PM PDT 24
Finished Jun 10 05:23:47 PM PDT 24
Peak memory 200352 kb
Host smart-01fd21ba-ef2f-4aaa-8f69-0e718674183a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805232669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.805232669
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3620536397
Short name T91
Test name
Test status
Simulation time 61079919 ps
CPU time 0.76 seconds
Started Jun 10 05:23:45 PM PDT 24
Finished Jun 10 05:23:46 PM PDT 24
Peak memory 200168 kb
Host smart-4f68c134-9d86-4ad8-8585-e4769b04a3af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620536397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3620536397
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2718184921
Short name T344
Test name
Test status
Simulation time 1231995635 ps
CPU time 5.48 seconds
Started Jun 10 05:23:44 PM PDT 24
Finished Jun 10 05:23:49 PM PDT 24
Peak memory 218000 kb
Host smart-cd6b81d9-8dce-4c43-ba4d-72d6778ea70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718184921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2718184921
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.772728557
Short name T297
Test name
Test status
Simulation time 247458779 ps
CPU time 1.05 seconds
Started Jun 10 05:23:48 PM PDT 24
Finished Jun 10 05:23:49 PM PDT 24
Peak memory 217580 kb
Host smart-1d9316f1-7114-440e-b96a-bee1fa99f875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772728557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.772728557
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.297581100
Short name T159
Test name
Test status
Simulation time 116822342 ps
CPU time 0.87 seconds
Started Jun 10 05:23:48 PM PDT 24
Finished Jun 10 05:23:49 PM PDT 24
Peak memory 200184 kb
Host smart-379296c1-eb80-411f-aae3-1a71da1b0f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297581100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.297581100
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3309842387
Short name T172
Test name
Test status
Simulation time 912250411 ps
CPU time 5.03 seconds
Started Jun 10 05:23:46 PM PDT 24
Finished Jun 10 05:23:51 PM PDT 24
Peak memory 200540 kb
Host smart-a6959531-6ed1-4813-a6c5-8b1ca52c81ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309842387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3309842387
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1730277957
Short name T235
Test name
Test status
Simulation time 103522450 ps
CPU time 1.05 seconds
Started Jun 10 05:23:44 PM PDT 24
Finished Jun 10 05:23:46 PM PDT 24
Peak memory 200500 kb
Host smart-4e41b57c-c71d-46a0-b5b0-0743b8c0376e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730277957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1730277957
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.738355458
Short name T213
Test name
Test status
Simulation time 110203303 ps
CPU time 1.17 seconds
Started Jun 10 05:23:45 PM PDT 24
Finished Jun 10 05:23:47 PM PDT 24
Peak memory 200524 kb
Host smart-e63c5067-bc0a-4357-a446-cb1c548b5c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738355458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.738355458
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2134805887
Short name T400
Test name
Test status
Simulation time 3702861384 ps
CPU time 15.07 seconds
Started Jun 10 05:23:46 PM PDT 24
Finished Jun 10 05:24:01 PM PDT 24
Peak memory 200628 kb
Host smart-e0e3129b-b9d2-482e-8d6e-36e76a5b1947
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134805887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2134805887
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3654773857
Short name T480
Test name
Test status
Simulation time 280323330 ps
CPU time 1.96 seconds
Started Jun 10 05:23:44 PM PDT 24
Finished Jun 10 05:23:47 PM PDT 24
Peak memory 200356 kb
Host smart-b699b8b7-89c7-49d1-b054-2bfc9f02d89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654773857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3654773857
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.895083855
Short name T474
Test name
Test status
Simulation time 98944973 ps
CPU time 0.97 seconds
Started Jun 10 05:23:48 PM PDT 24
Finished Jun 10 05:23:49 PM PDT 24
Peak memory 200328 kb
Host smart-362b18da-ce23-46c6-b827-19d2bc3772ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895083855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.895083855
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2468304735
Short name T240
Test name
Test status
Simulation time 72664990 ps
CPU time 0.76 seconds
Started Jun 10 05:23:46 PM PDT 24
Finished Jun 10 05:23:47 PM PDT 24
Peak memory 200160 kb
Host smart-0e666467-fa8b-495f-858e-8fb6ebe5d8d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468304735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2468304735
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1356178033
Short name T306
Test name
Test status
Simulation time 1894592971 ps
CPU time 7.17 seconds
Started Jun 10 05:23:44 PM PDT 24
Finished Jun 10 05:23:52 PM PDT 24
Peak memory 217960 kb
Host smart-11937af8-e12d-490b-aad2-ebd947a7f7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356178033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1356178033
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2295678933
Short name T24
Test name
Test status
Simulation time 244149473 ps
CPU time 1.14 seconds
Started Jun 10 05:23:45 PM PDT 24
Finished Jun 10 05:23:47 PM PDT 24
Peak memory 217620 kb
Host smart-a8e6e8ec-abe6-400b-903d-f828282e391b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295678933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2295678933
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2347873038
Short name T301
Test name
Test status
Simulation time 107358988 ps
CPU time 0.79 seconds
Started Jun 10 05:23:47 PM PDT 24
Finished Jun 10 05:23:48 PM PDT 24
Peak memory 200144 kb
Host smart-809f5089-e2bf-48c3-821f-3958be5a33d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347873038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2347873038
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2178289577
Short name T367
Test name
Test status
Simulation time 890613597 ps
CPU time 4.33 seconds
Started Jun 10 05:23:51 PM PDT 24
Finished Jun 10 05:23:56 PM PDT 24
Peak memory 200468 kb
Host smart-81940083-ac63-439d-8bf2-48d2b9382355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178289577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2178289577
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.428122690
Short name T238
Test name
Test status
Simulation time 98689100 ps
CPU time 1.03 seconds
Started Jun 10 05:23:47 PM PDT 24
Finished Jun 10 05:23:49 PM PDT 24
Peak memory 200368 kb
Host smart-69bd3d0f-b3bc-4679-b618-d610e255ee42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428122690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.428122690
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.4085480753
Short name T491
Test name
Test status
Simulation time 247070666 ps
CPU time 1.46 seconds
Started Jun 10 05:23:46 PM PDT 24
Finished Jun 10 05:23:48 PM PDT 24
Peak memory 200520 kb
Host smart-4fb6254c-a251-45d9-8727-3f910aaff948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085480753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.4085480753
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1378048326
Short name T90
Test name
Test status
Simulation time 7801850407 ps
CPU time 30.36 seconds
Started Jun 10 05:23:46 PM PDT 24
Finished Jun 10 05:24:17 PM PDT 24
Peak memory 200736 kb
Host smart-27736973-9cdd-4ca9-be31-ee1b08c7e0de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378048326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1378048326
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.371115447
Short name T176
Test name
Test status
Simulation time 473084917 ps
CPU time 2.71 seconds
Started Jun 10 05:23:46 PM PDT 24
Finished Jun 10 05:23:49 PM PDT 24
Peak memory 200340 kb
Host smart-9c07f63d-d8a9-433e-82fd-204ef19cd9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371115447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.371115447
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.148886737
Short name T514
Test name
Test status
Simulation time 90065078 ps
CPU time 0.85 seconds
Started Jun 10 05:23:51 PM PDT 24
Finished Jun 10 05:23:52 PM PDT 24
Peak memory 200268 kb
Host smart-c23397db-c8b7-4a29-8c3d-658e6854910d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148886737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.148886737
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3280713675
Short name T319
Test name
Test status
Simulation time 60164529 ps
CPU time 0.74 seconds
Started Jun 10 05:22:38 PM PDT 24
Finished Jun 10 05:22:39 PM PDT 24
Peak memory 200144 kb
Host smart-2c072c4b-4f6b-4b25-a298-bb872a1d6280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280713675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3280713675
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3559809680
Short name T89
Test name
Test status
Simulation time 243122154 ps
CPU time 1.14 seconds
Started Jun 10 05:22:31 PM PDT 24
Finished Jun 10 05:22:32 PM PDT 24
Peak memory 217488 kb
Host smart-968aed8c-8b68-4e5a-92a0-9dbabf3532e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559809680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3559809680
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.2397954631
Short name T4
Test name
Test status
Simulation time 167578639 ps
CPU time 0.9 seconds
Started Jun 10 05:22:32 PM PDT 24
Finished Jun 10 05:22:34 PM PDT 24
Peak memory 200224 kb
Host smart-5d3e285e-46a3-4d8e-8ff2-409200608c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397954631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2397954631
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.52053676
Short name T174
Test name
Test status
Simulation time 1635791431 ps
CPU time 7.19 seconds
Started Jun 10 05:22:36 PM PDT 24
Finished Jun 10 05:22:43 PM PDT 24
Peak memory 200456 kb
Host smart-5287f46c-d678-4c1d-841e-8c7108509db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52053676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.52053676
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1877627236
Short name T56
Test name
Test status
Simulation time 141541629 ps
CPU time 1.13 seconds
Started Jun 10 05:22:35 PM PDT 24
Finished Jun 10 05:22:37 PM PDT 24
Peak memory 200396 kb
Host smart-212f94d5-298d-4a97-9050-6e85cf7f9236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877627236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1877627236
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1812686323
Short name T420
Test name
Test status
Simulation time 191414041 ps
CPU time 1.49 seconds
Started Jun 10 05:22:31 PM PDT 24
Finished Jun 10 05:22:33 PM PDT 24
Peak memory 200508 kb
Host smart-cf9726a9-9de1-4b36-b0b0-b61ff53c0901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812686323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1812686323
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1484785256
Short name T291
Test name
Test status
Simulation time 3531143964 ps
CPU time 16.8 seconds
Started Jun 10 05:22:36 PM PDT 24
Finished Jun 10 05:22:53 PM PDT 24
Peak memory 208812 kb
Host smart-c022b907-63f6-4165-b7e4-bb09aa078869
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484785256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1484785256
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1191121574
Short name T186
Test name
Test status
Simulation time 433367074 ps
CPU time 2.58 seconds
Started Jun 10 05:22:32 PM PDT 24
Finished Jun 10 05:22:35 PM PDT 24
Peak memory 200336 kb
Host smart-cd2fdeb4-68c7-4f25-855e-4e6a8e874a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191121574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1191121574
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1043138343
Short name T187
Test name
Test status
Simulation time 114654574 ps
CPU time 1.01 seconds
Started Jun 10 05:22:36 PM PDT 24
Finished Jun 10 05:22:38 PM PDT 24
Peak memory 200376 kb
Host smart-d969bc7c-f611-4105-9b3b-03d4c62d4dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043138343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1043138343
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3523004208
Short name T296
Test name
Test status
Simulation time 83331095 ps
CPU time 0.83 seconds
Started Jun 10 05:22:32 PM PDT 24
Finished Jun 10 05:22:33 PM PDT 24
Peak memory 200200 kb
Host smart-00f27e48-10d2-451b-93ed-0293c21abf6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523004208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3523004208
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.959426619
Short name T519
Test name
Test status
Simulation time 1233036402 ps
CPU time 5.88 seconds
Started Jun 10 05:22:36 PM PDT 24
Finished Jun 10 05:22:43 PM PDT 24
Peak memory 217572 kb
Host smart-f8fd3c41-2141-4e7f-bf43-156b0a659424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959426619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.959426619
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2922480297
Short name T457
Test name
Test status
Simulation time 245025928 ps
CPU time 1.09 seconds
Started Jun 10 05:22:32 PM PDT 24
Finished Jun 10 05:22:33 PM PDT 24
Peak memory 217628 kb
Host smart-c15d4e63-1812-4fa3-9091-b415b7c209cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922480297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2922480297
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3224555187
Short name T330
Test name
Test status
Simulation time 123826581 ps
CPU time 0.82 seconds
Started Jun 10 05:22:32 PM PDT 24
Finished Jun 10 05:22:34 PM PDT 24
Peak memory 200084 kb
Host smart-db1aa2f1-7957-4c9a-83f8-47188eb82be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224555187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3224555187
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.676133482
Short name T188
Test name
Test status
Simulation time 878626313 ps
CPU time 4.81 seconds
Started Jun 10 05:22:35 PM PDT 24
Finished Jun 10 05:22:40 PM PDT 24
Peak memory 200460 kb
Host smart-18aada61-c64e-497e-af58-f0bab3463d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676133482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.676133482
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2938142715
Short name T143
Test name
Test status
Simulation time 144243213 ps
CPU time 1.13 seconds
Started Jun 10 05:22:33 PM PDT 24
Finished Jun 10 05:22:34 PM PDT 24
Peak memory 200292 kb
Host smart-2acb6a25-647a-4584-9b5a-787b56afb08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938142715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2938142715
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.4250346310
Short name T8
Test name
Test status
Simulation time 187198661 ps
CPU time 1.37 seconds
Started Jun 10 05:22:35 PM PDT 24
Finished Jun 10 05:22:37 PM PDT 24
Peak memory 200520 kb
Host smart-2377ea47-c18f-4dfb-9c34-9aff407f61d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250346310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.4250346310
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1341314989
Short name T357
Test name
Test status
Simulation time 156029844 ps
CPU time 1.88 seconds
Started Jun 10 05:22:38 PM PDT 24
Finished Jun 10 05:22:40 PM PDT 24
Peak memory 200320 kb
Host smart-afebb738-4135-4104-bea3-24d79d061382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341314989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1341314989
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3441333276
Short name T54
Test name
Test status
Simulation time 164273056 ps
CPU time 1.19 seconds
Started Jun 10 05:22:32 PM PDT 24
Finished Jun 10 05:22:34 PM PDT 24
Peak memory 200364 kb
Host smart-f49048c1-df2d-4c9c-89a1-351b3b286206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441333276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3441333276
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.128413186
Short name T85
Test name
Test status
Simulation time 71120859 ps
CPU time 0.79 seconds
Started Jun 10 05:22:38 PM PDT 24
Finished Jun 10 05:22:39 PM PDT 24
Peak memory 200180 kb
Host smart-0e5118f9-ced3-4396-a9fb-2995fd456ab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128413186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.128413186
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2845067835
Short name T35
Test name
Test status
Simulation time 1883536537 ps
CPU time 7.68 seconds
Started Jun 10 05:22:40 PM PDT 24
Finished Jun 10 05:22:48 PM PDT 24
Peak memory 217632 kb
Host smart-6a6d50c2-07c9-4d80-a276-c5c0c80c00c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845067835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2845067835
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3752004581
Short name T248
Test name
Test status
Simulation time 244206296 ps
CPU time 1.07 seconds
Started Jun 10 05:22:38 PM PDT 24
Finished Jun 10 05:22:40 PM PDT 24
Peak memory 217500 kb
Host smart-1626fc80-c137-465c-a17e-69e2b9c18ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752004581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3752004581
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1607685590
Short name T266
Test name
Test status
Simulation time 129903605 ps
CPU time 0.87 seconds
Started Jun 10 05:22:31 PM PDT 24
Finished Jun 10 05:22:33 PM PDT 24
Peak memory 200084 kb
Host smart-7ceaa58c-811a-4f91-ba35-473db1337d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607685590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1607685590
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3462525322
Short name T22
Test name
Test status
Simulation time 965325152 ps
CPU time 4.83 seconds
Started Jun 10 05:22:38 PM PDT 24
Finished Jun 10 05:22:43 PM PDT 24
Peak memory 200512 kb
Host smart-90b2ee71-3d87-4ba7-ac39-5698af61376e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462525322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3462525322
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.78731659
Short name T157
Test name
Test status
Simulation time 100658544 ps
CPU time 1.05 seconds
Started Jun 10 05:22:39 PM PDT 24
Finished Jun 10 05:22:40 PM PDT 24
Peak memory 200332 kb
Host smart-1b348519-3566-4dda-9334-8cd66651745f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78731659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.78731659
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.1130012189
Short name T473
Test name
Test status
Simulation time 118359952 ps
CPU time 1.17 seconds
Started Jun 10 05:22:34 PM PDT 24
Finished Jun 10 05:22:35 PM PDT 24
Peak memory 200472 kb
Host smart-d2ba7853-b201-4092-b943-1b6fde21ca7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130012189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.1130012189
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2397035349
Short name T421
Test name
Test status
Simulation time 1023251083 ps
CPU time 5.05 seconds
Started Jun 10 05:22:38 PM PDT 24
Finished Jun 10 05:22:43 PM PDT 24
Peak memory 200552 kb
Host smart-c1c4d4b7-2b6e-46ea-81cb-b700252f7488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397035349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2397035349
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.896545594
Short name T156
Test name
Test status
Simulation time 128372256 ps
CPU time 1.53 seconds
Started Jun 10 05:22:36 PM PDT 24
Finished Jun 10 05:22:38 PM PDT 24
Peak memory 200268 kb
Host smart-e8b59a00-9763-4600-af6f-379c5251876a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896545594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.896545594
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3722073814
Short name T427
Test name
Test status
Simulation time 266166645 ps
CPU time 1.57 seconds
Started Jun 10 05:22:32 PM PDT 24
Finished Jun 10 05:22:34 PM PDT 24
Peak memory 200496 kb
Host smart-471aced1-a146-4b28-9ee4-705687fc5b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722073814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3722073814
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.307084186
Short name T60
Test name
Test status
Simulation time 62105967 ps
CPU time 0.76 seconds
Started Jun 10 05:22:39 PM PDT 24
Finished Jun 10 05:22:40 PM PDT 24
Peak memory 200180 kb
Host smart-ac7a3995-6a80-4de5-b9c6-32ac55902697
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307084186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.307084186
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.572395953
Short name T425
Test name
Test status
Simulation time 2359260668 ps
CPU time 8.06 seconds
Started Jun 10 05:22:41 PM PDT 24
Finished Jun 10 05:22:49 PM PDT 24
Peak memory 217860 kb
Host smart-fca93b27-4727-4e44-b0e0-aff23d623ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572395953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.572395953
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.828334389
Short name T437
Test name
Test status
Simulation time 243705200 ps
CPU time 1.15 seconds
Started Jun 10 05:22:39 PM PDT 24
Finished Jun 10 05:22:40 PM PDT 24
Peak memory 217548 kb
Host smart-9fa8e673-a8ee-4cc2-afa8-39c6b498f2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828334389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.828334389
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3524683493
Short name T201
Test name
Test status
Simulation time 215906521 ps
CPU time 0.96 seconds
Started Jun 10 05:22:42 PM PDT 24
Finished Jun 10 05:22:43 PM PDT 24
Peak memory 200164 kb
Host smart-f5a99ae3-2db4-4ca0-8cc1-f8f5be811e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524683493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3524683493
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.1978872310
Short name T300
Test name
Test status
Simulation time 949078844 ps
CPU time 4.66 seconds
Started Jun 10 05:22:37 PM PDT 24
Finished Jun 10 05:22:42 PM PDT 24
Peak memory 200556 kb
Host smart-3eedf65c-14e5-4823-b239-9be73d53f294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978872310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1978872310
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3620573314
Short name T376
Test name
Test status
Simulation time 149908485 ps
CPU time 1.11 seconds
Started Jun 10 05:22:37 PM PDT 24
Finished Jun 10 05:22:39 PM PDT 24
Peak memory 200412 kb
Host smart-104132ef-431c-46fc-b3c1-b2f4ba33ca2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620573314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3620573314
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3751976989
Short name T193
Test name
Test status
Simulation time 119998281 ps
CPU time 1.2 seconds
Started Jun 10 05:22:38 PM PDT 24
Finished Jun 10 05:22:40 PM PDT 24
Peak memory 200516 kb
Host smart-42cf554f-3980-42ab-a5af-0c65735a13bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751976989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3751976989
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.4193382546
Short name T458
Test name
Test status
Simulation time 4642742241 ps
CPU time 20.64 seconds
Started Jun 10 05:22:38 PM PDT 24
Finished Jun 10 05:22:59 PM PDT 24
Peak memory 208896 kb
Host smart-f3a289a2-2e12-4435-b047-1524a353bd58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193382546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.4193382546
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3286079873
Short name T199
Test name
Test status
Simulation time 420372994 ps
CPU time 2.35 seconds
Started Jun 10 05:22:38 PM PDT 24
Finished Jun 10 05:22:41 PM PDT 24
Peak memory 208544 kb
Host smart-4eb61b03-1e4f-48bc-b30c-8b4f9efde4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286079873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3286079873
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.3592050202
Short name T136
Test name
Test status
Simulation time 62871875 ps
CPU time 0.76 seconds
Started Jun 10 05:22:40 PM PDT 24
Finished Jun 10 05:22:41 PM PDT 24
Peak memory 200364 kb
Host smart-14124828-88b5-461c-a681-2d135d37b409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592050202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3592050202
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2129705553
Short name T165
Test name
Test status
Simulation time 96371198 ps
CPU time 0.8 seconds
Started Jun 10 05:22:44 PM PDT 24
Finished Jun 10 05:22:45 PM PDT 24
Peak memory 200164 kb
Host smart-5e41a32e-4f59-4c93-8a53-906bd8946575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129705553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2129705553
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1723368895
Short name T397
Test name
Test status
Simulation time 1229577094 ps
CPU time 5.7 seconds
Started Jun 10 05:22:37 PM PDT 24
Finished Jun 10 05:22:43 PM PDT 24
Peak memory 217960 kb
Host smart-d8931bf9-62d4-4146-bb6f-ace6b0e62d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723368895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1723368895
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1138118790
Short name T263
Test name
Test status
Simulation time 243774745 ps
CPU time 1.08 seconds
Started Jun 10 05:22:41 PM PDT 24
Finished Jun 10 05:22:43 PM PDT 24
Peak memory 217580 kb
Host smart-1517f9f8-d5aa-4bd7-afe0-0b5c9db0c059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138118790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1138118790
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.177287696
Short name T534
Test name
Test status
Simulation time 123777491 ps
CPU time 0.79 seconds
Started Jun 10 05:22:41 PM PDT 24
Finished Jun 10 05:22:42 PM PDT 24
Peak memory 200180 kb
Host smart-1524413f-005b-4cdb-ab28-4331bdb94fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177287696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.177287696
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.228823594
Short name T249
Test name
Test status
Simulation time 1405914925 ps
CPU time 5.04 seconds
Started Jun 10 05:22:40 PM PDT 24
Finished Jun 10 05:22:45 PM PDT 24
Peak memory 200564 kb
Host smart-bc9922b8-577a-4967-913f-6cfa79043414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228823594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.228823594
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.74226903
Short name T406
Test name
Test status
Simulation time 108984159 ps
CPU time 1.07 seconds
Started Jun 10 05:22:37 PM PDT 24
Finished Jun 10 05:22:39 PM PDT 24
Peak memory 200352 kb
Host smart-19077888-94e4-4a8b-9ed3-9111e115e382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74226903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.74226903
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.608958748
Short name T145
Test name
Test status
Simulation time 128945658 ps
CPU time 1.22 seconds
Started Jun 10 05:22:37 PM PDT 24
Finished Jun 10 05:22:38 PM PDT 24
Peak memory 200508 kb
Host smart-96e6f436-9e24-403b-9291-51fea3d2f267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608958748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.608958748
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3726226771
Short name T177
Test name
Test status
Simulation time 639786264 ps
CPU time 2.99 seconds
Started Jun 10 05:22:45 PM PDT 24
Finished Jun 10 05:22:48 PM PDT 24
Peak memory 200388 kb
Host smart-56acc706-f186-4f57-9c0f-b0bb4133eaed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726226771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3726226771
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3018066098
Short name T440
Test name
Test status
Simulation time 406871872 ps
CPU time 2.25 seconds
Started Jun 10 05:22:38 PM PDT 24
Finished Jun 10 05:22:41 PM PDT 24
Peak memory 208704 kb
Host smart-650cbb93-a067-4b6d-8d54-7d0a931e72dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018066098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3018066098
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2477791300
Short name T442
Test name
Test status
Simulation time 173029467 ps
CPU time 1.33 seconds
Started Jun 10 05:22:38 PM PDT 24
Finished Jun 10 05:22:40 PM PDT 24
Peak memory 200560 kb
Host smart-0f81ccd9-dbc2-4e2d-8206-4d68db803fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477791300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2477791300
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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