Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7797

1

T4

17

T6

21

T8

5

auto[1]

10480

1

T1

4

T3

4

T4

84

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5703	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6174	1			T1	2		T2	1		T3	2
reset_info_cp[2]	2776	1			T1	1		T3	1		T4	17
reset_info_cp[4]	3688	1			T1	1		T3	1		T4	17
reset_info_cp[8]	118	1			T4	1		T91	1		T57	1
reset_info_cp[16]	110	1			T4	1		T6	1		T12	1
reset_info_cp[32]	98	1			T4	1		T25	1		T91	2
reset_info_cp[64]	109	1			T31	1		T91	1		T42	1
reset_info_cp[128]	120	1			T4	1		T25	1		T56	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2975	1			T4	17		T6	4		T31	19
reset_info_cp[1]	auto[1]	2580	1			T1	1		T3	1		T4	9
reset_info_cp[2]	auto[0]	870	1			T6	1		T25	4		T56	6
reset_info_cp[2]	auto[1]	1906	1			T1	1		T3	1		T4	17
reset_info_cp[4]	auto[0]	1347	1			T6	7		T25	7		T56	6
reset_info_cp[4]	auto[1]	2341	1			T1	1		T3	1		T4	17
reset_info_cp[8]	auto[0]	43	1			T91	1		T58	3		T108	1
reset_info_cp[8]	auto[1]	75	1			T4	1		T57	1		T42	1
reset_info_cp[16]	auto[0]	48	1			T6	1		T56	2		T91	1
reset_info_cp[16]	auto[1]	62	1			T4	1		T12	1		T28	1
reset_info_cp[32]	auto[0]	43	1			T91	2		T57	1		T141	1
reset_info_cp[32]	auto[1]	55	1			T4	1		T25	1		T57	1
reset_info_cp[64]	auto[0]	47	1			T91	1		T84	1		T104	1
reset_info_cp[64]	auto[1]	62	1			T31	1		T42	1		T32	1
reset_info_cp[128]	auto[0]	40	1			T25	1		T56	1		T57	1
reset_info_cp[128]	auto[1]	80	1			T4	1		T42	1		T32	1