Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 619
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T538 /workspace/coverage/default/30.rstmgr_smoke.932501064 Jun 11 12:24:17 PM PDT 24 Jun 11 12:24:20 PM PDT 24 197247823 ps
T539 /workspace/coverage/default/36.rstmgr_sw_rst.1389424328 Jun 11 12:24:44 PM PDT 24 Jun 11 12:24:48 PM PDT 24 111868323 ps
T540 /workspace/coverage/default/45.rstmgr_stress_all.2439064851 Jun 11 12:25:07 PM PDT 24 Jun 11 12:25:47 PM PDT 24 10405327138 ps
T541 /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2095943744 Jun 11 12:23:46 PM PDT 24 Jun 11 12:23:55 PM PDT 24 247860818 ps
T71 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1498272344 Jun 11 12:22:08 PM PDT 24 Jun 11 12:22:12 PM PDT 24 109163182 ps
T72 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1277286957 Jun 11 12:23:42 PM PDT 24 Jun 11 12:23:46 PM PDT 24 91314857 ps
T73 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2412875507 Jun 11 12:23:42 PM PDT 24 Jun 11 12:23:48 PM PDT 24 980747787 ps
T74 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2209897779 Jun 11 12:20:41 PM PDT 24 Jun 11 12:20:52 PM PDT 24 2282597981 ps
T75 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.4247202659 Jun 11 12:22:10 PM PDT 24 Jun 11 12:22:14 PM PDT 24 472192080 ps
T76 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3565292798 Jun 11 12:23:46 PM PDT 24 Jun 11 12:23:55 PM PDT 24 239288591 ps
T542 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1183973696 Jun 11 12:22:24 PM PDT 24 Jun 11 12:22:27 PM PDT 24 100416374 ps
T118 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.148119955 Jun 11 12:19:14 PM PDT 24 Jun 11 12:19:15 PM PDT 24 80367819 ps
T97 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1180651306 Jun 11 12:22:51 PM PDT 24 Jun 11 12:22:54 PM PDT 24 99867199 ps
T98 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1534237702 Jun 11 12:21:49 PM PDT 24 Jun 11 12:21:51 PM PDT 24 131904231 ps
T543 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.954000644 Jun 11 12:22:31 PM PDT 24 Jun 11 12:22:36 PM PDT 24 115531178 ps
T77 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1444184784 Jun 11 12:22:08 PM PDT 24 Jun 11 12:22:13 PM PDT 24 236734485 ps
T99 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1297552964 Jun 11 12:22:27 PM PDT 24 Jun 11 12:22:29 PM PDT 24 181735070 ps
T100 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3725407948 Jun 11 12:18:03 PM PDT 24 Jun 11 12:18:06 PM PDT 24 466574063 ps
T101 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.240743099 Jun 11 12:22:30 PM PDT 24 Jun 11 12:22:37 PM PDT 24 461246726 ps
T544 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3902989092 Jun 11 12:22:57 PM PDT 24 Jun 11 12:23:01 PM PDT 24 91777325 ps
T119 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3239575599 Jun 11 12:19:53 PM PDT 24 Jun 11 12:19:56 PM PDT 24 108577228 ps
T120 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.927419664 Jun 11 12:22:54 PM PDT 24 Jun 11 12:22:56 PM PDT 24 59576375 ps
T129 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3216283816 Jun 11 12:22:51 PM PDT 24 Jun 11 12:22:56 PM PDT 24 928615785 ps
T102 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1034347175 Jun 11 12:22:56 PM PDT 24 Jun 11 12:23:01 PM PDT 24 120196083 ps
T545 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.220362562 Jun 11 12:22:43 PM PDT 24 Jun 11 12:22:46 PM PDT 24 99779929 ps
T103 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2752611061 Jun 11 12:22:53 PM PDT 24 Jun 11 12:22:58 PM PDT 24 858159477 ps
T546 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.69470386 Jun 11 12:22:39 PM PDT 24 Jun 11 12:22:42 PM PDT 24 111695866 ps
T547 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.965871527 Jun 11 12:22:48 PM PDT 24 Jun 11 12:22:52 PM PDT 24 83706628 ps
T127 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.505714830 Jun 11 12:22:30 PM PDT 24 Jun 11 12:22:35 PM PDT 24 184290831 ps
T145 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.260687044 Jun 11 12:22:51 PM PDT 24 Jun 11 12:22:54 PM PDT 24 468866219 ps
T548 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.214329040 Jun 11 12:17:08 PM PDT 24 Jun 11 12:17:12 PM PDT 24 353446360 ps
T549 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.458091582 Jun 11 12:20:41 PM PDT 24 Jun 11 12:20:44 PM PDT 24 164155855 ps
T128 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1702289434 Jun 11 12:20:42 PM PDT 24 Jun 11 12:20:46 PM PDT 24 184152021 ps
T550 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3027057918 Jun 11 12:22:56 PM PDT 24 Jun 11 12:23:01 PM PDT 24 165250449 ps
T121 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3127212273 Jun 11 12:22:32 PM PDT 24 Jun 11 12:22:37 PM PDT 24 73998857 ps
T106 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.15728905 Jun 11 12:22:41 PM PDT 24 Jun 11 12:22:45 PM PDT 24 63369411 ps
T551 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1055810686 Jun 11 12:17:57 PM PDT 24 Jun 11 12:18:00 PM PDT 24 408990981 ps
T122 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2554943446 Jun 11 12:22:29 PM PDT 24 Jun 11 12:22:34 PM PDT 24 84658505 ps
T138 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2505065309 Jun 11 12:23:22 PM PDT 24 Jun 11 12:23:27 PM PDT 24 96278242 ps
T136 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.4153866340 Jun 11 12:22:27 PM PDT 24 Jun 11 12:22:30 PM PDT 24 104121626 ps
T123 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.702840503 Jun 11 12:22:29 PM PDT 24 Jun 11 12:22:34 PM PDT 24 284039836 ps
T124 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.419788960 Jun 11 12:22:43 PM PDT 24 Jun 11 12:22:47 PM PDT 24 120206648 ps
T552 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.687861251 Jun 11 12:22:59 PM PDT 24 Jun 11 12:23:05 PM PDT 24 125147223 ps
T130 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2080984142 Jun 11 12:19:56 PM PDT 24 Jun 11 12:20:00 PM PDT 24 778119273 ps
T553 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.220082948 Jun 11 12:22:26 PM PDT 24 Jun 11 12:22:33 PM PDT 24 476705312 ps
T131 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.562091387 Jun 11 12:21:27 PM PDT 24 Jun 11 12:21:31 PM PDT 24 868877384 ps
T125 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1476220231 Jun 11 12:22:50 PM PDT 24 Jun 11 12:22:53 PM PDT 24 73480835 ps
T554 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.284622542 Jun 11 12:21:28 PM PDT 24 Jun 11 12:21:30 PM PDT 24 195897649 ps
T555 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3075447533 Jun 11 12:22:40 PM PDT 24 Jun 11 12:22:44 PM PDT 24 195706094 ps
T137 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1972497112 Jun 11 12:22:57 PM PDT 24 Jun 11 12:23:04 PM PDT 24 488863136 ps
T556 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3327957181 Jun 11 12:22:57 PM PDT 24 Jun 11 12:23:02 PM PDT 24 147732448 ps
T557 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3471958532 Jun 11 12:20:56 PM PDT 24 Jun 11 12:20:58 PM PDT 24 179489748 ps
T126 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1665378135 Jun 11 12:20:05 PM PDT 24 Jun 11 12:20:06 PM PDT 24 123361789 ps
T133 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1303920441 Jun 11 12:22:49 PM PDT 24 Jun 11 12:22:54 PM PDT 24 938031720 ps
T558 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1345799368 Jun 11 12:22:48 PM PDT 24 Jun 11 12:22:51 PM PDT 24 121737030 ps
T559 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3062014622 Jun 11 12:23:26 PM PDT 24 Jun 11 12:23:32 PM PDT 24 236290344 ps
T560 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2978836162 Jun 11 12:20:43 PM PDT 24 Jun 11 12:20:45 PM PDT 24 177274217 ps
T135 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3172224695 Jun 11 12:22:54 PM PDT 24 Jun 11 12:23:00 PM PDT 24 1105071934 ps
T561 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3221539259 Jun 11 12:19:39 PM PDT 24 Jun 11 12:19:41 PM PDT 24 86778338 ps
T562 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2363129020 Jun 11 12:19:50 PM PDT 24 Jun 11 12:19:55 PM PDT 24 955738953 ps
T563 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.759109992 Jun 11 12:22:42 PM PDT 24 Jun 11 12:22:53 PM PDT 24 2286544434 ps
T564 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.836409965 Jun 11 12:22:57 PM PDT 24 Jun 11 12:23:03 PM PDT 24 179985350 ps
T565 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.497468578 Jun 11 12:22:25 PM PDT 24 Jun 11 12:22:28 PM PDT 24 121611638 ps
T566 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.4218594367 Jun 11 12:22:49 PM PDT 24 Jun 11 12:22:53 PM PDT 24 191037594 ps
T567 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1811704615 Jun 11 12:20:42 PM PDT 24 Jun 11 12:20:44 PM PDT 24 92490759 ps
T568 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2261480742 Jun 11 12:22:40 PM PDT 24 Jun 11 12:22:45 PM PDT 24 948905810 ps
T569 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3785814398 Jun 11 12:23:26 PM PDT 24 Jun 11 12:23:32 PM PDT 24 122785079 ps
T570 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.210396657 Jun 11 12:23:19 PM PDT 24 Jun 11 12:23:22 PM PDT 24 154823497 ps
T571 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3396331282 Jun 11 12:22:57 PM PDT 24 Jun 11 12:23:04 PM PDT 24 884786796 ps
T572 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2667307513 Jun 11 12:17:59 PM PDT 24 Jun 11 12:18:01 PM PDT 24 144326227 ps
T573 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2854381792 Jun 11 12:22:40 PM PDT 24 Jun 11 12:22:43 PM PDT 24 110748459 ps
T134 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2725866234 Jun 11 12:23:38 PM PDT 24 Jun 11 12:23:44 PM PDT 24 840172072 ps
T574 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2024699588 Jun 11 12:22:42 PM PDT 24 Jun 11 12:22:46 PM PDT 24 256691504 ps
T575 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.407764090 Jun 11 12:19:54 PM PDT 24 Jun 11 12:19:57 PM PDT 24 265000147 ps
T576 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2589737636 Jun 11 12:22:55 PM PDT 24 Jun 11 12:23:03 PM PDT 24 1176125348 ps
T577 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.970415383 Jun 11 12:23:23 PM PDT 24 Jun 11 12:23:27 PM PDT 24 149360306 ps
T578 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1464457132 Jun 11 12:23:38 PM PDT 24 Jun 11 12:23:43 PM PDT 24 205119780 ps
T579 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.462372785 Jun 11 12:20:41 PM PDT 24 Jun 11 12:20:43 PM PDT 24 128830611 ps
T580 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.172167771 Jun 11 12:19:52 PM PDT 24 Jun 11 12:19:55 PM PDT 24 69745942 ps
T581 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.342136567 Jun 11 12:22:26 PM PDT 24 Jun 11 12:22:28 PM PDT 24 83703570 ps
T582 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.887580974 Jun 11 12:22:40 PM PDT 24 Jun 11 12:22:44 PM PDT 24 269150913 ps
T583 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.844650837 Jun 11 12:23:42 PM PDT 24 Jun 11 12:23:47 PM PDT 24 69688961 ps
T584 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3624627338 Jun 11 12:22:31 PM PDT 24 Jun 11 12:22:36 PM PDT 24 101781840 ps
T132 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3374480455 Jun 11 12:18:43 PM PDT 24 Jun 11 12:18:46 PM PDT 24 429375389 ps
T585 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1360489293 Jun 11 12:22:29 PM PDT 24 Jun 11 12:22:33 PM PDT 24 167939600 ps
T586 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3179259153 Jun 11 12:22:26 PM PDT 24 Jun 11 12:22:29 PM PDT 24 479911872 ps
T587 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3857316144 Jun 11 12:22:11 PM PDT 24 Jun 11 12:22:15 PM PDT 24 195489554 ps
T588 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.82039006 Jun 11 12:22:48 PM PDT 24 Jun 11 12:22:52 PM PDT 24 157406692 ps
T589 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2966601445 Jun 11 12:18:39 PM PDT 24 Jun 11 12:18:41 PM PDT 24 61441973 ps
T590 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3886780294 Jun 11 12:19:51 PM PDT 24 Jun 11 12:19:54 PM PDT 24 109782510 ps
T591 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.683417273 Jun 11 12:22:30 PM PDT 24 Jun 11 12:22:34 PM PDT 24 102449912 ps
T592 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1918412796 Jun 11 12:18:20 PM PDT 24 Jun 11 12:18:22 PM PDT 24 150993461 ps
T593 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2741821998 Jun 11 12:23:11 PM PDT 24 Jun 11 12:23:13 PM PDT 24 74988956 ps
T594 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3211194382 Jun 11 12:22:53 PM PDT 24 Jun 11 12:22:57 PM PDT 24 123371089 ps
T595 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2896123237 Jun 11 12:17:14 PM PDT 24 Jun 11 12:17:18 PM PDT 24 876117590 ps
T596 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.634187605 Jun 11 12:22:09 PM PDT 24 Jun 11 12:22:12 PM PDT 24 96702025 ps
T597 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1535184722 Jun 11 12:22:29 PM PDT 24 Jun 11 12:22:35 PM PDT 24 909112689 ps
T598 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2442754303 Jun 11 12:22:10 PM PDT 24 Jun 11 12:22:13 PM PDT 24 145123659 ps
T599 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.674915200 Jun 11 12:22:56 PM PDT 24 Jun 11 12:23:00 PM PDT 24 80280940 ps
T600 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.151381344 Jun 11 12:22:59 PM PDT 24 Jun 11 12:23:05 PM PDT 24 177323102 ps
T601 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.4211197170 Jun 11 12:23:17 PM PDT 24 Jun 11 12:23:19 PM PDT 24 55579645 ps
T602 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.990993539 Jun 11 12:22:41 PM PDT 24 Jun 11 12:22:44 PM PDT 24 69196633 ps
T603 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1705431089 Jun 11 12:20:17 PM PDT 24 Jun 11 12:20:19 PM PDT 24 107691131 ps
T604 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1971434124 Jun 11 12:17:57 PM PDT 24 Jun 11 12:17:59 PM PDT 24 75365185 ps
T605 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.279944265 Jun 11 12:23:12 PM PDT 24 Jun 11 12:23:14 PM PDT 24 186357305 ps
T606 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1315442849 Jun 11 12:22:32 PM PDT 24 Jun 11 12:22:38 PM PDT 24 216491463 ps
T607 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3281572335 Jun 11 12:23:23 PM PDT 24 Jun 11 12:23:27 PM PDT 24 108614542 ps
T608 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1866287796 Jun 11 12:22:56 PM PDT 24 Jun 11 12:23:00 PM PDT 24 60370911 ps
T609 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3500466011 Jun 11 12:21:34 PM PDT 24 Jun 11 12:21:36 PM PDT 24 73652725 ps
T610 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.4110230683 Jun 11 12:22:31 PM PDT 24 Jun 11 12:22:37 PM PDT 24 76332262 ps
T611 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1198385451 Jun 11 12:23:19 PM PDT 24 Jun 11 12:23:22 PM PDT 24 131038458 ps
T612 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2110726153 Jun 11 12:22:56 PM PDT 24 Jun 11 12:23:03 PM PDT 24 433332346 ps
T613 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.244447678 Jun 11 12:23:40 PM PDT 24 Jun 11 12:23:43 PM PDT 24 89155737 ps
T614 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.4237349715 Jun 11 12:22:11 PM PDT 24 Jun 11 12:22:14 PM PDT 24 525197159 ps
T615 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2492200571 Jun 11 12:22:42 PM PDT 24 Jun 11 12:22:46 PM PDT 24 64784116 ps
T616 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.808965571 Jun 11 12:22:52 PM PDT 24 Jun 11 12:22:54 PM PDT 24 126398983 ps
T617 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.80159211 Jun 11 12:22:30 PM PDT 24 Jun 11 12:22:34 PM PDT 24 83453673 ps
T618 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1938647650 Jun 11 12:19:40 PM PDT 24 Jun 11 12:19:45 PM PDT 24 793459990 ps
T619 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2831973129 Jun 11 12:22:26 PM PDT 24 Jun 11 12:22:28 PM PDT 24 206459086 ps

Test location /workspace/coverage/default/28.rstmgr_reset.3680127428
Short name T6
Test name
Test status
Simulation time 720613441 ps
CPU time 3.56 seconds
Started Jun 11 12:24:04 PM PDT 24
Finished Jun 11 12:24:10 PM PDT 24
Peak memory 200476 kb
Host smart-1427f887-b4c7-45a8-abc6-e88447e39a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680127428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3680127428
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.4027985496
Short name T57
Test name
Test status
Simulation time 6433491790 ps
CPU time 28.96 seconds
Started Jun 11 12:24:41 PM PDT 24
Finished Jun 11 12:25:11 PM PDT 24
Peak memory 208816 kb
Host smart-87286494-5a25-4fd5-a0b5-8d128b6999d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027985496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.4027985496
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.740057520
Short name T48
Test name
Test status
Simulation time 325653132 ps
CPU time 1.86 seconds
Started Jun 11 12:24:40 PM PDT 24
Finished Jun 11 12:24:43 PM PDT 24
Peak memory 200300 kb
Host smart-10eba0cf-e574-4a6e-9ca2-1cf218272d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740057520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.740057520
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1498272344
Short name T71
Test name
Test status
Simulation time 109163182 ps
CPU time 1.14 seconds
Started Jun 11 12:22:08 PM PDT 24
Finished Jun 11 12:22:12 PM PDT 24
Peak memory 206820 kb
Host smart-043d7206-d582-45ed-b4d9-3b694eb4f474
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498272344 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1498272344
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.585318654
Short name T79
Test name
Test status
Simulation time 17078084643 ps
CPU time 26.4 seconds
Started Jun 11 12:23:20 PM PDT 24
Finished Jun 11 12:23:50 PM PDT 24
Peak memory 217224 kb
Host smart-b45c89f0-82f3-4106-a087-5a7339223779
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585318654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.585318654
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2113361920
Short name T42
Test name
Test status
Simulation time 1222545426 ps
CPU time 5.41 seconds
Started Jun 11 12:23:43 PM PDT 24
Finished Jun 11 12:23:53 PM PDT 24
Peak memory 221856 kb
Host smart-b9a1f9bd-1aa0-4ec0-ae5d-45311309b31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113361920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2113361920
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2412875507
Short name T73
Test name
Test status
Simulation time 980747787 ps
CPU time 2.97 seconds
Started Jun 11 12:23:42 PM PDT 24
Finished Jun 11 12:23:48 PM PDT 24
Peak memory 200488 kb
Host smart-27762766-8920-46d9-817f-4ef0556fd298
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412875507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2412875507
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.1244773284
Short name T9
Test name
Test status
Simulation time 81164195 ps
CPU time 0.86 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:22:43 PM PDT 24
Peak memory 198512 kb
Host smart-512d46a8-3514-40e6-9c69-54b5bc83af63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244773284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1244773284
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3572368011
Short name T91
Test name
Test status
Simulation time 220824359 ps
CPU time 1.26 seconds
Started Jun 11 12:24:21 PM PDT 24
Finished Jun 11 12:24:23 PM PDT 24
Peak memory 200204 kb
Host smart-20826908-baef-4dc7-aab0-8fcc041d530c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572368011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3572368011
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.14576855
Short name T49
Test name
Test status
Simulation time 103910222 ps
CPU time 0.98 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:23:00 PM PDT 24
Peak memory 200000 kb
Host smart-c3ec7343-b2cf-45fe-b96e-1f1d3012d216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14576855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.14576855
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1534237702
Short name T98
Test name
Test status
Simulation time 131904231 ps
CPU time 1.85 seconds
Started Jun 11 12:21:49 PM PDT 24
Finished Jun 11 12:21:51 PM PDT 24
Peak memory 216808 kb
Host smart-4dbffdcb-778b-48bd-855b-64a1a28585cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534237702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1534237702
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2152269754
Short name T33
Test name
Test status
Simulation time 2353388397 ps
CPU time 8.5 seconds
Started Jun 11 12:24:23 PM PDT 24
Finished Jun 11 12:24:33 PM PDT 24
Peak memory 218076 kb
Host smart-8657fcaf-d24a-471f-b6e7-b754057ed97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152269754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2152269754
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2615732967
Short name T113
Test name
Test status
Simulation time 1661078641 ps
CPU time 5.95 seconds
Started Jun 11 12:22:55 PM PDT 24
Finished Jun 11 12:23:04 PM PDT 24
Peak memory 200096 kb
Host smart-e0b19c55-fef3-49ee-acc4-bbdebcfff9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615732967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2615732967
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3327957181
Short name T556
Test name
Test status
Simulation time 147732448 ps
CPU time 2.02 seconds
Started Jun 11 12:22:57 PM PDT 24
Finished Jun 11 12:23:02 PM PDT 24
Peak memory 208360 kb
Host smart-ba9c79d9-9d72-4f3f-93cc-5f3f801429e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327957181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3327957181
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3569096690
Short name T60
Test name
Test status
Simulation time 1892961308 ps
CPU time 7.19 seconds
Started Jun 11 12:23:48 PM PDT 24
Finished Jun 11 12:24:03 PM PDT 24
Peak memory 221548 kb
Host smart-2b1785de-e8f6-4825-8ee3-a55fbb568b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569096690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3569096690
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2080984142
Short name T130
Test name
Test status
Simulation time 778119273 ps
CPU time 2.78 seconds
Started Jun 11 12:19:56 PM PDT 24
Finished Jun 11 12:20:00 PM PDT 24
Peak memory 200484 kb
Host smart-3fcfaecf-a3d6-4904-9c60-580362b1aed2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080984142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2080984142
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1665378135
Short name T126
Test name
Test status
Simulation time 123361789 ps
CPU time 1.06 seconds
Started Jun 11 12:20:05 PM PDT 24
Finished Jun 11 12:20:06 PM PDT 24
Peak memory 200144 kb
Host smart-bb59a2a2-df24-40fa-80a1-6679a2dc5e66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665378135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1665378135
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2852099127
Short name T14
Test name
Test status
Simulation time 161497878 ps
CPU time 0.79 seconds
Started Jun 11 12:23:46 PM PDT 24
Finished Jun 11 12:23:55 PM PDT 24
Peak memory 200140 kb
Host smart-cf4f04f9-dca0-4eb0-832c-f24e1497ecd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852099127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2852099127
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2752611061
Short name T103
Test name
Test status
Simulation time 858159477 ps
CPU time 2.83 seconds
Started Jun 11 12:22:53 PM PDT 24
Finished Jun 11 12:22:58 PM PDT 24
Peak memory 200044 kb
Host smart-53b167ab-edd2-4433-bbd9-0703dbdb5a81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752611061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2752611061
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2704677095
Short name T182
Test name
Test status
Simulation time 152414505 ps
CPU time 1.35 seconds
Started Jun 11 12:23:49 PM PDT 24
Finished Jun 11 12:23:58 PM PDT 24
Peak memory 200216 kb
Host smart-2a6aab30-c03d-406c-b39d-dfae18478b9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704677095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2704677095
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1183973696
Short name T542
Test name
Test status
Simulation time 100416374 ps
CPU time 1.36 seconds
Started Jun 11 12:22:24 PM PDT 24
Finished Jun 11 12:22:27 PM PDT 24
Peak memory 199508 kb
Host smart-7d5d0abd-066d-4317-990b-a2cee9804031
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183973696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.1
183973696
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.220082948
Short name T553
Test name
Test status
Simulation time 476705312 ps
CPU time 5.59 seconds
Started Jun 11 12:22:26 PM PDT 24
Finished Jun 11 12:22:33 PM PDT 24
Peak memory 200016 kb
Host smart-4fff7c7c-60ba-4f33-bec7-55dc7cd7f7c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220082948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.220082948
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3221539259
Short name T561
Test name
Test status
Simulation time 86778338 ps
CPU time 0.83 seconds
Started Jun 11 12:19:39 PM PDT 24
Finished Jun 11 12:19:41 PM PDT 24
Peak memory 200164 kb
Host smart-bc8a0384-a7d7-4eba-a305-01cb7e106028
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221539259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
221539259
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1297552964
Short name T99
Test name
Test status
Simulation time 181735070 ps
CPU time 1.19 seconds
Started Jun 11 12:22:27 PM PDT 24
Finished Jun 11 12:22:29 PM PDT 24
Peak memory 200228 kb
Host smart-a4daab50-75ea-422b-8047-f31852d99804
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297552964 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1297552964
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.342136567
Short name T581
Test name
Test status
Simulation time 83703570 ps
CPU time 0.8 seconds
Started Jun 11 12:22:26 PM PDT 24
Finished Jun 11 12:22:28 PM PDT 24
Peak memory 199740 kb
Host smart-3967a453-7388-4cab-b404-46a262b0b993
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342136567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.342136567
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.4153866340
Short name T136
Test name
Test status
Simulation time 104121626 ps
CPU time 1.35 seconds
Started Jun 11 12:22:27 PM PDT 24
Finished Jun 11 12:22:30 PM PDT 24
Peak memory 210096 kb
Host smart-9e57b1d1-66e6-44ec-92e3-81f4b6f1d77c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153866340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.4153866340
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.214329040
Short name T548
Test name
Test status
Simulation time 353446360 ps
CPU time 2.47 seconds
Started Jun 11 12:17:08 PM PDT 24
Finished Jun 11 12:17:12 PM PDT 24
Peak memory 200720 kb
Host smart-d9add326-61cb-4269-ac99-984425dd51bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214329040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.214329040
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2589737636
Short name T576
Test name
Test status
Simulation time 1176125348 ps
CPU time 4.96 seconds
Started Jun 11 12:22:55 PM PDT 24
Finished Jun 11 12:23:03 PM PDT 24
Peak memory 200260 kb
Host smart-1a1ea7bf-6a7e-4bc0-974c-7e1134353451
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589737636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
589737636
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.954000644
Short name T543
Test name
Test status
Simulation time 115531178 ps
CPU time 0.87 seconds
Started Jun 11 12:22:31 PM PDT 24
Finished Jun 11 12:22:36 PM PDT 24
Peak memory 199888 kb
Host smart-c2c82742-4ba2-4325-8001-205b47d0f605
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954000644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.954000644
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1315442849
Short name T606
Test name
Test status
Simulation time 216491463 ps
CPU time 1.42 seconds
Started Jun 11 12:22:32 PM PDT 24
Finished Jun 11 12:22:38 PM PDT 24
Peak memory 208180 kb
Host smart-d2a9e4ad-b627-4e34-9611-1eaf80d12add
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315442849 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1315442849
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3902989092
Short name T544
Test name
Test status
Simulation time 91777325 ps
CPU time 0.84 seconds
Started Jun 11 12:22:57 PM PDT 24
Finished Jun 11 12:23:01 PM PDT 24
Peak memory 200008 kb
Host smart-f4783d2a-46c4-45cb-9679-2e1deafd034b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902989092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3902989092
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.702840503
Short name T123
Test name
Test status
Simulation time 284039836 ps
CPU time 1.64 seconds
Started Jun 11 12:22:29 PM PDT 24
Finished Jun 11 12:22:34 PM PDT 24
Peak memory 199280 kb
Host smart-aae056a8-5481-4857-aa07-8de1aaf6f003
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702840503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.702840503
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1034347175
Short name T102
Test name
Test status
Simulation time 120196083 ps
CPU time 1.69 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:23:01 PM PDT 24
Peak memory 208288 kb
Host smart-02c33e52-e447-40fb-8450-3120c02e6e19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034347175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1034347175
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1535184722
Short name T597
Test name
Test status
Simulation time 909112689 ps
CPU time 3.3 seconds
Started Jun 11 12:22:29 PM PDT 24
Finished Jun 11 12:22:35 PM PDT 24
Peak memory 200044 kb
Host smart-eba5bf7d-f61f-4f25-a2a4-6e8f7274b436
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535184722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1535184722
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3281572335
Short name T607
Test name
Test status
Simulation time 108614542 ps
CPU time 1 seconds
Started Jun 11 12:23:23 PM PDT 24
Finished Jun 11 12:23:27 PM PDT 24
Peak memory 198060 kb
Host smart-d20ee975-6b68-429d-a474-e189651412c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281572335 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3281572335
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2492200571
Short name T615
Test name
Test status
Simulation time 64784116 ps
CPU time 0.73 seconds
Started Jun 11 12:22:42 PM PDT 24
Finished Jun 11 12:22:46 PM PDT 24
Peak memory 199888 kb
Host smart-0807d234-85f0-4506-b221-40ce1d721ef1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492200571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2492200571
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.970415383
Short name T577
Test name
Test status
Simulation time 149360306 ps
CPU time 1.19 seconds
Started Jun 11 12:23:23 PM PDT 24
Finished Jun 11 12:23:27 PM PDT 24
Peak memory 198016 kb
Host smart-0f43680d-9269-4956-84a6-44db20cc62f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970415383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.970415383
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2505065309
Short name T138
Test name
Test status
Simulation time 96278242 ps
CPU time 1.3 seconds
Started Jun 11 12:23:22 PM PDT 24
Finished Jun 11 12:23:27 PM PDT 24
Peak memory 207480 kb
Host smart-c08951dc-e4f3-4907-bf88-95471324e43c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505065309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2505065309
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2725866234
Short name T134
Test name
Test status
Simulation time 840172072 ps
CPU time 2.87 seconds
Started Jun 11 12:23:38 PM PDT 24
Finished Jun 11 12:23:44 PM PDT 24
Peak memory 200432 kb
Host smart-67812bbc-7126-4a5f-bdaa-e8360fcff253
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725866234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2725866234
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1198385451
Short name T611
Test name
Test status
Simulation time 131038458 ps
CPU time 0.97 seconds
Started Jun 11 12:23:19 PM PDT 24
Finished Jun 11 12:23:22 PM PDT 24
Peak memory 199904 kb
Host smart-e200aac9-ce7d-4389-9e9e-ed6af0613607
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198385451 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.1198385451
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.844650837
Short name T583
Test name
Test status
Simulation time 69688961 ps
CPU time 0.79 seconds
Started Jun 11 12:23:42 PM PDT 24
Finished Jun 11 12:23:47 PM PDT 24
Peak memory 200120 kb
Host smart-12eb75d9-1975-4687-999c-1232aaf2863d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844650837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.844650837
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.210396657
Short name T570
Test name
Test status
Simulation time 154823497 ps
CPU time 1.17 seconds
Started Jun 11 12:23:19 PM PDT 24
Finished Jun 11 12:23:22 PM PDT 24
Peak memory 199936 kb
Host smart-53c78ce2-0dde-4c5e-9131-945abdcfdd6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210396657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sa
me_csr_outstanding.210396657
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3886780294
Short name T590
Test name
Test status
Simulation time 109782510 ps
CPU time 1.48 seconds
Started Jun 11 12:19:51 PM PDT 24
Finished Jun 11 12:19:54 PM PDT 24
Peak memory 208392 kb
Host smart-0916cf93-8702-422f-b608-11c39da24a3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886780294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3886780294
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2363129020
Short name T562
Test name
Test status
Simulation time 955738953 ps
CPU time 3.08 seconds
Started Jun 11 12:19:50 PM PDT 24
Finished Jun 11 12:19:55 PM PDT 24
Peak memory 198696 kb
Host smart-f2be51fb-cda5-41f5-a8f5-9e63568dee60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363129020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2363129020
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3075447533
Short name T555
Test name
Test status
Simulation time 195706094 ps
CPU time 1.84 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:22:44 PM PDT 24
Peak memory 212036 kb
Host smart-05706b3d-e842-4c0c-bf11-702ce31a5b8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075447533 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3075447533
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2554943446
Short name T122
Test name
Test status
Simulation time 84658505 ps
CPU time 0.85 seconds
Started Jun 11 12:22:29 PM PDT 24
Finished Jun 11 12:22:34 PM PDT 24
Peak memory 198960 kb
Host smart-e2c42e51-efbc-45b9-8b5d-6b47e99aeff4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554943446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2554943446
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1971434124
Short name T604
Test name
Test status
Simulation time 75365185 ps
CPU time 0.98 seconds
Started Jun 11 12:17:57 PM PDT 24
Finished Jun 11 12:17:59 PM PDT 24
Peak memory 200540 kb
Host smart-785a13ac-00e3-4075-9128-162c2cb29368
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971434124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1971434124
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3565292798
Short name T76
Test name
Test status
Simulation time 239288591 ps
CPU time 1.71 seconds
Started Jun 11 12:23:46 PM PDT 24
Finished Jun 11 12:23:55 PM PDT 24
Peak memory 208596 kb
Host smart-27ce9792-a4ea-4861-b79a-8898b7b0a4a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565292798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3565292798
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1055810686
Short name T551
Test name
Test status
Simulation time 408990981 ps
CPU time 1.76 seconds
Started Jun 11 12:17:57 PM PDT 24
Finished Jun 11 12:18:00 PM PDT 24
Peak memory 200488 kb
Host smart-2074662c-7e2d-4d1d-a8be-2ed848cf5760
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055810686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1055810686
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.69470386
Short name T546
Test name
Test status
Simulation time 111695866 ps
CPU time 0.98 seconds
Started Jun 11 12:22:39 PM PDT 24
Finished Jun 11 12:22:42 PM PDT 24
Peak memory 198652 kb
Host smart-2eebe631-b341-46a7-b9c3-107c26e1e084
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69470386 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.69470386
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3127212273
Short name T121
Test name
Test status
Simulation time 73998857 ps
CPU time 0.84 seconds
Started Jun 11 12:22:32 PM PDT 24
Finished Jun 11 12:22:37 PM PDT 24
Peak memory 199848 kb
Host smart-36189477-e20e-4d90-96c0-75446dbb60f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127212273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3127212273
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.887580974
Short name T582
Test name
Test status
Simulation time 269150913 ps
CPU time 1.51 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:22:44 PM PDT 24
Peak memory 199124 kb
Host smart-47a3191e-4f5f-4d66-89cb-55d7c15821bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887580974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.887580974
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.836409965
Short name T564
Test name
Test status
Simulation time 179985350 ps
CPU time 1.4 seconds
Started Jun 11 12:22:57 PM PDT 24
Finished Jun 11 12:23:03 PM PDT 24
Peak memory 208348 kb
Host smart-b718b738-065c-49b9-bbef-b76262cfb371
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836409965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.836409965
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3725407948
Short name T100
Test name
Test status
Simulation time 466574063 ps
CPU time 2.03 seconds
Started Jun 11 12:18:03 PM PDT 24
Finished Jun 11 12:18:06 PM PDT 24
Peak memory 200380 kb
Host smart-3350a8eb-3911-4726-acb5-364711ddc2ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725407948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3725407948
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3211194382
Short name T594
Test name
Test status
Simulation time 123371089 ps
CPU time 1.31 seconds
Started Jun 11 12:22:53 PM PDT 24
Finished Jun 11 12:22:57 PM PDT 24
Peak memory 207028 kb
Host smart-7f2187eb-b065-4788-915c-ffa40955a6d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211194382 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3211194382
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1866287796
Short name T608
Test name
Test status
Simulation time 60370911 ps
CPU time 0.75 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:23:00 PM PDT 24
Peak memory 199400 kb
Host smart-818e6856-665c-4819-a725-273165749378
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866287796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1866287796
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3624627338
Short name T584
Test name
Test status
Simulation time 101781840 ps
CPU time 1.15 seconds
Started Jun 11 12:22:31 PM PDT 24
Finished Jun 11 12:22:36 PM PDT 24
Peak memory 200092 kb
Host smart-de18cee8-c8c8-47e1-9cdd-0742fa347deb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624627338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3624627338
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1360489293
Short name T585
Test name
Test status
Simulation time 167939600 ps
CPU time 1.49 seconds
Started Jun 11 12:22:29 PM PDT 24
Finished Jun 11 12:22:33 PM PDT 24
Peak memory 199240 kb
Host smart-431cbe5c-b038-4815-bacf-b834f29c460f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360489293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1360489293
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.462372785
Short name T579
Test name
Test status
Simulation time 128830611 ps
CPU time 1.31 seconds
Started Jun 11 12:20:41 PM PDT 24
Finished Jun 11 12:20:43 PM PDT 24
Peak memory 211952 kb
Host smart-ef5ae941-8520-461e-b351-5c94dc20573e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462372785 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.462372785
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.634187605
Short name T596
Test name
Test status
Simulation time 96702025 ps
CPU time 0.82 seconds
Started Jun 11 12:22:09 PM PDT 24
Finished Jun 11 12:22:12 PM PDT 24
Peak memory 199764 kb
Host smart-80f29eea-cc87-4621-84c9-14b7e8c89132
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634187605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.634187605
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.80159211
Short name T617
Test name
Test status
Simulation time 83453673 ps
CPU time 0.9 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 12:22:34 PM PDT 24
Peak memory 199756 kb
Host smart-b4e3fff7-1f20-4743-8e5f-a90fecdeed27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80159211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sam
e_csr_outstanding.80159211
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3374480455
Short name T132
Test name
Test status
Simulation time 429375389 ps
CPU time 1.94 seconds
Started Jun 11 12:18:43 PM PDT 24
Finished Jun 11 12:18:46 PM PDT 24
Peak memory 200812 kb
Host smart-f16b50fb-9e4d-4dc8-be30-603fd7feb669
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374480455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3374480455
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.279944265
Short name T605
Test name
Test status
Simulation time 186357305 ps
CPU time 1.73 seconds
Started Jun 11 12:23:12 PM PDT 24
Finished Jun 11 12:23:14 PM PDT 24
Peak memory 214108 kb
Host smart-094d3fd5-682d-47f4-af14-20ec85b58271
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279944265 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.279944265
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.4211197170
Short name T601
Test name
Test status
Simulation time 55579645 ps
CPU time 0.75 seconds
Started Jun 11 12:23:17 PM PDT 24
Finished Jun 11 12:23:19 PM PDT 24
Peak memory 200068 kb
Host smart-b86cf5ed-a00b-4f78-a917-1b0ba55133f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211197170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.4211197170
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2741821998
Short name T593
Test name
Test status
Simulation time 74988956 ps
CPU time 0.97 seconds
Started Jun 11 12:23:11 PM PDT 24
Finished Jun 11 12:23:13 PM PDT 24
Peak memory 199252 kb
Host smart-28b09890-980f-48c8-8ffd-7f3e14616479
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741821998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2741821998
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3857316144
Short name T587
Test name
Test status
Simulation time 195489554 ps
CPU time 1.64 seconds
Started Jun 11 12:22:11 PM PDT 24
Finished Jun 11 12:22:15 PM PDT 24
Peak memory 210728 kb
Host smart-d6532e68-ecfe-4323-a45c-d53ad74338ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857316144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3857316144
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.4237349715
Short name T614
Test name
Test status
Simulation time 525197159 ps
CPU time 1.86 seconds
Started Jun 11 12:22:11 PM PDT 24
Finished Jun 11 12:22:14 PM PDT 24
Peak memory 200212 kb
Host smart-7b3f10a4-88ef-44f4-9934-3f915dfc88cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237349715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.4237349715
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.82039006
Short name T588
Test name
Test status
Simulation time 157406692 ps
CPU time 1.42 seconds
Started Jun 11 12:22:48 PM PDT 24
Finished Jun 11 12:22:52 PM PDT 24
Peak memory 208596 kb
Host smart-5a1ceba1-ab10-40a0-93e9-a33db415ef01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82039006 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.82039006
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.927419664
Short name T120
Test name
Test status
Simulation time 59576375 ps
CPU time 0.73 seconds
Started Jun 11 12:22:54 PM PDT 24
Finished Jun 11 12:22:56 PM PDT 24
Peak memory 199644 kb
Host smart-d535b3b2-8ca9-460f-89a6-45393fd6d670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927419664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.927419664
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.151381344
Short name T600
Test name
Test status
Simulation time 177323102 ps
CPU time 1.17 seconds
Started Jun 11 12:22:59 PM PDT 24
Finished Jun 11 12:23:05 PM PDT 24
Peak memory 200048 kb
Host smart-fd3fba7d-df5d-4cac-a8e5-d1c1b8c65b35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151381344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.151381344
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3062014622
Short name T559
Test name
Test status
Simulation time 236290344 ps
CPU time 1.78 seconds
Started Jun 11 12:23:26 PM PDT 24
Finished Jun 11 12:23:32 PM PDT 24
Peak memory 208512 kb
Host smart-11b1afc6-971f-475f-be7a-1569e7016745
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062014622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3062014622
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2261480742
Short name T568
Test name
Test status
Simulation time 948905810 ps
CPU time 3.03 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:22:45 PM PDT 24
Peak memory 198920 kb
Host smart-3530b485-bedb-49a0-b355-81d5691324e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261480742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2261480742
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1180651306
Short name T97
Test name
Test status
Simulation time 99867199 ps
CPU time 0.92 seconds
Started Jun 11 12:22:51 PM PDT 24
Finished Jun 11 12:22:54 PM PDT 24
Peak memory 200044 kb
Host smart-a4fd577b-52a9-41e8-b362-91365a36cce6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180651306 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1180651306
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.172167771
Short name T580
Test name
Test status
Simulation time 69745942 ps
CPU time 0.76 seconds
Started Jun 11 12:19:52 PM PDT 24
Finished Jun 11 12:19:55 PM PDT 24
Peak memory 199692 kb
Host smart-76a1e050-cb3c-4741-934a-9c7c27f323f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172167771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.172167771
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3239575599
Short name T119
Test name
Test status
Simulation time 108577228 ps
CPU time 0.93 seconds
Started Jun 11 12:19:53 PM PDT 24
Finished Jun 11 12:19:56 PM PDT 24
Peak memory 199944 kb
Host smart-821548bf-aaec-4345-9808-9a87797d995b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239575599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3239575599
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.407764090
Short name T575
Test name
Test status
Simulation time 265000147 ps
CPU time 1.85 seconds
Started Jun 11 12:19:54 PM PDT 24
Finished Jun 11 12:19:57 PM PDT 24
Peak memory 210896 kb
Host smart-8fde9d61-9151-44e9-881f-f3c854de2b4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407764090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.407764090
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1303920441
Short name T133
Test name
Test status
Simulation time 938031720 ps
CPU time 2.91 seconds
Started Jun 11 12:22:49 PM PDT 24
Finished Jun 11 12:22:54 PM PDT 24
Peak memory 200488 kb
Host smart-3b08f1cc-72c9-4b4f-9560-b2131fe33a97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303920441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1303920441
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1277286957
Short name T72
Test name
Test status
Simulation time 91314857 ps
CPU time 0.85 seconds
Started Jun 11 12:23:42 PM PDT 24
Finished Jun 11 12:23:46 PM PDT 24
Peak memory 200272 kb
Host smart-8f462187-5e00-4711-a7cf-74bf546a12e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277286957 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1277286957
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.244447678
Short name T613
Test name
Test status
Simulation time 89155737 ps
CPU time 0.82 seconds
Started Jun 11 12:23:40 PM PDT 24
Finished Jun 11 12:23:43 PM PDT 24
Peak memory 200148 kb
Host smart-3415886b-5229-4fe7-bb96-750e0ace8703
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244447678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.244447678
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1705431089
Short name T603
Test name
Test status
Simulation time 107691131 ps
CPU time 1.23 seconds
Started Jun 11 12:20:17 PM PDT 24
Finished Jun 11 12:20:19 PM PDT 24
Peak memory 200724 kb
Host smart-4eefb42c-85e6-44ab-af0a-2482d3db2961
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705431089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1705431089
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1972497112
Short name T137
Test name
Test status
Simulation time 488863136 ps
CPU time 3.38 seconds
Started Jun 11 12:22:57 PM PDT 24
Finished Jun 11 12:23:04 PM PDT 24
Peak memory 211112 kb
Host smart-29b54288-2741-40a5-9591-849dfaa0d2e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972497112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1972497112
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.284622542
Short name T554
Test name
Test status
Simulation time 195897649 ps
CPU time 1.57 seconds
Started Jun 11 12:21:28 PM PDT 24
Finished Jun 11 12:21:30 PM PDT 24
Peak memory 200280 kb
Host smart-2c8868f8-ca8d-4f13-b3e3-27da24b5d999
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284622542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.284622542
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1938647650
Short name T618
Test name
Test status
Simulation time 793459990 ps
CPU time 4.4 seconds
Started Jun 11 12:19:40 PM PDT 24
Finished Jun 11 12:19:45 PM PDT 24
Peak memory 200484 kb
Host smart-7785d926-392d-4e87-a692-bd45a83854e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938647650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
938647650
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.683417273
Short name T591
Test name
Test status
Simulation time 102449912 ps
CPU time 0.79 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 12:22:34 PM PDT 24
Peak memory 199780 kb
Host smart-6bdaec14-b0ad-4e67-afbb-82a4cccb2cb8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683417273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.683417273
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2978836162
Short name T560
Test name
Test status
Simulation time 177274217 ps
CPU time 1.22 seconds
Started Jun 11 12:20:43 PM PDT 24
Finished Jun 11 12:20:45 PM PDT 24
Peak memory 208388 kb
Host smart-a2c259d1-4b99-4433-9f4e-f0d1a203cd04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978836162 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2978836162
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.674915200
Short name T599
Test name
Test status
Simulation time 80280940 ps
CPU time 0.8 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:23:00 PM PDT 24
Peak memory 200100 kb
Host smart-9f70b373-7ec8-42b5-8216-14e033dfcf92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674915200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.674915200
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2831973129
Short name T619
Test name
Test status
Simulation time 206459086 ps
CPU time 1.41 seconds
Started Jun 11 12:22:26 PM PDT 24
Finished Jun 11 12:22:28 PM PDT 24
Peak memory 200032 kb
Host smart-d3e22127-92fb-4652-b5e7-274defc04569
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831973129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2831973129
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.505714830
Short name T127
Test name
Test status
Simulation time 184290831 ps
CPU time 1.43 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 12:22:35 PM PDT 24
Peak memory 216508 kb
Host smart-21425ce1-db68-40ca-946a-300339fbe4e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505714830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.505714830
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.562091387
Short name T131
Test name
Test status
Simulation time 868877384 ps
CPU time 3.2 seconds
Started Jun 11 12:21:27 PM PDT 24
Finished Jun 11 12:21:31 PM PDT 24
Peak memory 200456 kb
Host smart-37f24d11-59bc-43de-863d-ac195a5c865b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562091387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.
562091387
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3027057918
Short name T550
Test name
Test status
Simulation time 165250449 ps
CPU time 1.84 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:23:01 PM PDT 24
Peak memory 208628 kb
Host smart-2a94510a-deb4-40d5-8542-cbf854bc29bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027057918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
027057918
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2209897779
Short name T74
Test name
Test status
Simulation time 2282597981 ps
CPU time 10.52 seconds
Started Jun 11 12:20:41 PM PDT 24
Finished Jun 11 12:20:52 PM PDT 24
Peak memory 216848 kb
Host smart-acd7cb1a-4135-45f8-9624-9a5217df2521
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209897779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
209897779
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1811704615
Short name T567
Test name
Test status
Simulation time 92490759 ps
CPU time 0.78 seconds
Started Jun 11 12:20:42 PM PDT 24
Finished Jun 11 12:20:44 PM PDT 24
Peak memory 200132 kb
Host smart-5f6c95e7-3760-4e7a-ab47-cb79006e9d16
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811704615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
811704615
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1918412796
Short name T592
Test name
Test status
Simulation time 150993461 ps
CPU time 1.12 seconds
Started Jun 11 12:18:20 PM PDT 24
Finished Jun 11 12:18:22 PM PDT 24
Peak memory 208812 kb
Host smart-b8b39b5d-be69-4df1-89bf-cf7f8865d5bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918412796 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1918412796
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3500466011
Short name T609
Test name
Test status
Simulation time 73652725 ps
CPU time 0.77 seconds
Started Jun 11 12:21:34 PM PDT 24
Finished Jun 11 12:21:36 PM PDT 24
Peak memory 200064 kb
Host smart-6fe7e282-a65a-487f-8fb6-a14d33b9d91a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500466011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3500466011
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2024699588
Short name T574
Test name
Test status
Simulation time 256691504 ps
CPU time 1.61 seconds
Started Jun 11 12:22:42 PM PDT 24
Finished Jun 11 12:22:46 PM PDT 24
Peak memory 200128 kb
Host smart-c2dd2819-e8a6-45dd-b63a-01bf75d350d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024699588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2024699588
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.497468578
Short name T565
Test name
Test status
Simulation time 121611638 ps
CPU time 1.66 seconds
Started Jun 11 12:22:25 PM PDT 24
Finished Jun 11 12:22:28 PM PDT 24
Peak memory 207608 kb
Host smart-aa8d40a5-a585-4c20-b337-825c59d42bba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497468578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.497468578
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3179259153
Short name T586
Test name
Test status
Simulation time 479911872 ps
CPU time 1.82 seconds
Started Jun 11 12:22:26 PM PDT 24
Finished Jun 11 12:22:29 PM PDT 24
Peak memory 200096 kb
Host smart-98a07a14-b932-4723-bd79-7abb10a9d547
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179259153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3179259153
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2110726153
Short name T612
Test name
Test status
Simulation time 433332346 ps
CPU time 2.61 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:23:03 PM PDT 24
Peak memory 200164 kb
Host smart-e08bb8ca-fe3b-4a52-bf63-d1b3023e6f1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110726153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
110726153
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.759109992
Short name T563
Test name
Test status
Simulation time 2286544434 ps
CPU time 9.18 seconds
Started Jun 11 12:22:42 PM PDT 24
Finished Jun 11 12:22:53 PM PDT 24
Peak memory 199884 kb
Host smart-83d67666-3f4c-4799-b9f1-574caea98b44
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759109992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.759109992
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.220362562
Short name T545
Test name
Test status
Simulation time 99779929 ps
CPU time 0.9 seconds
Started Jun 11 12:22:43 PM PDT 24
Finished Jun 11 12:22:46 PM PDT 24
Peak memory 199884 kb
Host smart-e1f2b64c-771c-4f7c-ad84-5557fd064355
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220362562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.220362562
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.458091582
Short name T549
Test name
Test status
Simulation time 164155855 ps
CPU time 1.56 seconds
Started Jun 11 12:20:41 PM PDT 24
Finished Jun 11 12:20:44 PM PDT 24
Peak memory 208616 kb
Host smart-32f3fa7b-698d-4670-9d79-fc96fda055ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458091582 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.458091582
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.15728905
Short name T106
Test name
Test status
Simulation time 63369411 ps
CPU time 0.87 seconds
Started Jun 11 12:22:41 PM PDT 24
Finished Jun 11 12:22:45 PM PDT 24
Peak memory 198944 kb
Host smart-c5a21879-c270-4ce3-9023-d71461ab7f83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15728905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.15728905
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.148119955
Short name T118
Test name
Test status
Simulation time 80367819 ps
CPU time 0.92 seconds
Started Jun 11 12:19:14 PM PDT 24
Finished Jun 11 12:19:15 PM PDT 24
Peak memory 200232 kb
Host smart-15d3f723-da67-42a9-849e-2ddd090f892e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148119955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.148119955
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1702289434
Short name T128
Test name
Test status
Simulation time 184152021 ps
CPU time 2.55 seconds
Started Jun 11 12:20:42 PM PDT 24
Finished Jun 11 12:20:46 PM PDT 24
Peak memory 211996 kb
Host smart-85e9e8e1-6cad-4f44-97eb-b66b519c0c9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702289434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.1702289434
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2896123237
Short name T595
Test name
Test status
Simulation time 876117590 ps
CPU time 3.2 seconds
Started Jun 11 12:17:14 PM PDT 24
Finished Jun 11 12:17:18 PM PDT 24
Peak memory 199996 kb
Host smart-5927797c-dd89-437b-b78a-02184403478f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896123237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2896123237
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1476220231
Short name T125
Test name
Test status
Simulation time 73480835 ps
CPU time 0.8 seconds
Started Jun 11 12:22:50 PM PDT 24
Finished Jun 11 12:22:53 PM PDT 24
Peak memory 199736 kb
Host smart-89fa351e-5534-438b-9d70-065feac5d770
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476220231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1476220231
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2442754303
Short name T598
Test name
Test status
Simulation time 145123659 ps
CPU time 1.23 seconds
Started Jun 11 12:22:10 PM PDT 24
Finished Jun 11 12:22:13 PM PDT 24
Peak memory 199860 kb
Host smart-187522d2-5cb9-4479-809d-e1a7bcfa4ae4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442754303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.2442754303
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.240743099
Short name T101
Test name
Test status
Simulation time 461246726 ps
CPU time 3.31 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 12:22:37 PM PDT 24
Peak memory 208196 kb
Host smart-a8d84bba-219a-4fdb-be48-f316f71eab98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240743099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.240743099
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3172224695
Short name T135
Test name
Test status
Simulation time 1105071934 ps
CPU time 3.57 seconds
Started Jun 11 12:22:54 PM PDT 24
Finished Jun 11 12:23:00 PM PDT 24
Peak memory 200124 kb
Host smart-0782071e-ce5e-4bae-8f83-5d9e36182631
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172224695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.3172224695
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3471958532
Short name T557
Test name
Test status
Simulation time 179489748 ps
CPU time 1.15 seconds
Started Jun 11 12:20:56 PM PDT 24
Finished Jun 11 12:20:58 PM PDT 24
Peak memory 208512 kb
Host smart-b893e151-5771-49ba-b7f4-f3a7342efe64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471958532 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.3471958532
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2966601445
Short name T589
Test name
Test status
Simulation time 61441973 ps
CPU time 0.82 seconds
Started Jun 11 12:18:39 PM PDT 24
Finished Jun 11 12:18:41 PM PDT 24
Peak memory 200484 kb
Host smart-88cad6a1-4edc-4fde-bdf7-902b1e677c7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966601445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2966601445
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2667307513
Short name T572
Test name
Test status
Simulation time 144326227 ps
CPU time 1.2 seconds
Started Jun 11 12:17:59 PM PDT 24
Finished Jun 11 12:18:01 PM PDT 24
Peak memory 200172 kb
Host smart-b1a95101-3291-4d7a-9eb9-6f73025c27c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667307513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.2667307513
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1444184784
Short name T77
Test name
Test status
Simulation time 236734485 ps
CPU time 1.88 seconds
Started Jun 11 12:22:08 PM PDT 24
Finished Jun 11 12:22:13 PM PDT 24
Peak memory 207052 kb
Host smart-abd247f0-a5f8-44b2-97e7-c20ebc5c439d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444184784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1444184784
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.4247202659
Short name T75
Test name
Test status
Simulation time 472192080 ps
CPU time 1.99 seconds
Started Jun 11 12:22:10 PM PDT 24
Finished Jun 11 12:22:14 PM PDT 24
Peak memory 199044 kb
Host smart-3606e3b2-8d6d-45e7-9022-d6155caba0e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247202659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.4247202659
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.4218594367
Short name T566
Test name
Test status
Simulation time 191037594 ps
CPU time 1.19 seconds
Started Jun 11 12:22:49 PM PDT 24
Finished Jun 11 12:22:53 PM PDT 24
Peak memory 209988 kb
Host smart-ab935c09-a6e7-42f9-8490-41bf87a41fcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218594367 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.4218594367
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.4110230683
Short name T610
Test name
Test status
Simulation time 76332262 ps
CPU time 0.85 seconds
Started Jun 11 12:22:31 PM PDT 24
Finished Jun 11 12:22:37 PM PDT 24
Peak memory 199276 kb
Host smart-45b944db-8847-4a98-a939-f3633f9ff08f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110230683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.4110230683
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.419788960
Short name T124
Test name
Test status
Simulation time 120206648 ps
CPU time 1.04 seconds
Started Jun 11 12:22:43 PM PDT 24
Finished Jun 11 12:22:47 PM PDT 24
Peak memory 199092 kb
Host smart-29579e40-f26c-4cd5-862b-0579209b7f4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419788960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sam
e_csr_outstanding.419788960
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2854381792
Short name T573
Test name
Test status
Simulation time 110748459 ps
CPU time 1.64 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:22:43 PM PDT 24
Peak memory 207020 kb
Host smart-05dcdb5f-3ed9-47a1-9b81-66bb6a952409
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854381792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2854381792
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3396331282
Short name T571
Test name
Test status
Simulation time 884786796 ps
CPU time 3.05 seconds
Started Jun 11 12:22:57 PM PDT 24
Finished Jun 11 12:23:04 PM PDT 24
Peak memory 200264 kb
Host smart-9c11369d-a206-4aff-be4b-f46ec966b778
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396331282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3396331282
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1345799368
Short name T558
Test name
Test status
Simulation time 121737030 ps
CPU time 1.31 seconds
Started Jun 11 12:22:48 PM PDT 24
Finished Jun 11 12:22:51 PM PDT 24
Peak memory 212712 kb
Host smart-800925da-76ac-4707-9d89-fd5ecbf86c04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345799368 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1345799368
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.965871527
Short name T547
Test name
Test status
Simulation time 83706628 ps
CPU time 0.84 seconds
Started Jun 11 12:22:48 PM PDT 24
Finished Jun 11 12:22:52 PM PDT 24
Peak memory 199844 kb
Host smart-efb928e9-ece4-4fc3-a51e-0e46cb471e59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965871527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.965871527
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.808965571
Short name T616
Test name
Test status
Simulation time 126398983 ps
CPU time 1.1 seconds
Started Jun 11 12:22:52 PM PDT 24
Finished Jun 11 12:22:54 PM PDT 24
Peak memory 200040 kb
Host smart-d86789ce-9a41-4387-8adf-cd5d99993226
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808965571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.808965571
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.687861251
Short name T552
Test name
Test status
Simulation time 125147223 ps
CPU time 1.59 seconds
Started Jun 11 12:22:59 PM PDT 24
Finished Jun 11 12:23:05 PM PDT 24
Peak memory 208468 kb
Host smart-064c5c66-96b5-4ddd-878b-c644e175a050
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687861251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.687861251
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3216283816
Short name T129
Test name
Test status
Simulation time 928615785 ps
CPU time 3.14 seconds
Started Jun 11 12:22:51 PM PDT 24
Finished Jun 11 12:22:56 PM PDT 24
Peak memory 200136 kb
Host smart-919b55c2-36f9-4f01-a0d9-b0d645873f15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216283816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3216283816
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1464457132
Short name T578
Test name
Test status
Simulation time 205119780 ps
CPU time 1.28 seconds
Started Jun 11 12:23:38 PM PDT 24
Finished Jun 11 12:23:43 PM PDT 24
Peak memory 208396 kb
Host smart-4de9d99e-4380-4d7f-87df-6c2cd64443d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464457132 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1464457132
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.990993539
Short name T602
Test name
Test status
Simulation time 69196633 ps
CPU time 0.74 seconds
Started Jun 11 12:22:41 PM PDT 24
Finished Jun 11 12:22:44 PM PDT 24
Peak memory 199784 kb
Host smart-040f94bd-f661-477e-8b28-5cc6c81eaa9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990993539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.990993539
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3785814398
Short name T569
Test name
Test status
Simulation time 122785079 ps
CPU time 1.01 seconds
Started Jun 11 12:23:26 PM PDT 24
Finished Jun 11 12:23:32 PM PDT 24
Peak memory 199448 kb
Host smart-ee2732ea-69b2-4097-bb84-e5c449fb78b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785814398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3785814398
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.260687044
Short name T145
Test name
Test status
Simulation time 468866219 ps
CPU time 1.83 seconds
Started Jun 11 12:22:51 PM PDT 24
Finished Jun 11 12:22:54 PM PDT 24
Peak memory 200116 kb
Host smart-4e21593c-6cc2-4b43-b921-8735d4daeb9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260687044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
260687044
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.364179948
Short name T31
Test name
Test status
Simulation time 1231674700 ps
CPU time 5.98 seconds
Started Jun 11 12:22:45 PM PDT 24
Finished Jun 11 12:22:53 PM PDT 24
Peak memory 217668 kb
Host smart-97c8d9c7-ca99-43f6-8142-c3f37adcb108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364179948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.364179948
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3064560585
Short name T449
Test name
Test status
Simulation time 244234821 ps
CPU time 1.09 seconds
Started Jun 11 12:22:41 PM PDT 24
Finished Jun 11 12:22:45 PM PDT 24
Peak memory 216348 kb
Host smart-f0994b60-8ad3-43e5-ad5e-9262c961f111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064560585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3064560585
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.2880270409
Short name T406
Test name
Test status
Simulation time 139656885 ps
CPU time 0.8 seconds
Started Jun 11 12:20:18 PM PDT 24
Finished Jun 11 12:20:19 PM PDT 24
Peak memory 200140 kb
Host smart-d85754cd-0a38-49ca-8edb-51375330c9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880270409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2880270409
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.858925403
Short name T56
Test name
Test status
Simulation time 799706845 ps
CPU time 4.13 seconds
Started Jun 11 12:21:33 PM PDT 24
Finished Jun 11 12:21:38 PM PDT 24
Peak memory 200428 kb
Host smart-64827064-7819-489b-8dec-9090103d77c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858925403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.858925403
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1151124011
Short name T81
Test name
Test status
Simulation time 16529623481 ps
CPU time 33.1 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:23:33 PM PDT 24
Peak memory 218444 kb
Host smart-6dfbc7b9-47df-401b-a5ec-7a0f3515aabd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151124011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1151124011
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2815821159
Short name T207
Test name
Test status
Simulation time 107618044 ps
CPU time 0.98 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:22:43 PM PDT 24
Peak memory 199772 kb
Host smart-e81f294d-4f30-4331-b740-44fce5a26831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815821159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2815821159
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1514686616
Short name T423
Test name
Test status
Simulation time 117571277 ps
CPU time 1.13 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 12:22:35 PM PDT 24
Peak memory 200164 kb
Host smart-2e0230fc-b2e9-4520-be04-bf43129c8ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514686616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1514686616
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3583310376
Short name T261
Test name
Test status
Simulation time 191248272 ps
CPU time 1.73 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:22:44 PM PDT 24
Peak memory 199096 kb
Host smart-7a5f64db-c8f0-4a8e-a5c0-03245a2aa2e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583310376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3583310376
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2769109312
Short name T152
Test name
Test status
Simulation time 371371975 ps
CPU time 2.16 seconds
Started Jun 11 12:22:25 PM PDT 24
Finished Jun 11 12:22:28 PM PDT 24
Peak memory 199452 kb
Host smart-fa488951-ad2c-4a16-8a97-a23250b919cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769109312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2769109312
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.493953442
Short name T184
Test name
Test status
Simulation time 151953267 ps
CPU time 1.23 seconds
Started Jun 11 12:20:04 PM PDT 24
Finished Jun 11 12:20:06 PM PDT 24
Peak memory 200404 kb
Host smart-d2b1a62d-bbf2-4628-97aa-f73b22d5c486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493953442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.493953442
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3944324688
Short name T220
Test name
Test status
Simulation time 65063146 ps
CPU time 0.79 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:23:01 PM PDT 24
Peak memory 199844 kb
Host smart-ae0b12fa-b8ed-4005-8588-ab9c796f02ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944324688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3944324688
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.118689891
Short name T433
Test name
Test status
Simulation time 1902420073 ps
CPU time 6.6 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:22:48 PM PDT 24
Peak memory 221572 kb
Host smart-cdfaea81-2218-403f-a44b-95b532464a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118689891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.118689891
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2401196632
Short name T181
Test name
Test status
Simulation time 244245610 ps
CPU time 1.09 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 12:22:34 PM PDT 24
Peak memory 216212 kb
Host smart-917e573d-fa7d-4161-ae66-3f9117798ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401196632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2401196632
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2848112735
Short name T347
Test name
Test status
Simulation time 185121285 ps
CPU time 0.94 seconds
Started Jun 11 12:22:41 PM PDT 24
Finished Jun 11 12:22:45 PM PDT 24
Peak memory 199164 kb
Host smart-1e115a79-ac79-47d1-9b4c-a9c21d4a0d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848112735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2848112735
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2386163313
Short name T470
Test name
Test status
Simulation time 1634090059 ps
CPU time 5.77 seconds
Started Jun 11 12:22:44 PM PDT 24
Finished Jun 11 12:22:53 PM PDT 24
Peak memory 200188 kb
Host smart-bb473cf6-c6cc-418f-816d-7a9b9119167b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386163313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2386163313
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.2286579477
Short name T501
Test name
Test status
Simulation time 122280534 ps
CPU time 1.14 seconds
Started Jun 11 12:22:43 PM PDT 24
Finished Jun 11 12:22:47 PM PDT 24
Peak memory 200276 kb
Host smart-bba5802a-b6ea-4908-ab8b-09257aa0a58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286579477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2286579477
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.639312658
Short name T238
Test name
Test status
Simulation time 4119141265 ps
CPU time 13.59 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:22:55 PM PDT 24
Peak memory 209536 kb
Host smart-2495d658-4b9c-4709-923a-0a95e66fc221
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639312658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.639312658
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3002898153
Short name T66
Test name
Test status
Simulation time 435781920 ps
CPU time 2.62 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:22:44 PM PDT 24
Peak memory 199976 kb
Host smart-880a582b-4f54-491c-a101-3ef14243ed22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002898153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3002898153
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2084292355
Short name T278
Test name
Test status
Simulation time 113829005 ps
CPU time 0.95 seconds
Started Jun 11 12:20:43 PM PDT 24
Finished Jun 11 12:20:45 PM PDT 24
Peak memory 200184 kb
Host smart-2dbdae93-a063-455b-a683-b304102dd0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084292355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2084292355
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3525231874
Short name T173
Test name
Test status
Simulation time 74816815 ps
CPU time 0.77 seconds
Started Jun 11 12:23:34 PM PDT 24
Finished Jun 11 12:23:39 PM PDT 24
Peak memory 200068 kb
Host smart-bf37ef8f-558e-4ca4-adf3-36ed86d2082c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525231874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3525231874
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1477349919
Short name T32
Test name
Test status
Simulation time 1231877822 ps
CPU time 5.36 seconds
Started Jun 11 12:23:46 PM PDT 24
Finished Jun 11 12:23:59 PM PDT 24
Peak memory 217308 kb
Host smart-15590150-01e7-4362-9eed-fde46bc73161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477349919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1477349919
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3626912902
Short name T384
Test name
Test status
Simulation time 244110628 ps
CPU time 1.03 seconds
Started Jun 11 12:23:43 PM PDT 24
Finished Jun 11 12:23:48 PM PDT 24
Peak memory 217520 kb
Host smart-1f6221ec-8d89-480d-8620-442a3b1809e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626912902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3626912902
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.3756339324
Short name T429
Test name
Test status
Simulation time 207162973 ps
CPU time 0.97 seconds
Started Jun 11 12:23:41 PM PDT 24
Finished Jun 11 12:23:45 PM PDT 24
Peak memory 200096 kb
Host smart-602db3d6-5b02-4481-95b1-f619ea9a6acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756339324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3756339324
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2311839910
Short name T140
Test name
Test status
Simulation time 1696831525 ps
CPU time 5.78 seconds
Started Jun 11 12:23:44 PM PDT 24
Finished Jun 11 12:23:57 PM PDT 24
Peak memory 200516 kb
Host smart-57827252-55ab-4904-a806-ef26e1e19972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311839910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2311839910
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1951530787
Short name T154
Test name
Test status
Simulation time 110533464 ps
CPU time 1.04 seconds
Started Jun 11 12:23:33 PM PDT 24
Finished Jun 11 12:23:39 PM PDT 24
Peak memory 200192 kb
Host smart-a4da7ade-0343-4157-8fc4-d04fee9b8541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951530787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1951530787
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.3458337603
Short name T417
Test name
Test status
Simulation time 195154659 ps
CPU time 1.31 seconds
Started Jun 11 12:23:46 PM PDT 24
Finished Jun 11 12:23:55 PM PDT 24
Peak memory 200500 kb
Host smart-0e8b36b7-bff3-424b-bf29-3bc808d1e13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458337603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3458337603
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1273339886
Short name T212
Test name
Test status
Simulation time 232196426 ps
CPU time 1.74 seconds
Started Jun 11 12:23:43 PM PDT 24
Finished Jun 11 12:23:49 PM PDT 24
Peak memory 200300 kb
Host smart-d4236521-4b9c-47a7-8b1b-3fc1fc5c0202
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273339886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1273339886
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1518919050
Short name T92
Test name
Test status
Simulation time 454622090 ps
CPU time 2.52 seconds
Started Jun 11 12:23:39 PM PDT 24
Finished Jun 11 12:23:45 PM PDT 24
Peak memory 200276 kb
Host smart-dd8c2336-e48b-41d9-951d-311802bcc468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518919050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1518919050
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.1083429200
Short name T58
Test name
Test status
Simulation time 142482682 ps
CPU time 1.18 seconds
Started Jun 11 12:23:37 PM PDT 24
Finished Jun 11 12:23:42 PM PDT 24
Peak memory 200296 kb
Host smart-860c5281-b9ef-43bf-9b34-42693af245cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083429200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.1083429200
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2370858912
Short name T229
Test name
Test status
Simulation time 63743148 ps
CPU time 0.7 seconds
Started Jun 11 12:23:43 PM PDT 24
Finished Jun 11 12:23:48 PM PDT 24
Peak memory 199968 kb
Host smart-e36e10d9-980c-44be-b940-58236d057a83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370858912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2370858912
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2371453899
Short name T464
Test name
Test status
Simulation time 245071921 ps
CPU time 1.03 seconds
Started Jun 11 12:23:43 PM PDT 24
Finished Jun 11 12:23:48 PM PDT 24
Peak memory 217524 kb
Host smart-5c86700c-66f9-4cae-b721-8eed160df9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371453899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.2371453899
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.763978522
Short name T459
Test name
Test status
Simulation time 87193255 ps
CPU time 0.74 seconds
Started Jun 11 12:23:36 PM PDT 24
Finished Jun 11 12:23:41 PM PDT 24
Peak memory 200120 kb
Host smart-88f06d8b-5fdb-441c-a628-13978ecc6a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763978522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.763978522
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.3737989208
Short name T204
Test name
Test status
Simulation time 1593627051 ps
CPU time 5.44 seconds
Started Jun 11 12:23:39 PM PDT 24
Finished Jun 11 12:23:48 PM PDT 24
Peak memory 200428 kb
Host smart-063007af-58f4-4bda-98f3-27988d79813e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737989208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3737989208
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.908272803
Short name T276
Test name
Test status
Simulation time 105943813 ps
CPU time 0.95 seconds
Started Jun 11 12:23:30 PM PDT 24
Finished Jun 11 12:23:36 PM PDT 24
Peak memory 200252 kb
Host smart-e243b7eb-3e13-4d0b-b6c8-4a8bc65d9489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908272803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.908272803
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.4080726110
Short name T340
Test name
Test status
Simulation time 110659290 ps
CPU time 1.14 seconds
Started Jun 11 12:23:46 PM PDT 24
Finished Jun 11 12:23:55 PM PDT 24
Peak memory 200176 kb
Host smart-3682dbb5-75c1-49d0-aa1d-6b62843f8eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080726110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.4080726110
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1033884043
Short name T412
Test name
Test status
Simulation time 2125664105 ps
CPU time 10.12 seconds
Started Jun 11 12:23:36 PM PDT 24
Finished Jun 11 12:23:50 PM PDT 24
Peak memory 200476 kb
Host smart-8be0a6f6-11df-47c2-ae26-e82e677af6c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033884043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1033884043
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.283265275
Short name T248
Test name
Test status
Simulation time 455529076 ps
CPU time 2.39 seconds
Started Jun 11 12:23:47 PM PDT 24
Finished Jun 11 12:23:58 PM PDT 24
Peak memory 200324 kb
Host smart-7cc73378-bba2-4b4c-9540-2b21c2dad132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283265275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.283265275
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.462439583
Short name T263
Test name
Test status
Simulation time 78321056 ps
CPU time 0.83 seconds
Started Jun 11 12:23:31 PM PDT 24
Finished Jun 11 12:23:36 PM PDT 24
Peak memory 200128 kb
Host smart-db6d4785-3a79-442d-88cb-329d76275336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462439583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.462439583
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3647034400
Short name T520
Test name
Test status
Simulation time 57872141 ps
CPU time 0.73 seconds
Started Jun 11 12:23:48 PM PDT 24
Finished Jun 11 12:23:57 PM PDT 24
Peak memory 200152 kb
Host smart-2bccbd01-8788-4ee8-9b39-ab0ba86cdbf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647034400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3647034400
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.1929990067
Short name T70
Test name
Test status
Simulation time 2363885094 ps
CPU time 7.81 seconds
Started Jun 11 12:23:46 PM PDT 24
Finished Jun 11 12:24:02 PM PDT 24
Peak memory 222004 kb
Host smart-4a71c723-c423-4906-aa9f-818b9f306560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929990067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1929990067
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.191199618
Short name T148
Test name
Test status
Simulation time 244239852 ps
CPU time 1.07 seconds
Started Jun 11 12:23:43 PM PDT 24
Finished Jun 11 12:23:48 PM PDT 24
Peak memory 217516 kb
Host smart-941b128d-4f48-4777-a273-b204d4f7b75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191199618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.191199618
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3973479688
Short name T311
Test name
Test status
Simulation time 83274479 ps
CPU time 0.74 seconds
Started Jun 11 12:23:32 PM PDT 24
Finished Jun 11 12:23:37 PM PDT 24
Peak memory 200396 kb
Host smart-4f30d251-4260-4018-a6eb-a48932d4010c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973479688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3973479688
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.663627619
Short name T505
Test name
Test status
Simulation time 1703710410 ps
CPU time 6.31 seconds
Started Jun 11 12:23:46 PM PDT 24
Finished Jun 11 12:24:00 PM PDT 24
Peak memory 200168 kb
Host smart-7c4e2ea9-5e50-461c-af1d-ba8c0b059856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663627619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.663627619
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.317933070
Short name T201
Test name
Test status
Simulation time 150367107 ps
CPU time 1.14 seconds
Started Jun 11 12:23:46 PM PDT 24
Finished Jun 11 12:23:55 PM PDT 24
Peak memory 200316 kb
Host smart-24b76ec7-bee6-4c2f-95f9-158241946a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317933070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.317933070
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3202039313
Short name T185
Test name
Test status
Simulation time 229605983 ps
CPU time 1.49 seconds
Started Jun 11 12:23:31 PM PDT 24
Finished Jun 11 12:23:38 PM PDT 24
Peak memory 200764 kb
Host smart-ab1db7be-d70e-4580-b09e-57b26b9e3824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202039313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3202039313
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.765964620
Short name T116
Test name
Test status
Simulation time 5965834851 ps
CPU time 20.37 seconds
Started Jun 11 12:23:36 PM PDT 24
Finished Jun 11 12:24:00 PM PDT 24
Peak memory 200636 kb
Host smart-287b8b1b-b32e-421b-87c8-4eebe9cd2833
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765964620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.765964620
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1682777640
Short name T413
Test name
Test status
Simulation time 560252032 ps
CPU time 2.89 seconds
Started Jun 11 12:23:36 PM PDT 24
Finished Jun 11 12:23:43 PM PDT 24
Peak memory 200304 kb
Host smart-211072b2-d15e-4eef-a40b-f83bb779b578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682777640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1682777640
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2365552244
Short name T382
Test name
Test status
Simulation time 162739629 ps
CPU time 1.03 seconds
Started Jun 11 12:23:43 PM PDT 24
Finished Jun 11 12:23:48 PM PDT 24
Peak memory 200168 kb
Host smart-083a7622-6fc4-4c21-a143-d6117c586e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365552244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2365552244
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3126766689
Short name T460
Test name
Test status
Simulation time 65449598 ps
CPU time 0.79 seconds
Started Jun 11 12:23:39 PM PDT 24
Finished Jun 11 12:23:43 PM PDT 24
Peak memory 199388 kb
Host smart-0c7dfd4f-fcc3-44ce-bbf5-e88859652cd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126766689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3126766689
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2070180907
Short name T290
Test name
Test status
Simulation time 244579145 ps
CPU time 1.12 seconds
Started Jun 11 12:23:48 PM PDT 24
Finished Jun 11 12:23:57 PM PDT 24
Peak memory 217504 kb
Host smart-817dff8d-ae31-40a1-824e-9d376dcfa5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070180907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2070180907
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.671271610
Short name T391
Test name
Test status
Simulation time 214372284 ps
CPU time 0.88 seconds
Started Jun 11 12:23:41 PM PDT 24
Finished Jun 11 12:23:45 PM PDT 24
Peak memory 200104 kb
Host smart-e69e92af-0c2a-43ad-8aab-b0d1220be250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671271610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.671271610
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2827228851
Short name T427
Test name
Test status
Simulation time 697073360 ps
CPU time 3.88 seconds
Started Jun 11 12:23:42 PM PDT 24
Finished Jun 11 12:23:50 PM PDT 24
Peak memory 200524 kb
Host smart-344c8ee0-95eb-4f63-9989-17b00e880f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827228851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2827228851
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.4099203088
Short name T183
Test name
Test status
Simulation time 186522938 ps
CPU time 1.15 seconds
Started Jun 11 12:23:41 PM PDT 24
Finished Jun 11 12:23:45 PM PDT 24
Peak memory 200080 kb
Host smart-2137860f-5217-4b6f-a30f-4674676ff637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099203088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.4099203088
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3306836889
Short name T167
Test name
Test status
Simulation time 122151158 ps
CPU time 1.14 seconds
Started Jun 11 12:23:41 PM PDT 24
Finished Jun 11 12:23:45 PM PDT 24
Peak memory 200396 kb
Host smart-02a735a2-f329-4cd5-986a-40363ab9759f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306836889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3306836889
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1199013786
Short name T466
Test name
Test status
Simulation time 1638500803 ps
CPU time 6.37 seconds
Started Jun 11 12:23:39 PM PDT 24
Finished Jun 11 12:23:49 PM PDT 24
Peak memory 200460 kb
Host smart-0a5d0ba2-eb8f-4a9b-860d-096bd2d0e068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199013786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1199013786
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3255580878
Short name T403
Test name
Test status
Simulation time 124321051 ps
CPU time 1.56 seconds
Started Jun 11 12:23:41 PM PDT 24
Finished Jun 11 12:23:46 PM PDT 24
Peak memory 208464 kb
Host smart-66e66004-01cb-4846-8487-e45266cfda9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255580878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3255580878
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1485125517
Short name T168
Test name
Test status
Simulation time 281231571 ps
CPU time 1.42 seconds
Started Jun 11 12:23:47 PM PDT 24
Finished Jun 11 12:23:57 PM PDT 24
Peak memory 200332 kb
Host smart-932f9231-41aa-4b1a-ab50-bac00eae4cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485125517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1485125517
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.2343268760
Short name T174
Test name
Test status
Simulation time 70457426 ps
CPU time 0.78 seconds
Started Jun 11 12:23:48 PM PDT 24
Finished Jun 11 12:23:57 PM PDT 24
Peak memory 200140 kb
Host smart-81084c33-4384-4b24-a7bd-98dcc23a775c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343268760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2343268760
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3791320016
Short name T35
Test name
Test status
Simulation time 1896168830 ps
CPU time 6.68 seconds
Started Jun 11 12:23:34 PM PDT 24
Finished Jun 11 12:23:45 PM PDT 24
Peak memory 217384 kb
Host smart-5164dcc8-afb9-41c8-a10a-8100a83ed513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791320016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3791320016
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.638923326
Short name T260
Test name
Test status
Simulation time 244117746 ps
CPU time 1.1 seconds
Started Jun 11 12:23:46 PM PDT 24
Finished Jun 11 12:23:55 PM PDT 24
Peak memory 217560 kb
Host smart-28532995-7aba-41f0-afba-658f289e56b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638923326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.638923326
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3889291330
Short name T364
Test name
Test status
Simulation time 196325227 ps
CPU time 0.93 seconds
Started Jun 11 12:23:39 PM PDT 24
Finished Jun 11 12:23:43 PM PDT 24
Peak memory 200100 kb
Host smart-69c2c4bb-c8bd-41f2-9609-24c16fcf0fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889291330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3889291330
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2632236119
Short name T241
Test name
Test status
Simulation time 1757953248 ps
CPU time 6.82 seconds
Started Jun 11 12:23:48 PM PDT 24
Finished Jun 11 12:24:03 PM PDT 24
Peak memory 200552 kb
Host smart-afc0aad6-5291-4bf2-9359-d4aaae614d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632236119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2632236119
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3524005852
Short name T64
Test name
Test status
Simulation time 179244282 ps
CPU time 1.2 seconds
Started Jun 11 12:23:48 PM PDT 24
Finished Jun 11 12:23:58 PM PDT 24
Peak memory 200332 kb
Host smart-a1817970-866a-4714-9631-ab8cc3e6ae7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524005852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3524005852
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2658052019
Short name T313
Test name
Test status
Simulation time 251659672 ps
CPU time 1.43 seconds
Started Jun 11 12:23:48 PM PDT 24
Finished Jun 11 12:23:57 PM PDT 24
Peak memory 200480 kb
Host smart-4752e395-98d7-41cc-ab49-663106dcad66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658052019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2658052019
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2900020602
Short name T404
Test name
Test status
Simulation time 512741583 ps
CPU time 2.74 seconds
Started Jun 11 12:23:34 PM PDT 24
Finished Jun 11 12:23:41 PM PDT 24
Peak memory 200196 kb
Host smart-bbe91277-73b0-49cf-8a04-8134ab7cad55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900020602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2900020602
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.4180721982
Short name T197
Test name
Test status
Simulation time 148440712 ps
CPU time 1.24 seconds
Started Jun 11 12:23:39 PM PDT 24
Finished Jun 11 12:23:43 PM PDT 24
Peak memory 200460 kb
Host smart-8848ef31-ed0d-4390-ba20-25491c84170c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180721982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.4180721982
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.1493937670
Short name T322
Test name
Test status
Simulation time 54660373 ps
CPU time 0.69 seconds
Started Jun 11 12:23:48 PM PDT 24
Finished Jun 11 12:23:57 PM PDT 24
Peak memory 200148 kb
Host smart-3282f1b6-3e53-44f3-a644-e86e3d047a01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493937670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.1493937670
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1809094475
Short name T62
Test name
Test status
Simulation time 2358262035 ps
CPU time 7.55 seconds
Started Jun 11 12:23:48 PM PDT 24
Finished Jun 11 12:24:04 PM PDT 24
Peak memory 222028 kb
Host smart-012fef1f-3905-42d7-a8f8-4f8c781cd1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809094475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1809094475
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1933356049
Short name T345
Test name
Test status
Simulation time 243569260 ps
CPU time 1.01 seconds
Started Jun 11 12:23:51 PM PDT 24
Finished Jun 11 12:23:59 PM PDT 24
Peak memory 217484 kb
Host smart-a22c90b2-afad-4f23-8a37-8b199f50807c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933356049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1933356049
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.1387189197
Short name T499
Test name
Test status
Simulation time 133282616 ps
CPU time 0.8 seconds
Started Jun 11 12:23:46 PM PDT 24
Finished Jun 11 12:23:54 PM PDT 24
Peak memory 200080 kb
Host smart-1115497c-7a5a-4d10-a605-71ce3479b9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387189197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1387189197
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1647526995
Short name T487
Test name
Test status
Simulation time 868654282 ps
CPU time 3.95 seconds
Started Jun 11 12:23:49 PM PDT 24
Finished Jun 11 12:24:01 PM PDT 24
Peak memory 200484 kb
Host smart-7b75d671-327a-466e-be3d-f21b22ce7003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647526995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1647526995
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1209072831
Short name T484
Test name
Test status
Simulation time 153326160 ps
CPU time 1.12 seconds
Started Jun 11 12:23:51 PM PDT 24
Finished Jun 11 12:23:59 PM PDT 24
Peak memory 200248 kb
Host smart-dcd64692-db81-4769-be97-feab01cd2fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209072831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1209072831
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.520730206
Short name T526
Test name
Test status
Simulation time 128538351 ps
CPU time 1.15 seconds
Started Jun 11 12:23:41 PM PDT 24
Finished Jun 11 12:23:45 PM PDT 24
Peak memory 200468 kb
Host smart-dca467ad-1324-405d-8e88-dbf7eec4ba67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520730206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.520730206
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.571375463
Short name T434
Test name
Test status
Simulation time 3542721014 ps
CPU time 14.58 seconds
Started Jun 11 12:23:48 PM PDT 24
Finished Jun 11 12:24:11 PM PDT 24
Peak memory 200632 kb
Host smart-f9b8d163-d853-4aaf-b304-081a1af1bccc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571375463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.571375463
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2114869543
Short name T420
Test name
Test status
Simulation time 336575599 ps
CPU time 2.14 seconds
Started Jun 11 12:23:48 PM PDT 24
Finished Jun 11 12:23:59 PM PDT 24
Peak memory 208552 kb
Host smart-c87c5c4c-8ba1-4051-a3bf-454a1f50ce29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114869543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2114869543
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.58308188
Short name T456
Test name
Test status
Simulation time 275859607 ps
CPU time 1.39 seconds
Started Jun 11 12:23:48 PM PDT 24
Finished Jun 11 12:23:58 PM PDT 24
Peak memory 200268 kb
Host smart-8dade542-8610-42b1-a547-03eb5c92ce14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58308188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.58308188
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.3376866489
Short name T507
Test name
Test status
Simulation time 69325472 ps
CPU time 0.77 seconds
Started Jun 11 12:23:47 PM PDT 24
Finished Jun 11 12:23:56 PM PDT 24
Peak memory 200084 kb
Host smart-9da14542-216f-4f51-b622-80da50f9eb73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376866489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3376866489
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.4120667561
Short name T432
Test name
Test status
Simulation time 2159958797 ps
CPU time 7.32 seconds
Started Jun 11 12:23:46 PM PDT 24
Finished Jun 11 12:24:01 PM PDT 24
Peak memory 221912 kb
Host smart-eafb1619-d1fb-415a-9265-cc50c088567c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120667561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.4120667561
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2095943744
Short name T541
Test name
Test status
Simulation time 247860818 ps
CPU time 1.06 seconds
Started Jun 11 12:23:46 PM PDT 24
Finished Jun 11 12:23:55 PM PDT 24
Peak memory 217528 kb
Host smart-d93d40ef-1a22-4624-bd59-6514a39034a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095943744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2095943744
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2859109119
Short name T259
Test name
Test status
Simulation time 82662563 ps
CPU time 0.75 seconds
Started Jun 11 12:23:43 PM PDT 24
Finished Jun 11 12:23:48 PM PDT 24
Peak memory 200168 kb
Host smart-d1eb7f3b-b34e-47de-901e-8b30b1af1693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859109119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2859109119
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.3639430789
Short name T114
Test name
Test status
Simulation time 1774088327 ps
CPU time 6.31 seconds
Started Jun 11 12:23:49 PM PDT 24
Finished Jun 11 12:24:03 PM PDT 24
Peak memory 200484 kb
Host smart-d5941553-be5f-4e32-b5e5-36c556fe0e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639430789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3639430789
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3748608941
Short name T251
Test name
Test status
Simulation time 152541877 ps
CPU time 1.15 seconds
Started Jun 11 12:23:48 PM PDT 24
Finished Jun 11 12:23:58 PM PDT 24
Peak memory 200372 kb
Host smart-bb895cb9-7894-44a4-86e6-99eed957e2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748608941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3748608941
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3892866676
Short name T24
Test name
Test status
Simulation time 191731663 ps
CPU time 1.37 seconds
Started Jun 11 12:23:43 PM PDT 24
Finished Jun 11 12:23:48 PM PDT 24
Peak memory 200772 kb
Host smart-e70dc63e-d05c-4bb3-8fc1-0416fd8eebea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892866676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3892866676
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1814448987
Short name T230
Test name
Test status
Simulation time 1415505240 ps
CPU time 5.29 seconds
Started Jun 11 12:23:52 PM PDT 24
Finished Jun 11 12:24:04 PM PDT 24
Peak memory 200196 kb
Host smart-b9f3cb49-a5b0-4b67-851e-b77e21777855
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814448987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1814448987
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3242194096
Short name T199
Test name
Test status
Simulation time 366868302 ps
CPU time 2.19 seconds
Started Jun 11 12:23:50 PM PDT 24
Finished Jun 11 12:23:59 PM PDT 24
Peak memory 200236 kb
Host smart-aaeca763-43f3-4822-b5f5-3872b06483b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242194096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3242194096
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1475765310
Short name T170
Test name
Test status
Simulation time 119108869 ps
CPU time 1.2 seconds
Started Jun 11 12:23:44 PM PDT 24
Finished Jun 11 12:23:53 PM PDT 24
Peak memory 200204 kb
Host smart-faf72b37-fd71-46a0-b430-a00cc9ca2994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475765310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1475765310
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.995864659
Short name T356
Test name
Test status
Simulation time 59987712 ps
CPU time 0.67 seconds
Started Jun 11 12:23:46 PM PDT 24
Finished Jun 11 12:23:55 PM PDT 24
Peak memory 200140 kb
Host smart-78ad94d4-90fb-4883-ae9d-a2ed9a8e041b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995864659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.995864659
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.568505698
Short name T398
Test name
Test status
Simulation time 1898787625 ps
CPU time 8.02 seconds
Started Jun 11 12:23:50 PM PDT 24
Finished Jun 11 12:24:05 PM PDT 24
Peak memory 217412 kb
Host smart-b174dad3-a2fd-4cec-a1f2-a5476a3ed9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568505698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.568505698
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2228457869
Short name T213
Test name
Test status
Simulation time 244733433 ps
CPU time 1 seconds
Started Jun 11 12:23:47 PM PDT 24
Finished Jun 11 12:23:56 PM PDT 24
Peak memory 217528 kb
Host smart-e2c24f8c-3b02-4cdd-9f97-aed3e96b873c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228457869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2228457869
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1769637112
Short name T363
Test name
Test status
Simulation time 861573547 ps
CPU time 3.97 seconds
Started Jun 11 12:23:44 PM PDT 24
Finished Jun 11 12:23:55 PM PDT 24
Peak memory 200512 kb
Host smart-29a1b57b-3107-478d-a086-39a64bf3bf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769637112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1769637112
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2312997845
Short name T508
Test name
Test status
Simulation time 186322372 ps
CPU time 1.16 seconds
Started Jun 11 12:23:48 PM PDT 24
Finished Jun 11 12:23:57 PM PDT 24
Peak memory 200372 kb
Host smart-c77bd7f6-5ab6-40a7-929a-839e68ec4e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312997845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.2312997845
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1982302499
Short name T379
Test name
Test status
Simulation time 189356175 ps
CPU time 1.34 seconds
Started Jun 11 12:23:51 PM PDT 24
Finished Jun 11 12:23:58 PM PDT 24
Peak memory 200428 kb
Host smart-30b48e9b-cf13-4f8f-af88-f52bd24a1129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982302499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1982302499
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3642511326
Short name T512
Test name
Test status
Simulation time 11282755767 ps
CPU time 43.8 seconds
Started Jun 11 12:23:51 PM PDT 24
Finished Jun 11 12:24:41 PM PDT 24
Peak memory 200552 kb
Host smart-214eaaf2-2f92-4ba5-a42e-1bd7cf9c86ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642511326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3642511326
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.3921700434
Short name T286
Test name
Test status
Simulation time 129661177 ps
CPU time 1.47 seconds
Started Jun 11 12:23:42 PM PDT 24
Finished Jun 11 12:23:47 PM PDT 24
Peak memory 200300 kb
Host smart-600069ba-837a-48bb-b6f4-1ee94ff89181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921700434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3921700434
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.4194389527
Short name T418
Test name
Test status
Simulation time 203200843 ps
CPU time 1.25 seconds
Started Jun 11 12:23:41 PM PDT 24
Finished Jun 11 12:23:45 PM PDT 24
Peak memory 200280 kb
Host smart-d9a0e2ca-cb79-43a1-ab65-7789dcbd09da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194389527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.4194389527
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.4029970999
Short name T518
Test name
Test status
Simulation time 70948082 ps
CPU time 0.77 seconds
Started Jun 11 12:23:45 PM PDT 24
Finished Jun 11 12:23:53 PM PDT 24
Peak memory 200096 kb
Host smart-e3785ce3-faed-4d36-814d-8a22ce20b17c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029970999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.4029970999
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3750516190
Short name T47
Test name
Test status
Simulation time 1900874405 ps
CPU time 6.64 seconds
Started Jun 11 12:23:43 PM PDT 24
Finished Jun 11 12:23:55 PM PDT 24
Peak memory 221836 kb
Host smart-8e8b8844-99fe-49a6-909f-36cc584ee1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750516190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3750516190
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.838407179
Short name T90
Test name
Test status
Simulation time 243816240 ps
CPU time 1.03 seconds
Started Jun 11 12:23:43 PM PDT 24
Finished Jun 11 12:23:49 PM PDT 24
Peak memory 217528 kb
Host smart-95721401-985b-4f77-9394-bb3e9ea0ce6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838407179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.838407179
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.686981974
Short name T351
Test name
Test status
Simulation time 100158334 ps
CPU time 0.76 seconds
Started Jun 11 12:23:43 PM PDT 24
Finished Jun 11 12:23:49 PM PDT 24
Peak memory 200052 kb
Host smart-8075cc44-47fb-4e3c-ae1f-f47b7e4a25f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686981974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.686981974
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3504022940
Short name T506
Test name
Test status
Simulation time 939120958 ps
CPU time 4.1 seconds
Started Jun 11 12:23:51 PM PDT 24
Finished Jun 11 12:24:02 PM PDT 24
Peak memory 200424 kb
Host smart-8285cb82-5891-4c15-b6a3-56bcbf56ab1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504022940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3504022940
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3351379519
Short name T291
Test name
Test status
Simulation time 159278938 ps
CPU time 1.11 seconds
Started Jun 11 12:23:46 PM PDT 24
Finished Jun 11 12:23:55 PM PDT 24
Peak memory 200272 kb
Host smart-7624104e-6e5e-40a5-8337-e220acdb04bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351379519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3351379519
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.340625083
Short name T399
Test name
Test status
Simulation time 128357965 ps
CPU time 1.13 seconds
Started Jun 11 12:23:45 PM PDT 24
Finished Jun 11 12:23:55 PM PDT 24
Peak memory 200444 kb
Host smart-93268632-32aa-418f-a52a-b010e015f233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340625083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.340625083
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2855348560
Short name T84
Test name
Test status
Simulation time 2215423009 ps
CPU time 9.93 seconds
Started Jun 11 12:23:44 PM PDT 24
Finished Jun 11 12:24:00 PM PDT 24
Peak memory 208844 kb
Host smart-547be0ba-844a-41ac-bf8e-fd40f569f6bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855348560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2855348560
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.4064280218
Short name T463
Test name
Test status
Simulation time 407493834 ps
CPU time 2.23 seconds
Started Jun 11 12:23:47 PM PDT 24
Finished Jun 11 12:23:58 PM PDT 24
Peak memory 200292 kb
Host smart-89ec1997-8510-4c20-b673-5352ebbdef19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064280218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.4064280218
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2019103260
Short name T85
Test name
Test status
Simulation time 78412500 ps
CPU time 0.86 seconds
Started Jun 11 12:23:51 PM PDT 24
Finished Jun 11 12:23:58 PM PDT 24
Peak memory 200244 kb
Host smart-c1e37cfd-2795-4a0a-8aee-795d09773215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019103260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2019103260
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2732581967
Short name T327
Test name
Test status
Simulation time 74831228 ps
CPU time 0.75 seconds
Started Jun 11 12:23:51 PM PDT 24
Finished Jun 11 12:23:58 PM PDT 24
Peak memory 200068 kb
Host smart-449d51cc-7327-4cc7-af96-ec2b013c3719
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732581967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2732581967
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.847583469
Short name T360
Test name
Test status
Simulation time 1232586926 ps
CPU time 4.99 seconds
Started Jun 11 12:23:47 PM PDT 24
Finished Jun 11 12:23:59 PM PDT 24
Peak memory 216876 kb
Host smart-84381499-d992-4df5-ba35-d6164894f165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847583469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.847583469
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.318360093
Short name T149
Test name
Test status
Simulation time 244074389 ps
CPU time 1.03 seconds
Started Jun 11 12:23:50 PM PDT 24
Finished Jun 11 12:23:58 PM PDT 24
Peak memory 217384 kb
Host smart-736c5c96-81a7-48d2-b300-8a976b268b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318360093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.318360093
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3592616579
Short name T476
Test name
Test status
Simulation time 223203624 ps
CPU time 0.89 seconds
Started Jun 11 12:23:43 PM PDT 24
Finished Jun 11 12:23:49 PM PDT 24
Peak memory 199952 kb
Host smart-8af23c98-4e15-49ef-9ac7-095dd062c593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592616579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3592616579
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3509543346
Short name T117
Test name
Test status
Simulation time 1810752358 ps
CPU time 6.24 seconds
Started Jun 11 12:23:47 PM PDT 24
Finished Jun 11 12:24:01 PM PDT 24
Peak memory 200424 kb
Host smart-7a3354c0-4349-48e0-a4ff-3faca1bb3eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509543346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3509543346
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.977755840
Short name T515
Test name
Test status
Simulation time 139987144 ps
CPU time 1.08 seconds
Started Jun 11 12:23:46 PM PDT 24
Finished Jun 11 12:23:55 PM PDT 24
Peak memory 200336 kb
Host smart-01f33173-3354-4a48-8212-4ee6897c3666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977755840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.977755840
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.18027003
Short name T211
Test name
Test status
Simulation time 114483620 ps
CPU time 1.23 seconds
Started Jun 11 12:23:45 PM PDT 24
Finished Jun 11 12:23:55 PM PDT 24
Peak memory 200560 kb
Host smart-2c7c934d-9913-40eb-af0c-b5d7c6e3811b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18027003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.18027003
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3519031143
Short name T196
Test name
Test status
Simulation time 6830751235 ps
CPU time 22.73 seconds
Started Jun 11 12:23:45 PM PDT 24
Finished Jun 11 12:24:16 PM PDT 24
Peak memory 210580 kb
Host smart-3c442a50-277d-4abd-9888-a4806b01c3cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519031143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3519031143
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.4207883040
Short name T307
Test name
Test status
Simulation time 385198750 ps
CPU time 2.28 seconds
Started Jun 11 12:23:44 PM PDT 24
Finished Jun 11 12:23:54 PM PDT 24
Peak memory 200124 kb
Host smart-1ddf9a94-c19d-46ec-a83d-aeacc5c4e1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207883040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.4207883040
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2160175462
Short name T177
Test name
Test status
Simulation time 149108102 ps
CPU time 1.17 seconds
Started Jun 11 12:23:49 PM PDT 24
Finished Jun 11 12:23:58 PM PDT 24
Peak memory 200448 kb
Host smart-afb836e5-224d-4587-a3b9-99654efcca9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160175462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2160175462
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.4221288033
Short name T41
Test name
Test status
Simulation time 72064683 ps
CPU time 0.75 seconds
Started Jun 11 12:22:43 PM PDT 24
Finished Jun 11 12:22:46 PM PDT 24
Peak memory 199924 kb
Host smart-7fa0384e-35ac-4b0e-ab74-b424bdb90256
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221288033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.4221288033
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.4033664299
Short name T63
Test name
Test status
Simulation time 1902634025 ps
CPU time 6.5 seconds
Started Jun 11 12:22:57 PM PDT 24
Finished Jun 11 12:23:08 PM PDT 24
Peak memory 229856 kb
Host smart-468d068c-757a-4c6c-a7fe-e006d7faacce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033664299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.4033664299
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3707027012
Short name T270
Test name
Test status
Simulation time 243116434 ps
CPU time 1.06 seconds
Started Jun 11 12:22:45 PM PDT 24
Finished Jun 11 12:22:49 PM PDT 24
Peak memory 217116 kb
Host smart-4550ed43-9f73-4ec3-b060-9cf6bf48a5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707027012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3707027012
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3589754235
Short name T295
Test name
Test status
Simulation time 153662770 ps
CPU time 0.8 seconds
Started Jun 11 12:23:46 PM PDT 24
Finished Jun 11 12:23:55 PM PDT 24
Peak memory 199984 kb
Host smart-34142648-1032-4e94-828a-bc88b8183fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589754235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3589754235
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2949037279
Short name T80
Test name
Test status
Simulation time 8299923531 ps
CPU time 14.94 seconds
Started Jun 11 12:22:31 PM PDT 24
Finished Jun 11 12:22:50 PM PDT 24
Peak memory 217120 kb
Host smart-23bafb9b-099b-4efb-8855-bbf7ab5cfb7d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949037279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2949037279
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2793779804
Short name T243
Test name
Test status
Simulation time 110078229 ps
CPU time 0.99 seconds
Started Jun 11 12:22:45 PM PDT 24
Finished Jun 11 12:22:49 PM PDT 24
Peak memory 200100 kb
Host smart-94c26869-23d1-431b-ae10-1d210b156e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793779804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2793779804
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.281276969
Short name T206
Test name
Test status
Simulation time 236982359 ps
CPU time 1.68 seconds
Started Jun 11 12:19:19 PM PDT 24
Finished Jun 11 12:19:22 PM PDT 24
Peak memory 200480 kb
Host smart-a78afdb2-2d5f-4d91-b364-441a0e93f824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281276969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.281276969
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2293601575
Short name T371
Test name
Test status
Simulation time 4544408880 ps
CPU time 17.81 seconds
Started Jun 11 12:22:45 PM PDT 24
Finished Jun 11 12:23:05 PM PDT 24
Peak memory 208452 kb
Host smart-86b3b06d-b4fa-49d9-8616-9a19ee0209ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293601575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2293601575
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2698217100
Short name T191
Test name
Test status
Simulation time 310242097 ps
CPU time 1.94 seconds
Started Jun 11 12:22:55 PM PDT 24
Finished Jun 11 12:23:00 PM PDT 24
Peak memory 199856 kb
Host smart-bc98d94d-c274-4d57-8ab8-d1ebc8cab24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698217100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2698217100
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.113462413
Short name T8
Test name
Test status
Simulation time 127497558 ps
CPU time 0.98 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:23:01 PM PDT 24
Peak memory 200028 kb
Host smart-3f42145a-782c-4f4d-96d2-479765147b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113462413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.113462413
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3402772033
Short name T175
Test name
Test status
Simulation time 77029761 ps
CPU time 0.75 seconds
Started Jun 11 12:23:43 PM PDT 24
Finished Jun 11 12:23:48 PM PDT 24
Peak memory 200004 kb
Host smart-80f3dc92-25a5-4d64-9ba7-3a6f719086fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402772033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3402772033
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3086180812
Short name T378
Test name
Test status
Simulation time 1910206114 ps
CPU time 7.83 seconds
Started Jun 11 12:23:48 PM PDT 24
Finished Jun 11 12:24:04 PM PDT 24
Peak memory 221824 kb
Host smart-15f1ecd8-2f50-4d87-8cb6-8c4089d2b182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086180812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3086180812
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.585884812
Short name T438
Test name
Test status
Simulation time 243695195 ps
CPU time 1.13 seconds
Started Jun 11 12:23:52 PM PDT 24
Finished Jun 11 12:24:00 PM PDT 24
Peak memory 217400 kb
Host smart-415e5157-7ffe-4626-b791-a6b38114db7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585884812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.585884812
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.782740653
Short name T481
Test name
Test status
Simulation time 108571389 ps
CPU time 0.74 seconds
Started Jun 11 12:23:48 PM PDT 24
Finished Jun 11 12:23:57 PM PDT 24
Peak memory 200176 kb
Host smart-0e410542-d726-4bcb-bdf2-ff118e7e8791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782740653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.782740653
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3559900629
Short name T314
Test name
Test status
Simulation time 1595451372 ps
CPU time 5.91 seconds
Started Jun 11 12:23:46 PM PDT 24
Finished Jun 11 12:24:00 PM PDT 24
Peak memory 200404 kb
Host smart-ccf5bbfc-0221-42b1-b369-384d08b354fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559900629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3559900629
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.423083256
Short name T225
Test name
Test status
Simulation time 148912359 ps
CPU time 1.07 seconds
Started Jun 11 12:23:48 PM PDT 24
Finished Jun 11 12:23:57 PM PDT 24
Peak memory 200372 kb
Host smart-8bf63fc5-1651-4ef4-a01c-7ee837f9817b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423083256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.423083256
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.676954939
Short name T342
Test name
Test status
Simulation time 259283086 ps
CPU time 1.45 seconds
Started Jun 11 12:23:52 PM PDT 24
Finished Jun 11 12:24:00 PM PDT 24
Peak memory 200260 kb
Host smart-6a4cd051-5bee-48ee-b390-5146b1c3ae32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676954939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.676954939
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.907660858
Short name T55
Test name
Test status
Simulation time 417321248 ps
CPU time 1.76 seconds
Started Jun 11 12:23:52 PM PDT 24
Finished Jun 11 12:24:00 PM PDT 24
Peak memory 200432 kb
Host smart-ca58e50a-df3b-4df4-a95a-da1f9ad08fa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907660858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.907660858
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.912509608
Short name T486
Test name
Test status
Simulation time 144318772 ps
CPU time 1.74 seconds
Started Jun 11 12:23:42 PM PDT 24
Finished Jun 11 12:23:47 PM PDT 24
Peak memory 208408 kb
Host smart-cc5c4e16-6225-4d9d-b841-616da5e997eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912509608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.912509608
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1837295727
Short name T141
Test name
Test status
Simulation time 209565044 ps
CPU time 1.17 seconds
Started Jun 11 12:23:47 PM PDT 24
Finished Jun 11 12:23:57 PM PDT 24
Peak memory 200260 kb
Host smart-18428f0d-4999-4c91-8efb-7a9c1cc220cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837295727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1837295727
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3318117524
Short name T247
Test name
Test status
Simulation time 79699679 ps
CPU time 0.73 seconds
Started Jun 11 12:23:52 PM PDT 24
Finished Jun 11 12:23:59 PM PDT 24
Peak memory 200132 kb
Host smart-3ac7ed6c-82ef-4892-9a0e-e84f8de40461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318117524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3318117524
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2903125991
Short name T43
Test name
Test status
Simulation time 2187127468 ps
CPU time 8.48 seconds
Started Jun 11 12:23:52 PM PDT 24
Finished Jun 11 12:24:07 PM PDT 24
Peak memory 217596 kb
Host smart-42e8b2e3-edde-466b-9acf-0737e6d89228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903125991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2903125991
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.657101966
Short name T533
Test name
Test status
Simulation time 245991442 ps
CPU time 1.1 seconds
Started Jun 11 12:23:53 PM PDT 24
Finished Jun 11 12:24:00 PM PDT 24
Peak memory 217520 kb
Host smart-8887f0bc-192a-4ce9-a212-caf4dad5550f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657101966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.657101966
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2459671895
Short name T264
Test name
Test status
Simulation time 224452309 ps
CPU time 0.85 seconds
Started Jun 11 12:23:44 PM PDT 24
Finished Jun 11 12:23:52 PM PDT 24
Peak memory 200024 kb
Host smart-ec3bd8c1-8425-4dcd-bfb4-0d1029feaa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459671895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2459671895
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.2626045565
Short name T353
Test name
Test status
Simulation time 1857210787 ps
CPU time 6.94 seconds
Started Jun 11 12:23:52 PM PDT 24
Finished Jun 11 12:24:06 PM PDT 24
Peak memory 200072 kb
Host smart-0f752985-c17c-4a59-9d8b-30315b8b7ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626045565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2626045565
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.248902265
Short name T193
Test name
Test status
Simulation time 174325131 ps
CPU time 1.14 seconds
Started Jun 11 12:23:48 PM PDT 24
Finished Jun 11 12:23:57 PM PDT 24
Peak memory 200276 kb
Host smart-195a3b45-07ff-4f6b-82db-c184851118ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248902265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.248902265
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1064463127
Short name T536
Test name
Test status
Simulation time 123332954 ps
CPU time 1.1 seconds
Started Jun 11 12:23:52 PM PDT 24
Finished Jun 11 12:24:00 PM PDT 24
Peak memory 200292 kb
Host smart-07ff8624-bf95-4175-b47c-545f52bd3e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064463127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1064463127
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.3610985933
Short name T405
Test name
Test status
Simulation time 15544036091 ps
CPU time 48.99 seconds
Started Jun 11 12:23:52 PM PDT 24
Finished Jun 11 12:24:48 PM PDT 24
Peak memory 208792 kb
Host smart-835dbae8-71c6-426c-81ee-cc43687e697e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610985933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3610985933
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.704514728
Short name T298
Test name
Test status
Simulation time 416154307 ps
CPU time 2.23 seconds
Started Jun 11 12:23:50 PM PDT 24
Finished Jun 11 12:23:59 PM PDT 24
Peak memory 208428 kb
Host smart-1afe9c0d-3b07-445f-988e-4f12c4c19866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704514728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.704514728
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.253241553
Short name T365
Test name
Test status
Simulation time 106234818 ps
CPU time 0.92 seconds
Started Jun 11 12:23:43 PM PDT 24
Finished Jun 11 12:23:48 PM PDT 24
Peak memory 200148 kb
Host smart-3b09ec3d-e6ab-4359-bc54-a3f7c0668ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253241553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.253241553
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3407151850
Short name T242
Test name
Test status
Simulation time 66189753 ps
CPU time 0.74 seconds
Started Jun 11 12:23:51 PM PDT 24
Finished Jun 11 12:23:58 PM PDT 24
Peak memory 200064 kb
Host smart-dc2ca401-8b9e-43df-a7b1-b32611264a97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407151850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3407151850
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2733146516
Short name T44
Test name
Test status
Simulation time 2377014436 ps
CPU time 7.55 seconds
Started Jun 11 12:23:51 PM PDT 24
Finished Jun 11 12:24:05 PM PDT 24
Peak memory 221928 kb
Host smart-c42d469f-8487-4816-8436-d8b7c1296cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733146516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2733146516
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1302016158
Short name T222
Test name
Test status
Simulation time 244201922 ps
CPU time 1.17 seconds
Started Jun 11 12:23:50 PM PDT 24
Finished Jun 11 12:23:58 PM PDT 24
Peak memory 217504 kb
Host smart-3313b2fa-3dc3-4cc4-80ac-529ad2f0d6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302016158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1302016158
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3433627087
Short name T408
Test name
Test status
Simulation time 183658330 ps
CPU time 0.83 seconds
Started Jun 11 12:23:53 PM PDT 24
Finished Jun 11 12:24:00 PM PDT 24
Peak memory 200100 kb
Host smart-aa0ce1e6-afb2-4240-b8fb-60929f07aeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433627087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3433627087
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.802598288
Short name T52
Test name
Test status
Simulation time 1652577265 ps
CPU time 6.08 seconds
Started Jun 11 12:23:53 PM PDT 24
Finished Jun 11 12:24:06 PM PDT 24
Peak memory 200460 kb
Host smart-6dbd9b76-40c3-431d-8ac2-0f0b39e4f574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802598288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.802598288
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1285349293
Short name T65
Test name
Test status
Simulation time 103783443 ps
CPU time 1.01 seconds
Started Jun 11 12:23:51 PM PDT 24
Finished Jun 11 12:23:58 PM PDT 24
Peak memory 200244 kb
Host smart-cefb076c-c3c2-481f-a14a-d2c5f78af26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285349293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1285349293
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3700275611
Short name T151
Test name
Test status
Simulation time 108612415 ps
CPU time 1.09 seconds
Started Jun 11 12:23:53 PM PDT 24
Finished Jun 11 12:24:00 PM PDT 24
Peak memory 200452 kb
Host smart-d229d4ef-7eef-4962-a016-4414d9728162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700275611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3700275611
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1480962293
Short name T96
Test name
Test status
Simulation time 4163685839 ps
CPU time 16.44 seconds
Started Jun 11 12:23:48 PM PDT 24
Finished Jun 11 12:24:12 PM PDT 24
Peak memory 200588 kb
Host smart-90f7b058-34b2-4765-a5c0-579bc21fff6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480962293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1480962293
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3809887080
Short name T208
Test name
Test status
Simulation time 126189474 ps
CPU time 1.59 seconds
Started Jun 11 12:23:51 PM PDT 24
Finished Jun 11 12:23:59 PM PDT 24
Peak memory 200232 kb
Host smart-38d97642-e353-48e0-8189-7261f6200932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809887080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3809887080
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3106201512
Short name T328
Test name
Test status
Simulation time 176457868 ps
CPU time 1.19 seconds
Started Jun 11 12:23:53 PM PDT 24
Finished Jun 11 12:24:00 PM PDT 24
Peak memory 200280 kb
Host smart-32c4949b-318e-488b-89de-ff4b6d41ecbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106201512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3106201512
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.70054665
Short name T279
Test name
Test status
Simulation time 71399170 ps
CPU time 0.74 seconds
Started Jun 11 12:24:09 PM PDT 24
Finished Jun 11 12:24:12 PM PDT 24
Peak memory 200144 kb
Host smart-9f4822f2-6991-44a8-9c35-e4ead75f0443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70054665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.70054665
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3092082733
Short name T529
Test name
Test status
Simulation time 1214994723 ps
CPU time 5.04 seconds
Started Jun 11 12:23:53 PM PDT 24
Finished Jun 11 12:24:04 PM PDT 24
Peak memory 216900 kb
Host smart-747fcb1b-fbc2-467f-bb93-035031fd4213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092082733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3092082733
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.4289402524
Short name T164
Test name
Test status
Simulation time 244036350 ps
CPU time 1.09 seconds
Started Jun 11 12:23:56 PM PDT 24
Finished Jun 11 12:24:02 PM PDT 24
Peak memory 217544 kb
Host smart-04f37b71-f1af-473d-9ce1-23b32e1e76a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289402524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.4289402524
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2722700097
Short name T410
Test name
Test status
Simulation time 96653131 ps
CPU time 0.73 seconds
Started Jun 11 12:23:53 PM PDT 24
Finished Jun 11 12:24:00 PM PDT 24
Peak memory 200132 kb
Host smart-035268a0-4442-4f17-890d-84ba02c72967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722700097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2722700097
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2230754274
Short name T25
Test name
Test status
Simulation time 1344049300 ps
CPU time 4.95 seconds
Started Jun 11 12:23:56 PM PDT 24
Finished Jun 11 12:24:06 PM PDT 24
Peak memory 200516 kb
Host smart-50c0e88e-2ad0-4750-b6df-240f5b92cd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230754274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2230754274
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2391344268
Short name T7
Test name
Test status
Simulation time 149399871 ps
CPU time 1.09 seconds
Started Jun 11 12:24:09 PM PDT 24
Finished Jun 11 12:24:12 PM PDT 24
Peak memory 200348 kb
Host smart-15efb4ee-acef-4260-bb57-f89722870cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391344268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2391344268
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.4079333738
Short name T455
Test name
Test status
Simulation time 231242345 ps
CPU time 1.42 seconds
Started Jun 11 12:23:55 PM PDT 24
Finished Jun 11 12:24:02 PM PDT 24
Peak memory 200364 kb
Host smart-db496ecb-22a6-46c3-8bbe-582ec62393bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079333738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.4079333738
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3744152502
Short name T262
Test name
Test status
Simulation time 3724487059 ps
CPU time 15.6 seconds
Started Jun 11 12:23:57 PM PDT 24
Finished Jun 11 12:24:17 PM PDT 24
Peak memory 200712 kb
Host smart-b9d4cd4b-2bc5-466c-b699-eeb579218d6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744152502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3744152502
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.302935484
Short name T534
Test name
Test status
Simulation time 273983181 ps
CPU time 1.88 seconds
Started Jun 11 12:23:55 PM PDT 24
Finished Jun 11 12:24:03 PM PDT 24
Peak memory 200568 kb
Host smart-11ff7626-b910-4bc6-8f48-6e96003ee643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302935484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.302935484
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3380450314
Short name T190
Test name
Test status
Simulation time 212664521 ps
CPU time 1.17 seconds
Started Jun 11 12:23:55 PM PDT 24
Finished Jun 11 12:24:01 PM PDT 24
Peak memory 200168 kb
Host smart-5fe055f1-47bc-42e3-a7f2-646dc66f3ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380450314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3380450314
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.404612848
Short name T217
Test name
Test status
Simulation time 62455445 ps
CPU time 0.78 seconds
Started Jun 11 12:24:00 PM PDT 24
Finished Jun 11 12:24:04 PM PDT 24
Peak memory 200060 kb
Host smart-2b562936-6008-4f12-94f2-b8fb8b0ada0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404612848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.404612848
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.775323903
Short name T439
Test name
Test status
Simulation time 2372626762 ps
CPU time 8.15 seconds
Started Jun 11 12:23:58 PM PDT 24
Finished Jun 11 12:24:10 PM PDT 24
Peak memory 218080 kb
Host smart-34d60a82-6ca5-447c-89b6-8c0f0f6ba8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775323903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.775323903
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2692519213
Short name T421
Test name
Test status
Simulation time 243858910 ps
CPU time 1.12 seconds
Started Jun 11 12:23:53 PM PDT 24
Finished Jun 11 12:24:00 PM PDT 24
Peak memory 217388 kb
Host smart-1b8bdfb4-fd35-4dc3-bbcf-0e69065f1c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692519213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2692519213
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1104491910
Short name T282
Test name
Test status
Simulation time 174078572 ps
CPU time 0.89 seconds
Started Jun 11 12:24:08 PM PDT 24
Finished Jun 11 12:24:11 PM PDT 24
Peak memory 200160 kb
Host smart-873b2cb3-ef2d-48fc-9cf0-e250babe1598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104491910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1104491910
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3312850679
Short name T205
Test name
Test status
Simulation time 1286127363 ps
CPU time 5.3 seconds
Started Jun 11 12:23:55 PM PDT 24
Finished Jun 11 12:24:06 PM PDT 24
Peak memory 200324 kb
Host smart-87786695-8687-4798-8431-11cd42441773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312850679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3312850679
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3753561398
Short name T419
Test name
Test status
Simulation time 167950577 ps
CPU time 1.1 seconds
Started Jun 11 12:23:56 PM PDT 24
Finished Jun 11 12:24:02 PM PDT 24
Peak memory 200196 kb
Host smart-7fff496e-fd52-4a3e-8945-e56dbae83743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753561398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3753561398
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.3111113100
Short name T93
Test name
Test status
Simulation time 200816922 ps
CPU time 1.38 seconds
Started Jun 11 12:24:09 PM PDT 24
Finished Jun 11 12:24:12 PM PDT 24
Peak memory 200524 kb
Host smart-e80d0c75-dc91-4fe6-afdc-f94ea0395453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111113100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.3111113100
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2488214676
Short name T187
Test name
Test status
Simulation time 4611643495 ps
CPU time 18.77 seconds
Started Jun 11 12:23:55 PM PDT 24
Finished Jun 11 12:24:19 PM PDT 24
Peak memory 209448 kb
Host smart-0074db35-6c50-4225-ba13-bb9eca926f87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488214676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2488214676
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.458740074
Short name T471
Test name
Test status
Simulation time 361077492 ps
CPU time 1.99 seconds
Started Jun 11 12:24:01 PM PDT 24
Finished Jun 11 12:24:06 PM PDT 24
Peak memory 200312 kb
Host smart-39ecb85c-c5ab-40f2-a60d-9c3fb1b3ca03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458740074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.458740074
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1327142207
Short name T458
Test name
Test status
Simulation time 162898365 ps
CPU time 1.1 seconds
Started Jun 11 12:24:06 PM PDT 24
Finished Jun 11 12:24:09 PM PDT 24
Peak memory 200348 kb
Host smart-41d51e4e-2bc1-4b72-a046-2f11dfc59e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327142207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1327142207
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.902324323
Short name T306
Test name
Test status
Simulation time 78654549 ps
CPU time 0.78 seconds
Started Jun 11 12:24:09 PM PDT 24
Finished Jun 11 12:24:12 PM PDT 24
Peak memory 200164 kb
Host smart-308874be-b46e-4af3-99aa-534469959535
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902324323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.902324323
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2006862895
Short name T337
Test name
Test status
Simulation time 1901337197 ps
CPU time 6.6 seconds
Started Jun 11 12:23:52 PM PDT 24
Finished Jun 11 12:24:05 PM PDT 24
Peak memory 216836 kb
Host smart-efb6a105-3f7d-4f8c-8354-cf64b11a3278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006862895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2006862895
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3558789551
Short name T528
Test name
Test status
Simulation time 244693807 ps
CPU time 1.09 seconds
Started Jun 11 12:23:53 PM PDT 24
Finished Jun 11 12:24:00 PM PDT 24
Peak memory 217384 kb
Host smart-40edba3c-2978-4b32-a366-420c61c3fa33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558789551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3558789551
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.2132723164
Short name T301
Test name
Test status
Simulation time 75704407 ps
CPU time 0.69 seconds
Started Jun 11 12:23:56 PM PDT 24
Finished Jun 11 12:24:02 PM PDT 24
Peak memory 199992 kb
Host smart-d518cd63-9b81-4783-b357-ee88072ca189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132723164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2132723164
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.3100790057
Short name T396
Test name
Test status
Simulation time 1350999328 ps
CPU time 5.15 seconds
Started Jun 11 12:23:58 PM PDT 24
Finished Jun 11 12:24:07 PM PDT 24
Peak memory 200552 kb
Host smart-c69a244c-cf65-42c8-9835-36d8bc99b6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100790057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3100790057
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.4060101712
Short name T162
Test name
Test status
Simulation time 146398536 ps
CPU time 1.09 seconds
Started Jun 11 12:24:08 PM PDT 24
Finished Jun 11 12:24:12 PM PDT 24
Peak memory 200344 kb
Host smart-fabc87ea-74e0-4d09-88ad-3353e364492a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060101712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.4060101712
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2407701211
Short name T452
Test name
Test status
Simulation time 206776665 ps
CPU time 1.38 seconds
Started Jun 11 12:24:09 PM PDT 24
Finished Jun 11 12:24:12 PM PDT 24
Peak memory 200528 kb
Host smart-8d603005-3618-4803-9f17-e69944ee3354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407701211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2407701211
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.852746499
Short name T112
Test name
Test status
Simulation time 1839995172 ps
CPU time 7.96 seconds
Started Jun 11 12:23:56 PM PDT 24
Finished Jun 11 12:24:09 PM PDT 24
Peak memory 200436 kb
Host smart-56dd17cd-b9de-40d9-a5b1-55722d23b493
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852746499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.852746499
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1376161671
Short name T155
Test name
Test status
Simulation time 325358262 ps
CPU time 2.09 seconds
Started Jun 11 12:23:53 PM PDT 24
Finished Jun 11 12:24:02 PM PDT 24
Peak memory 200332 kb
Host smart-5ad7b1a8-c786-4574-aae0-ee04b898c70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376161671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1376161671
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3767284222
Short name T10
Test name
Test status
Simulation time 60771783 ps
CPU time 0.77 seconds
Started Jun 11 12:24:00 PM PDT 24
Finished Jun 11 12:24:04 PM PDT 24
Peak memory 200240 kb
Host smart-34734a81-528f-4e50-bfc5-6a2abcf53f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767284222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3767284222
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2852454859
Short name T377
Test name
Test status
Simulation time 78356862 ps
CPU time 0.76 seconds
Started Jun 11 12:24:09 PM PDT 24
Finished Jun 11 12:24:11 PM PDT 24
Peak memory 200012 kb
Host smart-f4fd45d2-9682-4cde-a586-8ef6958ab9e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852454859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2852454859
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.483154336
Short name T383
Test name
Test status
Simulation time 1221615511 ps
CPU time 5.25 seconds
Started Jun 11 12:24:04 PM PDT 24
Finished Jun 11 12:24:12 PM PDT 24
Peak memory 217788 kb
Host smart-a851b5dc-8845-4b05-b9a5-b4055e353fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483154336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.483154336
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.4044494116
Short name T186
Test name
Test status
Simulation time 243866863 ps
CPU time 1.09 seconds
Started Jun 11 12:24:07 PM PDT 24
Finished Jun 11 12:24:10 PM PDT 24
Peak memory 217564 kb
Host smart-556a90da-38b4-4f31-8d85-0ce93747fc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044494116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.4044494116
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.4191732655
Short name T393
Test name
Test status
Simulation time 147189469 ps
CPU time 0.79 seconds
Started Jun 11 12:24:08 PM PDT 24
Finished Jun 11 12:24:11 PM PDT 24
Peak memory 200156 kb
Host smart-2c00099e-0227-4b63-a5e9-7e0218f85807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191732655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.4191732655
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1164362817
Short name T447
Test name
Test status
Simulation time 1303795867 ps
CPU time 5.72 seconds
Started Jun 11 12:23:53 PM PDT 24
Finished Jun 11 12:24:05 PM PDT 24
Peak memory 200776 kb
Host smart-ef114d33-7e67-4ff1-ad33-ba5a1233a840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164362817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1164362817
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3174160710
Short name T395
Test name
Test status
Simulation time 112898107 ps
CPU time 0.95 seconds
Started Jun 11 12:24:05 PM PDT 24
Finished Jun 11 12:24:08 PM PDT 24
Peak memory 200360 kb
Host smart-4f4404e2-d498-4177-b2f8-89b6e531cfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174160710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3174160710
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.977794037
Short name T224
Test name
Test status
Simulation time 116150934 ps
CPU time 1.15 seconds
Started Jun 11 12:24:09 PM PDT 24
Finished Jun 11 12:24:12 PM PDT 24
Peak memory 200216 kb
Host smart-3042d12d-5514-43fc-ba06-487f904859ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977794037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.977794037
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3597847082
Short name T440
Test name
Test status
Simulation time 4833904462 ps
CPU time 14.77 seconds
Started Jun 11 12:24:08 PM PDT 24
Finished Jun 11 12:24:25 PM PDT 24
Peak memory 200624 kb
Host smart-0bb0ffc5-df79-42c6-bfe0-1ca03ee6ec4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597847082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3597847082
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.1746384844
Short name T144
Test name
Test status
Simulation time 483530864 ps
CPU time 2.57 seconds
Started Jun 11 12:24:04 PM PDT 24
Finished Jun 11 12:24:09 PM PDT 24
Peak memory 200264 kb
Host smart-059a993c-51ee-4579-91e3-b2236a9af32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746384844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.1746384844
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3350529150
Short name T265
Test name
Test status
Simulation time 151407322 ps
CPU time 1.06 seconds
Started Jun 11 12:24:09 PM PDT 24
Finished Jun 11 12:24:12 PM PDT 24
Peak memory 199816 kb
Host smart-5167764f-c72c-41e4-b5fc-d41467a4c024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350529150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3350529150
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1125997987
Short name T150
Test name
Test status
Simulation time 82272245 ps
CPU time 0.82 seconds
Started Jun 11 12:24:05 PM PDT 24
Finished Jun 11 12:24:08 PM PDT 24
Peak memory 200044 kb
Host smart-06632523-d399-48dc-8359-e173cee6ebd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125997987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1125997987
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1284755409
Short name T335
Test name
Test status
Simulation time 1225958779 ps
CPU time 5.44 seconds
Started Jun 11 12:24:06 PM PDT 24
Finished Jun 11 12:24:14 PM PDT 24
Peak memory 217936 kb
Host smart-79293760-32a6-4118-8fb7-1543cb27dc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284755409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1284755409
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1502095834
Short name T165
Test name
Test status
Simulation time 244956211 ps
CPU time 1.07 seconds
Started Jun 11 12:24:04 PM PDT 24
Finished Jun 11 12:24:08 PM PDT 24
Peak memory 217460 kb
Host smart-31b37e90-a464-477e-8212-7cd849d718d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502095834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1502095834
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1509200041
Short name T498
Test name
Test status
Simulation time 85742991 ps
CPU time 0.74 seconds
Started Jun 11 12:24:04 PM PDT 24
Finished Jun 11 12:24:07 PM PDT 24
Peak memory 200080 kb
Host smart-c31c8f7a-3abc-4e13-b591-c9e581d0eaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509200041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1509200041
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1756519129
Short name T110
Test name
Test status
Simulation time 2130837500 ps
CPU time 7.74 seconds
Started Jun 11 12:24:04 PM PDT 24
Finished Jun 11 12:24:14 PM PDT 24
Peak memory 200396 kb
Host smart-9e630312-86d7-4e92-9ae4-219ffc18ce32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756519129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1756519129
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3388188191
Short name T11
Test name
Test status
Simulation time 137164498 ps
CPU time 1.07 seconds
Started Jun 11 12:24:06 PM PDT 24
Finished Jun 11 12:24:09 PM PDT 24
Peak memory 200348 kb
Host smart-89326616-f9d1-4df7-82c6-2f5667be147e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388188191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3388188191
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.1882952704
Short name T474
Test name
Test status
Simulation time 117772849 ps
CPU time 1.15 seconds
Started Jun 11 12:24:05 PM PDT 24
Finished Jun 11 12:24:08 PM PDT 24
Peak memory 200528 kb
Host smart-4264f081-225d-4294-8d0c-5496f44cf7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882952704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1882952704
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3993691730
Short name T323
Test name
Test status
Simulation time 6198033880 ps
CPU time 27.4 seconds
Started Jun 11 12:24:03 PM PDT 24
Finished Jun 11 12:24:33 PM PDT 24
Peak memory 200664 kb
Host smart-60a7caf9-aff9-433c-a642-cc430fe5fb69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993691730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3993691730
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.4284744615
Short name T200
Test name
Test status
Simulation time 348942598 ps
CPU time 1.92 seconds
Started Jun 11 12:24:05 PM PDT 24
Finished Jun 11 12:24:09 PM PDT 24
Peak memory 200228 kb
Host smart-0f1150cf-f928-41f9-997c-6ab700774587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284744615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.4284744615
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.29639858
Short name T178
Test name
Test status
Simulation time 154374311 ps
CPU time 1.04 seconds
Started Jun 11 12:24:04 PM PDT 24
Finished Jun 11 12:24:07 PM PDT 24
Peak memory 200364 kb
Host smart-19e5fb41-0d6c-470a-b3ee-548c1c574d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29639858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.29639858
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.907819020
Short name T517
Test name
Test status
Simulation time 68652501 ps
CPU time 0.74 seconds
Started Jun 11 12:24:07 PM PDT 24
Finished Jun 11 12:24:09 PM PDT 24
Peak memory 200136 kb
Host smart-df3004d1-5a99-4f04-9d51-79a8eca15d53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907819020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.907819020
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2911630431
Short name T386
Test name
Test status
Simulation time 1895244725 ps
CPU time 7.38 seconds
Started Jun 11 12:24:09 PM PDT 24
Finished Jun 11 12:24:18 PM PDT 24
Peak memory 217820 kb
Host smart-7dab9d37-3063-4353-a7e3-0233d5a4caa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911630431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2911630431
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3643206318
Short name T234
Test name
Test status
Simulation time 247398778 ps
CPU time 1.01 seconds
Started Jun 11 12:24:06 PM PDT 24
Finished Jun 11 12:24:09 PM PDT 24
Peak memory 217544 kb
Host smart-168d7d85-5d81-4f17-9862-9866450c2d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643206318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3643206318
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.1826601517
Short name T22
Test name
Test status
Simulation time 166121855 ps
CPU time 0.82 seconds
Started Jun 11 12:24:06 PM PDT 24
Finished Jun 11 12:24:09 PM PDT 24
Peak memory 200096 kb
Host smart-07186baa-9ae2-40ff-bdf2-2c063e6ab8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826601517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.1826601517
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2759728334
Short name T226
Test name
Test status
Simulation time 169570603 ps
CPU time 1.1 seconds
Started Jun 11 12:24:07 PM PDT 24
Finished Jun 11 12:24:10 PM PDT 24
Peak memory 200360 kb
Host smart-d64a51a6-c3df-47ce-a49e-ce1a1402514e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759728334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2759728334
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.126722066
Short name T316
Test name
Test status
Simulation time 250662401 ps
CPU time 1.45 seconds
Started Jun 11 12:24:07 PM PDT 24
Finished Jun 11 12:24:10 PM PDT 24
Peak memory 200408 kb
Host smart-bde6f978-694f-4cb1-b0e6-8a1c22e38f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126722066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.126722066
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3157831752
Short name T527
Test name
Test status
Simulation time 6845043728 ps
CPU time 27.28 seconds
Started Jun 11 12:24:04 PM PDT 24
Finished Jun 11 12:24:34 PM PDT 24
Peak memory 208832 kb
Host smart-d9b61b84-c663-476c-9360-b6c428f60e12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157831752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3157831752
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.371083953
Short name T310
Test name
Test status
Simulation time 295997346 ps
CPU time 1.9 seconds
Started Jun 11 12:24:07 PM PDT 24
Finished Jun 11 12:24:11 PM PDT 24
Peak memory 200188 kb
Host smart-bf34c167-dbc4-4635-9872-9ed1f28c6bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371083953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.371083953
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.834697725
Short name T146
Test name
Test status
Simulation time 64439763 ps
CPU time 0.73 seconds
Started Jun 11 12:24:05 PM PDT 24
Finished Jun 11 12:24:08 PM PDT 24
Peak memory 200188 kb
Host smart-a0b4b4e5-087c-4410-9f53-ea7261757a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834697725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.834697725
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1081569050
Short name T203
Test name
Test status
Simulation time 81568688 ps
CPU time 0.82 seconds
Started Jun 11 12:24:14 PM PDT 24
Finished Jun 11 12:24:16 PM PDT 24
Peak memory 200152 kb
Host smart-31a913f4-5a25-44cb-aa02-c3c812ad8f31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081569050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1081569050
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1200294735
Short name T46
Test name
Test status
Simulation time 2354753562 ps
CPU time 8.04 seconds
Started Jun 11 12:24:14 PM PDT 24
Finished Jun 11 12:24:23 PM PDT 24
Peak memory 218184 kb
Host smart-efee8feb-f045-4377-abad-8057f03a3bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200294735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1200294735
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.278883418
Short name T156
Test name
Test status
Simulation time 244783859 ps
CPU time 0.98 seconds
Started Jun 11 12:24:14 PM PDT 24
Finished Jun 11 12:24:16 PM PDT 24
Peak memory 217544 kb
Host smart-6701c9fb-4e45-44e1-8f42-6f0ceb6645e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278883418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.278883418
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1596284909
Short name T376
Test name
Test status
Simulation time 174236636 ps
CPU time 0.82 seconds
Started Jun 11 12:24:07 PM PDT 24
Finished Jun 11 12:24:10 PM PDT 24
Peak memory 200124 kb
Host smart-cca778ba-501f-420c-b17a-74e816c0c4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596284909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1596284909
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2178645739
Short name T51
Test name
Test status
Simulation time 1497298477 ps
CPU time 5.41 seconds
Started Jun 11 12:24:04 PM PDT 24
Finished Jun 11 12:24:12 PM PDT 24
Peak memory 200512 kb
Host smart-15677282-6bd3-4c0a-b221-61b4e7e928c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178645739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2178645739
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2732227344
Short name T372
Test name
Test status
Simulation time 103564734 ps
CPU time 0.96 seconds
Started Jun 11 12:24:14 PM PDT 24
Finished Jun 11 12:24:17 PM PDT 24
Peak memory 200220 kb
Host smart-be385e7b-6fdb-4125-9472-e44661be14f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732227344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2732227344
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1785927362
Short name T479
Test name
Test status
Simulation time 196321048 ps
CPU time 1.31 seconds
Started Jun 11 12:24:11 PM PDT 24
Finished Jun 11 12:24:14 PM PDT 24
Peak memory 200372 kb
Host smart-acc096f0-3893-442c-a0fc-597a14c854d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785927362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1785927362
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1274797114
Short name T446
Test name
Test status
Simulation time 2629226135 ps
CPU time 9.5 seconds
Started Jun 11 12:24:19 PM PDT 24
Finished Jun 11 12:24:29 PM PDT 24
Peak memory 210132 kb
Host smart-a7549d31-a4ff-480d-acb7-892c91a878c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274797114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1274797114
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1548372202
Short name T381
Test name
Test status
Simulation time 123245962 ps
CPU time 1.43 seconds
Started Jun 11 12:24:19 PM PDT 24
Finished Jun 11 12:24:21 PM PDT 24
Peak memory 200128 kb
Host smart-ec54a1f6-be39-4788-b9be-62ad85af802b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548372202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1548372202
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1894918144
Short name T472
Test name
Test status
Simulation time 108067744 ps
CPU time 0.99 seconds
Started Jun 11 12:24:08 PM PDT 24
Finished Jun 11 12:24:11 PM PDT 24
Peak memory 200344 kb
Host smart-00e06fc3-097e-423c-a900-70f3d14d9ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894918144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1894918144
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.2943498742
Short name T169
Test name
Test status
Simulation time 68578057 ps
CPU time 0.7 seconds
Started Jun 11 12:23:26 PM PDT 24
Finished Jun 11 12:23:32 PM PDT 24
Peak memory 200012 kb
Host smart-93e29a42-c791-45b2-ac15-2989d293c4e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943498742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.2943498742
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1983784309
Short name T350
Test name
Test status
Simulation time 1901123455 ps
CPU time 6.85 seconds
Started Jun 11 12:23:28 PM PDT 24
Finished Jun 11 12:23:39 PM PDT 24
Peak memory 216848 kb
Host smart-d82c3046-b2fb-41b2-b47c-567f84ad65a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983784309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1983784309
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2465103369
Short name T443
Test name
Test status
Simulation time 246945685 ps
CPU time 1.02 seconds
Started Jun 11 12:23:29 PM PDT 24
Finished Jun 11 12:23:34 PM PDT 24
Peak memory 217508 kb
Host smart-86d17dc6-b7c5-4ec0-8e0e-1f2c1b5c81d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465103369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2465103369
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3818627493
Short name T397
Test name
Test status
Simulation time 215397746 ps
CPU time 0.91 seconds
Started Jun 11 12:23:28 PM PDT 24
Finished Jun 11 12:23:34 PM PDT 24
Peak memory 199984 kb
Host smart-febeda61-084c-4d14-aa42-0fadbc1f1919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818627493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3818627493
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1368746125
Short name T445
Test name
Test status
Simulation time 1743463920 ps
CPU time 5.98 seconds
Started Jun 11 12:23:27 PM PDT 24
Finished Jun 11 12:23:38 PM PDT 24
Peak memory 200316 kb
Host smart-d7d7a34c-5558-4ddc-9e43-84f3c022c80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368746125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1368746125
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3155460665
Short name T82
Test name
Test status
Simulation time 16545200912 ps
CPU time 25.59 seconds
Started Jun 11 12:23:23 PM PDT 24
Finished Jun 11 12:23:52 PM PDT 24
Peak memory 217912 kb
Host smart-f25dd6f7-89b9-4957-88e1-c871bd72d7b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155460665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3155460665
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1958091615
Short name T147
Test name
Test status
Simulation time 178487434 ps
CPU time 1.19 seconds
Started Jun 11 12:23:26 PM PDT 24
Finished Jun 11 12:23:32 PM PDT 24
Peak memory 200140 kb
Host smart-f129118e-5dc6-4d16-bcf6-e990163ccfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958091615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1958091615
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.4241584828
Short name T331
Test name
Test status
Simulation time 111070130 ps
CPU time 1.13 seconds
Started Jun 11 12:23:28 PM PDT 24
Finished Jun 11 12:23:33 PM PDT 24
Peak memory 200416 kb
Host smart-92b16e77-d373-42a7-b71e-c9241a540e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241584828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.4241584828
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.2029999678
Short name T258
Test name
Test status
Simulation time 4046148109 ps
CPU time 15.6 seconds
Started Jun 11 12:23:25 PM PDT 24
Finished Jun 11 12:23:45 PM PDT 24
Peak memory 208684 kb
Host smart-f54780d7-cde7-4df3-8e88-3d866557bf72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029999678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2029999678
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1389607073
Short name T68
Test name
Test status
Simulation time 118700257 ps
CPU time 1.35 seconds
Started Jun 11 12:23:23 PM PDT 24
Finished Jun 11 12:23:28 PM PDT 24
Peak memory 200208 kb
Host smart-4fd7584a-9a0b-44eb-ad75-1f622457d531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389607073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1389607073
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.1431603157
Short name T50
Test name
Test status
Simulation time 108361351 ps
CPU time 0.93 seconds
Started Jun 11 12:23:26 PM PDT 24
Finished Jun 11 12:23:32 PM PDT 24
Peak memory 200184 kb
Host smart-be565534-87cc-4f9d-a2ac-16c7f0c88d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431603157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1431603157
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.2234856517
Short name T2
Test name
Test status
Simulation time 78903626 ps
CPU time 0.81 seconds
Started Jun 11 12:24:19 PM PDT 24
Finished Jun 11 12:24:21 PM PDT 24
Peak memory 200408 kb
Host smart-32fb207a-cc4e-4ee2-b880-076a49520a09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234856517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.2234856517
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.316949777
Short name T411
Test name
Test status
Simulation time 1878964568 ps
CPU time 7.15 seconds
Started Jun 11 12:24:16 PM PDT 24
Finished Jun 11 12:24:24 PM PDT 24
Peak memory 217124 kb
Host smart-b741abc9-7046-4445-90c5-8665a4c5d99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316949777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.316949777
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3219744758
Short name T430
Test name
Test status
Simulation time 244705434 ps
CPU time 1.03 seconds
Started Jun 11 12:24:16 PM PDT 24
Finished Jun 11 12:24:18 PM PDT 24
Peak memory 217544 kb
Host smart-1ca98cd5-6d22-41e2-9f0e-cb2c37fa0d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219744758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3219744758
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2989467329
Short name T300
Test name
Test status
Simulation time 165445562 ps
CPU time 0.84 seconds
Started Jun 11 12:24:14 PM PDT 24
Finished Jun 11 12:24:16 PM PDT 24
Peak memory 200048 kb
Host smart-e2c02270-609d-4b14-8e85-a81fd2d2567b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989467329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2989467329
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.858106955
Short name T318
Test name
Test status
Simulation time 988405780 ps
CPU time 4.97 seconds
Started Jun 11 12:24:15 PM PDT 24
Finished Jun 11 12:24:22 PM PDT 24
Peak memory 200572 kb
Host smart-cf60a523-0577-4273-8c32-96b8ec61e626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858106955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.858106955
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1127510311
Short name T12
Test name
Test status
Simulation time 107063331 ps
CPU time 0.99 seconds
Started Jun 11 12:24:18 PM PDT 24
Finished Jun 11 12:24:21 PM PDT 24
Peak memory 200592 kb
Host smart-57129348-da27-427f-9bcf-67b9202a5357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127510311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1127510311
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.932501064
Short name T538
Test name
Test status
Simulation time 197247823 ps
CPU time 1.41 seconds
Started Jun 11 12:24:17 PM PDT 24
Finished Jun 11 12:24:20 PM PDT 24
Peak memory 200424 kb
Host smart-deeb51ec-c261-42cf-b4d8-b289ddcf0120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932501064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.932501064
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.3677749394
Short name T235
Test name
Test status
Simulation time 11448752034 ps
CPU time 42.24 seconds
Started Jun 11 12:24:17 PM PDT 24
Finished Jun 11 12:25:01 PM PDT 24
Peak memory 209412 kb
Host smart-f1c3c410-e6f0-470b-b0af-3b10eec60db4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677749394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3677749394
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.16670847
Short name T426
Test name
Test status
Simulation time 393615806 ps
CPU time 2.39 seconds
Started Jun 11 12:24:17 PM PDT 24
Finished Jun 11 12:24:21 PM PDT 24
Peak memory 200128 kb
Host smart-8adade3d-ba4c-421d-9374-374ad2897c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16670847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.16670847
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2000373935
Short name T214
Test name
Test status
Simulation time 75036632 ps
CPU time 0.75 seconds
Started Jun 11 12:24:14 PM PDT 24
Finished Jun 11 12:24:15 PM PDT 24
Peak memory 200036 kb
Host smart-808c9a0c-eb3f-4309-ae1e-635d48e95bee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000373935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2000373935
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.4288802484
Short name T39
Test name
Test status
Simulation time 1232456509 ps
CPU time 5.21 seconds
Started Jun 11 12:24:21 PM PDT 24
Finished Jun 11 12:24:27 PM PDT 24
Peak memory 217888 kb
Host smart-9b8d60e9-1e62-4da9-a1d9-0ad53735d1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288802484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.4288802484
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.812976
Short name T160
Test name
Test status
Simulation time 244775147 ps
CPU time 1.13 seconds
Started Jun 11 12:24:14 PM PDT 24
Finished Jun 11 12:24:17 PM PDT 24
Peak memory 217620 kb
Host smart-bf6ba073-1623-43e4-aaa6-083498ef4b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.812976
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.3215026346
Short name T21
Test name
Test status
Simulation time 178241181 ps
CPU time 0.83 seconds
Started Jun 11 12:24:16 PM PDT 24
Finished Jun 11 12:24:19 PM PDT 24
Peak memory 200092 kb
Host smart-58c24ced-7c96-498b-888d-41c905f4f2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215026346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3215026346
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3051327454
Short name T308
Test name
Test status
Simulation time 902002538 ps
CPU time 4.23 seconds
Started Jun 11 12:24:13 PM PDT 24
Finished Jun 11 12:24:19 PM PDT 24
Peak memory 200472 kb
Host smart-55e1687c-1cc6-497b-81a5-a91f2ddcb87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051327454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3051327454
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2854410173
Short name T361
Test name
Test status
Simulation time 100986015 ps
CPU time 1.04 seconds
Started Jun 11 12:24:16 PM PDT 24
Finished Jun 11 12:24:18 PM PDT 24
Peak memory 200568 kb
Host smart-708c5178-5120-4373-994e-f20231aa6055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854410173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2854410173
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.281226206
Short name T414
Test name
Test status
Simulation time 237953237 ps
CPU time 1.51 seconds
Started Jun 11 12:24:22 PM PDT 24
Finished Jun 11 12:24:25 PM PDT 24
Peak memory 200420 kb
Host smart-c5f8e74f-34af-4e7e-be75-52cc3bc0ac67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281226206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.281226206
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3876577672
Short name T253
Test name
Test status
Simulation time 239111441 ps
CPU time 1.31 seconds
Started Jun 11 12:24:16 PM PDT 24
Finished Jun 11 12:24:19 PM PDT 24
Peak memory 199956 kb
Host smart-46fd0116-4fde-4f55-a139-7fb94182c3f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876577672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3876577672
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.554974444
Short name T171
Test name
Test status
Simulation time 259084236 ps
CPU time 1.83 seconds
Started Jun 11 12:24:15 PM PDT 24
Finished Jun 11 12:24:18 PM PDT 24
Peak memory 200216 kb
Host smart-bf5a9d32-2e15-427b-aa1e-c9d6a77cf82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554974444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.554974444
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.268176010
Short name T227
Test name
Test status
Simulation time 150408600 ps
CPU time 1.1 seconds
Started Jun 11 12:24:23 PM PDT 24
Finished Jun 11 12:24:25 PM PDT 24
Peak memory 200236 kb
Host smart-2cc9d0c0-4f66-4a8e-a93e-0ced88e136a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268176010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.268176010
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.625957534
Short name T189
Test name
Test status
Simulation time 84450734 ps
CPU time 0.73 seconds
Started Jun 11 12:24:15 PM PDT 24
Finished Jun 11 12:24:17 PM PDT 24
Peak memory 200056 kb
Host smart-9dab737c-0773-4a03-8ef4-479b07336d08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625957534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.625957534
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1041592841
Short name T219
Test name
Test status
Simulation time 244406029 ps
CPU time 1.07 seconds
Started Jun 11 12:24:19 PM PDT 24
Finished Jun 11 12:24:21 PM PDT 24
Peak memory 217520 kb
Host smart-6a27ff7a-3b4e-40a5-8d11-12cafef5886c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041592841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1041592841
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3077871098
Short name T23
Test name
Test status
Simulation time 150897769 ps
CPU time 0.79 seconds
Started Jun 11 12:24:13 PM PDT 24
Finished Jun 11 12:24:15 PM PDT 24
Peak memory 200124 kb
Host smart-a8eea7d2-b3f3-4d1e-9379-e070b55066fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077871098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3077871098
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.593372183
Short name T494
Test name
Test status
Simulation time 859910051 ps
CPU time 4.13 seconds
Started Jun 11 12:24:19 PM PDT 24
Finished Jun 11 12:24:24 PM PDT 24
Peak memory 200452 kb
Host smart-734d9886-e95a-4e03-993f-41ad55e7328e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593372183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.593372183
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3916671012
Short name T531
Test name
Test status
Simulation time 110533375 ps
CPU time 0.99 seconds
Started Jun 11 12:24:16 PM PDT 24
Finished Jun 11 12:24:19 PM PDT 24
Peak memory 200220 kb
Host smart-bb7cd024-f445-4f9e-ac20-c5479466eaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916671012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3916671012
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2449519060
Short name T195
Test name
Test status
Simulation time 246784699 ps
CPU time 1.49 seconds
Started Jun 11 12:24:21 PM PDT 24
Finished Jun 11 12:24:24 PM PDT 24
Peak memory 200372 kb
Host smart-e965d49a-0d2b-4971-8cce-e344521af556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449519060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2449519060
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.245538284
Short name T254
Test name
Test status
Simulation time 4594947153 ps
CPU time 17.05 seconds
Started Jun 11 12:24:15 PM PDT 24
Finished Jun 11 12:24:33 PM PDT 24
Peak memory 200688 kb
Host smart-6fc45beb-34a1-46d8-9b49-b7b855d15ff9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245538284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.245538284
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.1354171871
Short name T525
Test name
Test status
Simulation time 375162584 ps
CPU time 2.3 seconds
Started Jun 11 12:24:17 PM PDT 24
Finished Jun 11 12:24:21 PM PDT 24
Peak memory 200576 kb
Host smart-51d49b70-2301-4149-b328-42eae58d8ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354171871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1354171871
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2879880362
Short name T157
Test name
Test status
Simulation time 177539831 ps
CPU time 1.33 seconds
Started Jun 11 12:24:16 PM PDT 24
Finished Jun 11 12:24:19 PM PDT 24
Peak memory 200276 kb
Host smart-b42809db-a8b9-4d11-a527-f9effea1e09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879880362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2879880362
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.4151564945
Short name T437
Test name
Test status
Simulation time 64238713 ps
CPU time 0.75 seconds
Started Jun 11 12:24:14 PM PDT 24
Finished Jun 11 12:24:16 PM PDT 24
Peak memory 200120 kb
Host smart-482cfade-955c-4ee8-93ee-6c1418942e85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151564945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.4151564945
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.807470514
Short name T45
Test name
Test status
Simulation time 2175878847 ps
CPU time 7.69 seconds
Started Jun 11 12:24:18 PM PDT 24
Finished Jun 11 12:24:27 PM PDT 24
Peak memory 217628 kb
Host smart-6d52cf8d-bde1-4294-93ef-41a1bb9998f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807470514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.807470514
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.8080084
Short name T369
Test name
Test status
Simulation time 244238314 ps
CPU time 1.04 seconds
Started Jun 11 12:24:18 PM PDT 24
Finished Jun 11 12:24:20 PM PDT 24
Peak memory 217464 kb
Host smart-f43b97bd-bd19-421e-90f2-e906d5398ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8080084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.8080084
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2349421547
Short name T401
Test name
Test status
Simulation time 100284804 ps
CPU time 0.73 seconds
Started Jun 11 12:24:21 PM PDT 24
Finished Jun 11 12:24:23 PM PDT 24
Peak memory 200056 kb
Host smart-3dbfb987-2dc8-4a67-9c06-5c91e4455007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349421547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2349421547
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3625533238
Short name T329
Test name
Test status
Simulation time 1458497274 ps
CPU time 5.74 seconds
Started Jun 11 12:24:22 PM PDT 24
Finished Jun 11 12:24:29 PM PDT 24
Peak memory 200416 kb
Host smart-461e50d9-dd00-4e6c-b23f-cfba2d404dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625533238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3625533238
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.523975886
Short name T348
Test name
Test status
Simulation time 163333596 ps
CPU time 1.2 seconds
Started Jun 11 12:24:17 PM PDT 24
Finished Jun 11 12:24:20 PM PDT 24
Peak memory 200576 kb
Host smart-76f34709-2119-4fd6-9b65-b7e09b0b1062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523975886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.523975886
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2513681605
Short name T309
Test name
Test status
Simulation time 267125022 ps
CPU time 1.55 seconds
Started Jun 11 12:24:16 PM PDT 24
Finished Jun 11 12:24:19 PM PDT 24
Peak memory 200440 kb
Host smart-23b7da80-af80-4ad6-b7bb-def1ad3fbb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513681605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2513681605
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.3813583581
Short name T115
Test name
Test status
Simulation time 7289261744 ps
CPU time 32.88 seconds
Started Jun 11 12:24:16 PM PDT 24
Finished Jun 11 12:24:50 PM PDT 24
Peak memory 200660 kb
Host smart-b04fb27d-f21e-4141-80b8-83510ae8c806
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813583581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3813583581
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3635631375
Short name T249
Test name
Test status
Simulation time 258369219 ps
CPU time 1.71 seconds
Started Jun 11 12:24:14 PM PDT 24
Finished Jun 11 12:24:17 PM PDT 24
Peak memory 200336 kb
Host smart-0dda74ee-e129-413a-8fb3-6f7548194bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635631375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3635631375
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3201339406
Short name T28
Test name
Test status
Simulation time 70081289 ps
CPU time 0.77 seconds
Started Jun 11 12:24:16 PM PDT 24
Finished Jun 11 12:24:18 PM PDT 24
Peak memory 199892 kb
Host smart-8db77d84-d676-47eb-9856-809d95f33809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201339406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3201339406
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.4157611259
Short name T252
Test name
Test status
Simulation time 67360593 ps
CPU time 0.75 seconds
Started Jun 11 12:24:40 PM PDT 24
Finished Jun 11 12:24:43 PM PDT 24
Peak memory 200012 kb
Host smart-3bb12852-3557-46dc-83f6-7e1c0d43433e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157611259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.4157611259
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.2525026017
Short name T374
Test name
Test status
Simulation time 1897502493 ps
CPU time 7.14 seconds
Started Jun 11 12:24:39 PM PDT 24
Finished Jun 11 12:24:47 PM PDT 24
Peak memory 217864 kb
Host smart-4c08412d-b65b-4318-ab4e-a2a38791b06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525026017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2525026017
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.149154710
Short name T521
Test name
Test status
Simulation time 244702002 ps
CPU time 1.1 seconds
Started Jun 11 12:24:42 PM PDT 24
Finished Jun 11 12:24:45 PM PDT 24
Peak memory 217532 kb
Host smart-9e7310b5-e953-42f9-8d27-631b15ff507b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149154710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.149154710
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2078372747
Short name T281
Test name
Test status
Simulation time 80164157 ps
CPU time 0.7 seconds
Started Jun 11 12:24:13 PM PDT 24
Finished Jun 11 12:24:14 PM PDT 24
Peak memory 200096 kb
Host smart-ed3d4d8a-7058-4d93-8896-b1111eab004b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078372747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2078372747
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3413823509
Short name T233
Test name
Test status
Simulation time 1288157328 ps
CPU time 5.11 seconds
Started Jun 11 12:24:15 PM PDT 24
Finished Jun 11 12:24:21 PM PDT 24
Peak memory 200440 kb
Host smart-78ec7e1c-f3ea-45dc-a764-9bb80018b0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413823509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3413823509
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.464728566
Short name T450
Test name
Test status
Simulation time 173788374 ps
CPU time 1.2 seconds
Started Jun 11 12:24:16 PM PDT 24
Finished Jun 11 12:24:19 PM PDT 24
Peak memory 200272 kb
Host smart-25ba5020-6cdf-4a70-a139-69ac7329b168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464728566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.464728566
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.912875944
Short name T388
Test name
Test status
Simulation time 116569638 ps
CPU time 1.14 seconds
Started Jun 11 12:24:23 PM PDT 24
Finished Jun 11 12:24:25 PM PDT 24
Peak memory 200420 kb
Host smart-78868ef8-6061-454c-8e6c-01066779b1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912875944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.912875944
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1706637594
Short name T358
Test name
Test status
Simulation time 321278059 ps
CPU time 2 seconds
Started Jun 11 12:24:44 PM PDT 24
Finished Jun 11 12:24:49 PM PDT 24
Peak memory 200552 kb
Host smart-6b706156-993d-4071-a1a3-78730fc84cb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706637594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1706637594
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.208390717
Short name T442
Test name
Test status
Simulation time 312983260 ps
CPU time 1.83 seconds
Started Jun 11 12:24:19 PM PDT 24
Finished Jun 11 12:24:22 PM PDT 24
Peak memory 200132 kb
Host smart-86ed09a5-a159-4b4d-9443-ba5edb9797d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208390717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.208390717
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1240899407
Short name T473
Test name
Test status
Simulation time 127154003 ps
CPU time 0.99 seconds
Started Jun 11 12:24:16 PM PDT 24
Finished Jun 11 12:24:18 PM PDT 24
Peak memory 200240 kb
Host smart-f2b5e590-90ea-460a-98cb-ccc05cd11d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240899407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1240899407
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2524120863
Short name T415
Test name
Test status
Simulation time 82572264 ps
CPU time 0.78 seconds
Started Jun 11 12:24:40 PM PDT 24
Finished Jun 11 12:24:42 PM PDT 24
Peak memory 200100 kb
Host smart-39f95fa7-37b4-40db-8161-f0c182d8dc6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524120863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2524120863
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3162119382
Short name T34
Test name
Test status
Simulation time 1901297065 ps
CPU time 7.77 seconds
Started Jun 11 12:24:44 PM PDT 24
Finished Jun 11 12:24:54 PM PDT 24
Peak memory 217824 kb
Host smart-96319e77-a8f3-4e78-8cb5-570d64d0f178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162119382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3162119382
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.4192570590
Short name T390
Test name
Test status
Simulation time 244495886 ps
CPU time 1.07 seconds
Started Jun 11 12:24:43 PM PDT 24
Finished Jun 11 12:24:47 PM PDT 24
Peak memory 217592 kb
Host smart-b945a54b-aaa2-43e2-9cd7-7d967837df70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192570590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.4192570590
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3966911507
Short name T346
Test name
Test status
Simulation time 164236787 ps
CPU time 0.79 seconds
Started Jun 11 12:24:44 PM PDT 24
Finished Jun 11 12:24:47 PM PDT 24
Peak memory 200164 kb
Host smart-4c7a1531-f7a9-499b-b190-a2fc2ce65411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966911507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3966911507
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.445892457
Short name T105
Test name
Test status
Simulation time 875496048 ps
CPU time 4.59 seconds
Started Jun 11 12:24:44 PM PDT 24
Finished Jun 11 12:24:51 PM PDT 24
Peak memory 200484 kb
Host smart-8c35d2ec-dbab-4385-9f9d-4f7f0afd950b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445892457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.445892457
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1027793556
Short name T13
Test name
Test status
Simulation time 147189525 ps
CPU time 1.07 seconds
Started Jun 11 12:24:41 PM PDT 24
Finished Jun 11 12:24:43 PM PDT 24
Peak memory 200360 kb
Host smart-d7c022b3-3c0c-41a6-b5ec-442f0aa95ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027793556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1027793556
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1086141767
Short name T209
Test name
Test status
Simulation time 117317034 ps
CPU time 1.15 seconds
Started Jun 11 12:24:44 PM PDT 24
Finished Jun 11 12:24:47 PM PDT 24
Peak memory 200532 kb
Host smart-480701c9-4385-459c-9fa5-706f4b591e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086141767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1086141767
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3444065095
Short name T94
Test name
Test status
Simulation time 2062421502 ps
CPU time 8.97 seconds
Started Jun 11 12:24:42 PM PDT 24
Finished Jun 11 12:24:53 PM PDT 24
Peak memory 200324 kb
Host smart-6dd8a21d-b211-4db0-8317-8e628aa0567b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444065095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3444065095
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3449824944
Short name T194
Test name
Test status
Simulation time 134076469 ps
CPU time 1.56 seconds
Started Jun 11 12:24:44 PM PDT 24
Finished Jun 11 12:24:49 PM PDT 24
Peak memory 200348 kb
Host smart-b9c49315-1af4-4903-bf81-af166d400898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449824944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3449824944
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1206745230
Short name T513
Test name
Test status
Simulation time 99942638 ps
CPU time 0.97 seconds
Started Jun 11 12:24:45 PM PDT 24
Finished Jun 11 12:24:48 PM PDT 24
Peak memory 200344 kb
Host smart-b0360826-f268-41b6-8bf3-7f5d16359efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206745230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1206745230
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.4287180148
Short name T218
Test name
Test status
Simulation time 66074004 ps
CPU time 0.7 seconds
Started Jun 11 12:24:42 PM PDT 24
Finished Jun 11 12:24:44 PM PDT 24
Peak memory 200116 kb
Host smart-0dda4444-487e-4cc9-b12a-04b0f552702c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287180148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.4287180148
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3300751725
Short name T61
Test name
Test status
Simulation time 2334175831 ps
CPU time 7.9 seconds
Started Jun 11 12:24:43 PM PDT 24
Finished Jun 11 12:24:53 PM PDT 24
Peak memory 222080 kb
Host smart-dc201fa8-afc0-473e-bb3a-441df5f75547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300751725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3300751725
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2836485798
Short name T255
Test name
Test status
Simulation time 243873497 ps
CPU time 1.13 seconds
Started Jun 11 12:24:40 PM PDT 24
Finished Jun 11 12:24:43 PM PDT 24
Peak memory 217508 kb
Host smart-b3f23fba-31c8-484a-babe-7102deefb258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836485798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2836485798
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.2949104612
Short name T284
Test name
Test status
Simulation time 194497319 ps
CPU time 0.88 seconds
Started Jun 11 12:24:44 PM PDT 24
Finished Jun 11 12:24:47 PM PDT 24
Peak memory 200172 kb
Host smart-7730d8b5-eab3-4f75-8663-6ee8ddf77935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949104612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.2949104612
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.856890243
Short name T325
Test name
Test status
Simulation time 1434380300 ps
CPU time 5.3 seconds
Started Jun 11 12:24:43 PM PDT 24
Finished Jun 11 12:24:51 PM PDT 24
Peak memory 200424 kb
Host smart-d84e768e-266c-49b6-bfc6-0a296fc72b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856890243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.856890243
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1273391594
Short name T29
Test name
Test status
Simulation time 137741876 ps
CPU time 1.11 seconds
Started Jun 11 12:24:45 PM PDT 24
Finished Jun 11 12:24:49 PM PDT 24
Peak memory 200360 kb
Host smart-fa145c07-7dfb-40cc-98dd-95a82796b30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273391594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1273391594
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.1959694486
Short name T519
Test name
Test status
Simulation time 247786001 ps
CPU time 1.44 seconds
Started Jun 11 12:24:37 PM PDT 24
Finished Jun 11 12:24:39 PM PDT 24
Peak memory 200404 kb
Host smart-3b8c6005-763e-4702-b510-629a08a5fe3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959694486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1959694486
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1557286393
Short name T359
Test name
Test status
Simulation time 12422870931 ps
CPU time 40.65 seconds
Started Jun 11 12:24:44 PM PDT 24
Finished Jun 11 12:25:27 PM PDT 24
Peak memory 208856 kb
Host smart-0c542859-0418-4b61-9d8a-1670edbc7d09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557286393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1557286393
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1389424328
Short name T539
Test name
Test status
Simulation time 111868323 ps
CPU time 1.43 seconds
Started Jun 11 12:24:44 PM PDT 24
Finished Jun 11 12:24:48 PM PDT 24
Peak memory 200224 kb
Host smart-8ebc72c2-3362-4d1b-aa1a-3aaa640a33df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389424328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1389424328
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.281237933
Short name T202
Test name
Test status
Simulation time 257366761 ps
CPU time 1.51 seconds
Started Jun 11 12:24:38 PM PDT 24
Finished Jun 11 12:24:40 PM PDT 24
Peak memory 200316 kb
Host smart-0c56db9b-0a95-4b74-bb49-007b14d96008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281237933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.281237933
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.24874009
Short name T40
Test name
Test status
Simulation time 56898808 ps
CPU time 0.7 seconds
Started Jun 11 12:24:41 PM PDT 24
Finished Jun 11 12:24:44 PM PDT 24
Peak memory 200120 kb
Host smart-ead9f580-54f7-4c46-8ee5-ad975ebfe0ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24874009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.24874009
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3068534811
Short name T461
Test name
Test status
Simulation time 1894875846 ps
CPU time 7.28 seconds
Started Jun 11 12:24:40 PM PDT 24
Finished Jun 11 12:24:49 PM PDT 24
Peak memory 217980 kb
Host smart-8c6365db-6c4f-4144-b9e3-5b69ac084857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068534811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3068534811
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.796784817
Short name T330
Test name
Test status
Simulation time 244110995 ps
CPU time 1.01 seconds
Started Jun 11 12:24:39 PM PDT 24
Finished Jun 11 12:24:41 PM PDT 24
Peak memory 217512 kb
Host smart-6654800d-bed0-4eb2-becd-7f3979e3594e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796784817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.796784817
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2369038245
Short name T478
Test name
Test status
Simulation time 101663972 ps
CPU time 0.74 seconds
Started Jun 11 12:24:40 PM PDT 24
Finished Jun 11 12:24:42 PM PDT 24
Peak memory 200148 kb
Host smart-28aaa159-a796-452b-b15c-a8305d6ec903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369038245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2369038245
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1081506182
Short name T453
Test name
Test status
Simulation time 1724719677 ps
CPU time 6.88 seconds
Started Jun 11 12:24:40 PM PDT 24
Finished Jun 11 12:24:48 PM PDT 24
Peak memory 200528 kb
Host smart-d1498561-7823-42f2-931d-b41cb25a5948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081506182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1081506182
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3421539242
Short name T332
Test name
Test status
Simulation time 178613634 ps
CPU time 1.15 seconds
Started Jun 11 12:24:41 PM PDT 24
Finished Jun 11 12:24:44 PM PDT 24
Peak memory 200196 kb
Host smart-c68bc8eb-8c65-4094-b646-85bdaf1449b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421539242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3421539242
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.3029397804
Short name T339
Test name
Test status
Simulation time 117196243 ps
CPU time 1.17 seconds
Started Jun 11 12:24:42 PM PDT 24
Finished Jun 11 12:24:45 PM PDT 24
Peak memory 200776 kb
Host smart-2c06cd78-878d-49a5-ae64-4d8bde93a765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029397804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.3029397804
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1042174996
Short name T468
Test name
Test status
Simulation time 182232327 ps
CPU time 1.13 seconds
Started Jun 11 12:24:41 PM PDT 24
Finished Jun 11 12:24:43 PM PDT 24
Peak memory 200256 kb
Host smart-425004c0-da49-4574-a057-7106cb8fd3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042174996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1042174996
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3222001977
Short name T83
Test name
Test status
Simulation time 72446101 ps
CPU time 0.78 seconds
Started Jun 11 12:24:39 PM PDT 24
Finished Jun 11 12:24:40 PM PDT 24
Peak memory 200092 kb
Host smart-66192851-ffaa-469d-8602-b2227e9c7623
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222001977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3222001977
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3200100735
Short name T37
Test name
Test status
Simulation time 2173005416 ps
CPU time 7.22 seconds
Started Jun 11 12:24:40 PM PDT 24
Finished Jun 11 12:24:48 PM PDT 24
Peak memory 217276 kb
Host smart-6a781112-3949-4a67-a2df-652e47947a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200100735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3200100735
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.3072029484
Short name T321
Test name
Test status
Simulation time 244871174 ps
CPU time 1.17 seconds
Started Jun 11 12:24:42 PM PDT 24
Finished Jun 11 12:24:45 PM PDT 24
Peak memory 217384 kb
Host smart-cc7a0ea5-a9a3-4e4f-a3ff-9344a6f25d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072029484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.3072029484
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3809382488
Short name T19
Test name
Test status
Simulation time 82861056 ps
CPU time 0.77 seconds
Started Jun 11 12:24:40 PM PDT 24
Finished Jun 11 12:24:43 PM PDT 24
Peak memory 199996 kb
Host smart-0ef6a9af-b831-465e-ae9c-772808fcb6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809382488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3809382488
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3093792813
Short name T283
Test name
Test status
Simulation time 1421536291 ps
CPU time 5.83 seconds
Started Jun 11 12:24:43 PM PDT 24
Finished Jun 11 12:24:51 PM PDT 24
Peak memory 200524 kb
Host smart-b6adcc93-e5ac-421b-99e2-848800452cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093792813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3093792813
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.653590777
Short name T489
Test name
Test status
Simulation time 107281483 ps
CPU time 0.98 seconds
Started Jun 11 12:24:44 PM PDT 24
Finished Jun 11 12:24:47 PM PDT 24
Peak memory 200348 kb
Host smart-a7959b76-227e-4989-a379-a8fac5429576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653590777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.653590777
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.725927186
Short name T159
Test name
Test status
Simulation time 120568352 ps
CPU time 1.13 seconds
Started Jun 11 12:24:39 PM PDT 24
Finished Jun 11 12:24:41 PM PDT 24
Peak memory 200456 kb
Host smart-ec887014-26d9-464d-997f-d562d7f1365c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725927186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.725927186
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.929858343
Short name T108
Test name
Test status
Simulation time 2813344195 ps
CPU time 12.02 seconds
Started Jun 11 12:24:39 PM PDT 24
Finished Jun 11 12:24:52 PM PDT 24
Peak memory 200496 kb
Host smart-06c95355-e7cd-4400-aa96-779f36b5e4c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929858343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.929858343
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3470040617
Short name T232
Test name
Test status
Simulation time 143243695 ps
CPU time 1.63 seconds
Started Jun 11 12:24:42 PM PDT 24
Finished Jun 11 12:24:46 PM PDT 24
Peak memory 208436 kb
Host smart-1779f252-9b56-433d-83bf-532b469eb498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470040617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3470040617
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2988399276
Short name T292
Test name
Test status
Simulation time 96866026 ps
CPU time 0.93 seconds
Started Jun 11 12:24:38 PM PDT 24
Finished Jun 11 12:24:40 PM PDT 24
Peak memory 200300 kb
Host smart-831227e5-9284-45d0-8f71-92b630da0811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988399276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2988399276
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.844923710
Short name T488
Test name
Test status
Simulation time 72405275 ps
CPU time 0.76 seconds
Started Jun 11 12:24:38 PM PDT 24
Finished Jun 11 12:24:39 PM PDT 24
Peak memory 200080 kb
Host smart-ccaf9d6b-6f37-4f2d-bf64-0f0326d36e74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844923710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.844923710
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.990889696
Short name T273
Test name
Test status
Simulation time 1899178176 ps
CPU time 7.04 seconds
Started Jun 11 12:24:40 PM PDT 24
Finished Jun 11 12:24:48 PM PDT 24
Peak memory 217800 kb
Host smart-ba66affd-20ec-4d9e-bed4-c0289928923a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990889696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.990889696
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.4090312299
Short name T210
Test name
Test status
Simulation time 246243930 ps
CPU time 1.03 seconds
Started Jun 11 12:24:44 PM PDT 24
Finished Jun 11 12:24:47 PM PDT 24
Peak memory 217560 kb
Host smart-64ed93ee-ab69-4032-af3b-b6f22f79a640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090312299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.4090312299
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1402694518
Short name T18
Test name
Test status
Simulation time 91871962 ps
CPU time 0.74 seconds
Started Jun 11 12:24:44 PM PDT 24
Finished Jun 11 12:24:47 PM PDT 24
Peak memory 200168 kb
Host smart-a01fd826-d939-47e0-8235-317ff6f3964a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402694518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1402694518
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.468498302
Short name T469
Test name
Test status
Simulation time 1125128322 ps
CPU time 5.14 seconds
Started Jun 11 12:24:43 PM PDT 24
Finished Jun 11 12:24:50 PM PDT 24
Peak memory 200484 kb
Host smart-288f7ab1-a4f2-403b-aae2-568f66f693b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468498302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.468498302
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2164521445
Short name T317
Test name
Test status
Simulation time 175705585 ps
CPU time 1.11 seconds
Started Jun 11 12:24:41 PM PDT 24
Finished Jun 11 12:24:44 PM PDT 24
Peak memory 200196 kb
Host smart-3a81825f-3304-4eaf-8a89-01a437b2db9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164521445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2164521445
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.4185319623
Short name T67
Test name
Test status
Simulation time 115817605 ps
CPU time 1.18 seconds
Started Jun 11 12:24:43 PM PDT 24
Finished Jun 11 12:24:46 PM PDT 24
Peak memory 200424 kb
Host smart-7e4be710-b10d-4f89-8502-d9852f29c8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185319623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.4185319623
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.412983075
Short name T333
Test name
Test status
Simulation time 7209096045 ps
CPU time 26.79 seconds
Started Jun 11 12:24:45 PM PDT 24
Finished Jun 11 12:25:14 PM PDT 24
Peak memory 209684 kb
Host smart-57cfac3f-2917-4e08-98f4-ddc46afcf8f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412983075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.412983075
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2543221774
Short name T266
Test name
Test status
Simulation time 121371394 ps
CPU time 1.36 seconds
Started Jun 11 12:24:43 PM PDT 24
Finished Jun 11 12:24:47 PM PDT 24
Peak memory 200332 kb
Host smart-ac5ddf90-4b0e-4859-9aef-07e443516d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543221774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2543221774
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3627630620
Short name T237
Test name
Test status
Simulation time 133791096 ps
CPU time 0.94 seconds
Started Jun 11 12:24:41 PM PDT 24
Finished Jun 11 12:24:43 PM PDT 24
Peak memory 200196 kb
Host smart-a3fd1bdf-9fc1-467e-ab14-115845b5aef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627630620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3627630620
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.1191046940
Short name T532
Test name
Test status
Simulation time 70364744 ps
CPU time 0.77 seconds
Started Jun 11 12:23:36 PM PDT 24
Finished Jun 11 12:23:41 PM PDT 24
Peak memory 200148 kb
Host smart-31e11f15-aedc-46da-9ee1-e887081cbb7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191046940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1191046940
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.232648791
Short name T324
Test name
Test status
Simulation time 1889382906 ps
CPU time 6.89 seconds
Started Jun 11 12:23:33 PM PDT 24
Finished Jun 11 12:23:44 PM PDT 24
Peak memory 221840 kb
Host smart-5feb94c6-ddc5-4256-aa00-43f2ebba3a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232648791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.232648791
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3447195316
Short name T86
Test name
Test status
Simulation time 245161594 ps
CPU time 1.05 seconds
Started Jun 11 12:23:29 PM PDT 24
Finished Jun 11 12:23:35 PM PDT 24
Peak memory 217592 kb
Host smart-cb4cff88-ed78-4e65-a232-14cb538e4863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447195316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3447195316
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.2967411997
Short name T16
Test name
Test status
Simulation time 183898015 ps
CPU time 0.84 seconds
Started Jun 11 12:23:22 PM PDT 24
Finished Jun 11 12:23:25 PM PDT 24
Peak memory 199956 kb
Host smart-d0f962b1-4a2f-4a88-9f0c-9b8d166de9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967411997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2967411997
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.434352322
Short name T109
Test name
Test status
Simulation time 2169557588 ps
CPU time 7.25 seconds
Started Jun 11 12:23:26 PM PDT 24
Finished Jun 11 12:23:37 PM PDT 24
Peak memory 200480 kb
Host smart-0e38d24f-8448-425c-8d35-766e6ae4f43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434352322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.434352322
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3423231655
Short name T78
Test name
Test status
Simulation time 8300769122 ps
CPU time 14.32 seconds
Started Jun 11 12:23:35 PM PDT 24
Finished Jun 11 12:23:54 PM PDT 24
Peak memory 217392 kb
Host smart-42c193cb-d305-4e6c-9196-6a92d816da0e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423231655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3423231655
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2556214889
Short name T334
Test name
Test status
Simulation time 183648906 ps
CPU time 1.15 seconds
Started Jun 11 12:23:27 PM PDT 24
Finished Jun 11 12:23:33 PM PDT 24
Peak memory 199936 kb
Host smart-5ba2fbb6-feaa-461c-bbc7-62e7355be5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556214889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2556214889
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2090966849
Short name T223
Test name
Test status
Simulation time 124497953 ps
CPU time 1.09 seconds
Started Jun 11 12:23:30 PM PDT 24
Finished Jun 11 12:23:36 PM PDT 24
Peak memory 200412 kb
Host smart-09724d8c-c233-450e-a5de-9a5f22dad9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090966849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2090966849
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3907492508
Short name T349
Test name
Test status
Simulation time 1094871486 ps
CPU time 5.05 seconds
Started Jun 11 12:23:35 PM PDT 24
Finished Jun 11 12:23:45 PM PDT 24
Peak memory 200536 kb
Host smart-ed1c3199-6d77-468e-bdbb-3cdac4f58b8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907492508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3907492508
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.97853467
Short name T166
Test name
Test status
Simulation time 319955544 ps
CPU time 2.08 seconds
Started Jun 11 12:23:29 PM PDT 24
Finished Jun 11 12:23:36 PM PDT 24
Peak memory 200344 kb
Host smart-c8312ca3-1133-4167-b124-e0a3e042206c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97853467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.97853467
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.280310755
Short name T287
Test name
Test status
Simulation time 112151467 ps
CPU time 0.89 seconds
Started Jun 11 12:23:27 PM PDT 24
Finished Jun 11 12:23:32 PM PDT 24
Peak memory 200224 kb
Host smart-91ffccec-b5f0-4314-848d-97df0ec52647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280310755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.280310755
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3540542930
Short name T436
Test name
Test status
Simulation time 64205991 ps
CPU time 0.74 seconds
Started Jun 11 12:24:42 PM PDT 24
Finished Jun 11 12:24:45 PM PDT 24
Peak memory 200056 kb
Host smart-11098036-48c7-4751-842d-07bc7fffc312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540542930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3540542930
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.3387306297
Short name T428
Test name
Test status
Simulation time 1877957314 ps
CPU time 7.16 seconds
Started Jun 11 12:24:42 PM PDT 24
Finished Jun 11 12:24:52 PM PDT 24
Peak memory 221768 kb
Host smart-2cd376ac-6b0f-48e4-a94e-e908d1c4c750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387306297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3387306297
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1860626597
Short name T107
Test name
Test status
Simulation time 244653419 ps
CPU time 1.11 seconds
Started Jun 11 12:24:44 PM PDT 24
Finished Jun 11 12:24:47 PM PDT 24
Peak memory 217564 kb
Host smart-f35980f8-1a8b-4aff-944e-f32299c948ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860626597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1860626597
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3008706165
Short name T192
Test name
Test status
Simulation time 121030232 ps
CPU time 0.78 seconds
Started Jun 11 12:24:45 PM PDT 24
Finished Jun 11 12:24:48 PM PDT 24
Peak memory 200164 kb
Host smart-7b22a699-8ec3-4f5c-a44b-36164b4a17dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008706165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3008706165
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.512308484
Short name T530
Test name
Test status
Simulation time 1591132742 ps
CPU time 5.98 seconds
Started Jun 11 12:24:43 PM PDT 24
Finished Jun 11 12:24:51 PM PDT 24
Peak memory 200376 kb
Host smart-d7d2253d-a3ae-4e4a-b735-6e434d7e9fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512308484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.512308484
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2153721797
Short name T3
Test name
Test status
Simulation time 161122851 ps
CPU time 1.14 seconds
Started Jun 11 12:24:40 PM PDT 24
Finished Jun 11 12:24:43 PM PDT 24
Peak memory 200332 kb
Host smart-35831fdf-a183-4829-bfc8-1439ed6bb38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153721797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2153721797
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2130897127
Short name T366
Test name
Test status
Simulation time 256446760 ps
CPU time 1.44 seconds
Started Jun 11 12:24:42 PM PDT 24
Finished Jun 11 12:24:46 PM PDT 24
Peak memory 200432 kb
Host smart-e70b153e-9fab-45e0-bf46-2a89d14e2990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130897127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2130897127
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.604604183
Short name T338
Test name
Test status
Simulation time 4044937628 ps
CPU time 18.5 seconds
Started Jun 11 12:24:44 PM PDT 24
Finished Jun 11 12:25:05 PM PDT 24
Peak memory 200660 kb
Host smart-5e6141dd-b8d5-446f-8054-a5711bb93b37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604604183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.604604183
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.424729986
Short name T296
Test name
Test status
Simulation time 461283975 ps
CPU time 2.49 seconds
Started Jun 11 12:24:45 PM PDT 24
Finished Jun 11 12:24:50 PM PDT 24
Peak memory 200348 kb
Host smart-17a50a3d-ccd6-4f47-9e28-eb50c243a46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424729986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.424729986
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2961915064
Short name T483
Test name
Test status
Simulation time 92415220 ps
CPU time 0.84 seconds
Started Jun 11 12:24:43 PM PDT 24
Finished Jun 11 12:24:46 PM PDT 24
Peak memory 200308 kb
Host smart-3824387e-b978-4f41-81a8-4c0fcf4c2ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961915064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2961915064
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.4275922830
Short name T516
Test name
Test status
Simulation time 79077137 ps
CPU time 0.75 seconds
Started Jun 11 12:24:40 PM PDT 24
Finished Jun 11 12:24:43 PM PDT 24
Peak memory 200056 kb
Host smart-dba576fe-5d2a-442b-8d28-be6a3e4d504b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275922830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.4275922830
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1205617962
Short name T444
Test name
Test status
Simulation time 1893215744 ps
CPU time 6.67 seconds
Started Jun 11 12:24:42 PM PDT 24
Finished Jun 11 12:24:51 PM PDT 24
Peak memory 216788 kb
Host smart-0de07835-9b5a-41b4-abf0-d2804d3dd490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205617962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1205617962
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2472769967
Short name T435
Test name
Test status
Simulation time 243957742 ps
CPU time 1.18 seconds
Started Jun 11 12:24:43 PM PDT 24
Finished Jun 11 12:24:46 PM PDT 24
Peak memory 217552 kb
Host smart-9d3e1afd-1bb4-4f53-b746-d54d76f1cc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472769967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2472769967
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.803960222
Short name T15
Test name
Test status
Simulation time 190081478 ps
CPU time 0.89 seconds
Started Jun 11 12:24:45 PM PDT 24
Finished Jun 11 12:24:48 PM PDT 24
Peak memory 200160 kb
Host smart-831022f7-2a67-437d-91d3-8a919abd9082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803960222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.803960222
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.1220822804
Short name T305
Test name
Test status
Simulation time 1569700226 ps
CPU time 6.2 seconds
Started Jun 11 12:24:43 PM PDT 24
Finished Jun 11 12:24:51 PM PDT 24
Peak memory 200484 kb
Host smart-e78bddc8-95b7-413d-bfb9-6f92a9f08057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220822804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.1220822804
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3323521495
Short name T402
Test name
Test status
Simulation time 108859547 ps
CPU time 0.95 seconds
Started Jun 11 12:24:46 PM PDT 24
Finished Jun 11 12:24:50 PM PDT 24
Peak memory 200360 kb
Host smart-5326d61d-c1fa-437d-b88c-63e1c0c60432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323521495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3323521495
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.4092492766
Short name T514
Test name
Test status
Simulation time 118356301 ps
CPU time 1.2 seconds
Started Jun 11 12:24:44 PM PDT 24
Finished Jun 11 12:24:48 PM PDT 24
Peak memory 200496 kb
Host smart-789a9f48-a09d-4e5e-b8e4-6b18bd567281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092492766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.4092492766
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.4136033033
Short name T425
Test name
Test status
Simulation time 2141056139 ps
CPU time 10.67 seconds
Started Jun 11 12:24:43 PM PDT 24
Finished Jun 11 12:24:56 PM PDT 24
Peak memory 200760 kb
Host smart-0fc26897-270e-486d-96af-1de96e3b3aa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136033033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.4136033033
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.478525203
Short name T236
Test name
Test status
Simulation time 133415047 ps
CPU time 1.53 seconds
Started Jun 11 12:24:44 PM PDT 24
Finished Jun 11 12:24:48 PM PDT 24
Peak memory 200336 kb
Host smart-a114c93d-a218-4729-bc95-a47caeb08a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478525203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.478525203
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1002845651
Short name T387
Test name
Test status
Simulation time 75190903 ps
CPU time 0.78 seconds
Started Jun 11 12:24:42 PM PDT 24
Finished Jun 11 12:24:45 PM PDT 24
Peak memory 200236 kb
Host smart-d4dcf4f8-72ac-43ad-b156-4ecb05f1e6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002845651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1002845651
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1695770338
Short name T69
Test name
Test status
Simulation time 65778869 ps
CPU time 0.73 seconds
Started Jun 11 12:25:03 PM PDT 24
Finished Jun 11 12:25:07 PM PDT 24
Peak memory 200116 kb
Host smart-de177b93-6b54-4d41-b2f4-00b3b29a6c07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695770338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1695770338
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1582349201
Short name T357
Test name
Test status
Simulation time 1221456790 ps
CPU time 5.6 seconds
Started Jun 11 12:24:41 PM PDT 24
Finished Jun 11 12:24:48 PM PDT 24
Peak memory 217384 kb
Host smart-e81c5726-a379-482b-b5a5-589a41e91e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582349201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1582349201
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2056960757
Short name T441
Test name
Test status
Simulation time 244905878 ps
CPU time 1.06 seconds
Started Jun 11 12:24:44 PM PDT 24
Finished Jun 11 12:24:48 PM PDT 24
Peak memory 217596 kb
Host smart-3e3dfe45-3bd8-4efe-9e34-292fe14c16b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056960757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2056960757
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3156298423
Short name T299
Test name
Test status
Simulation time 181206969 ps
CPU time 0.84 seconds
Started Jun 11 12:24:39 PM PDT 24
Finished Jun 11 12:24:40 PM PDT 24
Peak memory 200092 kb
Host smart-5a18f914-6b0f-490b-bca5-480a13ed37fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156298423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3156298423
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1729262978
Short name T392
Test name
Test status
Simulation time 2001965456 ps
CPU time 7.63 seconds
Started Jun 11 12:24:43 PM PDT 24
Finished Jun 11 12:24:53 PM PDT 24
Peak memory 200492 kb
Host smart-fc3e2c5c-2692-4ba4-b35c-fe20c882da4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729262978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1729262978
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2210156476
Short name T239
Test name
Test status
Simulation time 165859061 ps
CPU time 1.09 seconds
Started Jun 11 12:24:43 PM PDT 24
Finished Jun 11 12:24:46 PM PDT 24
Peak memory 200184 kb
Host smart-0b9bd5a0-6700-465f-80ae-b2910228da65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210156476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2210156476
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2848441236
Short name T1
Test name
Test status
Simulation time 122064375 ps
CPU time 1.31 seconds
Started Jun 11 12:24:43 PM PDT 24
Finished Jun 11 12:24:46 PM PDT 24
Peak memory 200812 kb
Host smart-5a542e04-ba8b-4098-b0e8-ba7da9bd2b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848441236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2848441236
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.3168002473
Short name T315
Test name
Test status
Simulation time 6210506883 ps
CPU time 26.71 seconds
Started Jun 11 12:24:44 PM PDT 24
Finished Jun 11 12:25:13 PM PDT 24
Peak memory 208848 kb
Host smart-d80f0c1b-7684-498e-bc6c-fc8e2361ab79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168002473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3168002473
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2787655498
Short name T510
Test name
Test status
Simulation time 256608516 ps
CPU time 1.72 seconds
Started Jun 11 12:24:40 PM PDT 24
Finished Jun 11 12:24:44 PM PDT 24
Peak memory 200244 kb
Host smart-50016185-9191-4b95-8aad-c9f29815e4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787655498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2787655498
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.4141267362
Short name T267
Test name
Test status
Simulation time 168022280 ps
CPU time 1.25 seconds
Started Jun 11 12:24:43 PM PDT 24
Finished Jun 11 12:24:46 PM PDT 24
Peak memory 200364 kb
Host smart-e06c6212-2e6d-4769-b7d9-b4a3d2d6cd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141267362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.4141267362
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2845595231
Short name T27
Test name
Test status
Simulation time 66282708 ps
CPU time 0.72 seconds
Started Jun 11 12:25:04 PM PDT 24
Finished Jun 11 12:25:08 PM PDT 24
Peak memory 200128 kb
Host smart-16c7e372-6237-4782-8774-6a44d666363b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845595231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2845595231
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3033075366
Short name T490
Test name
Test status
Simulation time 2172890922 ps
CPU time 7.87 seconds
Started Jun 11 12:25:03 PM PDT 24
Finished Jun 11 12:25:14 PM PDT 24
Peak memory 222020 kb
Host smart-e0c0e401-100d-43dd-ab5b-56187b19edc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033075366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3033075366
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2079089746
Short name T336
Test name
Test status
Simulation time 244615714 ps
CPU time 1 seconds
Started Jun 11 12:25:03 PM PDT 24
Finished Jun 11 12:25:08 PM PDT 24
Peak memory 217576 kb
Host smart-4e859302-289a-464b-9555-3c4918ff99ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079089746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2079089746
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.4033570247
Short name T407
Test name
Test status
Simulation time 182408595 ps
CPU time 0.87 seconds
Started Jun 11 12:24:56 PM PDT 24
Finished Jun 11 12:25:00 PM PDT 24
Peak memory 200164 kb
Host smart-3cfed1ef-b98e-4a1b-8cd1-bfdf8e25c83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033570247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.4033570247
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.678398852
Short name T221
Test name
Test status
Simulation time 1584879907 ps
CPU time 5.9 seconds
Started Jun 11 12:24:56 PM PDT 24
Finished Jun 11 12:25:05 PM PDT 24
Peak memory 200524 kb
Host smart-722d1928-c3a9-4583-8372-bddc23e3500e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678398852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.678398852
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3218297260
Short name T228
Test name
Test status
Simulation time 108288776 ps
CPU time 0.95 seconds
Started Jun 11 12:25:00 PM PDT 24
Finished Jun 11 12:25:04 PM PDT 24
Peak memory 200340 kb
Host smart-dbc34b19-14fb-4d70-9c06-11efcc41ea24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218297260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3218297260
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1975981048
Short name T257
Test name
Test status
Simulation time 113579280 ps
CPU time 1.11 seconds
Started Jun 11 12:25:01 PM PDT 24
Finished Jun 11 12:25:04 PM PDT 24
Peak memory 200452 kb
Host smart-71836849-6aad-4681-9b68-a804f2e29555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975981048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1975981048
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.2865648076
Short name T500
Test name
Test status
Simulation time 8200386082 ps
CPU time 27.6 seconds
Started Jun 11 12:25:01 PM PDT 24
Finished Jun 11 12:25:31 PM PDT 24
Peak memory 208780 kb
Host smart-1e57b6ec-e384-4c17-9256-228206e2bcc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865648076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2865648076
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.2097971867
Short name T277
Test name
Test status
Simulation time 356737122 ps
CPU time 2.12 seconds
Started Jun 11 12:25:00 PM PDT 24
Finished Jun 11 12:25:04 PM PDT 24
Peak memory 200328 kb
Host smart-589fad6e-c01b-4c82-8831-e1102acf8e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097971867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2097971867
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.516363332
Short name T341
Test name
Test status
Simulation time 202041627 ps
CPU time 1.25 seconds
Started Jun 11 12:25:03 PM PDT 24
Finished Jun 11 12:25:08 PM PDT 24
Peak memory 200272 kb
Host smart-927025d8-9ba5-4896-b9af-96df2e4054e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516363332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.516363332
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.873673140
Short name T312
Test name
Test status
Simulation time 123323207 ps
CPU time 0.86 seconds
Started Jun 11 12:25:01 PM PDT 24
Finished Jun 11 12:25:04 PM PDT 24
Peak memory 200160 kb
Host smart-6ec77adf-07af-4f5a-9ac1-a6edc8c32e76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873673140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.873673140
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.4101801292
Short name T503
Test name
Test status
Simulation time 1220204151 ps
CPU time 5.56 seconds
Started Jun 11 12:25:00 PM PDT 24
Finished Jun 11 12:25:08 PM PDT 24
Peak memory 217936 kb
Host smart-d9e301f9-6b5d-4eff-bcd8-682abf8d550b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101801292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.4101801292
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3084690362
Short name T509
Test name
Test status
Simulation time 243248004 ps
CPU time 1.01 seconds
Started Jun 11 12:25:01 PM PDT 24
Finished Jun 11 12:25:05 PM PDT 24
Peak memory 217472 kb
Host smart-c7bf59a3-4f57-42e8-a777-e297032b83b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084690362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3084690362
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2524899175
Short name T511
Test name
Test status
Simulation time 155958332 ps
CPU time 0.82 seconds
Started Jun 11 12:24:55 PM PDT 24
Finished Jun 11 12:24:59 PM PDT 24
Peak memory 200128 kb
Host smart-bb5cfda1-3a5d-453f-9b1c-6c17d76401f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524899175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2524899175
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2009131144
Short name T457
Test name
Test status
Simulation time 1146536453 ps
CPU time 4.43 seconds
Started Jun 11 12:25:08 PM PDT 24
Finished Jun 11 12:25:14 PM PDT 24
Peak memory 200484 kb
Host smart-ed566f7d-c6e3-47eb-b0a5-60b5639af811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009131144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2009131144
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3332828668
Short name T297
Test name
Test status
Simulation time 148701207 ps
CPU time 1.19 seconds
Started Jun 11 12:25:03 PM PDT 24
Finished Jun 11 12:25:07 PM PDT 24
Peak memory 200372 kb
Host smart-036e3881-c118-4f2d-8d3e-b34b039f1e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332828668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3332828668
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1884708239
Short name T143
Test name
Test status
Simulation time 258652981 ps
CPU time 1.4 seconds
Started Jun 11 12:25:00 PM PDT 24
Finished Jun 11 12:25:03 PM PDT 24
Peak memory 200524 kb
Host smart-f2fbfc09-247f-4edc-aa58-edc103f0b3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884708239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1884708239
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2534525406
Short name T422
Test name
Test status
Simulation time 3807690951 ps
CPU time 16.1 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:21 PM PDT 24
Peak memory 210508 kb
Host smart-66686c92-5a74-4c98-83bd-dd409f22c322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534525406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2534525406
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.327829376
Short name T409
Test name
Test status
Simulation time 351820613 ps
CPU time 2.24 seconds
Started Jun 11 12:25:00 PM PDT 24
Finished Jun 11 12:25:05 PM PDT 24
Peak memory 200240 kb
Host smart-23d72129-e2ce-4568-8f16-5a02ea438848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327829376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.327829376
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.3555761481
Short name T522
Test name
Test status
Simulation time 176661372 ps
CPU time 1.26 seconds
Started Jun 11 12:25:00 PM PDT 24
Finished Jun 11 12:25:04 PM PDT 24
Peak memory 200564 kb
Host smart-45d1bc0b-b10f-4fca-8990-4c0653bee32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555761481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3555761481
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.778218542
Short name T424
Test name
Test status
Simulation time 66483875 ps
CPU time 0.74 seconds
Started Jun 11 12:25:07 PM PDT 24
Finished Jun 11 12:25:11 PM PDT 24
Peak memory 200144 kb
Host smart-bc91ed49-f141-48f5-bdb6-8000cc6ec6b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778218542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.778218542
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.3831744887
Short name T480
Test name
Test status
Simulation time 1227254933 ps
CPU time 5.39 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:11 PM PDT 24
Peak memory 217924 kb
Host smart-feb795aa-cecd-4a49-b986-5bfc3daedcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831744887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.3831744887
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1378174257
Short name T54
Test name
Test status
Simulation time 245289155 ps
CPU time 1.01 seconds
Started Jun 11 12:25:01 PM PDT 24
Finished Jun 11 12:25:05 PM PDT 24
Peak memory 217472 kb
Host smart-14aa2f59-8a04-4a5a-9283-4a8b447b2c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378174257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1378174257
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3929862108
Short name T451
Test name
Test status
Simulation time 98872532 ps
CPU time 0.77 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:05 PM PDT 24
Peak memory 200076 kb
Host smart-95cc67da-5d0b-49c0-bb15-f29229ba3e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929862108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3929862108
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1887316014
Short name T355
Test name
Test status
Simulation time 1315295731 ps
CPU time 5.08 seconds
Started Jun 11 12:25:00 PM PDT 24
Finished Jun 11 12:25:07 PM PDT 24
Peak memory 200432 kb
Host smart-0c7933cd-f688-42cb-bf8e-23e287c43518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887316014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1887316014
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2307452544
Short name T523
Test name
Test status
Simulation time 108774429 ps
CPU time 0.96 seconds
Started Jun 11 12:25:01 PM PDT 24
Finished Jun 11 12:25:05 PM PDT 24
Peak memory 200276 kb
Host smart-f9a86755-03b5-4430-aa91-e3e92cd05920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307452544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2307452544
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.4116379082
Short name T89
Test name
Test status
Simulation time 202026204 ps
CPU time 1.32 seconds
Started Jun 11 12:24:55 PM PDT 24
Finished Jun 11 12:24:59 PM PDT 24
Peak memory 200492 kb
Host smart-46933e76-6ad8-4118-98d2-ffbd03ec6ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116379082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.4116379082
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.2439064851
Short name T540
Test name
Test status
Simulation time 10405327138 ps
CPU time 37.31 seconds
Started Jun 11 12:25:07 PM PDT 24
Finished Jun 11 12:25:47 PM PDT 24
Peak memory 208812 kb
Host smart-0f699a28-6b7b-4721-a311-eb2309f45384
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439064851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2439064851
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.2791887857
Short name T385
Test name
Test status
Simulation time 266542204 ps
CPU time 1.69 seconds
Started Jun 11 12:25:07 PM PDT 24
Finished Jun 11 12:25:11 PM PDT 24
Peak memory 200308 kb
Host smart-6e6cefde-a78a-4e42-bf35-03567961cd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791887857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2791887857
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1443180015
Short name T497
Test name
Test status
Simulation time 84908986 ps
CPU time 0.82 seconds
Started Jun 11 12:25:03 PM PDT 24
Finished Jun 11 12:25:07 PM PDT 24
Peak memory 200028 kb
Host smart-11a7d23c-5111-429c-8383-20a5c1a4e128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443180015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1443180015
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.4120269266
Short name T256
Test name
Test status
Simulation time 68941775 ps
CPU time 0.74 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:06 PM PDT 24
Peak memory 200016 kb
Host smart-ef8eb10f-a303-47cf-ae86-238011aeeda5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120269266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.4120269266
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.490121955
Short name T4
Test name
Test status
Simulation time 1898429871 ps
CPU time 7.45 seconds
Started Jun 11 12:25:07 PM PDT 24
Finished Jun 11 12:25:17 PM PDT 24
Peak memory 216984 kb
Host smart-d1703e3c-b0cb-44a0-91ef-41d5b7bc14ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490121955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.490121955
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2472425768
Short name T198
Test name
Test status
Simulation time 245537131 ps
CPU time 1.06 seconds
Started Jun 11 12:25:00 PM PDT 24
Finished Jun 11 12:25:04 PM PDT 24
Peak memory 217468 kb
Host smart-b88504ed-0148-4d87-9540-61ccfe8b24f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472425768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2472425768
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.643832255
Short name T537
Test name
Test status
Simulation time 200649416 ps
CPU time 0.88 seconds
Started Jun 11 12:25:03 PM PDT 24
Finished Jun 11 12:25:07 PM PDT 24
Peak memory 200048 kb
Host smart-6992f446-c248-457a-bc02-5dc16d2e4738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643832255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.643832255
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.330168527
Short name T431
Test name
Test status
Simulation time 1202783849 ps
CPU time 5.05 seconds
Started Jun 11 12:25:03 PM PDT 24
Finished Jun 11 12:25:12 PM PDT 24
Peak memory 200528 kb
Host smart-920669cc-edd9-4f82-b5f5-1ed37d8add3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330168527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.330168527
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1558796672
Short name T272
Test name
Test status
Simulation time 163404769 ps
CPU time 1.12 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:06 PM PDT 24
Peak memory 200276 kb
Host smart-dfcccd4f-39a5-492d-9c38-fb59283f7500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558796672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1558796672
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.2729401446
Short name T274
Test name
Test status
Simulation time 252657976 ps
CPU time 1.47 seconds
Started Jun 11 12:25:08 PM PDT 24
Finished Jun 11 12:25:11 PM PDT 24
Peak memory 200444 kb
Host smart-661b6c67-2e81-437f-a891-bacde5098528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729401446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2729401446
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.703704660
Short name T319
Test name
Test status
Simulation time 411036762 ps
CPU time 2.17 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:08 PM PDT 24
Peak memory 208628 kb
Host smart-b415e61d-e98f-425e-b516-eab432880a77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703704660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.703704660
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2596948315
Short name T367
Test name
Test status
Simulation time 146869869 ps
CPU time 1.7 seconds
Started Jun 11 12:25:03 PM PDT 24
Finished Jun 11 12:25:08 PM PDT 24
Peak memory 200360 kb
Host smart-76f639f1-e93a-4aba-a435-6c05f3d9ee49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596948315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2596948315
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2102840978
Short name T231
Test name
Test status
Simulation time 147443755 ps
CPU time 1.06 seconds
Started Jun 11 12:25:03 PM PDT 24
Finished Jun 11 12:25:07 PM PDT 24
Peak memory 200244 kb
Host smart-23bef69e-fbda-45e1-abea-f04cdb7651bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102840978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2102840978
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.735334486
Short name T172
Test name
Test status
Simulation time 78029078 ps
CPU time 0.77 seconds
Started Jun 11 12:25:03 PM PDT 24
Finished Jun 11 12:25:07 PM PDT 24
Peak memory 200192 kb
Host smart-1e4a745a-f0cc-4491-bd41-f2eba83cc80c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735334486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.735334486
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.831394069
Short name T36
Test name
Test status
Simulation time 1224282960 ps
CPU time 5.93 seconds
Started Jun 11 12:25:01 PM PDT 24
Finished Jun 11 12:25:10 PM PDT 24
Peak memory 221944 kb
Host smart-a1798924-bedc-409c-bd5a-c3d709c461a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831394069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.831394069
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2061115190
Short name T53
Test name
Test status
Simulation time 243747719 ps
CPU time 1.1 seconds
Started Jun 11 12:25:03 PM PDT 24
Finished Jun 11 12:25:08 PM PDT 24
Peak memory 217472 kb
Host smart-c971a728-21a2-490f-9013-585aa4a04990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061115190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2061115190
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.1898613294
Short name T304
Test name
Test status
Simulation time 187900658 ps
CPU time 0.82 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:06 PM PDT 24
Peak memory 200196 kb
Host smart-931d3d6b-06ce-4874-ae5b-1b18b8577b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898613294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1898613294
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2846888251
Short name T244
Test name
Test status
Simulation time 1982371395 ps
CPU time 7.25 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:13 PM PDT 24
Peak memory 200456 kb
Host smart-7f018882-08da-4ddf-8f05-fc68ad96fd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846888251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2846888251
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2212663587
Short name T502
Test name
Test status
Simulation time 150787274 ps
CPU time 1.15 seconds
Started Jun 11 12:25:03 PM PDT 24
Finished Jun 11 12:25:08 PM PDT 24
Peak memory 200244 kb
Host smart-ae07df80-399e-4b95-a8ea-d9878ab8bf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212663587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2212663587
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.3753426918
Short name T475
Test name
Test status
Simulation time 198240476 ps
CPU time 1.31 seconds
Started Jun 11 12:25:00 PM PDT 24
Finished Jun 11 12:25:03 PM PDT 24
Peak memory 200432 kb
Host smart-7b003117-f1e4-404b-aa66-86b6f4c2e1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753426918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3753426918
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2135732842
Short name T373
Test name
Test status
Simulation time 3110937961 ps
CPU time 13.49 seconds
Started Jun 11 12:25:08 PM PDT 24
Finished Jun 11 12:25:23 PM PDT 24
Peak memory 208828 kb
Host smart-e5424fa9-87ee-4060-b17f-372f4cea4cd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135732842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2135732842
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3583062376
Short name T344
Test name
Test status
Simulation time 331584146 ps
CPU time 1.99 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:07 PM PDT 24
Peak memory 200232 kb
Host smart-d05f2f16-aba1-4124-afe6-8d5980c98469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583062376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3583062376
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1080686404
Short name T326
Test name
Test status
Simulation time 158731727 ps
CPU time 1.16 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:06 PM PDT 24
Peak memory 200556 kb
Host smart-b0bc9406-312d-40ef-8eb6-94832749dfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080686404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1080686404
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.2629350375
Short name T293
Test name
Test status
Simulation time 78079382 ps
CPU time 0.77 seconds
Started Jun 11 12:24:56 PM PDT 24
Finished Jun 11 12:25:00 PM PDT 24
Peak memory 200156 kb
Host smart-b5874ea4-7971-4fa4-bbba-f2877d83f155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629350375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2629350375
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3850659582
Short name T38
Test name
Test status
Simulation time 1235628997 ps
CPU time 5.4 seconds
Started Jun 11 12:24:56 PM PDT 24
Finished Jun 11 12:25:05 PM PDT 24
Peak memory 221528 kb
Host smart-277ce3b5-6236-4ef4-967b-4be0dd6ff32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850659582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3850659582
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2753860486
Short name T87
Test name
Test status
Simulation time 246439556 ps
CPU time 1.05 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:06 PM PDT 24
Peak memory 218452 kb
Host smart-a77c10f9-f6c7-46b8-b17f-327dd17cdc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753860486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2753860486
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1153121104
Short name T20
Test name
Test status
Simulation time 145702404 ps
CPU time 0.84 seconds
Started Jun 11 12:25:03 PM PDT 24
Finished Jun 11 12:25:07 PM PDT 24
Peak memory 200168 kb
Host smart-37a8b5fc-eb7a-47e5-99de-92b4f8f792f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153121104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1153121104
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3149270803
Short name T139
Test name
Test status
Simulation time 1490996396 ps
CPU time 5.61 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:11 PM PDT 24
Peak memory 200552 kb
Host smart-175c1754-676f-421d-8d91-b2907ded4ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149270803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3149270803
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2899359243
Short name T524
Test name
Test status
Simulation time 145539613 ps
CPU time 1.06 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:05 PM PDT 24
Peak memory 200344 kb
Host smart-c1825b62-9020-4295-b274-57d3f7740740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899359243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2899359243
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3650418824
Short name T375
Test name
Test status
Simulation time 120941380 ps
CPU time 1.1 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:06 PM PDT 24
Peak memory 200412 kb
Host smart-14e094a5-3257-4851-8041-3b3c45d7fc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650418824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3650418824
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3716904840
Short name T294
Test name
Test status
Simulation time 13371977949 ps
CPU time 45.64 seconds
Started Jun 11 12:25:03 PM PDT 24
Finished Jun 11 12:25:52 PM PDT 24
Peak memory 210208 kb
Host smart-211d1b89-6baf-4694-abf9-75f712f0c004
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716904840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3716904840
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.1989850864
Short name T535
Test name
Test status
Simulation time 116866868 ps
CPU time 1.41 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:07 PM PDT 24
Peak memory 200332 kb
Host smart-acfe1e5c-906d-4dfd-b2eb-893bffed9f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989850864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1989850864
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.1230258220
Short name T250
Test name
Test status
Simulation time 124997769 ps
CPU time 1.1 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:06 PM PDT 24
Peak memory 200344 kb
Host smart-75359dfb-fa00-4012-9a75-bd9f2797d473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230258220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1230258220
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.3857647320
Short name T288
Test name
Test status
Simulation time 69040812 ps
CPU time 0.76 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:05 PM PDT 24
Peak memory 200184 kb
Host smart-9de979f2-54a7-46d4-ac5c-5fab048ec034
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857647320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3857647320
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2492400004
Short name T352
Test name
Test status
Simulation time 1221418588 ps
CPU time 5.35 seconds
Started Jun 11 12:25:05 PM PDT 24
Finished Jun 11 12:25:14 PM PDT 24
Peak memory 218048 kb
Host smart-76642cf8-84b5-4e91-b80d-b76a1e4fca2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492400004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2492400004
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3540941391
Short name T354
Test name
Test status
Simulation time 244498832 ps
CPU time 1 seconds
Started Jun 11 12:25:05 PM PDT 24
Finished Jun 11 12:25:10 PM PDT 24
Peak memory 217620 kb
Host smart-a7ba0e22-d1ad-49cd-b9be-20719fd2582d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540941391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3540941391
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1087859866
Short name T216
Test name
Test status
Simulation time 73617972 ps
CPU time 0.75 seconds
Started Jun 11 12:24:56 PM PDT 24
Finished Jun 11 12:25:00 PM PDT 24
Peak memory 200160 kb
Host smart-60e5c9ca-6026-42c0-89a1-4aa18d7e7b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087859866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1087859866
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2603111474
Short name T462
Test name
Test status
Simulation time 769739600 ps
CPU time 4.18 seconds
Started Jun 11 12:25:04 PM PDT 24
Finished Jun 11 12:25:12 PM PDT 24
Peak memory 200544 kb
Host smart-e41284e0-b488-4eb9-9d76-d6fda1669326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603111474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2603111474
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3338888554
Short name T495
Test name
Test status
Simulation time 148938836 ps
CPU time 1.08 seconds
Started Jun 11 12:24:53 PM PDT 24
Finished Jun 11 12:24:56 PM PDT 24
Peak memory 200332 kb
Host smart-4a9146ae-6632-4865-87d3-eebf47358293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338888554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3338888554
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.820229416
Short name T142
Test name
Test status
Simulation time 252910224 ps
CPU time 1.58 seconds
Started Jun 11 12:25:04 PM PDT 24
Finished Jun 11 12:25:10 PM PDT 24
Peak memory 200536 kb
Host smart-448a4e82-e139-45cd-b1ce-b6694fd7c956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820229416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.820229416
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3194641799
Short name T271
Test name
Test status
Simulation time 1281783612 ps
CPU time 5.78 seconds
Started Jun 11 12:25:03 PM PDT 24
Finished Jun 11 12:25:13 PM PDT 24
Peak memory 208720 kb
Host smart-fd0700ac-1737-484b-93cc-8b7a04fcae5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194641799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3194641799
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3150776964
Short name T95
Test name
Test status
Simulation time 123706059 ps
CPU time 1.45 seconds
Started Jun 11 12:25:05 PM PDT 24
Finished Jun 11 12:25:10 PM PDT 24
Peak memory 200380 kb
Host smart-e974c9d2-9576-4aac-93c3-337e9c0310cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150776964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3150776964
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3312605863
Short name T362
Test name
Test status
Simulation time 158788227 ps
CPU time 1.19 seconds
Started Jun 11 12:24:54 PM PDT 24
Finished Jun 11 12:24:59 PM PDT 24
Peak memory 200456 kb
Host smart-c5b816cb-c582-4adb-b0fd-182a63f7fe50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312605863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3312605863
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2994123669
Short name T176
Test name
Test status
Simulation time 152245944 ps
CPU time 0.89 seconds
Started Jun 11 12:23:34 PM PDT 24
Finished Jun 11 12:23:40 PM PDT 24
Peak memory 200152 kb
Host smart-332b5c4f-d3d7-47e8-86e9-6bf6d029680d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994123669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2994123669
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.904070520
Short name T59
Test name
Test status
Simulation time 1220000086 ps
CPU time 5.27 seconds
Started Jun 11 12:23:30 PM PDT 24
Finished Jun 11 12:23:40 PM PDT 24
Peak memory 217856 kb
Host smart-8bd00166-5dd5-47bd-9e5b-c5211700c53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904070520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.904070520
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1377057400
Short name T88
Test name
Test status
Simulation time 243915469 ps
CPU time 1.05 seconds
Started Jun 11 12:23:33 PM PDT 24
Finished Jun 11 12:23:38 PM PDT 24
Peak memory 217488 kb
Host smart-65b67dc3-5170-4dc5-b1ab-46aba1a68a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377057400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1377057400
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.287128779
Short name T268
Test name
Test status
Simulation time 217748703 ps
CPU time 1.01 seconds
Started Jun 11 12:23:34 PM PDT 24
Finished Jun 11 12:23:39 PM PDT 24
Peak memory 200128 kb
Host smart-0c5caada-e952-4e56-a733-9c5c6678a0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287128779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.287128779
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.3161644405
Short name T465
Test name
Test status
Simulation time 877991424 ps
CPU time 4.06 seconds
Started Jun 11 12:23:22 PM PDT 24
Finished Jun 11 12:23:29 PM PDT 24
Peak memory 200352 kb
Host smart-7eaeab81-6be7-418b-bec1-21683b658e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161644405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3161644405
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.539626247
Short name T26
Test name
Test status
Simulation time 148112852 ps
CPU time 1.1 seconds
Started Jun 11 12:23:31 PM PDT 24
Finished Jun 11 12:23:37 PM PDT 24
Peak memory 200284 kb
Host smart-8722115d-6bac-48c0-8935-8b9dcdb4dd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539626247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.539626247
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.999604717
Short name T368
Test name
Test status
Simulation time 250195142 ps
CPU time 1.49 seconds
Started Jun 11 12:23:36 PM PDT 24
Finished Jun 11 12:23:41 PM PDT 24
Peak memory 200512 kb
Host smart-9b8104bc-7070-4ac7-b5dc-7ae05e7b95ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999604717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.999604717
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2344482180
Short name T275
Test name
Test status
Simulation time 1692576630 ps
CPU time 7.65 seconds
Started Jun 11 12:23:34 PM PDT 24
Finished Jun 11 12:23:46 PM PDT 24
Peak memory 200520 kb
Host smart-4519f272-085d-4190-9a4b-9cd2bf61feec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344482180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2344482180
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1754388375
Short name T482
Test name
Test status
Simulation time 337790135 ps
CPU time 1.89 seconds
Started Jun 11 12:23:28 PM PDT 24
Finished Jun 11 12:23:35 PM PDT 24
Peak memory 200164 kb
Host smart-9ef78969-3ca7-410f-afb7-88272ae04ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754388375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1754388375
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.856870902
Short name T496
Test name
Test status
Simulation time 248697832 ps
CPU time 1.44 seconds
Started Jun 11 12:23:34 PM PDT 24
Finished Jun 11 12:23:39 PM PDT 24
Peak memory 200328 kb
Host smart-ed6f1819-eab1-4866-b83a-47157738d988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856870902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.856870902
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2538722651
Short name T153
Test name
Test status
Simulation time 66036660 ps
CPU time 0.73 seconds
Started Jun 11 12:23:30 PM PDT 24
Finished Jun 11 12:23:36 PM PDT 24
Peak memory 200044 kb
Host smart-adad858d-90a3-4186-9457-40724063f4f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538722651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2538722651
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1633400616
Short name T285
Test name
Test status
Simulation time 2353011834 ps
CPU time 7.54 seconds
Started Jun 11 12:23:31 PM PDT 24
Finished Jun 11 12:23:42 PM PDT 24
Peak memory 221820 kb
Host smart-7c6463c9-3bc5-412e-a253-fe843f5aa3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633400616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1633400616
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2755591023
Short name T370
Test name
Test status
Simulation time 244583042 ps
CPU time 0.97 seconds
Started Jun 11 12:23:30 PM PDT 24
Finished Jun 11 12:23:36 PM PDT 24
Peak memory 217468 kb
Host smart-a830d0ee-47ef-4c92-8027-5e99c3e47fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755591023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2755591023
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1355801746
Short name T17
Test name
Test status
Simulation time 178539213 ps
CPU time 0.83 seconds
Started Jun 11 12:23:30 PM PDT 24
Finished Jun 11 12:23:36 PM PDT 24
Peak memory 200048 kb
Host smart-1d372533-b6c5-4c39-901f-d7e9b775bb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355801746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1355801746
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1194530060
Short name T179
Test name
Test status
Simulation time 963871848 ps
CPU time 4.75 seconds
Started Jun 11 12:23:24 PM PDT 24
Finished Jun 11 12:23:32 PM PDT 24
Peak memory 200432 kb
Host smart-f6df29c9-7822-4bb7-81c2-ab0d93b98b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194530060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1194530060
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2901261258
Short name T493
Test name
Test status
Simulation time 105035858 ps
CPU time 0.98 seconds
Started Jun 11 12:23:21 PM PDT 24
Finished Jun 11 12:23:24 PM PDT 24
Peak memory 200132 kb
Host smart-a5a1c38f-4d10-40fa-99d8-e859a09616e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901261258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2901261258
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1197207665
Short name T416
Test name
Test status
Simulation time 127873423 ps
CPU time 1.17 seconds
Started Jun 11 12:23:34 PM PDT 24
Finished Jun 11 12:23:39 PM PDT 24
Peak memory 200492 kb
Host smart-05a51254-95a7-4a87-a872-fd233ac3de87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197207665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1197207665
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3325992635
Short name T188
Test name
Test status
Simulation time 3329548963 ps
CPU time 14.2 seconds
Started Jun 11 12:23:31 PM PDT 24
Finished Jun 11 12:23:50 PM PDT 24
Peak memory 208804 kb
Host smart-4b38ddc3-e9ec-4aaa-bf30-0f7e2e3c92ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325992635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3325992635
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1283653382
Short name T180
Test name
Test status
Simulation time 385279612 ps
CPU time 2.46 seconds
Started Jun 11 12:23:33 PM PDT 24
Finished Jun 11 12:23:40 PM PDT 24
Peak memory 200240 kb
Host smart-65706a2f-6845-4408-a223-ff642e8fba9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283653382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1283653382
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.2991624157
Short name T163
Test name
Test status
Simulation time 129076452 ps
CPU time 1 seconds
Started Jun 11 12:23:32 PM PDT 24
Finished Jun 11 12:23:38 PM PDT 24
Peak memory 200244 kb
Host smart-5446a1c8-4329-41e7-b529-5d8b6715a6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991624157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2991624157
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.266391385
Short name T492
Test name
Test status
Simulation time 70539441 ps
CPU time 0.77 seconds
Started Jun 11 12:23:46 PM PDT 24
Finished Jun 11 12:23:55 PM PDT 24
Peak memory 199968 kb
Host smart-b0f3d9de-8904-4d97-818b-cd994b6b4140
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266391385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.266391385
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.710463048
Short name T389
Test name
Test status
Simulation time 1224046467 ps
CPU time 5.37 seconds
Started Jun 11 12:23:36 PM PDT 24
Finished Jun 11 12:23:45 PM PDT 24
Peak memory 217940 kb
Host smart-14333d7f-2398-4571-b7fb-9e1295a58e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710463048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.710463048
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2234725406
Short name T302
Test name
Test status
Simulation time 257026606 ps
CPU time 1.05 seconds
Started Jun 11 12:23:41 PM PDT 24
Finished Jun 11 12:23:45 PM PDT 24
Peak memory 217480 kb
Host smart-efe31a66-a53f-40f2-b91b-1030b1bed437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234725406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2234725406
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.240589511
Short name T394
Test name
Test status
Simulation time 178829284 ps
CPU time 0.8 seconds
Started Jun 11 12:23:32 PM PDT 24
Finished Jun 11 12:23:38 PM PDT 24
Peak memory 200056 kb
Host smart-359948ae-3161-4b07-a1bb-cb062e5f4e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240589511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.240589511
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3859947372
Short name T111
Test name
Test status
Simulation time 1753418448 ps
CPU time 6.33 seconds
Started Jun 11 12:23:24 PM PDT 24
Finished Jun 11 12:23:34 PM PDT 24
Peak memory 200500 kb
Host smart-b356f9a3-151d-4ba7-8d22-bd14fa8d6009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859947372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3859947372
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.574521023
Short name T448
Test name
Test status
Simulation time 106156631 ps
CPU time 1.03 seconds
Started Jun 11 12:23:33 PM PDT 24
Finished Jun 11 12:23:38 PM PDT 24
Peak memory 200284 kb
Host smart-005152ce-7246-4831-958e-f26d1c11bcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574521023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.574521023
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3144761970
Short name T343
Test name
Test status
Simulation time 233156875 ps
CPU time 1.36 seconds
Started Jun 11 12:23:33 PM PDT 24
Finished Jun 11 12:23:39 PM PDT 24
Peak memory 200432 kb
Host smart-970956cb-1ba2-487c-bffc-bea0d27abc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144761970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3144761970
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2077277101
Short name T467
Test name
Test status
Simulation time 13048506039 ps
CPU time 46.71 seconds
Started Jun 11 12:23:32 PM PDT 24
Finished Jun 11 12:24:23 PM PDT 24
Peak memory 208736 kb
Host smart-f1b3351f-6327-4404-a7ea-81629f6f93ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077277101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2077277101
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3607837548
Short name T280
Test name
Test status
Simulation time 131317004 ps
CPU time 1.56 seconds
Started Jun 11 12:23:39 PM PDT 24
Finished Jun 11 12:23:44 PM PDT 24
Peak memory 199868 kb
Host smart-2dfd9d8a-9e21-4aa3-b0fe-8510c70564e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607837548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3607837548
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.335981352
Short name T240
Test name
Test status
Simulation time 171241669 ps
CPU time 1.25 seconds
Started Jun 11 12:23:31 PM PDT 24
Finished Jun 11 12:23:36 PM PDT 24
Peak memory 200452 kb
Host smart-08d70f3c-1444-4bfc-96da-94854b102644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335981352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.335981352
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.4211150633
Short name T400
Test name
Test status
Simulation time 83940147 ps
CPU time 0.74 seconds
Started Jun 11 12:23:47 PM PDT 24
Finished Jun 11 12:23:56 PM PDT 24
Peak memory 200152 kb
Host smart-36eb83ef-4f8f-46e6-84e6-72e8fa7b9402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211150633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.4211150633
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2446624386
Short name T504
Test name
Test status
Simulation time 2360091730 ps
CPU time 7.84 seconds
Started Jun 11 12:23:46 PM PDT 24
Finished Jun 11 12:24:02 PM PDT 24
Peak memory 218132 kb
Host smart-13235bd0-7168-46c8-ac8e-ca0e07a7f292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446624386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2446624386
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2334967850
Short name T158
Test name
Test status
Simulation time 243861482 ps
CPU time 1.07 seconds
Started Jun 11 12:23:30 PM PDT 24
Finished Jun 11 12:23:36 PM PDT 24
Peak memory 217496 kb
Host smart-8d4fc267-b5be-453d-811d-ef5bdd56785b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334967850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2334967850
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3021719284
Short name T303
Test name
Test status
Simulation time 174039104 ps
CPU time 0.84 seconds
Started Jun 11 12:23:41 PM PDT 24
Finished Jun 11 12:23:45 PM PDT 24
Peak memory 200076 kb
Host smart-8c8adfdd-3d62-45dc-b6d5-25f2671d444d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021719284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3021719284
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.700593454
Short name T215
Test name
Test status
Simulation time 1430923138 ps
CPU time 5.62 seconds
Started Jun 11 12:23:35 PM PDT 24
Finished Jun 11 12:23:45 PM PDT 24
Peak memory 200412 kb
Host smart-fee29413-e563-45ff-8c67-39e924482ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700593454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.700593454
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1371215270
Short name T320
Test name
Test status
Simulation time 105613773 ps
CPU time 0.99 seconds
Started Jun 11 12:23:34 PM PDT 24
Finished Jun 11 12:23:39 PM PDT 24
Peak memory 200244 kb
Host smart-2fc740e7-2bb8-4488-97f1-5afa86c1b773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371215270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1371215270
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.1397095873
Short name T485
Test name
Test status
Simulation time 111076880 ps
CPU time 1.23 seconds
Started Jun 11 12:23:32 PM PDT 24
Finished Jun 11 12:23:38 PM PDT 24
Peak memory 200780 kb
Host smart-8db66653-b343-4f91-9984-2587b1bc37ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397095873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1397095873
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.3898215389
Short name T491
Test name
Test status
Simulation time 1685169795 ps
CPU time 5.45 seconds
Started Jun 11 12:23:37 PM PDT 24
Finished Jun 11 12:23:46 PM PDT 24
Peak memory 208696 kb
Host smart-b4c10156-4f33-4f3b-b3a1-fe423df541b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898215389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3898215389
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.790860852
Short name T454
Test name
Test status
Simulation time 342624417 ps
CPU time 1.96 seconds
Started Jun 11 12:23:43 PM PDT 24
Finished Jun 11 12:23:50 PM PDT 24
Peak memory 200324 kb
Host smart-f1e85912-75cb-4421-95c3-2c9b1ba6707c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790860852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.790860852
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2675798909
Short name T245
Test name
Test status
Simulation time 120416585 ps
CPU time 1.06 seconds
Started Jun 11 12:23:32 PM PDT 24
Finished Jun 11 12:23:38 PM PDT 24
Peak memory 200592 kb
Host smart-a7ef4152-c70d-4329-82df-4084a9402e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675798909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2675798909
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.1961359666
Short name T289
Test name
Test status
Simulation time 60277634 ps
CPU time 0.73 seconds
Started Jun 11 12:23:36 PM PDT 24
Finished Jun 11 12:23:41 PM PDT 24
Peak memory 200148 kb
Host smart-467a221f-924e-46a8-9767-eeb24e63f162
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961359666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1961359666
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1019584695
Short name T5
Test name
Test status
Simulation time 248577726 ps
CPU time 1.14 seconds
Started Jun 11 12:23:39 PM PDT 24
Finished Jun 11 12:23:44 PM PDT 24
Peak memory 217408 kb
Host smart-6e9fe2a5-1471-41d4-b3b8-55a1579c0c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019584695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1019584695
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1005622962
Short name T246
Test name
Test status
Simulation time 204042124 ps
CPU time 0.85 seconds
Started Jun 11 12:23:32 PM PDT 24
Finished Jun 11 12:23:38 PM PDT 24
Peak memory 200108 kb
Host smart-a210016d-40d4-49df-b1a6-80a997ecd66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005622962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1005622962
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.1402932967
Short name T104
Test name
Test status
Simulation time 1345286201 ps
CPU time 5.19 seconds
Started Jun 11 12:23:36 PM PDT 24
Finished Jun 11 12:23:45 PM PDT 24
Peak memory 200500 kb
Host smart-8ea3921d-e0d0-4654-977c-eb9f5205aae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402932967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1402932967
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.4262573716
Short name T30
Test name
Test status
Simulation time 94661951 ps
CPU time 0.92 seconds
Started Jun 11 12:23:29 PM PDT 24
Finished Jun 11 12:23:35 PM PDT 24
Peak memory 200200 kb
Host smart-b5829ec5-fd26-49b5-8eeb-092f4b139424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262573716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.4262573716
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1196749690
Short name T477
Test name
Test status
Simulation time 255317702 ps
CPU time 1.46 seconds
Started Jun 11 12:23:44 PM PDT 24
Finished Jun 11 12:23:53 PM PDT 24
Peak memory 200520 kb
Host smart-acc03ec2-87a1-495a-b848-053f5967d83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196749690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1196749690
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.4093693523
Short name T380
Test name
Test status
Simulation time 590208955 ps
CPU time 2.3 seconds
Started Jun 11 12:23:42 PM PDT 24
Finished Jun 11 12:23:47 PM PDT 24
Peak memory 200472 kb
Host smart-3e73a512-dc73-42e6-a6d2-b20ead06d38c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093693523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.4093693523
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2517769191
Short name T269
Test name
Test status
Simulation time 120777574 ps
CPU time 1.53 seconds
Started Jun 11 12:23:43 PM PDT 24
Finished Jun 11 12:23:48 PM PDT 24
Peak memory 200272 kb
Host smart-e47f284a-1fb5-4ddf-9567-5ff6c500c456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517769191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2517769191
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1671642029
Short name T161
Test name
Test status
Simulation time 120701956 ps
CPU time 1.01 seconds
Started Jun 11 12:23:44 PM PDT 24
Finished Jun 11 12:23:52 PM PDT 24
Peak memory 200328 kb
Host smart-ba99ef83-82cd-40ac-830d-933b21ebf904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671642029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1671642029
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%