Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8001

1

T2

17

T4

31

T8

29

auto[1]

10823

1

T2

84

T3

4

T4

17

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5808	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6402	1			T1	1		T2	27		T3	2
reset_info_cp[2]	2898	1			T2	16		T3	1		T4	7
reset_info_cp[4]	3773	1			T2	18		T3	1		T4	11
reset_info_cp[8]	101	1			T2	1		T9	3		T75	2
reset_info_cp[16]	124	1			T9	4		T26	1		T27	1
reset_info_cp[32]	108	1			T2	1		T9	1		T75	1
reset_info_cp[64]	122	1			T2	1		T8	1		T9	2
reset_info_cp[128]	108	1			T9	1		T26	1		T33	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3125	1			T2	17		T4	10		T8	15
reset_info_cp[1]	auto[1]	2657	1			T2	9		T3	1		T4	4
reset_info_cp[2]	auto[0]	907	1			T4	5		T8	2		T9	29
reset_info_cp[2]	auto[1]	1991	1			T2	16		T3	1		T4	2
reset_info_cp[4]	auto[0]	1359	1			T4	4		T8	5		T9	38
reset_info_cp[4]	auto[1]	2414	1			T2	18		T3	1		T4	7
reset_info_cp[8]	auto[0]	33	1			T9	2		T75	2		T71	1
reset_info_cp[8]	auto[1]	68	1			T2	1		T9	1		T30	1
reset_info_cp[16]	auto[0]	43	1			T9	1		T27	1		T28	1
reset_info_cp[16]	auto[1]	81	1			T9	3		T26	1		T34	1
reset_info_cp[32]	auto[0]	40	1			T75	1		T85	1		T130	1
reset_info_cp[32]	auto[1]	68	1			T2	1		T9	1		T26	1
reset_info_cp[64]	auto[0]	51	1			T9	1		T27	1		T70	1
reset_info_cp[64]	auto[1]	71	1			T2	1		T8	1		T9	1
reset_info_cp[128]	auto[0]	43	1			T70	1		T71	1		T73	2
reset_info_cp[128]	auto[1]	65	1			T9	1		T26	1		T33	1