Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T539 /workspace/coverage/default/17.rstmgr_reset.3443573977 Jun 13 12:36:05 PM PDT 24 Jun 13 12:36:12 PM PDT 24 776531042 ps
T540 /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.4064974408 Jun 13 12:36:04 PM PDT 24 Jun 13 12:36:08 PM PDT 24 146867179 ps
T541 /workspace/coverage/default/6.rstmgr_por_stretcher.1026387642 Jun 13 12:36:04 PM PDT 24 Jun 13 12:36:08 PM PDT 24 139493483 ps
T542 /workspace/coverage/default/48.rstmgr_por_stretcher.1406282790 Jun 13 12:36:47 PM PDT 24 Jun 13 12:36:49 PM PDT 24 177613742 ps
T543 /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.3102381097 Jun 13 12:36:44 PM PDT 24 Jun 13 12:36:52 PM PDT 24 1889301660 ps
T52 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1306287547 Jun 13 12:35:35 PM PDT 24 Jun 13 12:35:40 PM PDT 24 507488395 ps
T56 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3161617422 Jun 13 12:35:26 PM PDT 24 Jun 13 12:35:28 PM PDT 24 171902345 ps
T53 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1472477612 Jun 13 12:35:30 PM PDT 24 Jun 13 12:35:31 PM PDT 24 60152690 ps
T57 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1429402486 Jun 13 12:35:22 PM PDT 24 Jun 13 12:35:25 PM PDT 24 297366010 ps
T58 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1711091368 Jun 13 12:35:36 PM PDT 24 Jun 13 12:35:40 PM PDT 24 96771959 ps
T79 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3771245911 Jun 13 12:35:37 PM PDT 24 Jun 13 12:35:42 PM PDT 24 109321924 ps
T54 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2979273954 Jun 13 12:35:23 PM PDT 24 Jun 13 12:35:29 PM PDT 24 479614209 ps
T55 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3685828092 Jun 13 12:35:24 PM PDT 24 Jun 13 12:35:28 PM PDT 24 462527910 ps
T97 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1075346281 Jun 13 12:35:44 PM PDT 24 Jun 13 12:35:46 PM PDT 24 123980969 ps
T64 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1826422299 Jun 13 12:35:26 PM PDT 24 Jun 13 12:35:29 PM PDT 24 487078594 ps
T80 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2371547294 Jun 13 12:35:39 PM PDT 24 Jun 13 12:35:44 PM PDT 24 414582040 ps
T65 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1008643928 Jun 13 12:35:30 PM PDT 24 Jun 13 12:35:32 PM PDT 24 121207163 ps
T544 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3337084321 Jun 13 12:35:27 PM PDT 24 Jun 13 12:35:37 PM PDT 24 2287552318 ps
T106 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3807380332 Jun 13 12:35:39 PM PDT 24 Jun 13 12:35:44 PM PDT 24 796777771 ps
T81 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1967328104 Jun 13 12:35:35 PM PDT 24 Jun 13 12:35:39 PM PDT 24 108527039 ps
T82 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.758244897 Jun 13 12:35:32 PM PDT 24 Jun 13 12:35:35 PM PDT 24 106609679 ps
T545 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.301330445 Jun 13 12:35:23 PM PDT 24 Jun 13 12:35:25 PM PDT 24 98207957 ps
T86 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2980950502 Jun 13 12:35:24 PM PDT 24 Jun 13 12:35:26 PM PDT 24 71705775 ps
T83 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.4147170530 Jun 13 12:35:25 PM PDT 24 Jun 13 12:35:28 PM PDT 24 191414245 ps
T98 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.797894855 Jun 13 12:35:34 PM PDT 24 Jun 13 12:35:39 PM PDT 24 106482150 ps
T99 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1790679333 Jun 13 12:35:35 PM PDT 24 Jun 13 12:35:39 PM PDT 24 153027860 ps
T100 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.782073738 Jun 13 12:35:32 PM PDT 24 Jun 13 12:35:36 PM PDT 24 102582605 ps
T84 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3913397123 Jun 13 12:35:21 PM PDT 24 Jun 13 12:35:26 PM PDT 24 580405635 ps
T101 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3356064311 Jun 13 12:35:53 PM PDT 24 Jun 13 12:35:58 PM PDT 24 67949735 ps
T112 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3370041414 Jun 13 12:35:31 PM PDT 24 Jun 13 12:35:35 PM PDT 24 396084691 ps
T546 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3730223956 Jun 13 12:35:24 PM PDT 24 Jun 13 12:35:26 PM PDT 24 181115966 ps
T547 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1132035865 Jun 13 12:36:10 PM PDT 24 Jun 13 12:36:15 PM PDT 24 212083771 ps
T102 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3133916089 Jun 13 12:35:23 PM PDT 24 Jun 13 12:35:25 PM PDT 24 133657908 ps
T114 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1105631033 Jun 13 12:35:22 PM PDT 24 Jun 13 12:35:26 PM PDT 24 904461060 ps
T548 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.579492682 Jun 13 12:35:30 PM PDT 24 Jun 13 12:35:32 PM PDT 24 197996608 ps
T549 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2252357789 Jun 13 12:35:26 PM PDT 24 Jun 13 12:35:28 PM PDT 24 130025337 ps
T550 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3936672141 Jun 13 12:35:33 PM PDT 24 Jun 13 12:35:39 PM PDT 24 68537338 ps
T103 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2492489444 Jun 13 12:35:35 PM PDT 24 Jun 13 12:35:39 PM PDT 24 124707006 ps
T104 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3846689549 Jun 13 12:35:52 PM PDT 24 Jun 13 12:35:57 PM PDT 24 88413515 ps
T551 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1105458065 Jun 13 12:35:22 PM PDT 24 Jun 13 12:35:29 PM PDT 24 479958541 ps
T105 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1597541985 Jun 13 12:35:23 PM PDT 24 Jun 13 12:35:25 PM PDT 24 151231330 ps
T552 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1302802447 Jun 13 12:35:34 PM PDT 24 Jun 13 12:35:38 PM PDT 24 97160213 ps
T113 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3235292005 Jun 13 12:35:54 PM PDT 24 Jun 13 12:35:59 PM PDT 24 140650340 ps
T553 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2130652897 Jun 13 12:35:34 PM PDT 24 Jun 13 12:35:39 PM PDT 24 213000157 ps
T554 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.4077551890 Jun 13 12:35:24 PM PDT 24 Jun 13 12:35:34 PM PDT 24 1981833940 ps
T555 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2859448906 Jun 13 12:35:34 PM PDT 24 Jun 13 12:35:41 PM PDT 24 528377279 ps
T556 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1527863 Jun 13 12:35:27 PM PDT 24 Jun 13 12:35:29 PM PDT 24 161154630 ps
T557 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2325234622 Jun 13 12:35:33 PM PDT 24 Jun 13 12:35:40 PM PDT 24 473116245 ps
T558 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2846612221 Jun 13 12:35:52 PM PDT 24 Jun 13 12:35:56 PM PDT 24 123413314 ps
T559 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.12005236 Jun 13 12:35:52 PM PDT 24 Jun 13 12:35:59 PM PDT 24 200483709 ps
T560 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.902643368 Jun 13 12:35:54 PM PDT 24 Jun 13 12:35:59 PM PDT 24 73115075 ps
T561 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2220272219 Jun 13 12:35:39 PM PDT 24 Jun 13 12:35:42 PM PDT 24 171868188 ps
T129 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1642789317 Jun 13 12:35:34 PM PDT 24 Jun 13 12:35:40 PM PDT 24 783165997 ps
T562 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4051252315 Jun 13 12:35:30 PM PDT 24 Jun 13 12:35:31 PM PDT 24 150789505 ps
T563 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1583310864 Jun 13 12:35:33 PM PDT 24 Jun 13 12:35:39 PM PDT 24 104531871 ps
T564 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3610446762 Jun 13 12:35:32 PM PDT 24 Jun 13 12:35:38 PM PDT 24 416821610 ps
T565 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3720099566 Jun 13 12:35:34 PM PDT 24 Jun 13 12:35:40 PM PDT 24 69993807 ps
T115 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.797767005 Jun 13 12:35:29 PM PDT 24 Jun 13 12:35:32 PM PDT 24 499575321 ps
T566 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2804315980 Jun 13 12:35:29 PM PDT 24 Jun 13 12:35:33 PM PDT 24 473024692 ps
T567 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.4290611199 Jun 13 12:35:32 PM PDT 24 Jun 13 12:35:38 PM PDT 24 73244851 ps
T568 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.423767503 Jun 13 12:35:29 PM PDT 24 Jun 13 12:35:31 PM PDT 24 110206813 ps
T569 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.114217449 Jun 13 12:35:35 PM PDT 24 Jun 13 12:35:40 PM PDT 24 128868907 ps
T570 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1738201620 Jun 13 12:35:35 PM PDT 24 Jun 13 12:35:39 PM PDT 24 131249218 ps
T571 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2665379841 Jun 13 12:35:38 PM PDT 24 Jun 13 12:35:44 PM PDT 24 206365157 ps
T572 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1094308830 Jun 13 12:35:22 PM PDT 24 Jun 13 12:35:24 PM PDT 24 140653648 ps
T110 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1516133710 Jun 13 12:35:25 PM PDT 24 Jun 13 12:35:29 PM PDT 24 949292820 ps
T573 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3748183156 Jun 13 12:35:25 PM PDT 24 Jun 13 12:35:27 PM PDT 24 103660287 ps
T574 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1775118706 Jun 13 12:35:58 PM PDT 24 Jun 13 12:36:04 PM PDT 24 133407177 ps
T575 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3472565087 Jun 13 12:35:24 PM PDT 24 Jun 13 12:35:26 PM PDT 24 112523814 ps
T87 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2451890243 Jun 13 12:35:25 PM PDT 24 Jun 13 12:35:27 PM PDT 24 139205538 ps
T576 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3263201095 Jun 13 12:35:31 PM PDT 24 Jun 13 12:35:33 PM PDT 24 237163797 ps
T577 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1397587210 Jun 13 12:35:21 PM PDT 24 Jun 13 12:35:23 PM PDT 24 214830656 ps
T578 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2928715966 Jun 13 12:35:24 PM PDT 24 Jun 13 12:35:27 PM PDT 24 234665592 ps
T579 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2103414241 Jun 13 12:35:22 PM PDT 24 Jun 13 12:35:24 PM PDT 24 72622511 ps
T580 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2081034900 Jun 13 12:35:31 PM PDT 24 Jun 13 12:35:33 PM PDT 24 71945838 ps
T581 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1699739887 Jun 13 12:35:34 PM PDT 24 Jun 13 12:35:39 PM PDT 24 83115756 ps
T582 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4122287868 Jun 13 12:35:20 PM PDT 24 Jun 13 12:35:22 PM PDT 24 149366143 ps
T583 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.57740356 Jun 13 12:35:27 PM PDT 24 Jun 13 12:35:29 PM PDT 24 421783460 ps
T584 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1703724994 Jun 13 12:35:32 PM PDT 24 Jun 13 12:35:37 PM PDT 24 64657857 ps
T585 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.975391456 Jun 13 12:35:33 PM PDT 24 Jun 13 12:35:38 PM PDT 24 66114451 ps
T586 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.220516161 Jun 13 12:35:33 PM PDT 24 Jun 13 12:35:39 PM PDT 24 202242227 ps
T587 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3063680613 Jun 13 12:35:25 PM PDT 24 Jun 13 12:35:29 PM PDT 24 193200705 ps
T588 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3644012996 Jun 13 12:35:23 PM PDT 24 Jun 13 12:35:25 PM PDT 24 58189773 ps
T589 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.400219683 Jun 13 12:35:25 PM PDT 24 Jun 13 12:35:41 PM PDT 24 267829775 ps
T107 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3493496343 Jun 13 12:35:31 PM PDT 24 Jun 13 12:35:33 PM PDT 24 487323353 ps
T590 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1177519707 Jun 13 12:35:33 PM PDT 24 Jun 13 12:35:39 PM PDT 24 433069552 ps
T591 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2511559324 Jun 13 12:35:33 PM PDT 24 Jun 13 12:35:40 PM PDT 24 852988021 ps
T592 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2980117308 Jun 13 12:35:34 PM PDT 24 Jun 13 12:35:39 PM PDT 24 145897396 ps
T593 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2832250356 Jun 13 12:35:22 PM PDT 24 Jun 13 12:35:24 PM PDT 24 116484899 ps
T594 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3859246518 Jun 13 12:35:20 PM PDT 24 Jun 13 12:35:23 PM PDT 24 158951969 ps
T595 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1690015002 Jun 13 12:35:34 PM PDT 24 Jun 13 12:35:38 PM PDT 24 78071576 ps
T596 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.4126365618 Jun 13 12:35:22 PM PDT 24 Jun 13 12:35:25 PM PDT 24 425833931 ps
T597 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3570360704 Jun 13 12:35:34 PM PDT 24 Jun 13 12:35:39 PM PDT 24 115316319 ps
T598 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.603076796 Jun 13 12:35:34 PM PDT 24 Jun 13 12:35:45 PM PDT 24 1012662383 ps
T599 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3941452909 Jun 13 12:35:54 PM PDT 24 Jun 13 12:36:00 PM PDT 24 180833719 ps
T600 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.425719899 Jun 13 12:35:20 PM PDT 24 Jun 13 12:35:22 PM PDT 24 134662675 ps
T128 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1308769932 Jun 13 12:35:24 PM PDT 24 Jun 13 12:35:28 PM PDT 24 762205063 ps
T601 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1324443371 Jun 13 12:35:25 PM PDT 24 Jun 13 12:35:27 PM PDT 24 177666672 ps
T602 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.431067280 Jun 13 12:35:31 PM PDT 24 Jun 13 12:35:33 PM PDT 24 106608729 ps
T603 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.336899551 Jun 13 12:35:37 PM PDT 24 Jun 13 12:35:41 PM PDT 24 87206592 ps
T604 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2560980712 Jun 13 12:35:32 PM PDT 24 Jun 13 12:35:37 PM PDT 24 73037283 ps
T605 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2410915360 Jun 13 12:35:24 PM PDT 24 Jun 13 12:35:26 PM PDT 24 100235446 ps
T606 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1043435051 Jun 13 12:35:19 PM PDT 24 Jun 13 12:35:21 PM PDT 24 66742570 ps
T607 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3722020906 Jun 13 12:35:37 PM PDT 24 Jun 13 12:35:45 PM PDT 24 1874092784 ps
T608 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3226256161 Jun 13 12:35:34 PM PDT 24 Jun 13 12:35:40 PM PDT 24 178663499 ps
T609 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.4054465651 Jun 13 12:35:28 PM PDT 24 Jun 13 12:35:29 PM PDT 24 76565750 ps
T610 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1517847727 Jun 13 12:35:23 PM PDT 24 Jun 13 12:35:25 PM PDT 24 72323305 ps
T611 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3578976520 Jun 13 12:35:21 PM PDT 24 Jun 13 12:35:23 PM PDT 24 146865912 ps
T612 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.929755285 Jun 13 12:35:23 PM PDT 24 Jun 13 12:35:27 PM PDT 24 351997258 ps
T108 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.35587443 Jun 13 12:35:30 PM PDT 24 Jun 13 12:35:32 PM PDT 24 507412616 ps
T613 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1424465427 Jun 13 12:35:33 PM PDT 24 Jun 13 12:35:39 PM PDT 24 122655003 ps
T614 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2416551676 Jun 13 12:35:33 PM PDT 24 Jun 13 12:35:38 PM PDT 24 55496505 ps
T615 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.714446705 Jun 13 12:35:32 PM PDT 24 Jun 13 12:35:35 PM PDT 24 173906117 ps
T616 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.960576646 Jun 13 12:35:51 PM PDT 24 Jun 13 12:35:55 PM PDT 24 94898744 ps
T617 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.142412641 Jun 13 12:35:29 PM PDT 24 Jun 13 12:35:30 PM PDT 24 74207284 ps
T109 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1554252617 Jun 13 12:35:38 PM PDT 24 Jun 13 12:35:43 PM PDT 24 451459965 ps
T618 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3881466078 Jun 13 12:35:43 PM PDT 24 Jun 13 12:35:45 PM PDT 24 90231658 ps
T619 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.380779560 Jun 13 12:35:58 PM PDT 24 Jun 13 12:36:04 PM PDT 24 511659449 ps
T111 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.286165648 Jun 13 12:36:10 PM PDT 24 Jun 13 12:36:15 PM PDT 24 499785851 ps
T620 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2543425311 Jun 13 12:35:36 PM PDT 24 Jun 13 12:35:39 PM PDT 24 66535873 ps

Test location /workspace/coverage/default/25.rstmgr_stress_all.3965126448
Short name T9
Test name
Test status
Simulation time 13464887973 ps
CPU time 45.61 seconds
Started Jun 13 12:36:10 PM PDT 24
Finished Jun 13 12:36:59 PM PDT 24
Peak memory 209104 kb
Host smart-4eb87af3-973a-46b6-9291-07ec07155ce0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965126448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3965126448
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3744584043
Short name T69
Test name
Test status
Simulation time 473774882 ps
CPU time 2.66 seconds
Started Jun 13 12:35:58 PM PDT 24
Finished Jun 13 12:36:05 PM PDT 24
Peak memory 200588 kb
Host smart-e8da0e68-3f04-4046-b196-d3d19ffdf6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744584043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3744584043
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1967328104
Short name T81
Test name
Test status
Simulation time 108527039 ps
CPU time 0.99 seconds
Started Jun 13 12:35:35 PM PDT 24
Finished Jun 13 12:35:39 PM PDT 24
Peak memory 200560 kb
Host smart-3b16522c-de0a-4e65-96ef-f133ef2b726e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967328104 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1967328104
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.3177410705
Short name T60
Test name
Test status
Simulation time 8292589139 ps
CPU time 12.82 seconds
Started Jun 13 12:35:43 PM PDT 24
Finished Jun 13 12:35:56 PM PDT 24
Peak memory 217592 kb
Host smart-a2838b40-e538-41b8-bc52-d1eaf4f31acb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177410705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3177410705
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.4033378197
Short name T33
Test name
Test status
Simulation time 1225877518 ps
CPU time 5.71 seconds
Started Jun 13 12:35:53 PM PDT 24
Finished Jun 13 12:36:03 PM PDT 24
Peak memory 217888 kb
Host smart-ebecab97-e8cb-4d9a-8ff6-8cb78a9efd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033378197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.4033378197
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3807380332
Short name T106
Test name
Test status
Simulation time 796777771 ps
CPU time 2.88 seconds
Started Jun 13 12:35:39 PM PDT 24
Finished Jun 13 12:35:44 PM PDT 24
Peak memory 200856 kb
Host smart-c1f8d20a-f833-4aff-b629-386a3d640823
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807380332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.3807380332
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3370041414
Short name T112
Test name
Test status
Simulation time 396084691 ps
CPU time 3.07 seconds
Started Jun 13 12:35:31 PM PDT 24
Finished Jun 13 12:35:35 PM PDT 24
Peak memory 212048 kb
Host smart-87023553-87d4-4d81-8f08-aee174201819
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370041414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3370041414
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.328173582
Short name T162
Test name
Test status
Simulation time 169371362 ps
CPU time 1.33 seconds
Started Jun 13 12:36:20 PM PDT 24
Finished Jun 13 12:36:24 PM PDT 24
Peak memory 200888 kb
Host smart-d2cf95b8-e236-41ac-ac51-9fa8089ab3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328173582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.328173582
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2860615212
Short name T135
Test name
Test status
Simulation time 141699370 ps
CPU time 1.15 seconds
Started Jun 13 12:35:56 PM PDT 24
Finished Jun 13 12:36:01 PM PDT 24
Peak memory 200704 kb
Host smart-14659f11-ca27-4188-9d75-59cdb8cfbae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860615212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2860615212
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1404730035
Short name T2
Test name
Test status
Simulation time 1220757105 ps
CPU time 5.68 seconds
Started Jun 13 12:36:30 PM PDT 24
Finished Jun 13 12:36:37 PM PDT 24
Peak memory 217984 kb
Host smart-f44b69bf-3897-4fe1-8871-b259b25120b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404730035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1404730035
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1279604167
Short name T152
Test name
Test status
Simulation time 66533717 ps
CPU time 0.8 seconds
Started Jun 13 12:36:05 PM PDT 24
Finished Jun 13 12:36:09 PM PDT 24
Peak memory 200492 kb
Host smart-644a5a95-034a-4eb4-ab51-1d946be7d8b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279604167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1279604167
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2371547294
Short name T80
Test name
Test status
Simulation time 414582040 ps
CPU time 2.58 seconds
Started Jun 13 12:35:39 PM PDT 24
Finished Jun 13 12:35:44 PM PDT 24
Peak memory 209000 kb
Host smart-96f178f8-5202-4dcc-a686-eaf8af406606
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371547294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2371547294
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.457943964
Short name T35
Test name
Test status
Simulation time 2345801780 ps
CPU time 8.19 seconds
Started Jun 13 12:36:11 PM PDT 24
Finished Jun 13 12:36:23 PM PDT 24
Peak memory 222388 kb
Host smart-9d71dd4d-edc5-4204-9c42-4de6bacbe809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457943964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.457943964
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3133916089
Short name T102
Test name
Test status
Simulation time 133657908 ps
CPU time 1.12 seconds
Started Jun 13 12:35:23 PM PDT 24
Finished Jun 13 12:35:25 PM PDT 24
Peak memory 200584 kb
Host smart-c83d0ea2-e329-4e0f-89df-61ff90b41ea0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133916089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3133916089
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3408973983
Short name T18
Test name
Test status
Simulation time 212871367 ps
CPU time 0.86 seconds
Started Jun 13 12:36:09 PM PDT 24
Finished Jun 13 12:36:12 PM PDT 24
Peak memory 200420 kb
Host smart-c141a9df-ed0a-4b64-a5f4-0112c972d9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408973983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3408973983
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1105631033
Short name T114
Test name
Test status
Simulation time 904461060 ps
CPU time 3.08 seconds
Started Jun 13 12:35:22 PM PDT 24
Finished Jun 13 12:35:26 PM PDT 24
Peak memory 200788 kb
Host smart-48c080f4-b8a2-45b8-aefe-9b2d48f50bf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105631033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1105631033
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1554252617
Short name T109
Test name
Test status
Simulation time 451459965 ps
CPU time 1.95 seconds
Started Jun 13 12:35:38 PM PDT 24
Finished Jun 13 12:35:43 PM PDT 24
Peak memory 200856 kb
Host smart-662e6af3-a415-45c9-ab27-13ec3823f73b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554252617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1554252617
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2454946016
Short name T78
Test name
Test status
Simulation time 1430825954 ps
CPU time 6.75 seconds
Started Jun 13 12:36:16 PM PDT 24
Finished Jun 13 12:36:27 PM PDT 24
Peak memory 209784 kb
Host smart-e8b915de-1505-4551-8ba0-fea6451bd151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454946016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2454946016
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3748183156
Short name T573
Test name
Test status
Simulation time 103660287 ps
CPU time 1.36 seconds
Started Jun 13 12:35:25 PM PDT 24
Finished Jun 13 12:35:27 PM PDT 24
Peak memory 200904 kb
Host smart-1ab42d17-8451-4112-ac54-7e30b4ca3cc7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748183156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3
748183156
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.4077551890
Short name T554
Test name
Test status
Simulation time 1981833940 ps
CPU time 9.6 seconds
Started Jun 13 12:35:24 PM PDT 24
Finished Jun 13 12:35:34 PM PDT 24
Peak memory 200860 kb
Host smart-f9b1eaae-8938-4659-abfa-35572e49f5d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077551890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.4
077551890
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1094308830
Short name T572
Test name
Test status
Simulation time 140653648 ps
CPU time 1 seconds
Started Jun 13 12:35:22 PM PDT 24
Finished Jun 13 12:35:24 PM PDT 24
Peak memory 200716 kb
Host smart-12335fbf-ecd4-40da-b988-05e1e39c9300
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094308830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
094308830
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1324443371
Short name T601
Test name
Test status
Simulation time 177666672 ps
CPU time 1.79 seconds
Started Jun 13 12:35:25 PM PDT 24
Finished Jun 13 12:35:27 PM PDT 24
Peak memory 209084 kb
Host smart-2082f2ae-7389-450e-af0b-b132e4ce98f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324443371 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1324443371
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2980950502
Short name T86
Test name
Test status
Simulation time 71705775 ps
CPU time 0.86 seconds
Started Jun 13 12:35:24 PM PDT 24
Finished Jun 13 12:35:26 PM PDT 24
Peak memory 200612 kb
Host smart-b539e32b-899b-47bc-8b5d-9d3c76489757
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980950502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2980950502
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3913397123
Short name T84
Test name
Test status
Simulation time 580405635 ps
CPU time 3.92 seconds
Started Jun 13 12:35:21 PM PDT 24
Finished Jun 13 12:35:26 PM PDT 24
Peak memory 208932 kb
Host smart-1a7520bf-f0d1-4dcc-bea7-981dc2d317d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913397123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3913397123
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3685828092
Short name T55
Test name
Test status
Simulation time 462527910 ps
CPU time 2.73 seconds
Started Jun 13 12:35:24 PM PDT 24
Finished Jun 13 12:35:28 PM PDT 24
Peak memory 200868 kb
Host smart-8847ca91-e2e1-4ce0-8b45-08b4f8a3bc6e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685828092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
685828092
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1105458065
Short name T551
Test name
Test status
Simulation time 479958541 ps
CPU time 5.8 seconds
Started Jun 13 12:35:22 PM PDT 24
Finished Jun 13 12:35:29 PM PDT 24
Peak memory 200800 kb
Host smart-da02f936-8f6a-4806-91ab-1dd99a73c3aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105458065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
105458065
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.425719899
Short name T600
Test name
Test status
Simulation time 134662675 ps
CPU time 0.98 seconds
Started Jun 13 12:35:20 PM PDT 24
Finished Jun 13 12:35:22 PM PDT 24
Peak memory 200632 kb
Host smart-87fccd7e-0e69-49a5-a229-0128d31dc96c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425719899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.425719899
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3730223956
Short name T546
Test name
Test status
Simulation time 181115966 ps
CPU time 1.2 seconds
Started Jun 13 12:35:24 PM PDT 24
Finished Jun 13 12:35:26 PM PDT 24
Peak memory 208796 kb
Host smart-f07251c0-8c7b-4d7e-8eb2-da1bad9dbb1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730223956 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3730223956
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2103414241
Short name T579
Test name
Test status
Simulation time 72622511 ps
CPU time 0.95 seconds
Started Jun 13 12:35:22 PM PDT 24
Finished Jun 13 12:35:24 PM PDT 24
Peak memory 200632 kb
Host smart-559e2dc5-0c2e-49b7-9002-bec88fe7e5c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103414241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2103414241
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1397587210
Short name T577
Test name
Test status
Simulation time 214830656 ps
CPU time 1.56 seconds
Started Jun 13 12:35:21 PM PDT 24
Finished Jun 13 12:35:23 PM PDT 24
Peak memory 200832 kb
Host smart-a588ea69-112c-4680-9b5a-f0793d18ab24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397587210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1397587210
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1429402486
Short name T57
Test name
Test status
Simulation time 297366010 ps
CPU time 2.3 seconds
Started Jun 13 12:35:22 PM PDT 24
Finished Jun 13 12:35:25 PM PDT 24
Peak memory 209024 kb
Host smart-64958e1f-bb00-4e85-bc8b-2ed804d5e5b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429402486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1429402486
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1516133710
Short name T110
Test name
Test status
Simulation time 949292820 ps
CPU time 3.24 seconds
Started Jun 13 12:35:25 PM PDT 24
Finished Jun 13 12:35:29 PM PDT 24
Peak memory 200760 kb
Host smart-0acd84f0-da71-4d48-8509-fc8d07c59f76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516133710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1516133710
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1008643928
Short name T65
Test name
Test status
Simulation time 121207163 ps
CPU time 1.29 seconds
Started Jun 13 12:35:30 PM PDT 24
Finished Jun 13 12:35:32 PM PDT 24
Peak memory 208896 kb
Host smart-701a656f-3844-4f4e-a814-58f00c7c5302
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008643928 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1008643928
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.4290611199
Short name T567
Test name
Test status
Simulation time 73244851 ps
CPU time 0.77 seconds
Started Jun 13 12:35:32 PM PDT 24
Finished Jun 13 12:35:38 PM PDT 24
Peak memory 200560 kb
Host smart-916c6a94-dcdc-4088-bde3-ad5a6235df8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290611199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.4290611199
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.431067280
Short name T602
Test name
Test status
Simulation time 106608729 ps
CPU time 1 seconds
Started Jun 13 12:35:31 PM PDT 24
Finished Jun 13 12:35:33 PM PDT 24
Peak memory 200572 kb
Host smart-17da45be-c995-4cf7-bb85-a62e4dd16897
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431067280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.431067280
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1642789317
Short name T129
Test name
Test status
Simulation time 783165997 ps
CPU time 2.68 seconds
Started Jun 13 12:35:34 PM PDT 24
Finished Jun 13 12:35:40 PM PDT 24
Peak memory 200892 kb
Host smart-af89a8bd-91c1-431c-a77a-4ede5810bd63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642789317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1642789317
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2252357789
Short name T549
Test name
Test status
Simulation time 130025337 ps
CPU time 1.13 seconds
Started Jun 13 12:35:26 PM PDT 24
Finished Jun 13 12:35:28 PM PDT 24
Peak memory 200656 kb
Host smart-5bf334c0-b19d-4c44-b4a4-aee27a92095d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252357789 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2252357789
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.902643368
Short name T560
Test name
Test status
Simulation time 73115075 ps
CPU time 0.78 seconds
Started Jun 13 12:35:54 PM PDT 24
Finished Jun 13 12:35:59 PM PDT 24
Peak memory 200676 kb
Host smart-796e67f8-ded8-4bd8-b248-ceeb2657a177
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902643368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.902643368
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1699739887
Short name T581
Test name
Test status
Simulation time 83115756 ps
CPU time 0.99 seconds
Started Jun 13 12:35:34 PM PDT 24
Finished Jun 13 12:35:39 PM PDT 24
Peak memory 200656 kb
Host smart-ed36dcfe-ab14-4f8a-b1c6-e8440d92f1c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699739887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1699739887
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3263201095
Short name T576
Test name
Test status
Simulation time 237163797 ps
CPU time 1.84 seconds
Started Jun 13 12:35:31 PM PDT 24
Finished Jun 13 12:35:33 PM PDT 24
Peak memory 217224 kb
Host smart-a9e11efd-de1c-4905-a68e-49cdf890d604
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263201095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3263201095
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2220272219
Short name T561
Test name
Test status
Simulation time 171868188 ps
CPU time 1.14 seconds
Started Jun 13 12:35:39 PM PDT 24
Finished Jun 13 12:35:42 PM PDT 24
Peak memory 208852 kb
Host smart-b7bc8c7b-c791-48bc-aa39-148c5076f21e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220272219 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2220272219
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1302802447
Short name T552
Test name
Test status
Simulation time 97160213 ps
CPU time 0.87 seconds
Started Jun 13 12:35:34 PM PDT 24
Finished Jun 13 12:35:38 PM PDT 24
Peak memory 200572 kb
Host smart-19154588-e9f3-4a27-a6c4-81a0de7bb23b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302802447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1302802447
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1790679333
Short name T99
Test name
Test status
Simulation time 153027860 ps
CPU time 1.17 seconds
Started Jun 13 12:35:35 PM PDT 24
Finished Jun 13 12:35:39 PM PDT 24
Peak memory 200608 kb
Host smart-d42fd14e-56bc-4324-8a77-b7752cfb68b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790679333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1790679333
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3063680613
Short name T587
Test name
Test status
Simulation time 193200705 ps
CPU time 3.26 seconds
Started Jun 13 12:35:25 PM PDT 24
Finished Jun 13 12:35:29 PM PDT 24
Peak memory 217128 kb
Host smart-4f868595-98e2-42c3-81c0-e6995236a633
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063680613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3063680613
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2511559324
Short name T591
Test name
Test status
Simulation time 852988021 ps
CPU time 2.79 seconds
Started Jun 13 12:35:33 PM PDT 24
Finished Jun 13 12:35:40 PM PDT 24
Peak memory 200844 kb
Host smart-fdecd0f3-f0af-4ff5-924b-03d784d1dffa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511559324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.2511559324
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.220516161
Short name T586
Test name
Test status
Simulation time 202242227 ps
CPU time 1.38 seconds
Started Jun 13 12:35:33 PM PDT 24
Finished Jun 13 12:35:39 PM PDT 24
Peak memory 208848 kb
Host smart-7af536fa-2a3e-4f51-96e1-0e6ea37d81fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220516161 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.220516161
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3936672141
Short name T550
Test name
Test status
Simulation time 68537338 ps
CPU time 0.81 seconds
Started Jun 13 12:35:33 PM PDT 24
Finished Jun 13 12:35:39 PM PDT 24
Peak memory 200216 kb
Host smart-d774ea4b-cd6d-427a-beac-4188c4ff4662
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936672141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3936672141
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.797894855
Short name T98
Test name
Test status
Simulation time 106482150 ps
CPU time 1.2 seconds
Started Jun 13 12:35:34 PM PDT 24
Finished Jun 13 12:35:39 PM PDT 24
Peak memory 200800 kb
Host smart-94ba5665-37d2-4654-b984-d38778adeb1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797894855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.797894855
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1583310864
Short name T563
Test name
Test status
Simulation time 104531871 ps
CPU time 1.42 seconds
Started Jun 13 12:35:33 PM PDT 24
Finished Jun 13 12:35:39 PM PDT 24
Peak memory 209000 kb
Host smart-ebe63b68-00f1-44b2-bff3-b325ca0f58c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583310864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1583310864
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.603076796
Short name T598
Test name
Test status
Simulation time 1012662383 ps
CPU time 3.12 seconds
Started Jun 13 12:35:34 PM PDT 24
Finished Jun 13 12:35:45 PM PDT 24
Peak memory 200832 kb
Host smart-26e4fb2c-fa67-4683-9187-e59a6443f4e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603076796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.603076796
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2980117308
Short name T592
Test name
Test status
Simulation time 145897396 ps
CPU time 1.26 seconds
Started Jun 13 12:35:34 PM PDT 24
Finished Jun 13 12:35:39 PM PDT 24
Peak memory 208552 kb
Host smart-3b4e4483-d170-4a14-8109-d164240b30b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980117308 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2980117308
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3720099566
Short name T565
Test name
Test status
Simulation time 69993807 ps
CPU time 0.77 seconds
Started Jun 13 12:35:34 PM PDT 24
Finished Jun 13 12:35:40 PM PDT 24
Peak memory 200580 kb
Host smart-4199c0a0-723f-4299-ae8f-06ddfcab798f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720099566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3720099566
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1738201620
Short name T570
Test name
Test status
Simulation time 131249218 ps
CPU time 1.13 seconds
Started Jun 13 12:35:35 PM PDT 24
Finished Jun 13 12:35:39 PM PDT 24
Peak memory 200656 kb
Host smart-00a4228f-da52-41b6-bf80-e9184fd321b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738201620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1738201620
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2130652897
Short name T553
Test name
Test status
Simulation time 213000157 ps
CPU time 1.6 seconds
Started Jun 13 12:35:34 PM PDT 24
Finished Jun 13 12:35:39 PM PDT 24
Peak memory 209000 kb
Host smart-038d2cf4-a0ec-45d8-9278-ea18eae216d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130652897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2130652897
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1306287547
Short name T52
Test name
Test status
Simulation time 507488395 ps
CPU time 1.91 seconds
Started Jun 13 12:35:35 PM PDT 24
Finished Jun 13 12:35:40 PM PDT 24
Peak memory 200888 kb
Host smart-b8ad2e1f-cd6f-4836-8ac4-a37275c10360
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306287547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1306287547
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1132035865
Short name T547
Test name
Test status
Simulation time 212083771 ps
CPU time 1.46 seconds
Started Jun 13 12:36:10 PM PDT 24
Finished Jun 13 12:36:15 PM PDT 24
Peak memory 208868 kb
Host smart-449af600-9592-4ffa-87b4-181e13dc53c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132035865 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1132035865
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.975391456
Short name T585
Test name
Test status
Simulation time 66114451 ps
CPU time 0.76 seconds
Started Jun 13 12:35:33 PM PDT 24
Finished Jun 13 12:35:38 PM PDT 24
Peak memory 200600 kb
Host smart-12dfc497-d79a-4b6c-824d-682587dd5546
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975391456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.975391456
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.960576646
Short name T616
Test name
Test status
Simulation time 94898744 ps
CPU time 1.19 seconds
Started Jun 13 12:35:51 PM PDT 24
Finished Jun 13 12:35:55 PM PDT 24
Peak memory 200792 kb
Host smart-97eb28b3-ce20-43c5-b47b-979a546ed686
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960576646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.960576646
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3610446762
Short name T564
Test name
Test status
Simulation time 416821610 ps
CPU time 2.95 seconds
Started Jun 13 12:35:32 PM PDT 24
Finished Jun 13 12:35:38 PM PDT 24
Peak memory 209112 kb
Host smart-6009bf54-a2e2-4ed3-b90d-03ad0425f43b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610446762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3610446762
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3235292005
Short name T113
Test name
Test status
Simulation time 140650340 ps
CPU time 1.12 seconds
Started Jun 13 12:35:54 PM PDT 24
Finished Jun 13 12:35:59 PM PDT 24
Peak memory 200828 kb
Host smart-6c20b377-7d4e-4281-853e-e47fbec849af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235292005 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3235292005
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.336899551
Short name T603
Test name
Test status
Simulation time 87206592 ps
CPU time 0.92 seconds
Started Jun 13 12:35:37 PM PDT 24
Finished Jun 13 12:35:41 PM PDT 24
Peak memory 200596 kb
Host smart-93c0071e-67bc-41b0-9720-6d3d8dfb7810
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336899551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.336899551
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2846612221
Short name T558
Test name
Test status
Simulation time 123413314 ps
CPU time 1.06 seconds
Started Jun 13 12:35:52 PM PDT 24
Finished Jun 13 12:35:56 PM PDT 24
Peak memory 200712 kb
Host smart-4295464a-26e1-4e9f-a7d9-9eb5d079909b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846612221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2846612221
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3226256161
Short name T608
Test name
Test status
Simulation time 178663499 ps
CPU time 2.55 seconds
Started Jun 13 12:35:34 PM PDT 24
Finished Jun 13 12:35:40 PM PDT 24
Peak memory 212160 kb
Host smart-e76d74a6-74ec-4317-ad71-9a6720ae3c39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226256161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3226256161
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.286165648
Short name T111
Test name
Test status
Simulation time 499785851 ps
CPU time 1.87 seconds
Started Jun 13 12:36:10 PM PDT 24
Finished Jun 13 12:36:15 PM PDT 24
Peak memory 200868 kb
Host smart-ce907e1c-8682-4486-b2a5-90aa9fb8ba14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286165648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err
.286165648
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3941452909
Short name T599
Test name
Test status
Simulation time 180833719 ps
CPU time 1.19 seconds
Started Jun 13 12:35:54 PM PDT 24
Finished Jun 13 12:36:00 PM PDT 24
Peak memory 200668 kb
Host smart-a4ac364a-a3f9-496f-8277-aed3bd89e428
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941452909 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3941452909
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3356064311
Short name T101
Test name
Test status
Simulation time 67949735 ps
CPU time 0.84 seconds
Started Jun 13 12:35:53 PM PDT 24
Finished Jun 13 12:35:58 PM PDT 24
Peak memory 200704 kb
Host smart-3af2258d-ae61-4c25-bb7e-c4f42f45d200
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356064311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3356064311
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3846689549
Short name T104
Test name
Test status
Simulation time 88413515 ps
CPU time 1.11 seconds
Started Jun 13 12:35:52 PM PDT 24
Finished Jun 13 12:35:57 PM PDT 24
Peak memory 200640 kb
Host smart-70fedb56-dd1d-429e-b87f-ca134d13e467
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846689549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.3846689549
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1775118706
Short name T574
Test name
Test status
Simulation time 133407177 ps
CPU time 1.73 seconds
Started Jun 13 12:35:58 PM PDT 24
Finished Jun 13 12:36:04 PM PDT 24
Peak memory 209060 kb
Host smart-025ab137-3fa7-4e57-8257-1e8f41126734
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775118706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1775118706
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.380779560
Short name T619
Test name
Test status
Simulation time 511659449 ps
CPU time 2.03 seconds
Started Jun 13 12:35:58 PM PDT 24
Finished Jun 13 12:36:04 PM PDT 24
Peak memory 200960 kb
Host smart-ac1810b1-7bb9-4f3e-bbf1-7eb71fd681de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380779560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.380779560
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1690015002
Short name T595
Test name
Test status
Simulation time 78071576 ps
CPU time 0.82 seconds
Started Jun 13 12:35:34 PM PDT 24
Finished Jun 13 12:35:38 PM PDT 24
Peak memory 200640 kb
Host smart-34f2a519-3218-4abb-81dc-45ce195b4f6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690015002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1690015002
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1075346281
Short name T97
Test name
Test status
Simulation time 123980969 ps
CPU time 1.11 seconds
Started Jun 13 12:35:44 PM PDT 24
Finished Jun 13 12:35:46 PM PDT 24
Peak memory 200656 kb
Host smart-bbf469e3-c2a3-4f35-9249-623d3d84273c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075346281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1075346281
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2665379841
Short name T571
Test name
Test status
Simulation time 206365157 ps
CPU time 3.33 seconds
Started Jun 13 12:35:38 PM PDT 24
Finished Jun 13 12:35:44 PM PDT 24
Peak memory 208972 kb
Host smart-8ce1f515-67ff-430c-bf78-6bcac265d1b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665379841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2665379841
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1177519707
Short name T590
Test name
Test status
Simulation time 433069552 ps
CPU time 1.76 seconds
Started Jun 13 12:35:33 PM PDT 24
Finished Jun 13 12:35:39 PM PDT 24
Peak memory 200868 kb
Host smart-e20a9128-1def-4c5d-8acf-4e187b3e73da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177519707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1177519707
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.12005236
Short name T559
Test name
Test status
Simulation time 200483709 ps
CPU time 1.36 seconds
Started Jun 13 12:35:52 PM PDT 24
Finished Jun 13 12:35:59 PM PDT 24
Peak memory 208888 kb
Host smart-79acfeef-75b8-49e2-ae03-4065a71df97b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12005236 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.12005236
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2543425311
Short name T620
Test name
Test status
Simulation time 66535873 ps
CPU time 0.78 seconds
Started Jun 13 12:35:36 PM PDT 24
Finished Jun 13 12:35:39 PM PDT 24
Peak memory 200676 kb
Host smart-489e55f2-6079-40d9-a7f1-27f235d81aff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543425311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2543425311
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.114217449
Short name T569
Test name
Test status
Simulation time 128868907 ps
CPU time 1.08 seconds
Started Jun 13 12:35:35 PM PDT 24
Finished Jun 13 12:35:40 PM PDT 24
Peak memory 200612 kb
Host smart-e161ce44-7557-4876-8def-2fad721d10a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114217449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.114217449
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1711091368
Short name T58
Test name
Test status
Simulation time 96771959 ps
CPU time 1.37 seconds
Started Jun 13 12:35:36 PM PDT 24
Finished Jun 13 12:35:40 PM PDT 24
Peak memory 208864 kb
Host smart-a0f7a464-178c-4411-953c-f80a84577613
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711091368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1711091368
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3722020906
Short name T607
Test name
Test status
Simulation time 1874092784 ps
CPU time 4.88 seconds
Started Jun 13 12:35:37 PM PDT 24
Finished Jun 13 12:35:45 PM PDT 24
Peak memory 200856 kb
Host smart-a3635285-60e5-4582-baf3-cd0676fa0722
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722020906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3722020906
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.929755285
Short name T612
Test name
Test status
Simulation time 351997258 ps
CPU time 2.28 seconds
Started Jun 13 12:35:23 PM PDT 24
Finished Jun 13 12:35:27 PM PDT 24
Peak memory 200808 kb
Host smart-1ca30903-5132-42f4-94cf-d76f8e59f3a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929755285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.929755285
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2979273954
Short name T54
Test name
Test status
Simulation time 479614209 ps
CPU time 5.81 seconds
Started Jun 13 12:35:23 PM PDT 24
Finished Jun 13 12:35:29 PM PDT 24
Peak memory 200900 kb
Host smart-1787f358-c95f-4e82-b6fa-e2d1d4840eb7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979273954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
979273954
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2451890243
Short name T87
Test name
Test status
Simulation time 139205538 ps
CPU time 0.95 seconds
Started Jun 13 12:35:25 PM PDT 24
Finished Jun 13 12:35:27 PM PDT 24
Peak memory 200716 kb
Host smart-7e9f0a8d-a055-47f9-8112-0d48ecc95e31
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451890243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
451890243
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2832250356
Short name T593
Test name
Test status
Simulation time 116484899 ps
CPU time 1.02 seconds
Started Jun 13 12:35:22 PM PDT 24
Finished Jun 13 12:35:24 PM PDT 24
Peak memory 200560 kb
Host smart-9510380a-00b7-4082-b716-f7ae72aaea75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832250356 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2832250356
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1043435051
Short name T606
Test name
Test status
Simulation time 66742570 ps
CPU time 0.79 seconds
Started Jun 13 12:35:19 PM PDT 24
Finished Jun 13 12:35:21 PM PDT 24
Peak memory 200532 kb
Host smart-3762a67e-7b5e-4459-b4c4-610a95df0c91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043435051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1043435051
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1597541985
Short name T105
Test name
Test status
Simulation time 151231330 ps
CPU time 1.28 seconds
Started Jun 13 12:35:23 PM PDT 24
Finished Jun 13 12:35:25 PM PDT 24
Peak memory 200636 kb
Host smart-245b393f-7573-4338-9264-9d15cf540ca0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597541985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1597541985
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3859246518
Short name T594
Test name
Test status
Simulation time 158951969 ps
CPU time 2.39 seconds
Started Jun 13 12:35:20 PM PDT 24
Finished Jun 13 12:35:23 PM PDT 24
Peak memory 200892 kb
Host smart-a07d8216-1fa5-44c8-b3ec-ebadadee5925
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859246518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3859246518
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.4126365618
Short name T596
Test name
Test status
Simulation time 425833931 ps
CPU time 1.81 seconds
Started Jun 13 12:35:22 PM PDT 24
Finished Jun 13 12:35:25 PM PDT 24
Peak memory 200792 kb
Host smart-88935a77-e392-48d9-a1e6-6712acd73950
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126365618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.4126365618
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2410915360
Short name T605
Test name
Test status
Simulation time 100235446 ps
CPU time 1.34 seconds
Started Jun 13 12:35:24 PM PDT 24
Finished Jun 13 12:35:26 PM PDT 24
Peak memory 200916 kb
Host smart-1d38c1e1-5b79-41c0-8fd5-b82fe8b03508
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410915360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.2
410915360
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3337084321
Short name T544
Test name
Test status
Simulation time 2287552318 ps
CPU time 9.45 seconds
Started Jun 13 12:35:27 PM PDT 24
Finished Jun 13 12:35:37 PM PDT 24
Peak memory 200952 kb
Host smart-9e04eb92-4a71-4fcc-86fd-e6070a7f6a58
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337084321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3
337084321
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4122287868
Short name T582
Test name
Test status
Simulation time 149366143 ps
CPU time 0.98 seconds
Started Jun 13 12:35:20 PM PDT 24
Finished Jun 13 12:35:22 PM PDT 24
Peak memory 200668 kb
Host smart-8aba7c36-b940-4323-85ec-f20c6864b822
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122287868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.4
122287868
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3472565087
Short name T575
Test name
Test status
Simulation time 112523814 ps
CPU time 1.03 seconds
Started Jun 13 12:35:24 PM PDT 24
Finished Jun 13 12:35:26 PM PDT 24
Peak memory 200868 kb
Host smart-3a799be7-75d0-4ac4-8959-e94be3706ad1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472565087 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3472565087
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3644012996
Short name T588
Test name
Test status
Simulation time 58189773 ps
CPU time 0.81 seconds
Started Jun 13 12:35:23 PM PDT 24
Finished Jun 13 12:35:25 PM PDT 24
Peak memory 200640 kb
Host smart-5e9f91d7-1e6e-4570-8c6e-59980fdcdd52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644012996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3644012996
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3578976520
Short name T611
Test name
Test status
Simulation time 146865912 ps
CPU time 1.21 seconds
Started Jun 13 12:35:21 PM PDT 24
Finished Jun 13 12:35:23 PM PDT 24
Peak memory 200588 kb
Host smart-3980e341-cc25-4a60-8681-ddc0ad99642d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578976520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3578976520
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3161617422
Short name T56
Test name
Test status
Simulation time 171902345 ps
CPU time 1.55 seconds
Started Jun 13 12:35:26 PM PDT 24
Finished Jun 13 12:35:28 PM PDT 24
Peak memory 208824 kb
Host smart-60254811-3e0e-4878-94e9-dbf2ad741a91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161617422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3161617422
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1826422299
Short name T64
Test name
Test status
Simulation time 487078594 ps
CPU time 2.1 seconds
Started Jun 13 12:35:26 PM PDT 24
Finished Jun 13 12:35:29 PM PDT 24
Peak memory 200796 kb
Host smart-8f20986d-a730-46fe-883a-f45d294a6978
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826422299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1826422299
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.423767503
Short name T568
Test name
Test status
Simulation time 110206813 ps
CPU time 1.31 seconds
Started Jun 13 12:35:29 PM PDT 24
Finished Jun 13 12:35:31 PM PDT 24
Peak memory 200888 kb
Host smart-4ca1b122-70c6-489a-a402-301b677af262
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423767503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.423767503
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.400219683
Short name T589
Test name
Test status
Simulation time 267829775 ps
CPU time 3.19 seconds
Started Jun 13 12:35:25 PM PDT 24
Finished Jun 13 12:35:41 PM PDT 24
Peak memory 200772 kb
Host smart-4217cde0-dbc6-40ee-bdc7-c82750cd029b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400219683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.400219683
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.301330445
Short name T545
Test name
Test status
Simulation time 98207957 ps
CPU time 0.86 seconds
Started Jun 13 12:35:23 PM PDT 24
Finished Jun 13 12:35:25 PM PDT 24
Peak memory 200592 kb
Host smart-7c291559-ae3c-45bd-a492-83156f32217f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301330445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.301330445
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3570360704
Short name T597
Test name
Test status
Simulation time 115316319 ps
CPU time 1.09 seconds
Started Jun 13 12:35:34 PM PDT 24
Finished Jun 13 12:35:39 PM PDT 24
Peak memory 216980 kb
Host smart-bc2ea39b-9139-4259-88a8-93df6630bdf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570360704 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.3570360704
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1517847727
Short name T610
Test name
Test status
Simulation time 72323305 ps
CPU time 0.81 seconds
Started Jun 13 12:35:23 PM PDT 24
Finished Jun 13 12:35:25 PM PDT 24
Peak memory 200572 kb
Host smart-e5e3757b-b328-403d-9695-3b7b26bf3b1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517847727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1517847727
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3881466078
Short name T618
Test name
Test status
Simulation time 90231658 ps
CPU time 1.12 seconds
Started Jun 13 12:35:43 PM PDT 24
Finished Jun 13 12:35:45 PM PDT 24
Peak memory 200780 kb
Host smart-090ed13d-a407-496c-a102-23c73e5c5f35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881466078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3881466078
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2928715966
Short name T578
Test name
Test status
Simulation time 234665592 ps
CPU time 1.9 seconds
Started Jun 13 12:35:24 PM PDT 24
Finished Jun 13 12:35:27 PM PDT 24
Peak memory 209060 kb
Host smart-ff933f3c-4a76-4187-a0ac-eb69cd5c3e4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928715966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2928715966
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1308769932
Short name T128
Test name
Test status
Simulation time 762205063 ps
CPU time 2.82 seconds
Started Jun 13 12:35:24 PM PDT 24
Finished Jun 13 12:35:28 PM PDT 24
Peak memory 200888 kb
Host smart-ce5dd1c2-7959-4ae8-b942-93e62fda2f86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308769932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1308769932
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1527863
Short name T556
Test name
Test status
Simulation time 161154630 ps
CPU time 1.67 seconds
Started Jun 13 12:35:27 PM PDT 24
Finished Jun 13 12:35:29 PM PDT 24
Peak memory 200704 kb
Host smart-16e18436-47b9-4e55-b787-01c104f7828e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527863 -assert nopostproc +UVM_TESTNAME=rs
tmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1527863
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2416551676
Short name T614
Test name
Test status
Simulation time 55496505 ps
CPU time 0.73 seconds
Started Jun 13 12:35:33 PM PDT 24
Finished Jun 13 12:35:38 PM PDT 24
Peak memory 200504 kb
Host smart-bcc7c22b-4892-40aa-be4c-eb7be5908d4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416551676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2416551676
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2492489444
Short name T103
Test name
Test status
Simulation time 124707006 ps
CPU time 1.11 seconds
Started Jun 13 12:35:35 PM PDT 24
Finished Jun 13 12:35:39 PM PDT 24
Peak memory 200636 kb
Host smart-b40b2d7b-b41e-4823-8c19-e17480f12ee0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492489444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.2492489444
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3493496343
Short name T107
Test name
Test status
Simulation time 487323353 ps
CPU time 1.94 seconds
Started Jun 13 12:35:31 PM PDT 24
Finished Jun 13 12:35:33 PM PDT 24
Peak memory 200780 kb
Host smart-2ba66cdf-6554-47ae-93fb-6e2981d4c4a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493496343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.3493496343
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1424465427
Short name T613
Test name
Test status
Simulation time 122655003 ps
CPU time 0.95 seconds
Started Jun 13 12:35:33 PM PDT 24
Finished Jun 13 12:35:39 PM PDT 24
Peak memory 200568 kb
Host smart-7ec35f93-2f38-4bcd-9d20-d5307c595b5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424465427 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1424465427
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1703724994
Short name T584
Test name
Test status
Simulation time 64657857 ps
CPU time 0.8 seconds
Started Jun 13 12:35:32 PM PDT 24
Finished Jun 13 12:35:37 PM PDT 24
Peak memory 200608 kb
Host smart-ce1b08ac-9ef1-4b2d-b27b-3b28bef9c913
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703724994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1703724994
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4051252315
Short name T562
Test name
Test status
Simulation time 150789505 ps
CPU time 1.16 seconds
Started Jun 13 12:35:30 PM PDT 24
Finished Jun 13 12:35:31 PM PDT 24
Peak memory 200636 kb
Host smart-c7986b3c-9584-4309-b13c-c6a7aa6d8399
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051252315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.4051252315
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3771245911
Short name T79
Test name
Test status
Simulation time 109321924 ps
CPU time 1.47 seconds
Started Jun 13 12:35:37 PM PDT 24
Finished Jun 13 12:35:42 PM PDT 24
Peak memory 211248 kb
Host smart-65bea471-961c-4f49-bef6-c43097256dbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771245911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3771245911
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.35587443
Short name T108
Test name
Test status
Simulation time 507412616 ps
CPU time 1.98 seconds
Started Jun 13 12:35:30 PM PDT 24
Finished Jun 13 12:35:32 PM PDT 24
Peak memory 200748 kb
Host smart-792cdbbc-e12a-40d5-b838-7c824fcd7dfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35587443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.35587443
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.758244897
Short name T82
Test name
Test status
Simulation time 106609679 ps
CPU time 1.09 seconds
Started Jun 13 12:35:32 PM PDT 24
Finished Jun 13 12:35:35 PM PDT 24
Peak memory 208868 kb
Host smart-904eaa18-3c62-4a03-b091-f90c63d823a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758244897 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.758244897
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2081034900
Short name T580
Test name
Test status
Simulation time 71945838 ps
CPU time 0.84 seconds
Started Jun 13 12:35:31 PM PDT 24
Finished Jun 13 12:35:33 PM PDT 24
Peak memory 200600 kb
Host smart-4fe005ac-d375-4f16-83f7-02feada65025
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081034900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2081034900
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.4054465651
Short name T609
Test name
Test status
Simulation time 76565750 ps
CPU time 0.96 seconds
Started Jun 13 12:35:28 PM PDT 24
Finished Jun 13 12:35:29 PM PDT 24
Peak memory 200612 kb
Host smart-30f9fdba-1fe9-4192-9283-81525e6bf667
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054465651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.4054465651
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.714446705
Short name T615
Test name
Test status
Simulation time 173906117 ps
CPU time 2.31 seconds
Started Jun 13 12:35:32 PM PDT 24
Finished Jun 13 12:35:35 PM PDT 24
Peak memory 216904 kb
Host smart-35659561-1c90-497a-94f8-9179c3698bb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714446705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.714446705
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.57740356
Short name T583
Test name
Test status
Simulation time 421783460 ps
CPU time 1.74 seconds
Started Jun 13 12:35:27 PM PDT 24
Finished Jun 13 12:35:29 PM PDT 24
Peak memory 200816 kb
Host smart-71bd3844-803b-45cc-9275-3a0b5f397624
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57740356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.57740356
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.4147170530
Short name T83
Test name
Test status
Simulation time 191414245 ps
CPU time 1.98 seconds
Started Jun 13 12:35:25 PM PDT 24
Finished Jun 13 12:35:28 PM PDT 24
Peak memory 209100 kb
Host smart-e94846e0-ad2a-459a-b9a6-33ae5a1eadef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147170530 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.4147170530
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1472477612
Short name T53
Test name
Test status
Simulation time 60152690 ps
CPU time 0.78 seconds
Started Jun 13 12:35:30 PM PDT 24
Finished Jun 13 12:35:31 PM PDT 24
Peak memory 200496 kb
Host smart-cd6ed98b-5d26-45ef-a057-1b0ca6d5d99c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472477612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1472477612
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.782073738
Short name T100
Test name
Test status
Simulation time 102582605 ps
CPU time 1.21 seconds
Started Jun 13 12:35:32 PM PDT 24
Finished Jun 13 12:35:36 PM PDT 24
Peak memory 200756 kb
Host smart-4caefc23-c090-46a8-b757-b7c7e2d095ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782073738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.782073738
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2859448906
Short name T555
Test name
Test status
Simulation time 528377279 ps
CPU time 3.46 seconds
Started Jun 13 12:35:34 PM PDT 24
Finished Jun 13 12:35:41 PM PDT 24
Peak memory 209144 kb
Host smart-c8f853d3-f666-40e1-9dff-40fb538f5b2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859448906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2859448906
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2325234622
Short name T557
Test name
Test status
Simulation time 473116245 ps
CPU time 1.96 seconds
Started Jun 13 12:35:33 PM PDT 24
Finished Jun 13 12:35:40 PM PDT 24
Peak memory 200768 kb
Host smart-0451147a-e879-42b5-8482-ce877fb52a5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325234622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.2325234622
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.579492682
Short name T548
Test name
Test status
Simulation time 197996608 ps
CPU time 1.35 seconds
Started Jun 13 12:35:30 PM PDT 24
Finished Jun 13 12:35:32 PM PDT 24
Peak memory 208840 kb
Host smart-f6a259c1-1d36-4d08-9fb3-9c1325c679be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579492682 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.579492682
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.142412641
Short name T617
Test name
Test status
Simulation time 74207284 ps
CPU time 0.87 seconds
Started Jun 13 12:35:29 PM PDT 24
Finished Jun 13 12:35:30 PM PDT 24
Peak memory 200644 kb
Host smart-293cd32a-8063-44e6-8a67-62f9e77f4948
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142412641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.142412641
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2560980712
Short name T604
Test name
Test status
Simulation time 73037283 ps
CPU time 0.94 seconds
Started Jun 13 12:35:32 PM PDT 24
Finished Jun 13 12:35:37 PM PDT 24
Peak memory 200596 kb
Host smart-64bb3d0d-538e-47a0-a682-c53736a3a466
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560980712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.2560980712
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2804315980
Short name T566
Test name
Test status
Simulation time 473024692 ps
CPU time 3.38 seconds
Started Jun 13 12:35:29 PM PDT 24
Finished Jun 13 12:35:33 PM PDT 24
Peak memory 209056 kb
Host smart-3175c371-fd02-469f-9f25-0203dd0b4ea1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804315980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2804315980
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.797767005
Short name T115
Test name
Test status
Simulation time 499575321 ps
CPU time 2.07 seconds
Started Jun 13 12:35:29 PM PDT 24
Finished Jun 13 12:35:32 PM PDT 24
Peak memory 200832 kb
Host smart-d82ef4b6-d5e0-41e1-ad77-f6fa37e702dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797767005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
797767005
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2019198714
Short name T220
Test name
Test status
Simulation time 73123219 ps
CPU time 0.79 seconds
Started Jun 13 12:35:55 PM PDT 24
Finished Jun 13 12:36:01 PM PDT 24
Peak memory 200484 kb
Host smart-85674670-a59e-4411-8e9a-f89fc4446c2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019198714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2019198714
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.166687594
Short name T262
Test name
Test status
Simulation time 2189386637 ps
CPU time 8.39 seconds
Started Jun 13 12:36:08 PM PDT 24
Finished Jun 13 12:36:19 PM PDT 24
Peak memory 218440 kb
Host smart-a8ce05df-8298-4301-8b0e-6a79aa56d2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166687594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.166687594
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3943789846
Short name T272
Test name
Test status
Simulation time 244192732 ps
CPU time 1.06 seconds
Started Jun 13 12:35:59 PM PDT 24
Finished Jun 13 12:36:04 PM PDT 24
Peak memory 218068 kb
Host smart-32fba8da-0cb5-475c-97de-9c303eb12a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943789846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3943789846
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3974144342
Short name T199
Test name
Test status
Simulation time 128190352 ps
CPU time 0.9 seconds
Started Jun 13 12:35:41 PM PDT 24
Finished Jun 13 12:35:43 PM PDT 24
Peak memory 200432 kb
Host smart-dd1cff8f-f2bb-4770-9376-d632d0ce6033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974144342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3974144342
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3703817474
Short name T428
Test name
Test status
Simulation time 1948747924 ps
CPU time 8.01 seconds
Started Jun 13 12:35:43 PM PDT 24
Finished Jun 13 12:35:51 PM PDT 24
Peak memory 200812 kb
Host smart-b62c557d-bd8b-4686-b53e-960c7581d3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703817474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3703817474
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2373836155
Short name T398
Test name
Test status
Simulation time 155529603 ps
CPU time 1.07 seconds
Started Jun 13 12:36:09 PM PDT 24
Finished Jun 13 12:36:12 PM PDT 24
Peak memory 200696 kb
Host smart-2f0d0a89-ccf9-4909-bd2e-75a5c9ffe903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373836155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2373836155
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1667169847
Short name T402
Test name
Test status
Simulation time 116815098 ps
CPU time 1.25 seconds
Started Jun 13 12:35:38 PM PDT 24
Finished Jun 13 12:35:42 PM PDT 24
Peak memory 200764 kb
Host smart-654fecd2-5f36-407a-85f8-8f35db48120e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667169847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1667169847
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3514154555
Short name T93
Test name
Test status
Simulation time 4395861710 ps
CPU time 14.95 seconds
Started Jun 13 12:35:54 PM PDT 24
Finished Jun 13 12:36:13 PM PDT 24
Peak memory 209032 kb
Host smart-3a60f4fb-29a5-465c-b718-144468ec13a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514154555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3514154555
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3416988623
Short name T267
Test name
Test status
Simulation time 354940618 ps
CPU time 1.95 seconds
Started Jun 13 12:35:49 PM PDT 24
Finished Jun 13 12:35:54 PM PDT 24
Peak memory 200424 kb
Host smart-87ce41ac-bb7e-473c-93d4-dc096c94e15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416988623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3416988623
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.146441087
Short name T454
Test name
Test status
Simulation time 59954068 ps
CPU time 0.71 seconds
Started Jun 13 12:35:56 PM PDT 24
Finished Jun 13 12:36:01 PM PDT 24
Peak memory 200588 kb
Host smart-687bfeb1-01ce-4c3b-b3bf-08dde5af53b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146441087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.146441087
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2325469919
Short name T471
Test name
Test status
Simulation time 65614629 ps
CPU time 0.73 seconds
Started Jun 13 12:35:52 PM PDT 24
Finished Jun 13 12:35:58 PM PDT 24
Peak memory 200436 kb
Host smart-a76d3975-81ca-47b5-9847-e22feee80ab2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325469919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2325469919
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3206806386
Short name T450
Test name
Test status
Simulation time 1876543023 ps
CPU time 6.88 seconds
Started Jun 13 12:35:50 PM PDT 24
Finished Jun 13 12:35:59 PM PDT 24
Peak memory 218388 kb
Host smart-61a52dff-feb4-4ed2-bb18-97a4a5268215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206806386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3206806386
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.4090272936
Short name T138
Test name
Test status
Simulation time 245833556 ps
CPU time 1.03 seconds
Started Jun 13 12:35:46 PM PDT 24
Finished Jun 13 12:35:48 PM PDT 24
Peak memory 218096 kb
Host smart-15a25fbf-ba21-4c62-ba31-0485ad805893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090272936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.4090272936
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.570299962
Short name T441
Test name
Test status
Simulation time 114159515 ps
CPU time 0.83 seconds
Started Jun 13 12:35:53 PM PDT 24
Finished Jun 13 12:35:58 PM PDT 24
Peak memory 200396 kb
Host smart-6c4f491d-d7b8-428e-8b4a-dfc673a7b184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570299962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.570299962
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.4076382606
Short name T335
Test name
Test status
Simulation time 1476167087 ps
CPU time 5.68 seconds
Started Jun 13 12:36:10 PM PDT 24
Finished Jun 13 12:36:19 PM PDT 24
Peak memory 200868 kb
Host smart-af37d6cf-dc6d-4db8-8406-c128acc66e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076382606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.4076382606
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.694246903
Short name T61
Test name
Test status
Simulation time 12223511188 ps
CPU time 19.49 seconds
Started Jun 13 12:35:53 PM PDT 24
Finished Jun 13 12:36:17 PM PDT 24
Peak memory 217416 kb
Host smart-ec402c77-8a17-4fbc-941b-91e695d2f251
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694246903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.694246903
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3663620092
Short name T351
Test name
Test status
Simulation time 148333155 ps
CPU time 1.13 seconds
Started Jun 13 12:35:49 PM PDT 24
Finished Jun 13 12:35:53 PM PDT 24
Peak memory 200600 kb
Host smart-28ca71c5-a664-4b0c-94f4-0f4926f3985c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663620092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3663620092
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.2664410309
Short name T256
Test name
Test status
Simulation time 110822745 ps
CPU time 1.16 seconds
Started Jun 13 12:35:55 PM PDT 24
Finished Jun 13 12:36:01 PM PDT 24
Peak memory 200788 kb
Host smart-3a592636-9d2d-4477-aba6-9652bfd74241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664410309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2664410309
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.726770894
Short name T520
Test name
Test status
Simulation time 3128434083 ps
CPU time 13.11 seconds
Started Jun 13 12:35:50 PM PDT 24
Finished Jun 13 12:36:07 PM PDT 24
Peak memory 210552 kb
Host smart-300b16db-afd7-4e86-a084-8b54ecf0ecf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726770894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.726770894
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.1837709820
Short name T528
Test name
Test status
Simulation time 129957971 ps
CPU time 1.64 seconds
Started Jun 13 12:35:51 PM PDT 24
Finished Jun 13 12:35:56 PM PDT 24
Peak memory 208820 kb
Host smart-fd360c74-84fb-420c-b5f0-c4a8fd928399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837709820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1837709820
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3549964577
Short name T326
Test name
Test status
Simulation time 221073016 ps
CPU time 1.46 seconds
Started Jun 13 12:35:56 PM PDT 24
Finished Jun 13 12:36:02 PM PDT 24
Peak memory 200616 kb
Host smart-8bdbff24-44a8-4813-b1e4-ea1df2b934ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549964577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3549964577
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.423062832
Short name T415
Test name
Test status
Simulation time 1892828362 ps
CPU time 7.13 seconds
Started Jun 13 12:35:59 PM PDT 24
Finished Jun 13 12:36:11 PM PDT 24
Peak memory 221884 kb
Host smart-4b372e64-4d22-4e6c-9245-4fcde5ec03bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423062832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.423062832
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2575555213
Short name T526
Test name
Test status
Simulation time 244278114 ps
CPU time 1.14 seconds
Started Jun 13 12:36:12 PM PDT 24
Finished Jun 13 12:36:17 PM PDT 24
Peak memory 218080 kb
Host smart-b8340a4e-da75-431f-abcf-2fc7ebd03583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575555213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2575555213
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2105630598
Short name T438
Test name
Test status
Simulation time 117950236 ps
CPU time 0.83 seconds
Started Jun 13 12:36:00 PM PDT 24
Finished Jun 13 12:36:05 PM PDT 24
Peak memory 200500 kb
Host smart-f7be50cc-7ff9-4d9e-ac20-673c08610f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105630598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2105630598
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3165639074
Short name T118
Test name
Test status
Simulation time 2042846546 ps
CPU time 7.43 seconds
Started Jun 13 12:36:05 PM PDT 24
Finished Jun 13 12:36:20 PM PDT 24
Peak memory 200748 kb
Host smart-3b7a03c4-f098-4457-a38a-b0954985c07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165639074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3165639074
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2281837949
Short name T297
Test name
Test status
Simulation time 159318854 ps
CPU time 1.13 seconds
Started Jun 13 12:35:58 PM PDT 24
Finished Jun 13 12:36:03 PM PDT 24
Peak memory 200580 kb
Host smart-508f3933-111a-4d0f-ae7b-51e78ed17ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281837949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2281837949
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.3201528920
Short name T194
Test name
Test status
Simulation time 200076959 ps
CPU time 1.26 seconds
Started Jun 13 12:36:07 PM PDT 24
Finished Jun 13 12:36:16 PM PDT 24
Peak memory 200808 kb
Host smart-d7ef6fc2-b732-4679-9c02-2dd87998c8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201528920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3201528920
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3753493568
Short name T379
Test name
Test status
Simulation time 363324398 ps
CPU time 1.99 seconds
Started Jun 13 12:35:52 PM PDT 24
Finished Jun 13 12:35:57 PM PDT 24
Peak memory 200792 kb
Host smart-b4032bba-5e67-41a5-b205-dbf723061fad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753493568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3753493568
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.885968882
Short name T122
Test name
Test status
Simulation time 413951052 ps
CPU time 2.39 seconds
Started Jun 13 12:36:14 PM PDT 24
Finished Jun 13 12:36:20 PM PDT 24
Peak memory 200648 kb
Host smart-a0955918-94bb-46ab-880d-8f120df86427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885968882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.885968882
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.505213603
Short name T532
Test name
Test status
Simulation time 148818661 ps
CPU time 1.27 seconds
Started Jun 13 12:36:04 PM PDT 24
Finished Jun 13 12:36:08 PM PDT 24
Peak memory 200652 kb
Host smart-8b9d75d4-2569-40eb-af08-4016bc2636e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505213603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.505213603
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.625839397
Short name T166
Test name
Test status
Simulation time 73563935 ps
CPU time 0.78 seconds
Started Jun 13 12:35:54 PM PDT 24
Finished Jun 13 12:36:00 PM PDT 24
Peak memory 200424 kb
Host smart-acab9275-4e33-4d98-8a5a-b6b96538574d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625839397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.625839397
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1589712326
Short name T284
Test name
Test status
Simulation time 2380175600 ps
CPU time 8.47 seconds
Started Jun 13 12:35:55 PM PDT 24
Finished Jun 13 12:36:08 PM PDT 24
Peak memory 221856 kb
Host smart-fb664c14-fd89-4792-907a-e708e02cbc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589712326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1589712326
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2260369491
Short name T208
Test name
Test status
Simulation time 243279831 ps
CPU time 1.14 seconds
Started Jun 13 12:35:53 PM PDT 24
Finished Jun 13 12:35:59 PM PDT 24
Peak memory 218096 kb
Host smart-9373b3e9-8f2e-4aea-bbc8-893779948ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260369491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.2260369491
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1656130216
Short name T167
Test name
Test status
Simulation time 174410610 ps
CPU time 0.87 seconds
Started Jun 13 12:36:12 PM PDT 24
Finished Jun 13 12:36:17 PM PDT 24
Peak memory 200404 kb
Host smart-6bb245e6-c2e3-463d-926a-2fc43fc05b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656130216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1656130216
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.69109944
Short name T527
Test name
Test status
Simulation time 1662922719 ps
CPU time 6.67 seconds
Started Jun 13 12:36:00 PM PDT 24
Finished Jun 13 12:36:11 PM PDT 24
Peak memory 200756 kb
Host smart-465c4a77-028e-4a53-b640-fd21b7a95454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69109944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.69109944
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3778633353
Short name T295
Test name
Test status
Simulation time 193907596 ps
CPU time 1.39 seconds
Started Jun 13 12:35:59 PM PDT 24
Finished Jun 13 12:36:05 PM PDT 24
Peak memory 200812 kb
Host smart-a88e8757-e1ca-404c-bea9-31941fcdd396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778633353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3778633353
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.977498812
Short name T281
Test name
Test status
Simulation time 318988680 ps
CPU time 1.55 seconds
Started Jun 13 12:35:59 PM PDT 24
Finished Jun 13 12:36:06 PM PDT 24
Peak memory 200748 kb
Host smart-f37b3c0d-d337-4b69-9f00-b9f7853b209c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977498812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.977498812
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.698261079
Short name T382
Test name
Test status
Simulation time 259156026 ps
CPU time 1.83 seconds
Started Jun 13 12:35:59 PM PDT 24
Finished Jun 13 12:36:09 PM PDT 24
Peak memory 200580 kb
Host smart-7ea49af3-6c84-4d64-911d-96911dedf1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698261079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.698261079
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.910759747
Short name T432
Test name
Test status
Simulation time 112406018 ps
CPU time 0.99 seconds
Started Jun 13 12:36:06 PM PDT 24
Finished Jun 13 12:36:10 PM PDT 24
Peak memory 200624 kb
Host smart-ecc31bba-6f86-47b3-b64a-364b5335d64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910759747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.910759747
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1686738994
Short name T175
Test name
Test status
Simulation time 86698570 ps
CPU time 0.79 seconds
Started Jun 13 12:36:09 PM PDT 24
Finished Jun 13 12:36:12 PM PDT 24
Peak memory 200392 kb
Host smart-5c1bf1f5-57ec-4c45-b402-91e27212f37b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686738994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1686738994
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.1732749639
Short name T346
Test name
Test status
Simulation time 1217630704 ps
CPU time 5.58 seconds
Started Jun 13 12:36:05 PM PDT 24
Finished Jun 13 12:36:14 PM PDT 24
Peak memory 222308 kb
Host smart-c25f115e-77ba-4fd5-b7a8-07ebc473fb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732749639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1732749639
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3532840550
Short name T465
Test name
Test status
Simulation time 244663827 ps
CPU time 1.06 seconds
Started Jun 13 12:35:59 PM PDT 24
Finished Jun 13 12:36:04 PM PDT 24
Peak memory 218104 kb
Host smart-f202d551-8b0c-43de-961e-531d513d458f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532840550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3532840550
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2128527809
Short name T507
Test name
Test status
Simulation time 186329837 ps
CPU time 0.86 seconds
Started Jun 13 12:36:05 PM PDT 24
Finished Jun 13 12:36:09 PM PDT 24
Peak memory 200372 kb
Host smart-383fe8fd-b1d8-4280-ad8c-28054946bc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128527809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2128527809
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.868090680
Short name T8
Test name
Test status
Simulation time 997615204 ps
CPU time 4.84 seconds
Started Jun 13 12:36:12 PM PDT 24
Finished Jun 13 12:36:21 PM PDT 24
Peak memory 200768 kb
Host smart-bd11d17d-92b9-40c4-825a-bd40dbafd0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868090680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.868090680
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2211153879
Short name T315
Test name
Test status
Simulation time 171904556 ps
CPU time 1.17 seconds
Started Jun 13 12:36:18 PM PDT 24
Finished Jun 13 12:36:23 PM PDT 24
Peak memory 200660 kb
Host smart-81c48632-a257-4f11-be3f-24a7a6e1ee57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211153879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2211153879
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2247932982
Short name T13
Test name
Test status
Simulation time 110331149 ps
CPU time 1.17 seconds
Started Jun 13 12:36:24 PM PDT 24
Finished Jun 13 12:36:28 PM PDT 24
Peak memory 200844 kb
Host smart-a8e1dcc3-b2e9-418c-808d-48b80ef74349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247932982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2247932982
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1386113111
Short name T204
Test name
Test status
Simulation time 136833125 ps
CPU time 1.69 seconds
Started Jun 13 12:36:20 PM PDT 24
Finished Jun 13 12:36:25 PM PDT 24
Peak memory 200684 kb
Host smart-4b3ad9d8-cc95-4a59-af68-1cb3d7b00e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386113111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1386113111
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.1167179105
Short name T475
Test name
Test status
Simulation time 86662387 ps
CPU time 0.96 seconds
Started Jun 13 12:36:00 PM PDT 24
Finished Jun 13 12:36:05 PM PDT 24
Peak memory 200604 kb
Host smart-0bbd96b7-1beb-41d5-b141-a240d8aa592a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167179105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1167179105
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2844526591
Short name T286
Test name
Test status
Simulation time 59823152 ps
CPU time 0.78 seconds
Started Jun 13 12:36:01 PM PDT 24
Finished Jun 13 12:36:06 PM PDT 24
Peak memory 200436 kb
Host smart-ddff2833-8cb0-4fd8-88f1-862249339ea3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844526591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2844526591
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1118018817
Short name T217
Test name
Test status
Simulation time 246000613 ps
CPU time 1.14 seconds
Started Jun 13 12:36:12 PM PDT 24
Finished Jun 13 12:36:17 PM PDT 24
Peak memory 218100 kb
Host smart-5c3ed6fc-f950-4a97-9ae0-a30f2372f756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118018817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1118018817
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1439469408
Short name T515
Test name
Test status
Simulation time 148815483 ps
CPU time 0.93 seconds
Started Jun 13 12:36:05 PM PDT 24
Finished Jun 13 12:36:10 PM PDT 24
Peak memory 200416 kb
Host smart-55e51860-8a58-4e43-8592-268f8b2bea10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439469408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1439469408
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2667840182
Short name T117
Test name
Test status
Simulation time 1590378995 ps
CPU time 5.85 seconds
Started Jun 13 12:36:05 PM PDT 24
Finished Jun 13 12:36:19 PM PDT 24
Peak memory 200832 kb
Host smart-bfe04f18-dc86-4873-bb4f-6c383ae8e882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667840182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2667840182
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2407241690
Short name T427
Test name
Test status
Simulation time 113034184 ps
CPU time 1.02 seconds
Started Jun 13 12:36:07 PM PDT 24
Finished Jun 13 12:36:11 PM PDT 24
Peak memory 200604 kb
Host smart-01bb0f34-4e09-40fe-953f-fe5a95d48ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407241690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2407241690
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3810594817
Short name T413
Test name
Test status
Simulation time 118986722 ps
CPU time 1.16 seconds
Started Jun 13 12:36:26 PM PDT 24
Finished Jun 13 12:36:30 PM PDT 24
Peak memory 200884 kb
Host smart-aba1f4f1-5d73-45c6-a815-066a74ee2beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810594817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3810594817
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1796500809
Short name T88
Test name
Test status
Simulation time 2195634930 ps
CPU time 8.1 seconds
Started Jun 13 12:36:24 PM PDT 24
Finished Jun 13 12:36:35 PM PDT 24
Peak memory 200876 kb
Host smart-0042e45f-bdee-426b-a26a-f8a983b82ae3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796500809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1796500809
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.836398209
Short name T145
Test name
Test status
Simulation time 146990014 ps
CPU time 1.84 seconds
Started Jun 13 12:35:55 PM PDT 24
Finished Jun 13 12:36:01 PM PDT 24
Peak memory 200580 kb
Host smart-c9e123ca-448c-473c-b692-f2af7b8df14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836398209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.836398209
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1599674106
Short name T522
Test name
Test status
Simulation time 167575003 ps
CPU time 1.33 seconds
Started Jun 13 12:36:06 PM PDT 24
Finished Jun 13 12:36:16 PM PDT 24
Peak memory 200800 kb
Host smart-f9ae37cb-92a1-472f-820e-c9a73bdd8068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599674106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1599674106
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.1777590928
Short name T62
Test name
Test status
Simulation time 56484244 ps
CPU time 0.74 seconds
Started Jun 13 12:36:18 PM PDT 24
Finished Jun 13 12:36:22 PM PDT 24
Peak memory 200496 kb
Host smart-01aa54fc-b59d-4100-9b86-021b8a00efd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777590928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1777590928
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1856997727
Short name T39
Test name
Test status
Simulation time 1225699491 ps
CPU time 5.4 seconds
Started Jun 13 12:35:52 PM PDT 24
Finished Jun 13 12:36:00 PM PDT 24
Peak memory 218384 kb
Host smart-81f4b9ab-58e1-46ac-bf9b-e17097e69366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856997727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1856997727
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.461622101
Short name T169
Test name
Test status
Simulation time 244248115 ps
CPU time 1.1 seconds
Started Jun 13 12:36:14 PM PDT 24
Finished Jun 13 12:36:19 PM PDT 24
Peak memory 218072 kb
Host smart-bc86aeae-f822-4b0e-a64d-b952359c891f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461622101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.461622101
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.4286094520
Short name T486
Test name
Test status
Simulation time 122205763 ps
CPU time 0.78 seconds
Started Jun 13 12:36:14 PM PDT 24
Finished Jun 13 12:36:18 PM PDT 24
Peak memory 200408 kb
Host smart-89382fb8-495a-4630-8fac-f0a850040d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286094520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.4286094520
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.568525523
Short name T181
Test name
Test status
Simulation time 1533800746 ps
CPU time 6.18 seconds
Started Jun 13 12:35:56 PM PDT 24
Finished Jun 13 12:36:07 PM PDT 24
Peak memory 200796 kb
Host smart-186fb9cc-4ff7-4a4b-b609-9f5dbf672ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568525523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.568525523
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1564464277
Short name T362
Test name
Test status
Simulation time 107647025 ps
CPU time 1.04 seconds
Started Jun 13 12:36:04 PM PDT 24
Finished Jun 13 12:36:08 PM PDT 24
Peak memory 200688 kb
Host smart-0a5441a3-362e-44c6-8e5f-813917d87b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564464277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1564464277
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3352657226
Short name T278
Test name
Test status
Simulation time 112246408 ps
CPU time 1.13 seconds
Started Jun 13 12:36:14 PM PDT 24
Finished Jun 13 12:36:19 PM PDT 24
Peak memory 200872 kb
Host smart-ddd1e859-66ea-436e-873a-ba7fd6b6542f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352657226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3352657226
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.66415899
Short name T303
Test name
Test status
Simulation time 3951696126 ps
CPU time 12.85 seconds
Started Jun 13 12:36:09 PM PDT 24
Finished Jun 13 12:36:24 PM PDT 24
Peak memory 210796 kb
Host smart-ea4a629d-4d25-43cc-8585-158865ee2873
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66415899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.66415899
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3698848696
Short name T377
Test name
Test status
Simulation time 272787663 ps
CPU time 1.83 seconds
Started Jun 13 12:35:57 PM PDT 24
Finished Jun 13 12:36:03 PM PDT 24
Peak memory 199828 kb
Host smart-ed34ea03-9b7d-4704-8845-b1ac79c387dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698848696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3698848696
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.449450348
Short name T75
Test name
Test status
Simulation time 229692199 ps
CPU time 1.48 seconds
Started Jun 13 12:36:08 PM PDT 24
Finished Jun 13 12:36:12 PM PDT 24
Peak memory 200648 kb
Host smart-097bed91-ba1b-4854-b84d-4c65cbf91f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449450348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.449450348
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2270129469
Short name T495
Test name
Test status
Simulation time 68910740 ps
CPU time 0.85 seconds
Started Jun 13 12:36:05 PM PDT 24
Finished Jun 13 12:36:09 PM PDT 24
Peak memory 200432 kb
Host smart-9c508833-59b9-4ad0-85b9-cde3f685fa7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270129469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2270129469
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1098289501
Short name T37
Test name
Test status
Simulation time 1873091777 ps
CPU time 7.06 seconds
Started Jun 13 12:36:14 PM PDT 24
Finished Jun 13 12:36:25 PM PDT 24
Peak memory 218388 kb
Host smart-a53e8565-4e13-4dd2-8531-49504a2a69c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098289501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1098289501
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3785931529
Short name T481
Test name
Test status
Simulation time 244119366 ps
CPU time 1.03 seconds
Started Jun 13 12:36:28 PM PDT 24
Finished Jun 13 12:36:31 PM PDT 24
Peak memory 218076 kb
Host smart-b516c32d-94a3-44f5-b2d4-f5d7cb1df649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785931529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3785931529
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2551633165
Short name T396
Test name
Test status
Simulation time 111323532 ps
CPU time 0.86 seconds
Started Jun 13 12:36:09 PM PDT 24
Finished Jun 13 12:36:12 PM PDT 24
Peak memory 200512 kb
Host smart-e4e86c85-5d31-48ae-b274-965434ba0cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551633165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2551633165
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1558534103
Short name T71
Test name
Test status
Simulation time 1016458408 ps
CPU time 4.69 seconds
Started Jun 13 12:36:36 PM PDT 24
Finished Jun 13 12:36:42 PM PDT 24
Peak memory 200804 kb
Host smart-c20df5a5-0110-4762-b343-6b50ca9dd4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558534103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1558534103
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2078685902
Short name T280
Test name
Test status
Simulation time 139522427 ps
CPU time 1.08 seconds
Started Jun 13 12:36:11 PM PDT 24
Finished Jun 13 12:36:15 PM PDT 24
Peak memory 200596 kb
Host smart-9aad5d61-cd27-4b52-9065-68b967e1a6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078685902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2078685902
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3928189436
Short name T160
Test name
Test status
Simulation time 117321386 ps
CPU time 1.22 seconds
Started Jun 13 12:36:12 PM PDT 24
Finished Jun 13 12:36:16 PM PDT 24
Peak memory 200840 kb
Host smart-7938f365-6418-43d9-b00c-64c9695ba483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928189436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3928189436
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2244942640
Short name T302
Test name
Test status
Simulation time 5731985149 ps
CPU time 24.85 seconds
Started Jun 13 12:36:10 PM PDT 24
Finished Jun 13 12:36:39 PM PDT 24
Peak memory 209036 kb
Host smart-e740787c-2345-4bfc-94eb-3d5d1a1a90cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244942640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2244942640
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.3171711569
Short name T300
Test name
Test status
Simulation time 322161040 ps
CPU time 2.02 seconds
Started Jun 13 12:36:12 PM PDT 24
Finished Jun 13 12:36:17 PM PDT 24
Peak memory 200596 kb
Host smart-85653a25-aea8-4a1a-8134-45460318b389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171711569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.3171711569
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3627294164
Short name T496
Test name
Test status
Simulation time 239732772 ps
CPU time 1.43 seconds
Started Jun 13 12:36:02 PM PDT 24
Finished Jun 13 12:36:07 PM PDT 24
Peak memory 200652 kb
Host smart-06c5c8d7-709c-4c24-bb2b-051e3b8027b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627294164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3627294164
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1769840610
Short name T453
Test name
Test status
Simulation time 98956469 ps
CPU time 0.81 seconds
Started Jun 13 12:36:09 PM PDT 24
Finished Jun 13 12:36:12 PM PDT 24
Peak memory 200400 kb
Host smart-67f45502-bc83-41b7-86a6-90f344df5274
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769840610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1769840610
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2504843058
Short name T298
Test name
Test status
Simulation time 1217947210 ps
CPU time 5.2 seconds
Started Jun 13 12:36:23 PM PDT 24
Finished Jun 13 12:36:32 PM PDT 24
Peak memory 222388 kb
Host smart-f8c6e542-d771-49d7-99b8-ceb033ef0fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504843058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2504843058
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.497759642
Short name T538
Test name
Test status
Simulation time 244617527 ps
CPU time 1.08 seconds
Started Jun 13 12:35:57 PM PDT 24
Finished Jun 13 12:36:02 PM PDT 24
Peak memory 218072 kb
Host smart-d40dd485-0009-49e7-a563-9f6c4a3a0788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497759642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.497759642
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1209472501
Short name T440
Test name
Test status
Simulation time 208783491 ps
CPU time 0.97 seconds
Started Jun 13 12:36:12 PM PDT 24
Finished Jun 13 12:36:17 PM PDT 24
Peak memory 200392 kb
Host smart-8f9ad2f0-d590-47ed-9026-e6ad7cbae413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209472501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1209472501
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.294041048
Short name T121
Test name
Test status
Simulation time 1605498519 ps
CPU time 6.39 seconds
Started Jun 13 12:36:23 PM PDT 24
Finished Jun 13 12:36:32 PM PDT 24
Peak memory 200868 kb
Host smart-5bfae047-3b4c-4cef-9651-9ab844028e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294041048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.294041048
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.687600978
Short name T150
Test name
Test status
Simulation time 108775314 ps
CPU time 1 seconds
Started Jun 13 12:36:17 PM PDT 24
Finished Jun 13 12:36:22 PM PDT 24
Peak memory 200668 kb
Host smart-d7ebfd38-a294-4bea-b0ac-4732d035641a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687600978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.687600978
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.4000968087
Short name T517
Test name
Test status
Simulation time 117908221 ps
CPU time 1.22 seconds
Started Jun 13 12:36:11 PM PDT 24
Finished Jun 13 12:36:16 PM PDT 24
Peak memory 200784 kb
Host smart-b53d1f20-80ee-4a0a-803d-0ca97b6a4c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000968087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.4000968087
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.3445354609
Short name T163
Test name
Test status
Simulation time 1035214883 ps
CPU time 4.6 seconds
Started Jun 13 12:36:07 PM PDT 24
Finished Jun 13 12:36:15 PM PDT 24
Peak memory 200812 kb
Host smart-aa8f8c18-4ccf-411a-a04e-079459c1716c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445354609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3445354609
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3882848060
Short name T293
Test name
Test status
Simulation time 127900958 ps
CPU time 1.59 seconds
Started Jun 13 12:36:13 PM PDT 24
Finished Jun 13 12:36:18 PM PDT 24
Peak memory 208884 kb
Host smart-f2dd672e-7a0a-4cbd-bf11-c265520c5a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882848060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3882848060
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1260709132
Short name T312
Test name
Test status
Simulation time 234945610 ps
CPU time 1.43 seconds
Started Jun 13 12:36:13 PM PDT 24
Finished Jun 13 12:36:18 PM PDT 24
Peak memory 200824 kb
Host smart-06e0b2e9-7565-4a80-a5f8-24ec735873d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260709132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1260709132
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2137297741
Short name T228
Test name
Test status
Simulation time 76819603 ps
CPU time 0.77 seconds
Started Jun 13 12:36:13 PM PDT 24
Finished Jun 13 12:36:17 PM PDT 24
Peak memory 200496 kb
Host smart-d137a0a4-a5eb-4e67-8fb5-e8fdefb52205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137297741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2137297741
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1578915472
Short name T384
Test name
Test status
Simulation time 1897344353 ps
CPU time 7.31 seconds
Started Jun 13 12:36:07 PM PDT 24
Finished Jun 13 12:36:17 PM PDT 24
Peak memory 217356 kb
Host smart-6de46e5b-b53b-44d8-8bcb-37b2d1f19c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578915472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1578915472
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3095791197
Short name T397
Test name
Test status
Simulation time 243706602 ps
CPU time 1.04 seconds
Started Jun 13 12:36:27 PM PDT 24
Finished Jun 13 12:36:30 PM PDT 24
Peak memory 218096 kb
Host smart-19740b07-6b90-4f0e-bc58-eb0490dcc498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095791197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3095791197
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3443573977
Short name T539
Test name
Test status
Simulation time 776531042 ps
CPU time 4.13 seconds
Started Jun 13 12:36:05 PM PDT 24
Finished Jun 13 12:36:12 PM PDT 24
Peak memory 200808 kb
Host smart-dfc3ac55-165c-4d6d-a6b6-cb5a8e68c005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443573977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3443573977
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1367958388
Short name T156
Test name
Test status
Simulation time 110445788 ps
CPU time 0.99 seconds
Started Jun 13 12:36:18 PM PDT 24
Finished Jun 13 12:36:23 PM PDT 24
Peak memory 200700 kb
Host smart-8a3aa4ca-4301-476e-ba4f-2ff80de39421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367958388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1367958388
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3252026749
Short name T497
Test name
Test status
Simulation time 186905124 ps
CPU time 1.3 seconds
Started Jun 13 12:36:09 PM PDT 24
Finished Jun 13 12:36:13 PM PDT 24
Peak memory 200812 kb
Host smart-2cb3cc57-2f93-402a-a083-9666ff915600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252026749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3252026749
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1744277433
Short name T499
Test name
Test status
Simulation time 6479866323 ps
CPU time 27.6 seconds
Started Jun 13 12:36:03 PM PDT 24
Finished Jun 13 12:36:34 PM PDT 24
Peak memory 200876 kb
Host smart-5fea35cd-fb5f-4d00-b060-9c14d269db4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744277433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1744277433
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.3557975347
Short name T434
Test name
Test status
Simulation time 333077199 ps
CPU time 2.29 seconds
Started Jun 13 12:36:07 PM PDT 24
Finished Jun 13 12:36:12 PM PDT 24
Peak memory 200584 kb
Host smart-2efec52c-6daa-411a-a8e9-ca0233a0ab17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557975347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3557975347
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.277103284
Short name T264
Test name
Test status
Simulation time 111441279 ps
CPU time 0.88 seconds
Started Jun 13 12:36:04 PM PDT 24
Finished Jun 13 12:36:08 PM PDT 24
Peak memory 200644 kb
Host smart-03297cde-33cb-46ba-b803-72269f715688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277103284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.277103284
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2025417693
Short name T189
Test name
Test status
Simulation time 65818511 ps
CPU time 0.73 seconds
Started Jun 13 12:36:13 PM PDT 24
Finished Jun 13 12:36:17 PM PDT 24
Peak memory 200436 kb
Host smart-44f08a44-2a2f-4d6e-8266-6e70c6d586a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025417693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2025417693
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3149206224
Short name T334
Test name
Test status
Simulation time 1894460870 ps
CPU time 6.73 seconds
Started Jun 13 12:36:23 PM PDT 24
Finished Jun 13 12:36:33 PM PDT 24
Peak memory 222436 kb
Host smart-82fcefbb-77ef-4a80-bddd-938131c2ac17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149206224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3149206224
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3159497672
Short name T296
Test name
Test status
Simulation time 244663268 ps
CPU time 1.07 seconds
Started Jun 13 12:36:08 PM PDT 24
Finished Jun 13 12:36:11 PM PDT 24
Peak memory 218012 kb
Host smart-d5307d31-339b-4ff7-aec5-5704697c8c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159497672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3159497672
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2458789626
Short name T394
Test name
Test status
Simulation time 136943525 ps
CPU time 0.84 seconds
Started Jun 13 12:36:16 PM PDT 24
Finished Jun 13 12:36:21 PM PDT 24
Peak memory 200512 kb
Host smart-7b12d6ef-1ccb-4ba8-8b82-ee410b159db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458789626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2458789626
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3410042335
Short name T325
Test name
Test status
Simulation time 800004112 ps
CPU time 4.56 seconds
Started Jun 13 12:36:11 PM PDT 24
Finished Jun 13 12:36:19 PM PDT 24
Peak memory 200804 kb
Host smart-3565ef3a-05e4-4063-923d-04bda11ae4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410042335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3410042335
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.10519387
Short name T419
Test name
Test status
Simulation time 109028993 ps
CPU time 1.03 seconds
Started Jun 13 12:36:43 PM PDT 24
Finished Jun 13 12:36:45 PM PDT 24
Peak memory 200608 kb
Host smart-fa3cf24b-285c-4470-8a6b-b78257e542f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10519387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.10519387
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.3343470214
Short name T354
Test name
Test status
Simulation time 126910339 ps
CPU time 1.13 seconds
Started Jun 13 12:36:11 PM PDT 24
Finished Jun 13 12:36:15 PM PDT 24
Peak memory 200884 kb
Host smart-246fa121-3eff-45bc-93bd-5f2b03f68914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343470214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.3343470214
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.1098093185
Short name T269
Test name
Test status
Simulation time 8549931588 ps
CPU time 32.5 seconds
Started Jun 13 12:36:22 PM PDT 24
Finished Jun 13 12:36:57 PM PDT 24
Peak memory 200876 kb
Host smart-2e22958a-1f8c-4d69-8a40-82b84590b404
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098093185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1098093185
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2243253540
Short name T374
Test name
Test status
Simulation time 374953075 ps
CPU time 2.44 seconds
Started Jun 13 12:36:09 PM PDT 24
Finished Jun 13 12:36:14 PM PDT 24
Peak memory 200628 kb
Host smart-a31bba62-b1c2-42e4-86ba-bd687bed622b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243253540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2243253540
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.629404601
Short name T473
Test name
Test status
Simulation time 211372572 ps
CPU time 1.34 seconds
Started Jun 13 12:36:16 PM PDT 24
Finished Jun 13 12:36:21 PM PDT 24
Peak memory 200664 kb
Host smart-c79756b6-5984-4328-a24d-151eebd20582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629404601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.629404601
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1679364571
Short name T29
Test name
Test status
Simulation time 63237871 ps
CPU time 0.74 seconds
Started Jun 13 12:36:10 PM PDT 24
Finished Jun 13 12:36:14 PM PDT 24
Peak memory 200400 kb
Host smart-ea7f6a9e-9991-4a02-8cf9-bcf1d42ec5c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679364571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1679364571
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.183675527
Short name T187
Test name
Test status
Simulation time 243576470 ps
CPU time 1.05 seconds
Started Jun 13 12:36:11 PM PDT 24
Finished Jun 13 12:36:15 PM PDT 24
Peak memory 218016 kb
Host smart-4e3519f7-4cad-4ebc-9d64-092a1d3e5461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183675527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.183675527
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3722880690
Short name T23
Test name
Test status
Simulation time 150201421 ps
CPU time 0.83 seconds
Started Jun 13 12:36:29 PM PDT 24
Finished Jun 13 12:36:32 PM PDT 24
Peak memory 200480 kb
Host smart-ca02c91b-fd44-4cec-aecd-eb5f07487e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722880690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3722880690
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3249240414
Short name T370
Test name
Test status
Simulation time 2000680328 ps
CPU time 7.39 seconds
Started Jun 13 12:36:23 PM PDT 24
Finished Jun 13 12:36:34 PM PDT 24
Peak memory 200812 kb
Host smart-c2f89851-6a98-4334-bdbd-0a044d05f440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249240414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3249240414
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1334588596
Short name T174
Test name
Test status
Simulation time 117155395 ps
CPU time 1.02 seconds
Started Jun 13 12:36:12 PM PDT 24
Finished Jun 13 12:36:22 PM PDT 24
Peak memory 200692 kb
Host smart-fd4818cb-c0a2-48d5-8d4f-bf0d2f9c2db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334588596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1334588596
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.1472235011
Short name T536
Test name
Test status
Simulation time 237404583 ps
CPU time 1.44 seconds
Started Jun 13 12:36:16 PM PDT 24
Finished Jun 13 12:36:21 PM PDT 24
Peak memory 200752 kb
Host smart-b0ede1d7-e57f-4177-9b0d-02e0f2625c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472235011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1472235011
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2278698841
Short name T27
Test name
Test status
Simulation time 5650914947 ps
CPU time 20.25 seconds
Started Jun 13 12:36:10 PM PDT 24
Finished Jun 13 12:36:34 PM PDT 24
Peak memory 200896 kb
Host smart-4be98a01-6519-454a-a033-7c90dbc9987a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278698841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2278698841
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.750535249
Short name T498
Test name
Test status
Simulation time 119735975 ps
CPU time 1.48 seconds
Started Jun 13 12:36:22 PM PDT 24
Finished Jun 13 12:36:26 PM PDT 24
Peak memory 200676 kb
Host smart-b0de1c07-09ff-4c66-a282-9f51c55765da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750535249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.750535249
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1132476912
Short name T385
Test name
Test status
Simulation time 113822851 ps
CPU time 1 seconds
Started Jun 13 12:36:14 PM PDT 24
Finished Jun 13 12:36:19 PM PDT 24
Peak memory 200640 kb
Host smart-a13726f1-2676-4a88-94af-d18639877f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132476912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1132476912
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2516148912
Short name T232
Test name
Test status
Simulation time 79444973 ps
CPU time 0.8 seconds
Started Jun 13 12:35:40 PM PDT 24
Finished Jun 13 12:35:42 PM PDT 24
Peak memory 200424 kb
Host smart-21c4fe12-f0d7-4054-b6bf-3ba2e0a003ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516148912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2516148912
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2721858414
Short name T36
Test name
Test status
Simulation time 1895919168 ps
CPU time 7.59 seconds
Started Jun 13 12:35:54 PM PDT 24
Finished Jun 13 12:36:05 PM PDT 24
Peak memory 218480 kb
Host smart-04425e5b-4624-4867-bd87-a07a54a5599e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721858414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2721858414
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.388291684
Short name T240
Test name
Test status
Simulation time 243948578 ps
CPU time 1.13 seconds
Started Jun 13 12:35:57 PM PDT 24
Finished Jun 13 12:36:03 PM PDT 24
Peak memory 218016 kb
Host smart-51a4939d-341d-498b-ae8f-d60733a8eeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388291684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.388291684
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1393670645
Short name T250
Test name
Test status
Simulation time 109663891 ps
CPU time 0.78 seconds
Started Jun 13 12:35:40 PM PDT 24
Finished Jun 13 12:35:42 PM PDT 24
Peak memory 200408 kb
Host smart-3280876f-ebd0-41af-ac82-d555b25967e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393670645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1393670645
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2787513684
Short name T341
Test name
Test status
Simulation time 2015870726 ps
CPU time 7.27 seconds
Started Jun 13 12:35:58 PM PDT 24
Finished Jun 13 12:36:10 PM PDT 24
Peak memory 200812 kb
Host smart-9cb8c05b-37da-41b6-ba7b-049532a664e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787513684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2787513684
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2973173328
Short name T67
Test name
Test status
Simulation time 8283962083 ps
CPU time 14.78 seconds
Started Jun 13 12:36:02 PM PDT 24
Finished Jun 13 12:36:21 PM PDT 24
Peak memory 217576 kb
Host smart-3b6a5d8b-9cc1-4265-99da-2cd1b32acf31
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973173328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2973173328
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2067190678
Short name T224
Test name
Test status
Simulation time 154910647 ps
CPU time 1.14 seconds
Started Jun 13 12:35:56 PM PDT 24
Finished Jun 13 12:36:02 PM PDT 24
Peak memory 200632 kb
Host smart-a426f1c5-f69f-4312-8cdb-15b213d257fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067190678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2067190678
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.2505891563
Short name T322
Test name
Test status
Simulation time 123651007 ps
CPU time 1.2 seconds
Started Jun 13 12:36:03 PM PDT 24
Finished Jun 13 12:36:12 PM PDT 24
Peak memory 200776 kb
Host smart-4bf31a00-f5be-48bd-a8eb-3559ead1cb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505891563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2505891563
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2876128281
Short name T363
Test name
Test status
Simulation time 7025094641 ps
CPU time 31.66 seconds
Started Jun 13 12:36:06 PM PDT 24
Finished Jun 13 12:36:41 PM PDT 24
Peak memory 200932 kb
Host smart-ad993844-952c-4743-8a92-388354253cb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876128281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2876128281
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3332310957
Short name T416
Test name
Test status
Simulation time 375165599 ps
CPU time 2.33 seconds
Started Jun 13 12:36:01 PM PDT 24
Finished Jun 13 12:36:08 PM PDT 24
Peak memory 200664 kb
Host smart-a17da16a-8983-4003-b071-c656ea9a72f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332310957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3332310957
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3757890377
Short name T238
Test name
Test status
Simulation time 132237962 ps
CPU time 1.14 seconds
Started Jun 13 12:35:39 PM PDT 24
Finished Jun 13 12:35:43 PM PDT 24
Peak memory 200644 kb
Host smart-12c2851d-5c3b-4668-aa37-52fc58b4f1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757890377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3757890377
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.4049045603
Short name T241
Test name
Test status
Simulation time 65490479 ps
CPU time 0.82 seconds
Started Jun 13 12:36:19 PM PDT 24
Finished Jun 13 12:36:23 PM PDT 24
Peak memory 200392 kb
Host smart-8d746a15-2e57-416d-914f-fcea8f383345
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049045603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.4049045603
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1850445972
Short name T34
Test name
Test status
Simulation time 1897719325 ps
CPU time 6.79 seconds
Started Jun 13 12:36:06 PM PDT 24
Finished Jun 13 12:36:16 PM PDT 24
Peak memory 222272 kb
Host smart-f13ebc2f-64cf-459f-ba85-8a5bb191f298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850445972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1850445972
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2347807305
Short name T230
Test name
Test status
Simulation time 243291797 ps
CPU time 1.07 seconds
Started Jun 13 12:36:13 PM PDT 24
Finished Jun 13 12:36:17 PM PDT 24
Peak memory 218004 kb
Host smart-5b571262-4706-4ebd-9636-8ddf2e36d0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347807305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2347807305
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2401568620
Short name T301
Test name
Test status
Simulation time 172446227 ps
CPU time 0.92 seconds
Started Jun 13 12:36:12 PM PDT 24
Finished Jun 13 12:36:26 PM PDT 24
Peak memory 200460 kb
Host smart-3986ccd8-0b5d-42c1-be8f-a78942e5ad14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401568620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2401568620
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.1316345520
Short name T323
Test name
Test status
Simulation time 1429048915 ps
CPU time 5.32 seconds
Started Jun 13 12:36:24 PM PDT 24
Finished Jun 13 12:36:33 PM PDT 24
Peak memory 200400 kb
Host smart-ee377194-eb5e-4a89-837f-daeb266b3726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316345520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1316345520
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1547495479
Short name T393
Test name
Test status
Simulation time 101997163 ps
CPU time 1.07 seconds
Started Jun 13 12:36:15 PM PDT 24
Finished Jun 13 12:36:20 PM PDT 24
Peak memory 200692 kb
Host smart-e44f3a4e-018b-4926-b0bb-7c5c4de4450a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547495479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1547495479
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3980005317
Short name T355
Test name
Test status
Simulation time 115412846 ps
CPU time 1.22 seconds
Started Jun 13 12:36:14 PM PDT 24
Finished Jun 13 12:36:19 PM PDT 24
Peak memory 201108 kb
Host smart-d20dbb40-e4a0-4019-b234-71e11126a242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980005317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3980005317
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.4225179470
Short name T226
Test name
Test status
Simulation time 1147463079 ps
CPU time 5.43 seconds
Started Jun 13 12:36:02 PM PDT 24
Finished Jun 13 12:36:12 PM PDT 24
Peak memory 209320 kb
Host smart-94c882fd-cf2a-461c-a607-1e4cf58ec011
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225179470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.4225179470
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2372194675
Short name T364
Test name
Test status
Simulation time 515786548 ps
CPU time 2.54 seconds
Started Jun 13 12:36:07 PM PDT 24
Finished Jun 13 12:36:13 PM PDT 24
Peak memory 200628 kb
Host smart-88a51cc0-2124-4760-b4ea-b0297013f89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372194675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2372194675
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2225413403
Short name T258
Test name
Test status
Simulation time 238653198 ps
CPU time 1.41 seconds
Started Jun 13 12:36:06 PM PDT 24
Finished Jun 13 12:36:11 PM PDT 24
Peak memory 200792 kb
Host smart-1f99959c-02e9-4bf1-afb0-7e32302bae76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225413403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2225413403
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2033545433
Short name T533
Test name
Test status
Simulation time 74438255 ps
CPU time 0.77 seconds
Started Jun 13 12:36:12 PM PDT 24
Finished Jun 13 12:36:16 PM PDT 24
Peak memory 200456 kb
Host smart-8073e1e7-659b-4f64-a313-a9e099f58d62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033545433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2033545433
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1641786484
Short name T44
Test name
Test status
Simulation time 1219745645 ps
CPU time 5.59 seconds
Started Jun 13 12:36:29 PM PDT 24
Finished Jun 13 12:36:40 PM PDT 24
Peak memory 217856 kb
Host smart-4439adfc-5bd5-496a-aed9-0553df92c94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641786484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1641786484
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2439071155
Short name T139
Test name
Test status
Simulation time 243484135 ps
CPU time 1.03 seconds
Started Jun 13 12:36:10 PM PDT 24
Finished Jun 13 12:36:15 PM PDT 24
Peak memory 218100 kb
Host smart-57d3ff08-f96c-4688-b88c-738ba6cc5842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439071155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2439071155
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3652445873
Short name T14
Test name
Test status
Simulation time 193705477 ps
CPU time 0.85 seconds
Started Jun 13 12:36:17 PM PDT 24
Finished Jun 13 12:36:21 PM PDT 24
Peak memory 200424 kb
Host smart-84e58d69-3d98-4a27-9b48-3adbe479c65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652445873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3652445873
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.1049503516
Short name T193
Test name
Test status
Simulation time 1416788269 ps
CPU time 6.02 seconds
Started Jun 13 12:36:15 PM PDT 24
Finished Jun 13 12:36:25 PM PDT 24
Peak memory 200784 kb
Host smart-b1071390-b8d0-4bb9-8423-55ca0fad662c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049503516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.1049503516
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1972317032
Short name T320
Test name
Test status
Simulation time 154116663 ps
CPU time 1.16 seconds
Started Jun 13 12:36:30 PM PDT 24
Finished Jun 13 12:36:33 PM PDT 24
Peak memory 200704 kb
Host smart-bad8c108-6d45-4bae-8ec1-6bdfa8f1384d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972317032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1972317032
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1320216411
Short name T236
Test name
Test status
Simulation time 117873977 ps
CPU time 1.15 seconds
Started Jun 13 12:36:10 PM PDT 24
Finished Jun 13 12:36:14 PM PDT 24
Peak memory 200812 kb
Host smart-83feb0c7-b7ff-432d-b90a-773c6f0fba2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320216411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1320216411
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.3610513133
Short name T257
Test name
Test status
Simulation time 6216196031 ps
CPU time 28.03 seconds
Started Jun 13 12:36:24 PM PDT 24
Finished Jun 13 12:36:56 PM PDT 24
Peak memory 209100 kb
Host smart-a5c2ea21-8a9b-49ad-a014-1c7ed3f24297
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610513133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3610513133
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2743736680
Short name T288
Test name
Test status
Simulation time 356659022 ps
CPU time 2.35 seconds
Started Jun 13 12:36:04 PM PDT 24
Finished Jun 13 12:36:10 PM PDT 24
Peak memory 200640 kb
Host smart-296d3b46-5124-46c3-a4e4-9ab0ac4a540b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743736680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2743736680
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.97271109
Short name T216
Test name
Test status
Simulation time 89746077 ps
CPU time 0.93 seconds
Started Jun 13 12:36:13 PM PDT 24
Finished Jun 13 12:36:18 PM PDT 24
Peak memory 200648 kb
Host smart-0edc5bd0-5362-4884-9e92-4ca4a4e015d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97271109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.97271109
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2140247244
Short name T245
Test name
Test status
Simulation time 66823582 ps
CPU time 0.73 seconds
Started Jun 13 12:36:10 PM PDT 24
Finished Jun 13 12:36:13 PM PDT 24
Peak memory 200436 kb
Host smart-e2a55c91-2e29-4c88-a80e-7b73aef7d16d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140247244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2140247244
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2776303627
Short name T345
Test name
Test status
Simulation time 1218822564 ps
CPU time 5.72 seconds
Started Jun 13 12:36:30 PM PDT 24
Finished Jun 13 12:36:38 PM PDT 24
Peak memory 217984 kb
Host smart-e09f11e7-7665-49eb-b6d5-dd87d8844466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776303627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2776303627
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1335268486
Short name T242
Test name
Test status
Simulation time 243741229 ps
CPU time 1.09 seconds
Started Jun 13 12:36:19 PM PDT 24
Finished Jun 13 12:36:23 PM PDT 24
Peak memory 217984 kb
Host smart-c096f12b-4a56-4d53-8710-a57ccd689320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335268486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1335268486
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.249137154
Short name T403
Test name
Test status
Simulation time 180321372 ps
CPU time 0.95 seconds
Started Jun 13 12:36:15 PM PDT 24
Finished Jun 13 12:36:19 PM PDT 24
Peak memory 200424 kb
Host smart-ab1dc2bc-63f9-45f6-87c6-a547c3a77c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249137154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.249137154
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3828956296
Short name T332
Test name
Test status
Simulation time 1466039834 ps
CPU time 6.02 seconds
Started Jun 13 12:36:13 PM PDT 24
Finished Jun 13 12:36:23 PM PDT 24
Peak memory 200904 kb
Host smart-d06fff0c-0107-4c2c-85ad-2422d0f3dd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828956296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3828956296
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1862389314
Short name T455
Test name
Test status
Simulation time 152983115 ps
CPU time 1.18 seconds
Started Jun 13 12:36:14 PM PDT 24
Finished Jun 13 12:36:19 PM PDT 24
Peak memory 200644 kb
Host smart-0bbfde4c-d87c-4719-a73a-6d45ef0ec139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862389314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1862389314
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2343524133
Short name T407
Test name
Test status
Simulation time 261660010 ps
CPU time 1.41 seconds
Started Jun 13 12:36:26 PM PDT 24
Finished Jun 13 12:36:30 PM PDT 24
Peak memory 200808 kb
Host smart-2ded138c-86f6-46c6-adc1-9a883beb9869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343524133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2343524133
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2233297313
Short name T94
Test name
Test status
Simulation time 4025306843 ps
CPU time 18.88 seconds
Started Jun 13 12:36:14 PM PDT 24
Finished Jun 13 12:36:37 PM PDT 24
Peak memory 209788 kb
Host smart-d88e6d64-f0a5-41df-a2b4-ceeb2d316780
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233297313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2233297313
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2490233140
Short name T509
Test name
Test status
Simulation time 388196306 ps
CPU time 2.5 seconds
Started Jun 13 12:36:16 PM PDT 24
Finished Jun 13 12:36:22 PM PDT 24
Peak memory 200624 kb
Host smart-81d734e7-cb45-4b61-ac10-08e74f102c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490233140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2490233140
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3637296526
Short name T373
Test name
Test status
Simulation time 138953081 ps
CPU time 1.15 seconds
Started Jun 13 12:36:16 PM PDT 24
Finished Jun 13 12:36:21 PM PDT 24
Peak memory 200700 kb
Host smart-46b7b80e-ce04-491c-b566-8f4128465eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637296526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3637296526
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1918613128
Short name T260
Test name
Test status
Simulation time 90400047 ps
CPU time 0.83 seconds
Started Jun 13 12:36:11 PM PDT 24
Finished Jun 13 12:36:15 PM PDT 24
Peak memory 200400 kb
Host smart-55d1bb34-a76d-48f2-9113-11c081dba915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918613128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1918613128
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1455750477
Short name T249
Test name
Test status
Simulation time 2340583319 ps
CPU time 8.05 seconds
Started Jun 13 12:36:29 PM PDT 24
Finished Jun 13 12:36:39 PM PDT 24
Peak memory 217832 kb
Host smart-b39398de-8221-4a01-912e-0fb654ba3881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455750477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1455750477
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.192223573
Short name T244
Test name
Test status
Simulation time 243866154 ps
CPU time 1.05 seconds
Started Jun 13 12:36:18 PM PDT 24
Finished Jun 13 12:36:27 PM PDT 24
Peak memory 217996 kb
Host smart-41e81ffc-73f0-432e-a48a-b7ceea7a659c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192223573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.192223573
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.313738396
Short name T378
Test name
Test status
Simulation time 81608233 ps
CPU time 0.74 seconds
Started Jun 13 12:36:32 PM PDT 24
Finished Jun 13 12:36:34 PM PDT 24
Peak memory 200488 kb
Host smart-23ea89b4-a67d-489c-8691-5117fbb1e608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313738396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.313738396
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.4149366939
Short name T96
Test name
Test status
Simulation time 764838156 ps
CPU time 3.8 seconds
Started Jun 13 12:36:15 PM PDT 24
Finished Jun 13 12:36:27 PM PDT 24
Peak memory 200848 kb
Host smart-01a05cc3-c394-4a99-b82e-493f9b967b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149366939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.4149366939
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1649970137
Short name T417
Test name
Test status
Simulation time 139660079 ps
CPU time 1.05 seconds
Started Jun 13 12:36:13 PM PDT 24
Finished Jun 13 12:36:18 PM PDT 24
Peak memory 200640 kb
Host smart-660bfb68-4bcd-407e-b974-9b7a0c5b0332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649970137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1649970137
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1911760489
Short name T386
Test name
Test status
Simulation time 198778003 ps
CPU time 1.35 seconds
Started Jun 13 12:36:22 PM PDT 24
Finished Jun 13 12:36:26 PM PDT 24
Peak memory 200860 kb
Host smart-4d9b2eb2-ef02-4f4f-a833-94dc36ae66a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911760489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1911760489
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.223107772
Short name T31
Test name
Test status
Simulation time 176695410 ps
CPU time 1.13 seconds
Started Jun 13 12:36:15 PM PDT 24
Finished Jun 13 12:36:20 PM PDT 24
Peak memory 200588 kb
Host smart-c76e18f4-0517-4a41-a2da-db49cb40eb53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223107772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.223107772
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2267286097
Short name T190
Test name
Test status
Simulation time 136319451 ps
CPU time 1.67 seconds
Started Jun 13 12:36:14 PM PDT 24
Finished Jun 13 12:36:19 PM PDT 24
Peak memory 208844 kb
Host smart-f5983e11-08ce-4499-83e9-f1b532505e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267286097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2267286097
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3678638157
Short name T530
Test name
Test status
Simulation time 121826119 ps
CPU time 1.21 seconds
Started Jun 13 12:36:10 PM PDT 24
Finished Jun 13 12:36:15 PM PDT 24
Peak memory 200604 kb
Host smart-f23633af-7d4f-402c-8419-0f1c9e551b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678638157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3678638157
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3022773919
Short name T420
Test name
Test status
Simulation time 77988526 ps
CPU time 0.79 seconds
Started Jun 13 12:36:24 PM PDT 24
Finished Jun 13 12:36:28 PM PDT 24
Peak memory 200400 kb
Host smart-f340e8f5-b995-4067-b02c-86b0fd607251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022773919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3022773919
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3869676261
Short name T366
Test name
Test status
Simulation time 1222995086 ps
CPU time 6.07 seconds
Started Jun 13 12:36:30 PM PDT 24
Finished Jun 13 12:36:38 PM PDT 24
Peak memory 218460 kb
Host smart-0c9515ff-bfd9-495c-b9a2-c108307b2d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869676261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3869676261
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3625800116
Short name T290
Test name
Test status
Simulation time 244788633 ps
CPU time 1.15 seconds
Started Jun 13 12:36:14 PM PDT 24
Finished Jun 13 12:36:19 PM PDT 24
Peak memory 218104 kb
Host smart-634fca26-13c4-4d44-ad81-94c948e17625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625800116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3625800116
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1247666118
Short name T448
Test name
Test status
Simulation time 205201738 ps
CPU time 0.96 seconds
Started Jun 13 12:36:14 PM PDT 24
Finished Jun 13 12:36:19 PM PDT 24
Peak memory 200412 kb
Host smart-e83d2d23-e340-4f84-a223-84b3b3d43605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247666118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1247666118
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.401140959
Short name T490
Test name
Test status
Simulation time 663168896 ps
CPU time 3.73 seconds
Started Jun 13 12:36:16 PM PDT 24
Finished Jun 13 12:36:23 PM PDT 24
Peak memory 200876 kb
Host smart-219054ca-62d2-4bcd-a9f0-b365435b72a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401140959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.401140959
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3037616256
Short name T243
Test name
Test status
Simulation time 166322839 ps
CPU time 1.13 seconds
Started Jun 13 12:36:18 PM PDT 24
Finished Jun 13 12:36:22 PM PDT 24
Peak memory 200672 kb
Host smart-0bdfaf06-744b-44c9-a14a-3b1619779d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037616256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3037616256
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1252198133
Short name T231
Test name
Test status
Simulation time 227867179 ps
CPU time 1.45 seconds
Started Jun 13 12:36:16 PM PDT 24
Finished Jun 13 12:36:21 PM PDT 24
Peak memory 200812 kb
Host smart-5fa77984-9c94-4745-8bb4-16eab831c82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252198133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1252198133
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3942747754
Short name T251
Test name
Test status
Simulation time 9459639100 ps
CPU time 34.1 seconds
Started Jun 13 12:36:35 PM PDT 24
Finished Jun 13 12:37:11 PM PDT 24
Peak memory 200836 kb
Host smart-7323fdda-d866-4281-83d5-bb5221851d15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942747754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3942747754
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1679344016
Short name T376
Test name
Test status
Simulation time 336444152 ps
CPU time 2.04 seconds
Started Jun 13 12:36:22 PM PDT 24
Finished Jun 13 12:36:27 PM PDT 24
Peak memory 208788 kb
Host smart-dd5e51a1-46c6-42fd-afa8-ab98d98d0643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679344016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1679344016
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2052862159
Short name T255
Test name
Test status
Simulation time 67699084 ps
CPU time 0.81 seconds
Started Jun 13 12:36:10 PM PDT 24
Finished Jun 13 12:36:14 PM PDT 24
Peak memory 200620 kb
Host smart-cc17105b-75eb-4020-9628-47841885dd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052862159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2052862159
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2904277052
Short name T196
Test name
Test status
Simulation time 167023245 ps
CPU time 1 seconds
Started Jun 13 12:36:34 PM PDT 24
Finished Jun 13 12:36:36 PM PDT 24
Peak memory 200400 kb
Host smart-f6666e8b-5c4e-4960-b8e5-da334156c4ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904277052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2904277052
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2051589047
Short name T418
Test name
Test status
Simulation time 1901345799 ps
CPU time 7.35 seconds
Started Jun 13 12:36:20 PM PDT 24
Finished Jun 13 12:36:36 PM PDT 24
Peak memory 218484 kb
Host smart-d7aafbfe-9bfa-4d8a-9a73-901a92934c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051589047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2051589047
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2679526486
Short name T305
Test name
Test status
Simulation time 245523257 ps
CPU time 1.02 seconds
Started Jun 13 12:36:20 PM PDT 24
Finished Jun 13 12:36:24 PM PDT 24
Peak memory 218124 kb
Host smart-5e9a66c0-e90f-455e-a3fa-c17bccde6d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679526486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2679526486
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.463021387
Short name T274
Test name
Test status
Simulation time 128415882 ps
CPU time 0.79 seconds
Started Jun 13 12:36:14 PM PDT 24
Finished Jun 13 12:36:19 PM PDT 24
Peak memory 200512 kb
Host smart-ec51cfab-e017-42d0-82f0-cb30bdb694e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463021387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.463021387
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.416186071
Short name T213
Test name
Test status
Simulation time 834613410 ps
CPU time 4.26 seconds
Started Jun 13 12:36:16 PM PDT 24
Finished Jun 13 12:36:24 PM PDT 24
Peak memory 200844 kb
Host smart-96491622-ab0e-47fc-a368-a63d8a572cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416186071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.416186071
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.653022049
Short name T491
Test name
Test status
Simulation time 154993966 ps
CPU time 1.06 seconds
Started Jun 13 12:36:36 PM PDT 24
Finished Jun 13 12:36:38 PM PDT 24
Peak memory 200604 kb
Host smart-ea09dc79-fabf-451e-abb9-5df0eeefaf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653022049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.653022049
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.1077996264
Short name T136
Test name
Test status
Simulation time 123289304 ps
CPU time 1.22 seconds
Started Jun 13 12:36:11 PM PDT 24
Finished Jun 13 12:36:16 PM PDT 24
Peak memory 200856 kb
Host smart-5de1472a-e63c-41f2-9118-f7564b23be29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077996264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1077996264
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.2446478254
Short name T184
Test name
Test status
Simulation time 128700439 ps
CPU time 1.59 seconds
Started Jun 13 12:36:15 PM PDT 24
Finished Jun 13 12:36:20 PM PDT 24
Peak memory 200684 kb
Host smart-f3341f7d-a9ea-42d5-8600-408f4913d770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446478254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.2446478254
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.149548258
Short name T28
Test name
Test status
Simulation time 216862769 ps
CPU time 1.23 seconds
Started Jun 13 12:36:23 PM PDT 24
Finished Jun 13 12:36:27 PM PDT 24
Peak memory 200704 kb
Host smart-71eb8ce4-3e09-46e8-8c82-db00e14688d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149548258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.149548258
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1076519438
Short name T424
Test name
Test status
Simulation time 72362448 ps
CPU time 0.75 seconds
Started Jun 13 12:36:19 PM PDT 24
Finished Jun 13 12:36:23 PM PDT 24
Peak memory 200432 kb
Host smart-523d1136-107c-4f43-8d9b-2c5ca2a3e51f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076519438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1076519438
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.511888297
Short name T306
Test name
Test status
Simulation time 1220672925 ps
CPU time 5.68 seconds
Started Jun 13 12:36:25 PM PDT 24
Finished Jun 13 12:36:34 PM PDT 24
Peak memory 217992 kb
Host smart-160249f8-a62d-414f-94af-ede6df62f466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511888297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.511888297
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2041870675
Short name T451
Test name
Test status
Simulation time 244994709 ps
CPU time 1.06 seconds
Started Jun 13 12:36:17 PM PDT 24
Finished Jun 13 12:36:22 PM PDT 24
Peak memory 218088 kb
Host smart-de88fb6d-c7f9-4bad-a137-8b1b16483764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041870675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2041870675
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3712863734
Short name T19
Test name
Test status
Simulation time 166201880 ps
CPU time 0.86 seconds
Started Jun 13 12:36:20 PM PDT 24
Finished Jun 13 12:36:24 PM PDT 24
Peak memory 200396 kb
Host smart-c196a30e-4d3e-4537-abb0-b6c9ffd653b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712863734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3712863734
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1279574335
Short name T433
Test name
Test status
Simulation time 807444798 ps
CPU time 4.5 seconds
Started Jun 13 12:36:38 PM PDT 24
Finished Jun 13 12:36:44 PM PDT 24
Peak memory 200872 kb
Host smart-9b838032-1a88-4654-ab12-6f51d6f665c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279574335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1279574335
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1750143608
Short name T447
Test name
Test status
Simulation time 148117510 ps
CPU time 1.13 seconds
Started Jun 13 12:36:12 PM PDT 24
Finished Jun 13 12:36:17 PM PDT 24
Peak memory 200612 kb
Host smart-88b67e2d-9552-4df1-b73a-92edbbfe58c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750143608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1750143608
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3884273174
Short name T292
Test name
Test status
Simulation time 122202617 ps
CPU time 1.24 seconds
Started Jun 13 12:36:22 PM PDT 24
Finished Jun 13 12:36:26 PM PDT 24
Peak memory 200872 kb
Host smart-6b9e2e92-a458-42cb-a956-56088d0b756c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884273174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3884273174
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3820165147
Short name T209
Test name
Test status
Simulation time 1226659961 ps
CPU time 5.76 seconds
Started Jun 13 12:36:44 PM PDT 24
Finished Jun 13 12:36:50 PM PDT 24
Peak memory 200836 kb
Host smart-48290097-119f-4a14-a54b-cb7c01ab5eb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820165147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3820165147
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2884497519
Short name T444
Test name
Test status
Simulation time 129188900 ps
CPU time 1.72 seconds
Started Jun 13 12:36:25 PM PDT 24
Finished Jun 13 12:36:30 PM PDT 24
Peak memory 200688 kb
Host smart-920b6621-7ec8-495c-b284-5098a533dd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884497519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2884497519
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.1415961083
Short name T130
Test name
Test status
Simulation time 223239147 ps
CPU time 1.28 seconds
Started Jun 13 12:36:36 PM PDT 24
Finished Jun 13 12:36:38 PM PDT 24
Peak memory 200600 kb
Host smart-b378c03f-5f24-4a16-9556-5e09ad24df7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415961083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1415961083
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2011244639
Short name T492
Test name
Test status
Simulation time 70705445 ps
CPU time 0.84 seconds
Started Jun 13 12:36:14 PM PDT 24
Finished Jun 13 12:36:19 PM PDT 24
Peak memory 200436 kb
Host smart-6c7c6baa-0728-49aa-90d3-f12475f5cc47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011244639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2011244639
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3273069079
Short name T474
Test name
Test status
Simulation time 1891121230 ps
CPU time 6.94 seconds
Started Jun 13 12:36:10 PM PDT 24
Finished Jun 13 12:36:20 PM PDT 24
Peak memory 218300 kb
Host smart-8235d549-e42c-4536-8579-3b4a531d6164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273069079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3273069079
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2790602547
Short name T445
Test name
Test status
Simulation time 245067014 ps
CPU time 1.05 seconds
Started Jun 13 12:36:25 PM PDT 24
Finished Jun 13 12:36:30 PM PDT 24
Peak memory 218108 kb
Host smart-5477a3f4-59e0-4b84-a5eb-1cf59ccc5626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790602547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2790602547
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.4067192181
Short name T22
Test name
Test status
Simulation time 174912052 ps
CPU time 0.89 seconds
Started Jun 13 12:36:36 PM PDT 24
Finished Jun 13 12:36:38 PM PDT 24
Peak memory 200500 kb
Host smart-d1cdfd95-96c4-4815-ba5c-9c311a677dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067192181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.4067192181
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2926338701
Short name T372
Test name
Test status
Simulation time 1140659971 ps
CPU time 4.57 seconds
Started Jun 13 12:36:13 PM PDT 24
Finished Jun 13 12:36:21 PM PDT 24
Peak memory 200864 kb
Host smart-44f717cb-4054-4afb-842d-765ad2285e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926338701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2926338701
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.4256492918
Short name T159
Test name
Test status
Simulation time 142530653 ps
CPU time 1.06 seconds
Started Jun 13 12:36:10 PM PDT 24
Finished Jun 13 12:36:20 PM PDT 24
Peak memory 200720 kb
Host smart-a7e31795-6d6d-4088-97d8-4d48b2ca297d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256492918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.4256492918
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2455336261
Short name T339
Test name
Test status
Simulation time 116866788 ps
CPU time 1.19 seconds
Started Jun 13 12:36:18 PM PDT 24
Finished Jun 13 12:36:23 PM PDT 24
Peak memory 200884 kb
Host smart-91417610-9b57-43aa-b67b-6d4e59bd099a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455336261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2455336261
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3033009218
Short name T89
Test name
Test status
Simulation time 4082181130 ps
CPU time 19.36 seconds
Started Jun 13 12:36:35 PM PDT 24
Finished Jun 13 12:36:56 PM PDT 24
Peak memory 200940 kb
Host smart-01d3b719-67d2-48ef-91a6-22d4db48ee86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033009218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3033009218
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.4118769645
Short name T431
Test name
Test status
Simulation time 339484235 ps
CPU time 2.19 seconds
Started Jun 13 12:36:21 PM PDT 24
Finished Jun 13 12:36:26 PM PDT 24
Peak memory 200592 kb
Host smart-06a9f6c9-a81d-4613-9339-d78d1a3d73f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118769645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.4118769645
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1583219599
Short name T77
Test name
Test status
Simulation time 104616300 ps
CPU time 0.95 seconds
Started Jun 13 12:36:35 PM PDT 24
Finished Jun 13 12:36:38 PM PDT 24
Peak memory 200604 kb
Host smart-9f6825e2-f977-437e-9275-a3be745dcd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583219599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1583219599
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.2522072712
Short name T423
Test name
Test status
Simulation time 59658011 ps
CPU time 0.75 seconds
Started Jun 13 12:36:14 PM PDT 24
Finished Jun 13 12:36:19 PM PDT 24
Peak memory 200472 kb
Host smart-dd60cd4e-e726-4b45-b9f6-f402c6d54f40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522072712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2522072712
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1934717422
Short name T291
Test name
Test status
Simulation time 1229997122 ps
CPU time 5.65 seconds
Started Jun 13 12:36:25 PM PDT 24
Finished Jun 13 12:36:33 PM PDT 24
Peak memory 218452 kb
Host smart-2ddfa427-e9f5-436d-b5a7-84ffec9705da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934717422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1934717422
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2801976715
Short name T309
Test name
Test status
Simulation time 244499930 ps
CPU time 1.09 seconds
Started Jun 13 12:36:15 PM PDT 24
Finished Jun 13 12:36:20 PM PDT 24
Peak memory 218056 kb
Host smart-6a5e9ac7-b00c-4328-87b1-14b762decf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801976715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2801976715
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.609909840
Short name T389
Test name
Test status
Simulation time 88614888 ps
CPU time 0.79 seconds
Started Jun 13 12:36:25 PM PDT 24
Finished Jun 13 12:36:29 PM PDT 24
Peak memory 200448 kb
Host smart-33dd285d-7a68-457f-8acc-4e48055ea2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609909840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.609909840
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.994882055
Short name T327
Test name
Test status
Simulation time 1049171793 ps
CPU time 4.96 seconds
Started Jun 13 12:36:20 PM PDT 24
Finished Jun 13 12:36:28 PM PDT 24
Peak memory 200768 kb
Host smart-2f5054d1-fe6b-4192-a1ce-eabbe57d5df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994882055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.994882055
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1189676432
Short name T185
Test name
Test status
Simulation time 191447286 ps
CPU time 1.16 seconds
Started Jun 13 12:36:14 PM PDT 24
Finished Jun 13 12:36:19 PM PDT 24
Peak memory 200688 kb
Host smart-ea125768-096f-4d0e-af19-4fe8ad4868c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189676432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1189676432
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.3666491157
Short name T183
Test name
Test status
Simulation time 202286203 ps
CPU time 1.48 seconds
Started Jun 13 12:36:14 PM PDT 24
Finished Jun 13 12:36:19 PM PDT 24
Peak memory 200812 kb
Host smart-b8d1b1a1-ca2f-4b90-8d68-606df3ecd4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666491157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3666491157
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.503115556
Short name T202
Test name
Test status
Simulation time 164530918 ps
CPU time 1.57 seconds
Started Jun 13 12:36:19 PM PDT 24
Finished Jun 13 12:36:24 PM PDT 24
Peak memory 200616 kb
Host smart-2c5e3ad9-681a-4c11-8a19-53a4277e1388
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503115556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.503115556
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1078838993
Short name T390
Test name
Test status
Simulation time 138444182 ps
CPU time 1.67 seconds
Started Jun 13 12:36:17 PM PDT 24
Finished Jun 13 12:36:22 PM PDT 24
Peak memory 200680 kb
Host smart-04a75665-5511-4c1c-abe1-532c9cbb332d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078838993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1078838993
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2793417423
Short name T463
Test name
Test status
Simulation time 129277309 ps
CPU time 1.14 seconds
Started Jun 13 12:36:13 PM PDT 24
Finished Jun 13 12:36:18 PM PDT 24
Peak memory 200652 kb
Host smart-865cbb30-cbf1-47f7-9de3-bf21646f9197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793417423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2793417423
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3728269772
Short name T172
Test name
Test status
Simulation time 73366529 ps
CPU time 0.77 seconds
Started Jun 13 12:36:48 PM PDT 24
Finished Jun 13 12:36:52 PM PDT 24
Peak memory 200436 kb
Host smart-38c3c0b9-c2fd-4023-9d9e-6efe359dfb28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728269772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3728269772
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.4219225231
Short name T307
Test name
Test status
Simulation time 1231757038 ps
CPU time 5.82 seconds
Started Jun 13 12:36:41 PM PDT 24
Finished Jun 13 12:36:48 PM PDT 24
Peak memory 218484 kb
Host smart-fae65d12-6382-4c81-8ea8-daf85eaeb2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219225231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.4219225231
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.314727377
Short name T430
Test name
Test status
Simulation time 244441438 ps
CPU time 1.05 seconds
Started Jun 13 12:36:39 PM PDT 24
Finished Jun 13 12:36:41 PM PDT 24
Peak memory 218000 kb
Host smart-c480ac7a-da43-4390-8720-e046413b0b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314727377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.314727377
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3556438844
Short name T477
Test name
Test status
Simulation time 243068186 ps
CPU time 0.99 seconds
Started Jun 13 12:36:49 PM PDT 24
Finished Jun 13 12:36:54 PM PDT 24
Peak memory 200524 kb
Host smart-71b20609-a42e-49f0-bd8a-b6e64394c13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556438844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3556438844
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.478279955
Short name T85
Test name
Test status
Simulation time 744737071 ps
CPU time 3.84 seconds
Started Jun 13 12:36:10 PM PDT 24
Finished Jun 13 12:36:17 PM PDT 24
Peak memory 200772 kb
Host smart-1baa23fd-5ee9-486b-9f1a-1036cc8cb145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478279955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.478279955
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2465784201
Short name T265
Test name
Test status
Simulation time 112524664 ps
CPU time 1.06 seconds
Started Jun 13 12:36:24 PM PDT 24
Finished Jun 13 12:36:28 PM PDT 24
Peak memory 200224 kb
Host smart-950c4adc-0ca4-4c8a-9363-09c919276aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465784201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2465784201
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3174064863
Short name T494
Test name
Test status
Simulation time 230523631 ps
CPU time 1.4 seconds
Started Jun 13 12:36:31 PM PDT 24
Finished Jun 13 12:36:34 PM PDT 24
Peak memory 200780 kb
Host smart-b5adca55-dc86-48a7-a26d-148db28abbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174064863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3174064863
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.454149928
Short name T518
Test name
Test status
Simulation time 2978558355 ps
CPU time 11.33 seconds
Started Jun 13 12:36:47 PM PDT 24
Finished Jun 13 12:36:59 PM PDT 24
Peak memory 209092 kb
Host smart-5a04c587-3423-4270-a7d2-f2ba82ec29c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454149928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.454149928
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3468712362
Short name T214
Test name
Test status
Simulation time 136411901 ps
CPU time 1.85 seconds
Started Jun 13 12:36:14 PM PDT 24
Finished Jun 13 12:36:20 PM PDT 24
Peak memory 200624 kb
Host smart-970ee530-b6ac-4265-9bd9-8c963fbdf9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468712362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3468712362
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1516000553
Short name T124
Test name
Test status
Simulation time 247911035 ps
CPU time 1.42 seconds
Started Jun 13 12:36:23 PM PDT 24
Finished Jun 13 12:36:27 PM PDT 24
Peak memory 200644 kb
Host smart-64b7d81a-b929-4430-a19b-73fa9c7e6cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516000553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1516000553
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1713960256
Short name T222
Test name
Test status
Simulation time 56414386 ps
CPU time 0.77 seconds
Started Jun 13 12:36:02 PM PDT 24
Finished Jun 13 12:36:07 PM PDT 24
Peak memory 200400 kb
Host smart-076a371c-4d13-4390-9782-5effdedfdb18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713960256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1713960256
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.443789826
Short name T429
Test name
Test status
Simulation time 1221087193 ps
CPU time 5.21 seconds
Started Jun 13 12:35:41 PM PDT 24
Finished Jun 13 12:35:47 PM PDT 24
Peak memory 221556 kb
Host smart-a00c2acf-37f4-423d-b240-59d202dce9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443789826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.443789826
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2244970128
Short name T324
Test name
Test status
Simulation time 244276073 ps
CPU time 1.15 seconds
Started Jun 13 12:35:39 PM PDT 24
Finished Jun 13 12:35:42 PM PDT 24
Peak memory 218036 kb
Host smart-f77cf605-5be4-421b-8dac-913610597124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244970128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2244970128
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3137579452
Short name T304
Test name
Test status
Simulation time 237329004 ps
CPU time 0.94 seconds
Started Jun 13 12:36:02 PM PDT 24
Finished Jun 13 12:36:07 PM PDT 24
Peak memory 200412 kb
Host smart-8510f9c3-d3ff-4326-8ba0-034404896b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137579452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3137579452
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2675649345
Short name T25
Test name
Test status
Simulation time 1381829089 ps
CPU time 5.6 seconds
Started Jun 13 12:35:54 PM PDT 24
Finished Jun 13 12:36:05 PM PDT 24
Peak memory 200844 kb
Host smart-1dd631d8-dac2-4e30-af4a-57a214b1803d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675649345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2675649345
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.4036155162
Short name T66
Test name
Test status
Simulation time 9085237098 ps
CPU time 13.45 seconds
Started Jun 13 12:35:50 PM PDT 24
Finished Jun 13 12:36:07 PM PDT 24
Peak memory 218064 kb
Host smart-8026edb3-585a-4831-94d1-a51f292c49a4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036155162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.4036155162
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.354629556
Short name T132
Test name
Test status
Simulation time 173372875 ps
CPU time 1.19 seconds
Started Jun 13 12:35:47 PM PDT 24
Finished Jun 13 12:35:49 PM PDT 24
Peak memory 200608 kb
Host smart-37b39310-79fa-4aab-9782-e3c37618ae86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354629556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.354629556
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1395767350
Short name T283
Test name
Test status
Simulation time 112374081 ps
CPU time 1.2 seconds
Started Jun 13 12:35:39 PM PDT 24
Finished Jun 13 12:35:43 PM PDT 24
Peak memory 200812 kb
Host smart-8804331c-e325-4dc7-9b15-f388a5c012d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395767350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1395767350
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.476262183
Short name T201
Test name
Test status
Simulation time 6122955527 ps
CPU time 22.4 seconds
Started Jun 13 12:36:01 PM PDT 24
Finished Jun 13 12:36:28 PM PDT 24
Peak memory 210232 kb
Host smart-97e40de4-a90b-44e6-8d2f-48cb4063d397
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476262183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.476262183
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3195644920
Short name T186
Test name
Test status
Simulation time 336208726 ps
CPU time 1.88 seconds
Started Jun 13 12:35:59 PM PDT 24
Finished Jun 13 12:36:05 PM PDT 24
Peak memory 200612 kb
Host smart-b02f5d38-9257-4927-97ce-3b02d4654bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195644920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3195644920
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2792360794
Short name T381
Test name
Test status
Simulation time 118108768 ps
CPU time 0.92 seconds
Started Jun 13 12:36:09 PM PDT 24
Finished Jun 13 12:36:13 PM PDT 24
Peak memory 200612 kb
Host smart-a84d4a20-912c-4d57-bcc8-f74f4c76d2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792360794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2792360794
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.999305703
Short name T380
Test name
Test status
Simulation time 70355400 ps
CPU time 0.79 seconds
Started Jun 13 12:36:19 PM PDT 24
Finished Jun 13 12:36:23 PM PDT 24
Peak memory 200388 kb
Host smart-0e310045-e187-4cad-8f3b-14ea7121d394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999305703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.999305703
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.2392368922
Short name T449
Test name
Test status
Simulation time 2348168534 ps
CPU time 8.3 seconds
Started Jun 13 12:36:19 PM PDT 24
Finished Jun 13 12:36:31 PM PDT 24
Peak memory 222524 kb
Host smart-470642e8-dfad-4d1a-85c5-93e60ab0e2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392368922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2392368922
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3591400761
Short name T24
Test name
Test status
Simulation time 243947837 ps
CPU time 1.08 seconds
Started Jun 13 12:36:18 PM PDT 24
Finished Jun 13 12:36:22 PM PDT 24
Peak memory 217996 kb
Host smart-617f7742-2170-4f3b-83f2-c15e1954bc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591400761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3591400761
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3975041088
Short name T271
Test name
Test status
Simulation time 109483977 ps
CPU time 0.74 seconds
Started Jun 13 12:36:21 PM PDT 24
Finished Jun 13 12:36:24 PM PDT 24
Peak memory 200508 kb
Host smart-5f3193f8-e757-430e-b6f1-95b2e4800d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975041088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3975041088
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3762679540
Short name T177
Test name
Test status
Simulation time 730745451 ps
CPU time 3.76 seconds
Started Jun 13 12:36:24 PM PDT 24
Finished Jun 13 12:36:31 PM PDT 24
Peak memory 200748 kb
Host smart-d03ada2c-b287-436e-893b-8c4f09a75b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762679540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3762679540
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1139277445
Short name T422
Test name
Test status
Simulation time 98693730 ps
CPU time 1.03 seconds
Started Jun 13 12:36:17 PM PDT 24
Finished Jun 13 12:36:21 PM PDT 24
Peak memory 200608 kb
Host smart-bf2f29e2-8fc9-4979-814b-2860af8eedfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139277445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1139277445
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.4284660732
Short name T123
Test name
Test status
Simulation time 250318979 ps
CPU time 1.52 seconds
Started Jun 13 12:36:30 PM PDT 24
Finished Jun 13 12:36:33 PM PDT 24
Peak memory 200748 kb
Host smart-9d2010d5-e850-4d7e-bd1d-b0b5c2555e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284660732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.4284660732
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1530701560
Short name T188
Test name
Test status
Simulation time 1122405485 ps
CPU time 5.26 seconds
Started Jun 13 12:36:31 PM PDT 24
Finished Jun 13 12:36:38 PM PDT 24
Peak memory 200804 kb
Host smart-3aceb1ca-be83-4509-a4d6-c406e119d81d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530701560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1530701560
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.2807853526
Short name T328
Test name
Test status
Simulation time 361498843 ps
CPU time 2.27 seconds
Started Jun 13 12:36:33 PM PDT 24
Finished Jun 13 12:36:36 PM PDT 24
Peak memory 200628 kb
Host smart-9a926935-a909-450b-997f-eec3b4b7b570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807853526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2807853526
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.3674786779
Short name T246
Test name
Test status
Simulation time 73747489 ps
CPU time 0.83 seconds
Started Jun 13 12:36:14 PM PDT 24
Finished Jun 13 12:36:18 PM PDT 24
Peak memory 200428 kb
Host smart-a13748b9-7084-4a22-bd9f-7cd71cf696df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674786779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3674786779
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3857836541
Short name T388
Test name
Test status
Simulation time 2166758641 ps
CPU time 8.33 seconds
Started Jun 13 12:36:26 PM PDT 24
Finished Jun 13 12:36:37 PM PDT 24
Peak memory 222440 kb
Host smart-072f0b8f-9e00-4675-9e67-40a60494ad17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857836541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3857836541
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.916330185
Short name T358
Test name
Test status
Simulation time 244118036 ps
CPU time 1.08 seconds
Started Jun 13 12:36:35 PM PDT 24
Finished Jun 13 12:36:37 PM PDT 24
Peak memory 218000 kb
Host smart-bbb9c785-a18e-4dc0-8310-9915ebbab030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916330185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.916330185
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.2499089806
Short name T277
Test name
Test status
Simulation time 227958499 ps
CPU time 0.96 seconds
Started Jun 13 12:36:22 PM PDT 24
Finished Jun 13 12:36:26 PM PDT 24
Peak memory 200420 kb
Host smart-d2634d58-353d-478d-b186-9148bc4fa3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499089806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2499089806
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.913366604
Short name T10
Test name
Test status
Simulation time 971082468 ps
CPU time 4.97 seconds
Started Jun 13 12:36:25 PM PDT 24
Finished Jun 13 12:36:33 PM PDT 24
Peak memory 200804 kb
Host smart-93420926-b33a-4b2f-a87f-eb3f2011c5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913366604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.913366604
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3004817174
Short name T131
Test name
Test status
Simulation time 141576467 ps
CPU time 1.13 seconds
Started Jun 13 12:36:21 PM PDT 24
Finished Jun 13 12:36:25 PM PDT 24
Peak memory 200640 kb
Host smart-5aa8caa8-d7d4-4fe1-8d13-886aff6573c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004817174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3004817174
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2648045830
Short name T524
Test name
Test status
Simulation time 114031448 ps
CPU time 1.23 seconds
Started Jun 13 12:36:41 PM PDT 24
Finished Jun 13 12:36:43 PM PDT 24
Peak memory 200820 kb
Host smart-48b0f682-e825-433b-b2c1-eebb83a62a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648045830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2648045830
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.258186737
Short name T223
Test name
Test status
Simulation time 2331755688 ps
CPU time 10.16 seconds
Started Jun 13 12:36:23 PM PDT 24
Finished Jun 13 12:36:35 PM PDT 24
Peak memory 200804 kb
Host smart-f837ac3d-aecf-4648-bdcd-2d77b3c2b674
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258186737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.258186737
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3272962005
Short name T452
Test name
Test status
Simulation time 120499455 ps
CPU time 1.53 seconds
Started Jun 13 12:36:17 PM PDT 24
Finished Jun 13 12:36:22 PM PDT 24
Peak memory 200680 kb
Host smart-0fcf4dd1-1f46-4cc1-bbc8-dc6f8d95ffe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272962005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3272962005
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3116238202
Short name T531
Test name
Test status
Simulation time 70659497 ps
CPU time 0.75 seconds
Started Jun 13 12:36:18 PM PDT 24
Finished Jun 13 12:36:22 PM PDT 24
Peak memory 200696 kb
Host smart-d438289f-7bf7-43f6-b7ef-51581ffaa067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116238202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3116238202
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.485629010
Short name T487
Test name
Test status
Simulation time 58987960 ps
CPU time 0.75 seconds
Started Jun 13 12:36:34 PM PDT 24
Finished Jun 13 12:36:36 PM PDT 24
Peak memory 200424 kb
Host smart-390466a0-6b13-4d87-93f8-c1044666839a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485629010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.485629010
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1738852322
Short name T38
Test name
Test status
Simulation time 1231961415 ps
CPU time 5.32 seconds
Started Jun 13 12:36:29 PM PDT 24
Finished Jun 13 12:36:36 PM PDT 24
Peak memory 222460 kb
Host smart-5aa26940-9085-40f7-8141-7f9d3bd0f796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738852322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1738852322
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.4012781194
Short name T45
Test name
Test status
Simulation time 243360103 ps
CPU time 1.03 seconds
Started Jun 13 12:36:27 PM PDT 24
Finished Jun 13 12:36:30 PM PDT 24
Peak memory 217976 kb
Host smart-2d72ee90-1029-4e5e-9b9a-a066851df5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012781194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.4012781194
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1406215592
Short name T16
Test name
Test status
Simulation time 131446142 ps
CPU time 0.85 seconds
Started Jun 13 12:36:27 PM PDT 24
Finished Jun 13 12:36:30 PM PDT 24
Peak memory 200488 kb
Host smart-21d57a25-0c69-4153-b03c-6080d4a47de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406215592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1406215592
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.99535089
Short name T178
Test name
Test status
Simulation time 1522756911 ps
CPU time 5.92 seconds
Started Jun 13 12:36:24 PM PDT 24
Finished Jun 13 12:36:33 PM PDT 24
Peak memory 200808 kb
Host smart-ced24463-e4d3-4e7d-9a66-61d78bd5a411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99535089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.99535089
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.984248933
Short name T426
Test name
Test status
Simulation time 98400131 ps
CPU time 0.95 seconds
Started Jun 13 12:36:21 PM PDT 24
Finished Jun 13 12:36:24 PM PDT 24
Peak memory 200680 kb
Host smart-376b7f9e-cd00-4b96-99a2-4547703db8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984248933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.984248933
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2364445057
Short name T285
Test name
Test status
Simulation time 111448042 ps
CPU time 1.15 seconds
Started Jun 13 12:36:17 PM PDT 24
Finished Jun 13 12:36:22 PM PDT 24
Peak memory 200864 kb
Host smart-b9545460-a720-41b2-a07d-3170289d994e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364445057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2364445057
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2116749629
Short name T459
Test name
Test status
Simulation time 8253755403 ps
CPU time 31.63 seconds
Started Jun 13 12:36:21 PM PDT 24
Finished Jun 13 12:36:55 PM PDT 24
Peak memory 209120 kb
Host smart-769730c6-0236-493d-bf73-5de650c3dc6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116749629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2116749629
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3103805171
Short name T404
Test name
Test status
Simulation time 388402257 ps
CPU time 2.43 seconds
Started Jun 13 12:36:35 PM PDT 24
Finished Jun 13 12:36:38 PM PDT 24
Peak memory 200624 kb
Host smart-33f47938-58f5-43d2-8fd2-44a9efbfc453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103805171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3103805171
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.141536343
Short name T294
Test name
Test status
Simulation time 103526469 ps
CPU time 0.87 seconds
Started Jun 13 12:36:29 PM PDT 24
Finished Jun 13 12:36:31 PM PDT 24
Peak memory 200680 kb
Host smart-cdfb01ab-b228-4b7c-b629-f34659c41b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141536343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.141536343
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.4094133635
Short name T359
Test name
Test status
Simulation time 79605353 ps
CPU time 0.78 seconds
Started Jun 13 12:36:25 PM PDT 24
Finished Jun 13 12:36:29 PM PDT 24
Peak memory 200372 kb
Host smart-4de52f77-5b69-4449-a8a4-cf990835cf2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094133635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.4094133635
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3273118421
Short name T468
Test name
Test status
Simulation time 1228841279 ps
CPU time 6.05 seconds
Started Jun 13 12:36:40 PM PDT 24
Finished Jun 13 12:36:47 PM PDT 24
Peak memory 218448 kb
Host smart-bd4896e2-8c83-4d08-8834-52e739c024a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273118421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3273118421
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1371745814
Short name T282
Test name
Test status
Simulation time 244371272 ps
CPU time 1.05 seconds
Started Jun 13 12:36:32 PM PDT 24
Finished Jun 13 12:36:34 PM PDT 24
Peak memory 218088 kb
Host smart-e0f1415c-74db-46f1-8b07-1fe47a4e7937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371745814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1371745814
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.275889446
Short name T15
Test name
Test status
Simulation time 195290462 ps
CPU time 0.96 seconds
Started Jun 13 12:36:15 PM PDT 24
Finished Jun 13 12:36:20 PM PDT 24
Peak memory 200412 kb
Host smart-01e3c88f-1bec-4557-a102-a441e5ddc4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275889446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.275889446
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3764706583
Short name T502
Test name
Test status
Simulation time 871996666 ps
CPU time 4.25 seconds
Started Jun 13 12:36:16 PM PDT 24
Finished Jun 13 12:36:24 PM PDT 24
Peak memory 200844 kb
Host smart-2ea6f43c-425f-4282-b98d-6452c91c518f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764706583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3764706583
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.54701067
Short name T5
Test name
Test status
Simulation time 186279534 ps
CPU time 1.18 seconds
Started Jun 13 12:36:14 PM PDT 24
Finished Jun 13 12:36:19 PM PDT 24
Peak memory 200708 kb
Host smart-9bd7ed81-cd64-480d-9f00-483c52e7e2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54701067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.54701067
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3061292963
Short name T191
Test name
Test status
Simulation time 253833620 ps
CPU time 1.6 seconds
Started Jun 13 12:36:26 PM PDT 24
Finished Jun 13 12:36:30 PM PDT 24
Peak memory 200840 kb
Host smart-f3a5c310-8215-4b70-9695-d30bfe339bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061292963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3061292963
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.349411057
Short name T461
Test name
Test status
Simulation time 10677153848 ps
CPU time 35.68 seconds
Started Jun 13 12:36:27 PM PDT 24
Finished Jun 13 12:37:05 PM PDT 24
Peak memory 217244 kb
Host smart-82d13fc5-b42b-4f14-9107-c6c31cb9fabd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349411057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.349411057
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1164300158
Short name T360
Test name
Test status
Simulation time 246155534 ps
CPU time 1.71 seconds
Started Jun 13 12:36:19 PM PDT 24
Finished Jun 13 12:36:24 PM PDT 24
Peak memory 200584 kb
Host smart-8b977dda-86d3-4a09-96cb-5972206b5e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164300158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1164300158
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2885904932
Short name T511
Test name
Test status
Simulation time 142750000 ps
CPU time 1.11 seconds
Started Jun 13 12:36:44 PM PDT 24
Finished Jun 13 12:36:46 PM PDT 24
Peak memory 200712 kb
Host smart-f1450c1b-ffb5-4952-a54a-7364bc90363c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885904932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2885904932
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2600709113
Short name T149
Test name
Test status
Simulation time 77870139 ps
CPU time 0.81 seconds
Started Jun 13 12:36:37 PM PDT 24
Finished Jun 13 12:36:39 PM PDT 24
Peak memory 200436 kb
Host smart-e737d5d5-fe98-41d6-b487-91d68bf81735
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600709113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2600709113
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.270147852
Short name T41
Test name
Test status
Simulation time 1901918435 ps
CPU time 7.45 seconds
Started Jun 13 12:36:24 PM PDT 24
Finished Jun 13 12:36:35 PM PDT 24
Peak memory 218364 kb
Host smart-5982cf90-7e60-463a-9d2f-78e85f6ccd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270147852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.270147852
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.758694337
Short name T311
Test name
Test status
Simulation time 244374506 ps
CPU time 1.06 seconds
Started Jun 13 12:36:34 PM PDT 24
Finished Jun 13 12:36:36 PM PDT 24
Peak memory 218072 kb
Host smart-cea8ae29-b7fa-4854-afa7-3dede9ad1ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758694337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.758694337
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2018373768
Short name T347
Test name
Test status
Simulation time 147701636 ps
CPU time 0.81 seconds
Started Jun 13 12:36:37 PM PDT 24
Finished Jun 13 12:36:39 PM PDT 24
Peak memory 200456 kb
Host smart-cf42898f-4227-4015-a145-0da7bc247b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018373768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2018373768
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2415475847
Short name T331
Test name
Test status
Simulation time 1671540999 ps
CPU time 6.02 seconds
Started Jun 13 12:36:36 PM PDT 24
Finished Jun 13 12:36:43 PM PDT 24
Peak memory 200884 kb
Host smart-61f22a9d-c6d6-47c8-8d52-5ed24e1e57ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415475847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2415475847
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3694634093
Short name T344
Test name
Test status
Simulation time 176200522 ps
CPU time 1.16 seconds
Started Jun 13 12:36:42 PM PDT 24
Finished Jun 13 12:36:44 PM PDT 24
Peak memory 200648 kb
Host smart-bdc56bae-0ad9-4894-b6f2-1c3994efe4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694634093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3694634093
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3537503688
Short name T479
Test name
Test status
Simulation time 249539876 ps
CPU time 1.56 seconds
Started Jun 13 12:36:13 PM PDT 24
Finished Jun 13 12:36:18 PM PDT 24
Peak memory 200776 kb
Host smart-34cfca82-d7ff-4b5b-8e30-9e9051a5288d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537503688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3537503688
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1853269063
Short name T266
Test name
Test status
Simulation time 9395308986 ps
CPU time 40.17 seconds
Started Jun 13 12:36:38 PM PDT 24
Finished Jun 13 12:37:19 PM PDT 24
Peak memory 209132 kb
Host smart-8212db8a-e565-4a15-8fe0-f51e91d7209f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853269063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1853269063
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3192960109
Short name T11
Test name
Test status
Simulation time 134030804 ps
CPU time 1.56 seconds
Started Jun 13 12:36:27 PM PDT 24
Finished Jun 13 12:36:31 PM PDT 24
Peak memory 208892 kb
Host smart-786e1eb5-ce5d-49f4-a584-1821ddfc1d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192960109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3192960109
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3920548942
Short name T170
Test name
Test status
Simulation time 74537344 ps
CPU time 0.81 seconds
Started Jun 13 12:36:26 PM PDT 24
Finished Jun 13 12:36:30 PM PDT 24
Peak memory 200632 kb
Host smart-5dbe7c88-61b2-4108-a4cb-af3a4b03c198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920548942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3920548942
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2644156818
Short name T365
Test name
Test status
Simulation time 76571995 ps
CPU time 0.81 seconds
Started Jun 13 12:36:19 PM PDT 24
Finished Jun 13 12:36:23 PM PDT 24
Peak memory 200436 kb
Host smart-ca46f847-2cdc-4ccf-b7df-52323048d8f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644156818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2644156818
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1507133276
Short name T49
Test name
Test status
Simulation time 2378975689 ps
CPU time 8.27 seconds
Started Jun 13 12:36:30 PM PDT 24
Finished Jun 13 12:36:40 PM PDT 24
Peak memory 222404 kb
Host smart-198f495d-b4c2-42bf-b5e3-85e9c5eafd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507133276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1507133276
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3225142284
Short name T1
Test name
Test status
Simulation time 243906062 ps
CPU time 1.09 seconds
Started Jun 13 12:36:24 PM PDT 24
Finished Jun 13 12:36:29 PM PDT 24
Peak memory 217992 kb
Host smart-a215087b-1fb1-452f-9f84-6155a2e2cebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225142284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3225142284
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1645070710
Short name T314
Test name
Test status
Simulation time 239375966 ps
CPU time 0.99 seconds
Started Jun 13 12:36:35 PM PDT 24
Finished Jun 13 12:36:37 PM PDT 24
Peak memory 200396 kb
Host smart-76f775d6-68d6-47b5-899d-3fd4a3996587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645070710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1645070710
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1514700311
Short name T383
Test name
Test status
Simulation time 850619161 ps
CPU time 4.18 seconds
Started Jun 13 12:36:47 PM PDT 24
Finished Jun 13 12:36:53 PM PDT 24
Peak memory 200892 kb
Host smart-6490ef3e-77a4-46f6-b3a2-ecaf4445d320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514700311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1514700311
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3903502322
Short name T225
Test name
Test status
Simulation time 100624866 ps
CPU time 0.94 seconds
Started Jun 13 12:36:55 PM PDT 24
Finished Jun 13 12:36:58 PM PDT 24
Peak memory 200664 kb
Host smart-36e51dc0-faa1-4828-afce-aafe0d342332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903502322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3903502322
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.563954906
Short name T207
Test name
Test status
Simulation time 115286978 ps
CPU time 1.2 seconds
Started Jun 13 12:36:35 PM PDT 24
Finished Jun 13 12:36:38 PM PDT 24
Peak memory 200848 kb
Host smart-bd321e74-7262-4d95-9277-3e50f10b3cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563954906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.563954906
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3648951633
Short name T500
Test name
Test status
Simulation time 9186358693 ps
CPU time 29.6 seconds
Started Jun 13 12:36:30 PM PDT 24
Finished Jun 13 12:37:01 PM PDT 24
Peak memory 209096 kb
Host smart-92cf6685-6e8d-46f0-91a0-20b8c7b9ff3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648951633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3648951633
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3342373840
Short name T392
Test name
Test status
Simulation time 351955713 ps
CPU time 2.41 seconds
Started Jun 13 12:36:32 PM PDT 24
Finished Jun 13 12:36:36 PM PDT 24
Peak memory 200588 kb
Host smart-bbbf952e-20cc-4849-84c7-ce2406b5319c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342373840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3342373840
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3162643471
Short name T142
Test name
Test status
Simulation time 140197576 ps
CPU time 1.11 seconds
Started Jun 13 12:36:52 PM PDT 24
Finished Jun 13 12:36:57 PM PDT 24
Peak memory 200708 kb
Host smart-9950e3f6-8d93-4d11-8683-c1ae3818c4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162643471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3162643471
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2904701427
Short name T519
Test name
Test status
Simulation time 72952131 ps
CPU time 0.79 seconds
Started Jun 13 12:36:43 PM PDT 24
Finished Jun 13 12:36:45 PM PDT 24
Peak memory 200428 kb
Host smart-11b2b663-18c7-472e-9dfb-cca1570d406e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904701427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2904701427
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1175583475
Short name T47
Test name
Test status
Simulation time 1881830148 ps
CPU time 6.44 seconds
Started Jun 13 12:36:52 PM PDT 24
Finished Jun 13 12:37:02 PM PDT 24
Peak memory 222328 kb
Host smart-784de49f-d58a-40ad-8a87-586a78143b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175583475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1175583475
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.873149387
Short name T195
Test name
Test status
Simulation time 244117852 ps
CPU time 1.09 seconds
Started Jun 13 12:36:34 PM PDT 24
Finished Jun 13 12:36:36 PM PDT 24
Peak memory 218044 kb
Host smart-b7079723-2bbe-439b-aefc-df5a68d5477a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873149387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.873149387
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.2702075879
Short name T371
Test name
Test status
Simulation time 132402302 ps
CPU time 0.85 seconds
Started Jun 13 12:36:29 PM PDT 24
Finished Jun 13 12:36:32 PM PDT 24
Peak memory 200532 kb
Host smart-a591f4bb-6052-4742-867a-536a0ab11619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702075879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.2702075879
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3215259546
Short name T4
Test name
Test status
Simulation time 742252176 ps
CPU time 3.79 seconds
Started Jun 13 12:36:23 PM PDT 24
Finished Jun 13 12:36:30 PM PDT 24
Peak memory 200780 kb
Host smart-3159a28f-40cb-44d9-874b-bb4b383693ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215259546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3215259546
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2056779938
Short name T525
Test name
Test status
Simulation time 114614900 ps
CPU time 1.03 seconds
Started Jun 13 12:36:21 PM PDT 24
Finished Jun 13 12:36:24 PM PDT 24
Peak memory 200684 kb
Host smart-1bf2e423-7d8f-4546-96a9-1668e5c1fed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056779938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2056779938
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2581386430
Short name T7
Test name
Test status
Simulation time 120815215 ps
CPU time 1.24 seconds
Started Jun 13 12:36:45 PM PDT 24
Finished Jun 13 12:36:47 PM PDT 24
Peak memory 200860 kb
Host smart-ce6db4ee-be92-4939-9e2d-2bc1b171acc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581386430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2581386430
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3526036393
Short name T173
Test name
Test status
Simulation time 2379501205 ps
CPU time 8.96 seconds
Started Jun 13 12:36:22 PM PDT 24
Finished Jun 13 12:36:34 PM PDT 24
Peak memory 208980 kb
Host smart-085fa827-9cd1-4b7d-9843-c1b9fed2104d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526036393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3526036393
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.855147753
Short name T395
Test name
Test status
Simulation time 154116068 ps
CPU time 1.91 seconds
Started Jun 13 12:36:31 PM PDT 24
Finished Jun 13 12:36:35 PM PDT 24
Peak memory 200624 kb
Host smart-9a7bb7ba-4f83-4944-b66b-93bd2538169b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855147753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.855147753
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.288253575
Short name T485
Test name
Test status
Simulation time 90113048 ps
CPU time 0.84 seconds
Started Jun 13 12:36:30 PM PDT 24
Finished Jun 13 12:36:37 PM PDT 24
Peak memory 200696 kb
Host smart-4962e1ad-c7c3-4f6a-b1f9-38a1460e4ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288253575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.288253575
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.91560374
Short name T375
Test name
Test status
Simulation time 61688632 ps
CPU time 0.72 seconds
Started Jun 13 12:36:26 PM PDT 24
Finished Jun 13 12:36:29 PM PDT 24
Peak memory 200396 kb
Host smart-d6c761b7-f3b8-4e69-ae73-b5777ebd462a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91560374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.91560374
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1583868955
Short name T26
Test name
Test status
Simulation time 2357640953 ps
CPU time 8.56 seconds
Started Jun 13 12:36:30 PM PDT 24
Finished Jun 13 12:36:41 PM PDT 24
Peak memory 218324 kb
Host smart-9076c6b2-59e7-493c-ad20-a06c5d85637e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583868955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1583868955
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.505865003
Short name T252
Test name
Test status
Simulation time 244455243 ps
CPU time 1.11 seconds
Started Jun 13 12:36:45 PM PDT 24
Finished Jun 13 12:36:47 PM PDT 24
Peak memory 217988 kb
Host smart-6ac6c25c-9346-429d-9b66-28822beded91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505865003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.505865003
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1352608156
Short name T206
Test name
Test status
Simulation time 205273839 ps
CPU time 0.93 seconds
Started Jun 13 12:36:42 PM PDT 24
Finished Jun 13 12:36:43 PM PDT 24
Peak memory 200536 kb
Host smart-5ff3ad16-b887-4dec-9aa9-6b8116340488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352608156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1352608156
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1187242645
Short name T151
Test name
Test status
Simulation time 1557707650 ps
CPU time 5.98 seconds
Started Jun 13 12:36:43 PM PDT 24
Finished Jun 13 12:36:50 PM PDT 24
Peak memory 200848 kb
Host smart-c64face0-7f49-4662-b823-88ac14c95e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187242645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1187242645
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3858880573
Short name T493
Test name
Test status
Simulation time 143778172 ps
CPU time 1.12 seconds
Started Jun 13 12:36:42 PM PDT 24
Finished Jun 13 12:36:44 PM PDT 24
Peak memory 200648 kb
Host smart-590adbda-1f64-4dca-b441-370f2c4a0685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858880573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3858880573
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.3709098999
Short name T443
Test name
Test status
Simulation time 254747882 ps
CPU time 1.57 seconds
Started Jun 13 12:36:35 PM PDT 24
Finished Jun 13 12:36:37 PM PDT 24
Peak memory 200780 kb
Host smart-33c3fa59-0d20-4711-8e26-6021b0431158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709098999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.3709098999
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.1070204750
Short name T30
Test name
Test status
Simulation time 2072051541 ps
CPU time 9.33 seconds
Started Jun 13 12:36:37 PM PDT 24
Finished Jun 13 12:36:48 PM PDT 24
Peak memory 209036 kb
Host smart-25fcfef1-e3d5-4145-93cc-99c469c7f1ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070204750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1070204750
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.541713597
Short name T68
Test name
Test status
Simulation time 113198865 ps
CPU time 1.53 seconds
Started Jun 13 12:36:49 PM PDT 24
Finished Jun 13 12:36:54 PM PDT 24
Peak memory 200712 kb
Host smart-efbfa59f-6ceb-454a-a5fc-f861fbb3af3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541713597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.541713597
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2209218836
Short name T436
Test name
Test status
Simulation time 89164491 ps
CPU time 0.84 seconds
Started Jun 13 12:36:32 PM PDT 24
Finished Jun 13 12:36:34 PM PDT 24
Peak memory 199716 kb
Host smart-4b7df515-76cd-46b1-8c92-d54b07136307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209218836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2209218836
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2323011660
Short name T406
Test name
Test status
Simulation time 59787976 ps
CPU time 0.74 seconds
Started Jun 13 12:36:30 PM PDT 24
Finished Jun 13 12:36:32 PM PDT 24
Peak memory 200452 kb
Host smart-5d747c2e-5f34-42ac-8bc2-4423589d873d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323011660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2323011660
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2311630336
Short name T350
Test name
Test status
Simulation time 1231663985 ps
CPU time 5.89 seconds
Started Jun 13 12:36:43 PM PDT 24
Finished Jun 13 12:36:50 PM PDT 24
Peak memory 222428 kb
Host smart-945acea5-1a20-4037-839f-2463a3db4d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311630336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2311630336
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.45693070
Short name T457
Test name
Test status
Simulation time 244832517 ps
CPU time 1.06 seconds
Started Jun 13 12:36:34 PM PDT 24
Finished Jun 13 12:36:36 PM PDT 24
Peak memory 218092 kb
Host smart-b2a2f430-f626-40c9-a8ae-9f8abc17a4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45693070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.45693070
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2309587053
Short name T313
Test name
Test status
Simulation time 105828659 ps
CPU time 0.83 seconds
Started Jun 13 12:36:42 PM PDT 24
Finished Jun 13 12:36:44 PM PDT 24
Peak memory 200540 kb
Host smart-0d467274-8d49-44c2-bfc2-bc13e70bdee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309587053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2309587053
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2437595614
Short name T435
Test name
Test status
Simulation time 1931332446 ps
CPU time 7.05 seconds
Started Jun 13 12:36:37 PM PDT 24
Finished Jun 13 12:36:45 PM PDT 24
Peak memory 200784 kb
Host smart-99942791-34b7-4098-b56a-5e5b77ec9dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437595614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2437595614
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3902958220
Short name T369
Test name
Test status
Simulation time 97037582 ps
CPU time 0.97 seconds
Started Jun 13 12:36:23 PM PDT 24
Finished Jun 13 12:36:27 PM PDT 24
Peak memory 200620 kb
Host smart-0816f194-d0d9-437c-a09d-40fbb69f1633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902958220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3902958220
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.4190694979
Short name T399
Test name
Test status
Simulation time 253207685 ps
CPU time 1.59 seconds
Started Jun 13 12:36:40 PM PDT 24
Finished Jun 13 12:36:43 PM PDT 24
Peak memory 200844 kb
Host smart-b60edc36-1aaf-4ba0-bee6-90d56617d8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190694979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.4190694979
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.420947970
Short name T90
Test name
Test status
Simulation time 3340772401 ps
CPU time 16.24 seconds
Started Jun 13 12:36:54 PM PDT 24
Finished Jun 13 12:37:16 PM PDT 24
Peak memory 201080 kb
Host smart-0ac94d57-35d0-4db3-977a-9f84fa95611d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420947970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.420947970
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.4006833031
Short name T6
Test name
Test status
Simulation time 498487153 ps
CPU time 2.6 seconds
Started Jun 13 12:36:36 PM PDT 24
Finished Jun 13 12:36:40 PM PDT 24
Peak memory 200696 kb
Host smart-c2ad243e-e438-4946-bcfa-068475118788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006833031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.4006833031
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1461531151
Short name T239
Test name
Test status
Simulation time 114815432 ps
CPU time 1.11 seconds
Started Jun 13 12:36:27 PM PDT 24
Finished Jun 13 12:36:30 PM PDT 24
Peak memory 200632 kb
Host smart-8bca2349-ff68-4cf0-b12c-d0a083ced40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461531151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1461531151
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.2689566677
Short name T329
Test name
Test status
Simulation time 67038876 ps
CPU time 0.76 seconds
Started Jun 13 12:36:37 PM PDT 24
Finished Jun 13 12:36:39 PM PDT 24
Peak memory 200508 kb
Host smart-2f2b3a36-fb79-4049-96bf-45f836310925
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689566677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2689566677
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.720817456
Short name T42
Test name
Test status
Simulation time 1223920739 ps
CPU time 5.48 seconds
Started Jun 13 12:36:42 PM PDT 24
Finished Jun 13 12:36:48 PM PDT 24
Peak memory 218424 kb
Host smart-261dab84-2955-4bbb-9bfb-9fa74c324875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720817456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.720817456
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2943814570
Short name T140
Test name
Test status
Simulation time 243833677 ps
CPU time 1.17 seconds
Started Jun 13 12:37:07 PM PDT 24
Finished Jun 13 12:37:10 PM PDT 24
Peak memory 218076 kb
Host smart-3be1b5cf-82af-4ef0-9edc-7d68fc297df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943814570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2943814570
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.535399837
Short name T310
Test name
Test status
Simulation time 104485733 ps
CPU time 0.77 seconds
Started Jun 13 12:36:50 PM PDT 24
Finished Jun 13 12:36:54 PM PDT 24
Peak memory 200508 kb
Host smart-4edaba71-1219-4c1b-882e-fcc5d3926828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535399837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.535399837
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2702113799
Short name T470
Test name
Test status
Simulation time 1359290364 ps
CPU time 5.35 seconds
Started Jun 13 12:36:29 PM PDT 24
Finished Jun 13 12:36:36 PM PDT 24
Peak memory 200800 kb
Host smart-ad645928-5347-489d-bb87-c89aa88e241d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702113799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2702113799
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1730456047
Short name T12
Test name
Test status
Simulation time 142985113 ps
CPU time 1.12 seconds
Started Jun 13 12:36:36 PM PDT 24
Finished Jun 13 12:36:38 PM PDT 24
Peak memory 200604 kb
Host smart-ac0de1f0-2805-4eb5-9c15-b081d8d21ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730456047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1730456047
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.4142756632
Short name T348
Test name
Test status
Simulation time 200833614 ps
CPU time 1.39 seconds
Started Jun 13 12:36:42 PM PDT 24
Finished Jun 13 12:36:44 PM PDT 24
Peak memory 200688 kb
Host smart-b362637a-3205-448f-ae66-b4f811dd22ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142756632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.4142756632
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.999616636
Short name T91
Test name
Test status
Simulation time 3806307499 ps
CPU time 17.88 seconds
Started Jun 13 12:36:37 PM PDT 24
Finished Jun 13 12:36:56 PM PDT 24
Peak memory 209160 kb
Host smart-8f29694e-3f97-43c9-b668-d04db92602e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999616636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.999616636
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3701928253
Short name T505
Test name
Test status
Simulation time 294192534 ps
CPU time 1.96 seconds
Started Jun 13 12:36:41 PM PDT 24
Finished Jun 13 12:36:44 PM PDT 24
Peak memory 200592 kb
Host smart-701f3be0-b7a6-484f-9e3f-7feadb92c582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701928253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3701928253
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3417546535
Short name T353
Test name
Test status
Simulation time 70440425 ps
CPU time 0.85 seconds
Started Jun 13 12:36:46 PM PDT 24
Finished Jun 13 12:36:48 PM PDT 24
Peak memory 200696 kb
Host smart-f07627c9-d80a-4370-aea6-85ba0cf4d8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417546535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3417546535
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2960874792
Short name T50
Test name
Test status
Simulation time 70623513 ps
CPU time 0.77 seconds
Started Jun 13 12:35:59 PM PDT 24
Finished Jun 13 12:36:05 PM PDT 24
Peak memory 200484 kb
Host smart-5812b5f7-01cf-4455-8e3b-e9ae3e7639fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960874792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2960874792
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2546657890
Short name T43
Test name
Test status
Simulation time 1890509075 ps
CPU time 6.81 seconds
Started Jun 13 12:35:48 PM PDT 24
Finished Jun 13 12:35:55 PM PDT 24
Peak memory 218400 kb
Host smart-2539a7e4-13be-4c8b-a9c8-7f8992cf1ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546657890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2546657890
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3922745133
Short name T268
Test name
Test status
Simulation time 243579295 ps
CPU time 1.18 seconds
Started Jun 13 12:35:43 PM PDT 24
Finished Jun 13 12:35:45 PM PDT 24
Peak memory 217980 kb
Host smart-4d394f6a-7348-412d-903b-e432b8718a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922745133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3922745133
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.658891377
Short name T275
Test name
Test status
Simulation time 141733992 ps
CPU time 0.81 seconds
Started Jun 13 12:35:43 PM PDT 24
Finished Jun 13 12:35:44 PM PDT 24
Peak memory 200456 kb
Host smart-a35bb628-f5af-4d9c-ac1d-fc3b184d56a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658891377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.658891377
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1071025497
Short name T270
Test name
Test status
Simulation time 2143754262 ps
CPU time 7.51 seconds
Started Jun 13 12:35:54 PM PDT 24
Finished Jun 13 12:36:06 PM PDT 24
Peak memory 200756 kb
Host smart-de020718-e480-409d-9d1a-9ae27e923416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071025497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1071025497
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.611875362
Short name T59
Test name
Test status
Simulation time 8348846001 ps
CPU time 12.85 seconds
Started Jun 13 12:36:07 PM PDT 24
Finished Jun 13 12:36:22 PM PDT 24
Peak memory 217540 kb
Host smart-1d8efa14-b03a-4398-b4a8-cf8be3a5325a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611875362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.611875362
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2635021815
Short name T133
Test name
Test status
Simulation time 95691107 ps
CPU time 1 seconds
Started Jun 13 12:35:59 PM PDT 24
Finished Jun 13 12:36:05 PM PDT 24
Peak memory 200684 kb
Host smart-1c572c75-7be7-416a-b2dd-8776cbe8ceaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635021815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2635021815
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1547285724
Short name T3
Test name
Test status
Simulation time 191401695 ps
CPU time 1.38 seconds
Started Jun 13 12:35:54 PM PDT 24
Finished Jun 13 12:36:00 PM PDT 24
Peak memory 200848 kb
Host smart-e15213c0-738f-4482-99dc-182ec5745662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547285724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1547285724
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.639411239
Short name T76
Test name
Test status
Simulation time 1045072937 ps
CPU time 5.25 seconds
Started Jun 13 12:35:40 PM PDT 24
Finished Jun 13 12:35:47 PM PDT 24
Peak memory 200804 kb
Host smart-0d423b2f-e39a-437a-83d2-b4ec9e93ba5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639411239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.639411239
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1796126069
Short name T176
Test name
Test status
Simulation time 409700415 ps
CPU time 2.4 seconds
Started Jun 13 12:35:38 PM PDT 24
Finished Jun 13 12:35:43 PM PDT 24
Peak memory 200672 kb
Host smart-2ff399fc-6147-488c-a336-644daf3bc1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796126069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1796126069
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2982040498
Short name T125
Test name
Test status
Simulation time 260745694 ps
CPU time 1.4 seconds
Started Jun 13 12:35:38 PM PDT 24
Finished Jun 13 12:35:42 PM PDT 24
Peak memory 200644 kb
Host smart-5de48658-01a2-40e6-ae1a-7ca9e59f88a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982040498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2982040498
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3626776643
Short name T200
Test name
Test status
Simulation time 62120636 ps
CPU time 0.74 seconds
Started Jun 13 12:36:35 PM PDT 24
Finished Jun 13 12:36:36 PM PDT 24
Peak memory 200460 kb
Host smart-5049eafa-2548-4a83-aa39-169ee7b7e103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626776643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3626776643
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.3899642143
Short name T253
Test name
Test status
Simulation time 2366680633 ps
CPU time 8.58 seconds
Started Jun 13 12:36:47 PM PDT 24
Finished Jun 13 12:36:58 PM PDT 24
Peak memory 221988 kb
Host smart-6d655e9d-8b36-4efa-bf21-306bfaf8a8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899642143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3899642143
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.976257422
Short name T254
Test name
Test status
Simulation time 244654413 ps
CPU time 1.11 seconds
Started Jun 13 12:36:42 PM PDT 24
Finished Jun 13 12:36:44 PM PDT 24
Peak memory 218012 kb
Host smart-286bce21-0f8b-4662-9932-63a2e2c0201a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976257422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.976257422
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.19233581
Short name T157
Test name
Test status
Simulation time 110197925 ps
CPU time 0.77 seconds
Started Jun 13 12:36:39 PM PDT 24
Finished Jun 13 12:36:40 PM PDT 24
Peak memory 200512 kb
Host smart-9c85e847-6cd1-4817-8c63-84f78365871d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19233581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.19233581
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2091161494
Short name T514
Test name
Test status
Simulation time 1528837401 ps
CPU time 6.24 seconds
Started Jun 13 12:36:45 PM PDT 24
Finished Jun 13 12:36:52 PM PDT 24
Peak memory 200852 kb
Host smart-fde9a0f3-75f8-4218-a8df-88850e3119b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091161494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2091161494
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2645763798
Short name T182
Test name
Test status
Simulation time 173282908 ps
CPU time 1.21 seconds
Started Jun 13 12:36:41 PM PDT 24
Finished Jun 13 12:36:43 PM PDT 24
Peak memory 200664 kb
Host smart-1d18db76-bead-4c42-b810-cf752a03b415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645763798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2645763798
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2077691114
Short name T248
Test name
Test status
Simulation time 215663784 ps
CPU time 1.54 seconds
Started Jun 13 12:36:37 PM PDT 24
Finished Jun 13 12:36:40 PM PDT 24
Peak memory 200872 kb
Host smart-4db8b7ca-de6b-4b97-bc4b-2d0a46c281a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077691114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2077691114
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.1578972975
Short name T120
Test name
Test status
Simulation time 16298454946 ps
CPU time 52.62 seconds
Started Jun 13 12:36:45 PM PDT 24
Finished Jun 13 12:37:38 PM PDT 24
Peak memory 200920 kb
Host smart-27054623-5945-440f-b3a5-414ace12fc27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578972975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1578972975
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.398806688
Short name T261
Test name
Test status
Simulation time 130695590 ps
CPU time 1.66 seconds
Started Jun 13 12:36:50 PM PDT 24
Finished Jun 13 12:36:55 PM PDT 24
Peak memory 200656 kb
Host smart-6943d530-5269-43d1-afb9-b41d103b3e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398806688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.398806688
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2384685959
Short name T340
Test name
Test status
Simulation time 62321464 ps
CPU time 0.76 seconds
Started Jun 13 12:36:41 PM PDT 24
Finished Jun 13 12:36:43 PM PDT 24
Peak memory 200696 kb
Host smart-75381200-544c-4531-b44f-dd6c3c3a0007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384685959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2384685959
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1546565857
Short name T141
Test name
Test status
Simulation time 84402442 ps
CPU time 0.91 seconds
Started Jun 13 12:36:42 PM PDT 24
Finished Jun 13 12:36:44 PM PDT 24
Peak memory 200460 kb
Host smart-6276be17-1495-4600-ab52-285c1ca3f417
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546565857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1546565857
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1022609178
Short name T259
Test name
Test status
Simulation time 1890542879 ps
CPU time 6.82 seconds
Started Jun 13 12:36:44 PM PDT 24
Finished Jun 13 12:36:51 PM PDT 24
Peak memory 218376 kb
Host smart-7e7334b9-1d44-4654-9261-365d16b83b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022609178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1022609178
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2229000311
Short name T234
Test name
Test status
Simulation time 244490251 ps
CPU time 1.19 seconds
Started Jun 13 12:36:50 PM PDT 24
Finished Jun 13 12:36:55 PM PDT 24
Peak memory 218060 kb
Host smart-df0d636f-3e70-41e3-83ca-b321773b6a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229000311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2229000311
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.4063429588
Short name T405
Test name
Test status
Simulation time 139498550 ps
CPU time 0.84 seconds
Started Jun 13 12:36:52 PM PDT 24
Finished Jun 13 12:36:56 PM PDT 24
Peak memory 200504 kb
Host smart-3c1a033c-a860-474b-a72f-c51589baa0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063429588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.4063429588
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.607679084
Short name T330
Test name
Test status
Simulation time 959321508 ps
CPU time 5.34 seconds
Started Jun 13 12:36:44 PM PDT 24
Finished Jun 13 12:36:51 PM PDT 24
Peak memory 200872 kb
Host smart-34b5e30f-d862-45b7-9e30-bbae40015169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607679084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.607679084
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2586103821
Short name T409
Test name
Test status
Simulation time 102272270 ps
CPU time 0.99 seconds
Started Jun 13 12:36:47 PM PDT 24
Finished Jun 13 12:36:49 PM PDT 24
Peak memory 200696 kb
Host smart-90050345-4218-4206-98f6-be801ca7b570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586103821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2586103821
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3826243900
Short name T126
Test name
Test status
Simulation time 244413907 ps
CPU time 1.58 seconds
Started Jun 13 12:36:42 PM PDT 24
Finished Jun 13 12:36:44 PM PDT 24
Peak memory 200836 kb
Host smart-3f7efb9d-f4d9-4173-b95f-15ebead7192f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826243900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3826243900
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1915387764
Short name T476
Test name
Test status
Simulation time 3240302425 ps
CPU time 14.67 seconds
Started Jun 13 12:36:45 PM PDT 24
Finished Jun 13 12:37:00 PM PDT 24
Peak memory 200920 kb
Host smart-a5a4bce9-69f3-4479-9b03-b83dd0575aab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915387764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1915387764
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1707014655
Short name T299
Test name
Test status
Simulation time 480072806 ps
CPU time 2.45 seconds
Started Jun 13 12:36:53 PM PDT 24
Finished Jun 13 12:36:59 PM PDT 24
Peak memory 200568 kb
Host smart-797e7ba6-246a-4f9e-b0ae-fb7808d78454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707014655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1707014655
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1202074655
Short name T337
Test name
Test status
Simulation time 107235721 ps
CPU time 0.93 seconds
Started Jun 13 12:36:48 PM PDT 24
Finished Jun 13 12:36:51 PM PDT 24
Peak memory 200580 kb
Host smart-93f6bdaf-e8b2-4444-89e2-ee43a692ab9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202074655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1202074655
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.937055344
Short name T391
Test name
Test status
Simulation time 75994394 ps
CPU time 0.83 seconds
Started Jun 13 12:36:35 PM PDT 24
Finished Jun 13 12:36:36 PM PDT 24
Peak memory 200400 kb
Host smart-4e6fa162-4706-40e0-8aee-8793d54cb6fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937055344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.937055344
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.3102381097
Short name T543
Test name
Test status
Simulation time 1889301660 ps
CPU time 6.89 seconds
Started Jun 13 12:36:44 PM PDT 24
Finished Jun 13 12:36:52 PM PDT 24
Peak memory 218136 kb
Host smart-e6a15062-14a4-4012-82f6-de0598fcb824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102381097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.3102381097
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1427229601
Short name T205
Test name
Test status
Simulation time 244292717 ps
CPU time 1.05 seconds
Started Jun 13 12:37:06 PM PDT 24
Finished Jun 13 12:37:08 PM PDT 24
Peak memory 218044 kb
Host smart-2e0f9572-863f-4801-a991-0bedaeda9b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427229601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1427229601
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.85940957
Short name T168
Test name
Test status
Simulation time 85355025 ps
CPU time 0.79 seconds
Started Jun 13 12:36:47 PM PDT 24
Finished Jun 13 12:36:48 PM PDT 24
Peak memory 200408 kb
Host smart-1a9e30e2-170b-43f2-bdbd-2268025331c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85940957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.85940957
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3504489522
Short name T442
Test name
Test status
Simulation time 2004126923 ps
CPU time 7.43 seconds
Started Jun 13 12:36:47 PM PDT 24
Finished Jun 13 12:36:56 PM PDT 24
Peak memory 200868 kb
Host smart-6622d530-51d9-456c-b594-1339ad8060a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504489522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3504489522
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3397967055
Short name T221
Test name
Test status
Simulation time 184706568 ps
CPU time 1.16 seconds
Started Jun 13 12:36:47 PM PDT 24
Finished Jun 13 12:36:51 PM PDT 24
Peak memory 200644 kb
Host smart-dc921759-97db-4fb6-8e22-9082c4929480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397967055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3397967055
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3789012231
Short name T342
Test name
Test status
Simulation time 113356531 ps
CPU time 1.24 seconds
Started Jun 13 12:36:43 PM PDT 24
Finished Jun 13 12:36:45 PM PDT 24
Peak memory 200812 kb
Host smart-746106a5-faf9-4606-b459-63ce2127c3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789012231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3789012231
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1130489521
Short name T414
Test name
Test status
Simulation time 305035601 ps
CPU time 1.48 seconds
Started Jun 13 12:36:52 PM PDT 24
Finished Jun 13 12:36:57 PM PDT 24
Peak memory 200564 kb
Host smart-3df6662e-4366-468e-9a77-93485df71c18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130489521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1130489521
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3865451630
Short name T287
Test name
Test status
Simulation time 469169545 ps
CPU time 2.49 seconds
Started Jun 13 12:37:01 PM PDT 24
Finished Jun 13 12:37:04 PM PDT 24
Peak memory 200648 kb
Host smart-58fde604-6810-4476-8871-09f764a4a4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865451630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3865451630
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1078006177
Short name T446
Test name
Test status
Simulation time 62571670 ps
CPU time 0.83 seconds
Started Jun 13 12:36:55 PM PDT 24
Finished Jun 13 12:36:58 PM PDT 24
Peak memory 200648 kb
Host smart-58da73ca-f59a-4bce-8a3c-5b780eab51dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078006177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1078006177
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2454898157
Short name T63
Test name
Test status
Simulation time 65749438 ps
CPU time 0.76 seconds
Started Jun 13 12:36:48 PM PDT 24
Finished Jun 13 12:36:51 PM PDT 24
Peak memory 200484 kb
Host smart-39cb4e3d-cf7a-442b-bcea-c0cc1b4e9aa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454898157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2454898157
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1037089629
Short name T276
Test name
Test status
Simulation time 1222123048 ps
CPU time 5.49 seconds
Started Jun 13 12:36:47 PM PDT 24
Finished Jun 13 12:36:54 PM PDT 24
Peak memory 218420 kb
Host smart-45d259fc-50b7-4e38-a231-7ad04f5a1375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037089629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1037089629
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.4204260655
Short name T367
Test name
Test status
Simulation time 243443131 ps
CPU time 1.07 seconds
Started Jun 13 12:36:55 PM PDT 24
Finished Jun 13 12:36:58 PM PDT 24
Peak memory 218080 kb
Host smart-b9305568-af3a-4f98-9be4-cf2b693244fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204260655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.4204260655
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.397449257
Short name T456
Test name
Test status
Simulation time 127455125 ps
CPU time 0.87 seconds
Started Jun 13 12:36:40 PM PDT 24
Finished Jun 13 12:36:41 PM PDT 24
Peak memory 200484 kb
Host smart-d24606e3-0bb7-4860-8a1b-b970cbb8b59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397449257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.397449257
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2463381573
Short name T333
Test name
Test status
Simulation time 773791613 ps
CPU time 4.05 seconds
Started Jun 13 12:36:42 PM PDT 24
Finished Jun 13 12:36:54 PM PDT 24
Peak memory 200772 kb
Host smart-2434bb9e-d353-40f7-83ef-d8fa6f1361ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463381573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2463381573
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2572238796
Short name T289
Test name
Test status
Simulation time 103572388 ps
CPU time 1.04 seconds
Started Jun 13 12:36:40 PM PDT 24
Finished Jun 13 12:36:42 PM PDT 24
Peak memory 200656 kb
Host smart-a0efe9ef-2c9e-45f7-98c3-e68e65205ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572238796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2572238796
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.290935056
Short name T467
Test name
Test status
Simulation time 203110187 ps
CPU time 1.49 seconds
Started Jun 13 12:36:39 PM PDT 24
Finished Jun 13 12:36:41 PM PDT 24
Peak memory 200836 kb
Host smart-1e0a488d-274b-4ae9-9000-d0d75b61a750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290935056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.290935056
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1059000858
Short name T119
Test name
Test status
Simulation time 14379979284 ps
CPU time 46.14 seconds
Started Jun 13 12:36:49 PM PDT 24
Finished Jun 13 12:37:37 PM PDT 24
Peak memory 200868 kb
Host smart-a2f91e99-09f5-44d9-80ed-6721716c40da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059000858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1059000858
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.4007240408
Short name T489
Test name
Test status
Simulation time 262822171 ps
CPU time 1.8 seconds
Started Jun 13 12:36:46 PM PDT 24
Finished Jun 13 12:36:48 PM PDT 24
Peak memory 200652 kb
Host smart-d17b60f3-37a5-4a51-9615-b5d5ebc43e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007240408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.4007240408
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.2329545933
Short name T317
Test name
Test status
Simulation time 117814346 ps
CPU time 0.92 seconds
Started Jun 13 12:36:49 PM PDT 24
Finished Jun 13 12:36:54 PM PDT 24
Peak memory 200660 kb
Host smart-75aa888d-496e-4662-8591-9b28a15d0ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329545933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2329545933
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.587156061
Short name T483
Test name
Test status
Simulation time 63778309 ps
CPU time 0.75 seconds
Started Jun 13 12:36:48 PM PDT 24
Finished Jun 13 12:36:51 PM PDT 24
Peak memory 200436 kb
Host smart-07347f28-d3fe-47b2-a52b-86e2a6d54b2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587156061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.587156061
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1859945152
Short name T412
Test name
Test status
Simulation time 1231004061 ps
CPU time 5.82 seconds
Started Jun 13 12:36:39 PM PDT 24
Finished Jun 13 12:36:46 PM PDT 24
Peak memory 218068 kb
Host smart-d5e068ad-ae54-4bb0-ad66-e608a729ac94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859945152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1859945152
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2104354604
Short name T521
Test name
Test status
Simulation time 243737719 ps
CPU time 1.17 seconds
Started Jun 13 12:36:45 PM PDT 24
Finished Jun 13 12:36:47 PM PDT 24
Peak memory 217792 kb
Host smart-7bfd7b90-af17-495d-9395-9d0c4cf5275f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104354604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2104354604
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2679753082
Short name T421
Test name
Test status
Simulation time 122778862 ps
CPU time 0.84 seconds
Started Jun 13 12:36:46 PM PDT 24
Finished Jun 13 12:36:48 PM PDT 24
Peak memory 200476 kb
Host smart-b4df1260-7dd8-4255-ac79-484db7033bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679753082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2679753082
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3617211796
Short name T127
Test name
Test status
Simulation time 1388912770 ps
CPU time 5.45 seconds
Started Jun 13 12:36:55 PM PDT 24
Finished Jun 13 12:37:03 PM PDT 24
Peak memory 200860 kb
Host smart-0e4d326d-0b05-4dad-b141-0d9a370416e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617211796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3617211796
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.136885676
Short name T537
Test name
Test status
Simulation time 107735165 ps
CPU time 1.01 seconds
Started Jun 13 12:36:51 PM PDT 24
Finished Jun 13 12:36:56 PM PDT 24
Peak memory 200724 kb
Host smart-f2879f50-861b-4577-b852-75681c52d002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136885676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.136885676
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3909860328
Short name T400
Test name
Test status
Simulation time 247822978 ps
CPU time 1.51 seconds
Started Jun 13 12:36:39 PM PDT 24
Finished Jun 13 12:36:42 PM PDT 24
Peak memory 200772 kb
Host smart-09f7ec07-030c-4b50-af97-3b10af6679de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909860328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3909860328
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2457976071
Short name T148
Test name
Test status
Simulation time 1408502082 ps
CPU time 6.49 seconds
Started Jun 13 12:36:48 PM PDT 24
Finished Jun 13 12:36:57 PM PDT 24
Peak memory 200848 kb
Host smart-19c876cb-a984-42fc-a7f7-e60bd2d7b755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457976071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2457976071
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.2161126827
Short name T51
Test name
Test status
Simulation time 370493703 ps
CPU time 2.54 seconds
Started Jun 13 12:36:50 PM PDT 24
Finished Jun 13 12:36:56 PM PDT 24
Peak memory 200564 kb
Host smart-55fd6c95-9f08-441a-96ba-29e2736c9e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161126827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2161126827
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1666391828
Short name T134
Test name
Test status
Simulation time 65821610 ps
CPU time 0.77 seconds
Started Jun 13 12:36:48 PM PDT 24
Finished Jun 13 12:36:51 PM PDT 24
Peak memory 200668 kb
Host smart-4d240cae-80e6-40d0-b850-bc2283e8a549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666391828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1666391828
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.1986418005
Short name T482
Test name
Test status
Simulation time 72193831 ps
CPU time 0.83 seconds
Started Jun 13 12:37:01 PM PDT 24
Finished Jun 13 12:37:02 PM PDT 24
Peak memory 200484 kb
Host smart-6509f4d3-cf24-4473-a376-a0ce241a1f2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986418005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1986418005
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1257175261
Short name T247
Test name
Test status
Simulation time 1885426961 ps
CPU time 7.08 seconds
Started Jun 13 12:36:33 PM PDT 24
Finished Jun 13 12:36:42 PM PDT 24
Peak memory 222340 kb
Host smart-0540d2c8-d9c3-4bf4-b7a9-c9659965163a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257175261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1257175261
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3868958361
Short name T164
Test name
Test status
Simulation time 243323265 ps
CPU time 1.06 seconds
Started Jun 13 12:36:44 PM PDT 24
Finished Jun 13 12:36:51 PM PDT 24
Peak memory 217984 kb
Host smart-0ae28f6f-b784-4480-afa4-96ec3338317c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868958361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3868958361
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1384330250
Short name T21
Test name
Test status
Simulation time 194955624 ps
CPU time 0.91 seconds
Started Jun 13 12:36:40 PM PDT 24
Finished Jun 13 12:36:42 PM PDT 24
Peak memory 200512 kb
Host smart-00e015b1-f9b4-4144-811f-c91740f7c91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384330250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1384330250
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2163588831
Short name T144
Test name
Test status
Simulation time 1152587768 ps
CPU time 4.68 seconds
Started Jun 13 12:36:48 PM PDT 24
Finished Jun 13 12:36:55 PM PDT 24
Peak memory 200852 kb
Host smart-55713031-a5f7-4171-8ba0-076e41b9c23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163588831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2163588831
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.174740802
Short name T143
Test name
Test status
Simulation time 105163300 ps
CPU time 0.99 seconds
Started Jun 13 12:37:06 PM PDT 24
Finished Jun 13 12:37:09 PM PDT 24
Peak memory 200692 kb
Host smart-83b2fede-ee4f-4517-adf1-6edba892857b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174740802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.174740802
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.4020855354
Short name T529
Test name
Test status
Simulation time 255826185 ps
CPU time 1.57 seconds
Started Jun 13 12:36:43 PM PDT 24
Finished Jun 13 12:36:45 PM PDT 24
Peak memory 200852 kb
Host smart-13bc1b89-f866-4223-b24d-ba9dcc73d942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020855354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.4020855354
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.766177241
Short name T343
Test name
Test status
Simulation time 4438612755 ps
CPU time 20.29 seconds
Started Jun 13 12:36:49 PM PDT 24
Finished Jun 13 12:37:12 PM PDT 24
Peak memory 210856 kb
Host smart-c6169d64-6dc5-4fd8-9497-344592d89370
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766177241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.766177241
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1509365956
Short name T233
Test name
Test status
Simulation time 144329003 ps
CPU time 1.78 seconds
Started Jun 13 12:36:29 PM PDT 24
Finished Jun 13 12:36:33 PM PDT 24
Peak memory 200588 kb
Host smart-cb8544f7-3554-47cb-8645-9f021758b99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509365956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1509365956
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.4196712856
Short name T484
Test name
Test status
Simulation time 73494474 ps
CPU time 0.77 seconds
Started Jun 13 12:36:50 PM PDT 24
Finished Jun 13 12:36:54 PM PDT 24
Peak memory 200688 kb
Host smart-41d9797e-b68e-4e7e-b5e2-2671b9538628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196712856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.4196712856
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.664227150
Short name T466
Test name
Test status
Simulation time 61117007 ps
CPU time 0.81 seconds
Started Jun 13 12:36:49 PM PDT 24
Finished Jun 13 12:36:52 PM PDT 24
Peak memory 200508 kb
Host smart-e1367105-5e53-4c24-bf26-e5bd8afbb235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664227150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.664227150
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3157502756
Short name T458
Test name
Test status
Simulation time 1219169923 ps
CPU time 5.66 seconds
Started Jun 13 12:36:55 PM PDT 24
Finished Jun 13 12:37:03 PM PDT 24
Peak memory 218372 kb
Host smart-4826a206-c105-4ade-92e8-a5c391e601ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157502756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3157502756
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3468228700
Short name T273
Test name
Test status
Simulation time 244206790 ps
CPU time 1.02 seconds
Started Jun 13 12:36:50 PM PDT 24
Finished Jun 13 12:36:55 PM PDT 24
Peak memory 218108 kb
Host smart-a6e8f81c-1f28-4f55-94cd-c5f55013819a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468228700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3468228700
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3140150995
Short name T411
Test name
Test status
Simulation time 164457661 ps
CPU time 0.91 seconds
Started Jun 13 12:36:48 PM PDT 24
Finished Jun 13 12:36:51 PM PDT 24
Peak memory 200460 kb
Host smart-29e3882f-c5db-4cab-829a-6e9339f19ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140150995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3140150995
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2026438326
Short name T513
Test name
Test status
Simulation time 863791833 ps
CPU time 4.37 seconds
Started Jun 13 12:36:54 PM PDT 24
Finished Jun 13 12:37:01 PM PDT 24
Peak memory 200860 kb
Host smart-8a16f99b-bf31-425b-8db9-345bfba8e550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026438326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2026438326
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.37944876
Short name T534
Test name
Test status
Simulation time 185619020 ps
CPU time 1.21 seconds
Started Jun 13 12:36:48 PM PDT 24
Finished Jun 13 12:36:52 PM PDT 24
Peak memory 200660 kb
Host smart-133deb9b-107a-406e-8de2-0bdde9b461a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37944876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.37944876
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.3504941890
Short name T153
Test name
Test status
Simulation time 193402171 ps
CPU time 1.31 seconds
Started Jun 13 12:36:49 PM PDT 24
Finished Jun 13 12:36:53 PM PDT 24
Peak memory 200860 kb
Host smart-485e8e46-2619-4d8f-98d4-6a375ef3e9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504941890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3504941890
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3369012733
Short name T506
Test name
Test status
Simulation time 9281475200 ps
CPU time 34.06 seconds
Started Jun 13 12:36:35 PM PDT 24
Finished Jun 13 12:37:09 PM PDT 24
Peak memory 209156 kb
Host smart-3dc2b89e-6c9f-4af3-a5b8-c0201d291513
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369012733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3369012733
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.506210214
Short name T503
Test name
Test status
Simulation time 487082337 ps
CPU time 2.85 seconds
Started Jun 13 12:36:40 PM PDT 24
Finished Jun 13 12:36:44 PM PDT 24
Peak memory 200636 kb
Host smart-cf888a0a-cd36-41c0-a6a9-c6176d7c777d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506210214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.506210214
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.111016230
Short name T480
Test name
Test status
Simulation time 250524340 ps
CPU time 1.44 seconds
Started Jun 13 12:36:45 PM PDT 24
Finished Jun 13 12:36:48 PM PDT 24
Peak memory 200496 kb
Host smart-32097fe8-8ada-437c-9aa5-fca0396f7682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111016230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.111016230
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.882638175
Short name T165
Test name
Test status
Simulation time 69818058 ps
CPU time 0.74 seconds
Started Jun 13 12:37:02 PM PDT 24
Finished Jun 13 12:37:04 PM PDT 24
Peak memory 200508 kb
Host smart-6f12f9fd-3404-4a4f-a8b5-24cdd769b7dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882638175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.882638175
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3227087157
Short name T227
Test name
Test status
Simulation time 1224464838 ps
CPU time 5.9 seconds
Started Jun 13 12:37:07 PM PDT 24
Finished Jun 13 12:37:15 PM PDT 24
Peak memory 222464 kb
Host smart-0a1c3235-6ffd-4471-b4b8-3555118eeff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227087157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3227087157
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3077978511
Short name T361
Test name
Test status
Simulation time 245233069 ps
CPU time 1.07 seconds
Started Jun 13 12:36:53 PM PDT 24
Finished Jun 13 12:36:57 PM PDT 24
Peak memory 217968 kb
Host smart-ef8d0b66-9db7-4ee3-8c7c-1af2e512bdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077978511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3077978511
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3418156797
Short name T439
Test name
Test status
Simulation time 164079525 ps
CPU time 0.9 seconds
Started Jun 13 12:36:46 PM PDT 24
Finished Jun 13 12:36:48 PM PDT 24
Peak memory 200468 kb
Host smart-6bf79f2f-477b-4d3f-be6a-b4f05fcf5898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418156797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3418156797
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2650608171
Short name T192
Test name
Test status
Simulation time 1815388534 ps
CPU time 7.39 seconds
Started Jun 13 12:37:01 PM PDT 24
Finished Jun 13 12:37:09 PM PDT 24
Peak memory 200748 kb
Host smart-cdd1b7e5-d68f-4981-9579-15736a6b3c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650608171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2650608171
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3188297489
Short name T210
Test name
Test status
Simulation time 96112063 ps
CPU time 1.01 seconds
Started Jun 13 12:36:44 PM PDT 24
Finished Jun 13 12:36:46 PM PDT 24
Peak memory 200672 kb
Host smart-6fe6d4ee-fde6-4c48-9e00-72d80ec59970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188297489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3188297489
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.3849933242
Short name T219
Test name
Test status
Simulation time 258666972 ps
CPU time 1.5 seconds
Started Jun 13 12:36:45 PM PDT 24
Finished Jun 13 12:36:51 PM PDT 24
Peak memory 200872 kb
Host smart-df457c1c-9d70-4caf-95a9-6b0834d12706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849933242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3849933242
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.4269303024
Short name T308
Test name
Test status
Simulation time 2723686037 ps
CPU time 11.82 seconds
Started Jun 13 12:36:47 PM PDT 24
Finished Jun 13 12:37:01 PM PDT 24
Peak memory 216944 kb
Host smart-e4cb60d6-51d5-46da-9d3b-c560c53d7062
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269303024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.4269303024
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3753411395
Short name T179
Test name
Test status
Simulation time 335997404 ps
CPU time 2.08 seconds
Started Jun 13 12:36:39 PM PDT 24
Finished Jun 13 12:36:42 PM PDT 24
Peak memory 200684 kb
Host smart-2c142782-0c29-462a-8d4b-7d7926649898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753411395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3753411395
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.711316763
Short name T338
Test name
Test status
Simulation time 118248750 ps
CPU time 1.03 seconds
Started Jun 13 12:36:49 PM PDT 24
Finished Jun 13 12:36:52 PM PDT 24
Peak memory 200600 kb
Host smart-4ae206b7-3595-46f9-aab5-f3c76bc726aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711316763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.711316763
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.1698866592
Short name T146
Test name
Test status
Simulation time 68328457 ps
CPU time 0.77 seconds
Started Jun 13 12:36:45 PM PDT 24
Finished Jun 13 12:36:47 PM PDT 24
Peak memory 200496 kb
Host smart-e05bdd3e-603d-4d36-ae77-f5849ca727c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698866592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1698866592
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.71705581
Short name T48
Test name
Test status
Simulation time 1875249726 ps
CPU time 7.57 seconds
Started Jun 13 12:36:47 PM PDT 24
Finished Jun 13 12:36:57 PM PDT 24
Peak memory 218088 kb
Host smart-a54c357c-d48b-4274-9519-f41bd558e9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71705581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.71705581
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1699516215
Short name T158
Test name
Test status
Simulation time 245078974 ps
CPU time 1.05 seconds
Started Jun 13 12:36:49 PM PDT 24
Finished Jun 13 12:36:54 PM PDT 24
Peak memory 218052 kb
Host smart-f3e55836-a90d-4325-b2d1-9080c51faf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699516215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1699516215
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1406282790
Short name T542
Test name
Test status
Simulation time 177613742 ps
CPU time 0.83 seconds
Started Jun 13 12:36:47 PM PDT 24
Finished Jun 13 12:36:49 PM PDT 24
Peak memory 200448 kb
Host smart-7f2ce00a-a4b6-4040-9208-cec43ee6f296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406282790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1406282790
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.2375150386
Short name T95
Test name
Test status
Simulation time 878448492 ps
CPU time 4.29 seconds
Started Jun 13 12:36:44 PM PDT 24
Finished Jun 13 12:36:50 PM PDT 24
Peak memory 200876 kb
Host smart-02fcec3a-3fd1-4e6d-ba08-7311a711014f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375150386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2375150386
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1738298948
Short name T154
Test name
Test status
Simulation time 98272086 ps
CPU time 1.01 seconds
Started Jun 13 12:36:50 PM PDT 24
Finished Jun 13 12:36:55 PM PDT 24
Peak memory 200724 kb
Host smart-1be44f72-4ddb-4cfc-b8bf-6471247191bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738298948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1738298948
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1579989882
Short name T488
Test name
Test status
Simulation time 226154483 ps
CPU time 1.49 seconds
Started Jun 13 12:37:01 PM PDT 24
Finished Jun 13 12:37:04 PM PDT 24
Peak memory 200772 kb
Host smart-2fe102e1-7900-4c66-96e6-1bf3954fc16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579989882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1579989882
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1434997049
Short name T70
Test name
Test status
Simulation time 4201115280 ps
CPU time 15.11 seconds
Started Jun 13 12:36:50 PM PDT 24
Finished Jun 13 12:37:08 PM PDT 24
Peak memory 209824 kb
Host smart-f801a890-1ab6-4c51-b21d-870d5a49d728
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434997049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1434997049
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2483245084
Short name T508
Test name
Test status
Simulation time 383573790 ps
CPU time 2.09 seconds
Started Jun 13 12:36:46 PM PDT 24
Finished Jun 13 12:36:48 PM PDT 24
Peak memory 200576 kb
Host smart-dddf34e2-3f18-471b-8ef6-49c482f895ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483245084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2483245084
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3741393060
Short name T357
Test name
Test status
Simulation time 232874035 ps
CPU time 1.5 seconds
Started Jun 13 12:36:47 PM PDT 24
Finished Jun 13 12:36:49 PM PDT 24
Peak memory 200848 kb
Host smart-e9210439-1d07-46d9-8656-96d62674a8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741393060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3741393060
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2270856228
Short name T501
Test name
Test status
Simulation time 67457661 ps
CPU time 0.74 seconds
Started Jun 13 12:37:22 PM PDT 24
Finished Jun 13 12:37:25 PM PDT 24
Peak memory 200456 kb
Host smart-ac6c1a28-0f25-4544-86b7-687445d5c17f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270856228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2270856228
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.4234588061
Short name T460
Test name
Test status
Simulation time 1213745252 ps
CPU time 5.52 seconds
Started Jun 13 12:37:00 PM PDT 24
Finished Jun 13 12:37:06 PM PDT 24
Peak memory 218112 kb
Host smart-4864e8ee-a7b5-4eed-8dc2-d4d557013658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234588061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.4234588061
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2481563901
Short name T464
Test name
Test status
Simulation time 245483433 ps
CPU time 1.07 seconds
Started Jun 13 12:36:52 PM PDT 24
Finished Jun 13 12:36:56 PM PDT 24
Peak memory 218340 kb
Host smart-55ea64e8-205d-4272-a6f7-f55408aa55ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481563901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2481563901
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.3234957883
Short name T155
Test name
Test status
Simulation time 134245364 ps
CPU time 0.78 seconds
Started Jun 13 12:37:16 PM PDT 24
Finished Jun 13 12:37:20 PM PDT 24
Peak memory 200500 kb
Host smart-302f7a69-0a0b-483a-986a-b2eb776e0e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234957883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3234957883
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.4278597885
Short name T469
Test name
Test status
Simulation time 1796676961 ps
CPU time 7.04 seconds
Started Jun 13 12:37:06 PM PDT 24
Finished Jun 13 12:37:15 PM PDT 24
Peak memory 200872 kb
Host smart-2e25a95e-5efe-4d2a-b45a-4b1bbbc7cf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278597885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.4278597885
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2891155986
Short name T263
Test name
Test status
Simulation time 106404965 ps
CPU time 1.02 seconds
Started Jun 13 12:36:47 PM PDT 24
Finished Jun 13 12:36:51 PM PDT 24
Peak memory 200700 kb
Host smart-cb05aa58-38c9-4cf7-a47c-e440ba8d3ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891155986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2891155986
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3604924525
Short name T203
Test name
Test status
Simulation time 192704792 ps
CPU time 1.46 seconds
Started Jun 13 12:37:36 PM PDT 24
Finished Jun 13 12:37:39 PM PDT 24
Peak memory 200920 kb
Host smart-c305e3ec-fb36-4363-864b-4af2abff1bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604924525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3604924525
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2738927592
Short name T92
Test name
Test status
Simulation time 4518855910 ps
CPU time 16.78 seconds
Started Jun 13 12:36:46 PM PDT 24
Finished Jun 13 12:37:06 PM PDT 24
Peak memory 200948 kb
Host smart-169c6b6e-5acd-4b85-b64b-7077c3ee8fd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738927592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2738927592
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.1250161031
Short name T387
Test name
Test status
Simulation time 326996914 ps
CPU time 2.17 seconds
Started Jun 13 12:36:46 PM PDT 24
Finished Jun 13 12:36:49 PM PDT 24
Peak memory 200680 kb
Host smart-38ee857b-69bf-4d9b-a8a8-eb74813058d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250161031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1250161031
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.4182513867
Short name T318
Test name
Test status
Simulation time 105951759 ps
CPU time 0.88 seconds
Started Jun 13 12:37:13 PM PDT 24
Finished Jun 13 12:37:16 PM PDT 24
Peak memory 200640 kb
Host smart-c4275170-2d48-4183-9f25-e8a4152513f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182513867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.4182513867
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3366807626
Short name T516
Test name
Test status
Simulation time 74039844 ps
CPU time 0.76 seconds
Started Jun 13 12:36:09 PM PDT 24
Finished Jun 13 12:36:13 PM PDT 24
Peak memory 200400 kb
Host smart-0a94ccab-2789-45f9-934d-fcb6464d2324
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366807626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3366807626
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3846525399
Short name T40
Test name
Test status
Simulation time 1226334267 ps
CPU time 5.5 seconds
Started Jun 13 12:36:00 PM PDT 24
Finished Jun 13 12:36:10 PM PDT 24
Peak memory 218412 kb
Host smart-2dc669a1-a677-4a42-ae5b-de6d7fcae16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846525399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3846525399
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.399870304
Short name T356
Test name
Test status
Simulation time 245275231 ps
CPU time 1.05 seconds
Started Jun 13 12:36:08 PM PDT 24
Finished Jun 13 12:36:12 PM PDT 24
Peak memory 218136 kb
Host smart-cdfcf4f7-ee23-408b-afdf-51760af45678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399870304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.399870304
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1767852884
Short name T510
Test name
Test status
Simulation time 232079947 ps
CPU time 1.01 seconds
Started Jun 13 12:35:49 PM PDT 24
Finished Jun 13 12:35:53 PM PDT 24
Peak memory 200724 kb
Host smart-48d56e55-830b-41a9-a104-c46f3817bc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767852884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1767852884
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1539032861
Short name T237
Test name
Test status
Simulation time 1651963202 ps
CPU time 6.81 seconds
Started Jun 13 12:36:02 PM PDT 24
Finished Jun 13 12:36:12 PM PDT 24
Peak memory 200768 kb
Host smart-a2b69146-2e98-4b59-9b3b-7d4bd4c876c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539032861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1539032861
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3055770296
Short name T462
Test name
Test status
Simulation time 104491163 ps
CPU time 0.98 seconds
Started Jun 13 12:36:11 PM PDT 24
Finished Jun 13 12:36:16 PM PDT 24
Peak memory 200680 kb
Host smart-82040481-6313-4271-8122-efa6c84572d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055770296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3055770296
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2946994977
Short name T512
Test name
Test status
Simulation time 205494113 ps
CPU time 1.41 seconds
Started Jun 13 12:35:55 PM PDT 24
Finished Jun 13 12:36:01 PM PDT 24
Peak memory 200768 kb
Host smart-047c914e-61fb-466c-b325-484b798c2db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946994977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2946994977
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2503775081
Short name T535
Test name
Test status
Simulation time 3138640366 ps
CPU time 14.08 seconds
Started Jun 13 12:35:54 PM PDT 24
Finished Jun 13 12:36:13 PM PDT 24
Peak memory 210856 kb
Host smart-5afec70e-7df2-4346-8c7c-4bf5ebc5a4ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503775081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2503775081
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1970070909
Short name T218
Test name
Test status
Simulation time 83536829 ps
CPU time 0.79 seconds
Started Jun 13 12:36:11 PM PDT 24
Finished Jun 13 12:36:15 PM PDT 24
Peak memory 200684 kb
Host smart-2267a2c1-f510-44a0-86ed-fb30e396d5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970070909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1970070909
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.4177522041
Short name T478
Test name
Test status
Simulation time 65697472 ps
CPU time 0.82 seconds
Started Jun 13 12:35:57 PM PDT 24
Finished Jun 13 12:36:02 PM PDT 24
Peak memory 199616 kb
Host smart-343aa085-4ee0-4de6-9307-37210827eb66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177522041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.4177522041
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3377195464
Short name T437
Test name
Test status
Simulation time 1896122365 ps
CPU time 7.05 seconds
Started Jun 13 12:36:03 PM PDT 24
Finished Jun 13 12:36:14 PM PDT 24
Peak memory 218400 kb
Host smart-9d2e9527-c778-4c59-8b7d-aeb9052990ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377195464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3377195464
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.961098881
Short name T147
Test name
Test status
Simulation time 244240714 ps
CPU time 1.02 seconds
Started Jun 13 12:35:58 PM PDT 24
Finished Jun 13 12:36:04 PM PDT 24
Peak memory 218076 kb
Host smart-509fd6f1-84c5-4598-b918-0d9d88e343c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961098881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.961098881
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1026387642
Short name T541
Test name
Test status
Simulation time 139493483 ps
CPU time 0.83 seconds
Started Jun 13 12:36:04 PM PDT 24
Finished Jun 13 12:36:08 PM PDT 24
Peak memory 200504 kb
Host smart-5552077d-da2d-4981-be29-5b6af8cc5b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026387642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1026387642
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.747539002
Short name T137
Test name
Test status
Simulation time 1402491198 ps
CPU time 6.04 seconds
Started Jun 13 12:35:51 PM PDT 24
Finished Jun 13 12:36:00 PM PDT 24
Peak memory 200784 kb
Host smart-2fb8b7ae-7af2-4e3e-8bcc-82027c9edc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747539002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.747539002
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.144120878
Short name T321
Test name
Test status
Simulation time 102455968 ps
CPU time 0.99 seconds
Started Jun 13 12:36:05 PM PDT 24
Finished Jun 13 12:36:09 PM PDT 24
Peak memory 200700 kb
Host smart-3ec5d434-afa1-447d-afed-dbe18d54fb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144120878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.144120878
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.3119349021
Short name T171
Test name
Test status
Simulation time 251243576 ps
CPU time 1.48 seconds
Started Jun 13 12:36:03 PM PDT 24
Finished Jun 13 12:36:08 PM PDT 24
Peak memory 200760 kb
Host smart-6338fb44-f7c2-4451-b1a2-fee2f1b76d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119349021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3119349021
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.508096267
Short name T352
Test name
Test status
Simulation time 9036597955 ps
CPU time 38.93 seconds
Started Jun 13 12:35:55 PM PDT 24
Finished Jun 13 12:36:38 PM PDT 24
Peak memory 200876 kb
Host smart-94eba933-cef6-4e8e-9d18-1fdeb98bca28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508096267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.508096267
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.2452817722
Short name T523
Test name
Test status
Simulation time 323734259 ps
CPU time 2.05 seconds
Started Jun 13 12:36:03 PM PDT 24
Finished Jun 13 12:36:09 PM PDT 24
Peak memory 200728 kb
Host smart-2cba2f1c-d1b6-466f-ae44-30aabadea1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452817722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2452817722
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.4064974408
Short name T540
Test name
Test status
Simulation time 146867179 ps
CPU time 1.06 seconds
Started Jun 13 12:36:04 PM PDT 24
Finished Jun 13 12:36:08 PM PDT 24
Peak memory 200604 kb
Host smart-19537e73-44cc-4021-a44f-45dd5ec90100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064974408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.4064974408
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3970793668
Short name T472
Test name
Test status
Simulation time 62280596 ps
CPU time 0.82 seconds
Started Jun 13 12:35:50 PM PDT 24
Finished Jun 13 12:35:53 PM PDT 24
Peak memory 200220 kb
Host smart-106ab345-548a-4099-89ab-af0188909150
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970793668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3970793668
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1942879628
Short name T46
Test name
Test status
Simulation time 1233413245 ps
CPU time 5.62 seconds
Started Jun 13 12:35:59 PM PDT 24
Finished Jun 13 12:36:09 PM PDT 24
Peak memory 222336 kb
Host smart-75f76765-f2ed-4e42-b636-76450ecbe0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942879628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1942879628
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1665546835
Short name T197
Test name
Test status
Simulation time 244705024 ps
CPU time 1.11 seconds
Started Jun 13 12:35:57 PM PDT 24
Finished Jun 13 12:36:03 PM PDT 24
Peak memory 218036 kb
Host smart-7f531608-89e5-4e47-b22e-8ca0cde53b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665546835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1665546835
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1892830369
Short name T20
Test name
Test status
Simulation time 168402725 ps
CPU time 0.83 seconds
Started Jun 13 12:36:17 PM PDT 24
Finished Jun 13 12:36:21 PM PDT 24
Peak memory 200516 kb
Host smart-02b96257-791a-47f5-918a-adad85fee26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892830369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1892830369
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3355093239
Short name T116
Test name
Test status
Simulation time 1589957198 ps
CPU time 5.78 seconds
Started Jun 13 12:35:59 PM PDT 24
Finished Jun 13 12:36:10 PM PDT 24
Peak memory 200816 kb
Host smart-ef9a09fa-2c9b-4c39-acd8-3294b0b7de3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355093239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3355093239
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2993136356
Short name T425
Test name
Test status
Simulation time 110862140 ps
CPU time 1 seconds
Started Jun 13 12:36:03 PM PDT 24
Finished Jun 13 12:36:08 PM PDT 24
Peak memory 200696 kb
Host smart-ee7d41a1-455b-4638-90cc-23228b7314a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993136356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2993136356
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3816487668
Short name T211
Test name
Test status
Simulation time 123488454 ps
CPU time 1.15 seconds
Started Jun 13 12:35:59 PM PDT 24
Finished Jun 13 12:36:04 PM PDT 24
Peak memory 200772 kb
Host smart-155c0ca1-11ea-48ad-8a4e-0501a2c5ac5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816487668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3816487668
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.478316400
Short name T349
Test name
Test status
Simulation time 9139737251 ps
CPU time 33.41 seconds
Started Jun 13 12:36:02 PM PDT 24
Finished Jun 13 12:36:39 PM PDT 24
Peak memory 200872 kb
Host smart-8f8b3611-c82b-4508-bd1e-c5932cccaf21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478316400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.478316400
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.2737367637
Short name T368
Test name
Test status
Simulation time 136910775 ps
CPU time 1.87 seconds
Started Jun 13 12:35:55 PM PDT 24
Finished Jun 13 12:36:02 PM PDT 24
Peak memory 200584 kb
Host smart-c5cebba2-9041-4817-b576-23c52e680e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737367637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2737367637
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3014316557
Short name T408
Test name
Test status
Simulation time 82193240 ps
CPU time 0.9 seconds
Started Jun 13 12:35:56 PM PDT 24
Finished Jun 13 12:36:01 PM PDT 24
Peak memory 200612 kb
Host smart-43de2dc1-1f39-4ce5-b346-ebe1bbda08e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014316557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3014316557
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2047862357
Short name T336
Test name
Test status
Simulation time 54483525 ps
CPU time 0.74 seconds
Started Jun 13 12:35:58 PM PDT 24
Finished Jun 13 12:36:03 PM PDT 24
Peak memory 200468 kb
Host smart-adc6f505-bc57-4f8d-868c-b726519949b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047862357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2047862357
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3227074163
Short name T319
Test name
Test status
Simulation time 1902718587 ps
CPU time 7.29 seconds
Started Jun 13 12:35:54 PM PDT 24
Finished Jun 13 12:36:05 PM PDT 24
Peak memory 222300 kb
Host smart-37b418b2-df19-44c9-8b99-3138aafcde31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227074163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3227074163
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2563406725
Short name T32
Test name
Test status
Simulation time 244625112 ps
CPU time 1.06 seconds
Started Jun 13 12:36:04 PM PDT 24
Finished Jun 13 12:36:09 PM PDT 24
Peak memory 218024 kb
Host smart-1aa9b24e-09cc-43c4-bb35-251ec0dd2974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563406725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2563406725
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2576167896
Short name T17
Test name
Test status
Simulation time 170416338 ps
CPU time 0.9 seconds
Started Jun 13 12:35:57 PM PDT 24
Finished Jun 13 12:36:03 PM PDT 24
Peak memory 200416 kb
Host smart-98334f8c-b390-4845-a40b-01c3376b99c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576167896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2576167896
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.4071524534
Short name T279
Test name
Test status
Simulation time 987745728 ps
CPU time 5.06 seconds
Started Jun 13 12:35:53 PM PDT 24
Finished Jun 13 12:36:02 PM PDT 24
Peak memory 200844 kb
Host smart-6dbb8cc2-41a9-4365-a220-128ddbe4ba6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071524534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.4071524534
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.4093101889
Short name T74
Test name
Test status
Simulation time 182746114 ps
CPU time 1.2 seconds
Started Jun 13 12:35:57 PM PDT 24
Finished Jun 13 12:36:03 PM PDT 24
Peak memory 200608 kb
Host smart-5b9c26aa-df2b-4679-aaa4-1db27e47144c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093101889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.4093101889
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2479816163
Short name T72
Test name
Test status
Simulation time 207538327 ps
CPU time 1.39 seconds
Started Jun 13 12:36:10 PM PDT 24
Finished Jun 13 12:36:15 PM PDT 24
Peak memory 200868 kb
Host smart-557a00e8-cfe3-434a-8ce7-59574092902f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479816163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2479816163
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.3613417195
Short name T401
Test name
Test status
Simulation time 2512130138 ps
CPU time 11.59 seconds
Started Jun 13 12:36:11 PM PDT 24
Finished Jun 13 12:36:27 PM PDT 24
Peak memory 210288 kb
Host smart-ef321887-dbb1-4ccf-ac9d-bfd5f2522c2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613417195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3613417195
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.1199683491
Short name T212
Test name
Test status
Simulation time 318910194 ps
CPU time 2.18 seconds
Started Jun 13 12:36:06 PM PDT 24
Finished Jun 13 12:36:11 PM PDT 24
Peak memory 200564 kb
Host smart-93db70a6-f6d0-411b-89aa-247543baeaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199683491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1199683491
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.72635626
Short name T73
Test name
Test status
Simulation time 254574977 ps
CPU time 1.46 seconds
Started Jun 13 12:36:06 PM PDT 24
Finished Jun 13 12:36:11 PM PDT 24
Peak memory 200800 kb
Host smart-b57726af-7d83-44e8-a27a-0d8983db6e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72635626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.72635626
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3916736530
Short name T161
Test name
Test status
Simulation time 60409528 ps
CPU time 0.81 seconds
Started Jun 13 12:35:56 PM PDT 24
Finished Jun 13 12:36:01 PM PDT 24
Peak memory 200412 kb
Host smart-35bd99ec-0645-4048-85b8-0e1e323bef9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916736530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3916736530
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.672534779
Short name T180
Test name
Test status
Simulation time 244410502 ps
CPU time 1.05 seconds
Started Jun 13 12:35:51 PM PDT 24
Finished Jun 13 12:35:55 PM PDT 24
Peak memory 217984 kb
Host smart-3efbf06f-be9b-4453-bd04-2af1bebcc8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672534779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.672534779
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2473503755
Short name T316
Test name
Test status
Simulation time 136246390 ps
CPU time 0.82 seconds
Started Jun 13 12:35:55 PM PDT 24
Finished Jun 13 12:36:00 PM PDT 24
Peak memory 200452 kb
Host smart-2a201872-ca26-474e-ad7b-d0fc3b51915a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473503755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2473503755
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.2042618729
Short name T504
Test name
Test status
Simulation time 1429004405 ps
CPU time 5.57 seconds
Started Jun 13 12:35:57 PM PDT 24
Finished Jun 13 12:36:07 PM PDT 24
Peak memory 200804 kb
Host smart-c4d94d9f-dd68-4af3-8ae7-37e215e1b0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042618729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2042618729
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1867433734
Short name T229
Test name
Test status
Simulation time 101409498 ps
CPU time 0.99 seconds
Started Jun 13 12:36:09 PM PDT 24
Finished Jun 13 12:36:12 PM PDT 24
Peak memory 200608 kb
Host smart-5acf57b8-b374-4612-82c9-a0aa56656be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867433734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1867433734
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.3525278110
Short name T235
Test name
Test status
Simulation time 113903046 ps
CPU time 1.19 seconds
Started Jun 13 12:35:55 PM PDT 24
Finished Jun 13 12:36:00 PM PDT 24
Peak memory 200808 kb
Host smart-30cb7d3d-cfdb-4db5-b0fa-18417d56cd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525278110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3525278110
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3844356978
Short name T198
Test name
Test status
Simulation time 1431378052 ps
CPU time 6.75 seconds
Started Jun 13 12:36:11 PM PDT 24
Finished Jun 13 12:36:21 PM PDT 24
Peak memory 208972 kb
Host smart-253e85f9-def7-4ee0-8afd-47bb2189f2fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844356978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3844356978
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3326354449
Short name T410
Test name
Test status
Simulation time 270455039 ps
CPU time 1.8 seconds
Started Jun 13 12:36:03 PM PDT 24
Finished Jun 13 12:36:08 PM PDT 24
Peak memory 200596 kb
Host smart-43b9bed3-197a-4bd8-a9d3-325c1d34db5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326354449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3326354449
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2087051728
Short name T215
Test name
Test status
Simulation time 90824030 ps
CPU time 0.91 seconds
Started Jun 13 12:36:11 PM PDT 24
Finished Jun 13 12:36:20 PM PDT 24
Peak memory 200672 kb
Host smart-f4fae37d-33fc-4d58-bd37-ed5285531132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087051728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2087051728
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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