Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7674

1

T3

18

T6

13

T10

15

auto[1]

10717

1

T2

4

T3

83

T4

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5672	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6242	1			T1	1		T2	2		T3	27
reset_info_cp[2]	2830	1			T2	1		T3	16		T4	1
reset_info_cp[4]	3712	1			T2	1		T3	17		T4	1
reset_info_cp[8]	134	1			T10	2		T30	1		T31	2
reset_info_cp[16]	96	1			T3	1		T11	1		T30	2
reset_info_cp[32]	108	1			T11	1		T13	1		T30	1
reset_info_cp[64]	110	1			T3	2		T14	1		T30	1
reset_info_cp[128]	107	1			T11	2		T14	1		T77	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2987	1			T3	18		T10	15		T30	17
reset_info_cp[1]	auto[1]	2635	1			T2	1		T3	8		T4	1
reset_info_cp[2]	auto[0]	870	1			T32	4		T46	8		T56	4
reset_info_cp[2]	auto[1]	1960	1			T2	1		T3	16		T4	1
reset_info_cp[4]	auto[0]	1286	1			T32	8		T46	22		T56	10
reset_info_cp[4]	auto[1]	2426	1			T2	1		T3	17		T4	1
reset_info_cp[8]	auto[0]	54	1			T32	1		T46	1		T80	1
reset_info_cp[8]	auto[1]	80	1			T10	2		T30	1		T31	2
reset_info_cp[16]	auto[0]	37	1			T11	1		T77	4		T133	1
reset_info_cp[16]	auto[1]	59	1			T3	1		T30	2		T50	1
reset_info_cp[32]	auto[0]	41	1			T11	1		T77	2		T88	3
reset_info_cp[32]	auto[1]	67	1			T13	1		T30	1		T31	1
reset_info_cp[64]	auto[0]	36	1			T88	3		T135	1		T141	1
reset_info_cp[64]	auto[1]	74	1			T3	2		T14	1		T30	1
reset_info_cp[128]	auto[0]	44	1			T11	2		T14	1		T77	1
reset_info_cp[128]	auto[1]	63	1			T88	2		T89	1		T90	1