Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T539 /workspace/coverage/default/2.rstmgr_stress_all.2061370462 Jun 21 05:12:14 PM PDT 24 Jun 21 05:12:51 PM PDT 24 10361403102 ps
T540 /workspace/coverage/default/37.rstmgr_smoke.1640987750 Jun 21 05:13:23 PM PDT 24 Jun 21 05:13:31 PM PDT 24 123106164 ps
T541 /workspace/coverage/default/12.rstmgr_por_stretcher.21597161 Jun 21 05:12:39 PM PDT 24 Jun 21 05:12:41 PM PDT 24 102688552 ps
T542 /workspace/coverage/default/32.rstmgr_alert_test.1022404850 Jun 21 05:13:17 PM PDT 24 Jun 21 05:13:23 PM PDT 24 72910679 ps
T543 /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.4059097327 Jun 21 05:12:35 PM PDT 24 Jun 21 05:12:38 PM PDT 24 244322242 ps
T59 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4154991346 Jun 21 05:11:12 PM PDT 24 Jun 21 05:11:16 PM PDT 24 898502098 ps
T60 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3917012031 Jun 21 05:11:38 PM PDT 24 Jun 21 05:11:41 PM PDT 24 220200271 ps
T61 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.4264163507 Jun 21 05:11:55 PM PDT 24 Jun 21 05:11:56 PM PDT 24 69815404 ps
T62 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.496587572 Jun 21 05:11:10 PM PDT 24 Jun 21 05:11:15 PM PDT 24 816948708 ps
T63 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3121170256 Jun 21 05:11:46 PM PDT 24 Jun 21 05:11:48 PM PDT 24 120360948 ps
T107 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3273898941 Jun 21 05:12:05 PM PDT 24 Jun 21 05:12:07 PM PDT 24 72284439 ps
T64 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3768051020 Jun 21 05:12:06 PM PDT 24 Jun 21 05:12:09 PM PDT 24 128288878 ps
T116 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2269886526 Jun 21 05:11:22 PM PDT 24 Jun 21 05:11:29 PM PDT 24 485199876 ps
T108 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3327159963 Jun 21 05:12:08 PM PDT 24 Jun 21 05:12:11 PM PDT 24 133831626 ps
T65 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1728399286 Jun 21 05:11:38 PM PDT 24 Jun 21 05:11:40 PM PDT 24 109524761 ps
T66 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3259285312 Jun 21 05:11:47 PM PDT 24 Jun 21 05:11:50 PM PDT 24 477870571 ps
T67 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1830752172 Jun 21 05:11:19 PM PDT 24 Jun 21 05:11:22 PM PDT 24 765832031 ps
T82 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.289233984 Jun 21 05:11:46 PM PDT 24 Jun 21 05:11:48 PM PDT 24 133700977 ps
T83 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1345443196 Jun 21 05:11:39 PM PDT 24 Jun 21 05:11:43 PM PDT 24 152705029 ps
T84 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2335117618 Jun 21 05:11:38 PM PDT 24 Jun 21 05:11:41 PM PDT 24 195698925 ps
T85 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.125588869 Jun 21 05:11:45 PM PDT 24 Jun 21 05:11:48 PM PDT 24 197239720 ps
T109 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.229261936 Jun 21 05:11:29 PM PDT 24 Jun 21 05:11:31 PM PDT 24 71857422 ps
T86 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2643546289 Jun 21 05:11:40 PM PDT 24 Jun 21 05:11:43 PM PDT 24 159029490 ps
T87 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3720338145 Jun 21 05:11:46 PM PDT 24 Jun 21 05:11:49 PM PDT 24 91075198 ps
T544 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1372078366 Jun 21 05:11:11 PM PDT 24 Jun 21 05:11:12 PM PDT 24 86231748 ps
T117 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1278074053 Jun 21 05:11:55 PM PDT 24 Jun 21 05:11:59 PM PDT 24 452626633 ps
T118 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1394789324 Jun 21 05:11:38 PM PDT 24 Jun 21 05:11:42 PM PDT 24 497319714 ps
T110 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.607433096 Jun 21 05:11:58 PM PDT 24 Jun 21 05:12:01 PM PDT 24 223081170 ps
T111 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3389590399 Jun 21 05:11:36 PM PDT 24 Jun 21 05:11:38 PM PDT 24 73819793 ps
T545 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.89386133 Jun 21 05:11:21 PM PDT 24 Jun 21 05:11:32 PM PDT 24 2297135517 ps
T112 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.4085648589 Jun 21 05:11:45 PM PDT 24 Jun 21 05:11:46 PM PDT 24 86897834 ps
T546 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1370399289 Jun 21 05:11:30 PM PDT 24 Jun 21 05:11:33 PM PDT 24 353989571 ps
T119 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3988208572 Jun 21 05:11:58 PM PDT 24 Jun 21 05:12:02 PM PDT 24 325694865 ps
T547 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3312822127 Jun 21 05:11:48 PM PDT 24 Jun 21 05:11:50 PM PDT 24 180077654 ps
T120 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1709607819 Jun 21 05:11:26 PM PDT 24 Jun 21 05:11:30 PM PDT 24 795583192 ps
T127 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2832380585 Jun 21 05:11:11 PM PDT 24 Jun 21 05:11:15 PM PDT 24 379741669 ps
T113 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.4082893515 Jun 21 05:11:55 PM PDT 24 Jun 21 05:11:58 PM PDT 24 59828335 ps
T548 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2193013022 Jun 21 05:11:54 PM PDT 24 Jun 21 05:11:55 PM PDT 24 140820296 ps
T140 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2853607870 Jun 21 05:11:46 PM PDT 24 Jun 21 05:11:51 PM PDT 24 960251487 ps
T123 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.588309376 Jun 21 05:11:37 PM PDT 24 Jun 21 05:11:41 PM PDT 24 921910705 ps
T114 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.4098485817 Jun 21 05:11:54 PM PDT 24 Jun 21 05:11:57 PM PDT 24 140290789 ps
T128 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1297487954 Jun 21 05:11:20 PM PDT 24 Jun 21 05:11:23 PM PDT 24 179236536 ps
T549 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1212427203 Jun 21 05:11:55 PM PDT 24 Jun 21 05:11:58 PM PDT 24 107622810 ps
T550 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1909760044 Jun 21 05:11:12 PM PDT 24 Jun 21 05:11:15 PM PDT 24 161152130 ps
T551 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1075339859 Jun 21 05:11:36 PM PDT 24 Jun 21 05:11:40 PM PDT 24 403203817 ps
T552 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2322331978 Jun 21 05:11:19 PM PDT 24 Jun 21 05:11:21 PM PDT 24 154897633 ps
T553 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.4051180308 Jun 21 05:11:56 PM PDT 24 Jun 21 05:11:59 PM PDT 24 157496673 ps
T554 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3503901235 Jun 21 05:11:21 PM PDT 24 Jun 21 05:11:22 PM PDT 24 65240079 ps
T555 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2312322135 Jun 21 05:11:19 PM PDT 24 Jun 21 05:11:21 PM PDT 24 147358939 ps
T556 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.4264900510 Jun 21 05:11:54 PM PDT 24 Jun 21 05:11:56 PM PDT 24 119360945 ps
T96 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.618173500 Jun 21 05:12:04 PM PDT 24 Jun 21 05:12:06 PM PDT 24 64281053 ps
T557 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2742219984 Jun 21 05:11:39 PM PDT 24 Jun 21 05:11:42 PM PDT 24 63913131 ps
T558 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3883710193 Jun 21 05:11:47 PM PDT 24 Jun 21 05:11:51 PM PDT 24 182999718 ps
T559 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.843587112 Jun 21 05:11:21 PM PDT 24 Jun 21 05:11:23 PM PDT 24 203023143 ps
T560 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2516968526 Jun 21 05:11:55 PM PDT 24 Jun 21 05:12:00 PM PDT 24 559697333 ps
T561 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1155842499 Jun 21 05:11:20 PM PDT 24 Jun 21 05:11:22 PM PDT 24 236411343 ps
T125 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3450121381 Jun 21 05:11:38 PM PDT 24 Jun 21 05:11:42 PM PDT 24 939408087 ps
T562 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.218812137 Jun 21 05:11:57 PM PDT 24 Jun 21 05:12:00 PM PDT 24 71860441 ps
T563 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1613790341 Jun 21 05:11:28 PM PDT 24 Jun 21 05:11:30 PM PDT 24 120022696 ps
T564 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3041804125 Jun 21 05:11:21 PM PDT 24 Jun 21 05:11:23 PM PDT 24 73906143 ps
T565 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3563654453 Jun 21 05:11:37 PM PDT 24 Jun 21 05:11:39 PM PDT 24 122075961 ps
T566 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1477933040 Jun 21 05:11:29 PM PDT 24 Jun 21 05:11:31 PM PDT 24 126200409 ps
T567 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2891687797 Jun 21 05:11:30 PM PDT 24 Jun 21 05:11:33 PM PDT 24 418534407 ps
T568 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4253994044 Jun 21 05:11:58 PM PDT 24 Jun 21 05:12:02 PM PDT 24 162692333 ps
T124 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.322718415 Jun 21 05:11:56 PM PDT 24 Jun 21 05:12:00 PM PDT 24 417998636 ps
T569 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1481386479 Jun 21 05:11:54 PM PDT 24 Jun 21 05:11:57 PM PDT 24 430115685 ps
T570 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1744826812 Jun 21 05:11:44 PM PDT 24 Jun 21 05:11:46 PM PDT 24 80028911 ps
T571 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3104656973 Jun 21 05:12:05 PM PDT 24 Jun 21 05:12:07 PM PDT 24 176371432 ps
T572 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1491011617 Jun 21 05:11:26 PM PDT 24 Jun 21 05:11:28 PM PDT 24 116155127 ps
T121 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.872632254 Jun 21 05:12:06 PM PDT 24 Jun 21 05:12:11 PM PDT 24 896989883 ps
T126 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1941992204 Jun 21 05:11:57 PM PDT 24 Jun 21 05:12:02 PM PDT 24 876075336 ps
T573 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.4070151726 Jun 21 05:11:48 PM PDT 24 Jun 21 05:11:50 PM PDT 24 225574402 ps
T574 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1341259308 Jun 21 05:11:54 PM PDT 24 Jun 21 05:11:56 PM PDT 24 103363133 ps
T575 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.759131797 Jun 21 05:12:05 PM PDT 24 Jun 21 05:12:08 PM PDT 24 119038595 ps
T576 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3175880787 Jun 21 05:11:38 PM PDT 24 Jun 21 05:11:40 PM PDT 24 456901608 ps
T577 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2912932167 Jun 21 05:11:54 PM PDT 24 Jun 21 05:11:56 PM PDT 24 83279052 ps
T578 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2165613291 Jun 21 05:11:32 PM PDT 24 Jun 21 05:11:33 PM PDT 24 126163558 ps
T579 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3295660165 Jun 21 05:11:44 PM PDT 24 Jun 21 05:11:46 PM PDT 24 125537332 ps
T580 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2642117942 Jun 21 05:11:55 PM PDT 24 Jun 21 05:12:00 PM PDT 24 782331616 ps
T581 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3450319811 Jun 21 05:11:20 PM PDT 24 Jun 21 05:11:22 PM PDT 24 108492572 ps
T582 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2690703868 Jun 21 05:11:45 PM PDT 24 Jun 21 05:11:48 PM PDT 24 265036093 ps
T583 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2042762283 Jun 21 05:11:18 PM PDT 24 Jun 21 05:11:20 PM PDT 24 103862637 ps
T584 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2945687388 Jun 21 05:11:55 PM PDT 24 Jun 21 05:11:58 PM PDT 24 115570494 ps
T585 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.4002009615 Jun 21 05:11:27 PM PDT 24 Jun 21 05:11:28 PM PDT 24 78410641 ps
T586 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.821130222 Jun 21 05:11:21 PM PDT 24 Jun 21 05:11:23 PM PDT 24 436743109 ps
T587 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3419163783 Jun 21 05:12:07 PM PDT 24 Jun 21 05:12:12 PM PDT 24 877493326 ps
T588 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.241837890 Jun 21 05:11:54 PM PDT 24 Jun 21 05:11:56 PM PDT 24 193689375 ps
T589 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2712469751 Jun 21 05:11:58 PM PDT 24 Jun 21 05:12:01 PM PDT 24 56113632 ps
T590 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3863788503 Jun 21 05:11:19 PM PDT 24 Jun 21 05:11:23 PM PDT 24 510989424 ps
T591 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1954827711 Jun 21 05:11:38 PM PDT 24 Jun 21 05:11:40 PM PDT 24 57615458 ps
T592 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3087371576 Jun 21 05:11:54 PM PDT 24 Jun 21 05:11:57 PM PDT 24 929545287 ps
T122 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3194372227 Jun 21 05:11:27 PM PDT 24 Jun 21 05:11:30 PM PDT 24 465030124 ps
T593 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1742155890 Jun 21 05:11:19 PM PDT 24 Jun 21 05:11:21 PM PDT 24 175148023 ps
T594 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3832408616 Jun 21 05:11:21 PM PDT 24 Jun 21 05:11:23 PM PDT 24 110416236 ps
T595 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3735562463 Jun 21 05:11:19 PM PDT 24 Jun 21 05:11:21 PM PDT 24 158332493 ps
T596 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1038490979 Jun 21 05:11:27 PM PDT 24 Jun 21 05:11:31 PM PDT 24 456863838 ps
T597 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.488874672 Jun 21 05:11:37 PM PDT 24 Jun 21 05:11:38 PM PDT 24 88205066 ps
T598 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2009837464 Jun 21 05:11:39 PM PDT 24 Jun 21 05:11:43 PM PDT 24 339205028 ps
T599 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.4017033294 Jun 21 05:11:36 PM PDT 24 Jun 21 05:11:40 PM PDT 24 952374138 ps
T600 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1677380381 Jun 21 05:11:17 PM PDT 24 Jun 21 05:11:19 PM PDT 24 168072757 ps
T601 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3005641216 Jun 21 05:11:48 PM PDT 24 Jun 21 05:11:51 PM PDT 24 196742073 ps
T602 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2327107951 Jun 21 05:11:46 PM PDT 24 Jun 21 05:11:49 PM PDT 24 149238848 ps
T603 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1674116606 Jun 21 05:11:36 PM PDT 24 Jun 21 05:11:37 PM PDT 24 76580643 ps
T604 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.428353334 Jun 21 05:11:39 PM PDT 24 Jun 21 05:11:42 PM PDT 24 79065197 ps
T605 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1010127756 Jun 21 05:11:39 PM PDT 24 Jun 21 05:11:43 PM PDT 24 936579359 ps
T606 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.89871250 Jun 21 05:11:47 PM PDT 24 Jun 21 05:11:50 PM PDT 24 473121599 ps
T607 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.978652999 Jun 21 05:11:12 PM PDT 24 Jun 21 05:11:14 PM PDT 24 58949805 ps
T608 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2488226786 Jun 21 05:12:04 PM PDT 24 Jun 21 05:12:09 PM PDT 24 548818456 ps
T609 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2407698694 Jun 21 05:11:28 PM PDT 24 Jun 21 05:11:34 PM PDT 24 478956259 ps
T610 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2654846387 Jun 21 05:11:55 PM PDT 24 Jun 21 05:11:58 PM PDT 24 190358020 ps
T611 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.513720143 Jun 21 05:11:54 PM PDT 24 Jun 21 05:11:56 PM PDT 24 194410207 ps
T612 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.171441555 Jun 21 05:11:28 PM PDT 24 Jun 21 05:11:30 PM PDT 24 103614931 ps
T613 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3884534634 Jun 21 05:11:55 PM PDT 24 Jun 21 05:11:58 PM PDT 24 305702823 ps
T614 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.608434275 Jun 21 05:11:30 PM PDT 24 Jun 21 05:11:33 PM PDT 24 358957394 ps
T615 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.4059767875 Jun 21 05:11:47 PM PDT 24 Jun 21 05:11:49 PM PDT 24 62118846 ps
T616 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3144472471 Jun 21 05:11:38 PM PDT 24 Jun 21 05:11:41 PM PDT 24 257733821 ps
T617 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4131703874 Jun 21 05:11:30 PM PDT 24 Jun 21 05:11:37 PM PDT 24 489903778 ps
T618 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.424692904 Jun 21 05:11:29 PM PDT 24 Jun 21 05:11:31 PM PDT 24 93747288 ps
T619 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2235846358 Jun 21 05:11:22 PM PDT 24 Jun 21 05:11:27 PM PDT 24 202917219 ps
T620 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3465646200 Jun 21 05:11:38 PM PDT 24 Jun 21 05:11:40 PM PDT 24 73693640 ps

Test location /workspace/coverage/default/10.rstmgr_smoke.38381095
Short name T2
Test name
Test status
Simulation time 129158031 ps
CPU time 1.15 seconds
Started Jun 21 05:12:34 PM PDT 24
Finished Jun 21 05:12:37 PM PDT 24
Peak memory 200800 kb
Host smart-353ade17-6c55-48d0-bfd4-52e1f1b12588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38381095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.38381095
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1085325678
Short name T27
Test name
Test status
Simulation time 418579819 ps
CPU time 2.27 seconds
Started Jun 21 05:12:49 PM PDT 24
Finished Jun 21 05:12:54 PM PDT 24
Peak memory 200676 kb
Host smart-26d711b7-6943-4587-b731-977907cd2443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085325678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1085325678
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1855853979
Short name T32
Test name
Test status
Simulation time 1766797240 ps
CPU time 6.55 seconds
Started Jun 21 05:13:25 PM PDT 24
Finished Jun 21 05:13:37 PM PDT 24
Peak memory 200864 kb
Host smart-b984188f-61d1-46d3-abe2-e85864f076c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855853979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1855853979
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4154991346
Short name T59
Test name
Test status
Simulation time 898502098 ps
CPU time 2.93 seconds
Started Jun 21 05:11:12 PM PDT 24
Finished Jun 21 05:11:16 PM PDT 24
Peak memory 200728 kb
Host smart-c9206caf-3e8f-4e6b-ac50-f0e0fd87c650
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154991346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.4154991346
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2853887324
Short name T55
Test name
Test status
Simulation time 16528035881 ps
CPU time 33.09 seconds
Started Jun 21 05:12:17 PM PDT 24
Finished Jun 21 05:12:52 PM PDT 24
Peak memory 218668 kb
Host smart-8a8e5a23-4a68-4f82-95b9-9aab138da475
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853887324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2853887324
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.507010662
Short name T3
Test name
Test status
Simulation time 2183388623 ps
CPU time 8.23 seconds
Started Jun 21 05:13:22 PM PDT 24
Finished Jun 21 05:13:37 PM PDT 24
Peak memory 218548 kb
Host smart-bc4377f6-bb84-4891-b8bc-179571a4f0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507010662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.507010662
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1278074053
Short name T117
Test name
Test status
Simulation time 452626633 ps
CPU time 2.92 seconds
Started Jun 21 05:11:55 PM PDT 24
Finished Jun 21 05:11:59 PM PDT 24
Peak memory 209056 kb
Host smart-4ecd8974-424e-4812-bc27-6e018c76a21f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278074053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1278074053
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2588848601
Short name T88
Test name
Test status
Simulation time 7683391665 ps
CPU time 33.96 seconds
Started Jun 21 05:12:32 PM PDT 24
Finished Jun 21 05:13:08 PM PDT 24
Peak memory 209248 kb
Host smart-accdf43b-e957-4096-a1fa-a3118d558f59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588848601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2588848601
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3113409604
Short name T11
Test name
Test status
Simulation time 139067040 ps
CPU time 1.06 seconds
Started Jun 21 05:12:35 PM PDT 24
Finished Jun 21 05:12:38 PM PDT 24
Peak memory 200676 kb
Host smart-54bdb3e4-67cc-4b76-98d3-74e2cc2e2202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113409604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3113409604
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2276493103
Short name T75
Test name
Test status
Simulation time 166080592 ps
CPU time 1.15 seconds
Started Jun 21 05:12:05 PM PDT 24
Finished Jun 21 05:12:07 PM PDT 24
Peak memory 200680 kb
Host smart-35b71992-c6b4-41e5-bdf5-7aa4f2cbce4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276493103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2276493103
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2736241303
Short name T37
Test name
Test status
Simulation time 1904675627 ps
CPU time 7.34 seconds
Started Jun 21 05:13:08 PM PDT 24
Finished Jun 21 05:13:19 PM PDT 24
Peak memory 218428 kb
Host smart-0d280a8e-0f6c-4583-909e-92c36f8f055d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736241303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2736241303
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3553883004
Short name T165
Test name
Test status
Simulation time 74740648 ps
CPU time 0.77 seconds
Started Jun 21 05:12:06 PM PDT 24
Finished Jun 21 05:12:09 PM PDT 24
Peak memory 200464 kb
Host smart-37b4ef59-03e1-421a-8499-cf57a4653ca7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553883004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3553883004
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1075339859
Short name T551
Test name
Test status
Simulation time 403203817 ps
CPU time 2.73 seconds
Started Jun 21 05:11:36 PM PDT 24
Finished Jun 21 05:11:40 PM PDT 24
Peak memory 209028 kb
Host smart-d065b0e8-381e-4e7b-963d-69bdf6d07703
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075339859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1075339859
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.2857795007
Short name T31
Test name
Test status
Simulation time 1231500788 ps
CPU time 5.54 seconds
Started Jun 21 05:13:40 PM PDT 24
Finished Jun 21 05:13:48 PM PDT 24
Peak memory 218384 kb
Host smart-6f5927cb-810e-4691-91d6-8d3243a8cb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857795007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2857795007
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1941992204
Short name T126
Test name
Test status
Simulation time 876075336 ps
CPU time 3.07 seconds
Started Jun 21 05:11:57 PM PDT 24
Finished Jun 21 05:12:02 PM PDT 24
Peak memory 200964 kb
Host smart-63a00670-8466-492e-bc20-4c81f316e6c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941992204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1941992204
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.872632254
Short name T121
Test name
Test status
Simulation time 896989883 ps
CPU time 2.92 seconds
Started Jun 21 05:12:06 PM PDT 24
Finished Jun 21 05:12:11 PM PDT 24
Peak memory 200864 kb
Host smart-8e56d164-108a-4a9c-8a8d-5edb98ae45ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872632254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.872632254
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.4085648589
Short name T112
Test name
Test status
Simulation time 86897834 ps
CPU time 0.84 seconds
Started Jun 21 05:11:45 PM PDT 24
Finished Jun 21 05:11:46 PM PDT 24
Peak memory 200628 kb
Host smart-92e0ab00-c1b4-4355-8718-587575b8146d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085648589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.4085648589
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2622879441
Short name T23
Test name
Test status
Simulation time 123531001 ps
CPU time 0.77 seconds
Started Jun 21 05:12:41 PM PDT 24
Finished Jun 21 05:12:44 PM PDT 24
Peak memory 200448 kb
Host smart-54a3ba64-3e11-4de7-bfe1-03a94f01a73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622879441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2622879441
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2022360308
Short name T183
Test name
Test status
Simulation time 146822792 ps
CPU time 1.82 seconds
Started Jun 21 05:12:06 PM PDT 24
Finished Jun 21 05:12:10 PM PDT 24
Peak memory 200664 kb
Host smart-23b1b8c3-0054-4d5c-9922-3ab1b2b22de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022360308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2022360308
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1909760044
Short name T550
Test name
Test status
Simulation time 161152130 ps
CPU time 2.02 seconds
Started Jun 21 05:11:12 PM PDT 24
Finished Jun 21 05:11:15 PM PDT 24
Peak memory 200960 kb
Host smart-5eda74ac-8e46-46ca-8e88-770f7831595c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909760044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.1
909760044
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.496587572
Short name T62
Test name
Test status
Simulation time 816948708 ps
CPU time 4.55 seconds
Started Jun 21 05:11:10 PM PDT 24
Finished Jun 21 05:11:15 PM PDT 24
Peak memory 200792 kb
Host smart-961c240b-4d9a-4502-9639-237a8ebf6576
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496587572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.496587572
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1372078366
Short name T544
Test name
Test status
Simulation time 86231748 ps
CPU time 0.77 seconds
Started Jun 21 05:11:11 PM PDT 24
Finished Jun 21 05:11:12 PM PDT 24
Peak memory 200704 kb
Host smart-9511ae13-e40e-43b0-841f-f82733161668
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372078366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
372078366
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1742155890
Short name T593
Test name
Test status
Simulation time 175148023 ps
CPU time 1.22 seconds
Started Jun 21 05:11:19 PM PDT 24
Finished Jun 21 05:11:21 PM PDT 24
Peak memory 208840 kb
Host smart-fe4f7881-f84d-4951-b987-f0906d5617bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742155890 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1742155890
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.978652999
Short name T607
Test name
Test status
Simulation time 58949805 ps
CPU time 0.77 seconds
Started Jun 21 05:11:12 PM PDT 24
Finished Jun 21 05:11:14 PM PDT 24
Peak memory 200556 kb
Host smart-edf86038-edd2-4d5f-b429-e114c9d78d80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978652999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.978652999
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3450319811
Short name T581
Test name
Test status
Simulation time 108492572 ps
CPU time 1.21 seconds
Started Jun 21 05:11:20 PM PDT 24
Finished Jun 21 05:11:22 PM PDT 24
Peak memory 200832 kb
Host smart-2f66e041-16c5-4644-887d-1b5a134a34cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450319811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3450319811
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2832380585
Short name T127
Test name
Test status
Simulation time 379741669 ps
CPU time 2.8 seconds
Started Jun 21 05:11:11 PM PDT 24
Finished Jun 21 05:11:15 PM PDT 24
Peak memory 209044 kb
Host smart-a664ed71-fa99-4bf5-aec5-a24972e23294
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832380585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2832380585
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.843587112
Short name T559
Test name
Test status
Simulation time 203023143 ps
CPU time 1.53 seconds
Started Jun 21 05:11:21 PM PDT 24
Finished Jun 21 05:11:23 PM PDT 24
Peak memory 200888 kb
Host smart-8bc27ac3-0e7f-40ce-8152-b05e8c3372b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843587112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.843587112
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.89386133
Short name T545
Test name
Test status
Simulation time 2297135517 ps
CPU time 10.06 seconds
Started Jun 21 05:11:21 PM PDT 24
Finished Jun 21 05:11:32 PM PDT 24
Peak memory 200876 kb
Host smart-c9249025-9c04-4161-a2ba-1949eb8991d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89386133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.89386133
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2312322135
Short name T555
Test name
Test status
Simulation time 147358939 ps
CPU time 1.03 seconds
Started Jun 21 05:11:19 PM PDT 24
Finished Jun 21 05:11:21 PM PDT 24
Peak memory 200696 kb
Host smart-7cd57d74-1f42-46b4-be6f-9c43776e13f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312322135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
312322135
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3832408616
Short name T594
Test name
Test status
Simulation time 110416236 ps
CPU time 1.03 seconds
Started Jun 21 05:11:21 PM PDT 24
Finished Jun 21 05:11:23 PM PDT 24
Peak memory 208816 kb
Host smart-7eb3a6fd-8a96-4c71-a22d-4ec1bcd6b4af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832408616 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3832408616
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3503901235
Short name T554
Test name
Test status
Simulation time 65240079 ps
CPU time 0.8 seconds
Started Jun 21 05:11:21 PM PDT 24
Finished Jun 21 05:11:22 PM PDT 24
Peak memory 200568 kb
Host smart-286474d8-e8e5-47b5-a24f-1671a6b48b72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503901235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3503901235
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2322331978
Short name T552
Test name
Test status
Simulation time 154897633 ps
CPU time 1.12 seconds
Started Jun 21 05:11:19 PM PDT 24
Finished Jun 21 05:11:21 PM PDT 24
Peak memory 200572 kb
Host smart-c3aa9cdf-a3a4-4569-9424-2e36c9f2b501
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322331978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2322331978
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2235846358
Short name T619
Test name
Test status
Simulation time 202917219 ps
CPU time 2.78 seconds
Started Jun 21 05:11:22 PM PDT 24
Finished Jun 21 05:11:27 PM PDT 24
Peak memory 208952 kb
Host smart-acd07c14-e461-4fb9-8246-a310541963ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235846358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2235846358
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1830752172
Short name T67
Test name
Test status
Simulation time 765832031 ps
CPU time 2.63 seconds
Started Jun 21 05:11:19 PM PDT 24
Finished Jun 21 05:11:22 PM PDT 24
Peak memory 200764 kb
Host smart-b47c3c23-0e17-4bcd-81a5-3530351a4851
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830752172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1830752172
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.289233984
Short name T82
Test name
Test status
Simulation time 133700977 ps
CPU time 1.09 seconds
Started Jun 21 05:11:46 PM PDT 24
Finished Jun 21 05:11:48 PM PDT 24
Peak memory 209016 kb
Host smart-311289cc-d7b7-4302-b444-006e5a9eb266
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289233984 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.289233984
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1744826812
Short name T570
Test name
Test status
Simulation time 80028911 ps
CPU time 0.85 seconds
Started Jun 21 05:11:44 PM PDT 24
Finished Jun 21 05:11:46 PM PDT 24
Peak memory 200592 kb
Host smart-ddbc2bd5-a566-4c96-8bee-75b12b503fa5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744826812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1744826812
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.4070151726
Short name T573
Test name
Test status
Simulation time 225574402 ps
CPU time 1.55 seconds
Started Jun 21 05:11:48 PM PDT 24
Finished Jun 21 05:11:50 PM PDT 24
Peak memory 200832 kb
Host smart-61fd8ddd-fa0a-473e-9a7f-e85b52b1a511
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070151726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.4070151726
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.125588869
Short name T85
Test name
Test status
Simulation time 197239720 ps
CPU time 2.62 seconds
Started Jun 21 05:11:45 PM PDT 24
Finished Jun 21 05:11:48 PM PDT 24
Peak memory 208980 kb
Host smart-bd945b26-40d8-4d0e-a964-be04f8745b91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125588869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.125588869
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2853607870
Short name T140
Test name
Test status
Simulation time 960251487 ps
CPU time 3.06 seconds
Started Jun 21 05:11:46 PM PDT 24
Finished Jun 21 05:11:51 PM PDT 24
Peak memory 200868 kb
Host smart-ff9b004f-eaa8-4ac1-bf1c-6f0c48231a5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853607870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2853607870
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3121170256
Short name T63
Test name
Test status
Simulation time 120360948 ps
CPU time 1.28 seconds
Started Jun 21 05:11:46 PM PDT 24
Finished Jun 21 05:11:48 PM PDT 24
Peak memory 208884 kb
Host smart-c71d0e7d-1702-404e-bf6c-f3be989d8a04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121170256 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3121170256
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3295660165
Short name T579
Test name
Test status
Simulation time 125537332 ps
CPU time 1.19 seconds
Started Jun 21 05:11:44 PM PDT 24
Finished Jun 21 05:11:46 PM PDT 24
Peak memory 200756 kb
Host smart-1f25b34b-a8b5-4fe2-a17f-b590b881ca70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295660165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.3295660165
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3720338145
Short name T87
Test name
Test status
Simulation time 91075198 ps
CPU time 1.17 seconds
Started Jun 21 05:11:46 PM PDT 24
Finished Jun 21 05:11:49 PM PDT 24
Peak memory 208952 kb
Host smart-4d726ab0-7f98-4946-bb45-0e7cb46ee8b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720338145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3720338145
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3259285312
Short name T66
Test name
Test status
Simulation time 477870571 ps
CPU time 1.89 seconds
Started Jun 21 05:11:47 PM PDT 24
Finished Jun 21 05:11:50 PM PDT 24
Peak memory 200892 kb
Host smart-efad283c-7e94-4131-963b-932a68d2faf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259285312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.3259285312
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3312822127
Short name T547
Test name
Test status
Simulation time 180077654 ps
CPU time 1.11 seconds
Started Jun 21 05:11:48 PM PDT 24
Finished Jun 21 05:11:50 PM PDT 24
Peak memory 208816 kb
Host smart-fb17acf5-a13b-42f7-b405-ec632ef4df07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312822127 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3312822127
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.4059767875
Short name T615
Test name
Test status
Simulation time 62118846 ps
CPU time 0.79 seconds
Started Jun 21 05:11:47 PM PDT 24
Finished Jun 21 05:11:49 PM PDT 24
Peak memory 200560 kb
Host smart-33857336-f8e5-48a2-a0ad-b5b0ae035998
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059767875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.4059767875
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2690703868
Short name T582
Test name
Test status
Simulation time 265036093 ps
CPU time 1.62 seconds
Started Jun 21 05:11:45 PM PDT 24
Finished Jun 21 05:11:48 PM PDT 24
Peak memory 200740 kb
Host smart-717afd99-95a8-4263-aa19-67d7382ea715
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690703868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.2690703868
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3883710193
Short name T558
Test name
Test status
Simulation time 182999718 ps
CPU time 2.64 seconds
Started Jun 21 05:11:47 PM PDT 24
Finished Jun 21 05:11:51 PM PDT 24
Peak memory 217020 kb
Host smart-74fe6320-4e92-48f0-973c-58cb6fcf27c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883710193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3883710193
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.89871250
Short name T606
Test name
Test status
Simulation time 473121599 ps
CPU time 1.94 seconds
Started Jun 21 05:11:47 PM PDT 24
Finished Jun 21 05:11:50 PM PDT 24
Peak memory 200940 kb
Host smart-611a1cb5-6bb7-4437-bd0d-f71da4f7ff5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89871250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err.89871250
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4253994044
Short name T568
Test name
Test status
Simulation time 162692333 ps
CPU time 1.51 seconds
Started Jun 21 05:11:58 PM PDT 24
Finished Jun 21 05:12:02 PM PDT 24
Peak memory 209208 kb
Host smart-a2f94be8-f115-4a4c-b293-a4974b25d9ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253994044 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.4253994044
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2712469751
Short name T589
Test name
Test status
Simulation time 56113632 ps
CPU time 0.8 seconds
Started Jun 21 05:11:58 PM PDT 24
Finished Jun 21 05:12:01 PM PDT 24
Peak memory 200580 kb
Host smart-7054166d-79fa-4ded-ad59-e003d5c53ffb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712469751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2712469751
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.4098485817
Short name T114
Test name
Test status
Simulation time 140290789 ps
CPU time 1.13 seconds
Started Jun 21 05:11:54 PM PDT 24
Finished Jun 21 05:11:57 PM PDT 24
Peak memory 200540 kb
Host smart-5c661f05-bd91-4ae4-9c6f-d238150579ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098485817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.4098485817
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3884534634
Short name T613
Test name
Test status
Simulation time 305702823 ps
CPU time 2.04 seconds
Started Jun 21 05:11:55 PM PDT 24
Finished Jun 21 05:11:58 PM PDT 24
Peak memory 208964 kb
Host smart-38295ec5-bb70-4492-8202-21df9c95fee7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884534634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3884534634
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1341259308
Short name T574
Test name
Test status
Simulation time 103363133 ps
CPU time 0.94 seconds
Started Jun 21 05:11:54 PM PDT 24
Finished Jun 21 05:11:56 PM PDT 24
Peak memory 200680 kb
Host smart-c5fce72e-14d7-44a9-9c1f-8a08cc1dc042
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341259308 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.1341259308
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2912932167
Short name T577
Test name
Test status
Simulation time 83279052 ps
CPU time 0.82 seconds
Started Jun 21 05:11:54 PM PDT 24
Finished Jun 21 05:11:56 PM PDT 24
Peak memory 200652 kb
Host smart-843599f6-da04-4ee6-bb79-438171b6be07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912932167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2912932167
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.4264900510
Short name T556
Test name
Test status
Simulation time 119360945 ps
CPU time 1 seconds
Started Jun 21 05:11:54 PM PDT 24
Finished Jun 21 05:11:56 PM PDT 24
Peak memory 200548 kb
Host smart-0b29d426-3a34-447a-8273-fdd71ead82ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264900510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.4264900510
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2516968526
Short name T560
Test name
Test status
Simulation time 559697333 ps
CPU time 3.85 seconds
Started Jun 21 05:11:55 PM PDT 24
Finished Jun 21 05:12:00 PM PDT 24
Peak memory 212432 kb
Host smart-36a77989-8bcb-49ad-806f-a7dc2053c0c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516968526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2516968526
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3087371576
Short name T592
Test name
Test status
Simulation time 929545287 ps
CPU time 2.79 seconds
Started Jun 21 05:11:54 PM PDT 24
Finished Jun 21 05:11:57 PM PDT 24
Peak memory 200964 kb
Host smart-f5d1b23b-9289-4eff-bc4b-bef802f24e0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087371576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3087371576
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2193013022
Short name T548
Test name
Test status
Simulation time 140820296 ps
CPU time 1.07 seconds
Started Jun 21 05:11:54 PM PDT 24
Finished Jun 21 05:11:55 PM PDT 24
Peak memory 208792 kb
Host smart-06374f1c-b810-4bfa-9355-1df95bd30b70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193013022 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2193013022
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.218812137
Short name T562
Test name
Test status
Simulation time 71860441 ps
CPU time 0.82 seconds
Started Jun 21 05:11:57 PM PDT 24
Finished Jun 21 05:12:00 PM PDT 24
Peak memory 200636 kb
Host smart-1acf22e1-7a8f-432e-8c39-822b0f5340d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218812137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.218812137
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1212427203
Short name T549
Test name
Test status
Simulation time 107622810 ps
CPU time 1.31 seconds
Started Jun 21 05:11:55 PM PDT 24
Finished Jun 21 05:11:58 PM PDT 24
Peak memory 200728 kb
Host smart-957f4689-e94a-44d4-828e-1dc6faaa8b7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212427203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1212427203
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2945687388
Short name T584
Test name
Test status
Simulation time 115570494 ps
CPU time 1.5 seconds
Started Jun 21 05:11:55 PM PDT 24
Finished Jun 21 05:11:58 PM PDT 24
Peak memory 208992 kb
Host smart-3370c1e8-943c-4af1-9cbc-8cd0e19fd363
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945687388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2945687388
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2642117942
Short name T580
Test name
Test status
Simulation time 782331616 ps
CPU time 3.13 seconds
Started Jun 21 05:11:55 PM PDT 24
Finished Jun 21 05:12:00 PM PDT 24
Peak memory 200780 kb
Host smart-211e2a75-2638-45bc-9d08-21751f66eef1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642117942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.2642117942
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2654846387
Short name T610
Test name
Test status
Simulation time 190358020 ps
CPU time 1.17 seconds
Started Jun 21 05:11:55 PM PDT 24
Finished Jun 21 05:11:58 PM PDT 24
Peak memory 208880 kb
Host smart-8626a7de-9f4c-4180-ab25-73c09b33b64e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654846387 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2654846387
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.4264163507
Short name T61
Test name
Test status
Simulation time 69815404 ps
CPU time 0.78 seconds
Started Jun 21 05:11:55 PM PDT 24
Finished Jun 21 05:11:56 PM PDT 24
Peak memory 200644 kb
Host smart-b56d755f-d651-4e59-a9e6-6fe8d0aa1288
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264163507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.4264163507
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.4051180308
Short name T553
Test name
Test status
Simulation time 157496673 ps
CPU time 1.3 seconds
Started Jun 21 05:11:56 PM PDT 24
Finished Jun 21 05:11:59 PM PDT 24
Peak memory 200628 kb
Host smart-7050e00b-e0ba-4b96-a3d6-c31e6d9ccc52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051180308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.4051180308
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.241837890
Short name T588
Test name
Test status
Simulation time 193689375 ps
CPU time 1.41 seconds
Started Jun 21 05:11:54 PM PDT 24
Finished Jun 21 05:11:56 PM PDT 24
Peak memory 208812 kb
Host smart-987a2ff0-8344-4a66-97db-798046298a69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241837890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.241837890
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1481386479
Short name T569
Test name
Test status
Simulation time 430115685 ps
CPU time 1.73 seconds
Started Jun 21 05:11:54 PM PDT 24
Finished Jun 21 05:11:57 PM PDT 24
Peak memory 200884 kb
Host smart-8a61af18-e124-404e-bcbc-41842f2fe1eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481386479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1481386479
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.513720143
Short name T611
Test name
Test status
Simulation time 194410207 ps
CPU time 1.32 seconds
Started Jun 21 05:11:54 PM PDT 24
Finished Jun 21 05:11:56 PM PDT 24
Peak memory 208764 kb
Host smart-ea1703e9-546b-4383-a1a3-046bd48e80e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513720143 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.513720143
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.4082893515
Short name T113
Test name
Test status
Simulation time 59828335 ps
CPU time 0.83 seconds
Started Jun 21 05:11:55 PM PDT 24
Finished Jun 21 05:11:58 PM PDT 24
Peak memory 200612 kb
Host smart-2fabc90c-2bac-4765-ac7d-bc1cc4c7d561
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082893515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.4082893515
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.607433096
Short name T110
Test name
Test status
Simulation time 223081170 ps
CPU time 1.42 seconds
Started Jun 21 05:11:58 PM PDT 24
Finished Jun 21 05:12:01 PM PDT 24
Peak memory 200796 kb
Host smart-1255b69e-a65a-4310-9e2e-5923e74c33ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607433096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.607433096
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3988208572
Short name T119
Test name
Test status
Simulation time 325694865 ps
CPU time 2.24 seconds
Started Jun 21 05:11:58 PM PDT 24
Finished Jun 21 05:12:02 PM PDT 24
Peak memory 208940 kb
Host smart-ae51b5de-750d-499a-8511-0db2c013547f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988208572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3988208572
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.322718415
Short name T124
Test name
Test status
Simulation time 417998636 ps
CPU time 1.83 seconds
Started Jun 21 05:11:56 PM PDT 24
Finished Jun 21 05:12:00 PM PDT 24
Peak memory 200748 kb
Host smart-db50806e-4183-4d94-af26-eaf2ac14b6b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322718415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.322718415
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3768051020
Short name T64
Test name
Test status
Simulation time 128288878 ps
CPU time 1 seconds
Started Jun 21 05:12:06 PM PDT 24
Finished Jun 21 05:12:09 PM PDT 24
Peak memory 208844 kb
Host smart-0ed2b752-17f9-4902-a112-87281511fda3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768051020 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3768051020
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3273898941
Short name T107
Test name
Test status
Simulation time 72284439 ps
CPU time 0.77 seconds
Started Jun 21 05:12:05 PM PDT 24
Finished Jun 21 05:12:07 PM PDT 24
Peak memory 200636 kb
Host smart-d42a218d-18f5-4d87-bd7e-051601c3d1f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273898941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3273898941
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.759131797
Short name T575
Test name
Test status
Simulation time 119038595 ps
CPU time 1.11 seconds
Started Jun 21 05:12:05 PM PDT 24
Finished Jun 21 05:12:08 PM PDT 24
Peak memory 200608 kb
Host smart-50c84bbe-1156-4852-bbd5-4c120925a376
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759131797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.759131797
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3419163783
Short name T587
Test name
Test status
Simulation time 877493326 ps
CPU time 3.04 seconds
Started Jun 21 05:12:07 PM PDT 24
Finished Jun 21 05:12:12 PM PDT 24
Peak memory 200944 kb
Host smart-6f87696a-0d03-408f-85ad-66e802e598ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419163783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3419163783
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3104656973
Short name T571
Test name
Test status
Simulation time 176371432 ps
CPU time 1.64 seconds
Started Jun 21 05:12:05 PM PDT 24
Finished Jun 21 05:12:07 PM PDT 24
Peak memory 213716 kb
Host smart-4c48907f-3a07-4a3e-a0cb-523b1df09068
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104656973 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3104656973
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.618173500
Short name T96
Test name
Test status
Simulation time 64281053 ps
CPU time 0.74 seconds
Started Jun 21 05:12:04 PM PDT 24
Finished Jun 21 05:12:06 PM PDT 24
Peak memory 200624 kb
Host smart-b44481dc-6370-4558-9709-62d907c6973f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618173500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.618173500
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3327159963
Short name T108
Test name
Test status
Simulation time 133831626 ps
CPU time 1.41 seconds
Started Jun 21 05:12:08 PM PDT 24
Finished Jun 21 05:12:11 PM PDT 24
Peak memory 200756 kb
Host smart-8961d7ab-cfef-4b2b-ab5f-6d358ef2bde6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327159963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3327159963
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2488226786
Short name T608
Test name
Test status
Simulation time 548818456 ps
CPU time 3.44 seconds
Started Jun 21 05:12:04 PM PDT 24
Finished Jun 21 05:12:09 PM PDT 24
Peak memory 212712 kb
Host smart-f9b232d1-7704-437a-abbe-9d26071f6d0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488226786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2488226786
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1155842499
Short name T561
Test name
Test status
Simulation time 236411343 ps
CPU time 1.54 seconds
Started Jun 21 05:11:20 PM PDT 24
Finished Jun 21 05:11:22 PM PDT 24
Peak memory 200976 kb
Host smart-34c9bf3c-d096-4377-b27d-b6a0256c3396
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155842499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1
155842499
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2269886526
Short name T116
Test name
Test status
Simulation time 485199876 ps
CPU time 5.68 seconds
Started Jun 21 05:11:22 PM PDT 24
Finished Jun 21 05:11:29 PM PDT 24
Peak memory 200944 kb
Host smart-87dfab93-3211-49c6-bb86-ae3bbbbbcc7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269886526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
269886526
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2042762283
Short name T583
Test name
Test status
Simulation time 103862637 ps
CPU time 0.84 seconds
Started Jun 21 05:11:18 PM PDT 24
Finished Jun 21 05:11:20 PM PDT 24
Peak memory 200704 kb
Host smart-1fe42704-2289-46b6-bf9c-b17f9c963983
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042762283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
042762283
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1677380381
Short name T600
Test name
Test status
Simulation time 168072757 ps
CPU time 1.17 seconds
Started Jun 21 05:11:17 PM PDT 24
Finished Jun 21 05:11:19 PM PDT 24
Peak memory 208852 kb
Host smart-fcf45b05-eca7-4ab9-8c5b-b8ca7ab1e5ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677380381 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1677380381
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3041804125
Short name T564
Test name
Test status
Simulation time 73906143 ps
CPU time 0.81 seconds
Started Jun 21 05:11:21 PM PDT 24
Finished Jun 21 05:11:23 PM PDT 24
Peak memory 200588 kb
Host smart-04830c1c-e193-4fda-8009-4f111e5fa3dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041804125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3041804125
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3735562463
Short name T595
Test name
Test status
Simulation time 158332493 ps
CPU time 1.11 seconds
Started Jun 21 05:11:19 PM PDT 24
Finished Jun 21 05:11:21 PM PDT 24
Peak memory 200636 kb
Host smart-f4d80a56-9988-48f9-b0e7-bb1ce01cca5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735562463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3735562463
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1297487954
Short name T128
Test name
Test status
Simulation time 179236536 ps
CPU time 2.44 seconds
Started Jun 21 05:11:20 PM PDT 24
Finished Jun 21 05:11:23 PM PDT 24
Peak memory 217052 kb
Host smart-3df2142a-b61a-44a6-ba4b-26c35fde0f61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297487954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1297487954
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.821130222
Short name T586
Test name
Test status
Simulation time 436743109 ps
CPU time 1.76 seconds
Started Jun 21 05:11:21 PM PDT 24
Finished Jun 21 05:11:23 PM PDT 24
Peak memory 200820 kb
Host smart-36fc2e29-9404-4f57-8b51-7565d7ebdb35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821130222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.
821130222
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1370399289
Short name T546
Test name
Test status
Simulation time 353989571 ps
CPU time 2.53 seconds
Started Jun 21 05:11:30 PM PDT 24
Finished Jun 21 05:11:33 PM PDT 24
Peak memory 200868 kb
Host smart-294808ae-eb30-4b94-a146-e10d25db4ec7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370399289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
370399289
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2407698694
Short name T609
Test name
Test status
Simulation time 478956259 ps
CPU time 5.68 seconds
Started Jun 21 05:11:28 PM PDT 24
Finished Jun 21 05:11:34 PM PDT 24
Peak memory 200976 kb
Host smart-13fcf8cd-a3e1-40f5-ae32-e4bc0a954485
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407698694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
407698694
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.424692904
Short name T618
Test name
Test status
Simulation time 93747288 ps
CPU time 0.8 seconds
Started Jun 21 05:11:29 PM PDT 24
Finished Jun 21 05:11:31 PM PDT 24
Peak memory 200500 kb
Host smart-dce2f28d-32c0-452a-962e-907d19b9927d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424692904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.424692904
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2165613291
Short name T578
Test name
Test status
Simulation time 126163558 ps
CPU time 0.98 seconds
Started Jun 21 05:11:32 PM PDT 24
Finished Jun 21 05:11:33 PM PDT 24
Peak memory 200624 kb
Host smart-a6304c44-931c-4e39-908b-808ff1c583b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165613291 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2165613291
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.4002009615
Short name T585
Test name
Test status
Simulation time 78410641 ps
CPU time 0.83 seconds
Started Jun 21 05:11:27 PM PDT 24
Finished Jun 21 05:11:28 PM PDT 24
Peak memory 200636 kb
Host smart-fd6a60d5-42cb-42d0-bd89-92ee61eb174c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002009615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.4002009615
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1477933040
Short name T566
Test name
Test status
Simulation time 126200409 ps
CPU time 1.05 seconds
Started Jun 21 05:11:29 PM PDT 24
Finished Jun 21 05:11:31 PM PDT 24
Peak memory 200600 kb
Host smart-4f6f8461-b7f0-4a2f-959d-a7e05153d6c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477933040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1477933040
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3863788503
Short name T590
Test name
Test status
Simulation time 510989424 ps
CPU time 3.36 seconds
Started Jun 21 05:11:19 PM PDT 24
Finished Jun 21 05:11:23 PM PDT 24
Peak memory 209088 kb
Host smart-634c1aa5-5178-4771-999a-7e8d584a9cd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863788503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3863788503
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1709607819
Short name T120
Test name
Test status
Simulation time 795583192 ps
CPU time 2.85 seconds
Started Jun 21 05:11:26 PM PDT 24
Finished Jun 21 05:11:30 PM PDT 24
Peak memory 200840 kb
Host smart-ff3a72b9-f54c-4f7b-9a9c-ca366bdfba5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709607819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1709607819
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2891687797
Short name T567
Test name
Test status
Simulation time 418534407 ps
CPU time 2.51 seconds
Started Jun 21 05:11:30 PM PDT 24
Finished Jun 21 05:11:33 PM PDT 24
Peak memory 208964 kb
Host smart-4ba7f73a-d61e-4d61-9d8d-d80abff13b83
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891687797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
891687797
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4131703874
Short name T617
Test name
Test status
Simulation time 489903778 ps
CPU time 6.03 seconds
Started Jun 21 05:11:30 PM PDT 24
Finished Jun 21 05:11:37 PM PDT 24
Peak memory 200880 kb
Host smart-bb958505-9acc-4b53-9d6c-f12e4249b4eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131703874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.4
131703874
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.171441555
Short name T612
Test name
Test status
Simulation time 103614931 ps
CPU time 0.84 seconds
Started Jun 21 05:11:28 PM PDT 24
Finished Jun 21 05:11:30 PM PDT 24
Peak memory 200624 kb
Host smart-f4d5b726-2d34-47ee-9e4c-b8a2dca94bbc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171441555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.171441555
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1491011617
Short name T572
Test name
Test status
Simulation time 116155127 ps
CPU time 0.95 seconds
Started Jun 21 05:11:26 PM PDT 24
Finished Jun 21 05:11:28 PM PDT 24
Peak memory 200684 kb
Host smart-4be6fdc0-5769-4ec7-95b8-c223632e2483
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491011617 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1491011617
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.229261936
Short name T109
Test name
Test status
Simulation time 71857422 ps
CPU time 0.85 seconds
Started Jun 21 05:11:29 PM PDT 24
Finished Jun 21 05:11:31 PM PDT 24
Peak memory 200620 kb
Host smart-c0b7fac7-7c0a-41a5-a33d-1082788dc4ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229261936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.229261936
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1613790341
Short name T563
Test name
Test status
Simulation time 120022696 ps
CPU time 1.05 seconds
Started Jun 21 05:11:28 PM PDT 24
Finished Jun 21 05:11:30 PM PDT 24
Peak memory 200628 kb
Host smart-c791c490-f84b-415b-acd4-6a021215244b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613790341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1613790341
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1038490979
Short name T596
Test name
Test status
Simulation time 456863838 ps
CPU time 3.16 seconds
Started Jun 21 05:11:27 PM PDT 24
Finished Jun 21 05:11:31 PM PDT 24
Peak memory 208880 kb
Host smart-f8226fec-a762-4077-ba01-731de0c8ec09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038490979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.1038490979
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3194372227
Short name T122
Test name
Test status
Simulation time 465030124 ps
CPU time 1.83 seconds
Started Jun 21 05:11:27 PM PDT 24
Finished Jun 21 05:11:30 PM PDT 24
Peak memory 200816 kb
Host smart-7c730a00-a0e7-4e64-bda2-eeff0094f024
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194372227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3194372227
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2335117618
Short name T84
Test name
Test status
Simulation time 195698925 ps
CPU time 1.3 seconds
Started Jun 21 05:11:38 PM PDT 24
Finished Jun 21 05:11:41 PM PDT 24
Peak memory 200692 kb
Host smart-f3e3a981-2ae8-4394-ac52-f350e8f1e25b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335117618 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2335117618
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.488874672
Short name T597
Test name
Test status
Simulation time 88205066 ps
CPU time 0.89 seconds
Started Jun 21 05:11:37 PM PDT 24
Finished Jun 21 05:11:38 PM PDT 24
Peak memory 200612 kb
Host smart-f4021e70-5e2c-43de-b141-6a5798264f69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488874672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.488874672
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.428353334
Short name T604
Test name
Test status
Simulation time 79065197 ps
CPU time 1.02 seconds
Started Jun 21 05:11:39 PM PDT 24
Finished Jun 21 05:11:42 PM PDT 24
Peak memory 200548 kb
Host smart-e45bb16c-9c4e-447b-9880-907de570edef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428353334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sam
e_csr_outstanding.428353334
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.608434275
Short name T614
Test name
Test status
Simulation time 358957394 ps
CPU time 2.35 seconds
Started Jun 21 05:11:30 PM PDT 24
Finished Jun 21 05:11:33 PM PDT 24
Peak memory 208992 kb
Host smart-af92019e-7c26-4bc8-aee2-bb6f58149d81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608434275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.608434275
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.4017033294
Short name T599
Test name
Test status
Simulation time 952374138 ps
CPU time 3.02 seconds
Started Jun 21 05:11:36 PM PDT 24
Finished Jun 21 05:11:40 PM PDT 24
Peak memory 200820 kb
Host smart-a4dbe4f8-84e7-472d-9a10-f6b7d8d43750
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017033294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.4017033294
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1728399286
Short name T65
Test name
Test status
Simulation time 109524761 ps
CPU time 1.11 seconds
Started Jun 21 05:11:38 PM PDT 24
Finished Jun 21 05:11:40 PM PDT 24
Peak memory 208844 kb
Host smart-7d849849-2205-4d7f-b0f6-2f93eca8475d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728399286 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1728399286
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1674116606
Short name T603
Test name
Test status
Simulation time 76580643 ps
CPU time 0.75 seconds
Started Jun 21 05:11:36 PM PDT 24
Finished Jun 21 05:11:37 PM PDT 24
Peak memory 200556 kb
Host smart-e246bf80-f268-43a5-af3e-87738239dc9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674116606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1674116606
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3465646200
Short name T620
Test name
Test status
Simulation time 73693640 ps
CPU time 0.94 seconds
Started Jun 21 05:11:38 PM PDT 24
Finished Jun 21 05:11:40 PM PDT 24
Peak memory 200512 kb
Host smart-95ca5872-2f44-4a87-be7a-640863487ba7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465646200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3465646200
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3175880787
Short name T576
Test name
Test status
Simulation time 456901608 ps
CPU time 1.76 seconds
Started Jun 21 05:11:38 PM PDT 24
Finished Jun 21 05:11:40 PM PDT 24
Peak memory 200840 kb
Host smart-41f45cba-ba19-427e-8a15-eb6269ba32ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175880787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3175880787
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2643546289
Short name T86
Test name
Test status
Simulation time 159029490 ps
CPU time 1.41 seconds
Started Jun 21 05:11:40 PM PDT 24
Finished Jun 21 05:11:43 PM PDT 24
Peak memory 209088 kb
Host smart-eaa5d7a3-1d8e-4e43-b503-63096f237584
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643546289 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2643546289
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1954827711
Short name T591
Test name
Test status
Simulation time 57615458 ps
CPU time 0.77 seconds
Started Jun 21 05:11:38 PM PDT 24
Finished Jun 21 05:11:40 PM PDT 24
Peak memory 200580 kb
Host smart-ab864e61-9922-4153-9e44-61ebca46d0c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954827711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1954827711
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3917012031
Short name T60
Test name
Test status
Simulation time 220200271 ps
CPU time 1.49 seconds
Started Jun 21 05:11:38 PM PDT 24
Finished Jun 21 05:11:41 PM PDT 24
Peak memory 200768 kb
Host smart-ceb46a9c-1fde-429c-8a7b-c29c908d6eb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917012031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3917012031
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1394789324
Short name T118
Test name
Test status
Simulation time 497319714 ps
CPU time 3.3 seconds
Started Jun 21 05:11:38 PM PDT 24
Finished Jun 21 05:11:42 PM PDT 24
Peak memory 209044 kb
Host smart-843581e0-b422-453c-8e36-9aaf0db345e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394789324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1394789324
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1010127756
Short name T605
Test name
Test status
Simulation time 936579359 ps
CPU time 2.95 seconds
Started Jun 21 05:11:39 PM PDT 24
Finished Jun 21 05:11:43 PM PDT 24
Peak memory 200840 kb
Host smart-7b60856c-8f44-4d04-a48b-981643677c28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010127756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.1010127756
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3563654453
Short name T565
Test name
Test status
Simulation time 122075961 ps
CPU time 1.23 seconds
Started Jun 21 05:11:37 PM PDT 24
Finished Jun 21 05:11:39 PM PDT 24
Peak memory 208888 kb
Host smart-87624837-7f65-43b9-b309-4006649047d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563654453 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3563654453
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3389590399
Short name T111
Test name
Test status
Simulation time 73819793 ps
CPU time 0.82 seconds
Started Jun 21 05:11:36 PM PDT 24
Finished Jun 21 05:11:38 PM PDT 24
Peak memory 200564 kb
Host smart-64213c34-1fa0-4baa-b755-06e6d2208298
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389590399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3389590399
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3144472471
Short name T616
Test name
Test status
Simulation time 257733821 ps
CPU time 1.55 seconds
Started Jun 21 05:11:38 PM PDT 24
Finished Jun 21 05:11:41 PM PDT 24
Peak memory 200780 kb
Host smart-38bbd5fd-edde-4268-adb5-adf6dd8d5712
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144472471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3144472471
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2009837464
Short name T598
Test name
Test status
Simulation time 339205028 ps
CPU time 2.43 seconds
Started Jun 21 05:11:39 PM PDT 24
Finished Jun 21 05:11:43 PM PDT 24
Peak memory 209020 kb
Host smart-73306e93-8961-4dd6-b005-3f5b5fc40876
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009837464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2009837464
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3450121381
Short name T125
Test name
Test status
Simulation time 939408087 ps
CPU time 3.41 seconds
Started Jun 21 05:11:38 PM PDT 24
Finished Jun 21 05:11:42 PM PDT 24
Peak memory 200788 kb
Host smart-d68dd407-c848-4f61-afb0-0f6be74de1b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450121381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3450121381
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2327107951
Short name T602
Test name
Test status
Simulation time 149238848 ps
CPU time 1.11 seconds
Started Jun 21 05:11:46 PM PDT 24
Finished Jun 21 05:11:49 PM PDT 24
Peak memory 208812 kb
Host smart-79a311ee-b303-4829-9421-20db2eab1a22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327107951 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2327107951
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2742219984
Short name T557
Test name
Test status
Simulation time 63913131 ps
CPU time 0.84 seconds
Started Jun 21 05:11:39 PM PDT 24
Finished Jun 21 05:11:42 PM PDT 24
Peak memory 200652 kb
Host smart-21d873d0-2a8d-46ea-aea2-e944ffdc7dd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742219984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2742219984
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3005641216
Short name T601
Test name
Test status
Simulation time 196742073 ps
CPU time 1.38 seconds
Started Jun 21 05:11:48 PM PDT 24
Finished Jun 21 05:11:51 PM PDT 24
Peak memory 200876 kb
Host smart-6a874ca0-4d66-4fef-ad18-d6a16e117a35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005641216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3005641216
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1345443196
Short name T83
Test name
Test status
Simulation time 152705029 ps
CPU time 2.38 seconds
Started Jun 21 05:11:39 PM PDT 24
Finished Jun 21 05:11:43 PM PDT 24
Peak memory 209000 kb
Host smart-47120c96-fe81-463b-b1a8-485bdf8e7247
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345443196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1345443196
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.588309376
Short name T123
Test name
Test status
Simulation time 921910705 ps
CPU time 3.1 seconds
Started Jun 21 05:11:37 PM PDT 24
Finished Jun 21 05:11:41 PM PDT 24
Peak memory 200780 kb
Host smart-e231d4d6-e055-4d75-b827-49107bab1a66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588309376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
588309376
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.146153923
Short name T287
Test name
Test status
Simulation time 2176547350 ps
CPU time 8.01 seconds
Started Jun 21 05:12:06 PM PDT 24
Finished Jun 21 05:12:16 PM PDT 24
Peak memory 218472 kb
Host smart-d25d3160-48d1-43a7-b4a3-d90f6414a66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146153923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.146153923
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1661571493
Short name T342
Test name
Test status
Simulation time 244790541 ps
CPU time 1.02 seconds
Started Jun 21 05:12:06 PM PDT 24
Finished Jun 21 05:12:09 PM PDT 24
Peak memory 218052 kb
Host smart-8023c35b-1bef-472b-b98e-c2c44627c752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661571493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1661571493
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.2415009416
Short name T439
Test name
Test status
Simulation time 155415725 ps
CPU time 0.81 seconds
Started Jun 21 05:12:06 PM PDT 24
Finished Jun 21 05:12:09 PM PDT 24
Peak memory 200488 kb
Host smart-58c5f0a8-8382-41c2-98ef-e3d58c20747e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415009416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2415009416
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1581782667
Short name T530
Test name
Test status
Simulation time 1899585869 ps
CPU time 7.15 seconds
Started Jun 21 05:12:04 PM PDT 24
Finished Jun 21 05:12:12 PM PDT 24
Peak memory 200876 kb
Host smart-6c36162f-b495-4bee-8635-0c8c11c6d2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581782667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1581782667
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2220578623
Short name T69
Test name
Test status
Simulation time 8292967096 ps
CPU time 13.27 seconds
Started Jun 21 05:12:07 PM PDT 24
Finished Jun 21 05:12:22 PM PDT 24
Peak memory 217648 kb
Host smart-85dc0e91-86c4-4c3d-92ec-f4cc98c4d32e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220578623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2220578623
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.646374657
Short name T188
Test name
Test status
Simulation time 113703862 ps
CPU time 1.29 seconds
Started Jun 21 05:12:06 PM PDT 24
Finished Jun 21 05:12:09 PM PDT 24
Peak memory 200880 kb
Host smart-075fc1dc-4a72-4d65-8c78-7e1360d5e8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646374657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.646374657
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1880603551
Short name T296
Test name
Test status
Simulation time 1727702320 ps
CPU time 6.16 seconds
Started Jun 21 05:12:06 PM PDT 24
Finished Jun 21 05:12:14 PM PDT 24
Peak memory 200864 kb
Host smart-69e19eb6-272a-4e6b-9ad5-e069477d490f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880603551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1880603551
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1903304347
Short name T401
Test name
Test status
Simulation time 136241967 ps
CPU time 1.68 seconds
Started Jun 21 05:12:07 PM PDT 24
Finished Jun 21 05:12:10 PM PDT 24
Peak memory 200420 kb
Host smart-8cc96e22-9667-4b43-8945-ac91336ae842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903304347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1903304347
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.848157803
Short name T412
Test name
Test status
Simulation time 136194484 ps
CPU time 1.06 seconds
Started Jun 21 05:12:05 PM PDT 24
Finished Jun 21 05:12:07 PM PDT 24
Peak memory 200688 kb
Host smart-288b0458-abf8-4ba9-94c6-09fd333a5ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848157803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.848157803
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1921431682
Short name T276
Test name
Test status
Simulation time 67028304 ps
CPU time 0.78 seconds
Started Jun 21 05:12:06 PM PDT 24
Finished Jun 21 05:12:09 PM PDT 24
Peak memory 200472 kb
Host smart-bb5ab97e-1e08-427c-9812-d642dfd80318
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921431682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1921431682
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.824674228
Short name T299
Test name
Test status
Simulation time 1223077434 ps
CPU time 5.55 seconds
Started Jun 21 05:12:07 PM PDT 24
Finished Jun 21 05:12:14 PM PDT 24
Peak memory 221888 kb
Host smart-4fa671d2-aac6-4539-995e-1d660affddb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824674228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.824674228
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1760562999
Short name T201
Test name
Test status
Simulation time 244777178 ps
CPU time 1.01 seconds
Started Jun 21 05:12:05 PM PDT 24
Finished Jun 21 05:12:07 PM PDT 24
Peak memory 218060 kb
Host smart-8338f05f-3767-484f-8eea-99661ed30a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760562999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1760562999
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.4130213104
Short name T406
Test name
Test status
Simulation time 174370311 ps
CPU time 0.87 seconds
Started Jun 21 05:12:07 PM PDT 24
Finished Jun 21 05:12:10 PM PDT 24
Peak memory 200444 kb
Host smart-10cf2d58-36d3-4ae4-8572-00ec043b97d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130213104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.4130213104
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.4286774174
Short name T252
Test name
Test status
Simulation time 1190911666 ps
CPU time 5.47 seconds
Started Jun 21 05:12:05 PM PDT 24
Finished Jun 21 05:12:11 PM PDT 24
Peak memory 200824 kb
Host smart-42f59e81-556e-49ab-8f60-72d3c39a6176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286774174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.4286774174
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.4005481813
Short name T70
Test name
Test status
Simulation time 16532835886 ps
CPU time 28.82 seconds
Started Jun 21 05:12:08 PM PDT 24
Finished Jun 21 05:12:38 PM PDT 24
Peak memory 218568 kb
Host smart-868310a8-df07-4fa0-ae33-3c52cb2f7b86
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005481813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.4005481813
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3756045243
Short name T314
Test name
Test status
Simulation time 109905015 ps
CPU time 1.05 seconds
Started Jun 21 05:12:07 PM PDT 24
Finished Jun 21 05:12:10 PM PDT 24
Peak memory 200672 kb
Host smart-fd0e07ea-1293-456a-a932-c5a2ec65b622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756045243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3756045243
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.3804308588
Short name T272
Test name
Test status
Simulation time 256248885 ps
CPU time 1.46 seconds
Started Jun 21 05:12:05 PM PDT 24
Finished Jun 21 05:12:08 PM PDT 24
Peak memory 200792 kb
Host smart-e6ae0c46-865d-4afc-b475-7e5f715bf35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804308588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3804308588
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.4166539443
Short name T115
Test name
Test status
Simulation time 1834660625 ps
CPU time 7.67 seconds
Started Jun 21 05:12:05 PM PDT 24
Finished Jun 21 05:12:15 PM PDT 24
Peak memory 217180 kb
Host smart-e3d8865c-23bd-4c78-ba0b-871faaacc29b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166539443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.4166539443
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3692521693
Short name T256
Test name
Test status
Simulation time 70455095 ps
CPU time 0.85 seconds
Started Jun 21 05:12:06 PM PDT 24
Finished Jun 21 05:12:09 PM PDT 24
Peak memory 200676 kb
Host smart-4d5baa4c-880c-4521-91ee-6f1f6bc49357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692521693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3692521693
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.257500244
Short name T403
Test name
Test status
Simulation time 65735309 ps
CPU time 0.82 seconds
Started Jun 21 05:12:31 PM PDT 24
Finished Jun 21 05:12:33 PM PDT 24
Peak memory 200460 kb
Host smart-a3cf3799-b02d-4cb3-996a-6afa95187964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257500244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.257500244
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.557172216
Short name T35
Test name
Test status
Simulation time 2378594116 ps
CPU time 8.58 seconds
Started Jun 21 05:12:32 PM PDT 24
Finished Jun 21 05:12:42 PM PDT 24
Peak memory 218616 kb
Host smart-03f55d8a-0e90-4555-b459-b404f6ea03ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557172216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.557172216
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2903720693
Short name T508
Test name
Test status
Simulation time 246745098 ps
CPU time 1.02 seconds
Started Jun 21 05:12:35 PM PDT 24
Finished Jun 21 05:12:38 PM PDT 24
Peak memory 218064 kb
Host smart-f012ab4e-41d7-401d-8dae-6d1b005347f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903720693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2903720693
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.4288690947
Short name T211
Test name
Test status
Simulation time 130617871 ps
CPU time 0.8 seconds
Started Jun 21 05:12:33 PM PDT 24
Finished Jun 21 05:12:36 PM PDT 24
Peak memory 200496 kb
Host smart-1bacd348-1357-483e-ad94-e4d0ef3f9053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288690947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.4288690947
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.381001379
Short name T186
Test name
Test status
Simulation time 1265532285 ps
CPU time 5.19 seconds
Started Jun 21 05:12:33 PM PDT 24
Finished Jun 21 05:12:40 PM PDT 24
Peak memory 200856 kb
Host smart-1e9bc8f3-877b-4d9c-a8a8-21eb98432e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381001379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.381001379
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.4117226342
Short name T157
Test name
Test status
Simulation time 109029284 ps
CPU time 0.97 seconds
Started Jun 21 05:12:31 PM PDT 24
Finished Jun 21 05:12:33 PM PDT 24
Peak memory 200676 kb
Host smart-9442edc8-7da7-475c-9475-4dfbc0c0b5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117226342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.4117226342
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.78026346
Short name T8
Test name
Test status
Simulation time 125938703 ps
CPU time 1.56 seconds
Started Jun 21 05:12:33 PM PDT 24
Finished Jun 21 05:12:37 PM PDT 24
Peak memory 208952 kb
Host smart-c1e3cde9-c0b4-43f0-8c37-15e79c4da60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78026346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.78026346
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2313982660
Short name T300
Test name
Test status
Simulation time 82247200 ps
CPU time 0.78 seconds
Started Jun 21 05:12:33 PM PDT 24
Finished Jun 21 05:12:35 PM PDT 24
Peak memory 200416 kb
Host smart-9088beda-dad1-4d0c-adf1-c93eedc100b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313982660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2313982660
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2227378268
Short name T440
Test name
Test status
Simulation time 1232333153 ps
CPU time 5.64 seconds
Started Jun 21 05:12:35 PM PDT 24
Finished Jun 21 05:12:43 PM PDT 24
Peak memory 218472 kb
Host smart-b58e162e-e876-4ba3-a794-6e4fa3a0b38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227378268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2227378268
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.4059097327
Short name T543
Test name
Test status
Simulation time 244322242 ps
CPU time 1.09 seconds
Started Jun 21 05:12:35 PM PDT 24
Finished Jun 21 05:12:38 PM PDT 24
Peak memory 218076 kb
Host smart-b4a42382-fed5-437f-a97d-86d7aa36517b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059097327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.4059097327
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.4110241804
Short name T527
Test name
Test status
Simulation time 121704465 ps
CPU time 0.82 seconds
Started Jun 21 05:12:32 PM PDT 24
Finished Jun 21 05:12:35 PM PDT 24
Peak memory 200500 kb
Host smart-f83b967c-28bb-4c9c-ac19-45c675860baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110241804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.4110241804
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.104712901
Short name T94
Test name
Test status
Simulation time 1396373410 ps
CPU time 5.27 seconds
Started Jun 21 05:12:34 PM PDT 24
Finished Jun 21 05:12:41 PM PDT 24
Peak memory 200828 kb
Host smart-15d0f163-8dcb-4324-b2d2-936250071b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104712901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.104712901
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2100584600
Short name T156
Test name
Test status
Simulation time 114450226 ps
CPU time 1.02 seconds
Started Jun 21 05:12:32 PM PDT 24
Finished Jun 21 05:12:34 PM PDT 24
Peak memory 200616 kb
Host smart-74326320-a1c2-4bec-8e96-53904a075aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100584600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2100584600
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1062643410
Short name T265
Test name
Test status
Simulation time 248197357 ps
CPU time 1.48 seconds
Started Jun 21 05:12:33 PM PDT 24
Finished Jun 21 05:12:37 PM PDT 24
Peak memory 200892 kb
Host smart-2b401438-2f9f-42da-a818-f30bcc6224bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062643410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1062643410
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3601798711
Short name T422
Test name
Test status
Simulation time 2843631786 ps
CPU time 13.85 seconds
Started Jun 21 05:12:32 PM PDT 24
Finished Jun 21 05:12:48 PM PDT 24
Peak memory 209056 kb
Host smart-6cdcfe7c-01f9-4ccd-854c-c0e44a03ddeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601798711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3601798711
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2091077676
Short name T271
Test name
Test status
Simulation time 367331208 ps
CPU time 2.14 seconds
Started Jun 21 05:12:34 PM PDT 24
Finished Jun 21 05:12:38 PM PDT 24
Peak memory 200652 kb
Host smart-393c357f-9e2b-4204-a64f-6eb50a039086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091077676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2091077676
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2053325849
Short name T516
Test name
Test status
Simulation time 122989485 ps
CPU time 1.05 seconds
Started Jun 21 05:12:31 PM PDT 24
Finished Jun 21 05:12:33 PM PDT 24
Peak memory 200688 kb
Host smart-6cad9431-e195-40b8-8014-15dd8f1d0c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053325849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2053325849
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.684963367
Short name T446
Test name
Test status
Simulation time 69283499 ps
CPU time 0.82 seconds
Started Jun 21 05:12:42 PM PDT 24
Finished Jun 21 05:12:45 PM PDT 24
Peak memory 200468 kb
Host smart-d948e985-892f-41f3-8602-c71af835d6ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684963367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.684963367
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3483338729
Short name T417
Test name
Test status
Simulation time 2370097475 ps
CPU time 8.35 seconds
Started Jun 21 05:12:42 PM PDT 24
Finished Jun 21 05:12:52 PM PDT 24
Peak memory 218304 kb
Host smart-05622abc-74f3-4b54-82f0-a1bdeee958c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483338729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3483338729
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2407224583
Short name T377
Test name
Test status
Simulation time 244495251 ps
CPU time 1.07 seconds
Started Jun 21 05:12:41 PM PDT 24
Finished Jun 21 05:12:45 PM PDT 24
Peak memory 218044 kb
Host smart-d12c9624-8945-4344-aacf-429c0b4c09d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407224583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2407224583
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.21597161
Short name T541
Test name
Test status
Simulation time 102688552 ps
CPU time 0.8 seconds
Started Jun 21 05:12:39 PM PDT 24
Finished Jun 21 05:12:41 PM PDT 24
Peak memory 200432 kb
Host smart-eefbae1f-5904-496d-97c1-655530becfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21597161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.21597161
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2258147620
Short name T92
Test name
Test status
Simulation time 1220368784 ps
CPU time 4.74 seconds
Started Jun 21 05:12:37 PM PDT 24
Finished Jun 21 05:12:43 PM PDT 24
Peak memory 200876 kb
Host smart-7a20b6df-f13d-4e7b-8584-46fde8253b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258147620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2258147620
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.768538529
Short name T258
Test name
Test status
Simulation time 152866424 ps
CPU time 1.14 seconds
Started Jun 21 05:12:40 PM PDT 24
Finished Jun 21 05:12:43 PM PDT 24
Peak memory 200620 kb
Host smart-9403bf6d-ef57-4b79-bf48-455fadc5c37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768538529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.768538529
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.951247632
Short name T488
Test name
Test status
Simulation time 220153381 ps
CPU time 1.42 seconds
Started Jun 21 05:12:32 PM PDT 24
Finished Jun 21 05:12:35 PM PDT 24
Peak memory 200876 kb
Host smart-e01529f2-8993-4e83-8b60-a75aaeb62e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951247632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.951247632
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3542979234
Short name T193
Test name
Test status
Simulation time 6935159642 ps
CPU time 24.85 seconds
Started Jun 21 05:12:40 PM PDT 24
Finished Jun 21 05:13:06 PM PDT 24
Peak memory 200920 kb
Host smart-66b64b76-8359-4bd2-9f94-b706e8b89194
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542979234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3542979234
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.3945436744
Short name T227
Test name
Test status
Simulation time 121245121 ps
CPU time 1.46 seconds
Started Jun 21 05:12:42 PM PDT 24
Finished Jun 21 05:12:45 PM PDT 24
Peak memory 200652 kb
Host smart-2e9361b4-691f-4a6b-ad34-ec151ea1e94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945436744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3945436744
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2338555406
Short name T79
Test name
Test status
Simulation time 132246787 ps
CPU time 1.06 seconds
Started Jun 21 05:12:39 PM PDT 24
Finished Jun 21 05:12:41 PM PDT 24
Peak memory 200676 kb
Host smart-72ef45ec-0f8a-45d4-ad1d-2c3c882da3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338555406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2338555406
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2177654272
Short name T343
Test name
Test status
Simulation time 72234137 ps
CPU time 0.79 seconds
Started Jun 21 05:12:39 PM PDT 24
Finished Jun 21 05:12:41 PM PDT 24
Peak memory 200540 kb
Host smart-5fb20e51-cc1a-4075-b1f1-b2c13cb0f896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177654272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2177654272
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.108326885
Short name T499
Test name
Test status
Simulation time 1902705227 ps
CPU time 7.62 seconds
Started Jun 21 05:12:40 PM PDT 24
Finished Jun 21 05:12:49 PM PDT 24
Peak memory 217424 kb
Host smart-fd38afde-4b75-4b67-8964-068db1f68cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108326885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.108326885
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1699766267
Short name T187
Test name
Test status
Simulation time 245070099 ps
CPU time 1.05 seconds
Started Jun 21 05:12:41 PM PDT 24
Finished Jun 21 05:12:45 PM PDT 24
Peak memory 218160 kb
Host smart-db6ca245-9b2b-47fc-9ac6-8b990f90fae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699766267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1699766267
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1991990826
Short name T251
Test name
Test status
Simulation time 134859225 ps
CPU time 0.8 seconds
Started Jun 21 05:12:40 PM PDT 24
Finished Jun 21 05:12:43 PM PDT 24
Peak memory 200504 kb
Host smart-b772a257-7509-4bed-9b15-78958f56082e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991990826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1991990826
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2615611024
Short name T56
Test name
Test status
Simulation time 1332958308 ps
CPU time 5.33 seconds
Started Jun 21 05:12:44 PM PDT 24
Finished Jun 21 05:12:51 PM PDT 24
Peak memory 200872 kb
Host smart-4bb6871c-c553-4b8b-9c4c-f2d964cefdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615611024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2615611024
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.792999983
Short name T163
Test name
Test status
Simulation time 141665211 ps
CPU time 1.11 seconds
Started Jun 21 05:12:44 PM PDT 24
Finished Jun 21 05:12:46 PM PDT 24
Peak memory 200800 kb
Host smart-c5d37bf3-ed11-43e7-9676-23fa371de263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792999983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.792999983
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3116004711
Short name T375
Test name
Test status
Simulation time 245621355 ps
CPU time 1.44 seconds
Started Jun 21 05:12:45 PM PDT 24
Finished Jun 21 05:12:47 PM PDT 24
Peak memory 200876 kb
Host smart-8dcc84bf-a1ba-4882-a85f-e35d570c2421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116004711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3116004711
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3476177753
Short name T431
Test name
Test status
Simulation time 1839630161 ps
CPU time 8.65 seconds
Started Jun 21 05:12:41 PM PDT 24
Finished Jun 21 05:12:52 PM PDT 24
Peak memory 200864 kb
Host smart-19108971-aac3-43a7-9749-4e9ce4ad2843
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476177753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3476177753
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2424785181
Short name T459
Test name
Test status
Simulation time 143618739 ps
CPU time 1.84 seconds
Started Jun 21 05:12:44 PM PDT 24
Finished Jun 21 05:12:47 PM PDT 24
Peak memory 200680 kb
Host smart-fa30c13c-a9dc-43fe-8b6e-467ae16f2277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424785181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2424785181
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1645273972
Short name T133
Test name
Test status
Simulation time 101355650 ps
CPU time 0.84 seconds
Started Jun 21 05:12:39 PM PDT 24
Finished Jun 21 05:12:42 PM PDT 24
Peak memory 200688 kb
Host smart-cce382d1-be67-4734-944c-a392cfba4cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645273972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1645273972
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.594684559
Short name T410
Test name
Test status
Simulation time 73118718 ps
CPU time 0.77 seconds
Started Jun 21 05:12:39 PM PDT 24
Finished Jun 21 05:12:40 PM PDT 24
Peak memory 200484 kb
Host smart-d80bdbec-3870-470e-95f3-128a07bd6176
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594684559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.594684559
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2460859599
Short name T472
Test name
Test status
Simulation time 1896166317 ps
CPU time 7.5 seconds
Started Jun 21 05:12:41 PM PDT 24
Finished Jun 21 05:12:51 PM PDT 24
Peak memory 218452 kb
Host smart-eab50d42-a131-4974-926c-c700e6c2bb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460859599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2460859599
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1882613742
Short name T218
Test name
Test status
Simulation time 244606365 ps
CPU time 1.06 seconds
Started Jun 21 05:12:40 PM PDT 24
Finished Jun 21 05:12:43 PM PDT 24
Peak memory 218012 kb
Host smart-e2873201-ae35-471b-8864-1729e12068ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882613742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.1882613742
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2611270076
Short name T471
Test name
Test status
Simulation time 1874303910 ps
CPU time 7.07 seconds
Started Jun 21 05:12:40 PM PDT 24
Finished Jun 21 05:12:48 PM PDT 24
Peak memory 200904 kb
Host smart-9121c4c2-b06e-40a3-a00a-3acbbf1aa7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611270076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2611270076
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.4023109940
Short name T208
Test name
Test status
Simulation time 102194279 ps
CPU time 1.01 seconds
Started Jun 21 05:12:42 PM PDT 24
Finished Jun 21 05:12:45 PM PDT 24
Peak memory 200644 kb
Host smart-e58bf85a-b642-4d4f-8ef6-e0b2ddb54b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023109940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.4023109940
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3215673199
Short name T28
Test name
Test status
Simulation time 128950200 ps
CPU time 1.2 seconds
Started Jun 21 05:12:40 PM PDT 24
Finished Jun 21 05:12:43 PM PDT 24
Peak memory 200920 kb
Host smart-d39e4cf8-387e-4ceb-a12a-93eb931243b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215673199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3215673199
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1192895664
Short name T233
Test name
Test status
Simulation time 73979929 ps
CPU time 0.8 seconds
Started Jun 21 05:12:42 PM PDT 24
Finished Jun 21 05:12:45 PM PDT 24
Peak memory 200460 kb
Host smart-63355fe0-4c84-43af-9847-d46f210c809a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192895664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1192895664
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3062047919
Short name T341
Test name
Test status
Simulation time 539112253 ps
CPU time 2.96 seconds
Started Jun 21 05:12:39 PM PDT 24
Finished Jun 21 05:12:44 PM PDT 24
Peak memory 200672 kb
Host smart-9077afc9-520e-4eee-ac4b-3a2450bb88ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062047919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3062047919
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3246730075
Short name T416
Test name
Test status
Simulation time 113650023 ps
CPU time 0.88 seconds
Started Jun 21 05:12:40 PM PDT 24
Finished Jun 21 05:12:43 PM PDT 24
Peak memory 200696 kb
Host smart-3c3b303f-d1b6-48b8-8179-7e5d8472766a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246730075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3246730075
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2899844658
Short name T191
Test name
Test status
Simulation time 74150328 ps
CPU time 0.8 seconds
Started Jun 21 05:12:40 PM PDT 24
Finished Jun 21 05:12:42 PM PDT 24
Peak memory 200428 kb
Host smart-e3a0b378-be0a-4f2a-8ee1-4f102e8d916a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899844658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2899844658
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1320485313
Short name T39
Test name
Test status
Simulation time 2382633668 ps
CPU time 8.25 seconds
Started Jun 21 05:12:41 PM PDT 24
Finished Jun 21 05:12:51 PM PDT 24
Peak memory 222492 kb
Host smart-96bc1cc0-9e5b-47b8-b3fe-f6274281d34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320485313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1320485313
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.831678977
Short name T175
Test name
Test status
Simulation time 244491783 ps
CPU time 1.04 seconds
Started Jun 21 05:12:40 PM PDT 24
Finished Jun 21 05:12:42 PM PDT 24
Peak memory 218076 kb
Host smart-bdd054d6-1204-4dba-86c1-88c292fa63bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831678977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.831678977
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2314930530
Short name T318
Test name
Test status
Simulation time 76748944 ps
CPU time 0.76 seconds
Started Jun 21 05:12:44 PM PDT 24
Finished Jun 21 05:12:46 PM PDT 24
Peak memory 200608 kb
Host smart-400b61ff-74db-4d4c-8a20-811e4e94d59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314930530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2314930530
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2283779387
Short name T95
Test name
Test status
Simulation time 1857626052 ps
CPU time 6.79 seconds
Started Jun 21 05:12:42 PM PDT 24
Finished Jun 21 05:12:51 PM PDT 24
Peak memory 200856 kb
Host smart-ccd5cb8c-8bd0-40d0-9e77-1bc0fbbebc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283779387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2283779387
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1020171185
Short name T242
Test name
Test status
Simulation time 102569691 ps
CPU time 1.01 seconds
Started Jun 21 05:12:43 PM PDT 24
Finished Jun 21 05:12:46 PM PDT 24
Peak memory 200664 kb
Host smart-a266a0a1-0d55-4beb-94a3-9e715328722c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020171185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1020171185
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.2694294354
Short name T139
Test name
Test status
Simulation time 249161811 ps
CPU time 1.61 seconds
Started Jun 21 05:12:41 PM PDT 24
Finished Jun 21 05:12:45 PM PDT 24
Peak memory 200868 kb
Host smart-86df8463-d92f-4ddb-872d-6a615024a9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694294354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.2694294354
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2693846301
Short name T176
Test name
Test status
Simulation time 4429565708 ps
CPU time 17.95 seconds
Started Jun 21 05:12:39 PM PDT 24
Finished Jun 21 05:12:59 PM PDT 24
Peak memory 200868 kb
Host smart-92d864ec-3117-4af5-84e1-e16a575ac081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693846301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2693846301
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.342958785
Short name T380
Test name
Test status
Simulation time 524750058 ps
CPU time 2.73 seconds
Started Jun 21 05:12:40 PM PDT 24
Finished Jun 21 05:12:45 PM PDT 24
Peak memory 200684 kb
Host smart-4e55c613-cbef-4649-a5cc-d4c15aa5d22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342958785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.342958785
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.206816222
Short name T14
Test name
Test status
Simulation time 76731473 ps
CPU time 0.82 seconds
Started Jun 21 05:12:42 PM PDT 24
Finished Jun 21 05:12:45 PM PDT 24
Peak memory 200676 kb
Host smart-c08e1f50-c2c3-4b07-80c7-aa4ddbee789b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206816222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.206816222
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1925166967
Short name T466
Test name
Test status
Simulation time 74566490 ps
CPU time 0.79 seconds
Started Jun 21 05:12:48 PM PDT 24
Finished Jun 21 05:12:51 PM PDT 24
Peak memory 200484 kb
Host smart-500bacf2-8e04-4bd4-b514-d14801c58965
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925166967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1925166967
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2745410747
Short name T36
Test name
Test status
Simulation time 2365303798 ps
CPU time 8.39 seconds
Started Jun 21 05:12:46 PM PDT 24
Finished Jun 21 05:12:56 PM PDT 24
Peak memory 222452 kb
Host smart-3d1609ad-4fc9-44db-bc57-8db44dfe36e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745410747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2745410747
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.470631856
Short name T372
Test name
Test status
Simulation time 244246108 ps
CPU time 1.11 seconds
Started Jun 21 05:12:50 PM PDT 24
Finished Jun 21 05:12:55 PM PDT 24
Peak memory 218036 kb
Host smart-b8cd416c-65e9-44fe-9f27-78fd8ab13438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470631856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.470631856
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2444066814
Short name T304
Test name
Test status
Simulation time 96819972 ps
CPU time 0.76 seconds
Started Jun 21 05:12:40 PM PDT 24
Finished Jun 21 05:12:43 PM PDT 24
Peak memory 200488 kb
Host smart-ca4a03c3-d565-4c8a-8b49-2dea4ff61ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444066814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2444066814
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.4014719014
Short name T436
Test name
Test status
Simulation time 1637253406 ps
CPU time 6.46 seconds
Started Jun 21 05:12:48 PM PDT 24
Finished Jun 21 05:12:56 PM PDT 24
Peak memory 200820 kb
Host smart-aa7ad3ea-c3e6-4728-beb6-58c15577bd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014719014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.4014719014
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3815491329
Short name T366
Test name
Test status
Simulation time 161694673 ps
CPU time 1.17 seconds
Started Jun 21 05:12:48 PM PDT 24
Finished Jun 21 05:12:51 PM PDT 24
Peak memory 200672 kb
Host smart-007ceedc-300f-417c-96f4-d5bd93c63c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815491329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3815491329
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3473929020
Short name T400
Test name
Test status
Simulation time 196121004 ps
CPU time 1.36 seconds
Started Jun 21 05:12:43 PM PDT 24
Finished Jun 21 05:12:46 PM PDT 24
Peak memory 200856 kb
Host smart-da36c4ca-0faa-4259-8e90-b509dc2a57a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473929020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3473929020
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2916488568
Short name T429
Test name
Test status
Simulation time 3897066752 ps
CPU time 14.14 seconds
Started Jun 21 05:12:48 PM PDT 24
Finished Jun 21 05:13:05 PM PDT 24
Peak memory 209128 kb
Host smart-73c38b12-f27f-4611-9e81-4b2cfca22230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916488568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2916488568
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.1903443838
Short name T358
Test name
Test status
Simulation time 387366679 ps
CPU time 2.33 seconds
Started Jun 21 05:12:48 PM PDT 24
Finished Jun 21 05:12:52 PM PDT 24
Peak memory 200728 kb
Host smart-a46500fa-2f4f-4372-b502-6d6e92b76b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903443838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1903443838
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2289293728
Short name T136
Test name
Test status
Simulation time 71151454 ps
CPU time 0.75 seconds
Started Jun 21 05:12:46 PM PDT 24
Finished Jun 21 05:12:48 PM PDT 24
Peak memory 200696 kb
Host smart-4f372514-1c79-475c-b4f3-d5b3d47c6ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289293728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2289293728
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.4209320873
Short name T517
Test name
Test status
Simulation time 236952143 ps
CPU time 1.06 seconds
Started Jun 21 05:12:46 PM PDT 24
Finished Jun 21 05:12:48 PM PDT 24
Peak memory 200488 kb
Host smart-5b8e863e-ea4b-4be2-bcd2-6fd8f8c6587a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209320873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.4209320873
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2333779892
Short name T40
Test name
Test status
Simulation time 2369002254 ps
CPU time 8.15 seconds
Started Jun 21 05:12:48 PM PDT 24
Finished Jun 21 05:12:59 PM PDT 24
Peak memory 218308 kb
Host smart-da28b749-7ea9-4356-9cca-60d4025774e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333779892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2333779892
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.825461300
Short name T174
Test name
Test status
Simulation time 244114267 ps
CPU time 1.07 seconds
Started Jun 21 05:12:49 PM PDT 24
Finished Jun 21 05:12:53 PM PDT 24
Peak memory 218068 kb
Host smart-b56c1296-d992-4139-9930-62d0982f8c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825461300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.825461300
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1958697753
Short name T362
Test name
Test status
Simulation time 154574127 ps
CPU time 0.84 seconds
Started Jun 21 05:12:51 PM PDT 24
Finished Jun 21 05:12:55 PM PDT 24
Peak memory 200488 kb
Host smart-ab1d0a55-8466-4a8c-91a0-5cd8d14b85ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958697753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1958697753
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2100577724
Short name T132
Test name
Test status
Simulation time 1368164906 ps
CPU time 5.46 seconds
Started Jun 21 05:12:47 PM PDT 24
Finished Jun 21 05:12:54 PM PDT 24
Peak memory 200828 kb
Host smart-2495eda3-fe36-4a3f-ba4b-01656b39009c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100577724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2100577724
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3635957258
Short name T184
Test name
Test status
Simulation time 144068796 ps
CPU time 1.11 seconds
Started Jun 21 05:12:49 PM PDT 24
Finished Jun 21 05:12:53 PM PDT 24
Peak memory 200668 kb
Host smart-2f6277c6-688c-4d78-82fe-6cd064363855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635957258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3635957258
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.719481302
Short name T275
Test name
Test status
Simulation time 111910671 ps
CPU time 1.2 seconds
Started Jun 21 05:12:47 PM PDT 24
Finished Jun 21 05:12:49 PM PDT 24
Peak memory 200840 kb
Host smart-1c65f032-3f7b-464b-85eb-0e27b0767003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719481302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.719481302
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3994440900
Short name T502
Test name
Test status
Simulation time 3730058268 ps
CPU time 15.24 seconds
Started Jun 21 05:12:50 PM PDT 24
Finished Jun 21 05:13:08 PM PDT 24
Peak memory 209116 kb
Host smart-e802981a-c2c8-43c4-b33e-35de5fa1b06c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994440900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3994440900
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.4036366463
Short name T534
Test name
Test status
Simulation time 290867779 ps
CPU time 2.15 seconds
Started Jun 21 05:12:50 PM PDT 24
Finished Jun 21 05:12:55 PM PDT 24
Peak memory 200656 kb
Host smart-0bcb1cdc-b182-4e47-a2f7-7a1b6d8b3918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036366463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.4036366463
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2626465043
Short name T268
Test name
Test status
Simulation time 157651513 ps
CPU time 1.31 seconds
Started Jun 21 05:12:48 PM PDT 24
Finished Jun 21 05:12:52 PM PDT 24
Peak memory 200868 kb
Host smart-cbfe417e-6ea1-41d0-9a59-16a3810ce9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626465043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2626465043
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2811113935
Short name T322
Test name
Test status
Simulation time 66480649 ps
CPU time 0.75 seconds
Started Jun 21 05:12:48 PM PDT 24
Finished Jun 21 05:12:51 PM PDT 24
Peak memory 200484 kb
Host smart-221aedb9-55bc-44e0-8b9e-688ea8e76301
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811113935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2811113935
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.1463982081
Short name T447
Test name
Test status
Simulation time 1882494742 ps
CPU time 7.11 seconds
Started Jun 21 05:12:48 PM PDT 24
Finished Jun 21 05:12:57 PM PDT 24
Peak memory 222424 kb
Host smart-f01a81cf-ea14-426f-89e5-7d23f6cd3a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463982081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1463982081
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1843160185
Short name T493
Test name
Test status
Simulation time 244239946 ps
CPU time 1.15 seconds
Started Jun 21 05:12:48 PM PDT 24
Finished Jun 21 05:12:52 PM PDT 24
Peak memory 217996 kb
Host smart-9c846d53-e9fe-4bfb-b2ed-38b99a555300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843160185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1843160185
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.162961237
Short name T17
Test name
Test status
Simulation time 155526766 ps
CPU time 0.85 seconds
Started Jun 21 05:12:46 PM PDT 24
Finished Jun 21 05:12:48 PM PDT 24
Peak memory 200424 kb
Host smart-296d9c0a-ec3e-4f02-80c7-88b7eafa03f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162961237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.162961237
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1004289533
Short name T131
Test name
Test status
Simulation time 1435421304 ps
CPU time 5.82 seconds
Started Jun 21 05:12:46 PM PDT 24
Finished Jun 21 05:12:53 PM PDT 24
Peak memory 200880 kb
Host smart-63d5adf6-1c04-4913-b19c-610a82d46a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004289533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1004289533
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2639979019
Short name T384
Test name
Test status
Simulation time 142734752 ps
CPU time 1.06 seconds
Started Jun 21 05:12:48 PM PDT 24
Finished Jun 21 05:12:52 PM PDT 24
Peak memory 200648 kb
Host smart-cd5fc5ab-f6d7-4a63-9bff-95520928d636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639979019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2639979019
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.2907486640
Short name T496
Test name
Test status
Simulation time 118080077 ps
CPU time 1.25 seconds
Started Jun 21 05:12:49 PM PDT 24
Finished Jun 21 05:12:53 PM PDT 24
Peak memory 200904 kb
Host smart-52047523-7b0e-45b6-a7f7-0c564efa091d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907486640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2907486640
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.406456015
Short name T308
Test name
Test status
Simulation time 197444797 ps
CPU time 1.2 seconds
Started Jun 21 05:12:48 PM PDT 24
Finished Jun 21 05:12:52 PM PDT 24
Peak memory 200604 kb
Host smart-7cb2cd79-7fa5-4a8c-bf47-eda3a30426a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406456015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.406456015
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.999424238
Short name T512
Test name
Test status
Simulation time 172326488 ps
CPU time 1.2 seconds
Started Jun 21 05:12:49 PM PDT 24
Finished Jun 21 05:12:53 PM PDT 24
Peak memory 200688 kb
Host smart-dd4fe439-86c6-4ab1-91f2-99f56f258ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999424238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.999424238
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1723436866
Short name T224
Test name
Test status
Simulation time 77032088 ps
CPU time 0.78 seconds
Started Jun 21 05:12:48 PM PDT 24
Finished Jun 21 05:12:51 PM PDT 24
Peak memory 200504 kb
Host smart-cf063175-445a-4e72-a185-0dfac0083cd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723436866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1723436866
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1012789426
Short name T57
Test name
Test status
Simulation time 1903972336 ps
CPU time 7.49 seconds
Started Jun 21 05:12:49 PM PDT 24
Finished Jun 21 05:12:59 PM PDT 24
Peak memory 218120 kb
Host smart-8e6fc5ba-ea18-49df-a51a-85565bd45a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012789426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1012789426
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3896787344
Short name T455
Test name
Test status
Simulation time 244619034 ps
CPU time 1.08 seconds
Started Jun 21 05:12:52 PM PDT 24
Finished Jun 21 05:12:56 PM PDT 24
Peak memory 218040 kb
Host smart-a94a6eef-085f-4e6c-8d68-a185b7732137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896787344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3896787344
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.534972133
Short name T370
Test name
Test status
Simulation time 132897862 ps
CPU time 0.87 seconds
Started Jun 21 05:12:49 PM PDT 24
Finished Jun 21 05:12:53 PM PDT 24
Peak memory 200452 kb
Host smart-159e2cf7-a6ef-44f1-a664-e7c964948a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534972133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.534972133
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.1443533161
Short name T177
Test name
Test status
Simulation time 1398424002 ps
CPU time 5.39 seconds
Started Jun 21 05:12:49 PM PDT 24
Finished Jun 21 05:12:57 PM PDT 24
Peak memory 200860 kb
Host smart-e4ef99b2-aa9c-4dba-be95-39be8f46480e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443533161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1443533161
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1144098584
Short name T522
Test name
Test status
Simulation time 101939535 ps
CPU time 0.95 seconds
Started Jun 21 05:12:51 PM PDT 24
Finished Jun 21 05:12:55 PM PDT 24
Peak memory 200672 kb
Host smart-6839f9b1-1a6e-47bc-b2e0-bd7ba88b3b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144098584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1144098584
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.1017806305
Short name T331
Test name
Test status
Simulation time 201564854 ps
CPU time 1.39 seconds
Started Jun 21 05:12:48 PM PDT 24
Finished Jun 21 05:12:52 PM PDT 24
Peak memory 200880 kb
Host smart-7ce8ed8b-a386-4c16-ad44-21e40af011c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017806305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1017806305
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.38395251
Short name T130
Test name
Test status
Simulation time 3842725513 ps
CPU time 15.28 seconds
Started Jun 21 05:12:49 PM PDT 24
Finished Jun 21 05:13:06 PM PDT 24
Peak memory 200872 kb
Host smart-e9bd092b-99ca-4ad2-b32f-854db9376f29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38395251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.38395251
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1382164361
Short name T167
Test name
Test status
Simulation time 287164866 ps
CPU time 1.89 seconds
Started Jun 21 05:12:48 PM PDT 24
Finished Jun 21 05:12:52 PM PDT 24
Peak memory 200656 kb
Host smart-81ddde4c-1c76-4ecf-8c8b-ab308531580a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382164361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1382164361
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2908823828
Short name T134
Test name
Test status
Simulation time 161238358 ps
CPU time 1.16 seconds
Started Jun 21 05:12:47 PM PDT 24
Finished Jun 21 05:12:50 PM PDT 24
Peak memory 200708 kb
Host smart-bbea8037-3d68-4fb3-ac60-a4dcbf808478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908823828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2908823828
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1106392246
Short name T309
Test name
Test status
Simulation time 63114439 ps
CPU time 0.76 seconds
Started Jun 21 05:12:14 PM PDT 24
Finished Jun 21 05:12:17 PM PDT 24
Peak memory 200424 kb
Host smart-e1a14271-59e2-4d73-9cb5-8576478b8216
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106392246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1106392246
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2798575701
Short name T424
Test name
Test status
Simulation time 2361843335 ps
CPU time 8.1 seconds
Started Jun 21 05:12:15 PM PDT 24
Finished Jun 21 05:12:25 PM PDT 24
Peak memory 218524 kb
Host smart-21f7b23a-65c4-4a34-a590-1be4d8dc6120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798575701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2798575701
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1156364282
Short name T536
Test name
Test status
Simulation time 245315036 ps
CPU time 1.03 seconds
Started Jun 21 05:12:13 PM PDT 24
Finished Jun 21 05:12:15 PM PDT 24
Peak memory 218072 kb
Host smart-e6b9620e-bd75-441c-b169-54d28a70fc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156364282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1156364282
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3323226932
Short name T452
Test name
Test status
Simulation time 88082774 ps
CPU time 0.74 seconds
Started Jun 21 05:12:15 PM PDT 24
Finished Jun 21 05:12:18 PM PDT 24
Peak memory 200484 kb
Host smart-c6d36dc8-4975-44b7-8207-8cb971833efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323226932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3323226932
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1083102941
Short name T203
Test name
Test status
Simulation time 1180322571 ps
CPU time 4.6 seconds
Started Jun 21 05:12:16 PM PDT 24
Finished Jun 21 05:12:22 PM PDT 24
Peak memory 200792 kb
Host smart-6622c4e7-6c2a-48da-88e9-97259d7cdfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083102941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1083102941
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.3181043010
Short name T71
Test name
Test status
Simulation time 26350488588 ps
CPU time 43.79 seconds
Started Jun 21 05:12:17 PM PDT 24
Finished Jun 21 05:13:02 PM PDT 24
Peak memory 218520 kb
Host smart-318389fd-e82d-4797-b305-625c78c0f6a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181043010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3181043010
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1161688242
Short name T263
Test name
Test status
Simulation time 146981542 ps
CPU time 1.13 seconds
Started Jun 21 05:12:19 PM PDT 24
Finished Jun 21 05:12:21 PM PDT 24
Peak memory 200628 kb
Host smart-f5db48ad-fd3c-474c-917a-4372c3d38ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161688242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1161688242
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3531568255
Short name T150
Test name
Test status
Simulation time 113193871 ps
CPU time 1.13 seconds
Started Jun 21 05:12:14 PM PDT 24
Finished Jun 21 05:12:17 PM PDT 24
Peak memory 200916 kb
Host smart-20a7c550-4a32-4d1c-8ebe-ad1073b3ca60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531568255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3531568255
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2061370462
Short name T539
Test name
Test status
Simulation time 10361403102 ps
CPU time 35.7 seconds
Started Jun 21 05:12:14 PM PDT 24
Finished Jun 21 05:12:51 PM PDT 24
Peak memory 209064 kb
Host smart-7735f0d7-3b13-49be-8e75-55a903d14df6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061370462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2061370462
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3935940111
Short name T492
Test name
Test status
Simulation time 370699131 ps
CPU time 1.96 seconds
Started Jun 21 05:12:17 PM PDT 24
Finished Jun 21 05:12:21 PM PDT 24
Peak memory 200684 kb
Host smart-6cff9b7c-fafc-4c54-b6b2-e02981d09e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935940111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3935940111
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1192087358
Short name T348
Test name
Test status
Simulation time 229706250 ps
CPU time 1.41 seconds
Started Jun 21 05:12:14 PM PDT 24
Finished Jun 21 05:12:17 PM PDT 24
Peak memory 200688 kb
Host smart-55d52994-29f8-4b7e-bef2-8fc8731b8eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192087358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1192087358
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3575842349
Short name T357
Test name
Test status
Simulation time 76704294 ps
CPU time 0.82 seconds
Started Jun 21 05:13:03 PM PDT 24
Finished Jun 21 05:13:05 PM PDT 24
Peak memory 200484 kb
Host smart-d57cf884-b553-48b1-a102-4a286630a276
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575842349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3575842349
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.4078229984
Short name T236
Test name
Test status
Simulation time 2369958803 ps
CPU time 8.89 seconds
Started Jun 21 05:12:57 PM PDT 24
Finished Jun 21 05:13:08 PM PDT 24
Peak memory 222452 kb
Host smart-d1cd7b96-de27-466b-bda9-24edec42cace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078229984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.4078229984
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.181509096
Short name T328
Test name
Test status
Simulation time 243949601 ps
CPU time 1.06 seconds
Started Jun 21 05:12:55 PM PDT 24
Finished Jun 21 05:12:59 PM PDT 24
Peak memory 218052 kb
Host smart-1fed54fd-c450-44d8-9e97-3858f4a74219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181509096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.181509096
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2306794495
Short name T486
Test name
Test status
Simulation time 145204972 ps
CPU time 0.81 seconds
Started Jun 21 05:12:48 PM PDT 24
Finished Jun 21 05:12:51 PM PDT 24
Peak memory 200496 kb
Host smart-9ca5a1c6-9292-463f-a290-586f24a8e271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306794495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2306794495
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.805444896
Short name T411
Test name
Test status
Simulation time 1418799515 ps
CPU time 4.99 seconds
Started Jun 21 05:12:46 PM PDT 24
Finished Jun 21 05:12:52 PM PDT 24
Peak memory 200868 kb
Host smart-1971b451-e94a-4f2a-aeec-e642ebdd8ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805444896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.805444896
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3150449293
Short name T162
Test name
Test status
Simulation time 180158861 ps
CPU time 1.19 seconds
Started Jun 21 05:12:49 PM PDT 24
Finished Jun 21 05:12:54 PM PDT 24
Peak memory 200660 kb
Host smart-dbbb29ce-b6aa-4a83-a2c9-701176fec86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150449293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3150449293
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1517172564
Short name T481
Test name
Test status
Simulation time 124119025 ps
CPU time 1.18 seconds
Started Jun 21 05:12:50 PM PDT 24
Finished Jun 21 05:12:54 PM PDT 24
Peak memory 200868 kb
Host smart-0b37ee33-3bbe-479c-9cbb-327c81a279c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517172564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1517172564
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.1409909307
Short name T219
Test name
Test status
Simulation time 5159199344 ps
CPU time 18.49 seconds
Started Jun 21 05:13:03 PM PDT 24
Finished Jun 21 05:13:23 PM PDT 24
Peak memory 200888 kb
Host smart-b1cc026d-ab48-41b5-b8bd-9e96b8ede8d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409909307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1409909307
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.4163152371
Short name T408
Test name
Test status
Simulation time 380542319 ps
CPU time 2.44 seconds
Started Jun 21 05:12:47 PM PDT 24
Finished Jun 21 05:12:52 PM PDT 24
Peak memory 200652 kb
Host smart-03262195-05cf-4045-8fe9-1e107436e81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163152371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.4163152371
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.583511819
Short name T202
Test name
Test status
Simulation time 128194860 ps
CPU time 1.12 seconds
Started Jun 21 05:12:52 PM PDT 24
Finished Jun 21 05:12:56 PM PDT 24
Peak memory 200676 kb
Host smart-fd352180-970d-4d10-be33-b70f392f563c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583511819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.583511819
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1003999855
Short name T200
Test name
Test status
Simulation time 71021687 ps
CPU time 0.78 seconds
Started Jun 21 05:12:57 PM PDT 24
Finished Jun 21 05:13:00 PM PDT 24
Peak memory 200488 kb
Host smart-a35e23f2-232b-487c-a23a-cb2b62d2a086
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003999855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1003999855
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1730629448
Short name T418
Test name
Test status
Simulation time 1909092614 ps
CPU time 7.27 seconds
Started Jun 21 05:12:55 PM PDT 24
Finished Jun 21 05:13:04 PM PDT 24
Peak memory 222392 kb
Host smart-161b8fea-1706-4657-8bfb-96010563a815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730629448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1730629448
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3590554543
Short name T269
Test name
Test status
Simulation time 245573047 ps
CPU time 1 seconds
Started Jun 21 05:12:55 PM PDT 24
Finished Jun 21 05:12:59 PM PDT 24
Peak memory 218044 kb
Host smart-d35da7fd-cb6b-4363-8afa-df4734bdee37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590554543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3590554543
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3323047903
Short name T381
Test name
Test status
Simulation time 101948462 ps
CPU time 0.8 seconds
Started Jun 21 05:12:57 PM PDT 24
Finished Jun 21 05:13:00 PM PDT 24
Peak memory 200504 kb
Host smart-903538df-9ae4-4c2e-9a8c-d611c53bcbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323047903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3323047903
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.1007138148
Short name T274
Test name
Test status
Simulation time 1882205361 ps
CPU time 7.04 seconds
Started Jun 21 05:12:57 PM PDT 24
Finished Jun 21 05:13:06 PM PDT 24
Peak memory 200908 kb
Host smart-5ffabf63-2999-471e-8a4e-71bdb39b4ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007138148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.1007138148
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.4219226021
Short name T12
Test name
Test status
Simulation time 148573730 ps
CPU time 1.12 seconds
Started Jun 21 05:12:59 PM PDT 24
Finished Jun 21 05:13:02 PM PDT 24
Peak memory 200616 kb
Host smart-75c29421-e546-4346-be8c-c789cd9f9713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219226021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.4219226021
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3167450413
Short name T281
Test name
Test status
Simulation time 248996375 ps
CPU time 1.49 seconds
Started Jun 21 05:12:57 PM PDT 24
Finished Jun 21 05:13:00 PM PDT 24
Peak memory 200872 kb
Host smart-2ceabd3a-5ae4-4650-9447-ab862fc78004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167450413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3167450413
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1124271312
Short name T260
Test name
Test status
Simulation time 6415747899 ps
CPU time 21.05 seconds
Started Jun 21 05:12:58 PM PDT 24
Finished Jun 21 05:13:21 PM PDT 24
Peak memory 209124 kb
Host smart-99b48dd5-8741-40ba-bc90-86522b67ae6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124271312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1124271312
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.393529566
Short name T538
Test name
Test status
Simulation time 138455223 ps
CPU time 1.78 seconds
Started Jun 21 05:12:56 PM PDT 24
Finished Jun 21 05:13:00 PM PDT 24
Peak memory 200656 kb
Host smart-63808a46-30cf-4a6b-995d-0c75c59fd832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393529566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.393529566
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3569268678
Short name T209
Test name
Test status
Simulation time 119278036 ps
CPU time 0.96 seconds
Started Jun 21 05:12:56 PM PDT 24
Finished Jun 21 05:12:59 PM PDT 24
Peak memory 200636 kb
Host smart-fbd10d3f-db20-4dfc-8ea3-8777bd078e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569268678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3569268678
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2576858694
Short name T474
Test name
Test status
Simulation time 66617639 ps
CPU time 0.75 seconds
Started Jun 21 05:12:55 PM PDT 24
Finished Jun 21 05:12:58 PM PDT 24
Peak memory 200484 kb
Host smart-859d2f1f-4418-4090-ae6c-af70e565c507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576858694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2576858694
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2619232932
Short name T52
Test name
Test status
Simulation time 1224956961 ps
CPU time 5.98 seconds
Started Jun 21 05:12:56 PM PDT 24
Finished Jun 21 05:13:04 PM PDT 24
Peak memory 217976 kb
Host smart-11e56b08-3ccf-4cd8-bac0-9b4ebf954773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619232932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2619232932
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2388783626
Short name T402
Test name
Test status
Simulation time 245406226 ps
CPU time 1.14 seconds
Started Jun 21 05:12:58 PM PDT 24
Finished Jun 21 05:13:01 PM PDT 24
Peak memory 218176 kb
Host smart-6abff6ff-dd3e-4f20-9be4-2b57437367a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388783626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2388783626
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.1294422268
Short name T249
Test name
Test status
Simulation time 119196942 ps
CPU time 0.8 seconds
Started Jun 21 05:12:58 PM PDT 24
Finished Jun 21 05:13:01 PM PDT 24
Peak memory 200496 kb
Host smart-f4eba443-0ae0-490c-b471-b3c8b7be3ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294422268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1294422268
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3846401355
Short name T365
Test name
Test status
Simulation time 1573749059 ps
CPU time 6.65 seconds
Started Jun 21 05:12:55 PM PDT 24
Finished Jun 21 05:13:04 PM PDT 24
Peak memory 200868 kb
Host smart-513f225d-b4ca-474d-8271-64a5ffa5c27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846401355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3846401355
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2770827518
Short name T4
Test name
Test status
Simulation time 161817414 ps
CPU time 1.21 seconds
Started Jun 21 05:12:58 PM PDT 24
Finished Jun 21 05:13:01 PM PDT 24
Peak memory 200616 kb
Host smart-0e01fa30-6d9f-4041-87e5-ce44c82bec5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770827518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2770827518
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3604198254
Short name T197
Test name
Test status
Simulation time 245653243 ps
CPU time 1.47 seconds
Started Jun 21 05:12:58 PM PDT 24
Finished Jun 21 05:13:02 PM PDT 24
Peak memory 200876 kb
Host smart-c83f3973-d59a-496e-80a4-0af0e37b1dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604198254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3604198254
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.126982587
Short name T244
Test name
Test status
Simulation time 2040383169 ps
CPU time 7.66 seconds
Started Jun 21 05:12:58 PM PDT 24
Finished Jun 21 05:13:08 PM PDT 24
Peak memory 209064 kb
Host smart-67ae1c9b-2acc-4e00-a499-ec5a65e18a47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126982587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.126982587
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2398662032
Short name T259
Test name
Test status
Simulation time 136195222 ps
CPU time 1.65 seconds
Started Jun 21 05:12:56 PM PDT 24
Finished Jun 21 05:12:59 PM PDT 24
Peak memory 208872 kb
Host smart-7a1ffd99-1414-45bc-84ee-5e0da6b5c151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398662032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2398662032
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1216492615
Short name T179
Test name
Test status
Simulation time 219534303 ps
CPU time 1.36 seconds
Started Jun 21 05:12:57 PM PDT 24
Finished Jun 21 05:13:01 PM PDT 24
Peak memory 200616 kb
Host smart-f02e00ee-93d4-4033-acf9-37067ec20b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216492615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1216492615
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1084578614
Short name T247
Test name
Test status
Simulation time 73121975 ps
CPU time 0.82 seconds
Started Jun 21 05:13:08 PM PDT 24
Finished Jun 21 05:13:14 PM PDT 24
Peak memory 200484 kb
Host smart-e8a04a9d-4555-4dec-b48e-a5ae9c135cdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084578614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1084578614
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3331200657
Short name T34
Test name
Test status
Simulation time 1227252501 ps
CPU time 5.49 seconds
Started Jun 21 05:12:56 PM PDT 24
Finished Jun 21 05:13:03 PM PDT 24
Peak memory 218560 kb
Host smart-ffc22175-4d6c-4661-a0c5-af970cffa26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331200657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3331200657
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.705970220
Short name T305
Test name
Test status
Simulation time 246458487 ps
CPU time 1.12 seconds
Started Jun 21 05:12:57 PM PDT 24
Finished Jun 21 05:13:00 PM PDT 24
Peak memory 218040 kb
Host smart-e368bd2b-3a43-4092-aeca-3f5fa96f8fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705970220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.705970220
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2270271489
Short name T336
Test name
Test status
Simulation time 122271902 ps
CPU time 0.83 seconds
Started Jun 21 05:13:02 PM PDT 24
Finished Jun 21 05:13:05 PM PDT 24
Peak memory 200504 kb
Host smart-1f57a0b2-b1ea-4dad-bdda-4b62c6d6c4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270271489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2270271489
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1708664697
Short name T129
Test name
Test status
Simulation time 1478843200 ps
CPU time 6.15 seconds
Started Jun 21 05:12:56 PM PDT 24
Finished Jun 21 05:13:04 PM PDT 24
Peak memory 200864 kb
Host smart-5677bd2f-2c3f-417a-94e4-f1b45bd970c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708664697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1708664697
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3507480297
Short name T419
Test name
Test status
Simulation time 147148810 ps
CPU time 1.19 seconds
Started Jun 21 05:12:58 PM PDT 24
Finished Jun 21 05:13:02 PM PDT 24
Peak memory 200792 kb
Host smart-50b5a986-9413-4882-a789-d4d955fc4d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507480297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3507480297
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2563998402
Short name T399
Test name
Test status
Simulation time 247695831 ps
CPU time 1.54 seconds
Started Jun 21 05:12:59 PM PDT 24
Finished Jun 21 05:13:02 PM PDT 24
Peak memory 200884 kb
Host smart-3274f9ba-dbff-4c44-a0c7-70d78465c7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563998402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2563998402
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2693840995
Short name T435
Test name
Test status
Simulation time 5992826096 ps
CPU time 21.51 seconds
Started Jun 21 05:13:11 PM PDT 24
Finished Jun 21 05:13:38 PM PDT 24
Peak memory 200948 kb
Host smart-6fba1793-85c6-4a31-af6a-b75c69c30fbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693840995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2693840995
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.527974885
Short name T81
Test name
Test status
Simulation time 129203315 ps
CPU time 1.6 seconds
Started Jun 21 05:12:55 PM PDT 24
Finished Jun 21 05:12:59 PM PDT 24
Peak memory 208900 kb
Host smart-eed3de45-912b-4663-854b-3c74d2705938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527974885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.527974885
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1674769201
Short name T301
Test name
Test status
Simulation time 106527444 ps
CPU time 1.03 seconds
Started Jun 21 05:12:57 PM PDT 24
Finished Jun 21 05:13:00 PM PDT 24
Peak memory 200692 kb
Host smart-00540783-abc4-4648-b3da-1e14c9365416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674769201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1674769201
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2021671046
Short name T480
Test name
Test status
Simulation time 69157509 ps
CPU time 0.81 seconds
Started Jun 21 05:13:10 PM PDT 24
Finished Jun 21 05:13:16 PM PDT 24
Peak memory 200436 kb
Host smart-cb27733b-9efa-496a-963f-d8b2c5fcaee4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021671046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2021671046
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3462235895
Short name T30
Test name
Test status
Simulation time 1902635132 ps
CPU time 8.1 seconds
Started Jun 21 05:13:10 PM PDT 24
Finished Jun 21 05:13:24 PM PDT 24
Peak memory 218420 kb
Host smart-47b911fe-3da6-4b23-ae3f-4f4065da2cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462235895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3462235895
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.4098059942
Short name T15
Test name
Test status
Simulation time 245065792 ps
CPU time 1.1 seconds
Started Jun 21 05:13:08 PM PDT 24
Finished Jun 21 05:13:13 PM PDT 24
Peak memory 218060 kb
Host smart-08aebe8d-aeff-4d05-b348-4f931c0012c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098059942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.4098059942
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.192552052
Short name T19
Test name
Test status
Simulation time 190033945 ps
CPU time 0.89 seconds
Started Jun 21 05:13:08 PM PDT 24
Finished Jun 21 05:13:14 PM PDT 24
Peak memory 200472 kb
Host smart-caba8cda-d4ef-4fce-a7df-ad15667acf8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192552052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.192552052
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.501166120
Short name T270
Test name
Test status
Simulation time 1220117066 ps
CPU time 4.71 seconds
Started Jun 21 05:13:08 PM PDT 24
Finished Jun 21 05:13:15 PM PDT 24
Peak memory 200868 kb
Host smart-ae62e39f-1882-4e7d-9078-05cc087bcf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501166120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.501166120
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3195715154
Short name T282
Test name
Test status
Simulation time 144618299 ps
CPU time 1.12 seconds
Started Jun 21 05:13:07 PM PDT 24
Finished Jun 21 05:13:10 PM PDT 24
Peak memory 200688 kb
Host smart-ffe18ca1-83b8-4bd1-a57d-333a5c883762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195715154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3195715154
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1607512935
Short name T332
Test name
Test status
Simulation time 248457866 ps
CPU time 1.6 seconds
Started Jun 21 05:13:08 PM PDT 24
Finished Jun 21 05:13:15 PM PDT 24
Peak memory 200840 kb
Host smart-d1619876-3e26-4471-87bd-523c3d1f0114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607512935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1607512935
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3127823425
Short name T327
Test name
Test status
Simulation time 4652032717 ps
CPU time 21.64 seconds
Started Jun 21 05:13:08 PM PDT 24
Finished Jun 21 05:13:35 PM PDT 24
Peak memory 210716 kb
Host smart-8cf5fd58-eac4-4e39-bf13-25cd1645af2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127823425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3127823425
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.961404636
Short name T149
Test name
Test status
Simulation time 127704033 ps
CPU time 1.59 seconds
Started Jun 21 05:13:08 PM PDT 24
Finished Jun 21 05:13:15 PM PDT 24
Peak memory 208948 kb
Host smart-6f15e557-1ba5-4a5f-9ac2-8cd5ababdb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961404636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.961404636
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3302963286
Short name T478
Test name
Test status
Simulation time 90456803 ps
CPU time 0.87 seconds
Started Jun 21 05:13:07 PM PDT 24
Finished Jun 21 05:13:12 PM PDT 24
Peak memory 200668 kb
Host smart-5588744e-0f5a-4351-8ca0-535de6b26874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302963286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3302963286
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1429176625
Short name T278
Test name
Test status
Simulation time 73694022 ps
CPU time 0.81 seconds
Started Jun 21 05:13:10 PM PDT 24
Finished Jun 21 05:13:15 PM PDT 24
Peak memory 200500 kb
Host smart-b5b11cfd-16c4-49ef-b777-320865feaabc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429176625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1429176625
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1884636508
Short name T395
Test name
Test status
Simulation time 243743107 ps
CPU time 1.17 seconds
Started Jun 21 05:13:09 PM PDT 24
Finished Jun 21 05:13:15 PM PDT 24
Peak memory 218044 kb
Host smart-9bac1099-6dfb-4024-9cbb-1d35f4cb039a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884636508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1884636508
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.4078343255
Short name T16
Test name
Test status
Simulation time 179279968 ps
CPU time 0.88 seconds
Started Jun 21 05:13:08 PM PDT 24
Finished Jun 21 05:13:13 PM PDT 24
Peak memory 200432 kb
Host smart-fe451b8b-fb31-40aa-8a13-103f1f926c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078343255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.4078343255
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2173320672
Short name T323
Test name
Test status
Simulation time 741155247 ps
CPU time 4.17 seconds
Started Jun 21 05:13:09 PM PDT 24
Finished Jun 21 05:13:18 PM PDT 24
Peak memory 200864 kb
Host smart-ff3e0796-6006-4195-aff8-eb6e0caf39fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173320672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2173320672
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.614107043
Short name T490
Test name
Test status
Simulation time 109066170 ps
CPU time 0.99 seconds
Started Jun 21 05:13:07 PM PDT 24
Finished Jun 21 05:13:11 PM PDT 24
Peak memory 200604 kb
Host smart-b055e0cc-064f-49d0-8e2a-27919b85a3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614107043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.614107043
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.195499817
Short name T230
Test name
Test status
Simulation time 201037358 ps
CPU time 1.38 seconds
Started Jun 21 05:13:10 PM PDT 24
Finished Jun 21 05:13:16 PM PDT 24
Peak memory 200828 kb
Host smart-33457274-e282-4c9b-9c14-479fbf423075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195499817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.195499817
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1674614808
Short name T89
Test name
Test status
Simulation time 1272368801 ps
CPU time 5.75 seconds
Started Jun 21 05:13:09 PM PDT 24
Finished Jun 21 05:13:20 PM PDT 24
Peak memory 200896 kb
Host smart-948d995d-ebdb-4546-b283-e9e6bef041cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674614808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1674614808
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1529868358
Short name T1
Test name
Test status
Simulation time 119950415 ps
CPU time 1.42 seconds
Started Jun 21 05:13:07 PM PDT 24
Finished Jun 21 05:13:12 PM PDT 24
Peak memory 200652 kb
Host smart-ea36ee79-c9fc-46ae-86d3-92dafe7ea3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529868358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1529868358
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2789380857
Short name T173
Test name
Test status
Simulation time 83604927 ps
CPU time 0.82 seconds
Started Jun 21 05:13:08 PM PDT 24
Finished Jun 21 05:13:12 PM PDT 24
Peak memory 200620 kb
Host smart-398bf9a9-e422-4ae8-8824-c4a9c9bc41f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789380857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2789380857
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1523208139
Short name T423
Test name
Test status
Simulation time 77274634 ps
CPU time 0.81 seconds
Started Jun 21 05:13:10 PM PDT 24
Finished Jun 21 05:13:15 PM PDT 24
Peak memory 200428 kb
Host smart-b4ed7e8b-54c8-4dab-9c41-e13f546aa0f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523208139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1523208139
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.3066567795
Short name T441
Test name
Test status
Simulation time 2356890534 ps
CPU time 7.95 seconds
Started Jun 21 05:13:10 PM PDT 24
Finished Jun 21 05:13:23 PM PDT 24
Peak memory 222484 kb
Host smart-8b0b7822-f3f1-44c1-85d9-3f99fcb12252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066567795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3066567795
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2443292021
Short name T273
Test name
Test status
Simulation time 243374087 ps
CPU time 1.13 seconds
Started Jun 21 05:13:10 PM PDT 24
Finished Jun 21 05:13:17 PM PDT 24
Peak memory 218084 kb
Host smart-0716fc76-ffb8-4542-b21a-25e204a4fa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443292021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2443292021
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1923512745
Short name T238
Test name
Test status
Simulation time 113945154 ps
CPU time 0.76 seconds
Started Jun 21 05:13:10 PM PDT 24
Finished Jun 21 05:13:16 PM PDT 24
Peak memory 200456 kb
Host smart-2a6466fc-cfb8-4ac1-806b-5da83679bec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923512745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1923512745
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1157188612
Short name T467
Test name
Test status
Simulation time 1378452865 ps
CPU time 5.73 seconds
Started Jun 21 05:13:07 PM PDT 24
Finished Jun 21 05:13:15 PM PDT 24
Peak memory 200988 kb
Host smart-50a6e96a-4934-4a96-a8bf-9f6b3fce9c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157188612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1157188612
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.334788283
Short name T532
Test name
Test status
Simulation time 103124091 ps
CPU time 1.01 seconds
Started Jun 21 05:13:07 PM PDT 24
Finished Jun 21 05:13:11 PM PDT 24
Peak memory 200664 kb
Host smart-6eac1019-1cdb-4451-817f-fc00dfd331c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334788283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.334788283
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1582589645
Short name T344
Test name
Test status
Simulation time 187361831 ps
CPU time 1.41 seconds
Started Jun 21 05:13:10 PM PDT 24
Finished Jun 21 05:13:17 PM PDT 24
Peak memory 200836 kb
Host smart-eefb6f59-9d2b-4db3-965e-15fce3aed746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582589645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1582589645
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2889592980
Short name T80
Test name
Test status
Simulation time 9479557864 ps
CPU time 36.33 seconds
Started Jun 21 05:13:09 PM PDT 24
Finished Jun 21 05:13:50 PM PDT 24
Peak memory 200936 kb
Host smart-c10cb629-8275-493b-b4a3-82f5f7390f5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889592980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2889592980
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.1115005530
Short name T223
Test name
Test status
Simulation time 333696422 ps
CPU time 2.21 seconds
Started Jun 21 05:13:08 PM PDT 24
Finished Jun 21 05:13:14 PM PDT 24
Peak memory 208928 kb
Host smart-93354ec4-c389-4a80-aec7-150ef425c5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115005530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.1115005530
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2748765503
Short name T284
Test name
Test status
Simulation time 133327270 ps
CPU time 1.09 seconds
Started Jun 21 05:13:07 PM PDT 24
Finished Jun 21 05:13:10 PM PDT 24
Peak memory 200652 kb
Host smart-65b38a56-5929-4bfd-9a9e-c8969a14d35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748765503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2748765503
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1183867787
Short name T257
Test name
Test status
Simulation time 57482841 ps
CPU time 0.72 seconds
Started Jun 21 05:13:08 PM PDT 24
Finished Jun 21 05:13:13 PM PDT 24
Peak memory 200472 kb
Host smart-2ccfd7af-ffc6-4084-81b7-a5ce762d9214
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183867787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1183867787
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1394050812
Short name T51
Test name
Test status
Simulation time 1899708960 ps
CPU time 7.3 seconds
Started Jun 21 05:13:10 PM PDT 24
Finished Jun 21 05:13:22 PM PDT 24
Peak memory 222376 kb
Host smart-2bbb47ff-1f2b-442f-84c5-62a84f2d293a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394050812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1394050812
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3258016993
Short name T43
Test name
Test status
Simulation time 243998761 ps
CPU time 1.04 seconds
Started Jun 21 05:13:06 PM PDT 24
Finished Jun 21 05:13:09 PM PDT 24
Peak memory 218076 kb
Host smart-9ad8173c-0d9a-49ee-a22f-8756a904e6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258016993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3258016993
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.468761729
Short name T25
Test name
Test status
Simulation time 160493885 ps
CPU time 0.88 seconds
Started Jun 21 05:13:11 PM PDT 24
Finished Jun 21 05:13:17 PM PDT 24
Peak memory 200608 kb
Host smart-2658f7b4-2844-447a-9f50-cd3c7dd99423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468761729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.468761729
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.3026051681
Short name T453
Test name
Test status
Simulation time 1244454144 ps
CPU time 5.8 seconds
Started Jun 21 05:13:08 PM PDT 24
Finished Jun 21 05:13:19 PM PDT 24
Peak memory 200876 kb
Host smart-1ea669f2-1851-414e-8ae7-657e194b3f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026051681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.3026051681
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2628754814
Short name T290
Test name
Test status
Simulation time 159655590 ps
CPU time 1.14 seconds
Started Jun 21 05:13:09 PM PDT 24
Finished Jun 21 05:13:15 PM PDT 24
Peak memory 200596 kb
Host smart-ee6e32d5-108f-4c94-9f98-0dd4eeecaa11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628754814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2628754814
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.1738360226
Short name T204
Test name
Test status
Simulation time 190625308 ps
CPU time 1.32 seconds
Started Jun 21 05:13:08 PM PDT 24
Finished Jun 21 05:13:14 PM PDT 24
Peak memory 200880 kb
Host smart-2546f1e0-4388-42cc-9a65-c80fac778a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738360226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1738360226
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2925763480
Short name T102
Test name
Test status
Simulation time 4487647466 ps
CPU time 20.07 seconds
Started Jun 21 05:13:11 PM PDT 24
Finished Jun 21 05:13:36 PM PDT 24
Peak memory 200912 kb
Host smart-8524ad6c-2bdc-4875-af8a-9f8848630ae2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925763480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2925763480
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1326520416
Short name T171
Test name
Test status
Simulation time 324618229 ps
CPU time 2.18 seconds
Started Jun 21 05:13:07 PM PDT 24
Finished Jun 21 05:13:11 PM PDT 24
Peak memory 200656 kb
Host smart-bb80cf16-b3db-4ab9-a937-28b8df76245a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326520416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1326520416
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3458867612
Short name T198
Test name
Test status
Simulation time 127321617 ps
CPU time 1.01 seconds
Started Jun 21 05:13:10 PM PDT 24
Finished Jun 21 05:13:16 PM PDT 24
Peak memory 200692 kb
Host smart-e39076c6-1198-4f3f-b209-6d9f95341e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458867612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3458867612
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1162059690
Short name T485
Test name
Test status
Simulation time 86023987 ps
CPU time 0.87 seconds
Started Jun 21 05:13:22 PM PDT 24
Finished Jun 21 05:13:29 PM PDT 24
Peak memory 200488 kb
Host smart-8a9a0515-3a13-4941-a382-6728b880234d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162059690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1162059690
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1033401086
Short name T212
Test name
Test status
Simulation time 244617041 ps
CPU time 1.01 seconds
Started Jun 21 05:13:21 PM PDT 24
Finished Jun 21 05:13:28 PM PDT 24
Peak memory 218080 kb
Host smart-b6c810e1-7386-448c-be40-8c835bfc4953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033401086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1033401086
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.1541727546
Short name T469
Test name
Test status
Simulation time 171532303 ps
CPU time 0.86 seconds
Started Jun 21 05:13:06 PM PDT 24
Finished Jun 21 05:13:09 PM PDT 24
Peak memory 200496 kb
Host smart-e6d67def-5932-4825-bdc5-fbdba1c3a7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541727546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.1541727546
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1097913744
Short name T462
Test name
Test status
Simulation time 1055455712 ps
CPU time 4.94 seconds
Started Jun 21 05:13:15 PM PDT 24
Finished Jun 21 05:13:24 PM PDT 24
Peak memory 200856 kb
Host smart-7d9c5ec8-0b01-405d-a2b1-c8215b42ac63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097913744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1097913744
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2593432902
Short name T13
Test name
Test status
Simulation time 110582147 ps
CPU time 1.04 seconds
Started Jun 21 05:13:18 PM PDT 24
Finished Jun 21 05:13:25 PM PDT 24
Peak memory 200672 kb
Host smart-bb7ab5da-4d4a-4004-9044-511f07f47a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593432902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2593432902
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.4162769965
Short name T519
Test name
Test status
Simulation time 260318520 ps
CPU time 1.55 seconds
Started Jun 21 05:13:08 PM PDT 24
Finished Jun 21 05:13:15 PM PDT 24
Peak memory 200832 kb
Host smart-5ec1c617-703f-48f5-bd0a-ac3c224dfbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162769965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.4162769965
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1221195127
Short name T154
Test name
Test status
Simulation time 220409950 ps
CPU time 1.21 seconds
Started Jun 21 05:13:20 PM PDT 24
Finished Jun 21 05:13:28 PM PDT 24
Peak memory 200580 kb
Host smart-2681ae15-30de-4093-b97e-db05f3c34ac3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221195127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1221195127
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1395451390
Short name T199
Test name
Test status
Simulation time 320033474 ps
CPU time 2.08 seconds
Started Jun 21 05:13:16 PM PDT 24
Finished Jun 21 05:13:21 PM PDT 24
Peak memory 200676 kb
Host smart-09ccea58-4cd5-46cc-bd8e-8378dc69a54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395451390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1395451390
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2816415575
Short name T491
Test name
Test status
Simulation time 135915063 ps
CPU time 1.15 seconds
Started Jun 21 05:13:17 PM PDT 24
Finished Jun 21 05:13:21 PM PDT 24
Peak memory 200684 kb
Host smart-b65eaaab-61d8-4f4d-8d03-65ee38565603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816415575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2816415575
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1613996102
Short name T385
Test name
Test status
Simulation time 89660386 ps
CPU time 0.8 seconds
Started Jun 21 05:13:17 PM PDT 24
Finished Jun 21 05:13:23 PM PDT 24
Peak memory 200476 kb
Host smart-bc80156d-6cb4-4d34-98b9-00f2a7b1ca60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613996102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1613996102
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.647767792
Short name T443
Test name
Test status
Simulation time 1880547240 ps
CPU time 7.28 seconds
Started Jun 21 05:13:18 PM PDT 24
Finished Jun 21 05:13:31 PM PDT 24
Peak memory 218460 kb
Host smart-8e8011a6-2af4-4746-ad2e-94f0cc70bd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647767792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.647767792
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.745064841
Short name T394
Test name
Test status
Simulation time 243698607 ps
CPU time 1.11 seconds
Started Jun 21 05:13:17 PM PDT 24
Finished Jun 21 05:13:22 PM PDT 24
Peak memory 218048 kb
Host smart-0b0a40f0-73ea-410b-85e7-df31813c27ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745064841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.745064841
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2105371946
Short name T311
Test name
Test status
Simulation time 90081839 ps
CPU time 0.74 seconds
Started Jun 21 05:13:20 PM PDT 24
Finished Jun 21 05:13:28 PM PDT 24
Peak memory 200408 kb
Host smart-66c34527-ba48-470b-a09e-6d3d7687e9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105371946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2105371946
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3857886841
Short name T392
Test name
Test status
Simulation time 1915374115 ps
CPU time 7.15 seconds
Started Jun 21 05:13:15 PM PDT 24
Finished Jun 21 05:13:26 PM PDT 24
Peak memory 200904 kb
Host smart-b678389d-4012-4210-982c-bf28f34932f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857886841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3857886841
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2912016350
Short name T291
Test name
Test status
Simulation time 98910549 ps
CPU time 1.02 seconds
Started Jun 21 05:13:20 PM PDT 24
Finished Jun 21 05:13:27 PM PDT 24
Peak memory 200600 kb
Host smart-cd587425-34aa-4675-aff2-646710013e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912016350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2912016350
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2427214235
Short name T161
Test name
Test status
Simulation time 200859039 ps
CPU time 1.35 seconds
Started Jun 21 05:13:20 PM PDT 24
Finished Jun 21 05:13:28 PM PDT 24
Peak memory 200852 kb
Host smart-3c404105-156a-46cb-82e8-a09f431299d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427214235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2427214235
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.148503983
Short name T285
Test name
Test status
Simulation time 2260840816 ps
CPU time 10.3 seconds
Started Jun 21 05:13:15 PM PDT 24
Finished Jun 21 05:13:29 PM PDT 24
Peak memory 200952 kb
Host smart-018d414a-acd1-4e54-9650-45d9d38d16df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148503983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.148503983
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1383871725
Short name T9
Test name
Test status
Simulation time 133118231 ps
CPU time 1.7 seconds
Started Jun 21 05:13:16 PM PDT 24
Finished Jun 21 05:13:21 PM PDT 24
Peak memory 208912 kb
Host smart-8b7bafc7-ea05-4fbf-a3d2-cd9bcd172f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383871725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1383871725
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1153112704
Short name T77
Test name
Test status
Simulation time 255408244 ps
CPU time 1.46 seconds
Started Jun 21 05:13:18 PM PDT 24
Finished Jun 21 05:13:25 PM PDT 24
Peak memory 200676 kb
Host smart-4966554a-519e-4891-a2cf-ff6f9a7ba02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153112704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1153112704
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3334166181
Short name T364
Test name
Test status
Simulation time 58696175 ps
CPU time 0.72 seconds
Started Jun 21 05:12:21 PM PDT 24
Finished Jun 21 05:12:23 PM PDT 24
Peak memory 200480 kb
Host smart-65702941-a5f1-4284-af69-aa2d1eae7cd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334166181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3334166181
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.805313528
Short name T442
Test name
Test status
Simulation time 1227585222 ps
CPU time 5.71 seconds
Started Jun 21 05:12:16 PM PDT 24
Finished Jun 21 05:12:24 PM PDT 24
Peak memory 230568 kb
Host smart-c0df4bb7-a181-4ef5-8e92-b13d06937039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805313528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.805313528
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1496414641
Short name T526
Test name
Test status
Simulation time 243946512 ps
CPU time 1.12 seconds
Started Jun 21 05:12:14 PM PDT 24
Finished Jun 21 05:12:17 PM PDT 24
Peak memory 218072 kb
Host smart-9c1de37d-2cb3-4439-823b-73ee395956b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496414641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1496414641
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3041654061
Short name T264
Test name
Test status
Simulation time 169484501 ps
CPU time 0.9 seconds
Started Jun 21 05:12:18 PM PDT 24
Finished Jun 21 05:12:20 PM PDT 24
Peak memory 200444 kb
Host smart-249de402-dab1-4e8c-a9d0-9fc60f95f991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041654061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3041654061
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1497713188
Short name T528
Test name
Test status
Simulation time 822662351 ps
CPU time 4.34 seconds
Started Jun 21 05:12:13 PM PDT 24
Finished Jun 21 05:12:19 PM PDT 24
Peak memory 200860 kb
Host smart-c0dffd78-3c99-47bb-ac14-29156809605a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497713188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1497713188
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3844683563
Short name T225
Test name
Test status
Simulation time 108949091 ps
CPU time 1.04 seconds
Started Jun 21 05:12:16 PM PDT 24
Finished Jun 21 05:12:19 PM PDT 24
Peak memory 200684 kb
Host smart-edfd8405-f41a-4d8e-a5f2-fa3c023a4927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844683563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3844683563
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.3328178090
Short name T407
Test name
Test status
Simulation time 115022230 ps
CPU time 1.16 seconds
Started Jun 21 05:12:16 PM PDT 24
Finished Jun 21 05:12:19 PM PDT 24
Peak memory 200880 kb
Host smart-a85180ab-765c-4795-b526-0d87b541f70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328178090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3328178090
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.2076198437
Short name T46
Test name
Test status
Simulation time 5676157089 ps
CPU time 20.26 seconds
Started Jun 21 05:12:16 PM PDT 24
Finished Jun 21 05:12:39 PM PDT 24
Peak memory 210868 kb
Host smart-45e5b7ae-d407-4e10-a989-fa069288b28f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076198437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2076198437
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2439030223
Short name T524
Test name
Test status
Simulation time 344109215 ps
CPU time 2.27 seconds
Started Jun 21 05:12:18 PM PDT 24
Finished Jun 21 05:12:21 PM PDT 24
Peak memory 208880 kb
Host smart-65a6e17d-78fd-46e0-b322-db18f39a887c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439030223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2439030223
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.330916761
Short name T501
Test name
Test status
Simulation time 237940879 ps
CPU time 1.51 seconds
Started Jun 21 05:12:13 PM PDT 24
Finished Jun 21 05:12:17 PM PDT 24
Peak memory 201020 kb
Host smart-42bec3c5-5d1e-4b7c-8a96-183a1d6be75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330916761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.330916761
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1370831283
Short name T48
Test name
Test status
Simulation time 65998754 ps
CPU time 0.75 seconds
Started Jun 21 05:13:17 PM PDT 24
Finished Jun 21 05:13:22 PM PDT 24
Peak memory 200472 kb
Host smart-9feb74ff-0bce-4e9b-94a6-7b61c8a21368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370831283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1370831283
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1648859444
Short name T321
Test name
Test status
Simulation time 1224459694 ps
CPU time 5.47 seconds
Started Jun 21 05:13:21 PM PDT 24
Finished Jun 21 05:13:33 PM PDT 24
Peak memory 230636 kb
Host smart-0f19b283-9737-42f0-934f-960b6295afc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648859444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1648859444
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3771407053
Short name T521
Test name
Test status
Simulation time 243908541 ps
CPU time 1.09 seconds
Started Jun 21 05:13:18 PM PDT 24
Finished Jun 21 05:13:24 PM PDT 24
Peak memory 218004 kb
Host smart-02b441c2-cbed-4993-91ed-e915097b196b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771407053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3771407053
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3237771145
Short name T21
Test name
Test status
Simulation time 110611781 ps
CPU time 0.79 seconds
Started Jun 21 05:13:17 PM PDT 24
Finished Jun 21 05:13:21 PM PDT 24
Peak memory 200512 kb
Host smart-96dde8c9-0f03-4f37-b58e-d66c58e6d15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237771145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3237771145
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2209071418
Short name T237
Test name
Test status
Simulation time 762040143 ps
CPU time 3.76 seconds
Started Jun 21 05:13:17 PM PDT 24
Finished Jun 21 05:13:24 PM PDT 24
Peak memory 200868 kb
Host smart-fd2b03f9-8c64-46a2-980f-a63cdbdd1ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209071418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2209071418
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.451609221
Short name T76
Test name
Test status
Simulation time 181074203 ps
CPU time 1.17 seconds
Started Jun 21 05:13:22 PM PDT 24
Finished Jun 21 05:13:29 PM PDT 24
Peak memory 200600 kb
Host smart-8fccc352-453d-4e02-8e6b-85ed890bc6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451609221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.451609221
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2839214026
Short name T234
Test name
Test status
Simulation time 249623385 ps
CPU time 1.46 seconds
Started Jun 21 05:13:15 PM PDT 24
Finished Jun 21 05:13:20 PM PDT 24
Peak memory 200876 kb
Host smart-e54e81cc-e50c-4f57-8ef1-754a7ec16e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839214026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2839214026
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.99157701
Short name T426
Test name
Test status
Simulation time 3808438236 ps
CPU time 13.19 seconds
Started Jun 21 05:13:17 PM PDT 24
Finished Jun 21 05:13:34 PM PDT 24
Peak memory 209096 kb
Host smart-037b7dee-4606-43c0-8232-3fd21f8ef458
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99157701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.99157701
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.2225477444
Short name T525
Test name
Test status
Simulation time 260572849 ps
CPU time 1.84 seconds
Started Jun 21 05:13:19 PM PDT 24
Finished Jun 21 05:13:27 PM PDT 24
Peak memory 200324 kb
Host smart-d773b9f7-dd84-452a-85d6-14ac8fa597a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225477444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2225477444
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.4149194885
Short name T457
Test name
Test status
Simulation time 91743125 ps
CPU time 0.93 seconds
Started Jun 21 05:13:18 PM PDT 24
Finished Jun 21 05:13:25 PM PDT 24
Peak memory 200700 kb
Host smart-7794116d-5d51-45df-acbd-c32769590048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149194885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.4149194885
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.3445475521
Short name T142
Test name
Test status
Simulation time 66405404 ps
CPU time 0.78 seconds
Started Jun 21 05:13:15 PM PDT 24
Finished Jun 21 05:13:20 PM PDT 24
Peak memory 200492 kb
Host smart-d707022a-9cc4-46d7-b31f-53a32f8d81a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445475521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3445475521
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1907499801
Short name T335
Test name
Test status
Simulation time 1224539816 ps
CPU time 5.48 seconds
Started Jun 21 05:13:21 PM PDT 24
Finished Jun 21 05:13:33 PM PDT 24
Peak memory 217420 kb
Host smart-89cb1291-512a-4500-a707-e19ef1200549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907499801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1907499801
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1722301341
Short name T302
Test name
Test status
Simulation time 244156948 ps
CPU time 1.2 seconds
Started Jun 21 05:13:15 PM PDT 24
Finished Jun 21 05:13:20 PM PDT 24
Peak memory 218052 kb
Host smart-10d24ed8-303b-4285-a793-1214d47232a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722301341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1722301341
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.104261673
Short name T24
Test name
Test status
Simulation time 243903611 ps
CPU time 0.91 seconds
Started Jun 21 05:13:21 PM PDT 24
Finished Jun 21 05:13:28 PM PDT 24
Peak memory 200492 kb
Host smart-ecb8a198-e0f3-456b-aeed-5c914ea9551d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104261673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.104261673
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.956522077
Short name T239
Test name
Test status
Simulation time 1056159960 ps
CPU time 5 seconds
Started Jun 21 05:13:17 PM PDT 24
Finished Jun 21 05:13:26 PM PDT 24
Peak memory 200804 kb
Host smart-49646d07-4b36-477e-ba79-63a4e21ab6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956522077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.956522077
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.498888063
Short name T148
Test name
Test status
Simulation time 165402102 ps
CPU time 1.16 seconds
Started Jun 21 05:13:21 PM PDT 24
Finished Jun 21 05:13:29 PM PDT 24
Peak memory 200676 kb
Host smart-2ac34456-439a-4345-9d73-23742231e3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498888063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.498888063
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.513691494
Short name T425
Test name
Test status
Simulation time 229106758 ps
CPU time 1.5 seconds
Started Jun 21 05:13:17 PM PDT 24
Finished Jun 21 05:13:23 PM PDT 24
Peak memory 200888 kb
Host smart-041de548-67d1-4008-97aa-3459631eeae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513691494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.513691494
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2068550357
Short name T359
Test name
Test status
Simulation time 3255385768 ps
CPU time 12.29 seconds
Started Jun 21 05:13:15 PM PDT 24
Finished Jun 21 05:13:31 PM PDT 24
Peak memory 200892 kb
Host smart-055aebb3-7da2-4cb4-9190-fc9ea7247a7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068550357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2068550357
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3441006019
Short name T449
Test name
Test status
Simulation time 446956990 ps
CPU time 2.43 seconds
Started Jun 21 05:13:21 PM PDT 24
Finished Jun 21 05:13:30 PM PDT 24
Peak memory 200620 kb
Host smart-a266cf4c-e926-4499-9e32-ced02d9a8d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441006019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3441006019
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3988620164
Short name T353
Test name
Test status
Simulation time 209483764 ps
CPU time 1.35 seconds
Started Jun 21 05:13:17 PM PDT 24
Finished Jun 21 05:13:23 PM PDT 24
Peak memory 200676 kb
Host smart-285784b7-251f-4c83-81a8-502d2c773fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988620164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3988620164
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1022404850
Short name T542
Test name
Test status
Simulation time 72910679 ps
CPU time 0.77 seconds
Started Jun 21 05:13:17 PM PDT 24
Finished Jun 21 05:13:23 PM PDT 24
Peak memory 200484 kb
Host smart-7c512c0e-43cc-4401-817e-1b0b76c8587f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022404850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1022404850
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.407721125
Short name T389
Test name
Test status
Simulation time 1900665847 ps
CPU time 6.98 seconds
Started Jun 21 05:13:22 PM PDT 24
Finished Jun 21 05:13:35 PM PDT 24
Peak memory 222388 kb
Host smart-9ca47d66-357a-401d-9ed7-5c95d5bff4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407721125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.407721125
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2945348823
Short name T168
Test name
Test status
Simulation time 244125318 ps
CPU time 1.13 seconds
Started Jun 21 05:13:16 PM PDT 24
Finished Jun 21 05:13:21 PM PDT 24
Peak memory 218000 kb
Host smart-52c3f5e8-80e0-4af2-9726-d44c77d0c5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945348823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.2945348823
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.132696847
Short name T18
Test name
Test status
Simulation time 88576059 ps
CPU time 0.76 seconds
Started Jun 21 05:13:21 PM PDT 24
Finished Jun 21 05:13:28 PM PDT 24
Peak memory 200472 kb
Host smart-7046ce73-e521-4e7b-af17-1493907de0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132696847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.132696847
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1868006831
Short name T487
Test name
Test status
Simulation time 686075141 ps
CPU time 3.64 seconds
Started Jun 21 05:13:19 PM PDT 24
Finished Jun 21 05:13:28 PM PDT 24
Peak memory 200548 kb
Host smart-9eb9a504-3e3e-44e7-bc33-716c39e7126e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868006831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1868006831
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2896972755
Short name T535
Test name
Test status
Simulation time 98108420 ps
CPU time 0.97 seconds
Started Jun 21 05:13:21 PM PDT 24
Finished Jun 21 05:13:29 PM PDT 24
Peak memory 200668 kb
Host smart-4eb1a55c-2be1-486a-97c8-9e1ff37caced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896972755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2896972755
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.3354513594
Short name T495
Test name
Test status
Simulation time 120988558 ps
CPU time 1.18 seconds
Started Jun 21 05:13:22 PM PDT 24
Finished Jun 21 05:13:29 PM PDT 24
Peak memory 200772 kb
Host smart-a424c4e5-4f3e-4310-9c6f-648a959f2a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354513594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.3354513594
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.415319706
Short name T360
Test name
Test status
Simulation time 7203304344 ps
CPU time 24.2 seconds
Started Jun 21 05:13:23 PM PDT 24
Finished Jun 21 05:13:54 PM PDT 24
Peak memory 209120 kb
Host smart-979d1160-a409-4271-8196-8e019d3e8780
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415319706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.415319706
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.2664923551
Short name T254
Test name
Test status
Simulation time 122033731 ps
CPU time 1.57 seconds
Started Jun 21 05:13:17 PM PDT 24
Finished Jun 21 05:13:23 PM PDT 24
Peak memory 208904 kb
Host smart-f48e4c07-6e3b-47c6-942b-b3a7db1196ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664923551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.2664923551
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2842402684
Short name T135
Test name
Test status
Simulation time 178903310 ps
CPU time 1.15 seconds
Started Jun 21 05:13:16 PM PDT 24
Finished Jun 21 05:13:21 PM PDT 24
Peak memory 200636 kb
Host smart-fc2c7630-07eb-4d68-9b00-f191d8e9f1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842402684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2842402684
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2084931418
Short name T160
Test name
Test status
Simulation time 73980465 ps
CPU time 0.84 seconds
Started Jun 21 05:13:15 PM PDT 24
Finished Jun 21 05:13:19 PM PDT 24
Peak memory 200488 kb
Host smart-f1ac33df-6afc-4323-86e9-52fa9ae7aca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084931418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2084931418
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.780934104
Short name T500
Test name
Test status
Simulation time 2363883544 ps
CPU time 7.96 seconds
Started Jun 21 05:13:22 PM PDT 24
Finished Jun 21 05:13:36 PM PDT 24
Peak memory 217836 kb
Host smart-2bc22ee9-e0a2-41bd-a195-bb5a45f16c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780934104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.780934104
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2088956330
Short name T293
Test name
Test status
Simulation time 246023997 ps
CPU time 0.99 seconds
Started Jun 21 05:13:14 PM PDT 24
Finished Jun 21 05:13:19 PM PDT 24
Peak memory 218040 kb
Host smart-25f1c509-3080-40b3-aeb8-f168bbbe1c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088956330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2088956330
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1504816295
Short name T235
Test name
Test status
Simulation time 165865250 ps
CPU time 0.86 seconds
Started Jun 21 05:13:17 PM PDT 24
Finished Jun 21 05:13:23 PM PDT 24
Peak memory 200500 kb
Host smart-3a03e762-a30f-4e77-80d6-62ca09834748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504816295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1504816295
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1036365158
Short name T387
Test name
Test status
Simulation time 2015503444 ps
CPU time 7.11 seconds
Started Jun 21 05:13:21 PM PDT 24
Finished Jun 21 05:13:35 PM PDT 24
Peak memory 200872 kb
Host smart-5153635f-7ac0-4297-a5df-01ea5ca143cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036365158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1036365158
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1666063785
Short name T172
Test name
Test status
Simulation time 174406975 ps
CPU time 1.2 seconds
Started Jun 21 05:13:18 PM PDT 24
Finished Jun 21 05:13:25 PM PDT 24
Peak memory 200048 kb
Host smart-588f2988-172e-4c61-95b7-22b3108ee398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666063785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1666063785
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3644010376
Short name T482
Test name
Test status
Simulation time 109411093 ps
CPU time 1.22 seconds
Started Jun 21 05:13:18 PM PDT 24
Finished Jun 21 05:13:25 PM PDT 24
Peak memory 200304 kb
Host smart-432cb977-40be-49ce-b466-f3ff6ed74078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644010376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3644010376
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.781727478
Short name T463
Test name
Test status
Simulation time 9510688770 ps
CPU time 37.03 seconds
Started Jun 21 05:13:20 PM PDT 24
Finished Jun 21 05:14:03 PM PDT 24
Peak memory 200888 kb
Host smart-c88c7d09-fb1c-44a0-ac94-42073b8a57c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781727478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.781727478
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.30832018
Short name T283
Test name
Test status
Simulation time 402165122 ps
CPU time 2.3 seconds
Started Jun 21 05:13:16 PM PDT 24
Finished Jun 21 05:13:22 PM PDT 24
Peak memory 200632 kb
Host smart-21801f4c-5128-4ced-b629-12859127e3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30832018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.30832018
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.1653436208
Short name T6
Test name
Test status
Simulation time 217572649 ps
CPU time 1.33 seconds
Started Jun 21 05:13:18 PM PDT 24
Finished Jun 21 05:13:25 PM PDT 24
Peak memory 200680 kb
Host smart-84f0bacc-b5bc-4415-a4b4-2dac89dc3f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653436208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1653436208
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3451269871
Short name T279
Test name
Test status
Simulation time 81790675 ps
CPU time 0.75 seconds
Started Jun 21 05:13:22 PM PDT 24
Finished Jun 21 05:13:29 PM PDT 24
Peak memory 200488 kb
Host smart-cb19da7b-54e8-417b-9270-1b3c99e140f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451269871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3451269871
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3502804001
Short name T38
Test name
Test status
Simulation time 2355503368 ps
CPU time 8.31 seconds
Started Jun 21 05:13:24 PM PDT 24
Finished Jun 21 05:13:38 PM PDT 24
Peak memory 218364 kb
Host smart-119415a6-e45b-45d2-8501-b767b9a5db07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502804001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3502804001
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3063604669
Short name T434
Test name
Test status
Simulation time 243237498 ps
CPU time 1.22 seconds
Started Jun 21 05:13:24 PM PDT 24
Finished Jun 21 05:13:31 PM PDT 24
Peak memory 218060 kb
Host smart-a3ac9bc9-e8ac-4e36-8aef-7bd0429ff948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063604669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3063604669
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2116211822
Short name T428
Test name
Test status
Simulation time 99202932 ps
CPU time 0.83 seconds
Started Jun 21 05:13:21 PM PDT 24
Finished Jun 21 05:13:29 PM PDT 24
Peak memory 200500 kb
Host smart-b72661e3-bb0b-47ef-ac2b-ec0bba2fec3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116211822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2116211822
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2385075957
Short name T106
Test name
Test status
Simulation time 2169091658 ps
CPU time 7.5 seconds
Started Jun 21 05:13:15 PM PDT 24
Finished Jun 21 05:13:26 PM PDT 24
Peak memory 200912 kb
Host smart-f345dbe5-4f8b-4dc1-aece-caea697aab5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385075957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2385075957
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1306097061
Short name T351
Test name
Test status
Simulation time 96362976 ps
CPU time 1.06 seconds
Started Jun 21 05:13:17 PM PDT 24
Finished Jun 21 05:13:23 PM PDT 24
Peak memory 200668 kb
Host smart-b4c44d61-c917-41b0-8b0f-bb37374fd09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306097061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1306097061
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.817955890
Short name T306
Test name
Test status
Simulation time 193121426 ps
CPU time 1.39 seconds
Started Jun 21 05:13:16 PM PDT 24
Finished Jun 21 05:13:21 PM PDT 24
Peak memory 200832 kb
Host smart-e70a596f-60bb-4322-8961-562eb66d316a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817955890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.817955890
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.910413455
Short name T477
Test name
Test status
Simulation time 6045918791 ps
CPU time 29.13 seconds
Started Jun 21 05:13:23 PM PDT 24
Finished Jun 21 05:13:59 PM PDT 24
Peak memory 200916 kb
Host smart-b73850eb-087b-4ba4-87af-48c6c2b74dde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910413455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.910413455
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.2315691135
Short name T72
Test name
Test status
Simulation time 131366917 ps
CPU time 1.54 seconds
Started Jun 21 05:13:16 PM PDT 24
Finished Jun 21 05:13:21 PM PDT 24
Peak memory 200712 kb
Host smart-731099de-2593-499d-95f9-e5323e668af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315691135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.2315691135
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.4231197991
Short name T141
Test name
Test status
Simulation time 167824219 ps
CPU time 1.31 seconds
Started Jun 21 05:13:17 PM PDT 24
Finished Jun 21 05:13:23 PM PDT 24
Peak memory 200876 kb
Host smart-c924510d-768b-4ab7-9200-da64473eacaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231197991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.4231197991
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3019126019
Short name T216
Test name
Test status
Simulation time 87021771 ps
CPU time 0.85 seconds
Started Jun 21 05:13:25 PM PDT 24
Finished Jun 21 05:13:32 PM PDT 24
Peak memory 200436 kb
Host smart-99dfc0b0-4331-4274-b2d1-de0844cd5c50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019126019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3019126019
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.4207834515
Short name T316
Test name
Test status
Simulation time 1226780786 ps
CPU time 5.75 seconds
Started Jun 21 05:13:23 PM PDT 24
Finished Jun 21 05:13:35 PM PDT 24
Peak memory 218432 kb
Host smart-cfe2ece4-bb0f-40b1-be6b-ccea65c24d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207834515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.4207834515
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.553599824
Short name T338
Test name
Test status
Simulation time 244832101 ps
CPU time 1.02 seconds
Started Jun 21 05:13:25 PM PDT 24
Finished Jun 21 05:13:32 PM PDT 24
Peak memory 218068 kb
Host smart-54de85c1-81e3-4de5-9bec-12b060ad34ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553599824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.553599824
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2417609337
Short name T337
Test name
Test status
Simulation time 148791059 ps
CPU time 0.82 seconds
Started Jun 21 05:13:23 PM PDT 24
Finished Jun 21 05:13:31 PM PDT 24
Peak memory 200500 kb
Host smart-12164954-d90f-484d-b3a5-19f3efe32867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417609337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2417609337
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3600824125
Short name T217
Test name
Test status
Simulation time 1489043199 ps
CPU time 6.04 seconds
Started Jun 21 05:13:23 PM PDT 24
Finished Jun 21 05:13:36 PM PDT 24
Peak memory 200880 kb
Host smart-2ca484ff-d222-47ea-bd46-340d9423ef54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600824125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3600824125
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2335058799
Short name T479
Test name
Test status
Simulation time 95582234 ps
CPU time 1 seconds
Started Jun 21 05:13:23 PM PDT 24
Finished Jun 21 05:13:31 PM PDT 24
Peak memory 200660 kb
Host smart-25c3ce59-d914-4731-b10c-76b28a851091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335058799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2335058799
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1326016812
Short name T489
Test name
Test status
Simulation time 253442391 ps
CPU time 1.55 seconds
Started Jun 21 05:13:23 PM PDT 24
Finished Jun 21 05:13:31 PM PDT 24
Peak memory 200884 kb
Host smart-10be24ea-3333-4c3d-98a2-1e2c10730e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326016812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1326016812
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1558746492
Short name T98
Test name
Test status
Simulation time 5017824533 ps
CPU time 17.06 seconds
Started Jun 21 05:13:24 PM PDT 24
Finished Jun 21 05:13:47 PM PDT 24
Peak memory 200956 kb
Host smart-818c8e61-c968-4dc6-b3b0-f4fe1803d5af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558746492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1558746492
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.982172439
Short name T444
Test name
Test status
Simulation time 127236392 ps
CPU time 1.54 seconds
Started Jun 21 05:13:25 PM PDT 24
Finished Jun 21 05:13:33 PM PDT 24
Peak memory 200832 kb
Host smart-9d94dbc6-d689-479d-a52c-01dcc762e2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982172439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.982172439
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2717278575
Short name T465
Test name
Test status
Simulation time 138538966 ps
CPU time 1.15 seconds
Started Jun 21 05:13:24 PM PDT 24
Finished Jun 21 05:13:31 PM PDT 24
Peak memory 200684 kb
Host smart-d7f17403-57d4-4b5d-a3f9-04d750213a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717278575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2717278575
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1442614017
Short name T497
Test name
Test status
Simulation time 96833084 ps
CPU time 0.89 seconds
Started Jun 21 05:13:25 PM PDT 24
Finished Jun 21 05:13:32 PM PDT 24
Peak memory 200284 kb
Host smart-cf192b3f-2325-4db6-b3ae-61a82dc77022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442614017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1442614017
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.467441678
Short name T294
Test name
Test status
Simulation time 1903469699 ps
CPU time 7.4 seconds
Started Jun 21 05:13:24 PM PDT 24
Finished Jun 21 05:13:37 PM PDT 24
Peak memory 218456 kb
Host smart-755c44bb-7517-4f5a-ab1c-adda1c777e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467441678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.467441678
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.730590682
Short name T253
Test name
Test status
Simulation time 244321531 ps
CPU time 1.08 seconds
Started Jun 21 05:13:23 PM PDT 24
Finished Jun 21 05:13:31 PM PDT 24
Peak memory 218060 kb
Host smart-d3fff749-851d-4b6e-a522-7a167a176eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730590682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.730590682
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3517910337
Short name T363
Test name
Test status
Simulation time 204873371 ps
CPU time 0.88 seconds
Started Jun 21 05:13:22 PM PDT 24
Finished Jun 21 05:13:29 PM PDT 24
Peak memory 200508 kb
Host smart-3097b2a0-9d5e-4f80-8641-726c29b8ebc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517910337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3517910337
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3623529436
Short name T405
Test name
Test status
Simulation time 1512374751 ps
CPU time 6.19 seconds
Started Jun 21 05:13:23 PM PDT 24
Finished Jun 21 05:13:36 PM PDT 24
Peak memory 200940 kb
Host smart-013564bf-f246-48fc-86c4-110540c1596d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623529436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3623529436
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2714529627
Short name T222
Test name
Test status
Simulation time 173898701 ps
CPU time 1.12 seconds
Started Jun 21 05:13:24 PM PDT 24
Finished Jun 21 05:13:31 PM PDT 24
Peak memory 200648 kb
Host smart-87366c21-20b0-48d2-9674-57775062867f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714529627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2714529627
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.612890604
Short name T137
Test name
Test status
Simulation time 229484245 ps
CPU time 1.53 seconds
Started Jun 21 05:13:23 PM PDT 24
Finished Jun 21 05:13:32 PM PDT 24
Peak memory 200900 kb
Host smart-bbd65b5b-1a78-4628-989d-74c7ff3176ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612890604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.612890604
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1522212614
Short name T356
Test name
Test status
Simulation time 3513899828 ps
CPU time 14.85 seconds
Started Jun 21 05:13:25 PM PDT 24
Finished Jun 21 05:13:45 PM PDT 24
Peak memory 200960 kb
Host smart-2d59f30a-33db-408f-9dcf-b075866383e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522212614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1522212614
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3724088142
Short name T33
Test name
Test status
Simulation time 366904760 ps
CPU time 2.1 seconds
Started Jun 21 05:13:23 PM PDT 24
Finished Jun 21 05:13:32 PM PDT 24
Peak memory 200680 kb
Host smart-b6af40e5-e823-4ad4-b968-9127551aaaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724088142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3724088142
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3656758673
Short name T180
Test name
Test status
Simulation time 79988334 ps
CPU time 0.78 seconds
Started Jun 21 05:13:23 PM PDT 24
Finished Jun 21 05:13:31 PM PDT 24
Peak memory 200700 kb
Host smart-ddfb201e-78e7-493f-8594-3b3371c2b731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656758673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3656758673
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.939326330
Short name T415
Test name
Test status
Simulation time 58441148 ps
CPU time 0.77 seconds
Started Jun 21 05:13:25 PM PDT 24
Finished Jun 21 05:13:32 PM PDT 24
Peak memory 200200 kb
Host smart-1e76b056-8b8f-4df4-95c8-514e518c2b8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939326330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.939326330
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2834047640
Short name T288
Test name
Test status
Simulation time 1901997716 ps
CPU time 6.85 seconds
Started Jun 21 05:13:22 PM PDT 24
Finished Jun 21 05:13:35 PM PDT 24
Peak memory 217964 kb
Host smart-fa8cd4a6-7891-48c7-8126-4ac6a52e3651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834047640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2834047640
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1529085560
Short name T189
Test name
Test status
Simulation time 243746905 ps
CPU time 1.11 seconds
Started Jun 21 05:13:23 PM PDT 24
Finished Jun 21 05:13:31 PM PDT 24
Peak memory 218060 kb
Host smart-7b164d25-552e-4e17-ba8c-53ee487326fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529085560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1529085560
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2306211438
Short name T505
Test name
Test status
Simulation time 178358744 ps
CPU time 0.89 seconds
Started Jun 21 05:13:23 PM PDT 24
Finished Jun 21 05:13:31 PM PDT 24
Peak memory 200496 kb
Host smart-3235172a-8f54-4dda-8cc9-ca99717df525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306211438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2306211438
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1927599112
Short name T350
Test name
Test status
Simulation time 1592169291 ps
CPU time 5.94 seconds
Started Jun 21 05:13:24 PM PDT 24
Finished Jun 21 05:13:36 PM PDT 24
Peak memory 200892 kb
Host smart-3b0e338f-0ead-44d6-948a-0df6f1c3ca13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927599112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1927599112
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.4080044988
Short name T147
Test name
Test status
Simulation time 114027639 ps
CPU time 1.01 seconds
Started Jun 21 05:13:24 PM PDT 24
Finished Jun 21 05:13:31 PM PDT 24
Peak memory 200620 kb
Host smart-92a01a75-cc6a-4f5b-b2f5-6e997af4601c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080044988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.4080044988
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1640987750
Short name T540
Test name
Test status
Simulation time 123106164 ps
CPU time 1.15 seconds
Started Jun 21 05:13:23 PM PDT 24
Finished Jun 21 05:13:31 PM PDT 24
Peak memory 200880 kb
Host smart-11e81ea0-f493-4f00-8daa-a9dd76629ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640987750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1640987750
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.1122846836
Short name T93
Test name
Test status
Simulation time 3333388321 ps
CPU time 11.42 seconds
Started Jun 21 05:13:23 PM PDT 24
Finished Jun 21 05:13:41 PM PDT 24
Peak memory 209120 kb
Host smart-bc131e91-302e-44b5-a1d9-e3b352494a41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122846836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1122846836
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2483142528
Short name T320
Test name
Test status
Simulation time 124072601 ps
CPU time 1.68 seconds
Started Jun 21 05:13:23 PM PDT 24
Finished Jun 21 05:13:32 PM PDT 24
Peak memory 208932 kb
Host smart-401609ea-4663-4045-96c9-b1e6330ec98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483142528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2483142528
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1922015452
Short name T413
Test name
Test status
Simulation time 88117779 ps
CPU time 0.93 seconds
Started Jun 21 05:13:27 PM PDT 24
Finished Jun 21 05:13:33 PM PDT 24
Peak memory 200800 kb
Host smart-90fe357d-76a9-405f-9579-352b401f80a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922015452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1922015452
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.238446349
Short name T396
Test name
Test status
Simulation time 67815750 ps
CPU time 0.81 seconds
Started Jun 21 05:13:29 PM PDT 24
Finished Jun 21 05:13:34 PM PDT 24
Peak memory 200464 kb
Host smart-f1651cb1-50ab-438b-b7f3-e65697a3deed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238446349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.238446349
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.524541774
Short name T367
Test name
Test status
Simulation time 2355334398 ps
CPU time 7.9 seconds
Started Jun 21 05:13:27 PM PDT 24
Finished Jun 21 05:13:40 PM PDT 24
Peak memory 218596 kb
Host smart-2fe3f7a6-b954-4abe-9855-47e2523b9fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524541774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.524541774
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.3385902924
Short name T433
Test name
Test status
Simulation time 244366987 ps
CPU time 1.06 seconds
Started Jun 21 05:13:24 PM PDT 24
Finished Jun 21 05:13:31 PM PDT 24
Peak memory 218100 kb
Host smart-51304d11-cdfd-4427-a3bf-40c23341503d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385902924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.3385902924
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2156542538
Short name T379
Test name
Test status
Simulation time 167374125 ps
CPU time 0.83 seconds
Started Jun 21 05:13:22 PM PDT 24
Finished Jun 21 05:13:29 PM PDT 24
Peak memory 200488 kb
Host smart-bc05d676-0c5c-4382-937f-3536db0878a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156542538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2156542538
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2728060070
Short name T354
Test name
Test status
Simulation time 110452447 ps
CPU time 1.06 seconds
Started Jun 21 05:13:24 PM PDT 24
Finished Jun 21 05:13:31 PM PDT 24
Peak memory 200656 kb
Host smart-7de6d0e2-4a04-4b48-a747-001b854de6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728060070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2728060070
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.4047450155
Short name T303
Test name
Test status
Simulation time 120275390 ps
CPU time 1.24 seconds
Started Jun 21 05:13:23 PM PDT 24
Finished Jun 21 05:13:31 PM PDT 24
Peak memory 200888 kb
Host smart-a735e922-cd25-4659-a8f5-6eb47f7a9ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047450155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.4047450155
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1365947830
Short name T245
Test name
Test status
Simulation time 10460027017 ps
CPU time 35.3 seconds
Started Jun 21 05:13:33 PM PDT 24
Finished Jun 21 05:14:13 PM PDT 24
Peak memory 200920 kb
Host smart-a01a558d-614b-41fa-ad6c-188e5063285c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365947830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1365947830
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1569591653
Short name T229
Test name
Test status
Simulation time 490118956 ps
CPU time 2.94 seconds
Started Jun 21 05:13:23 PM PDT 24
Finished Jun 21 05:13:32 PM PDT 24
Peak memory 200668 kb
Host smart-d9fc655e-9d74-41d5-8ce1-46cd5d17cd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569591653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1569591653
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.62185804
Short name T195
Test name
Test status
Simulation time 155151956 ps
CPU time 1.14 seconds
Started Jun 21 05:13:22 PM PDT 24
Finished Jun 21 05:13:30 PM PDT 24
Peak memory 200808 kb
Host smart-0df15114-d15a-488f-bdba-eef840970d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62185804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.62185804
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.2041204780
Short name T159
Test name
Test status
Simulation time 62526710 ps
CPU time 0.72 seconds
Started Jun 21 05:13:30 PM PDT 24
Finished Jun 21 05:13:35 PM PDT 24
Peak memory 200488 kb
Host smart-11d1ae36-53ba-4595-a549-ded08cd1a08f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041204780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2041204780
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1091021717
Short name T54
Test name
Test status
Simulation time 1903915057 ps
CPU time 7.07 seconds
Started Jun 21 05:13:32 PM PDT 24
Finished Jun 21 05:13:43 PM PDT 24
Peak memory 217480 kb
Host smart-9f678ce1-09a8-4d97-8982-1b21df31135c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091021717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1091021717
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1612258841
Short name T47
Test name
Test status
Simulation time 244617762 ps
CPU time 1.13 seconds
Started Jun 21 05:13:32 PM PDT 24
Finished Jun 21 05:13:37 PM PDT 24
Peak memory 218036 kb
Host smart-a0aa6c45-0a08-48d1-8dc1-5ce272a36cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612258841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1612258841
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2535040012
Short name T220
Test name
Test status
Simulation time 115616076 ps
CPU time 0.87 seconds
Started Jun 21 05:13:31 PM PDT 24
Finished Jun 21 05:13:35 PM PDT 24
Peak memory 200504 kb
Host smart-99b74635-40e2-4893-b09b-86e65c0db8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535040012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2535040012
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2610862957
Short name T310
Test name
Test status
Simulation time 872002953 ps
CPU time 4.44 seconds
Started Jun 21 05:13:36 PM PDT 24
Finished Jun 21 05:13:44 PM PDT 24
Peak memory 200916 kb
Host smart-f562e1c4-e56f-4edb-9c59-5894a31f6834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610862957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2610862957
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.4265196503
Short name T267
Test name
Test status
Simulation time 107817735 ps
CPU time 1.03 seconds
Started Jun 21 05:13:31 PM PDT 24
Finished Jun 21 05:13:36 PM PDT 24
Peak memory 200672 kb
Host smart-b4d73594-5fe4-4ff2-80d8-a424afba5593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265196503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.4265196503
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.383060556
Short name T277
Test name
Test status
Simulation time 123498199 ps
CPU time 1.23 seconds
Started Jun 21 05:13:35 PM PDT 24
Finished Jun 21 05:13:40 PM PDT 24
Peak memory 200884 kb
Host smart-18188898-2a73-421d-a717-7a7847171078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383060556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.383060556
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2691950533
Short name T243
Test name
Test status
Simulation time 997452191 ps
CPU time 5.14 seconds
Started Jun 21 05:13:33 PM PDT 24
Finished Jun 21 05:13:43 PM PDT 24
Peak memory 200864 kb
Host smart-eddaf8c8-e12a-4d7c-ad7d-0d3370a7e7a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691950533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2691950533
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2619334066
Short name T454
Test name
Test status
Simulation time 123037334 ps
CPU time 1.49 seconds
Started Jun 21 05:13:34 PM PDT 24
Finished Jun 21 05:13:40 PM PDT 24
Peak memory 200656 kb
Host smart-18894468-9197-4d68-8ac4-125a132bde66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619334066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2619334066
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3521167139
Short name T473
Test name
Test status
Simulation time 141939210 ps
CPU time 1.04 seconds
Started Jun 21 05:13:30 PM PDT 24
Finished Jun 21 05:13:35 PM PDT 24
Peak memory 200632 kb
Host smart-0610e673-575a-4b27-b178-c6cc0f04bce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521167139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3521167139
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.673312055
Short name T145
Test name
Test status
Simulation time 73828753 ps
CPU time 0.77 seconds
Started Jun 21 05:12:14 PM PDT 24
Finished Jun 21 05:12:16 PM PDT 24
Peak memory 200476 kb
Host smart-0e97961e-7662-4b88-b7c8-d1f25b4ab9eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673312055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.673312055
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1503831631
Short name T41
Test name
Test status
Simulation time 1215462995 ps
CPU time 5.54 seconds
Started Jun 21 05:12:16 PM PDT 24
Finished Jun 21 05:12:23 PM PDT 24
Peak memory 218392 kb
Host smart-9629967d-5791-45b6-8cd3-376a8b9a957b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503831631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1503831631
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3746744739
Short name T146
Test name
Test status
Simulation time 244614730 ps
CPU time 1.14 seconds
Started Jun 21 05:12:15 PM PDT 24
Finished Jun 21 05:12:18 PM PDT 24
Peak memory 218052 kb
Host smart-d9f348d4-6c0b-4b0a-b3b8-49a7a1419cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746744739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3746744739
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1662451730
Short name T325
Test name
Test status
Simulation time 195289357 ps
CPU time 0.88 seconds
Started Jun 21 05:12:13 PM PDT 24
Finished Jun 21 05:12:16 PM PDT 24
Peak memory 200500 kb
Host smart-b3c433e3-8555-4c83-a30c-73cc3059cc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662451730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1662451730
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.11765528
Short name T386
Test name
Test status
Simulation time 1849085055 ps
CPU time 7.41 seconds
Started Jun 21 05:12:20 PM PDT 24
Finished Jun 21 05:12:29 PM PDT 24
Peak memory 200864 kb
Host smart-68c030dc-2c30-4b1b-8c08-2a1226e1c55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11765528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.11765528
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.1093553202
Short name T68
Test name
Test status
Simulation time 8433809213 ps
CPU time 12.31 seconds
Started Jun 21 05:12:14 PM PDT 24
Finished Jun 21 05:12:28 PM PDT 24
Peak memory 217508 kb
Host smart-7b861d2e-ff0b-47d1-8d8d-65f6665a22f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093553202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1093553202
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.881609636
Short name T29
Test name
Test status
Simulation time 161741019 ps
CPU time 1.28 seconds
Started Jun 21 05:12:15 PM PDT 24
Finished Jun 21 05:12:19 PM PDT 24
Peak memory 200644 kb
Host smart-b895c81d-b2f2-469e-9e02-fc40221aa21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881609636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.881609636
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.70015897
Short name T182
Test name
Test status
Simulation time 118500033 ps
CPU time 1.19 seconds
Started Jun 21 05:12:17 PM PDT 24
Finished Jun 21 05:12:20 PM PDT 24
Peak memory 200812 kb
Host smart-5161d2fc-585a-4fba-bffb-7b7210f6fb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70015897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.70015897
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2087845814
Short name T346
Test name
Test status
Simulation time 11024910964 ps
CPU time 38.74 seconds
Started Jun 21 05:12:14 PM PDT 24
Finished Jun 21 05:12:54 PM PDT 24
Peak memory 200904 kb
Host smart-ea0c9fcc-7e52-4366-9422-24a772e9df96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087845814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2087845814
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1145017862
Short name T226
Test name
Test status
Simulation time 115313867 ps
CPU time 1.38 seconds
Started Jun 21 05:12:15 PM PDT 24
Finished Jun 21 05:12:18 PM PDT 24
Peak memory 200680 kb
Host smart-5fddc059-8e16-4e1a-9d25-f04891c3e059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145017862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1145017862
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.3584427699
Short name T261
Test name
Test status
Simulation time 219700022 ps
CPU time 1.39 seconds
Started Jun 21 05:12:20 PM PDT 24
Finished Jun 21 05:12:23 PM PDT 24
Peak memory 200688 kb
Host smart-3f87e90d-945e-41f5-89b4-e853e37cbd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584427699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.3584427699
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.1501659700
Short name T194
Test name
Test status
Simulation time 81457358 ps
CPU time 0.8 seconds
Started Jun 21 05:13:33 PM PDT 24
Finished Jun 21 05:13:38 PM PDT 24
Peak memory 200480 kb
Host smart-1789c384-9f29-458f-8b40-1d8904cefb4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501659700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.1501659700
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1087079243
Short name T476
Test name
Test status
Simulation time 1901545969 ps
CPU time 7.23 seconds
Started Jun 21 05:13:30 PM PDT 24
Finished Jun 21 05:13:41 PM PDT 24
Peak memory 218476 kb
Host smart-ccb6de8c-a7ba-4a0d-8b23-d9766b544a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087079243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1087079243
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3198116304
Short name T340
Test name
Test status
Simulation time 244281120 ps
CPU time 1.16 seconds
Started Jun 21 05:13:33 PM PDT 24
Finished Jun 21 05:13:39 PM PDT 24
Peak memory 218052 kb
Host smart-c8839009-ec84-4c82-8710-cd40d917d844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198116304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3198116304
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.1871569732
Short name T345
Test name
Test status
Simulation time 83896512 ps
CPU time 0.82 seconds
Started Jun 21 05:13:32 PM PDT 24
Finished Jun 21 05:13:37 PM PDT 24
Peak memory 200504 kb
Host smart-16e8b476-793f-41d1-aa5e-016158f52b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871569732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1871569732
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2928204493
Short name T315
Test name
Test status
Simulation time 943493925 ps
CPU time 4.85 seconds
Started Jun 21 05:13:35 PM PDT 24
Finished Jun 21 05:13:44 PM PDT 24
Peak memory 200820 kb
Host smart-03ebfe9e-e331-43be-86f4-4e2c2429145d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928204493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2928204493
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.4281539558
Short name T393
Test name
Test status
Simulation time 142818884 ps
CPU time 1.14 seconds
Started Jun 21 05:13:33 PM PDT 24
Finished Jun 21 05:13:39 PM PDT 24
Peak memory 200668 kb
Host smart-706b1079-2d68-416d-b059-58a04406ff58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281539558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.4281539558
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2086369532
Short name T74
Test name
Test status
Simulation time 107280352 ps
CPU time 1.13 seconds
Started Jun 21 05:13:31 PM PDT 24
Finished Jun 21 05:13:36 PM PDT 24
Peak memory 200936 kb
Host smart-1bfd20d7-d6bb-4adc-bb85-c19b20478e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086369532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2086369532
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3074878008
Short name T90
Test name
Test status
Simulation time 6314916247 ps
CPU time 22.33 seconds
Started Jun 21 05:13:32 PM PDT 24
Finished Jun 21 05:13:58 PM PDT 24
Peak memory 200592 kb
Host smart-1eb3f438-76e9-4893-8d76-290dd282a50a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074878008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3074878008
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2315994558
Short name T390
Test name
Test status
Simulation time 380532848 ps
CPU time 2.29 seconds
Started Jun 21 05:13:29 PM PDT 24
Finished Jun 21 05:13:36 PM PDT 24
Peak memory 200684 kb
Host smart-d42dc7c3-1d25-4733-a4aa-dc1a019aae1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315994558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2315994558
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2061260222
Short name T248
Test name
Test status
Simulation time 162689377 ps
CPU time 1.38 seconds
Started Jun 21 05:13:32 PM PDT 24
Finished Jun 21 05:13:37 PM PDT 24
Peak memory 200584 kb
Host smart-2f9313ca-22fe-4f5e-a016-273a0a9815eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061260222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2061260222
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3931651231
Short name T44
Test name
Test status
Simulation time 78117898 ps
CPU time 0.8 seconds
Started Jun 21 05:13:32 PM PDT 24
Finished Jun 21 05:13:36 PM PDT 24
Peak memory 200476 kb
Host smart-a5546888-4d93-4194-9300-48ed755e1a4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931651231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3931651231
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1142507550
Short name T42
Test name
Test status
Simulation time 1899209715 ps
CPU time 6.68 seconds
Started Jun 21 05:13:30 PM PDT 24
Finished Jun 21 05:13:41 PM PDT 24
Peak memory 222320 kb
Host smart-4eec3e9e-2f57-4d82-a63a-4515918165c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142507550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1142507550
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3706880205
Short name T192
Test name
Test status
Simulation time 244818424 ps
CPU time 1.07 seconds
Started Jun 21 05:13:36 PM PDT 24
Finished Jun 21 05:13:42 PM PDT 24
Peak memory 218000 kb
Host smart-62608855-6823-494c-b220-019a74c95799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706880205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3706880205
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.3937893544
Short name T503
Test name
Test status
Simulation time 162161121 ps
CPU time 0.83 seconds
Started Jun 21 05:13:31 PM PDT 24
Finished Jun 21 05:13:35 PM PDT 24
Peak memory 200504 kb
Host smart-e609c75c-0a53-47d2-b571-b58001c89584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937893544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3937893544
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3951917442
Short name T246
Test name
Test status
Simulation time 1183908383 ps
CPU time 4.79 seconds
Started Jun 21 05:13:35 PM PDT 24
Finished Jun 21 05:13:44 PM PDT 24
Peak memory 200836 kb
Host smart-550318bd-1471-4e16-a423-83a2d65f885b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951917442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3951917442
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.510411844
Short name T5
Test name
Test status
Simulation time 151582279 ps
CPU time 1.14 seconds
Started Jun 21 05:13:33 PM PDT 24
Finished Jun 21 05:13:38 PM PDT 24
Peak memory 200676 kb
Host smart-55c56778-adbb-4253-b7b4-04f420daf169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510411844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.510411844
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.4237584908
Short name T533
Test name
Test status
Simulation time 122248299 ps
CPU time 1.19 seconds
Started Jun 21 05:13:31 PM PDT 24
Finished Jun 21 05:13:36 PM PDT 24
Peak memory 200872 kb
Host smart-7991dea9-d90a-4335-bd35-65b2f388a3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237584908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.4237584908
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.659510872
Short name T355
Test name
Test status
Simulation time 2674427496 ps
CPU time 11.66 seconds
Started Jun 21 05:13:35 PM PDT 24
Finished Jun 21 05:13:51 PM PDT 24
Peak memory 209140 kb
Host smart-a6643924-c176-40b8-9841-3de61018a1c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659510872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.659510872
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3522060745
Short name T215
Test name
Test status
Simulation time 293359462 ps
CPU time 1.92 seconds
Started Jun 21 05:13:29 PM PDT 24
Finished Jun 21 05:13:36 PM PDT 24
Peak memory 200672 kb
Host smart-9955eaf8-871b-4e8a-bc42-6eb9150c4d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522060745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3522060745
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.4180228814
Short name T228
Test name
Test status
Simulation time 233107927 ps
CPU time 1.37 seconds
Started Jun 21 05:13:32 PM PDT 24
Finished Jun 21 05:13:37 PM PDT 24
Peak memory 200688 kb
Host smart-a4b83e3b-4816-40d0-8d65-ec1a99181da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180228814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.4180228814
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2822602017
Short name T421
Test name
Test status
Simulation time 59745258 ps
CPU time 0.73 seconds
Started Jun 21 05:13:35 PM PDT 24
Finished Jun 21 05:13:40 PM PDT 24
Peak memory 200472 kb
Host smart-3cf4f035-5337-443f-a44c-e6b30bcdab65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822602017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2822602017
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.719372908
Short name T50
Test name
Test status
Simulation time 2365932660 ps
CPU time 9.33 seconds
Started Jun 21 05:13:32 PM PDT 24
Finished Jun 21 05:13:45 PM PDT 24
Peak memory 218280 kb
Host smart-a9f9952a-eb04-4451-b4f3-362c52fc34a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719372908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.719372908
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1952647872
Short name T240
Test name
Test status
Simulation time 243861448 ps
CPU time 1.09 seconds
Started Jun 21 05:13:32 PM PDT 24
Finished Jun 21 05:13:36 PM PDT 24
Peak memory 218084 kb
Host smart-18554a5e-f7f9-42ff-ae73-ee1be743a9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952647872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1952647872
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1232242833
Short name T483
Test name
Test status
Simulation time 181023312 ps
CPU time 0.89 seconds
Started Jun 21 05:13:33 PM PDT 24
Finished Jun 21 05:13:37 PM PDT 24
Peak memory 200516 kb
Host smart-e7d010d3-4042-4889-af51-98ad6b8b3e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232242833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1232242833
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1831239911
Short name T241
Test name
Test status
Simulation time 1185204343 ps
CPU time 4.71 seconds
Started Jun 21 05:13:30 PM PDT 24
Finished Jun 21 05:13:39 PM PDT 24
Peak memory 200908 kb
Host smart-746ddac7-4957-4931-9c47-080e50f51fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831239911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1831239911
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1861147579
Short name T152
Test name
Test status
Simulation time 97859677 ps
CPU time 0.99 seconds
Started Jun 21 05:13:31 PM PDT 24
Finished Jun 21 05:13:36 PM PDT 24
Peak memory 200648 kb
Host smart-72c25b54-d450-4dd5-a172-fc9af5266326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861147579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1861147579
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.216547479
Short name T232
Test name
Test status
Simulation time 194194355 ps
CPU time 1.34 seconds
Started Jun 21 05:13:31 PM PDT 24
Finished Jun 21 05:13:36 PM PDT 24
Peak memory 200880 kb
Host smart-f712ca46-6488-4c0b-aa9b-03e4f160fcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216547479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.216547479
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.169204381
Short name T514
Test name
Test status
Simulation time 384123717 ps
CPU time 2.41 seconds
Started Jun 21 05:13:32 PM PDT 24
Finished Jun 21 05:13:38 PM PDT 24
Peak memory 200880 kb
Host smart-ed3b99d8-edb7-47f7-9900-aec38ae8196c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169204381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.169204381
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1633378277
Short name T506
Test name
Test status
Simulation time 146696449 ps
CPU time 1.82 seconds
Started Jun 21 05:13:32 PM PDT 24
Finished Jun 21 05:13:37 PM PDT 24
Peak memory 200604 kb
Host smart-ef9184a1-2b46-4f61-a955-70fd8f7bbabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633378277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1633378277
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1161269046
Short name T155
Test name
Test status
Simulation time 74869933 ps
CPU time 0.79 seconds
Started Jun 21 05:13:33 PM PDT 24
Finished Jun 21 05:13:38 PM PDT 24
Peak memory 200704 kb
Host smart-89a340f0-d6a2-4079-a80b-67e0f8bdce15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161269046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1161269046
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.310660407
Short name T347
Test name
Test status
Simulation time 70493875 ps
CPU time 0.76 seconds
Started Jun 21 05:13:29 PM PDT 24
Finished Jun 21 05:13:34 PM PDT 24
Peak memory 200476 kb
Host smart-b681f990-995c-4959-bcc4-58ddc9376f39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310660407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.310660407
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2545054711
Short name T58
Test name
Test status
Simulation time 1897126713 ps
CPU time 6.68 seconds
Started Jun 21 05:13:35 PM PDT 24
Finished Jun 21 05:13:46 PM PDT 24
Peak memory 221556 kb
Host smart-068432b7-4da3-45fb-a684-4a91edc92458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545054711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2545054711
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.814060023
Short name T7
Test name
Test status
Simulation time 245704759 ps
CPU time 1.06 seconds
Started Jun 21 05:13:30 PM PDT 24
Finished Jun 21 05:13:35 PM PDT 24
Peak memory 218032 kb
Host smart-b3f2560f-a94f-4044-aba4-5a97554e3467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814060023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.814060023
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3619124197
Short name T250
Test name
Test status
Simulation time 178703670 ps
CPU time 0.9 seconds
Started Jun 21 05:13:31 PM PDT 24
Finished Jun 21 05:13:36 PM PDT 24
Peak memory 200488 kb
Host smart-115a3b7b-48fc-427d-b087-62d615252257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619124197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3619124197
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.477208462
Short name T420
Test name
Test status
Simulation time 1231870659 ps
CPU time 4.67 seconds
Started Jun 21 05:13:35 PM PDT 24
Finished Jun 21 05:13:44 PM PDT 24
Peak memory 200804 kb
Host smart-aa3a1ff2-2e2f-4252-b8db-28dd81955bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477208462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.477208462
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.106908053
Short name T520
Test name
Test status
Simulation time 185952847 ps
CPU time 1.19 seconds
Started Jun 21 05:13:33 PM PDT 24
Finished Jun 21 05:13:39 PM PDT 24
Peak memory 200652 kb
Host smart-2de8d4e3-2213-420d-acf2-d1cfce5854b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106908053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.106908053
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.995874291
Short name T537
Test name
Test status
Simulation time 195117310 ps
CPU time 1.32 seconds
Started Jun 21 05:13:31 PM PDT 24
Finished Jun 21 05:13:36 PM PDT 24
Peak memory 200848 kb
Host smart-4ccb36b1-6b0a-4b39-bc73-e1ed306ebefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995874291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.995874291
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1865581149
Short name T450
Test name
Test status
Simulation time 7678340732 ps
CPU time 27.53 seconds
Started Jun 21 05:13:31 PM PDT 24
Finished Jun 21 05:14:03 PM PDT 24
Peak memory 201072 kb
Host smart-e767dcb8-897b-43f4-b9d1-cffaa48430a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865581149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1865581149
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3017500332
Short name T158
Test name
Test status
Simulation time 119239952 ps
CPU time 1.55 seconds
Started Jun 21 05:13:31 PM PDT 24
Finished Jun 21 05:13:37 PM PDT 24
Peak memory 200720 kb
Host smart-3dd9ac0b-d525-4ade-ade7-95dcba47945f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017500332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3017500332
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.2438728695
Short name T164
Test name
Test status
Simulation time 97276203 ps
CPU time 0.9 seconds
Started Jun 21 05:13:33 PM PDT 24
Finished Jun 21 05:13:38 PM PDT 24
Peak memory 200676 kb
Host smart-65e60420-14ef-4888-a9f9-3817779a6224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438728695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2438728695
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2272769000
Short name T382
Test name
Test status
Simulation time 63614594 ps
CPU time 0.73 seconds
Started Jun 21 05:13:39 PM PDT 24
Finished Jun 21 05:13:43 PM PDT 24
Peak memory 200488 kb
Host smart-05cd80db-983e-4ba2-8cfb-427e7f6b513e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272769000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2272769000
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2507680194
Short name T458
Test name
Test status
Simulation time 1886038527 ps
CPU time 6.96 seconds
Started Jun 21 05:13:40 PM PDT 24
Finished Jun 21 05:13:50 PM PDT 24
Peak memory 218396 kb
Host smart-57d87249-b0e4-4668-8abc-95a444e80275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507680194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2507680194
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.283469879
Short name T437
Test name
Test status
Simulation time 244733898 ps
CPU time 1.1 seconds
Started Jun 21 05:13:40 PM PDT 24
Finished Jun 21 05:13:44 PM PDT 24
Peak memory 218116 kb
Host smart-a03bb0dc-20e8-48fb-9c06-9fbf0d5a0aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283469879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.283469879
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3787938026
Short name T361
Test name
Test status
Simulation time 216147934 ps
CPU time 0.93 seconds
Started Jun 21 05:13:38 PM PDT 24
Finished Jun 21 05:13:42 PM PDT 24
Peak memory 200448 kb
Host smart-bccf79c8-b5f4-43ae-a9b6-4253c7f2f4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787938026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3787938026
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.527709398
Short name T101
Test name
Test status
Simulation time 1606707163 ps
CPU time 7.16 seconds
Started Jun 21 05:13:39 PM PDT 24
Finished Jun 21 05:13:50 PM PDT 24
Peak memory 200820 kb
Host smart-6959d161-50ef-4f93-82db-c6fa173f34e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527709398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.527709398
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2431066911
Short name T430
Test name
Test status
Simulation time 101082724 ps
CPU time 0.95 seconds
Started Jun 21 05:13:38 PM PDT 24
Finished Jun 21 05:13:42 PM PDT 24
Peak memory 200668 kb
Host smart-fa31ebb2-93fb-4ecb-a331-9b039fb03210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431066911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2431066911
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.781724696
Short name T451
Test name
Test status
Simulation time 240366305 ps
CPU time 1.53 seconds
Started Jun 21 05:13:34 PM PDT 24
Finished Jun 21 05:13:39 PM PDT 24
Peak memory 200876 kb
Host smart-874984f6-142a-450a-a0b7-dd6f11e06e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781724696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.781724696
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2007296168
Short name T280
Test name
Test status
Simulation time 4021322705 ps
CPU time 18.95 seconds
Started Jun 21 05:13:52 PM PDT 24
Finished Jun 21 05:14:12 PM PDT 24
Peak memory 209844 kb
Host smart-d95ca2e1-beb5-4ced-81d2-c2cf32d2c68a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007296168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2007296168
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.429921866
Short name T432
Test name
Test status
Simulation time 148952679 ps
CPU time 1.91 seconds
Started Jun 21 05:13:39 PM PDT 24
Finished Jun 21 05:13:44 PM PDT 24
Peak memory 200688 kb
Host smart-5216e9ef-4a9d-4d58-9089-ae443e38d2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429921866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.429921866
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.234801774
Short name T231
Test name
Test status
Simulation time 206608161 ps
CPU time 1.27 seconds
Started Jun 21 05:13:40 PM PDT 24
Finished Jun 21 05:13:44 PM PDT 24
Peak memory 200668 kb
Host smart-263c6113-01eb-4a13-989d-3682f5cf2c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234801774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.234801774
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.890554863
Short name T523
Test name
Test status
Simulation time 89404357 ps
CPU time 0.83 seconds
Started Jun 21 05:13:52 PM PDT 24
Finished Jun 21 05:13:54 PM PDT 24
Peak memory 200220 kb
Host smart-beb23004-8f9f-4cc7-8610-800ab1835a60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890554863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.890554863
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2025158376
Short name T373
Test name
Test status
Simulation time 2348850639 ps
CPU time 7.94 seconds
Started Jun 21 05:13:38 PM PDT 24
Finished Jun 21 05:13:50 PM PDT 24
Peak memory 218524 kb
Host smart-a517c465-e848-4621-bf42-87f9a6dc444b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025158376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2025158376
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.576618770
Short name T409
Test name
Test status
Simulation time 244248270 ps
CPU time 1.08 seconds
Started Jun 21 05:13:38 PM PDT 24
Finished Jun 21 05:13:42 PM PDT 24
Peak memory 218068 kb
Host smart-cf35035d-1a52-4103-be2f-894ff3fe1ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576618770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.576618770
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3259562615
Short name T507
Test name
Test status
Simulation time 207151933 ps
CPU time 0.9 seconds
Started Jun 21 05:13:52 PM PDT 24
Finished Jun 21 05:13:54 PM PDT 24
Peak memory 200392 kb
Host smart-903f5355-540e-4be5-8314-0966de58fce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259562615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3259562615
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2326248718
Short name T104
Test name
Test status
Simulation time 805043253 ps
CPU time 4.23 seconds
Started Jun 21 05:13:52 PM PDT 24
Finished Jun 21 05:13:57 PM PDT 24
Peak memory 200868 kb
Host smart-d90a98a6-560b-4ff8-87cb-2dfd9931f911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326248718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2326248718
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.598571485
Short name T427
Test name
Test status
Simulation time 176744282 ps
CPU time 1.13 seconds
Started Jun 21 05:13:38 PM PDT 24
Finished Jun 21 05:13:43 PM PDT 24
Peak memory 200704 kb
Host smart-0a663591-bbab-475d-aec2-22bfa2297f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598571485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.598571485
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2672588210
Short name T313
Test name
Test status
Simulation time 114526774 ps
CPU time 1.16 seconds
Started Jun 21 05:13:41 PM PDT 24
Finished Jun 21 05:13:45 PM PDT 24
Peak memory 200804 kb
Host smart-e9c357d9-a791-4e74-8298-eff223831c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672588210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2672588210
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3801673935
Short name T334
Test name
Test status
Simulation time 6841759926 ps
CPU time 25.97 seconds
Started Jun 21 05:13:40 PM PDT 24
Finished Jun 21 05:14:09 PM PDT 24
Peak memory 209120 kb
Host smart-6cdf7102-1714-4204-ba10-87bfbb8c2ca3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801673935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3801673935
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1235885700
Short name T210
Test name
Test status
Simulation time 420158378 ps
CPU time 2.33 seconds
Started Jun 21 05:13:39 PM PDT 24
Finished Jun 21 05:13:45 PM PDT 24
Peak memory 208868 kb
Host smart-908d0c1f-9ecc-4c8e-b01f-1a49f5652c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235885700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1235885700
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2604419497
Short name T326
Test name
Test status
Simulation time 172230903 ps
CPU time 1.18 seconds
Started Jun 21 05:13:39 PM PDT 24
Finished Jun 21 05:13:43 PM PDT 24
Peak memory 200692 kb
Host smart-2109e1d5-b71b-433b-b875-373458afd11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604419497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2604419497
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.286077126
Short name T213
Test name
Test status
Simulation time 57736569 ps
CPU time 0.73 seconds
Started Jun 21 05:13:52 PM PDT 24
Finished Jun 21 05:13:53 PM PDT 24
Peak memory 200440 kb
Host smart-72126743-6b36-4cbe-a87b-71d9d1d6268d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286077126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.286077126
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.930723888
Short name T464
Test name
Test status
Simulation time 243739445 ps
CPU time 1.11 seconds
Started Jun 21 05:13:39 PM PDT 24
Finished Jun 21 05:13:44 PM PDT 24
Peak memory 218012 kb
Host smart-9a99e2c0-5d62-4b4b-af84-7e90207f51c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930723888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.930723888
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.220223484
Short name T307
Test name
Test status
Simulation time 182647637 ps
CPU time 0.83 seconds
Started Jun 21 05:13:40 PM PDT 24
Finished Jun 21 05:13:44 PM PDT 24
Peak memory 200476 kb
Host smart-3a6c0245-b659-4a55-975f-20abc0464dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220223484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.220223484
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2120112438
Short name T510
Test name
Test status
Simulation time 873284583 ps
CPU time 3.95 seconds
Started Jun 21 05:13:40 PM PDT 24
Finished Jun 21 05:13:47 PM PDT 24
Peak memory 200876 kb
Host smart-0b22a547-9c47-4b84-aa3e-34fe401a4609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120112438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2120112438
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1709704302
Short name T339
Test name
Test status
Simulation time 101022542 ps
CPU time 1.07 seconds
Started Jun 21 05:13:40 PM PDT 24
Finished Jun 21 05:13:44 PM PDT 24
Peak memory 200684 kb
Host smart-abb302d5-ad2b-443e-bd58-f5ed30ba91f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709704302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1709704302
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1577842109
Short name T330
Test name
Test status
Simulation time 228647875 ps
CPU time 1.46 seconds
Started Jun 21 05:13:39 PM PDT 24
Finished Jun 21 05:13:43 PM PDT 24
Peak memory 200884 kb
Host smart-80b69e35-efde-4371-ad4b-c8263ac8a577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577842109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1577842109
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1495756533
Short name T100
Test name
Test status
Simulation time 7425924204 ps
CPU time 34.15 seconds
Started Jun 21 05:13:39 PM PDT 24
Finished Jun 21 05:14:16 PM PDT 24
Peak memory 201008 kb
Host smart-6d18f768-901f-44f3-b9a6-27590e94c134
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495756533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1495756533
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3414162317
Short name T206
Test name
Test status
Simulation time 139489857 ps
CPU time 1.85 seconds
Started Jun 21 05:13:52 PM PDT 24
Finished Jun 21 05:13:55 PM PDT 24
Peak memory 200628 kb
Host smart-55177797-bee5-45fc-8d46-32a56323ea4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414162317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3414162317
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2547522791
Short name T445
Test name
Test status
Simulation time 177916674 ps
CPU time 1.26 seconds
Started Jun 21 05:13:40 PM PDT 24
Finished Jun 21 05:13:45 PM PDT 24
Peak memory 200804 kb
Host smart-4f27494f-213d-4e7a-ad56-a2028bc2f6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547522791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2547522791
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3896571226
Short name T169
Test name
Test status
Simulation time 66406207 ps
CPU time 0.79 seconds
Started Jun 21 05:13:37 PM PDT 24
Finished Jun 21 05:13:42 PM PDT 24
Peak memory 200488 kb
Host smart-1ae115f1-f228-4f22-ae0d-7ba278c456f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896571226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3896571226
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.102646510
Short name T317
Test name
Test status
Simulation time 2170586915 ps
CPU time 8 seconds
Started Jun 21 05:13:39 PM PDT 24
Finished Jun 21 05:13:50 PM PDT 24
Peak memory 222448 kb
Host smart-9be1a409-c99e-46de-9580-28d608fced16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102646510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.102646510
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.928775485
Short name T391
Test name
Test status
Simulation time 244233780 ps
CPU time 1.2 seconds
Started Jun 21 05:13:38 PM PDT 24
Finished Jun 21 05:13:43 PM PDT 24
Peak memory 218064 kb
Host smart-8e7eb43b-b970-46b4-8b8e-381728c78551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928775485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.928775485
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.1891468947
Short name T221
Test name
Test status
Simulation time 132113718 ps
CPU time 0.83 seconds
Started Jun 21 05:13:52 PM PDT 24
Finished Jun 21 05:13:54 PM PDT 24
Peak memory 200380 kb
Host smart-39c81373-9285-4cf1-b947-e2c9a3d73e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891468947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1891468947
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.3599055599
Short name T266
Test name
Test status
Simulation time 1857079369 ps
CPU time 6.34 seconds
Started Jun 21 05:13:37 PM PDT 24
Finished Jun 21 05:13:47 PM PDT 24
Peak memory 200872 kb
Host smart-e046c790-232e-4d49-9855-f78e58e12389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599055599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3599055599
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.144706750
Short name T368
Test name
Test status
Simulation time 158618729 ps
CPU time 1.14 seconds
Started Jun 21 05:13:39 PM PDT 24
Finished Jun 21 05:13:44 PM PDT 24
Peak memory 200676 kb
Host smart-9ee52353-fb6e-4611-a6a5-6d6405562643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144706750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.144706750
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1933311158
Short name T45
Test name
Test status
Simulation time 202272582 ps
CPU time 1.4 seconds
Started Jun 21 05:13:40 PM PDT 24
Finished Jun 21 05:13:44 PM PDT 24
Peak memory 200872 kb
Host smart-a8c55ffa-e2e3-4ad3-a717-e4b56e17d267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933311158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1933311158
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1877861327
Short name T513
Test name
Test status
Simulation time 4228657518 ps
CPU time 21.68 seconds
Started Jun 21 05:13:40 PM PDT 24
Finished Jun 21 05:14:05 PM PDT 24
Peak memory 210408 kb
Host smart-d1d2a39b-ef23-4f65-bfc6-668b725dbdcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877861327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1877861327
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.1604572909
Short name T170
Test name
Test status
Simulation time 137563615 ps
CPU time 1.6 seconds
Started Jun 21 05:13:40 PM PDT 24
Finished Jun 21 05:13:44 PM PDT 24
Peak memory 208868 kb
Host smart-805efd72-12d8-49bf-bf7b-187faf177812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604572909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1604572909
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2640863977
Short name T515
Test name
Test status
Simulation time 104192267 ps
CPU time 0.9 seconds
Started Jun 21 05:13:40 PM PDT 24
Finished Jun 21 05:13:44 PM PDT 24
Peak memory 200692 kb
Host smart-f3944b52-aec2-4d51-a042-dd447066c551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640863977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2640863977
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.826097806
Short name T205
Test name
Test status
Simulation time 108163435 ps
CPU time 0.85 seconds
Started Jun 21 05:13:46 PM PDT 24
Finished Jun 21 05:13:48 PM PDT 24
Peak memory 200452 kb
Host smart-27c21bdc-f22d-42d9-8caa-d2962075e507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826097806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.826097806
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1011621763
Short name T352
Test name
Test status
Simulation time 1226703940 ps
CPU time 5.55 seconds
Started Jun 21 05:13:48 PM PDT 24
Finished Jun 21 05:13:55 PM PDT 24
Peak memory 217992 kb
Host smart-92ecd7f2-999e-4f77-931f-ef8410ed6d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011621763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1011621763
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3283616859
Short name T78
Test name
Test status
Simulation time 254491915 ps
CPU time 1.11 seconds
Started Jun 21 05:13:48 PM PDT 24
Finished Jun 21 05:13:50 PM PDT 24
Peak memory 218008 kb
Host smart-2010773f-323d-4541-8c34-d87d90d72e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283616859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3283616859
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3859302449
Short name T349
Test name
Test status
Simulation time 215909295 ps
CPU time 0.93 seconds
Started Jun 21 05:13:54 PM PDT 24
Finished Jun 21 05:13:56 PM PDT 24
Peak memory 200456 kb
Host smart-d1703efc-6512-477a-84a0-ef58b793b1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859302449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3859302449
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1246862681
Short name T374
Test name
Test status
Simulation time 1412542471 ps
CPU time 6.6 seconds
Started Jun 21 05:13:50 PM PDT 24
Finished Jun 21 05:13:58 PM PDT 24
Peak memory 200868 kb
Host smart-54049997-462c-4098-8ed5-d0da1ac2648b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246862681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1246862681
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.401670542
Short name T143
Test name
Test status
Simulation time 96733198 ps
CPU time 1.02 seconds
Started Jun 21 05:13:46 PM PDT 24
Finished Jun 21 05:13:48 PM PDT 24
Peak memory 200672 kb
Host smart-3132a788-ff26-42cc-ad93-7a9e46c5f4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401670542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.401670542
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2521163049
Short name T404
Test name
Test status
Simulation time 118705790 ps
CPU time 1.14 seconds
Started Jun 21 05:13:39 PM PDT 24
Finished Jun 21 05:13:44 PM PDT 24
Peak memory 200820 kb
Host smart-4b62bee1-1592-48d9-ad5d-a0dd1497a815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521163049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2521163049
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1152241019
Short name T99
Test name
Test status
Simulation time 5512500162 ps
CPU time 23.37 seconds
Started Jun 21 05:13:45 PM PDT 24
Finished Jun 21 05:14:09 PM PDT 24
Peak memory 200912 kb
Host smart-d3515a6a-7cff-40c9-8dc9-cca00b760aa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152241019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1152241019
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2908384388
Short name T494
Test name
Test status
Simulation time 143445904 ps
CPU time 1.83 seconds
Started Jun 21 05:13:50 PM PDT 24
Finished Jun 21 05:13:54 PM PDT 24
Peak memory 200680 kb
Host smart-6e2ea08e-bebb-44a6-a585-135ba0319fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908384388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2908384388
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.769354398
Short name T181
Test name
Test status
Simulation time 75404588 ps
CPU time 0.85 seconds
Started Jun 21 05:13:48 PM PDT 24
Finished Jun 21 05:13:50 PM PDT 24
Peak memory 200688 kb
Host smart-83b7e253-ef02-4330-8f32-ad73e0b9689a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769354398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.769354398
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.3947778795
Short name T166
Test name
Test status
Simulation time 65488589 ps
CPU time 0.78 seconds
Started Jun 21 05:13:48 PM PDT 24
Finished Jun 21 05:13:51 PM PDT 24
Peak memory 200488 kb
Host smart-53f86a24-b7b9-4909-9f47-4eccd1d7ce56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947778795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3947778795
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3233302734
Short name T383
Test name
Test status
Simulation time 1214204906 ps
CPU time 5.84 seconds
Started Jun 21 05:13:48 PM PDT 24
Finished Jun 21 05:13:55 PM PDT 24
Peak memory 218512 kb
Host smart-3ac2a0c0-87c3-4b18-a7aa-636c6067fdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233302734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3233302734
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.47028787
Short name T509
Test name
Test status
Simulation time 243492084 ps
CPU time 1.14 seconds
Started Jun 21 05:13:47 PM PDT 24
Finished Jun 21 05:13:49 PM PDT 24
Peak memory 218008 kb
Host smart-b7d86fc4-6e46-4405-a4e9-9841617830b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47028787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.47028787
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.3519840310
Short name T468
Test name
Test status
Simulation time 216490521 ps
CPU time 0.95 seconds
Started Jun 21 05:13:49 PM PDT 24
Finished Jun 21 05:13:52 PM PDT 24
Peak memory 200504 kb
Host smart-7f8679cb-22a0-4fe5-b864-b2839d3cf3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519840310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3519840310
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.87345948
Short name T97
Test name
Test status
Simulation time 1149418950 ps
CPU time 4.96 seconds
Started Jun 21 05:13:47 PM PDT 24
Finished Jun 21 05:13:54 PM PDT 24
Peak memory 200860 kb
Host smart-609b06fa-0fcf-4555-ba7c-b82c918745cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87345948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.87345948
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3414939206
Short name T295
Test name
Test status
Simulation time 106239998 ps
CPU time 1.06 seconds
Started Jun 21 05:13:48 PM PDT 24
Finished Jun 21 05:13:50 PM PDT 24
Peak memory 200800 kb
Host smart-ac63aa4f-91f3-49cd-813a-7ba92d0bb242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414939206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3414939206
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3063412817
Short name T470
Test name
Test status
Simulation time 119776702 ps
CPU time 1.16 seconds
Started Jun 21 05:13:50 PM PDT 24
Finished Jun 21 05:13:53 PM PDT 24
Peak memory 200916 kb
Host smart-d5ce3dfa-a827-49cf-8965-d5965b509a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063412817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3063412817
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1644931376
Short name T103
Test name
Test status
Simulation time 7179006010 ps
CPU time 23.5 seconds
Started Jun 21 05:13:46 PM PDT 24
Finished Jun 21 05:14:11 PM PDT 24
Peak memory 200896 kb
Host smart-2f2e4020-fe62-4cd2-9f7f-5302af819990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644931376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1644931376
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2313194945
Short name T484
Test name
Test status
Simulation time 380001538 ps
CPU time 2.62 seconds
Started Jun 21 05:13:46 PM PDT 24
Finished Jun 21 05:13:50 PM PDT 24
Peak memory 200680 kb
Host smart-abcb1bc3-6d32-468c-a9ce-a5f932b8d1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313194945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2313194945
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1482410332
Short name T448
Test name
Test status
Simulation time 108621209 ps
CPU time 0.92 seconds
Started Jun 21 05:13:48 PM PDT 24
Finished Jun 21 05:13:51 PM PDT 24
Peak memory 200692 kb
Host smart-ede6572e-1adf-48d5-a80a-4b26c58a938f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482410332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1482410332
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.125933202
Short name T397
Test name
Test status
Simulation time 67231077 ps
CPU time 0.77 seconds
Started Jun 21 05:12:24 PM PDT 24
Finished Jun 21 05:12:26 PM PDT 24
Peak memory 200484 kb
Host smart-2430d2da-00b4-4424-8ac9-36b18a5eec7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125933202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.125933202
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.852154827
Short name T53
Test name
Test status
Simulation time 1227950055 ps
CPU time 6.17 seconds
Started Jun 21 05:12:13 PM PDT 24
Finished Jun 21 05:12:21 PM PDT 24
Peak memory 218324 kb
Host smart-11406384-2143-4665-ab76-f47650c7fcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852154827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.852154827
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2164052981
Short name T289
Test name
Test status
Simulation time 244036349 ps
CPU time 1.05 seconds
Started Jun 21 05:12:14 PM PDT 24
Finished Jun 21 05:12:16 PM PDT 24
Peak memory 218052 kb
Host smart-90d8924c-6570-4952-a845-f1faa4e8b2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164052981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2164052981
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.929035939
Short name T20
Test name
Test status
Simulation time 78411501 ps
CPU time 0.73 seconds
Started Jun 21 05:12:17 PM PDT 24
Finished Jun 21 05:12:19 PM PDT 24
Peak memory 200448 kb
Host smart-cb525d15-10ad-48f4-abea-da8d4a5b7da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929035939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.929035939
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.3750930398
Short name T369
Test name
Test status
Simulation time 1618956077 ps
CPU time 6.21 seconds
Started Jun 21 05:12:16 PM PDT 24
Finished Jun 21 05:12:24 PM PDT 24
Peak memory 200876 kb
Host smart-811e13af-6a2c-4903-90ed-6ebb7c4cb346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750930398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3750930398
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1530011635
Short name T185
Test name
Test status
Simulation time 177956813 ps
CPU time 1.14 seconds
Started Jun 21 05:12:15 PM PDT 24
Finished Jun 21 05:12:18 PM PDT 24
Peak memory 200632 kb
Host smart-42878932-4025-41e4-9283-6dfcd876d6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530011635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1530011635
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3873519377
Short name T196
Test name
Test status
Simulation time 186565351 ps
CPU time 1.31 seconds
Started Jun 21 05:12:20 PM PDT 24
Finished Jun 21 05:12:22 PM PDT 24
Peak memory 200880 kb
Host smart-b33fabc3-eeff-4be6-a268-89572738c4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873519377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3873519377
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1207449176
Short name T376
Test name
Test status
Simulation time 3346006184 ps
CPU time 11.99 seconds
Started Jun 21 05:12:16 PM PDT 24
Finished Jun 21 05:12:30 PM PDT 24
Peak memory 209944 kb
Host smart-2f7024fa-6ba4-400b-b9c0-1a0e91a31596
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207449176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1207449176
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.116050875
Short name T144
Test name
Test status
Simulation time 354569321 ps
CPU time 2.22 seconds
Started Jun 21 05:12:16 PM PDT 24
Finished Jun 21 05:12:20 PM PDT 24
Peak memory 200648 kb
Host smart-3394d61c-cbe2-45a6-8259-a9bf3fbfc73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116050875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.116050875
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2798799613
Short name T153
Test name
Test status
Simulation time 115274420 ps
CPU time 1.01 seconds
Started Jun 21 05:12:18 PM PDT 24
Finished Jun 21 05:12:21 PM PDT 24
Peak memory 200636 kb
Host smart-7c471dee-53a0-40c5-b5b5-4de3f8b97f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798799613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2798799613
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.650301318
Short name T324
Test name
Test status
Simulation time 65819198 ps
CPU time 0.75 seconds
Started Jun 21 05:12:24 PM PDT 24
Finished Jun 21 05:12:26 PM PDT 24
Peak memory 200432 kb
Host smart-68613a71-196d-49de-82c6-06a843c87604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650301318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.650301318
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2748094739
Short name T286
Test name
Test status
Simulation time 1881671868 ps
CPU time 7.1 seconds
Started Jun 21 05:12:25 PM PDT 24
Finished Jun 21 05:12:34 PM PDT 24
Peak memory 218428 kb
Host smart-f129793a-baa1-4911-83b8-c7d5486505b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748094739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2748094739
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2012452913
Short name T460
Test name
Test status
Simulation time 244702493 ps
CPU time 1.05 seconds
Started Jun 21 05:12:23 PM PDT 24
Finished Jun 21 05:12:26 PM PDT 24
Peak memory 217964 kb
Host smart-fea6b419-454b-4a58-884f-93a8a37f8c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012452913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2012452913
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1787798956
Short name T262
Test name
Test status
Simulation time 203117149 ps
CPU time 0.9 seconds
Started Jun 21 05:12:23 PM PDT 24
Finished Jun 21 05:12:26 PM PDT 24
Peak memory 200544 kb
Host smart-4bb995b8-3bcb-4e9b-8625-e3e5f9633070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787798956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1787798956
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2222322952
Short name T414
Test name
Test status
Simulation time 1082714953 ps
CPU time 4.72 seconds
Started Jun 21 05:12:22 PM PDT 24
Finished Jun 21 05:12:29 PM PDT 24
Peak memory 200816 kb
Host smart-707c02e6-f5a1-415b-939f-a880f8350c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222322952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2222322952
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3225650739
Short name T292
Test name
Test status
Simulation time 106733710 ps
CPU time 1.01 seconds
Started Jun 21 05:12:22 PM PDT 24
Finished Jun 21 05:12:24 PM PDT 24
Peak memory 200800 kb
Host smart-ec2d283e-1d63-412e-8c9b-64c550eef382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225650739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3225650739
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.4253156558
Short name T511
Test name
Test status
Simulation time 248707938 ps
CPU time 1.58 seconds
Started Jun 21 05:12:25 PM PDT 24
Finished Jun 21 05:12:28 PM PDT 24
Peak memory 200828 kb
Host smart-fc944e22-26a5-4ae6-91aa-4cf09411822e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253156558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.4253156558
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3717112611
Short name T298
Test name
Test status
Simulation time 5416898847 ps
CPU time 24.38 seconds
Started Jun 21 05:12:28 PM PDT 24
Finished Jun 21 05:12:54 PM PDT 24
Peak memory 200864 kb
Host smart-26198a51-1e87-4673-976f-22de0215b740
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717112611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3717112611
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.3873866946
Short name T388
Test name
Test status
Simulation time 310783516 ps
CPU time 1.97 seconds
Started Jun 21 05:12:26 PM PDT 24
Finished Jun 21 05:12:29 PM PDT 24
Peak memory 208860 kb
Host smart-8459835a-6585-422b-a015-3f07f82e4df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873866946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.3873866946
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.878534284
Short name T518
Test name
Test status
Simulation time 181322759 ps
CPU time 1.3 seconds
Started Jun 21 05:12:29 PM PDT 24
Finished Jun 21 05:12:31 PM PDT 24
Peak memory 200628 kb
Host smart-4a31eb57-943a-4fe2-85f6-7995fb5400de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878534284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.878534284
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3308816685
Short name T26
Test name
Test status
Simulation time 73028512 ps
CPU time 0.77 seconds
Started Jun 21 05:12:29 PM PDT 24
Finished Jun 21 05:12:31 PM PDT 24
Peak memory 200420 kb
Host smart-bdb04846-41d6-404e-839c-2491e19abdd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308816685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3308816685
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1089615211
Short name T456
Test name
Test status
Simulation time 2361475266 ps
CPU time 7.76 seconds
Started Jun 21 05:12:25 PM PDT 24
Finished Jun 21 05:12:35 PM PDT 24
Peak memory 218540 kb
Host smart-9b034d03-9d92-4831-8048-0ddf9bec795f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089615211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1089615211
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2900683631
Short name T319
Test name
Test status
Simulation time 244326895 ps
CPU time 1.08 seconds
Started Jun 21 05:12:25 PM PDT 24
Finished Jun 21 05:12:28 PM PDT 24
Peak memory 218080 kb
Host smart-ae621930-7f04-4162-b17e-2965f65ab60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900683631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2900683631
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1128756226
Short name T329
Test name
Test status
Simulation time 154355646 ps
CPU time 0.89 seconds
Started Jun 21 05:12:24 PM PDT 24
Finished Jun 21 05:12:26 PM PDT 24
Peak memory 200448 kb
Host smart-b20825ce-6e6b-46a5-91e7-6509e4f4c1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128756226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1128756226
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.1395273327
Short name T529
Test name
Test status
Simulation time 1493254293 ps
CPU time 5.54 seconds
Started Jun 21 05:12:23 PM PDT 24
Finished Jun 21 05:12:30 PM PDT 24
Peak memory 200860 kb
Host smart-7d5eee56-c4f3-405d-8956-bfb32e38fb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395273327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1395273327
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.4111026167
Short name T531
Test name
Test status
Simulation time 149993202 ps
CPU time 1.18 seconds
Started Jun 21 05:12:24 PM PDT 24
Finished Jun 21 05:12:27 PM PDT 24
Peak memory 200628 kb
Host smart-531c5abf-1cc2-44b6-ad29-8277632f37ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111026167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.4111026167
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3971934147
Short name T49
Test name
Test status
Simulation time 235364195 ps
CPU time 1.48 seconds
Started Jun 21 05:12:26 PM PDT 24
Finished Jun 21 05:12:29 PM PDT 24
Peak memory 200876 kb
Host smart-941e0890-128b-46cd-b317-5b1f8d1847b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971934147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3971934147
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.79053935
Short name T475
Test name
Test status
Simulation time 8427922889 ps
CPU time 28.92 seconds
Started Jun 21 05:12:25 PM PDT 24
Finished Jun 21 05:12:56 PM PDT 24
Peak memory 209120 kb
Host smart-91c47083-fef3-448a-b0c7-8c6b281b760a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79053935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.79053935
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.563661126
Short name T73
Test name
Test status
Simulation time 420865136 ps
CPU time 2.16 seconds
Started Jun 21 05:12:23 PM PDT 24
Finished Jun 21 05:12:27 PM PDT 24
Peak memory 208824 kb
Host smart-24b7cbcd-d8a0-46d4-81e0-af7150c1cb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563661126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.563661126
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.4100899041
Short name T504
Test name
Test status
Simulation time 161578154 ps
CPU time 1.28 seconds
Started Jun 21 05:12:25 PM PDT 24
Finished Jun 21 05:12:28 PM PDT 24
Peak memory 200676 kb
Host smart-4023dcb2-c955-42c5-8ccb-ad7ae6ee134a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100899041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.4100899041
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1511332885
Short name T312
Test name
Test status
Simulation time 70024539 ps
CPU time 0.75 seconds
Started Jun 21 05:12:26 PM PDT 24
Finished Jun 21 05:12:29 PM PDT 24
Peak memory 200444 kb
Host smart-9b076deb-29d6-4124-b649-5f91320c024b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511332885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1511332885
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.4259019327
Short name T255
Test name
Test status
Simulation time 1893797012 ps
CPU time 7.07 seconds
Started Jun 21 05:12:30 PM PDT 24
Finished Jun 21 05:12:38 PM PDT 24
Peak memory 218404 kb
Host smart-9777b788-79cf-44b7-b202-8b48059f309c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259019327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.4259019327
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3347950995
Short name T178
Test name
Test status
Simulation time 244156693 ps
CPU time 1.12 seconds
Started Jun 21 05:12:26 PM PDT 24
Finished Jun 21 05:12:28 PM PDT 24
Peak memory 218064 kb
Host smart-d1159bcd-4a15-4643-8dfd-29284a11d5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347950995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3347950995
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.4021175553
Short name T498
Test name
Test status
Simulation time 135951798 ps
CPU time 0.83 seconds
Started Jun 21 05:12:25 PM PDT 24
Finished Jun 21 05:12:28 PM PDT 24
Peak memory 200480 kb
Host smart-92d8a3db-0b6a-42b6-813a-0a919d4e6159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021175553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.4021175553
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.4170106650
Short name T91
Test name
Test status
Simulation time 885155184 ps
CPU time 4.95 seconds
Started Jun 21 05:12:25 PM PDT 24
Finished Jun 21 05:12:32 PM PDT 24
Peak memory 200872 kb
Host smart-59c06127-1dc5-4c87-bbb8-b465cd80ef03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170106650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.4170106650
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1203907973
Short name T151
Test name
Test status
Simulation time 146940520 ps
CPU time 1.09 seconds
Started Jun 21 05:12:24 PM PDT 24
Finished Jun 21 05:12:27 PM PDT 24
Peak memory 200680 kb
Host smart-06c34334-c836-476f-a174-f8871861707f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203907973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1203907973
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.922109099
Short name T398
Test name
Test status
Simulation time 128783448 ps
CPU time 1.19 seconds
Started Jun 21 05:12:23 PM PDT 24
Finished Jun 21 05:12:26 PM PDT 24
Peak memory 200860 kb
Host smart-3fb59943-2227-451d-9118-0a227e89502d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922109099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.922109099
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.884716899
Short name T378
Test name
Test status
Simulation time 1776541079 ps
CPU time 7.21 seconds
Started Jun 21 05:12:28 PM PDT 24
Finished Jun 21 05:12:37 PM PDT 24
Peak memory 208996 kb
Host smart-d1ffabbb-cdaa-4b7e-beeb-ac75a4988f77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884716899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.884716899
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.367904006
Short name T207
Test name
Test status
Simulation time 387751238 ps
CPU time 2.35 seconds
Started Jun 21 05:12:26 PM PDT 24
Finished Jun 21 05:12:30 PM PDT 24
Peak memory 200616 kb
Host smart-c0fce080-e583-44a1-bf99-3f927b9031f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367904006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.367904006
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1148541897
Short name T371
Test name
Test status
Simulation time 93608052 ps
CPU time 0.94 seconds
Started Jun 21 05:12:25 PM PDT 24
Finished Jun 21 05:12:28 PM PDT 24
Peak memory 200704 kb
Host smart-fada9913-15cc-44d1-8102-b4a31d9ee7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148541897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1148541897
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2894280811
Short name T190
Test name
Test status
Simulation time 77786907 ps
CPU time 0.82 seconds
Started Jun 21 05:12:34 PM PDT 24
Finished Jun 21 05:12:37 PM PDT 24
Peak memory 200484 kb
Host smart-7d521550-eca3-4ac4-8761-06da1a0a3fd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894280811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2894280811
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.3319853139
Short name T10
Test name
Test status
Simulation time 2194926082 ps
CPU time 7.73 seconds
Started Jun 21 05:12:31 PM PDT 24
Finished Jun 21 05:12:39 PM PDT 24
Peak memory 218416 kb
Host smart-34a1ce51-5687-423c-ba88-4b7bbdea6c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319853139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3319853139
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2700404046
Short name T297
Test name
Test status
Simulation time 244276649 ps
CPU time 1.08 seconds
Started Jun 21 05:12:34 PM PDT 24
Finished Jun 21 05:12:37 PM PDT 24
Peak memory 218016 kb
Host smart-8290eb10-c83f-42f2-bdaf-8cdc814bc15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700404046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2700404046
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3168920920
Short name T22
Test name
Test status
Simulation time 83954947 ps
CPU time 0.78 seconds
Started Jun 21 05:12:23 PM PDT 24
Finished Jun 21 05:12:26 PM PDT 24
Peak memory 200484 kb
Host smart-b1f98c42-f7a8-4e90-beb3-f18b1c3ddc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168920920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3168920920
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.1191499339
Short name T438
Test name
Test status
Simulation time 1884037498 ps
CPU time 6.69 seconds
Started Jun 21 05:12:30 PM PDT 24
Finished Jun 21 05:12:38 PM PDT 24
Peak memory 200820 kb
Host smart-cf52b5b0-2f34-42c5-88a4-1c053a14a79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191499339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1191499339
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2365924162
Short name T333
Test name
Test status
Simulation time 140914615 ps
CPU time 1.05 seconds
Started Jun 21 05:12:35 PM PDT 24
Finished Jun 21 05:12:38 PM PDT 24
Peak memory 200676 kb
Host smart-a380fef3-354d-4837-a76f-01cad02347f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365924162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2365924162
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.274353508
Short name T214
Test name
Test status
Simulation time 120662541 ps
CPU time 1.23 seconds
Started Jun 21 05:12:23 PM PDT 24
Finished Jun 21 05:12:26 PM PDT 24
Peak memory 200880 kb
Host smart-58d5ca00-48ca-48a3-93a6-44d94cfba0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274353508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.274353508
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.2824864565
Short name T105
Test name
Test status
Simulation time 9305731977 ps
CPU time 36.55 seconds
Started Jun 21 05:12:32 PM PDT 24
Finished Jun 21 05:13:11 PM PDT 24
Peak memory 209060 kb
Host smart-fe059cb7-92ee-48c5-8cbf-41bc0a5e5749
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824864565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2824864565
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.714225063
Short name T138
Test name
Test status
Simulation time 531827844 ps
CPU time 2.84 seconds
Started Jun 21 05:12:31 PM PDT 24
Finished Jun 21 05:12:35 PM PDT 24
Peak memory 200660 kb
Host smart-96d72846-1fad-4fd7-bbb6-804b038f9281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714225063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.714225063
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3281487705
Short name T461
Test name
Test status
Simulation time 235988018 ps
CPU time 1.38 seconds
Started Jun 21 05:12:25 PM PDT 24
Finished Jun 21 05:12:28 PM PDT 24
Peak memory 200660 kb
Host smart-3b0e98d1-545a-4455-92fe-7af82516ea71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281487705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3281487705
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%