Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8536

1

T1

29

T2

6

T5

225

auto[1]

11432

1

T1

16

T2

1

T3

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6206	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6758	1			T1	15		T2	1		T3	2
reset_info_cp[2]	3071	1			T1	6		T3	1		T5	60
reset_info_cp[4]	3987	1			T1	14		T3	1		T5	107
reset_info_cp[8]	104	1			T5	2		T26	3		T45	3
reset_info_cp[16]	107	1			T5	2		T13	1		T42	1
reset_info_cp[32]	117	1			T1	1		T5	1		T6	1
reset_info_cp[64]	106	1			T5	1		T6	3		T13	2
reset_info_cp[128]	132	1			T5	3		T6	1		T7	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3293	1			T1	9		T5	58		T6	42
reset_info_cp[1]	auto[1]	2845	1			T1	5		T3	1		T5	57
reset_info_cp[2]	auto[0]	973	1			T1	4		T5	26		T6	24
reset_info_cp[2]	auto[1]	2098	1			T1	2		T3	1		T5	34
reset_info_cp[4]	auto[0]	1482	1			T1	8		T5	54		T6	32
reset_info_cp[4]	auto[1]	2505	1			T1	6		T3	1		T5	53
reset_info_cp[8]	auto[0]	42	1			T5	1		T45	2		T75	1
reset_info_cp[8]	auto[1]	62	1			T5	1		T26	3		T45	1
reset_info_cp[16]	auto[0]	48	1			T5	2		T45	1		T46	2
reset_info_cp[16]	auto[1]	59	1			T13	1		T42	1		T45	1
reset_info_cp[32]	auto[0]	44	1			T1	1		T5	1		T45	1
reset_info_cp[32]	auto[1]	73	1			T6	1		T7	1		T26	3
reset_info_cp[64]	auto[0]	45	1			T6	1		T45	1		T78	1
reset_info_cp[64]	auto[1]	61	1			T5	1		T6	2		T13	2
reset_info_cp[128]	auto[0]	45	1			T93	2		T69	1		T74	1
reset_info_cp[128]	auto[1]	87	1			T5	3		T6	1		T7	2