Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T538 /workspace/coverage/default/13.rstmgr_stress_all.4110826393 Jun 22 04:58:37 PM PDT 24 Jun 22 04:58:49 PM PDT 24 3163050837 ps
T539 /workspace/coverage/default/33.rstmgr_sw_rst.2382409547 Jun 22 04:59:00 PM PDT 24 Jun 22 04:59:06 PM PDT 24 325038851 ps
T540 /workspace/coverage/default/0.rstmgr_alert_test.833121459 Jun 22 04:58:13 PM PDT 24 Jun 22 04:58:14 PM PDT 24 74902356 ps
T541 /workspace/coverage/default/19.rstmgr_alert_test.467104640 Jun 22 04:58:55 PM PDT 24 Jun 22 04:58:58 PM PDT 24 68732533 ps
T542 /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1711992142 Jun 22 04:58:54 PM PDT 24 Jun 22 04:58:56 PM PDT 24 93784711 ps
T55 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.4091004552 Jun 22 04:38:57 PM PDT 24 Jun 22 04:38:59 PM PDT 24 226363358 ps
T56 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.554228187 Jun 22 04:38:55 PM PDT 24 Jun 22 04:38:57 PM PDT 24 149572995 ps
T57 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.698755052 Jun 22 04:39:04 PM PDT 24 Jun 22 04:39:06 PM PDT 24 126985904 ps
T59 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1420651734 Jun 22 04:38:41 PM PDT 24 Jun 22 04:38:46 PM PDT 24 184576965 ps
T58 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.363325385 Jun 22 04:38:49 PM PDT 24 Jun 22 04:38:50 PM PDT 24 79039802 ps
T60 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3806461939 Jun 22 04:38:59 PM PDT 24 Jun 22 04:39:01 PM PDT 24 176202368 ps
T61 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1189103339 Jun 22 04:39:12 PM PDT 24 Jun 22 04:39:16 PM PDT 24 130194325 ps
T102 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.885706911 Jun 22 04:39:04 PM PDT 24 Jun 22 04:39:06 PM PDT 24 71946476 ps
T81 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.618850467 Jun 22 04:38:42 PM PDT 24 Jun 22 04:38:47 PM PDT 24 805653492 ps
T87 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1052049729 Jun 22 04:39:04 PM PDT 24 Jun 22 04:39:07 PM PDT 24 421859729 ps
T82 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.485875711 Jun 22 04:39:09 PM PDT 24 Jun 22 04:39:13 PM PDT 24 369039359 ps
T103 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.560096499 Jun 22 04:39:02 PM PDT 24 Jun 22 04:39:04 PM PDT 24 80151281 ps
T104 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1443325303 Jun 22 04:39:00 PM PDT 24 Jun 22 04:39:02 PM PDT 24 80080289 ps
T105 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2094143874 Jun 22 04:38:58 PM PDT 24 Jun 22 04:39:01 PM PDT 24 80232294 ps
T88 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1079359738 Jun 22 04:39:22 PM PDT 24 Jun 22 04:39:26 PM PDT 24 963624253 ps
T89 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2890159716 Jun 22 04:39:00 PM PDT 24 Jun 22 04:39:03 PM PDT 24 489196737 ps
T106 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.4252664455 Jun 22 04:38:55 PM PDT 24 Jun 22 04:38:57 PM PDT 24 252905535 ps
T107 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1565788078 Jun 22 04:38:40 PM PDT 24 Jun 22 04:38:44 PM PDT 24 69405656 ps
T108 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.869279504 Jun 22 04:39:06 PM PDT 24 Jun 22 04:39:08 PM PDT 24 68735945 ps
T83 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.438052722 Jun 22 04:39:03 PM PDT 24 Jun 22 04:39:05 PM PDT 24 213782901 ps
T84 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.13959002 Jun 22 04:39:13 PM PDT 24 Jun 22 04:39:17 PM PDT 24 363905303 ps
T85 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1202236151 Jun 22 04:39:07 PM PDT 24 Jun 22 04:39:10 PM PDT 24 111612257 ps
T543 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.4204780765 Jun 22 04:38:51 PM PDT 24 Jun 22 04:38:52 PM PDT 24 106036260 ps
T544 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3427792355 Jun 22 04:39:08 PM PDT 24 Jun 22 04:39:11 PM PDT 24 112785754 ps
T109 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3433629141 Jun 22 04:38:54 PM PDT 24 Jun 22 04:38:56 PM PDT 24 94079106 ps
T86 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3124195593 Jun 22 04:39:11 PM PDT 24 Jun 22 04:39:17 PM PDT 24 883418219 ps
T545 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1142799421 Jun 22 04:39:03 PM PDT 24 Jun 22 04:39:06 PM PDT 24 346109649 ps
T119 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.276632907 Jun 22 04:38:46 PM PDT 24 Jun 22 04:38:48 PM PDT 24 214864338 ps
T110 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3835019487 Jun 22 04:38:58 PM PDT 24 Jun 22 04:39:01 PM PDT 24 231199003 ps
T546 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4215317300 Jun 22 04:38:45 PM PDT 24 Jun 22 04:38:47 PM PDT 24 145866703 ps
T111 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1163607107 Jun 22 04:39:01 PM PDT 24 Jun 22 04:39:04 PM PDT 24 116818575 ps
T547 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.4057550014 Jun 22 04:38:56 PM PDT 24 Jun 22 04:38:58 PM PDT 24 103956745 ps
T548 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1103709278 Jun 22 04:39:09 PM PDT 24 Jun 22 04:39:16 PM PDT 24 487913821 ps
T549 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.699106190 Jun 22 04:38:42 PM PDT 24 Jun 22 04:38:48 PM PDT 24 277024181 ps
T115 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.746616111 Jun 22 04:39:08 PM PDT 24 Jun 22 04:39:12 PM PDT 24 146408049 ps
T550 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2574614195 Jun 22 04:38:58 PM PDT 24 Jun 22 04:39:01 PM PDT 24 74579730 ps
T551 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1387481569 Jun 22 04:38:56 PM PDT 24 Jun 22 04:38:58 PM PDT 24 130868668 ps
T552 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2172742392 Jun 22 04:39:03 PM PDT 24 Jun 22 04:39:06 PM PDT 24 249787248 ps
T118 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3028488863 Jun 22 04:39:14 PM PDT 24 Jun 22 04:39:16 PM PDT 24 129956730 ps
T117 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.488184901 Jun 22 04:39:04 PM PDT 24 Jun 22 04:39:06 PM PDT 24 122566668 ps
T553 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.950299059 Jun 22 04:39:11 PM PDT 24 Jun 22 04:39:16 PM PDT 24 193791506 ps
T122 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2824358095 Jun 22 04:39:02 PM PDT 24 Jun 22 04:39:06 PM PDT 24 831287422 ps
T112 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2836077403 Jun 22 04:38:54 PM PDT 24 Jun 22 04:38:58 PM PDT 24 810581183 ps
T554 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2925412377 Jun 22 04:38:46 PM PDT 24 Jun 22 04:38:48 PM PDT 24 128569815 ps
T555 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2957198476 Jun 22 04:39:11 PM PDT 24 Jun 22 04:39:17 PM PDT 24 441369142 ps
T556 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.955187749 Jun 22 04:39:32 PM PDT 24 Jun 22 04:39:36 PM PDT 24 83868681 ps
T557 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3125787047 Jun 22 04:38:40 PM PDT 24 Jun 22 04:38:42 PM PDT 24 90607126 ps
T558 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1380261357 Jun 22 04:38:44 PM PDT 24 Jun 22 04:38:47 PM PDT 24 480487279 ps
T559 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.757699042 Jun 22 04:38:49 PM PDT 24 Jun 22 04:38:51 PM PDT 24 109954371 ps
T560 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3269356117 Jun 22 04:39:05 PM PDT 24 Jun 22 04:39:07 PM PDT 24 133191939 ps
T561 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2035242948 Jun 22 04:38:59 PM PDT 24 Jun 22 04:39:02 PM PDT 24 510614018 ps
T562 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4107138376 Jun 22 04:38:45 PM PDT 24 Jun 22 04:38:47 PM PDT 24 117983946 ps
T563 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1050351992 Jun 22 04:38:54 PM PDT 24 Jun 22 04:38:58 PM PDT 24 778377391 ps
T564 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1103109662 Jun 22 04:39:30 PM PDT 24 Jun 22 04:39:33 PM PDT 24 134904281 ps
T116 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3392083062 Jun 22 04:39:04 PM PDT 24 Jun 22 04:39:06 PM PDT 24 183114866 ps
T565 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3210817792 Jun 22 04:38:42 PM PDT 24 Jun 22 04:38:45 PM PDT 24 141818948 ps
T566 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3415112305 Jun 22 04:39:20 PM PDT 24 Jun 22 04:39:23 PM PDT 24 161498906 ps
T567 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4138603731 Jun 22 04:39:07 PM PDT 24 Jun 22 04:39:11 PM PDT 24 492905921 ps
T123 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3946212492 Jun 22 04:39:28 PM PDT 24 Jun 22 04:39:32 PM PDT 24 947241518 ps
T568 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3723604306 Jun 22 04:39:10 PM PDT 24 Jun 22 04:39:13 PM PDT 24 83775283 ps
T569 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1036372220 Jun 22 04:38:53 PM PDT 24 Jun 22 04:39:00 PM PDT 24 99785926 ps
T570 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1498844545 Jun 22 04:38:57 PM PDT 24 Jun 22 04:39:00 PM PDT 24 183081473 ps
T571 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.447057870 Jun 22 04:39:12 PM PDT 24 Jun 22 04:39:15 PM PDT 24 74784243 ps
T572 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3406495745 Jun 22 04:39:11 PM PDT 24 Jun 22 04:39:15 PM PDT 24 125665080 ps
T573 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3136530107 Jun 22 04:39:03 PM PDT 24 Jun 22 04:39:05 PM PDT 24 114942909 ps
T574 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2822601158 Jun 22 04:39:12 PM PDT 24 Jun 22 04:39:17 PM PDT 24 178369538 ps
T575 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.4046447033 Jun 22 04:39:18 PM PDT 24 Jun 22 04:39:21 PM PDT 24 493160901 ps
T576 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1959314451 Jun 22 04:39:00 PM PDT 24 Jun 22 04:39:02 PM PDT 24 86607214 ps
T577 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3811900977 Jun 22 04:39:05 PM PDT 24 Jun 22 04:39:07 PM PDT 24 116114989 ps
T578 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2765797746 Jun 22 04:38:57 PM PDT 24 Jun 22 04:39:03 PM PDT 24 1017340278 ps
T113 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.4119996497 Jun 22 04:39:02 PM PDT 24 Jun 22 04:39:05 PM PDT 24 417150900 ps
T579 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.4069867991 Jun 22 04:39:09 PM PDT 24 Jun 22 04:39:11 PM PDT 24 60787328 ps
T580 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2232323921 Jun 22 04:39:02 PM PDT 24 Jun 22 04:39:03 PM PDT 24 72364782 ps
T581 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3764871371 Jun 22 04:39:10 PM PDT 24 Jun 22 04:39:16 PM PDT 24 270232079 ps
T582 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4164638492 Jun 22 04:39:07 PM PDT 24 Jun 22 04:39:10 PM PDT 24 123449397 ps
T583 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.127928057 Jun 22 04:39:11 PM PDT 24 Jun 22 04:39:14 PM PDT 24 56949694 ps
T584 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1513854927 Jun 22 04:39:06 PM PDT 24 Jun 22 04:39:08 PM PDT 24 129204337 ps
T585 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3580597763 Jun 22 04:38:45 PM PDT 24 Jun 22 04:38:49 PM PDT 24 279784279 ps
T586 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2309565219 Jun 22 04:38:59 PM PDT 24 Jun 22 04:39:03 PM PDT 24 467584086 ps
T587 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.763119360 Jun 22 04:38:56 PM PDT 24 Jun 22 04:38:58 PM PDT 24 55526964 ps
T588 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1883717672 Jun 22 04:38:54 PM PDT 24 Jun 22 04:38:57 PM PDT 24 204955954 ps
T589 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3760865865 Jun 22 04:39:03 PM PDT 24 Jun 22 04:39:07 PM PDT 24 274742830 ps
T590 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3639714494 Jun 22 04:39:25 PM PDT 24 Jun 22 04:39:27 PM PDT 24 127694651 ps
T591 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2686805548 Jun 22 04:39:06 PM PDT 24 Jun 22 04:39:09 PM PDT 24 185332977 ps
T592 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3980194288 Jun 22 04:39:08 PM PDT 24 Jun 22 04:39:11 PM PDT 24 113522046 ps
T593 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.121151403 Jun 22 04:39:12 PM PDT 24 Jun 22 04:39:16 PM PDT 24 197772611 ps
T594 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.373066995 Jun 22 04:39:06 PM PDT 24 Jun 22 04:39:09 PM PDT 24 330569745 ps
T595 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3838892575 Jun 22 04:39:03 PM PDT 24 Jun 22 04:39:07 PM PDT 24 926085722 ps
T596 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3069254828 Jun 22 04:39:03 PM PDT 24 Jun 22 04:39:05 PM PDT 24 89165691 ps
T597 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1971569294 Jun 22 04:39:22 PM PDT 24 Jun 22 04:39:26 PM PDT 24 793403663 ps
T598 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.875210319 Jun 22 04:39:11 PM PDT 24 Jun 22 04:39:15 PM PDT 24 208067019 ps
T599 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3748418409 Jun 22 04:39:03 PM PDT 24 Jun 22 04:39:05 PM PDT 24 76190652 ps
T600 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2293670073 Jun 22 04:38:49 PM PDT 24 Jun 22 04:38:53 PM PDT 24 389325303 ps
T601 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1579307292 Jun 22 04:39:08 PM PDT 24 Jun 22 04:39:11 PM PDT 24 252619063 ps
T602 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.539257565 Jun 22 04:39:01 PM PDT 24 Jun 22 04:39:03 PM PDT 24 150033952 ps
T603 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.774562380 Jun 22 04:39:03 PM PDT 24 Jun 22 04:39:05 PM PDT 24 171154887 ps
T604 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3034947938 Jun 22 04:39:03 PM PDT 24 Jun 22 04:39:05 PM PDT 24 107825414 ps
T605 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2507165161 Jun 22 04:39:10 PM PDT 24 Jun 22 04:39:13 PM PDT 24 84116331 ps
T606 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3226950085 Jun 22 04:38:51 PM PDT 24 Jun 22 04:38:54 PM PDT 24 185030539 ps
T607 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.539223793 Jun 22 04:38:54 PM PDT 24 Jun 22 04:38:57 PM PDT 24 423652084 ps
T608 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3710432447 Jun 22 04:38:58 PM PDT 24 Jun 22 04:39:02 PM PDT 24 467323107 ps
T609 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1137952024 Jun 22 04:39:09 PM PDT 24 Jun 22 04:39:12 PM PDT 24 135332698 ps
T610 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2387832483 Jun 22 04:39:04 PM PDT 24 Jun 22 04:39:06 PM PDT 24 178665937 ps
T611 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1711661340 Jun 22 04:38:44 PM PDT 24 Jun 22 04:38:47 PM PDT 24 276741271 ps
T124 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3333045688 Jun 22 04:38:54 PM PDT 24 Jun 22 04:38:57 PM PDT 24 461665314 ps
T612 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1613298059 Jun 22 04:39:08 PM PDT 24 Jun 22 04:39:11 PM PDT 24 63070360 ps
T613 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2961160271 Jun 22 04:39:04 PM PDT 24 Jun 22 04:39:07 PM PDT 24 136950659 ps
T614 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3260759247 Jun 22 04:39:21 PM PDT 24 Jun 22 04:39:24 PM PDT 24 121693275 ps
T615 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1740490005 Jun 22 04:39:08 PM PDT 24 Jun 22 04:39:11 PM PDT 24 130397017 ps
T616 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.877091449 Jun 22 04:39:11 PM PDT 24 Jun 22 04:39:15 PM PDT 24 95576284 ps
T617 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1848368997 Jun 22 04:39:17 PM PDT 24 Jun 22 04:39:19 PM PDT 24 75320050 ps
T618 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1784495495 Jun 22 04:39:01 PM PDT 24 Jun 22 04:39:05 PM PDT 24 386907822 ps
T619 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.958051501 Jun 22 04:39:14 PM PDT 24 Jun 22 04:39:18 PM PDT 24 473485620 ps
T620 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1134040424 Jun 22 04:39:06 PM PDT 24 Jun 22 04:39:09 PM PDT 24 498703867 ps
T114 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1958361742 Jun 22 04:39:10 PM PDT 24 Jun 22 04:39:16 PM PDT 24 1224006233 ps

Test location /workspace/coverage/default/28.rstmgr_stress_all.3662805991
Short name T5
Test name
Test status
Simulation time 11813793360 ps
CPU time 42.09 seconds
Started Jun 22 04:58:54 PM PDT 24
Finished Jun 22 04:59:37 PM PDT 24
Peak memory 209152 kb
Host smart-2caf2970-3ad4-4210-8394-99be4ecec56d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662805991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3662805991
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.2644773336
Short name T77
Test name
Test status
Simulation time 118362196 ps
CPU time 1.6 seconds
Started Jun 22 04:58:22 PM PDT 24
Finished Jun 22 04:58:25 PM PDT 24
Peak memory 200692 kb
Host smart-2f1ba79c-fb36-4ad0-b24c-fe8be6868dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644773336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2644773336
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.618850467
Short name T81
Test name
Test status
Simulation time 805653492 ps
CPU time 2.76 seconds
Started Jun 22 04:38:42 PM PDT 24
Finished Jun 22 04:38:47 PM PDT 24
Peak memory 200912 kb
Host smart-65987394-da86-4d25-b38b-99a572a1cc43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618850467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
618850467
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.3791714208
Short name T63
Test name
Test status
Simulation time 16745997059 ps
CPU time 25.69 seconds
Started Jun 22 04:58:12 PM PDT 24
Finished Jun 22 04:58:39 PM PDT 24
Peak memory 218732 kb
Host smart-bf021b24-678d-4315-8fea-da9241f4a6c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791714208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3791714208
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1806093522
Short name T7
Test name
Test status
Simulation time 1219456058 ps
CPU time 5.35 seconds
Started Jun 22 04:59:02 PM PDT 24
Finished Jun 22 04:59:10 PM PDT 24
Peak memory 218412 kb
Host smart-2c2fbbe7-4886-4dc7-a7a0-59d9280608b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806093522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1806093522
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1420651734
Short name T59
Test name
Test status
Simulation time 184576965 ps
CPU time 2.67 seconds
Started Jun 22 04:38:41 PM PDT 24
Finished Jun 22 04:38:46 PM PDT 24
Peak memory 209088 kb
Host smart-a924d7dd-76ac-4e8b-9a53-f38e457b253a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420651734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1420651734
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1829997979
Short name T78
Test name
Test status
Simulation time 12434127441 ps
CPU time 46.09 seconds
Started Jun 22 04:58:14 PM PDT 24
Finished Jun 22 04:59:02 PM PDT 24
Peak memory 209144 kb
Host smart-630138af-d644-4a77-8701-82d216a31d10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829997979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1829997979
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2223635890
Short name T153
Test name
Test status
Simulation time 183857300 ps
CPU time 1.25 seconds
Started Jun 22 04:58:13 PM PDT 24
Finished Jun 22 04:58:16 PM PDT 24
Peak memory 200700 kb
Host smart-d6a7c845-d9be-4d3d-9b7d-b179673e1fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223635890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2223635890
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2337153903
Short name T158
Test name
Test status
Simulation time 73242235 ps
CPU time 0.8 seconds
Started Jun 22 04:58:37 PM PDT 24
Finished Jun 22 04:58:39 PM PDT 24
Peak memory 200516 kb
Host smart-704a06b5-26da-4f16-b219-572244fc9c55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337153903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2337153903
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3946212492
Short name T123
Test name
Test status
Simulation time 947241518 ps
CPU time 3.22 seconds
Started Jun 22 04:39:28 PM PDT 24
Finished Jun 22 04:39:32 PM PDT 24
Peak memory 200864 kb
Host smart-d875f0e2-a764-42d2-a396-395214033735
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946212492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3946212492
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2253508332
Short name T32
Test name
Test status
Simulation time 1907469505 ps
CPU time 6.75 seconds
Started Jun 22 04:58:54 PM PDT 24
Finished Jun 22 04:59:02 PM PDT 24
Peak memory 222352 kb
Host smart-8d172d8f-1a2c-4e76-85c7-f409e346fc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253508332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2253508332
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3789825316
Short name T125
Test name
Test status
Simulation time 74233138 ps
CPU time 0.8 seconds
Started Jun 22 04:58:15 PM PDT 24
Finished Jun 22 04:58:17 PM PDT 24
Peak memory 200684 kb
Host smart-244d5ea7-cbe7-4328-a0e6-d5f1021d6ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789825316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3789825316
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_reset.923239762
Short name T195
Test name
Test status
Simulation time 1475212883 ps
CPU time 5.67 seconds
Started Jun 22 04:58:39 PM PDT 24
Finished Jun 22 04:58:46 PM PDT 24
Peak memory 200920 kb
Host smart-448abe40-f5cb-4fa9-99e0-3360e3aae571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923239762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.923239762
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1079359738
Short name T88
Test name
Test status
Simulation time 963624253 ps
CPU time 3.02 seconds
Started Jun 22 04:39:22 PM PDT 24
Finished Jun 22 04:39:26 PM PDT 24
Peak memory 200880 kb
Host smart-b1e65c52-ef63-4185-9350-dac7111afcb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079359738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1079359738
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2094143874
Short name T105
Test name
Test status
Simulation time 80232294 ps
CPU time 0.86 seconds
Started Jun 22 04:38:58 PM PDT 24
Finished Jun 22 04:39:01 PM PDT 24
Peak memory 200552 kb
Host smart-96b0f430-207a-4b71-abf5-5d4e5df9f574
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094143874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2094143874
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.455834864
Short name T8
Test name
Test status
Simulation time 229416729 ps
CPU time 0.94 seconds
Started Jun 22 04:58:13 PM PDT 24
Finished Jun 22 04:58:15 PM PDT 24
Peak memory 200756 kb
Host smart-1f4293be-126b-4946-8da3-0227b910f647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455834864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.455834864
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3431960851
Short name T36
Test name
Test status
Simulation time 1229007324 ps
CPU time 5.85 seconds
Started Jun 22 04:58:45 PM PDT 24
Finished Jun 22 04:58:52 PM PDT 24
Peak memory 218152 kb
Host smart-84e87a0c-563d-4451-88af-b30bfb146180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431960851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3431960851
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2293670073
Short name T600
Test name
Test status
Simulation time 389325303 ps
CPU time 2.82 seconds
Started Jun 22 04:38:49 PM PDT 24
Finished Jun 22 04:38:53 PM PDT 24
Peak memory 208904 kb
Host smart-fe4dd447-2177-4a93-94fe-3a43cb7665e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293670073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2293670073
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1958361742
Short name T114
Test name
Test status
Simulation time 1224006233 ps
CPU time 3.58 seconds
Started Jun 22 04:39:10 PM PDT 24
Finished Jun 22 04:39:16 PM PDT 24
Peak memory 200884 kb
Host smart-01151f8e-3bf1-49f6-b766-362dbec94913
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958361742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1958361742
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2836077403
Short name T112
Test name
Test status
Simulation time 810581183 ps
CPU time 2.77 seconds
Started Jun 22 04:38:54 PM PDT 24
Finished Jun 22 04:38:58 PM PDT 24
Peak memory 200808 kb
Host smart-0a28f36d-9e06-4995-a80c-7cdc34c2d989
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836077403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.2836077403
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2309565219
Short name T586
Test name
Test status
Simulation time 467584086 ps
CPU time 2.84 seconds
Started Jun 22 04:38:59 PM PDT 24
Finished Jun 22 04:39:03 PM PDT 24
Peak memory 200816 kb
Host smart-4fd5666e-378f-43f9-a6f0-e619b7e26c56
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309565219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
309565219
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1103709278
Short name T548
Test name
Test status
Simulation time 487913821 ps
CPU time 5.55 seconds
Started Jun 22 04:39:09 PM PDT 24
Finished Jun 22 04:39:16 PM PDT 24
Peak memory 200828 kb
Host smart-d235ca55-d4f6-45ef-bb5e-a2105184850d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103709278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
103709278
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1036372220
Short name T569
Test name
Test status
Simulation time 99785926 ps
CPU time 0.8 seconds
Started Jun 22 04:38:53 PM PDT 24
Finished Jun 22 04:39:00 PM PDT 24
Peak memory 200624 kb
Host smart-80ea69db-f7ba-4f25-9886-02debc354815
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036372220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
036372220
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.276632907
Short name T119
Test name
Test status
Simulation time 214864338 ps
CPU time 1.36 seconds
Started Jun 22 04:38:46 PM PDT 24
Finished Jun 22 04:38:48 PM PDT 24
Peak memory 208920 kb
Host smart-a0ceb959-918c-4d11-af94-358f73a120b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276632907 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.276632907
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3210817792
Short name T565
Test name
Test status
Simulation time 141818948 ps
CPU time 1.28 seconds
Started Jun 22 04:38:42 PM PDT 24
Finished Jun 22 04:38:45 PM PDT 24
Peak memory 200800 kb
Host smart-31b3d5ee-ee02-4a13-a35f-b54825ed6d3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210817792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3210817792
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3333045688
Short name T124
Test name
Test status
Simulation time 461665314 ps
CPU time 1.94 seconds
Started Jun 22 04:38:54 PM PDT 24
Finished Jun 22 04:38:57 PM PDT 24
Peak memory 201088 kb
Host smart-4741b6bc-99c2-4d3e-b122-2fe61aa8c82f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333045688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.3333045688
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1142799421
Short name T545
Test name
Test status
Simulation time 346109649 ps
CPU time 2.37 seconds
Started Jun 22 04:39:03 PM PDT 24
Finished Jun 22 04:39:06 PM PDT 24
Peak memory 200860 kb
Host smart-2cd23435-a9b1-4372-9607-b6ab26757acd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142799421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1
142799421
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.699106190
Short name T549
Test name
Test status
Simulation time 277024181 ps
CPU time 3.2 seconds
Started Jun 22 04:38:42 PM PDT 24
Finished Jun 22 04:38:48 PM PDT 24
Peak memory 200752 kb
Host smart-b034286b-04ff-43d6-9312-f4a303ea6483
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699106190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.699106190
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4107138376
Short name T562
Test name
Test status
Simulation time 117983946 ps
CPU time 0.88 seconds
Started Jun 22 04:38:45 PM PDT 24
Finished Jun 22 04:38:47 PM PDT 24
Peak memory 200604 kb
Host smart-ce9a009e-9a46-4eb0-8e44-5a3ab4d30e36
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107138376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.4
107138376
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.757699042
Short name T559
Test name
Test status
Simulation time 109954371 ps
CPU time 0.93 seconds
Started Jun 22 04:38:49 PM PDT 24
Finished Jun 22 04:38:51 PM PDT 24
Peak memory 209180 kb
Host smart-fbfb03bf-44d3-4119-b9be-58c1935ff69a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757699042 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.757699042
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1565788078
Short name T107
Test name
Test status
Simulation time 69405656 ps
CPU time 0.78 seconds
Started Jun 22 04:38:40 PM PDT 24
Finished Jun 22 04:38:44 PM PDT 24
Peak memory 200652 kb
Host smart-8c0978ee-e003-48de-b653-1ca794719ec0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565788078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1565788078
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2925412377
Short name T554
Test name
Test status
Simulation time 128569815 ps
CPU time 1.09 seconds
Started Jun 22 04:38:46 PM PDT 24
Finished Jun 22 04:38:48 PM PDT 24
Peak memory 200564 kb
Host smart-6be23bee-350b-40e1-b754-3b94a3dd06b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925412377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2925412377
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3838892575
Short name T595
Test name
Test status
Simulation time 926085722 ps
CPU time 3.32 seconds
Started Jun 22 04:39:03 PM PDT 24
Finished Jun 22 04:39:07 PM PDT 24
Peak memory 200720 kb
Host smart-50a8d5a8-fafa-480a-884c-75afe4890079
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838892575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3838892575
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1189103339
Short name T61
Test name
Test status
Simulation time 130194325 ps
CPU time 1.45 seconds
Started Jun 22 04:39:12 PM PDT 24
Finished Jun 22 04:39:16 PM PDT 24
Peak memory 208972 kb
Host smart-3f4f4d94-2134-4f74-80af-426312e2951c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189103339 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1189103339
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3433629141
Short name T109
Test name
Test status
Simulation time 94079106 ps
CPU time 0.88 seconds
Started Jun 22 04:38:54 PM PDT 24
Finished Jun 22 04:38:56 PM PDT 24
Peak memory 200504 kb
Host smart-77cfca61-a61a-42a2-a790-872c8b01e42c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433629141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3433629141
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3034947938
Short name T604
Test name
Test status
Simulation time 107825414 ps
CPU time 1.2 seconds
Started Jun 22 04:39:03 PM PDT 24
Finished Jun 22 04:39:05 PM PDT 24
Peak memory 200872 kb
Host smart-e410f184-9e9f-448c-a968-d20572c2b088
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034947938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3034947938
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1784495495
Short name T618
Test name
Test status
Simulation time 386907822 ps
CPU time 2.85 seconds
Started Jun 22 04:39:01 PM PDT 24
Finished Jun 22 04:39:05 PM PDT 24
Peak memory 209044 kb
Host smart-290fb176-5123-4bd4-9519-09c5974a3eb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784495495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1784495495
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3124195593
Short name T86
Test name
Test status
Simulation time 883418219 ps
CPU time 3.45 seconds
Started Jun 22 04:39:11 PM PDT 24
Finished Jun 22 04:39:17 PM PDT 24
Peak memory 200872 kb
Host smart-464d39ec-cdd7-447c-8f82-4fa654be9401
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124195593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3124195593
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2387832483
Short name T610
Test name
Test status
Simulation time 178665937 ps
CPU time 1.2 seconds
Started Jun 22 04:39:04 PM PDT 24
Finished Jun 22 04:39:06 PM PDT 24
Peak memory 208792 kb
Host smart-4d100494-c107-47f6-af9e-748695d8d321
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387832483 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2387832483
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1959314451
Short name T576
Test name
Test status
Simulation time 86607214 ps
CPU time 0.86 seconds
Started Jun 22 04:39:00 PM PDT 24
Finished Jun 22 04:39:02 PM PDT 24
Peak memory 200552 kb
Host smart-e1dad802-a67d-460f-a462-dc5713becfda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959314451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1959314451
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1579307292
Short name T601
Test name
Test status
Simulation time 252619063 ps
CPU time 1.5 seconds
Started Jun 22 04:39:08 PM PDT 24
Finished Jun 22 04:39:11 PM PDT 24
Peak memory 200752 kb
Host smart-f22f6bf5-767d-44f9-9321-dbad23860e85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579307292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1579307292
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.373066995
Short name T594
Test name
Test status
Simulation time 330569745 ps
CPU time 2.23 seconds
Started Jun 22 04:39:06 PM PDT 24
Finished Jun 22 04:39:09 PM PDT 24
Peak memory 209000 kb
Host smart-b71aaada-b3ce-4753-97db-cc650ffb5f21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373066995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.373066995
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2035242948
Short name T561
Test name
Test status
Simulation time 510614018 ps
CPU time 1.99 seconds
Started Jun 22 04:38:59 PM PDT 24
Finished Jun 22 04:39:02 PM PDT 24
Peak memory 200796 kb
Host smart-d5fe16a4-b422-4be4-a1e7-78e87c7919f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035242948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2035242948
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3136530107
Short name T573
Test name
Test status
Simulation time 114942909 ps
CPU time 1.31 seconds
Started Jun 22 04:39:03 PM PDT 24
Finished Jun 22 04:39:05 PM PDT 24
Peak memory 208776 kb
Host smart-9e7cbc7e-9349-406f-8ee6-aad95a18fd6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136530107 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3136530107
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.4069867991
Short name T579
Test name
Test status
Simulation time 60787328 ps
CPU time 0.76 seconds
Started Jun 22 04:39:09 PM PDT 24
Finished Jun 22 04:39:11 PM PDT 24
Peak memory 200552 kb
Host smart-1e6ca2a4-5a9c-456d-a128-51cdc6b5bf44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069867991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.4069867991
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.539257565
Short name T602
Test name
Test status
Simulation time 150033952 ps
CPU time 1.11 seconds
Started Jun 22 04:39:01 PM PDT 24
Finished Jun 22 04:39:03 PM PDT 24
Peak memory 200640 kb
Host smart-c94fd32d-bf99-4b22-a7d8-dd85cdc4610a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539257565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.539257565
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.958051501
Short name T619
Test name
Test status
Simulation time 473485620 ps
CPU time 3.45 seconds
Started Jun 22 04:39:14 PM PDT 24
Finished Jun 22 04:39:18 PM PDT 24
Peak memory 209040 kb
Host smart-ed41f742-3ac6-41e7-943c-7592de64db32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958051501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.958051501
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.488184901
Short name T117
Test name
Test status
Simulation time 122566668 ps
CPU time 0.99 seconds
Started Jun 22 04:39:04 PM PDT 24
Finished Jun 22 04:39:06 PM PDT 24
Peak memory 200664 kb
Host smart-b734f136-4826-44d5-baa1-1f63255b733e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488184901 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.488184901
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.763119360
Short name T587
Test name
Test status
Simulation time 55526964 ps
CPU time 0.82 seconds
Started Jun 22 04:38:56 PM PDT 24
Finished Jun 22 04:38:58 PM PDT 24
Peak memory 200556 kb
Host smart-788cda94-835a-4efe-bf21-efa0fed50bc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763119360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.763119360
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.4252664455
Short name T106
Test name
Test status
Simulation time 252905535 ps
CPU time 1.53 seconds
Started Jun 22 04:38:55 PM PDT 24
Finished Jun 22 04:38:57 PM PDT 24
Peak memory 200724 kb
Host smart-9e8fe3c0-7a12-41c2-8293-fc0be8c2e6e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252664455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.4252664455
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3760865865
Short name T589
Test name
Test status
Simulation time 274742830 ps
CPU time 2.18 seconds
Started Jun 22 04:39:03 PM PDT 24
Finished Jun 22 04:39:07 PM PDT 24
Peak memory 208992 kb
Host smart-1d1e5af3-ad8e-42d9-95b1-ed82e7366d0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760865865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3760865865
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.4119996497
Short name T113
Test name
Test status
Simulation time 417150900 ps
CPU time 1.84 seconds
Started Jun 22 04:39:02 PM PDT 24
Finished Jun 22 04:39:05 PM PDT 24
Peak memory 200884 kb
Host smart-9933df40-26ae-47ed-814d-4485fd4cc082
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119996497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.4119996497
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3811900977
Short name T577
Test name
Test status
Simulation time 116114989 ps
CPU time 1.06 seconds
Started Jun 22 04:39:05 PM PDT 24
Finished Jun 22 04:39:07 PM PDT 24
Peak memory 200712 kb
Host smart-034e6c52-9d76-4b1f-8322-544e6c5d609d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811900977 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3811900977
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.560096499
Short name T103
Test name
Test status
Simulation time 80151281 ps
CPU time 0.87 seconds
Started Jun 22 04:39:02 PM PDT 24
Finished Jun 22 04:39:04 PM PDT 24
Peak memory 200552 kb
Host smart-0c782552-eccd-438b-858b-915f4cf9dafe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560096499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.560096499
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1513854927
Short name T584
Test name
Test status
Simulation time 129204337 ps
CPU time 1.26 seconds
Started Jun 22 04:39:06 PM PDT 24
Finished Jun 22 04:39:08 PM PDT 24
Peak memory 200804 kb
Host smart-900df537-17c7-4fc0-8112-93aa9ab18a5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513854927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1513854927
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3415112305
Short name T566
Test name
Test status
Simulation time 161498906 ps
CPU time 2.34 seconds
Started Jun 22 04:39:20 PM PDT 24
Finished Jun 22 04:39:23 PM PDT 24
Peak memory 209048 kb
Host smart-9eef678d-d71b-486d-9c6f-dde0da0ea02b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415112305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3415112305
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1050351992
Short name T563
Test name
Test status
Simulation time 778377391 ps
CPU time 2.8 seconds
Started Jun 22 04:38:54 PM PDT 24
Finished Jun 22 04:38:58 PM PDT 24
Peak memory 200884 kb
Host smart-088140a6-ad18-41b6-a45f-afb22be0633a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050351992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1050351992
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3639714494
Short name T590
Test name
Test status
Simulation time 127694651 ps
CPU time 0.98 seconds
Started Jun 22 04:39:25 PM PDT 24
Finished Jun 22 04:39:27 PM PDT 24
Peak memory 200628 kb
Host smart-73918760-8af5-4f6c-aa5c-64dd387347b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639714494 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3639714494
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2232323921
Short name T580
Test name
Test status
Simulation time 72364782 ps
CPU time 0.79 seconds
Started Jun 22 04:39:02 PM PDT 24
Finished Jun 22 04:39:03 PM PDT 24
Peak memory 200652 kb
Host smart-2bb326ce-4377-43bf-8a67-a287da443af7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232323921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2232323921
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2172742392
Short name T552
Test name
Test status
Simulation time 249787248 ps
CPU time 1.6 seconds
Started Jun 22 04:39:03 PM PDT 24
Finished Jun 22 04:39:06 PM PDT 24
Peak memory 200748 kb
Host smart-895d003e-5e66-4385-827b-1dfb8ad52b26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172742392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2172742392
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.485875711
Short name T82
Test name
Test status
Simulation time 369039359 ps
CPU time 2.66 seconds
Started Jun 22 04:39:09 PM PDT 24
Finished Jun 22 04:39:13 PM PDT 24
Peak memory 209016 kb
Host smart-05db66c2-55a5-4825-8b50-926cece31f2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485875711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.485875711
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4138603731
Short name T567
Test name
Test status
Simulation time 492905921 ps
CPU time 2.05 seconds
Started Jun 22 04:39:07 PM PDT 24
Finished Jun 22 04:39:11 PM PDT 24
Peak memory 200900 kb
Host smart-7dd7db1a-245d-4a45-9c78-04fff5baaa17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138603731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.4138603731
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.438052722
Short name T83
Test name
Test status
Simulation time 213782901 ps
CPU time 1.33 seconds
Started Jun 22 04:39:03 PM PDT 24
Finished Jun 22 04:39:05 PM PDT 24
Peak memory 208896 kb
Host smart-7b18da15-68c6-4e63-a4a2-3d8547c225c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438052722 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.438052722
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3069254828
Short name T596
Test name
Test status
Simulation time 89165691 ps
CPU time 0.85 seconds
Started Jun 22 04:39:03 PM PDT 24
Finished Jun 22 04:39:05 PM PDT 24
Peak memory 200628 kb
Host smart-8539c9b2-1836-4017-9c5e-b604d6081bad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069254828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3069254828
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.875210319
Short name T598
Test name
Test status
Simulation time 208067019 ps
CPU time 1.42 seconds
Started Jun 22 04:39:11 PM PDT 24
Finished Jun 22 04:39:15 PM PDT 24
Peak memory 200896 kb
Host smart-a90e28bb-e0b5-4211-ad23-5173d2a29778
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875210319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.875210319
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1498844545
Short name T570
Test name
Test status
Simulation time 183081473 ps
CPU time 2.43 seconds
Started Jun 22 04:38:57 PM PDT 24
Finished Jun 22 04:39:00 PM PDT 24
Peak memory 208952 kb
Host smart-114b6d69-99e4-4a5f-a63c-c59c10dc02b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498844545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1498844545
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.121151403
Short name T593
Test name
Test status
Simulation time 197772611 ps
CPU time 1.23 seconds
Started Jun 22 04:39:12 PM PDT 24
Finished Jun 22 04:39:16 PM PDT 24
Peak memory 200720 kb
Host smart-cf160536-a5cc-447f-9803-91fbf01d2691
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121151403 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.121151403
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.127928057
Short name T583
Test name
Test status
Simulation time 56949694 ps
CPU time 0.76 seconds
Started Jun 22 04:39:11 PM PDT 24
Finished Jun 22 04:39:14 PM PDT 24
Peak memory 200488 kb
Host smart-784211e8-c01e-40be-98f7-6e6246167697
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127928057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.127928057
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3260759247
Short name T614
Test name
Test status
Simulation time 121693275 ps
CPU time 1.3 seconds
Started Jun 22 04:39:21 PM PDT 24
Finished Jun 22 04:39:24 PM PDT 24
Peak memory 200804 kb
Host smart-4fc5db2a-13ea-4e06-8d97-0b2d24c3506d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260759247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.3260759247
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1137952024
Short name T609
Test name
Test status
Simulation time 135332698 ps
CPU time 1.89 seconds
Started Jun 22 04:39:09 PM PDT 24
Finished Jun 22 04:39:12 PM PDT 24
Peak memory 209024 kb
Host smart-a8d89f70-6a41-43c4-80bb-a849dda2bf81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137952024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1137952024
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3806461939
Short name T60
Test name
Test status
Simulation time 176202368 ps
CPU time 1.15 seconds
Started Jun 22 04:38:59 PM PDT 24
Finished Jun 22 04:39:01 PM PDT 24
Peak memory 208760 kb
Host smart-35b8ee4e-ba14-4cc9-81c6-d76f752f125a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806461939 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3806461939
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.447057870
Short name T571
Test name
Test status
Simulation time 74784243 ps
CPU time 0.82 seconds
Started Jun 22 04:39:12 PM PDT 24
Finished Jun 22 04:39:15 PM PDT 24
Peak memory 200496 kb
Host smart-1c2d1f8e-f0bb-4b5f-bb5d-726b5472fb67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447057870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.447057870
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2574614195
Short name T550
Test name
Test status
Simulation time 74579730 ps
CPU time 0.98 seconds
Started Jun 22 04:38:58 PM PDT 24
Finished Jun 22 04:39:01 PM PDT 24
Peak memory 200528 kb
Host smart-16f617a5-90f7-4c7b-8b6e-0d57c342c22d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574614195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2574614195
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2822601158
Short name T574
Test name
Test status
Simulation time 178369538 ps
CPU time 2.55 seconds
Started Jun 22 04:39:12 PM PDT 24
Finished Jun 22 04:39:17 PM PDT 24
Peak memory 212636 kb
Host smart-0e107542-d167-4f13-982a-7a8496442c3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822601158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2822601158
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.4046447033
Short name T575
Test name
Test status
Simulation time 493160901 ps
CPU time 1.76 seconds
Started Jun 22 04:39:18 PM PDT 24
Finished Jun 22 04:39:21 PM PDT 24
Peak memory 200820 kb
Host smart-655a1265-56d8-4a08-ac8a-19e9fa3f5859
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046447033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.4046447033
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3028488863
Short name T118
Test name
Test status
Simulation time 129956730 ps
CPU time 1.5 seconds
Started Jun 22 04:39:14 PM PDT 24
Finished Jun 22 04:39:16 PM PDT 24
Peak memory 208960 kb
Host smart-f654874b-7faf-4ed4-858c-6e7354d05cd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028488863 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3028488863
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1613298059
Short name T612
Test name
Test status
Simulation time 63070360 ps
CPU time 0.8 seconds
Started Jun 22 04:39:08 PM PDT 24
Finished Jun 22 04:39:11 PM PDT 24
Peak memory 200652 kb
Host smart-dc1ee121-bc5b-4eb0-a4bd-ac8e926b9ea8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613298059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1613298059
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.955187749
Short name T556
Test name
Test status
Simulation time 83868681 ps
CPU time 0.94 seconds
Started Jun 22 04:39:32 PM PDT 24
Finished Jun 22 04:39:36 PM PDT 24
Peak memory 200540 kb
Host smart-8c343ce1-958a-4b09-92cf-b35684e34d17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955187749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.955187749
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.13959002
Short name T84
Test name
Test status
Simulation time 363905303 ps
CPU time 2.74 seconds
Started Jun 22 04:39:13 PM PDT 24
Finished Jun 22 04:39:17 PM PDT 24
Peak memory 209020 kb
Host smart-0d288571-395f-45bc-a243-952161722134
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13959002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.13959002
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1971569294
Short name T597
Test name
Test status
Simulation time 793403663 ps
CPU time 2.91 seconds
Started Jun 22 04:39:22 PM PDT 24
Finished Jun 22 04:39:26 PM PDT 24
Peak memory 200824 kb
Host smart-787b217f-de9e-4b69-9706-536bfebc3dbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971569294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.1971569294
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.554228187
Short name T56
Test name
Test status
Simulation time 149572995 ps
CPU time 1.89 seconds
Started Jun 22 04:38:55 PM PDT 24
Finished Jun 22 04:38:57 PM PDT 24
Peak memory 200712 kb
Host smart-f5cda4af-bd74-4a6b-b79f-aa35b3472bfc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554228187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.554228187
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3580597763
Short name T585
Test name
Test status
Simulation time 279784279 ps
CPU time 3.25 seconds
Started Jun 22 04:38:45 PM PDT 24
Finished Jun 22 04:38:49 PM PDT 24
Peak memory 200780 kb
Host smart-d41eaa27-9d4f-493f-a336-337beb268c3f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580597763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
580597763
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.4204780765
Short name T543
Test name
Test status
Simulation time 106036260 ps
CPU time 0.86 seconds
Started Jun 22 04:38:51 PM PDT 24
Finished Jun 22 04:38:52 PM PDT 24
Peak memory 200468 kb
Host smart-6aa49c03-ce76-49d8-92fc-acd4dfe57921
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204780765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.4
204780765
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.698755052
Short name T57
Test name
Test status
Simulation time 126985904 ps
CPU time 0.98 seconds
Started Jun 22 04:39:04 PM PDT 24
Finished Jun 22 04:39:06 PM PDT 24
Peak memory 200528 kb
Host smart-366a4dc1-885c-4a3a-baa5-ac0202f63ade
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698755052 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.698755052
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.363325385
Short name T58
Test name
Test status
Simulation time 79039802 ps
CPU time 0.82 seconds
Started Jun 22 04:38:49 PM PDT 24
Finished Jun 22 04:38:50 PM PDT 24
Peak memory 200836 kb
Host smart-f464d253-7eb1-4fb0-8f50-73a5ccc07ba7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363325385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.363325385
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1443325303
Short name T104
Test name
Test status
Simulation time 80080289 ps
CPU time 0.94 seconds
Started Jun 22 04:39:00 PM PDT 24
Finished Jun 22 04:39:02 PM PDT 24
Peak memory 200644 kb
Host smart-fb032244-9587-4624-99fc-c19418c144c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443325303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1443325303
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1711661340
Short name T611
Test name
Test status
Simulation time 276741271 ps
CPU time 1.83 seconds
Started Jun 22 04:38:44 PM PDT 24
Finished Jun 22 04:38:47 PM PDT 24
Peak memory 211436 kb
Host smart-8644cbf4-3deb-44f9-949f-1c5d9ff0d391
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711661340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1711661340
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1883717672
Short name T588
Test name
Test status
Simulation time 204955954 ps
CPU time 1.5 seconds
Started Jun 22 04:38:54 PM PDT 24
Finished Jun 22 04:38:57 PM PDT 24
Peak memory 209404 kb
Host smart-24af31f3-5102-4e34-aff2-92122350fa39
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883717672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
883717672
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2765797746
Short name T578
Test name
Test status
Simulation time 1017340278 ps
CPU time 4.81 seconds
Started Jun 22 04:38:57 PM PDT 24
Finished Jun 22 04:39:03 PM PDT 24
Peak memory 200824 kb
Host smart-b0aed966-89db-4f1e-9a8c-d5596f8db155
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765797746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
765797746
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4215317300
Short name T546
Test name
Test status
Simulation time 145866703 ps
CPU time 0.97 seconds
Started Jun 22 04:38:45 PM PDT 24
Finished Jun 22 04:38:47 PM PDT 24
Peak memory 200724 kb
Host smart-65750448-49c0-4793-aec3-78bb131e6509
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215317300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.4
215317300
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3392083062
Short name T116
Test name
Test status
Simulation time 183114866 ps
CPU time 1.16 seconds
Started Jun 22 04:39:04 PM PDT 24
Finished Jun 22 04:39:06 PM PDT 24
Peak memory 208816 kb
Host smart-665f56c5-9650-4f04-acfd-601ea78d71e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392083062 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3392083062
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3125787047
Short name T557
Test name
Test status
Simulation time 90607126 ps
CPU time 0.9 seconds
Started Jun 22 04:38:40 PM PDT 24
Finished Jun 22 04:38:42 PM PDT 24
Peak memory 200908 kb
Host smart-58f98428-a22a-4f1b-920c-548993e01f7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125787047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3125787047
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1740490005
Short name T615
Test name
Test status
Simulation time 130397017 ps
CPU time 1.25 seconds
Started Jun 22 04:39:08 PM PDT 24
Finished Jun 22 04:39:11 PM PDT 24
Peak memory 200772 kb
Host smart-aaf746c8-2746-478b-82f9-67644401dc86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740490005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1740490005
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3226950085
Short name T606
Test name
Test status
Simulation time 185030539 ps
CPU time 2.87 seconds
Started Jun 22 04:38:51 PM PDT 24
Finished Jun 22 04:38:54 PM PDT 24
Peak memory 217480 kb
Host smart-73a93b93-b7b8-4684-a76f-0a893effddf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226950085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3226950085
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.539223793
Short name T607
Test name
Test status
Simulation time 423652084 ps
CPU time 1.73 seconds
Started Jun 22 04:38:54 PM PDT 24
Finished Jun 22 04:38:57 PM PDT 24
Peak memory 200812 kb
Host smart-90bd9b0a-ed66-455f-a8ef-a80f3eb0ebb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539223793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.
539223793
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3427792355
Short name T544
Test name
Test status
Simulation time 112785754 ps
CPU time 1.37 seconds
Started Jun 22 04:39:08 PM PDT 24
Finished Jun 22 04:39:11 PM PDT 24
Peak memory 209004 kb
Host smart-485a11db-6083-4e24-88b2-5f302a35d23e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427792355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
427792355
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3764871371
Short name T581
Test name
Test status
Simulation time 270232079 ps
CPU time 3.07 seconds
Started Jun 22 04:39:10 PM PDT 24
Finished Jun 22 04:39:16 PM PDT 24
Peak memory 200880 kb
Host smart-16818bab-a21d-43b6-84be-f65352ee1037
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764871371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3
764871371
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.4057550014
Short name T547
Test name
Test status
Simulation time 103956745 ps
CPU time 0.83 seconds
Started Jun 22 04:38:56 PM PDT 24
Finished Jun 22 04:38:58 PM PDT 24
Peak memory 200604 kb
Host smart-19aa1f8a-6ec2-448b-a2fa-3d6b311cdb1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057550014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.4
057550014
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1202236151
Short name T85
Test name
Test status
Simulation time 111612257 ps
CPU time 0.99 seconds
Started Jun 22 04:39:07 PM PDT 24
Finished Jun 22 04:39:10 PM PDT 24
Peak memory 200612 kb
Host smart-52ec2e07-9fdb-4ad0-8052-bbe7e620c169
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202236151 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1202236151
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.869279504
Short name T108
Test name
Test status
Simulation time 68735945 ps
CPU time 0.78 seconds
Started Jun 22 04:39:06 PM PDT 24
Finished Jun 22 04:39:08 PM PDT 24
Peak memory 200496 kb
Host smart-ff1ca97b-6e41-4261-b1d8-ca9a9fefb2d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869279504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.869279504
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3835019487
Short name T110
Test name
Test status
Simulation time 231199003 ps
CPU time 1.38 seconds
Started Jun 22 04:38:58 PM PDT 24
Finished Jun 22 04:39:01 PM PDT 24
Peak memory 200724 kb
Host smart-122f3c47-4d6d-40a4-8fdd-77420a740e06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835019487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3835019487
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.746616111
Short name T115
Test name
Test status
Simulation time 146408049 ps
CPU time 2.11 seconds
Started Jun 22 04:39:08 PM PDT 24
Finished Jun 22 04:39:12 PM PDT 24
Peak memory 211980 kb
Host smart-8cbf43d6-7857-4f7e-adaa-e6794202ff35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746616111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.746616111
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1380261357
Short name T558
Test name
Test status
Simulation time 480487279 ps
CPU time 1.78 seconds
Started Jun 22 04:38:44 PM PDT 24
Finished Jun 22 04:38:47 PM PDT 24
Peak memory 200912 kb
Host smart-92893325-d1af-49ce-92f1-94907a9841ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380261357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1380261357
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3406495745
Short name T572
Test name
Test status
Simulation time 125665080 ps
CPU time 1.3 seconds
Started Jun 22 04:39:11 PM PDT 24
Finished Jun 22 04:39:15 PM PDT 24
Peak memory 208628 kb
Host smart-abcce64b-a33f-4bb1-af1e-e34c8e466794
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406495745 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3406495745
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1848368997
Short name T617
Test name
Test status
Simulation time 75320050 ps
CPU time 0.8 seconds
Started Jun 22 04:39:17 PM PDT 24
Finished Jun 22 04:39:19 PM PDT 24
Peak memory 200628 kb
Host smart-402357b9-6eb0-43f9-a5a3-7fb2a08ccaab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848368997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1848368997
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2507165161
Short name T605
Test name
Test status
Simulation time 84116331 ps
CPU time 0.94 seconds
Started Jun 22 04:39:10 PM PDT 24
Finished Jun 22 04:39:13 PM PDT 24
Peak memory 199672 kb
Host smart-46bd3226-1754-4d8b-9069-cb0e6c933b1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507165161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.2507165161
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2961160271
Short name T613
Test name
Test status
Simulation time 136950659 ps
CPU time 1.82 seconds
Started Jun 22 04:39:04 PM PDT 24
Finished Jun 22 04:39:07 PM PDT 24
Peak memory 208928 kb
Host smart-8371f302-5061-47ea-8e17-172d54540b25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961160271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2961160271
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1052049729
Short name T87
Test name
Test status
Simulation time 421859729 ps
CPU time 1.62 seconds
Started Jun 22 04:39:04 PM PDT 24
Finished Jun 22 04:39:07 PM PDT 24
Peak memory 200740 kb
Host smart-5d695b2b-fede-4a6d-8d05-d1ecafff0154
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052049729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1052049729
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3980194288
Short name T592
Test name
Test status
Simulation time 113522046 ps
CPU time 1.06 seconds
Started Jun 22 04:39:08 PM PDT 24
Finished Jun 22 04:39:11 PM PDT 24
Peak memory 208916 kb
Host smart-2bf4fd57-77e3-42f9-88ba-8978647c1f18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980194288 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.3980194288
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3748418409
Short name T599
Test name
Test status
Simulation time 76190652 ps
CPU time 0.85 seconds
Started Jun 22 04:39:03 PM PDT 24
Finished Jun 22 04:39:05 PM PDT 24
Peak memory 200552 kb
Host smart-25b31cd7-8c6a-4248-a2b1-3e9cdf1e6342
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748418409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3748418409
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4164638492
Short name T582
Test name
Test status
Simulation time 123449397 ps
CPU time 1.04 seconds
Started Jun 22 04:39:07 PM PDT 24
Finished Jun 22 04:39:10 PM PDT 24
Peak memory 200548 kb
Host smart-fc9220ce-be79-40f3-a3a9-9ddbf4e56673
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164638492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.4164638492
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.950299059
Short name T553
Test name
Test status
Simulation time 193791506 ps
CPU time 2.63 seconds
Started Jun 22 04:39:11 PM PDT 24
Finished Jun 22 04:39:16 PM PDT 24
Peak memory 211876 kb
Host smart-7dbdf817-738f-481e-b9e1-d983274914a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950299059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.950299059
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1134040424
Short name T620
Test name
Test status
Simulation time 498703867 ps
CPU time 2.17 seconds
Started Jun 22 04:39:06 PM PDT 24
Finished Jun 22 04:39:09 PM PDT 24
Peak memory 200812 kb
Host smart-2445eb9c-b7fb-495a-abe6-d79ce0b217e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134040424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.1134040424
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2686805548
Short name T591
Test name
Test status
Simulation time 185332977 ps
CPU time 1.24 seconds
Started Jun 22 04:39:06 PM PDT 24
Finished Jun 22 04:39:09 PM PDT 24
Peak memory 208916 kb
Host smart-5c05c8a4-a49f-4bd6-8ac2-e30eae368d6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686805548 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2686805548
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.877091449
Short name T616
Test name
Test status
Simulation time 95576284 ps
CPU time 0.89 seconds
Started Jun 22 04:39:11 PM PDT 24
Finished Jun 22 04:39:15 PM PDT 24
Peak memory 200640 kb
Host smart-979d9403-a20e-4a35-9b8b-60ec182b7c25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877091449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.877091449
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.4091004552
Short name T55
Test name
Test status
Simulation time 226363358 ps
CPU time 1.58 seconds
Started Jun 22 04:38:57 PM PDT 24
Finished Jun 22 04:38:59 PM PDT 24
Peak memory 200776 kb
Host smart-3d04da5b-5e2e-47b2-8725-19ee4765aff0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091004552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.4091004552
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1163607107
Short name T111
Test name
Test status
Simulation time 116818575 ps
CPU time 1.67 seconds
Started Jun 22 04:39:01 PM PDT 24
Finished Jun 22 04:39:04 PM PDT 24
Peak memory 208948 kb
Host smart-586e9a32-0279-4142-bcf6-c31ad76e5600
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163607107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1163607107
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2890159716
Short name T89
Test name
Test status
Simulation time 489196737 ps
CPU time 1.95 seconds
Started Jun 22 04:39:00 PM PDT 24
Finished Jun 22 04:39:03 PM PDT 24
Peak memory 200812 kb
Host smart-004926bf-395e-4fb3-a0cc-3e553ecd27dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890159716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.2890159716
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.774562380
Short name T603
Test name
Test status
Simulation time 171154887 ps
CPU time 1.22 seconds
Started Jun 22 04:39:03 PM PDT 24
Finished Jun 22 04:39:05 PM PDT 24
Peak memory 210448 kb
Host smart-f9c72a61-b3a9-4395-b0c0-6f67b28d6a22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774562380 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.774562380
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3723604306
Short name T568
Test name
Test status
Simulation time 83775283 ps
CPU time 0.84 seconds
Started Jun 22 04:39:10 PM PDT 24
Finished Jun 22 04:39:13 PM PDT 24
Peak memory 199596 kb
Host smart-b6179508-04f0-4b0a-8d77-3c5e57ef85b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723604306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3723604306
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1103109662
Short name T564
Test name
Test status
Simulation time 134904281 ps
CPU time 1.29 seconds
Started Jun 22 04:39:30 PM PDT 24
Finished Jun 22 04:39:33 PM PDT 24
Peak memory 200748 kb
Host smart-6250cb05-fb71-4117-ad67-b9c444e45e76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103109662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.1103109662
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3710432447
Short name T608
Test name
Test status
Simulation time 467323107 ps
CPU time 3.16 seconds
Started Jun 22 04:38:58 PM PDT 24
Finished Jun 22 04:39:02 PM PDT 24
Peak memory 208944 kb
Host smart-cba5bd51-69cd-4e42-b096-058a9eb9b6ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710432447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3710432447
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3269356117
Short name T560
Test name
Test status
Simulation time 133191939 ps
CPU time 1.03 seconds
Started Jun 22 04:39:05 PM PDT 24
Finished Jun 22 04:39:07 PM PDT 24
Peak memory 200688 kb
Host smart-a17957d1-f0b0-49a2-a484-e1d5c0882f06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269356117 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3269356117
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.885706911
Short name T102
Test name
Test status
Simulation time 71946476 ps
CPU time 0.83 seconds
Started Jun 22 04:39:04 PM PDT 24
Finished Jun 22 04:39:06 PM PDT 24
Peak memory 200540 kb
Host smart-f06c385e-6b22-4f1e-87fd-f30ce8818128
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885706911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.885706911
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1387481569
Short name T551
Test name
Test status
Simulation time 130868668 ps
CPU time 1.06 seconds
Started Jun 22 04:38:56 PM PDT 24
Finished Jun 22 04:38:58 PM PDT 24
Peak memory 200564 kb
Host smart-1fd81d33-3492-4c20-8f4b-2ea8626af2bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387481569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1387481569
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2957198476
Short name T555
Test name
Test status
Simulation time 441369142 ps
CPU time 3.13 seconds
Started Jun 22 04:39:11 PM PDT 24
Finished Jun 22 04:39:17 PM PDT 24
Peak memory 208924 kb
Host smart-3fea47a5-39ce-454a-8bb5-eb98843c77f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957198476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2957198476
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2824358095
Short name T122
Test name
Test status
Simulation time 831287422 ps
CPU time 2.83 seconds
Started Jun 22 04:39:02 PM PDT 24
Finished Jun 22 04:39:06 PM PDT 24
Peak memory 200812 kb
Host smart-0a32045c-1c05-49c9-bb56-f77e950d03cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824358095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.2824358095
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.833121459
Short name T540
Test name
Test status
Simulation time 74902356 ps
CPU time 0.83 seconds
Started Jun 22 04:58:13 PM PDT 24
Finished Jun 22 04:58:14 PM PDT 24
Peak memory 200444 kb
Host smart-0455a950-023f-4186-a778-3d3ee75bc276
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833121459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.833121459
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2135984304
Short name T39
Test name
Test status
Simulation time 1878504488 ps
CPU time 6.97 seconds
Started Jun 22 04:58:08 PM PDT 24
Finished Jun 22 04:58:15 PM PDT 24
Peak memory 230596 kb
Host smart-6438b570-0a5b-4ffe-bb46-63ac6f4d4e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135984304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2135984304
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.4262855005
Short name T386
Test name
Test status
Simulation time 244166366 ps
CPU time 1.05 seconds
Started Jun 22 04:58:12 PM PDT 24
Finished Jun 22 04:58:14 PM PDT 24
Peak memory 218084 kb
Host smart-a9d2e9a4-968d-4468-8f8e-425d64f7b372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262855005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.4262855005
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1355965414
Short name T419
Test name
Test status
Simulation time 80158059 ps
CPU time 0.8 seconds
Started Jun 22 04:58:05 PM PDT 24
Finished Jun 22 04:58:06 PM PDT 24
Peak memory 200488 kb
Host smart-62f7d92d-edd4-4ffc-9600-5a02f3011ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355965414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1355965414
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.270428012
Short name T94
Test name
Test status
Simulation time 1793039242 ps
CPU time 6.66 seconds
Started Jun 22 04:58:05 PM PDT 24
Finished Jun 22 04:58:12 PM PDT 24
Peak memory 200824 kb
Host smart-1600d03a-5a5a-4f97-8381-6ee7e9b28ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270428012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.270428012
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2403775190
Short name T311
Test name
Test status
Simulation time 109696316 ps
CPU time 1 seconds
Started Jun 22 04:58:08 PM PDT 24
Finished Jun 22 04:58:10 PM PDT 24
Peak memory 200708 kb
Host smart-0d56d007-a877-41be-88d4-a1a7714779a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403775190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2403775190
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.3860929311
Short name T280
Test name
Test status
Simulation time 252565850 ps
CPU time 1.53 seconds
Started Jun 22 04:58:06 PM PDT 24
Finished Jun 22 04:58:08 PM PDT 24
Peak memory 200876 kb
Host smart-4767e32f-ea06-4be3-84ed-8cea98650617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860929311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3860929311
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.786588708
Short name T137
Test name
Test status
Simulation time 357030599 ps
CPU time 1.76 seconds
Started Jun 22 04:58:12 PM PDT 24
Finished Jun 22 04:58:15 PM PDT 24
Peak memory 200892 kb
Host smart-531c0552-c35c-4d33-a909-18dff5dfed6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786588708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.786588708
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2049725941
Short name T265
Test name
Test status
Simulation time 113073689 ps
CPU time 1.39 seconds
Started Jun 22 04:58:07 PM PDT 24
Finished Jun 22 04:58:08 PM PDT 24
Peak memory 200716 kb
Host smart-2a9e004e-5c21-4ba9-9807-a6f4de0a6760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049725941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2049725941
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2466546212
Short name T316
Test name
Test status
Simulation time 147275173 ps
CPU time 1.27 seconds
Started Jun 22 04:58:04 PM PDT 24
Finished Jun 22 04:58:06 PM PDT 24
Peak memory 200724 kb
Host smart-cac00e9a-e2d2-4eb5-aabd-39344840b663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466546212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2466546212
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3069083995
Short name T427
Test name
Test status
Simulation time 69831937 ps
CPU time 0.79 seconds
Started Jun 22 04:58:15 PM PDT 24
Finished Jun 22 04:58:17 PM PDT 24
Peak memory 200424 kb
Host smart-49d2ed0a-f6fe-4574-8c75-049c46fc1880
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069083995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3069083995
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3067470882
Short name T313
Test name
Test status
Simulation time 1898706530 ps
CPU time 7.12 seconds
Started Jun 22 04:58:15 PM PDT 24
Finished Jun 22 04:58:23 PM PDT 24
Peak memory 222468 kb
Host smart-5d3dbeb2-53bb-4c7e-8ad3-d424c746f6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067470882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3067470882
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1485796131
Short name T449
Test name
Test status
Simulation time 244568649 ps
CPU time 1.08 seconds
Started Jun 22 04:58:14 PM PDT 24
Finished Jun 22 04:58:16 PM PDT 24
Peak memory 218100 kb
Host smart-fdaaf2f4-d256-49d2-9fdf-6bc010d6f821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485796131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1485796131
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2855274437
Short name T282
Test name
Test status
Simulation time 876336976 ps
CPU time 4.03 seconds
Started Jun 22 04:58:12 PM PDT 24
Finished Jun 22 04:58:16 PM PDT 24
Peak memory 200868 kb
Host smart-6d5b2cfc-0262-47fa-8e7d-8d86f2de755a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855274437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2855274437
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1292178360
Short name T65
Test name
Test status
Simulation time 8366844383 ps
CPU time 13.61 seconds
Started Jun 22 04:58:15 PM PDT 24
Finished Jun 22 04:58:30 PM PDT 24
Peak memory 217616 kb
Host smart-976e9c4d-bc1c-476a-91c0-dee06a112c91
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292178360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1292178360
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1562226093
Short name T200
Test name
Test status
Simulation time 193409508 ps
CPU time 1.46 seconds
Started Jun 22 04:58:12 PM PDT 24
Finished Jun 22 04:58:15 PM PDT 24
Peak memory 200844 kb
Host smart-cc6d74a5-dcd3-4d20-bbbb-daa9e4324fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562226093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1562226093
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1719496573
Short name T466
Test name
Test status
Simulation time 4384972803 ps
CPU time 16.66 seconds
Started Jun 22 04:58:13 PM PDT 24
Finished Jun 22 04:58:30 PM PDT 24
Peak memory 217292 kb
Host smart-5e008e95-4040-4d8f-a5b4-c3f980ba08d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719496573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1719496573
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.1486216561
Short name T155
Test name
Test status
Simulation time 144287272 ps
CPU time 1.85 seconds
Started Jun 22 04:58:11 PM PDT 24
Finished Jun 22 04:58:13 PM PDT 24
Peak memory 200924 kb
Host smart-cc8421fd-4977-4c93-8f96-58f6de8e3480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486216561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1486216561
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3177693999
Short name T317
Test name
Test status
Simulation time 59996372 ps
CPU time 0.83 seconds
Started Jun 22 04:58:29 PM PDT 24
Finished Jun 22 04:58:31 PM PDT 24
Peak memory 200492 kb
Host smart-398cea56-c05d-4ce6-bb98-ded6b6eb7895
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177693999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3177693999
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1178401081
Short name T341
Test name
Test status
Simulation time 2173511521 ps
CPU time 8.5 seconds
Started Jun 22 04:58:28 PM PDT 24
Finished Jun 22 04:58:37 PM PDT 24
Peak memory 218620 kb
Host smart-702d8f52-3755-44c0-ba6a-50e89ffd0827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178401081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1178401081
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.683317851
Short name T216
Test name
Test status
Simulation time 244579466 ps
CPU time 1.02 seconds
Started Jun 22 04:58:27 PM PDT 24
Finished Jun 22 04:58:28 PM PDT 24
Peak memory 218024 kb
Host smart-4be99f84-b7fb-48d5-9fae-67af812fa001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683317851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.683317851
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.4211759422
Short name T529
Test name
Test status
Simulation time 210654752 ps
CPU time 0.95 seconds
Started Jun 22 04:58:27 PM PDT 24
Finished Jun 22 04:58:29 PM PDT 24
Peak memory 200488 kb
Host smart-b6a355aa-7d76-48e2-a242-c683a06c4783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211759422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.4211759422
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3017868603
Short name T381
Test name
Test status
Simulation time 103028786 ps
CPU time 0.99 seconds
Started Jun 22 04:58:40 PM PDT 24
Finished Jun 22 04:58:42 PM PDT 24
Peak memory 200728 kb
Host smart-07ce6c4d-496f-4de2-9295-5d7f13789eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017868603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3017868603
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.3676802134
Short name T533
Test name
Test status
Simulation time 120191134 ps
CPU time 1.31 seconds
Started Jun 22 04:58:28 PM PDT 24
Finished Jun 22 04:58:31 PM PDT 24
Peak memory 200872 kb
Host smart-6046e6fa-b56a-4eff-ba66-843c66714194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676802134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3676802134
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2485835407
Short name T495
Test name
Test status
Simulation time 7990722275 ps
CPU time 28.52 seconds
Started Jun 22 04:58:30 PM PDT 24
Finished Jun 22 04:58:59 PM PDT 24
Peak memory 209096 kb
Host smart-a7d26383-1883-4e39-ab0f-8f36f3694693
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485835407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2485835407
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.883917980
Short name T144
Test name
Test status
Simulation time 438877170 ps
CPU time 2.39 seconds
Started Jun 22 04:58:32 PM PDT 24
Finished Jun 22 04:58:35 PM PDT 24
Peak memory 208876 kb
Host smart-015e014f-2e79-4ad6-a55b-beb1650e0bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883917980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.883917980
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3627384228
Short name T180
Test name
Test status
Simulation time 120288602 ps
CPU time 1 seconds
Started Jun 22 04:58:28 PM PDT 24
Finished Jun 22 04:58:30 PM PDT 24
Peak memory 200728 kb
Host smart-69f1d4f3-a2b6-4220-ab3c-2ec9d81c6e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627384228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3627384228
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.4224382788
Short name T377
Test name
Test status
Simulation time 71029498 ps
CPU time 0.8 seconds
Started Jun 22 04:58:27 PM PDT 24
Finished Jun 22 04:58:29 PM PDT 24
Peak memory 200492 kb
Host smart-bc37afff-26f9-4494-83fd-10927b33ec06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224382788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.4224382788
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2830856307
Short name T37
Test name
Test status
Simulation time 2186056139 ps
CPU time 7.52 seconds
Started Jun 22 04:58:38 PM PDT 24
Finished Jun 22 04:58:47 PM PDT 24
Peak memory 218260 kb
Host smart-c869eb63-ad9a-4ccb-9a42-6867aeca58f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830856307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2830856307
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1945997206
Short name T411
Test name
Test status
Simulation time 243986110 ps
CPU time 1.07 seconds
Started Jun 22 04:58:27 PM PDT 24
Finished Jun 22 04:58:29 PM PDT 24
Peak memory 218024 kb
Host smart-8e1d3213-20c2-41ff-8f10-fb095d7b9e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945997206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1945997206
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2922391369
Short name T250
Test name
Test status
Simulation time 122284703 ps
CPU time 0.76 seconds
Started Jun 22 04:58:28 PM PDT 24
Finished Jun 22 04:58:29 PM PDT 24
Peak memory 200512 kb
Host smart-8d730776-8f4a-4aa0-bd89-fc86891a7876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922391369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2922391369
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.279578472
Short name T1
Test name
Test status
Simulation time 1576331203 ps
CPU time 5.28 seconds
Started Jun 22 04:58:39 PM PDT 24
Finished Jun 22 04:58:45 PM PDT 24
Peak memory 200884 kb
Host smart-8da49f3c-6c3b-4c3e-9a18-82a8d5799328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279578472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.279578472
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2165961946
Short name T224
Test name
Test status
Simulation time 172899118 ps
CPU time 1.22 seconds
Started Jun 22 04:58:28 PM PDT 24
Finished Jun 22 04:58:29 PM PDT 24
Peak memory 200720 kb
Host smart-1fbc8611-5aab-46e0-8e53-4c7c9dd660a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165961946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2165961946
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.703282318
Short name T266
Test name
Test status
Simulation time 236657111 ps
CPU time 1.55 seconds
Started Jun 22 04:58:32 PM PDT 24
Finished Jun 22 04:58:34 PM PDT 24
Peak memory 200868 kb
Host smart-a08390e9-fa88-485b-8dc7-2971fccc687b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703282318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.703282318
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2838242153
Short name T357
Test name
Test status
Simulation time 3970098626 ps
CPU time 14.02 seconds
Started Jun 22 04:58:30 PM PDT 24
Finished Jun 22 04:58:45 PM PDT 24
Peak memory 200992 kb
Host smart-8e0d487d-6547-4b55-b9c1-8117d72dedde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838242153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2838242153
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2894714948
Short name T382
Test name
Test status
Simulation time 351157735 ps
CPU time 2.36 seconds
Started Jun 22 04:58:26 PM PDT 24
Finished Jun 22 04:58:29 PM PDT 24
Peak memory 200672 kb
Host smart-b9abe885-5e6d-403a-9534-a9f6a18e6ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894714948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2894714948
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2529490550
Short name T233
Test name
Test status
Simulation time 125903405 ps
CPU time 1.08 seconds
Started Jun 22 04:58:29 PM PDT 24
Finished Jun 22 04:58:31 PM PDT 24
Peak memory 200724 kb
Host smart-131e7552-5eeb-4111-a512-b41d493f0e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529490550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2529490550
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1080229393
Short name T166
Test name
Test status
Simulation time 71905261 ps
CPU time 0.84 seconds
Started Jun 22 04:58:37 PM PDT 24
Finished Jun 22 04:58:39 PM PDT 24
Peak memory 200512 kb
Host smart-7028b5c0-8ba8-4306-8524-f5472b232cab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080229393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1080229393
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2536814414
Short name T491
Test name
Test status
Simulation time 1871871227 ps
CPU time 7.2 seconds
Started Jun 22 04:58:37 PM PDT 24
Finished Jun 22 04:58:45 PM PDT 24
Peak memory 222408 kb
Host smart-c0a6f1fb-14dd-4dc8-9a80-aa85b9cbaf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536814414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2536814414
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.258808716
Short name T432
Test name
Test status
Simulation time 244243821 ps
CPU time 1.22 seconds
Started Jun 22 04:58:37 PM PDT 24
Finished Jun 22 04:58:40 PM PDT 24
Peak memory 218076 kb
Host smart-09a4fd3d-ff2e-4841-b095-d2f45a94e733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258808716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.258808716
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.1412074024
Short name T281
Test name
Test status
Simulation time 120285089 ps
CPU time 0.8 seconds
Started Jun 22 04:58:29 PM PDT 24
Finished Jun 22 04:58:31 PM PDT 24
Peak memory 200492 kb
Host smart-59a7fa2b-ae03-457a-8e20-094a24f7d737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412074024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1412074024
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3333601796
Short name T501
Test name
Test status
Simulation time 903005960 ps
CPU time 4.94 seconds
Started Jun 22 04:58:39 PM PDT 24
Finished Jun 22 04:58:45 PM PDT 24
Peak memory 200904 kb
Host smart-85320e6c-971f-4137-a9c8-cedeccb4e861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333601796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3333601796
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.60270636
Short name T345
Test name
Test status
Simulation time 99111754 ps
CPU time 0.98 seconds
Started Jun 22 04:58:37 PM PDT 24
Finished Jun 22 04:58:40 PM PDT 24
Peak memory 200728 kb
Host smart-5731f058-2ea1-46ee-9b39-cae46edd53ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60270636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.60270636
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.264706473
Short name T464
Test name
Test status
Simulation time 194399763 ps
CPU time 1.37 seconds
Started Jun 22 04:58:27 PM PDT 24
Finished Jun 22 04:58:29 PM PDT 24
Peak memory 200864 kb
Host smart-27e593c4-5f65-405f-8a2e-54768d5037c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264706473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.264706473
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2084098031
Short name T69
Test name
Test status
Simulation time 3792484912 ps
CPU time 14.41 seconds
Started Jun 22 04:58:38 PM PDT 24
Finished Jun 22 04:58:53 PM PDT 24
Peak memory 209152 kb
Host smart-cdacfb18-0469-4fba-b68d-c95a7478ffdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084098031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2084098031
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.815315615
Short name T374
Test name
Test status
Simulation time 110486547 ps
CPU time 1.43 seconds
Started Jun 22 04:58:37 PM PDT 24
Finished Jun 22 04:58:40 PM PDT 24
Peak memory 200644 kb
Host smart-e7e7174e-3176-41a8-aaa8-8005676a160d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815315615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.815315615
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2401025633
Short name T327
Test name
Test status
Simulation time 102317860 ps
CPU time 0.93 seconds
Started Jun 22 04:58:36 PM PDT 24
Finished Jun 22 04:58:37 PM PDT 24
Peak memory 200704 kb
Host smart-c8074621-68f3-4a94-bbde-e5b028bb0f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401025633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2401025633
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3247171652
Short name T244
Test name
Test status
Simulation time 1903256711 ps
CPU time 7.67 seconds
Started Jun 22 04:58:39 PM PDT 24
Finished Jun 22 04:58:48 PM PDT 24
Peak memory 217464 kb
Host smart-ac63768e-e21c-4957-ad7e-eb2054c2711d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247171652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3247171652
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3258225872
Short name T221
Test name
Test status
Simulation time 244031510 ps
CPU time 1.16 seconds
Started Jun 22 04:58:36 PM PDT 24
Finished Jun 22 04:58:39 PM PDT 24
Peak memory 218168 kb
Host smart-179ed332-e009-4df6-8948-6129115a62be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258225872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.3258225872
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3706384817
Short name T19
Test name
Test status
Simulation time 215442221 ps
CPU time 0.98 seconds
Started Jun 22 04:58:36 PM PDT 24
Finished Jun 22 04:58:37 PM PDT 24
Peak memory 200436 kb
Host smart-6ea9710a-b267-49b4-9997-37af27a1dc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706384817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3706384817
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.711928708
Short name T412
Test name
Test status
Simulation time 1662089810 ps
CPU time 6.19 seconds
Started Jun 22 04:58:34 PM PDT 24
Finished Jun 22 04:58:41 PM PDT 24
Peak memory 200880 kb
Host smart-c6fadecd-3755-459b-9d13-bcd9facde7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711928708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.711928708
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.905416568
Short name T400
Test name
Test status
Simulation time 96659239 ps
CPU time 1.01 seconds
Started Jun 22 04:58:41 PM PDT 24
Finished Jun 22 04:58:42 PM PDT 24
Peak memory 200688 kb
Host smart-8a19b1f2-d5e9-4826-8e4a-5d66880466ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905416568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.905416568
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.535036219
Short name T509
Test name
Test status
Simulation time 194327010 ps
CPU time 1.49 seconds
Started Jun 22 04:58:35 PM PDT 24
Finished Jun 22 04:58:37 PM PDT 24
Peak memory 200880 kb
Host smart-c7aa0a3e-261e-4e4e-a974-da961482a192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535036219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.535036219
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.4110826393
Short name T538
Test name
Test status
Simulation time 3163050837 ps
CPU time 11.38 seconds
Started Jun 22 04:58:37 PM PDT 24
Finished Jun 22 04:58:49 PM PDT 24
Peak memory 200948 kb
Host smart-c7978de3-791f-4625-a74b-28ca9fcaadb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110826393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.4110826393
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2306880729
Short name T325
Test name
Test status
Simulation time 146152506 ps
CPU time 1.84 seconds
Started Jun 22 04:58:37 PM PDT 24
Finished Jun 22 04:58:40 PM PDT 24
Peak memory 200704 kb
Host smart-54181449-c93d-4333-a057-5e2396937ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306880729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2306880729
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3651393293
Short name T72
Test name
Test status
Simulation time 166500359 ps
CPU time 1.1 seconds
Started Jun 22 04:58:36 PM PDT 24
Finished Jun 22 04:58:38 PM PDT 24
Peak memory 200628 kb
Host smart-ab259016-8c78-429a-8def-4f4b21f8a82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651393293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3651393293
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.2313672610
Short name T493
Test name
Test status
Simulation time 53457832 ps
CPU time 0.75 seconds
Started Jun 22 04:58:37 PM PDT 24
Finished Jun 22 04:58:39 PM PDT 24
Peak memory 200508 kb
Host smart-954df6e8-10a4-4cba-9a21-f6075809ddce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313672610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2313672610
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2902127539
Short name T505
Test name
Test status
Simulation time 1909875356 ps
CPU time 7.82 seconds
Started Jun 22 04:58:38 PM PDT 24
Finished Jun 22 04:58:47 PM PDT 24
Peak memory 222440 kb
Host smart-d994ba6b-323a-45cf-b261-6e882cd57df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902127539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2902127539
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2448532354
Short name T129
Test name
Test status
Simulation time 245113137 ps
CPU time 1.04 seconds
Started Jun 22 04:58:35 PM PDT 24
Finished Jun 22 04:58:36 PM PDT 24
Peak memory 218104 kb
Host smart-19800f3b-c14b-4cb2-bb7c-8539f512a31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448532354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2448532354
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2400185607
Short name T246
Test name
Test status
Simulation time 132708213 ps
CPU time 0.82 seconds
Started Jun 22 04:58:39 PM PDT 24
Finished Jun 22 04:58:41 PM PDT 24
Peak memory 200512 kb
Host smart-021f39ce-2edf-4727-a09f-6ab4db9e88a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400185607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2400185607
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3611312065
Short name T189
Test name
Test status
Simulation time 885491402 ps
CPU time 5.03 seconds
Started Jun 22 04:58:41 PM PDT 24
Finished Jun 22 04:58:46 PM PDT 24
Peak memory 200892 kb
Host smart-3b7aca0d-bfc8-43b0-ac50-612c66a82edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611312065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3611312065
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1607195991
Short name T41
Test name
Test status
Simulation time 95441772 ps
CPU time 1.03 seconds
Started Jun 22 04:58:40 PM PDT 24
Finished Jun 22 04:58:42 PM PDT 24
Peak memory 200704 kb
Host smart-79911fe6-60b3-4697-ad4d-025fb27eab06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607195991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1607195991
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2238981574
Short name T194
Test name
Test status
Simulation time 113107246 ps
CPU time 1.18 seconds
Started Jun 22 04:58:38 PM PDT 24
Finished Jun 22 04:58:40 PM PDT 24
Peak memory 200912 kb
Host smart-1ff0fac4-2584-4876-b2d8-8dcc5c2101c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238981574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2238981574
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2443629048
Short name T389
Test name
Test status
Simulation time 1369797096 ps
CPU time 7.14 seconds
Started Jun 22 04:58:37 PM PDT 24
Finished Jun 22 04:58:46 PM PDT 24
Peak memory 200892 kb
Host smart-8bb36ea1-ba85-4c2b-a954-c56a924c451e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443629048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2443629048
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1787376422
Short name T406
Test name
Test status
Simulation time 147319896 ps
CPU time 1.93 seconds
Started Jun 22 04:58:38 PM PDT 24
Finished Jun 22 04:58:42 PM PDT 24
Peak memory 200924 kb
Host smart-27644b42-f899-46fb-886d-8d89ad53b139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787376422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1787376422
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2672286269
Short name T231
Test name
Test status
Simulation time 68700434 ps
CPU time 0.83 seconds
Started Jun 22 04:58:36 PM PDT 24
Finished Jun 22 04:58:38 PM PDT 24
Peak memory 200724 kb
Host smart-de4f287a-6fa2-4819-b6e6-90e1284f5df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672286269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2672286269
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.382711420
Short name T507
Test name
Test status
Simulation time 63485934 ps
CPU time 0.75 seconds
Started Jun 22 04:58:37 PM PDT 24
Finished Jun 22 04:58:39 PM PDT 24
Peak memory 200512 kb
Host smart-1a2d8071-c24d-4873-b986-b8c0bee373fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382711420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.382711420
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1486058486
Short name T380
Test name
Test status
Simulation time 1893096595 ps
CPU time 7.02 seconds
Started Jun 22 04:58:41 PM PDT 24
Finished Jun 22 04:58:49 PM PDT 24
Peak memory 218516 kb
Host smart-65232043-5803-4c09-9d3e-dbb60ac8cbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486058486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1486058486
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2966103355
Short name T523
Test name
Test status
Simulation time 244372762 ps
CPU time 1.1 seconds
Started Jun 22 04:58:39 PM PDT 24
Finished Jun 22 04:58:41 PM PDT 24
Peak memory 217960 kb
Host smart-93904642-5b39-40e4-bbef-b9d9fb67f5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966103355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2966103355
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2225479966
Short name T20
Test name
Test status
Simulation time 173366201 ps
CPU time 0.9 seconds
Started Jun 22 04:58:36 PM PDT 24
Finished Jun 22 04:58:37 PM PDT 24
Peak memory 200508 kb
Host smart-192a6964-5fa3-4e7b-a5eb-ab8aefc78e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225479966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2225479966
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3777956712
Short name T92
Test name
Test status
Simulation time 972500372 ps
CPU time 5.01 seconds
Started Jun 22 04:58:38 PM PDT 24
Finished Jun 22 04:58:45 PM PDT 24
Peak memory 200764 kb
Host smart-10f06677-d1c0-4894-b3de-25856b3a039a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777956712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3777956712
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3203873106
Short name T336
Test name
Test status
Simulation time 107577816 ps
CPU time 1.13 seconds
Started Jun 22 04:58:37 PM PDT 24
Finished Jun 22 04:58:39 PM PDT 24
Peak memory 200664 kb
Host smart-ae25d9c9-7e4e-4727-841f-73425dd399b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203873106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3203873106
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3836317466
Short name T433
Test name
Test status
Simulation time 203209071 ps
CPU time 1.41 seconds
Started Jun 22 04:58:37 PM PDT 24
Finished Jun 22 04:58:40 PM PDT 24
Peak memory 200892 kb
Host smart-129c75ec-4025-4aca-a5ea-f8fbbf67f2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836317466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3836317466
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3761371671
Short name T293
Test name
Test status
Simulation time 3469594700 ps
CPU time 15.21 seconds
Started Jun 22 04:58:40 PM PDT 24
Finished Jun 22 04:58:56 PM PDT 24
Peak memory 200932 kb
Host smart-a8065be7-0ac1-4415-bcae-74b7cdeb070a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761371671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3761371671
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.3079655785
Short name T186
Test name
Test status
Simulation time 134829683 ps
CPU time 1.72 seconds
Started Jun 22 04:58:39 PM PDT 24
Finished Jun 22 04:58:42 PM PDT 24
Peak memory 208896 kb
Host smart-d65179b6-8fa1-4fae-a79d-52eb6e7551e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079655785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.3079655785
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2974677875
Short name T139
Test name
Test status
Simulation time 68195905 ps
CPU time 0.83 seconds
Started Jun 22 04:58:36 PM PDT 24
Finished Jun 22 04:58:38 PM PDT 24
Peak memory 200700 kb
Host smart-7b7f661f-4230-4adf-8787-c68acc5bfa6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974677875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2974677875
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.3995773277
Short name T330
Test name
Test status
Simulation time 63984768 ps
CPU time 0.73 seconds
Started Jun 22 04:58:51 PM PDT 24
Finished Jun 22 04:58:52 PM PDT 24
Peak memory 200444 kb
Host smart-acae605a-aad0-4e7c-83fc-5b15866a9c0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995773277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3995773277
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.3448182948
Short name T443
Test name
Test status
Simulation time 1880799706 ps
CPU time 8.41 seconds
Started Jun 22 04:58:37 PM PDT 24
Finished Jun 22 04:58:47 PM PDT 24
Peak memory 222416 kb
Host smart-38ccd004-9b01-45a6-90f0-90b24d79787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448182948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.3448182948
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.304808544
Short name T306
Test name
Test status
Simulation time 244207815 ps
CPU time 1.11 seconds
Started Jun 22 04:58:37 PM PDT 24
Finished Jun 22 04:58:40 PM PDT 24
Peak memory 218032 kb
Host smart-8ddcb4e2-99ef-463e-816a-c2aac94adc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304808544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.304808544
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.809947252
Short name T348
Test name
Test status
Simulation time 93290086 ps
CPU time 0.78 seconds
Started Jun 22 04:58:42 PM PDT 24
Finished Jun 22 04:58:43 PM PDT 24
Peak memory 200536 kb
Host smart-fc810e67-f4c9-445a-b5b0-ac9f9c762658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809947252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.809947252
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2517498415
Short name T520
Test name
Test status
Simulation time 1116003714 ps
CPU time 5.51 seconds
Started Jun 22 04:58:38 PM PDT 24
Finished Jun 22 04:58:45 PM PDT 24
Peak memory 200948 kb
Host smart-745e7426-8ed1-4a7d-9a84-863aa34e3405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517498415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2517498415
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.970604371
Short name T157
Test name
Test status
Simulation time 109242718 ps
CPU time 1.01 seconds
Started Jun 22 04:58:37 PM PDT 24
Finished Jun 22 04:58:40 PM PDT 24
Peak memory 200724 kb
Host smart-0cdf9d89-c284-4051-940b-9de1ab5b7904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970604371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.970604371
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.4242869602
Short name T513
Test name
Test status
Simulation time 111243261 ps
CPU time 1.24 seconds
Started Jun 22 04:58:37 PM PDT 24
Finished Jun 22 04:58:39 PM PDT 24
Peak memory 200904 kb
Host smart-d19ba638-3ff2-4914-a1ab-f31b3d06844a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242869602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.4242869602
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1074824645
Short name T344
Test name
Test status
Simulation time 4904729091 ps
CPU time 22.67 seconds
Started Jun 22 04:58:46 PM PDT 24
Finished Jun 22 04:59:10 PM PDT 24
Peak memory 209024 kb
Host smart-083af1bf-870b-41ce-ab3e-690f47032c6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074824645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1074824645
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3780563780
Short name T516
Test name
Test status
Simulation time 391279020 ps
CPU time 2.42 seconds
Started Jun 22 04:58:37 PM PDT 24
Finished Jun 22 04:58:41 PM PDT 24
Peak memory 200688 kb
Host smart-36641764-7277-43c9-bf08-e66e93a01d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780563780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3780563780
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3724208223
Short name T205
Test name
Test status
Simulation time 134861482 ps
CPU time 1.21 seconds
Started Jun 22 04:58:38 PM PDT 24
Finished Jun 22 04:58:40 PM PDT 24
Peak memory 200676 kb
Host smart-9a1a9688-c613-4b17-a541-29561c5f2dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724208223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3724208223
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1620102426
Short name T479
Test name
Test status
Simulation time 76078362 ps
CPU time 0.84 seconds
Started Jun 22 04:58:50 PM PDT 24
Finished Jun 22 04:58:51 PM PDT 24
Peak memory 200516 kb
Host smart-1f4f9d60-528d-4a7d-86c5-f388e51179f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620102426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1620102426
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2187761801
Short name T468
Test name
Test status
Simulation time 244570335 ps
CPU time 1.16 seconds
Started Jun 22 04:58:46 PM PDT 24
Finished Jun 22 04:58:49 PM PDT 24
Peak memory 218044 kb
Host smart-c0b91bcd-6132-4946-8003-0ca7bca19df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187761801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2187761801
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1529943938
Short name T15
Test name
Test status
Simulation time 143112598 ps
CPU time 0.83 seconds
Started Jun 22 04:58:44 PM PDT 24
Finished Jun 22 04:58:46 PM PDT 24
Peak memory 200512 kb
Host smart-03cec812-25de-4f16-8968-13d2a3c8f230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529943938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1529943938
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.353342626
Short name T314
Test name
Test status
Simulation time 851872066 ps
CPU time 4.43 seconds
Started Jun 22 04:58:53 PM PDT 24
Finished Jun 22 04:58:59 PM PDT 24
Peak memory 200884 kb
Host smart-1dcf2a24-1653-4c97-91a2-24592b989579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353342626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.353342626
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.4096902706
Short name T182
Test name
Test status
Simulation time 176948195 ps
CPU time 1.17 seconds
Started Jun 22 04:58:53 PM PDT 24
Finished Jun 22 04:58:56 PM PDT 24
Peak memory 200724 kb
Host smart-cf2dcda2-5352-4b1c-a1e3-11a0353d0441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096902706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.4096902706
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1839104736
Short name T535
Test name
Test status
Simulation time 253369914 ps
CPU time 1.54 seconds
Started Jun 22 04:58:49 PM PDT 24
Finished Jun 22 04:58:51 PM PDT 24
Peak memory 201116 kb
Host smart-2eddfc12-9bbd-4fcc-9256-0ab50b41743b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839104736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1839104736
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1629948340
Short name T238
Test name
Test status
Simulation time 3271632367 ps
CPU time 13.83 seconds
Started Jun 22 04:58:55 PM PDT 24
Finished Jun 22 04:59:11 PM PDT 24
Peak memory 200896 kb
Host smart-87f6063b-2035-4779-a33e-de92533e1b9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629948340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1629948340
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2370571018
Short name T471
Test name
Test status
Simulation time 148032941 ps
CPU time 1.84 seconds
Started Jun 22 04:58:50 PM PDT 24
Finished Jun 22 04:58:52 PM PDT 24
Peak memory 200424 kb
Host smart-2564f5f7-d4ac-4a68-bf88-e6802f082dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370571018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2370571018
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.1276129359
Short name T342
Test name
Test status
Simulation time 79199269 ps
CPU time 0.9 seconds
Started Jun 22 04:58:47 PM PDT 24
Finished Jun 22 04:58:49 PM PDT 24
Peak memory 200928 kb
Host smart-3e8117b9-6fce-4c92-8de8-fcf6dcfb090e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276129359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1276129359
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.707999378
Short name T496
Test name
Test status
Simulation time 69820308 ps
CPU time 0.79 seconds
Started Jun 22 04:58:50 PM PDT 24
Finished Jun 22 04:58:52 PM PDT 24
Peak memory 200500 kb
Host smart-925f867a-899a-4e64-b0d6-2e7cd96720f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707999378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.707999378
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.1554525491
Short name T264
Test name
Test status
Simulation time 2365083905 ps
CPU time 8.58 seconds
Started Jun 22 04:58:50 PM PDT 24
Finished Jun 22 04:58:59 PM PDT 24
Peak memory 218228 kb
Host smart-1887d3ff-9db3-49c9-a3dc-aa37e1beacc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554525491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1554525491
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.4175522914
Short name T503
Test name
Test status
Simulation time 243959117 ps
CPU time 1.15 seconds
Started Jun 22 04:58:51 PM PDT 24
Finished Jun 22 04:58:53 PM PDT 24
Peak memory 218136 kb
Host smart-03a53845-a5bf-4916-9d22-2e9eb8113304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175522914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.4175522914
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1619084892
Short name T18
Test name
Test status
Simulation time 135124486 ps
CPU time 0.8 seconds
Started Jun 22 04:58:46 PM PDT 24
Finished Jun 22 04:58:48 PM PDT 24
Peak memory 200436 kb
Host smart-e1f75c45-177a-4701-80d4-bb7121fa0570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619084892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1619084892
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.2812335504
Short name T506
Test name
Test status
Simulation time 979534686 ps
CPU time 4.53 seconds
Started Jun 22 04:58:54 PM PDT 24
Finished Jun 22 04:59:01 PM PDT 24
Peak memory 200840 kb
Host smart-804d1f8e-b195-4055-8229-b644b862159e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812335504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2812335504
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3225683654
Short name T454
Test name
Test status
Simulation time 189066006 ps
CPU time 1.24 seconds
Started Jun 22 04:58:46 PM PDT 24
Finished Jun 22 04:58:49 PM PDT 24
Peak memory 200724 kb
Host smart-f46a9764-87b8-4d11-93fe-4617fa208e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225683654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3225683654
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.3045054146
Short name T429
Test name
Test status
Simulation time 264119801 ps
CPU time 1.51 seconds
Started Jun 22 04:58:50 PM PDT 24
Finished Jun 22 04:58:52 PM PDT 24
Peak memory 200892 kb
Host smart-0fc972f4-4631-4a0d-8418-162c063a2495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045054146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.3045054146
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.1027027371
Short name T167
Test name
Test status
Simulation time 4308156640 ps
CPU time 19.61 seconds
Started Jun 22 04:58:50 PM PDT 24
Finished Jun 22 04:59:10 PM PDT 24
Peak memory 200952 kb
Host smart-fff37490-3d3f-4832-a136-e527e387c2fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027027371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1027027371
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2149653515
Short name T517
Test name
Test status
Simulation time 261164197 ps
CPU time 1.79 seconds
Started Jun 22 04:58:51 PM PDT 24
Finished Jun 22 04:58:53 PM PDT 24
Peak memory 200652 kb
Host smart-68db49a4-d883-40fe-86ff-6ae63e5ef069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149653515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2149653515
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.3268577719
Short name T161
Test name
Test status
Simulation time 121025810 ps
CPU time 1.07 seconds
Started Jun 22 04:58:44 PM PDT 24
Finished Jun 22 04:58:46 PM PDT 24
Peak memory 200704 kb
Host smart-27483d6b-bc06-4e87-a763-a573daed6341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268577719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.3268577719
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.467104640
Short name T541
Test name
Test status
Simulation time 68732533 ps
CPU time 0.81 seconds
Started Jun 22 04:58:55 PM PDT 24
Finished Jun 22 04:58:58 PM PDT 24
Peak memory 200468 kb
Host smart-786efe93-f5f4-44d9-a4d8-a32f9869f9e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467104640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.467104640
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.404061928
Short name T40
Test name
Test status
Simulation time 2186377438 ps
CPU time 7.66 seconds
Started Jun 22 04:58:51 PM PDT 24
Finished Jun 22 04:59:00 PM PDT 24
Peak memory 222484 kb
Host smart-be41c318-0d4f-429e-aec5-542c7fd7f2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404061928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.404061928
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.338691719
Short name T214
Test name
Test status
Simulation time 243442647 ps
CPU time 1.05 seconds
Started Jun 22 04:58:51 PM PDT 24
Finished Jun 22 04:58:52 PM PDT 24
Peak memory 218144 kb
Host smart-622c9d5c-cb90-49a0-862c-f57d33490362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338691719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.338691719
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3973548402
Short name T213
Test name
Test status
Simulation time 182077696 ps
CPU time 0.87 seconds
Started Jun 22 04:58:48 PM PDT 24
Finished Jun 22 04:58:50 PM PDT 24
Peak memory 200480 kb
Host smart-6f5f37d6-dbd8-42a0-895c-bdf8b91c1b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973548402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3973548402
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.474282265
Short name T369
Test name
Test status
Simulation time 866865949 ps
CPU time 4.54 seconds
Started Jun 22 04:58:52 PM PDT 24
Finished Jun 22 04:58:57 PM PDT 24
Peak memory 200884 kb
Host smart-638c02d3-50e6-43eb-9290-ad862cd5c95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474282265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.474282265
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.321360956
Short name T393
Test name
Test status
Simulation time 106444418 ps
CPU time 1.08 seconds
Started Jun 22 04:58:47 PM PDT 24
Finished Jun 22 04:58:49 PM PDT 24
Peak memory 200692 kb
Host smart-4babcf14-bb6f-48f8-aeb1-9d11e0ff0b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321360956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.321360956
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3192720896
Short name T294
Test name
Test status
Simulation time 245583140 ps
CPU time 1.49 seconds
Started Jun 22 04:58:47 PM PDT 24
Finished Jun 22 04:58:49 PM PDT 24
Peak memory 200852 kb
Host smart-7ae4962a-d5fe-4ca7-8491-28451f21da58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192720896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3192720896
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.58709903
Short name T403
Test name
Test status
Simulation time 9522722086 ps
CPU time 31.08 seconds
Started Jun 22 04:58:49 PM PDT 24
Finished Jun 22 04:59:21 PM PDT 24
Peak memory 216632 kb
Host smart-b2446533-4f16-4416-a657-4e0a66e2d4c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58709903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.58709903
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3032002711
Short name T333
Test name
Test status
Simulation time 361152619 ps
CPU time 2.32 seconds
Started Jun 22 04:58:50 PM PDT 24
Finished Jun 22 04:58:53 PM PDT 24
Peak memory 200704 kb
Host smart-ce6fdcf4-c052-412f-93b8-b57a78034a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032002711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3032002711
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3870616887
Short name T305
Test name
Test status
Simulation time 199192264 ps
CPU time 1.41 seconds
Started Jun 22 04:58:46 PM PDT 24
Finished Jun 22 04:58:48 PM PDT 24
Peak memory 200668 kb
Host smart-6bb7bd15-c58a-4bc4-8ee3-10475b9cc547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870616887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3870616887
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2190972544
Short name T262
Test name
Test status
Simulation time 85453028 ps
CPU time 0.83 seconds
Started Jun 22 04:58:19 PM PDT 24
Finished Jun 22 04:58:20 PM PDT 24
Peak memory 200508 kb
Host smart-abd11630-d63d-448f-b233-21e1105650f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190972544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2190972544
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.623676034
Short name T288
Test name
Test status
Simulation time 1234421029 ps
CPU time 5.57 seconds
Started Jun 22 04:58:13 PM PDT 24
Finished Jun 22 04:58:19 PM PDT 24
Peak memory 218104 kb
Host smart-89bf1737-2e64-43b5-9ebd-e12b9142cf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623676034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.623676034
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.4142178981
Short name T237
Test name
Test status
Simulation time 244292587 ps
CPU time 1.14 seconds
Started Jun 22 04:58:19 PM PDT 24
Finished Jun 22 04:58:21 PM PDT 24
Peak memory 218096 kb
Host smart-9d0cbf06-69c1-4d3a-8509-ab9b57afd8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142178981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.4142178981
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2176287981
Short name T270
Test name
Test status
Simulation time 157315269 ps
CPU time 0.83 seconds
Started Jun 22 04:58:13 PM PDT 24
Finished Jun 22 04:58:14 PM PDT 24
Peak memory 200504 kb
Host smart-4f3a084e-2d9e-4770-8dce-da7e4cc781d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176287981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2176287981
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3177966037
Short name T518
Test name
Test status
Simulation time 2175516012 ps
CPU time 7.6 seconds
Started Jun 22 04:58:14 PM PDT 24
Finished Jun 22 04:58:23 PM PDT 24
Peak memory 200944 kb
Host smart-73facfea-d067-49f5-b8cc-404ffe2da924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177966037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3177966037
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.873007223
Short name T66
Test name
Test status
Simulation time 8280887568 ps
CPU time 15.27 seconds
Started Jun 22 04:58:18 PM PDT 24
Finished Jun 22 04:58:33 PM PDT 24
Peak memory 217776 kb
Host smart-08711f53-2a45-4d25-9475-2716270ce0f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873007223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.873007223
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.647126647
Short name T183
Test name
Test status
Simulation time 170022202 ps
CPU time 1.19 seconds
Started Jun 22 04:58:12 PM PDT 24
Finished Jun 22 04:58:14 PM PDT 24
Peak memory 200692 kb
Host smart-601d6553-dcba-48ce-be01-14a0d21ceef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647126647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.647126647
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.2266432670
Short name T457
Test name
Test status
Simulation time 235528139 ps
CPU time 1.59 seconds
Started Jun 22 04:58:12 PM PDT 24
Finished Jun 22 04:58:14 PM PDT 24
Peak memory 200892 kb
Host smart-9f8d5e98-9ed4-4065-a423-270bb518cb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266432670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2266432670
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.198765529
Short name T353
Test name
Test status
Simulation time 15793859027 ps
CPU time 58.23 seconds
Started Jun 22 04:58:13 PM PDT 24
Finished Jun 22 04:59:12 PM PDT 24
Peak memory 210808 kb
Host smart-f2524da8-f3f4-4a44-9bf9-300821897d65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198765529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.198765529
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3237169325
Short name T486
Test name
Test status
Simulation time 114122478 ps
CPU time 1.54 seconds
Started Jun 22 04:58:13 PM PDT 24
Finished Jun 22 04:58:16 PM PDT 24
Peak memory 200644 kb
Host smart-d1250cb3-bf91-4ce0-abd8-fe883639fc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237169325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3237169325
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.4265501200
Short name T284
Test name
Test status
Simulation time 273411036 ps
CPU time 1.48 seconds
Started Jun 22 04:58:14 PM PDT 24
Finished Jun 22 04:58:16 PM PDT 24
Peak memory 200912 kb
Host smart-cfb7a936-d8bd-4f1c-80c2-73ecdc542755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265501200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.4265501200
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.510787894
Short name T422
Test name
Test status
Simulation time 60414305 ps
CPU time 0.8 seconds
Started Jun 22 04:58:54 PM PDT 24
Finished Jun 22 04:58:56 PM PDT 24
Peak memory 200368 kb
Host smart-8487895a-c09f-4b70-a7e0-d4c6f8c20a8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510787894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.510787894
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.628508410
Short name T291
Test name
Test status
Simulation time 1888221133 ps
CPU time 7.62 seconds
Started Jun 22 04:58:55 PM PDT 24
Finished Jun 22 04:59:05 PM PDT 24
Peak memory 217500 kb
Host smart-8b6985dd-4f65-4de2-8a70-7c6ed86405f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628508410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.628508410
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3317311660
Short name T300
Test name
Test status
Simulation time 243614542 ps
CPU time 1.06 seconds
Started Jun 22 04:58:49 PM PDT 24
Finished Jun 22 04:58:51 PM PDT 24
Peak memory 218108 kb
Host smart-0dfd84b6-b71c-45ea-9b6d-c939c2132389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317311660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3317311660
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.661341602
Short name T385
Test name
Test status
Simulation time 198197263 ps
CPU time 0.93 seconds
Started Jun 22 04:58:45 PM PDT 24
Finished Jun 22 04:58:47 PM PDT 24
Peak memory 200532 kb
Host smart-a72d7f65-eb4f-4c13-a9ba-0ea21da98893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661341602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.661341602
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2874117657
Short name T192
Test name
Test status
Simulation time 805739085 ps
CPU time 3.98 seconds
Started Jun 22 04:58:53 PM PDT 24
Finished Jun 22 04:58:58 PM PDT 24
Peak memory 200912 kb
Host smart-204b2f04-9ead-44f2-a12b-b20bf546675e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874117657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2874117657
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1711992142
Short name T542
Test name
Test status
Simulation time 93784711 ps
CPU time 1.07 seconds
Started Jun 22 04:58:54 PM PDT 24
Finished Jun 22 04:58:56 PM PDT 24
Peak memory 200580 kb
Host smart-7ecfa1e2-fff7-438f-bac4-db20efdac5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711992142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1711992142
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.794495007
Short name T401
Test name
Test status
Simulation time 119496712 ps
CPU time 1.25 seconds
Started Jun 22 04:58:51 PM PDT 24
Finished Jun 22 04:58:54 PM PDT 24
Peak memory 200880 kb
Host smart-1e656193-2eb3-458e-b300-ab8671d2a7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794495007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.794495007
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.566415100
Short name T458
Test name
Test status
Simulation time 281662056 ps
CPU time 1.86 seconds
Started Jun 22 04:58:52 PM PDT 24
Finished Jun 22 04:58:54 PM PDT 24
Peak memory 200764 kb
Host smart-e0cc40fa-9380-43af-b42e-c951552282d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566415100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.566415100
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3267728825
Short name T530
Test name
Test status
Simulation time 138738796 ps
CPU time 1.76 seconds
Started Jun 22 04:58:49 PM PDT 24
Finished Jun 22 04:58:52 PM PDT 24
Peak memory 200716 kb
Host smart-d18604ee-03e5-4d99-b26b-51e5365db142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267728825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3267728825
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1868093009
Short name T273
Test name
Test status
Simulation time 94106041 ps
CPU time 0.87 seconds
Started Jun 22 04:58:45 PM PDT 24
Finished Jun 22 04:58:48 PM PDT 24
Peak memory 200724 kb
Host smart-51f87fa6-adf3-4333-81b9-5d303974799e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868093009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1868093009
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1260588749
Short name T356
Test name
Test status
Simulation time 73817239 ps
CPU time 0.77 seconds
Started Jun 22 04:58:54 PM PDT 24
Finished Jun 22 04:58:56 PM PDT 24
Peak memory 200516 kb
Host smart-a7d2c22f-d44b-4559-a999-6d7e6dc9c886
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260588749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1260588749
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.4079324975
Short name T370
Test name
Test status
Simulation time 1903793296 ps
CPU time 7.69 seconds
Started Jun 22 04:58:44 PM PDT 24
Finished Jun 22 04:58:53 PM PDT 24
Peak memory 230660 kb
Host smart-306e64c5-37e9-4c73-9672-ad20a4b1674d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079324975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.4079324975
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3632415840
Short name T143
Test name
Test status
Simulation time 243984724 ps
CPU time 1.13 seconds
Started Jun 22 04:58:57 PM PDT 24
Finished Jun 22 04:59:01 PM PDT 24
Peak memory 218072 kb
Host smart-780d6ed2-32c2-4ca3-873e-14d32f98d479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632415840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3632415840
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1846510391
Short name T206
Test name
Test status
Simulation time 135153363 ps
CPU time 0.88 seconds
Started Jun 22 04:58:46 PM PDT 24
Finished Jun 22 04:58:48 PM PDT 24
Peak memory 200432 kb
Host smart-3fdf9801-ea04-4302-bc38-2be59087fbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846510391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1846510391
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3416269696
Short name T249
Test name
Test status
Simulation time 923006006 ps
CPU time 4.72 seconds
Started Jun 22 04:58:49 PM PDT 24
Finished Jun 22 04:58:55 PM PDT 24
Peak memory 200908 kb
Host smart-b970b729-f099-473f-9e22-6e2f6c81ca8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416269696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3416269696
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.769989574
Short name T3
Test name
Test status
Simulation time 149233690 ps
CPU time 1.09 seconds
Started Jun 22 04:58:47 PM PDT 24
Finished Jun 22 04:58:49 PM PDT 24
Peak memory 200292 kb
Host smart-89d2d5b3-83fd-4b80-bed5-81326b2a8b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769989574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.769989574
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2038219112
Short name T460
Test name
Test status
Simulation time 108495461 ps
CPU time 1.14 seconds
Started Jun 22 04:58:53 PM PDT 24
Finished Jun 22 04:58:55 PM PDT 24
Peak memory 200944 kb
Host smart-3c87aada-1560-4268-830e-b6e09d715bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038219112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2038219112
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2616138837
Short name T74
Test name
Test status
Simulation time 7186710660 ps
CPU time 32.02 seconds
Started Jun 22 04:58:57 PM PDT 24
Finished Jun 22 04:59:32 PM PDT 24
Peak memory 209188 kb
Host smart-597ee9a6-72da-4759-8a60-cde8749b6169
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616138837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2616138837
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1428204393
Short name T44
Test name
Test status
Simulation time 321036786 ps
CPU time 1.97 seconds
Started Jun 22 04:58:49 PM PDT 24
Finished Jun 22 04:58:52 PM PDT 24
Peak memory 200620 kb
Host smart-71328c67-28ec-41a2-a934-70ca32b9a3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428204393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1428204393
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1448199114
Short name T394
Test name
Test status
Simulation time 154230402 ps
CPU time 1.23 seconds
Started Jun 22 04:58:47 PM PDT 24
Finished Jun 22 04:58:50 PM PDT 24
Peak memory 200384 kb
Host smart-595d8be1-c9c5-4fa7-ac60-f37cdc79ac36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448199114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1448199114
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2862984645
Short name T301
Test name
Test status
Simulation time 55240648 ps
CPU time 0.73 seconds
Started Jun 22 04:58:53 PM PDT 24
Finished Jun 22 04:58:55 PM PDT 24
Peak memory 200732 kb
Host smart-f333fb83-40a7-4fce-8257-b530370e114a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862984645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2862984645
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1592422840
Short name T54
Test name
Test status
Simulation time 1233746604 ps
CPU time 5.44 seconds
Started Jun 22 04:58:56 PM PDT 24
Finished Jun 22 04:59:03 PM PDT 24
Peak memory 217624 kb
Host smart-ebcdb63b-bfb3-42a2-80ac-2a2424178173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592422840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1592422840
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1192370454
Short name T199
Test name
Test status
Simulation time 243899514 ps
CPU time 1.1 seconds
Started Jun 22 04:58:57 PM PDT 24
Finished Jun 22 04:59:00 PM PDT 24
Peak memory 218076 kb
Host smart-547c7644-1946-4fbc-b354-f2b6cf191a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192370454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1192370454
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.1694517954
Short name T351
Test name
Test status
Simulation time 196080640 ps
CPU time 0.86 seconds
Started Jun 22 04:58:53 PM PDT 24
Finished Jun 22 04:58:55 PM PDT 24
Peak memory 200468 kb
Host smart-b27646f5-b3e3-4190-8daa-b323e3fd0b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694517954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1694517954
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2787523545
Short name T303
Test name
Test status
Simulation time 1493202451 ps
CPU time 5.76 seconds
Started Jun 22 04:58:54 PM PDT 24
Finished Jun 22 04:59:01 PM PDT 24
Peak memory 200868 kb
Host smart-9c057a1b-3082-42f8-a06c-c65f4baaf139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787523545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2787523545
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2434177325
Short name T310
Test name
Test status
Simulation time 99119505 ps
CPU time 1.04 seconds
Started Jun 22 04:59:01 PM PDT 24
Finished Jun 22 04:59:05 PM PDT 24
Peak memory 200684 kb
Host smart-57fbaf20-7bef-4a12-a7f4-a240ea2dccd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434177325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2434177325
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1021102467
Short name T142
Test name
Test status
Simulation time 115440342 ps
CPU time 1.15 seconds
Started Jun 22 04:58:59 PM PDT 24
Finished Jun 22 04:59:02 PM PDT 24
Peak memory 200880 kb
Host smart-bfb9167f-636e-4bdb-a752-ddfb1a762aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021102467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1021102467
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.451702352
Short name T243
Test name
Test status
Simulation time 770289269 ps
CPU time 3.7 seconds
Started Jun 22 04:58:57 PM PDT 24
Finished Jun 22 04:59:03 PM PDT 24
Peak memory 200932 kb
Host smart-0a354fe5-4824-4177-bb35-b7f3c686b9f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451702352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.451702352
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.4125051332
Short name T223
Test name
Test status
Simulation time 126981595 ps
CPU time 1.57 seconds
Started Jun 22 04:58:54 PM PDT 24
Finished Jun 22 04:58:58 PM PDT 24
Peak memory 208952 kb
Host smart-81a0deb5-f56e-487e-a93f-342af916865b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125051332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.4125051332
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1357200119
Short name T279
Test name
Test status
Simulation time 159583422 ps
CPU time 1.29 seconds
Started Jun 22 04:58:53 PM PDT 24
Finished Jun 22 04:58:55 PM PDT 24
Peak memory 200924 kb
Host smart-da3562ff-cfbf-4ff9-89de-fd810e712f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357200119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1357200119
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.2779495166
Short name T413
Test name
Test status
Simulation time 68159451 ps
CPU time 0.75 seconds
Started Jun 22 04:58:54 PM PDT 24
Finished Jun 22 04:58:57 PM PDT 24
Peak memory 200504 kb
Host smart-36dc4d62-5897-4958-aeda-cb3977b8b9b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779495166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.2779495166
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3942986517
Short name T27
Test name
Test status
Simulation time 1881965561 ps
CPU time 6.97 seconds
Started Jun 22 04:58:54 PM PDT 24
Finished Jun 22 04:59:03 PM PDT 24
Peak memory 222288 kb
Host smart-807bcb17-ceed-416f-997f-586482928abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942986517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3942986517
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3797220304
Short name T463
Test name
Test status
Simulation time 244490425 ps
CPU time 1.03 seconds
Started Jun 22 04:58:56 PM PDT 24
Finished Jun 22 04:58:59 PM PDT 24
Peak memory 218104 kb
Host smart-6c195e26-b24c-4d12-8375-69fd4cc90e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797220304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3797220304
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1966849580
Short name T510
Test name
Test status
Simulation time 164039479 ps
CPU time 0.87 seconds
Started Jun 22 04:58:55 PM PDT 24
Finished Jun 22 04:58:58 PM PDT 24
Peak memory 200456 kb
Host smart-4f1b3e2d-bf7b-4f18-858c-aabf1e4993ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966849580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1966849580
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2836719178
Short name T285
Test name
Test status
Simulation time 851754113 ps
CPU time 4.31 seconds
Started Jun 22 04:58:57 PM PDT 24
Finished Jun 22 04:59:03 PM PDT 24
Peak memory 200872 kb
Host smart-9e7a824a-34aa-432e-9425-e4bc1780ebd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836719178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2836719178
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2882453356
Short name T202
Test name
Test status
Simulation time 149617022 ps
CPU time 1.26 seconds
Started Jun 22 04:58:56 PM PDT 24
Finished Jun 22 04:59:00 PM PDT 24
Peak memory 200688 kb
Host smart-149dff5b-ad24-43d4-b7c0-4b078306c522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882453356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2882453356
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.889649964
Short name T321
Test name
Test status
Simulation time 240776091 ps
CPU time 1.42 seconds
Started Jun 22 04:58:57 PM PDT 24
Finished Jun 22 04:59:00 PM PDT 24
Peak memory 200852 kb
Host smart-46dcdc75-c374-4a8e-ab4d-0b8f432d999a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889649964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.889649964
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2821017008
Short name T95
Test name
Test status
Simulation time 7628799901 ps
CPU time 26.16 seconds
Started Jun 22 04:58:55 PM PDT 24
Finished Jun 22 04:59:23 PM PDT 24
Peak memory 209136 kb
Host smart-107bee23-097a-49b4-83c1-4329ccfb3ca1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821017008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2821017008
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1227941360
Short name T208
Test name
Test status
Simulation time 509335653 ps
CPU time 2.89 seconds
Started Jun 22 04:58:55 PM PDT 24
Finished Jun 22 04:59:00 PM PDT 24
Peak memory 200716 kb
Host smart-6938ffcd-49f3-41c3-84dc-ac62b09326eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227941360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1227941360
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.2543532704
Short name T371
Test name
Test status
Simulation time 109070790 ps
CPU time 1.01 seconds
Started Jun 22 04:59:01 PM PDT 24
Finished Jun 22 04:59:05 PM PDT 24
Peak memory 200688 kb
Host smart-c42ffa75-0292-4ea5-a1b0-879656eeac50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543532704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2543532704
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3105432542
Short name T151
Test name
Test status
Simulation time 71399684 ps
CPU time 0.8 seconds
Started Jun 22 04:58:58 PM PDT 24
Finished Jun 22 04:59:01 PM PDT 24
Peak memory 200452 kb
Host smart-2eb43d90-b411-4da9-800d-84b769a72d28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105432542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3105432542
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.460339226
Short name T28
Test name
Test status
Simulation time 2355623171 ps
CPU time 8.35 seconds
Started Jun 22 04:58:57 PM PDT 24
Finished Jun 22 04:59:08 PM PDT 24
Peak memory 222484 kb
Host smart-091fe20c-12d5-4fd9-bbe0-4ac6a23a1630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460339226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.460339226
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2919851968
Short name T488
Test name
Test status
Simulation time 244324305 ps
CPU time 1.17 seconds
Started Jun 22 04:58:52 PM PDT 24
Finished Jun 22 04:58:54 PM PDT 24
Peak memory 218056 kb
Host smart-15c857bf-f6d1-484a-8af5-264146106767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919851968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2919851968
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3476556433
Short name T269
Test name
Test status
Simulation time 118656198 ps
CPU time 0.79 seconds
Started Jun 22 04:59:00 PM PDT 24
Finished Jun 22 04:59:03 PM PDT 24
Peak memory 200504 kb
Host smart-3dfac92f-8588-48ac-9af4-b4402d366f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476556433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3476556433
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.1381785308
Short name T349
Test name
Test status
Simulation time 697833924 ps
CPU time 3.92 seconds
Started Jun 22 04:58:56 PM PDT 24
Finished Jun 22 04:59:02 PM PDT 24
Peak memory 200872 kb
Host smart-3fbf1ff1-397e-41ac-b6e2-e1c6003af93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381785308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1381785308
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1617246357
Short name T354
Test name
Test status
Simulation time 181200773 ps
CPU time 1.16 seconds
Started Jun 22 04:58:55 PM PDT 24
Finished Jun 22 04:58:58 PM PDT 24
Peak memory 200684 kb
Host smart-76781b7d-9560-4c4f-a2ed-9fdb9eb2bce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617246357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1617246357
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.4053127167
Short name T203
Test name
Test status
Simulation time 256160836 ps
CPU time 1.56 seconds
Started Jun 22 04:58:53 PM PDT 24
Finished Jun 22 04:58:55 PM PDT 24
Peak memory 200840 kb
Host smart-f61dbafa-1e65-4fac-b744-fde5ee94a2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053127167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.4053127167
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3581501700
Short name T193
Test name
Test status
Simulation time 4754228682 ps
CPU time 16.97 seconds
Started Jun 22 04:58:56 PM PDT 24
Finished Jun 22 04:59:15 PM PDT 24
Peak memory 210948 kb
Host smart-7e2ac84b-6532-446d-be51-aaad69693c21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581501700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3581501700
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.871710325
Short name T172
Test name
Test status
Simulation time 386872830 ps
CPU time 2.47 seconds
Started Jun 22 04:58:55 PM PDT 24
Finished Jun 22 04:59:00 PM PDT 24
Peak memory 200668 kb
Host smart-88c0c1c1-d247-4e76-8c0d-b2b4b7f8d914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871710325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.871710325
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1336463648
Short name T239
Test name
Test status
Simulation time 117233198 ps
CPU time 1.08 seconds
Started Jun 22 04:58:55 PM PDT 24
Finished Jun 22 04:58:58 PM PDT 24
Peak memory 200728 kb
Host smart-fc8d65be-9b42-4e1f-a2c6-c7426c91309a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336463648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1336463648
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3167459054
Short name T328
Test name
Test status
Simulation time 66277590 ps
CPU time 0.79 seconds
Started Jun 22 04:58:56 PM PDT 24
Finished Jun 22 04:58:59 PM PDT 24
Peak memory 200512 kb
Host smart-a0d9b92e-0fd8-41f2-a66f-8eb064fcf984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167459054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3167459054
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3694603684
Short name T361
Test name
Test status
Simulation time 1880055770 ps
CPU time 7.7 seconds
Started Jun 22 04:58:59 PM PDT 24
Finished Jun 22 04:59:09 PM PDT 24
Peak memory 217756 kb
Host smart-db84e06a-9dfc-4479-a904-fbd7ab95c7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694603684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3694603684
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2981885324
Short name T402
Test name
Test status
Simulation time 245072557 ps
CPU time 1.06 seconds
Started Jun 22 04:58:58 PM PDT 24
Finished Jun 22 04:59:01 PM PDT 24
Peak memory 218104 kb
Host smart-bab384b5-ee4a-4fac-bbc9-c314f2d1cd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981885324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2981885324
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.2673107289
Short name T17
Test name
Test status
Simulation time 159242445 ps
CPU time 0.89 seconds
Started Jun 22 04:58:57 PM PDT 24
Finished Jun 22 04:59:06 PM PDT 24
Peak memory 200488 kb
Host smart-199c6a76-ad88-4d6c-8663-529b5d1b3df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673107289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2673107289
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.3852505794
Short name T404
Test name
Test status
Simulation time 1740579969 ps
CPU time 6.48 seconds
Started Jun 22 04:58:55 PM PDT 24
Finished Jun 22 04:59:03 PM PDT 24
Peak memory 200912 kb
Host smart-def55f0c-919e-4318-9a3d-e07f07c626c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852505794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3852505794
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1519496753
Short name T408
Test name
Test status
Simulation time 98075252 ps
CPU time 0.97 seconds
Started Jun 22 04:58:55 PM PDT 24
Finished Jun 22 04:58:58 PM PDT 24
Peak memory 200696 kb
Host smart-f3f1dfe8-0b4f-4938-b59e-48467c4cb24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519496753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1519496753
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.1452842695
Short name T263
Test name
Test status
Simulation time 248708649 ps
CPU time 1.51 seconds
Started Jun 22 04:58:53 PM PDT 24
Finished Jun 22 04:58:56 PM PDT 24
Peak memory 200876 kb
Host smart-1c2bfd8d-4005-48cf-8a16-42cafd377cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452842695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1452842695
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1994447388
Short name T481
Test name
Test status
Simulation time 17816542432 ps
CPU time 61.69 seconds
Started Jun 22 04:58:58 PM PDT 24
Finished Jun 22 05:00:02 PM PDT 24
Peak memory 210920 kb
Host smart-ef9e9770-f8d9-49ff-9c78-1492d9e9d893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994447388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1994447388
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.2658788040
Short name T307
Test name
Test status
Simulation time 327775590 ps
CPU time 2.24 seconds
Started Jun 22 04:58:57 PM PDT 24
Finished Jun 22 04:59:02 PM PDT 24
Peak memory 200540 kb
Host smart-eb5ec6e2-80f6-4733-b953-4c5ac27ef816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658788040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.2658788040
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2551036548
Short name T68
Test name
Test status
Simulation time 174122774 ps
CPU time 1.33 seconds
Started Jun 22 04:58:57 PM PDT 24
Finished Jun 22 04:59:00 PM PDT 24
Peak memory 200928 kb
Host smart-3be26cf4-1c22-442e-ae2f-50dc52b47f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551036548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2551036548
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2937091273
Short name T492
Test name
Test status
Simulation time 79402828 ps
CPU time 0.82 seconds
Started Jun 22 04:58:51 PM PDT 24
Finished Jun 22 04:58:53 PM PDT 24
Peak memory 200508 kb
Host smart-27756ff6-a806-4af3-8723-945ce5e721ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937091273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2937091273
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.647363402
Short name T50
Test name
Test status
Simulation time 2362552287 ps
CPU time 7.83 seconds
Started Jun 22 04:59:00 PM PDT 24
Finished Jun 22 04:59:11 PM PDT 24
Peak memory 218556 kb
Host smart-dfb37f25-7905-4a8a-a0e3-70a971e94692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647363402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.647363402
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1827737252
Short name T145
Test name
Test status
Simulation time 246702266 ps
CPU time 1.13 seconds
Started Jun 22 04:58:58 PM PDT 24
Finished Jun 22 04:59:01 PM PDT 24
Peak memory 218068 kb
Host smart-3ef349ad-7d3b-4da5-8196-d3b517d21929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827737252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1827737252
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1668028838
Short name T441
Test name
Test status
Simulation time 178984538 ps
CPU time 0.87 seconds
Started Jun 22 04:58:58 PM PDT 24
Finished Jun 22 04:59:01 PM PDT 24
Peak memory 200500 kb
Host smart-4033ba0c-9bb3-4d0f-a75a-3e48d62b90ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668028838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1668028838
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.730108972
Short name T378
Test name
Test status
Simulation time 968200652 ps
CPU time 4.8 seconds
Started Jun 22 04:58:59 PM PDT 24
Finished Jun 22 04:59:06 PM PDT 24
Peak memory 200888 kb
Host smart-8b6bbbb5-4606-430d-9ff6-81af9e1c6a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730108972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.730108972
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3294766840
Short name T304
Test name
Test status
Simulation time 177108297 ps
CPU time 1.19 seconds
Started Jun 22 04:58:59 PM PDT 24
Finished Jun 22 04:59:02 PM PDT 24
Peak memory 200664 kb
Host smart-7eee05a2-1b0e-4c86-a150-91aff8b24e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294766840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3294766840
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3645903409
Short name T390
Test name
Test status
Simulation time 199872688 ps
CPU time 1.34 seconds
Started Jun 22 04:58:56 PM PDT 24
Finished Jun 22 04:59:00 PM PDT 24
Peak memory 200904 kb
Host smart-e2de5759-7409-48fe-b4d5-8f383c78e4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645903409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3645903409
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.453318794
Short name T96
Test name
Test status
Simulation time 2130914314 ps
CPU time 10.45 seconds
Started Jun 22 04:58:55 PM PDT 24
Finished Jun 22 04:59:07 PM PDT 24
Peak memory 200884 kb
Host smart-5acbf84c-2f88-4372-95d0-81a5d7528ae9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453318794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.453318794
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2828278610
Short name T363
Test name
Test status
Simulation time 530827961 ps
CPU time 2.72 seconds
Started Jun 22 04:58:55 PM PDT 24
Finished Jun 22 04:59:00 PM PDT 24
Peak memory 200680 kb
Host smart-c2632aae-a91a-4cce-a3f9-3233412250cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828278610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2828278610
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.1273771854
Short name T409
Test name
Test status
Simulation time 166792026 ps
CPU time 1.12 seconds
Started Jun 22 04:58:56 PM PDT 24
Finished Jun 22 04:58:59 PM PDT 24
Peak memory 200724 kb
Host smart-30782ea7-29bf-4fe8-a4c6-6dc46cf97afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273771854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1273771854
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.768722297
Short name T25
Test name
Test status
Simulation time 78288025 ps
CPU time 0.87 seconds
Started Jun 22 04:59:00 PM PDT 24
Finished Jun 22 04:59:03 PM PDT 24
Peak memory 200516 kb
Host smart-7982d505-2870-4afc-8784-f46715ea5229
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768722297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.768722297
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3593226222
Short name T53
Test name
Test status
Simulation time 2355052589 ps
CPU time 7.83 seconds
Started Jun 22 04:58:56 PM PDT 24
Finished Jun 22 04:59:06 PM PDT 24
Peak memory 218564 kb
Host smart-80576fe0-9021-4161-82f7-57c2db637e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593226222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3593226222
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2236813266
Short name T254
Test name
Test status
Simulation time 243750951 ps
CPU time 1.09 seconds
Started Jun 22 04:58:57 PM PDT 24
Finished Jun 22 04:59:01 PM PDT 24
Peak memory 218108 kb
Host smart-943d1ba3-233c-4112-bed6-f54f1d555aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236813266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2236813266
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.225827568
Short name T438
Test name
Test status
Simulation time 137704170 ps
CPU time 0.84 seconds
Started Jun 22 04:58:55 PM PDT 24
Finished Jun 22 04:58:58 PM PDT 24
Peak memory 200532 kb
Host smart-e841762f-3ce8-404a-8489-23b197c4975f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225827568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.225827568
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2785663594
Short name T268
Test name
Test status
Simulation time 1346798966 ps
CPU time 5.68 seconds
Started Jun 22 04:58:57 PM PDT 24
Finished Jun 22 04:59:05 PM PDT 24
Peak memory 200788 kb
Host smart-c3d9939c-81b4-4331-8a65-6f68e8d21aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785663594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2785663594
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.255283847
Short name T480
Test name
Test status
Simulation time 103066396 ps
CPU time 0.97 seconds
Started Jun 22 04:58:54 PM PDT 24
Finished Jun 22 04:58:56 PM PDT 24
Peak memory 200608 kb
Host smart-cbf0f889-be6f-4cd1-8c51-c481936b3222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255283847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.255283847
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.1060031203
Short name T474
Test name
Test status
Simulation time 108328669 ps
CPU time 1.23 seconds
Started Jun 22 04:58:54 PM PDT 24
Finished Jun 22 04:58:58 PM PDT 24
Peak memory 200792 kb
Host smart-ca6ed0e4-76d1-4410-895c-59978bbb687a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060031203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1060031203
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3752442133
Short name T498
Test name
Test status
Simulation time 9632645907 ps
CPU time 35.17 seconds
Started Jun 22 04:58:59 PM PDT 24
Finished Jun 22 04:59:36 PM PDT 24
Peak memory 200988 kb
Host smart-03237799-507e-4a12-bd25-b394ac22fa8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752442133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3752442133
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.610277266
Short name T352
Test name
Test status
Simulation time 512287626 ps
CPU time 2.84 seconds
Started Jun 22 04:58:56 PM PDT 24
Finished Jun 22 04:59:01 PM PDT 24
Peak memory 200716 kb
Host smart-24aa89a4-fbe4-494b-a514-128cc9c1a02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610277266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.610277266
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3568269242
Short name T147
Test name
Test status
Simulation time 141409447 ps
CPU time 1.18 seconds
Started Jun 22 04:58:53 PM PDT 24
Finished Jun 22 04:58:55 PM PDT 24
Peak memory 200708 kb
Host smart-a4892f57-4189-436a-87b4-179f0a0ca9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568269242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3568269242
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.825975241
Short name T211
Test name
Test status
Simulation time 72067750 ps
CPU time 0.8 seconds
Started Jun 22 04:58:59 PM PDT 24
Finished Jun 22 04:59:03 PM PDT 24
Peak memory 200516 kb
Host smart-21a3bbc7-23b5-4b90-adab-793501af25f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825975241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.825975241
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.773709939
Short name T272
Test name
Test status
Simulation time 244624089 ps
CPU time 1.04 seconds
Started Jun 22 04:58:56 PM PDT 24
Finished Jun 22 04:58:59 PM PDT 24
Peak memory 218112 kb
Host smart-a8468d09-fb9c-486f-95b1-5103dfac0045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773709939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.773709939
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.4064698890
Short name T470
Test name
Test status
Simulation time 173611048 ps
CPU time 0.83 seconds
Started Jun 22 04:58:59 PM PDT 24
Finished Jun 22 04:59:03 PM PDT 24
Peak memory 200508 kb
Host smart-cd6fb514-d72d-44b3-a77b-343bb40e7725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064698890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.4064698890
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1071374836
Short name T90
Test name
Test status
Simulation time 1530076859 ps
CPU time 5.97 seconds
Started Jun 22 04:58:51 PM PDT 24
Finished Jun 22 04:58:58 PM PDT 24
Peak memory 200816 kb
Host smart-3e1b8d96-f5bf-40b3-99b8-2cfc064d95bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071374836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1071374836
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2999162814
Short name T252
Test name
Test status
Simulation time 100326939 ps
CPU time 1.01 seconds
Started Jun 22 04:58:55 PM PDT 24
Finished Jun 22 04:58:58 PM PDT 24
Peak memory 200724 kb
Host smart-75769261-d7d8-40dc-bb19-eaad1d130e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999162814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2999162814
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1632212773
Short name T283
Test name
Test status
Simulation time 251077524 ps
CPU time 1.48 seconds
Started Jun 22 04:58:57 PM PDT 24
Finished Jun 22 04:59:01 PM PDT 24
Peak memory 200744 kb
Host smart-9551b5e5-99e9-4e41-a00d-9d901cfed68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632212773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1632212773
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3891934871
Short name T340
Test name
Test status
Simulation time 467994297 ps
CPU time 2.41 seconds
Started Jun 22 04:58:53 PM PDT 24
Finished Jun 22 04:58:57 PM PDT 24
Peak memory 208916 kb
Host smart-ee66fe7c-2464-4d57-bf66-f8c875ebb575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891934871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3891934871
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1095794635
Short name T527
Test name
Test status
Simulation time 236202043 ps
CPU time 1.4 seconds
Started Jun 22 04:58:54 PM PDT 24
Finished Jun 22 04:58:58 PM PDT 24
Peak memory 200900 kb
Host smart-50531bf9-630f-4873-b596-8bdfde8ad00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095794635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1095794635
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3650066788
Short name T423
Test name
Test status
Simulation time 61067964 ps
CPU time 0.78 seconds
Started Jun 22 04:59:00 PM PDT 24
Finished Jun 22 04:59:04 PM PDT 24
Peak memory 200728 kb
Host smart-3e135f19-ea57-4442-bfe5-eb0e780417a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650066788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3650066788
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3717406897
Short name T425
Test name
Test status
Simulation time 1900005320 ps
CPU time 7.01 seconds
Started Jun 22 04:59:01 PM PDT 24
Finished Jun 22 04:59:11 PM PDT 24
Peak memory 218464 kb
Host smart-2a49f6b4-d447-47e9-95d9-569e5c9c0ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717406897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3717406897
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2435872423
Short name T442
Test name
Test status
Simulation time 244575256 ps
CPU time 1.17 seconds
Started Jun 22 04:59:00 PM PDT 24
Finished Jun 22 04:59:05 PM PDT 24
Peak memory 218080 kb
Host smart-8cd9c431-a4d0-4365-b15c-b0f7a341ac98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435872423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2435872423
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3437204858
Short name T225
Test name
Test status
Simulation time 213152054 ps
CPU time 0.91 seconds
Started Jun 22 04:58:54 PM PDT 24
Finished Jun 22 04:58:56 PM PDT 24
Peak memory 200508 kb
Host smart-43d72170-77ad-4b94-9660-c556262c757a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437204858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3437204858
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2351946947
Short name T241
Test name
Test status
Simulation time 1187500600 ps
CPU time 5.43 seconds
Started Jun 22 04:59:00 PM PDT 24
Finished Jun 22 04:59:09 PM PDT 24
Peak memory 200896 kb
Host smart-8ae2145b-0eb5-4483-8d7a-a7e8de09d3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351946947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2351946947
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3486719011
Short name T320
Test name
Test status
Simulation time 102788403 ps
CPU time 0.99 seconds
Started Jun 22 04:59:02 PM PDT 24
Finished Jun 22 04:59:05 PM PDT 24
Peak memory 200696 kb
Host smart-2a2b2597-a603-48a7-a95d-3b70583d80ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486719011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3486719011
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.360387332
Short name T373
Test name
Test status
Simulation time 112041211 ps
CPU time 1.16 seconds
Started Jun 22 04:58:58 PM PDT 24
Finished Jun 22 04:59:01 PM PDT 24
Peak memory 200848 kb
Host smart-a5114458-245a-4e49-8f27-4f890359fc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360387332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.360387332
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2911334428
Short name T210
Test name
Test status
Simulation time 3667569124 ps
CPU time 14.11 seconds
Started Jun 22 04:59:22 PM PDT 24
Finished Jun 22 04:59:37 PM PDT 24
Peak memory 210820 kb
Host smart-86f96ece-c48c-4b0f-afb4-cd9ab52384e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911334428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2911334428
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1599827700
Short name T80
Test name
Test status
Simulation time 127244919 ps
CPU time 1.51 seconds
Started Jun 22 04:59:05 PM PDT 24
Finished Jun 22 04:59:08 PM PDT 24
Peak memory 200712 kb
Host smart-e51c8409-bf47-4fb4-b30b-5adb2c9a6949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599827700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1599827700
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2795202290
Short name T212
Test name
Test status
Simulation time 210078990 ps
CPU time 1.3 seconds
Started Jun 22 04:59:07 PM PDT 24
Finished Jun 22 04:59:09 PM PDT 24
Peak memory 200692 kb
Host smart-391a01e9-771b-4f31-900f-d514fcd833f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795202290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2795202290
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.709858533
Short name T179
Test name
Test status
Simulation time 64245507 ps
CPU time 0.83 seconds
Started Jun 22 04:58:14 PM PDT 24
Finished Jun 22 04:58:16 PM PDT 24
Peak memory 200516 kb
Host smart-2826546b-7f92-4939-ba3d-6f54067e4ea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709858533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.709858533
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.395051055
Short name T451
Test name
Test status
Simulation time 2353642387 ps
CPU time 7.88 seconds
Started Jun 22 04:58:14 PM PDT 24
Finished Jun 22 04:58:23 PM PDT 24
Peak memory 222520 kb
Host smart-f8addc2c-d130-4b0b-8508-1faecc8771cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395051055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.395051055
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.143521302
Short name T456
Test name
Test status
Simulation time 244441601 ps
CPU time 1.09 seconds
Started Jun 22 04:58:14 PM PDT 24
Finished Jun 22 04:58:17 PM PDT 24
Peak memory 218040 kb
Host smart-a4768acd-451f-4b16-aebc-94d32df15c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143521302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.143521302
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1546797603
Short name T278
Test name
Test status
Simulation time 106238330 ps
CPU time 0.84 seconds
Started Jun 22 04:58:13 PM PDT 24
Finished Jun 22 04:58:15 PM PDT 24
Peak memory 200508 kb
Host smart-a5236166-72a4-444c-83d8-77fa0ce8f86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546797603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1546797603
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2906621023
Short name T379
Test name
Test status
Simulation time 1987543712 ps
CPU time 8.01 seconds
Started Jun 22 04:58:13 PM PDT 24
Finished Jun 22 04:58:22 PM PDT 24
Peak memory 200856 kb
Host smart-ad2171d6-958a-4eef-94d3-ae2a7df7448c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906621023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2906621023
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3112642789
Short name T64
Test name
Test status
Simulation time 8534175909 ps
CPU time 14.4 seconds
Started Jun 22 04:58:14 PM PDT 24
Finished Jun 22 04:58:30 PM PDT 24
Peak memory 217596 kb
Host smart-f5128dfe-22da-4350-ab47-537d3db79af6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112642789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3112642789
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3147938371
Short name T10
Test name
Test status
Simulation time 100699433 ps
CPU time 1.01 seconds
Started Jun 22 04:58:14 PM PDT 24
Finished Jun 22 04:58:16 PM PDT 24
Peak memory 200708 kb
Host smart-ac0b47a3-7be9-421a-a9c9-1360fae98b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147938371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3147938371
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.345965373
Short name T232
Test name
Test status
Simulation time 115319946 ps
CPU time 1.17 seconds
Started Jun 22 04:58:15 PM PDT 24
Finished Jun 22 04:58:18 PM PDT 24
Peak memory 200848 kb
Host smart-e0548806-fb7b-4ad3-95b2-c91900571632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345965373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.345965373
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1424184814
Short name T146
Test name
Test status
Simulation time 133080775 ps
CPU time 1.65 seconds
Started Jun 22 04:58:12 PM PDT 24
Finished Jun 22 04:58:15 PM PDT 24
Peak memory 200700 kb
Host smart-59743a9b-8a61-42a0-a636-f9f9cabc674a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424184814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1424184814
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.1776405136
Short name T149
Test name
Test status
Simulation time 160815403 ps
CPU time 1.08 seconds
Started Jun 22 04:58:14 PM PDT 24
Finished Jun 22 04:58:17 PM PDT 24
Peak memory 200724 kb
Host smart-249745f5-fedd-47d8-a657-3fd4ed7779e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776405136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1776405136
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.612433252
Short name T410
Test name
Test status
Simulation time 63624259 ps
CPU time 0.79 seconds
Started Jun 22 04:59:13 PM PDT 24
Finished Jun 22 04:59:15 PM PDT 24
Peak memory 200516 kb
Host smart-8369e866-5fc6-4dfd-9f06-42388f83d3b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612433252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.612433252
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.2367265721
Short name T35
Test name
Test status
Simulation time 2378556435 ps
CPU time 8.17 seconds
Started Jun 22 04:59:03 PM PDT 24
Finished Jun 22 04:59:14 PM PDT 24
Peak memory 218128 kb
Host smart-41e720d0-2d58-4f09-9687-20f5ca73843a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367265721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2367265721
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.4143060895
Short name T128
Test name
Test status
Simulation time 246398788 ps
CPU time 1.07 seconds
Started Jun 22 04:59:06 PM PDT 24
Finished Jun 22 04:59:09 PM PDT 24
Peak memory 218084 kb
Host smart-59293f3d-ef9e-4325-a718-be3da5e2a9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143060895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.4143060895
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2726963985
Short name T275
Test name
Test status
Simulation time 157990514 ps
CPU time 0.9 seconds
Started Jun 22 04:59:07 PM PDT 24
Finished Jun 22 04:59:09 PM PDT 24
Peak memory 200500 kb
Host smart-c41afb68-b071-4003-8777-7b5d9b4839d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726963985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2726963985
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3982938700
Short name T169
Test name
Test status
Simulation time 833202958 ps
CPU time 4.31 seconds
Started Jun 22 04:59:03 PM PDT 24
Finished Jun 22 04:59:09 PM PDT 24
Peak memory 200876 kb
Host smart-1aeb66ec-e2df-4634-9f53-a75f3ac97d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982938700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3982938700
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.304816935
Short name T251
Test name
Test status
Simulation time 152619616 ps
CPU time 1.13 seconds
Started Jun 22 04:59:01 PM PDT 24
Finished Jun 22 04:59:05 PM PDT 24
Peak memory 200720 kb
Host smart-e080148e-ddbe-4c95-b164-fe30028c14e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304816935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.304816935
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2954312870
Short name T136
Test name
Test status
Simulation time 116071429 ps
CPU time 1.18 seconds
Started Jun 22 04:59:05 PM PDT 24
Finished Jun 22 04:59:08 PM PDT 24
Peak memory 200948 kb
Host smart-4b1df10c-d572-436d-b678-947ec569d156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954312870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2954312870
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2107389594
Short name T376
Test name
Test status
Simulation time 6701009658 ps
CPU time 22.23 seconds
Started Jun 22 04:59:05 PM PDT 24
Finished Jun 22 04:59:29 PM PDT 24
Peak memory 209124 kb
Host smart-f1e4eee3-b48f-4503-8037-74f908d011cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107389594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2107389594
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.2776673954
Short name T334
Test name
Test status
Simulation time 369825139 ps
CPU time 2.39 seconds
Started Jun 22 04:59:00 PM PDT 24
Finished Jun 22 04:59:06 PM PDT 24
Peak memory 200656 kb
Host smart-557ff1a9-4b83-4764-a4bd-6affce12d84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776673954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2776673954
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2672266645
Short name T485
Test name
Test status
Simulation time 140243462 ps
CPU time 1.19 seconds
Started Jun 22 04:58:58 PM PDT 24
Finished Jun 22 04:59:02 PM PDT 24
Peak memory 200724 kb
Host smart-0d6cfaa0-5e49-460d-ac4b-d5a0dc87411a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672266645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2672266645
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.4288936480
Short name T319
Test name
Test status
Simulation time 77610687 ps
CPU time 0.82 seconds
Started Jun 22 04:59:01 PM PDT 24
Finished Jun 22 04:59:04 PM PDT 24
Peak memory 200508 kb
Host smart-3b73f219-41b9-49d8-bf86-8991be882588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288936480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.4288936480
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.309631172
Short name T289
Test name
Test status
Simulation time 1227081757 ps
CPU time 5.78 seconds
Started Jun 22 04:59:00 PM PDT 24
Finished Jun 22 04:59:09 PM PDT 24
Peak memory 218432 kb
Host smart-ff8491e5-f416-4b9f-828a-0ef3d59b1bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309631172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.309631172
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.671993512
Short name T141
Test name
Test status
Simulation time 244403085 ps
CPU time 1.06 seconds
Started Jun 22 04:59:08 PM PDT 24
Finished Jun 22 04:59:15 PM PDT 24
Peak memory 218080 kb
Host smart-9d39212d-f0f0-4a2c-9980-92d4cb5d4775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671993512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.671993512
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1686648127
Short name T502
Test name
Test status
Simulation time 169823448 ps
CPU time 0.83 seconds
Started Jun 22 04:59:07 PM PDT 24
Finished Jun 22 04:59:09 PM PDT 24
Peak memory 200488 kb
Host smart-0c44352d-af43-4d58-a48a-b8ae04470060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686648127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1686648127
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3942267691
Short name T338
Test name
Test status
Simulation time 1922494649 ps
CPU time 7.08 seconds
Started Jun 22 04:59:03 PM PDT 24
Finished Jun 22 04:59:12 PM PDT 24
Peak memory 200888 kb
Host smart-fc3a2368-ce2f-4d7a-9419-ca8e1ddc10d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942267691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3942267691
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.4035814247
Short name T177
Test name
Test status
Simulation time 153120783 ps
CPU time 1.11 seconds
Started Jun 22 04:59:08 PM PDT 24
Finished Jun 22 04:59:11 PM PDT 24
Peak memory 200708 kb
Host smart-247706ef-8c95-4a13-90b8-6899233eac50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035814247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.4035814247
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1363313953
Short name T444
Test name
Test status
Simulation time 193069805 ps
CPU time 1.36 seconds
Started Jun 22 04:59:05 PM PDT 24
Finished Jun 22 04:59:08 PM PDT 24
Peak memory 200908 kb
Host smart-9bff5447-87af-47f3-a7cd-1ec914471a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363313953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1363313953
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3791648317
Short name T276
Test name
Test status
Simulation time 11522499601 ps
CPU time 40.36 seconds
Started Jun 22 04:59:05 PM PDT 24
Finished Jun 22 04:59:47 PM PDT 24
Peak memory 209156 kb
Host smart-c3c20d29-ccff-4d3a-864e-1714f89fb060
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791648317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3791648317
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.4008777990
Short name T359
Test name
Test status
Simulation time 358116872 ps
CPU time 2.22 seconds
Started Jun 22 04:59:05 PM PDT 24
Finished Jun 22 04:59:09 PM PDT 24
Peak memory 208916 kb
Host smart-46963276-7d70-4e6f-a1ff-1355f123c347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008777990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.4008777990
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1901736791
Short name T222
Test name
Test status
Simulation time 151702352 ps
CPU time 1.35 seconds
Started Jun 22 04:59:01 PM PDT 24
Finished Jun 22 04:59:05 PM PDT 24
Peak memory 200864 kb
Host smart-db16eeeb-6da4-443e-a658-dfd499e54b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901736791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1901736791
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.320834741
Short name T127
Test name
Test status
Simulation time 68868450 ps
CPU time 0.82 seconds
Started Jun 22 04:59:02 PM PDT 24
Finished Jun 22 04:59:05 PM PDT 24
Peak memory 200508 kb
Host smart-ea52841c-181b-4b4d-a5a7-53acc6aa9f7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320834741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.320834741
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3199477075
Short name T436
Test name
Test status
Simulation time 243607392 ps
CPU time 1.12 seconds
Started Jun 22 04:59:02 PM PDT 24
Finished Jun 22 04:59:05 PM PDT 24
Peak memory 218080 kb
Host smart-63a8f3fb-5069-4e4c-9ff4-efc86b84604c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199477075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3199477075
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1590157568
Short name T446
Test name
Test status
Simulation time 216079404 ps
CPU time 0.92 seconds
Started Jun 22 04:59:00 PM PDT 24
Finished Jun 22 04:59:04 PM PDT 24
Peak memory 200472 kb
Host smart-f96795e8-cb8d-4ecc-ad5d-0b180543ab06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590157568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1590157568
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1193952638
Short name T188
Test name
Test status
Simulation time 1268117027 ps
CPU time 5.08 seconds
Started Jun 22 04:59:15 PM PDT 24
Finished Jun 22 04:59:21 PM PDT 24
Peak memory 200884 kb
Host smart-e0ea7ea8-82e9-4885-9fb2-fbe914fe98dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193952638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1193952638
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3484299344
Short name T462
Test name
Test status
Simulation time 138908499 ps
CPU time 1.16 seconds
Started Jun 22 04:59:02 PM PDT 24
Finished Jun 22 04:59:06 PM PDT 24
Peak memory 200700 kb
Host smart-1ae258d7-7d6f-4849-b993-3c09cd5474cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484299344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3484299344
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2900541460
Short name T364
Test name
Test status
Simulation time 115995652 ps
CPU time 1.18 seconds
Started Jun 22 04:59:14 PM PDT 24
Finished Jun 22 04:59:16 PM PDT 24
Peak memory 200868 kb
Host smart-5b83fb92-f6ec-4598-9519-71c0efa385e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900541460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2900541460
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1626349849
Short name T76
Test name
Test status
Simulation time 9712159590 ps
CPU time 34.74 seconds
Started Jun 22 04:59:00 PM PDT 24
Finished Jun 22 04:59:38 PM PDT 24
Peak memory 217296 kb
Host smart-64bd265e-1ae0-47a6-8e1d-152bf309f5ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626349849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1626349849
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.1788114223
Short name T154
Test name
Test status
Simulation time 137817345 ps
CPU time 1.73 seconds
Started Jun 22 04:59:00 PM PDT 24
Finished Jun 22 04:59:05 PM PDT 24
Peak memory 200692 kb
Host smart-d101dff1-b4da-4aac-95c4-1d8b580d00dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788114223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1788114223
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.405888394
Short name T452
Test name
Test status
Simulation time 156112237 ps
CPU time 1.24 seconds
Started Jun 22 04:59:04 PM PDT 24
Finished Jun 22 04:59:08 PM PDT 24
Peak memory 201040 kb
Host smart-8a3a6f71-5ff2-4a82-a30a-e8531cef8e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405888394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.405888394
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1110361319
Short name T459
Test name
Test status
Simulation time 73076219 ps
CPU time 0.87 seconds
Started Jun 22 04:59:08 PM PDT 24
Finished Jun 22 04:59:10 PM PDT 24
Peak memory 200492 kb
Host smart-e291cd5e-499a-489b-b97c-99360b5feba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110361319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1110361319
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2487422900
Short name T34
Test name
Test status
Simulation time 1228451637 ps
CPU time 5.57 seconds
Started Jun 22 04:59:01 PM PDT 24
Finished Jun 22 04:59:09 PM PDT 24
Peak memory 218444 kb
Host smart-f4ade419-6d91-49f3-bddb-3f9f7d4c7261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487422900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2487422900
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1134810753
Short name T170
Test name
Test status
Simulation time 245784011 ps
CPU time 1.03 seconds
Started Jun 22 04:59:06 PM PDT 24
Finished Jun 22 04:59:08 PM PDT 24
Peak memory 218052 kb
Host smart-8a026915-b7dd-4d36-8c0d-5ae60daf29f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134810753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1134810753
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1943108180
Short name T260
Test name
Test status
Simulation time 90953617 ps
CPU time 0.77 seconds
Started Jun 22 04:59:13 PM PDT 24
Finished Jun 22 04:59:15 PM PDT 24
Peak memory 200464 kb
Host smart-d70aa011-1bc6-4c2b-864d-67abf1f670c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943108180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1943108180
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.4236597992
Short name T220
Test name
Test status
Simulation time 950664703 ps
CPU time 4.96 seconds
Started Jun 22 04:59:01 PM PDT 24
Finished Jun 22 04:59:09 PM PDT 24
Peak memory 200912 kb
Host smart-9a3ae12b-2598-46cb-b1b3-dfa04c5c1397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236597992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.4236597992
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.372176901
Short name T398
Test name
Test status
Simulation time 109829089 ps
CPU time 1.1 seconds
Started Jun 22 04:59:06 PM PDT 24
Finished Jun 22 04:59:08 PM PDT 24
Peak memory 200724 kb
Host smart-c936f979-8ee2-4672-ba0e-3570e74e8478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372176901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.372176901
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.421515264
Short name T201
Test name
Test status
Simulation time 116161300 ps
CPU time 1.24 seconds
Started Jun 22 04:59:01 PM PDT 24
Finished Jun 22 04:59:05 PM PDT 24
Peak memory 201072 kb
Host smart-c783b362-1222-40a3-aabd-c6e41be2bb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421515264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.421515264
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.788817416
Short name T434
Test name
Test status
Simulation time 14450478860 ps
CPU time 48.47 seconds
Started Jun 22 04:59:14 PM PDT 24
Finished Jun 22 05:00:03 PM PDT 24
Peak memory 209152 kb
Host smart-458e23b5-888a-4dbd-991b-9b0c57f9a3cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788817416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.788817416
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2382409547
Short name T539
Test name
Test status
Simulation time 325038851 ps
CPU time 2.27 seconds
Started Jun 22 04:59:00 PM PDT 24
Finished Jun 22 04:59:06 PM PDT 24
Peak memory 200644 kb
Host smart-95ea45ea-1510-422d-8f28-5ec7c68c4e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382409547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2382409547
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.1555630386
Short name T482
Test name
Test status
Simulation time 61605355 ps
CPU time 0.74 seconds
Started Jun 22 04:59:06 PM PDT 24
Finished Jun 22 04:59:08 PM PDT 24
Peak memory 200684 kb
Host smart-b69236df-33c5-4a57-adfe-343d4b2bcf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555630386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1555630386
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.820496454
Short name T71
Test name
Test status
Simulation time 68956413 ps
CPU time 0.78 seconds
Started Jun 22 04:59:07 PM PDT 24
Finished Jun 22 04:59:09 PM PDT 24
Peak memory 200496 kb
Host smart-1be71c65-3e26-400f-809b-234f95e94e68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820496454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.820496454
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.593234705
Short name T337
Test name
Test status
Simulation time 1902624751 ps
CPU time 6.68 seconds
Started Jun 22 04:59:10 PM PDT 24
Finished Jun 22 04:59:19 PM PDT 24
Peak memory 222420 kb
Host smart-c574dac9-e3ae-40fb-bef1-19f665bf6f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593234705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.593234705
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2526217002
Short name T126
Test name
Test status
Simulation time 244115989 ps
CPU time 1.08 seconds
Started Jun 22 04:59:06 PM PDT 24
Finished Jun 22 04:59:09 PM PDT 24
Peak memory 218040 kb
Host smart-348cea8a-20f5-4a80-b458-b61ad73503a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526217002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2526217002
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2807676999
Short name T22
Test name
Test status
Simulation time 120035128 ps
CPU time 0.82 seconds
Started Jun 22 04:59:08 PM PDT 24
Finished Jun 22 04:59:11 PM PDT 24
Peak memory 200452 kb
Host smart-21bf1743-c926-4524-ad62-aa12471e9992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807676999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2807676999
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.757068862
Short name T302
Test name
Test status
Simulation time 1183674395 ps
CPU time 5.16 seconds
Started Jun 22 04:59:02 PM PDT 24
Finished Jun 22 04:59:10 PM PDT 24
Peak memory 200880 kb
Host smart-2cc7195c-4bf8-4fea-baab-b1154d71d8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757068862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.757068862
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1839877270
Short name T274
Test name
Test status
Simulation time 105624342 ps
CPU time 1.07 seconds
Started Jun 22 04:59:00 PM PDT 24
Finished Jun 22 04:59:05 PM PDT 24
Peak memory 200708 kb
Host smart-eeef803d-69a0-46b4-b797-b58b078e744a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839877270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1839877270
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.293325768
Short name T531
Test name
Test status
Simulation time 229525122 ps
CPU time 1.49 seconds
Started Jun 22 04:59:00 PM PDT 24
Finished Jun 22 04:59:05 PM PDT 24
Peak memory 200820 kb
Host smart-9d449c71-181a-468c-8ad6-98b7af371785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293325768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.293325768
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3904031409
Short name T190
Test name
Test status
Simulation time 2308416073 ps
CPU time 10.33 seconds
Started Jun 22 04:59:05 PM PDT 24
Finished Jun 22 04:59:17 PM PDT 24
Peak memory 209148 kb
Host smart-829675d9-46a2-454d-9627-ec2cd824caa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904031409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3904031409
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3743659362
Short name T242
Test name
Test status
Simulation time 361953731 ps
CPU time 2.03 seconds
Started Jun 22 04:59:07 PM PDT 24
Finished Jun 22 04:59:10 PM PDT 24
Peak memory 200696 kb
Host smart-6a30e6fd-1638-4969-a5e1-ad2586feffdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743659362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3743659362
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1687385822
Short name T469
Test name
Test status
Simulation time 116408056 ps
CPU time 1.04 seconds
Started Jun 22 04:59:22 PM PDT 24
Finished Jun 22 04:59:24 PM PDT 24
Peak memory 200724 kb
Host smart-c59e2042-c4a9-4a3d-8f13-d8355890049d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687385822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1687385822
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2163516248
Short name T366
Test name
Test status
Simulation time 62494469 ps
CPU time 0.79 seconds
Started Jun 22 04:59:02 PM PDT 24
Finished Jun 22 04:59:05 PM PDT 24
Peak memory 200732 kb
Host smart-4d2a185b-e20b-4a85-b379-7a663514a56d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163516248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2163516248
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3082986652
Short name T31
Test name
Test status
Simulation time 1229202051 ps
CPU time 5.94 seconds
Started Jun 22 04:59:03 PM PDT 24
Finished Jun 22 04:59:11 PM PDT 24
Peak memory 222728 kb
Host smart-ddd868aa-6fe5-4185-9645-6ffb3640b85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082986652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3082986652
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3859610714
Short name T24
Test name
Test status
Simulation time 243989400 ps
CPU time 1.12 seconds
Started Jun 22 04:59:03 PM PDT 24
Finished Jun 22 04:59:06 PM PDT 24
Peak memory 218312 kb
Host smart-f40f6a0b-f751-413a-8671-003292a5409a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859610714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3859610714
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1859728292
Short name T297
Test name
Test status
Simulation time 121442837 ps
CPU time 0.8 seconds
Started Jun 22 04:59:02 PM PDT 24
Finished Jun 22 04:59:05 PM PDT 24
Peak memory 200500 kb
Host smart-eee611fb-739f-4500-a06b-05f10a22a0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859728292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1859728292
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.769264074
Short name T476
Test name
Test status
Simulation time 1822797425 ps
CPU time 6.56 seconds
Started Jun 22 04:59:04 PM PDT 24
Finished Jun 22 04:59:13 PM PDT 24
Peak memory 200880 kb
Host smart-731efe40-e343-456c-90d0-55827062a77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769264074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.769264074
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3253446282
Short name T514
Test name
Test status
Simulation time 151320905 ps
CPU time 1.2 seconds
Started Jun 22 04:59:00 PM PDT 24
Finished Jun 22 04:59:05 PM PDT 24
Peak memory 200700 kb
Host smart-f85090ce-e56c-468a-855e-a0c08d2826df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253446282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3253446282
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1057960821
Short name T152
Test name
Test status
Simulation time 229659768 ps
CPU time 1.58 seconds
Started Jun 22 04:59:00 PM PDT 24
Finished Jun 22 04:59:05 PM PDT 24
Peak memory 200892 kb
Host smart-3238fc9c-35ca-4453-bef6-8fe641c9ba1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057960821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1057960821
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3969376658
Short name T253
Test name
Test status
Simulation time 6574585268 ps
CPU time 25.07 seconds
Started Jun 22 04:59:07 PM PDT 24
Finished Jun 22 04:59:34 PM PDT 24
Peak memory 200932 kb
Host smart-008d5526-ce4f-400d-83a4-6378c404db16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969376658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3969376658
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3808334364
Short name T435
Test name
Test status
Simulation time 465453896 ps
CPU time 2.41 seconds
Started Jun 22 04:59:09 PM PDT 24
Finished Jun 22 04:59:14 PM PDT 24
Peak memory 200704 kb
Host smart-273a7817-ee4e-48af-a0ef-ac50fa474b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808334364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3808334364
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2536886777
Short name T173
Test name
Test status
Simulation time 158327210 ps
CPU time 1.25 seconds
Started Jun 22 04:59:08 PM PDT 24
Finished Jun 22 04:59:11 PM PDT 24
Peak memory 200692 kb
Host smart-79dfbee0-b7ce-434e-bb42-dc62de0d038b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536886777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2536886777
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.754389005
Short name T299
Test name
Test status
Simulation time 72535636 ps
CPU time 0.77 seconds
Started Jun 22 04:59:14 PM PDT 24
Finished Jun 22 04:59:16 PM PDT 24
Peak memory 200480 kb
Host smart-a4fa9c55-7765-40f8-a508-96286397ba81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754389005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.754389005
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.4236412063
Short name T455
Test name
Test status
Simulation time 1233591474 ps
CPU time 5.86 seconds
Started Jun 22 04:59:14 PM PDT 24
Finished Jun 22 04:59:21 PM PDT 24
Peak memory 218520 kb
Host smart-48e6deff-6f5f-4280-9f19-ca3ab8b2fb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236412063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.4236412063
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2046248477
Short name T267
Test name
Test status
Simulation time 244945064 ps
CPU time 1.07 seconds
Started Jun 22 04:59:28 PM PDT 24
Finished Jun 22 04:59:29 PM PDT 24
Peak memory 219072 kb
Host smart-360e46fa-9dc9-4e28-b222-e76e1a93dd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046248477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2046248477
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3280926697
Short name T236
Test name
Test status
Simulation time 109994196 ps
CPU time 0.76 seconds
Started Jun 22 04:59:12 PM PDT 24
Finished Jun 22 04:59:14 PM PDT 24
Peak memory 200412 kb
Host smart-a65ff1a5-31bd-4892-878e-3c4c29da69c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280926697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3280926697
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.2750103983
Short name T478
Test name
Test status
Simulation time 2047842929 ps
CPU time 7.29 seconds
Started Jun 22 04:59:10 PM PDT 24
Finished Jun 22 04:59:19 PM PDT 24
Peak memory 200872 kb
Host smart-282d6b88-c75a-4973-ba92-2fc490db1d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750103983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2750103983
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.477728321
Short name T397
Test name
Test status
Simulation time 152906816 ps
CPU time 1.17 seconds
Started Jun 22 04:59:22 PM PDT 24
Finished Jun 22 04:59:23 PM PDT 24
Peak memory 200948 kb
Host smart-32bcafb7-73bd-42c5-9a06-5aa8b697246b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477728321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.477728321
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.78606636
Short name T512
Test name
Test status
Simulation time 202700074 ps
CPU time 1.47 seconds
Started Jun 22 04:59:00 PM PDT 24
Finished Jun 22 04:59:04 PM PDT 24
Peak memory 200892 kb
Host smart-e3c8f602-f324-4d6b-bcf4-71964ba865c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78606636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.78606636
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1261659228
Short name T431
Test name
Test status
Simulation time 8800854668 ps
CPU time 32.3 seconds
Started Jun 22 04:59:25 PM PDT 24
Finished Jun 22 04:59:57 PM PDT 24
Peak memory 200992 kb
Host smart-fb339305-9d7e-413c-b08e-e477f5465f01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261659228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1261659228
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1094981139
Short name T135
Test name
Test status
Simulation time 288949650 ps
CPU time 1.94 seconds
Started Jun 22 04:59:14 PM PDT 24
Finished Jun 22 04:59:17 PM PDT 24
Peak memory 208792 kb
Host smart-6fb7ba79-03c9-4d7d-b10c-d0f0e1c2ba65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094981139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1094981139
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.4001274950
Short name T204
Test name
Test status
Simulation time 251833285 ps
CPU time 1.42 seconds
Started Jun 22 04:59:06 PM PDT 24
Finished Jun 22 04:59:08 PM PDT 24
Peak memory 200728 kb
Host smart-3481320c-d41a-4f18-8466-c85c79305400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001274950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.4001274950
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.687450572
Short name T181
Test name
Test status
Simulation time 71029990 ps
CPU time 0.83 seconds
Started Jun 22 04:59:13 PM PDT 24
Finished Jun 22 04:59:15 PM PDT 24
Peak memory 200516 kb
Host smart-a1339e2b-6277-491a-bb02-a8513026ad4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687450572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.687450572
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.793354391
Short name T347
Test name
Test status
Simulation time 1227465992 ps
CPU time 6.17 seconds
Started Jun 22 04:59:18 PM PDT 24
Finished Jun 22 04:59:25 PM PDT 24
Peak memory 218480 kb
Host smart-7329fb80-de53-4155-b271-389f27252245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793354391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.793354391
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1944283206
Short name T391
Test name
Test status
Simulation time 243500066 ps
CPU time 1.16 seconds
Started Jun 22 04:59:11 PM PDT 24
Finished Jun 22 04:59:14 PM PDT 24
Peak memory 218064 kb
Host smart-a51424e2-7b45-4df7-bbea-87e461f19f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944283206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1944283206
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2166579785
Short name T355
Test name
Test status
Simulation time 173157924 ps
CPU time 0.91 seconds
Started Jun 22 04:59:08 PM PDT 24
Finished Jun 22 04:59:11 PM PDT 24
Peak memory 200504 kb
Host smart-77656f8a-cbd9-4ecb-ba0a-debab3119f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166579785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2166579785
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.4040736345
Short name T101
Test name
Test status
Simulation time 784073767 ps
CPU time 3.69 seconds
Started Jun 22 04:59:08 PM PDT 24
Finished Jun 22 04:59:14 PM PDT 24
Peak memory 200896 kb
Host smart-4c5ebc80-bfe3-4200-93d7-5298839c3b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040736345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.4040736345
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.1877051180
Short name T407
Test name
Test status
Simulation time 180778355 ps
CPU time 1.21 seconds
Started Jun 22 04:59:09 PM PDT 24
Finished Jun 22 04:59:12 PM PDT 24
Peak memory 200728 kb
Host smart-f2459f22-2102-4069-b3eb-9c9745154de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877051180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.1877051180
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2337411842
Short name T532
Test name
Test status
Simulation time 195237307 ps
CPU time 1.32 seconds
Started Jun 22 04:59:15 PM PDT 24
Finished Jun 22 04:59:18 PM PDT 24
Peak memory 200916 kb
Host smart-c8e0dc36-695b-4250-a95c-f2702d5cd5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337411842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2337411842
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.79968412
Short name T271
Test name
Test status
Simulation time 986876155 ps
CPU time 4.66 seconds
Started Jun 22 04:59:09 PM PDT 24
Finished Jun 22 04:59:15 PM PDT 24
Peak memory 200844 kb
Host smart-a368508d-694c-4d56-82fa-5749cdef25c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79968412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.79968412
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.379741897
Short name T447
Test name
Test status
Simulation time 545532176 ps
CPU time 2.67 seconds
Started Jun 22 04:59:24 PM PDT 24
Finished Jun 22 04:59:27 PM PDT 24
Peak memory 200712 kb
Host smart-ddefbb42-166d-4cd3-8e3d-23e421a27d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379741897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.379741897
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1983459528
Short name T440
Test name
Test status
Simulation time 171821508 ps
CPU time 1.29 seconds
Started Jun 22 04:59:19 PM PDT 24
Finished Jun 22 04:59:21 PM PDT 24
Peak memory 200948 kb
Host smart-c63405cd-3908-4c81-9c82-db71308765f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983459528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1983459528
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2236963732
Short name T384
Test name
Test status
Simulation time 75439052 ps
CPU time 0.8 seconds
Started Jun 22 04:59:12 PM PDT 24
Finished Jun 22 04:59:14 PM PDT 24
Peak memory 200412 kb
Host smart-7e69d010-1bd1-41d5-a8d5-22794868ca77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236963732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2236963732
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3059391225
Short name T33
Test name
Test status
Simulation time 1223701175 ps
CPU time 5.59 seconds
Started Jun 22 04:59:09 PM PDT 24
Finished Jun 22 04:59:21 PM PDT 24
Peak memory 218432 kb
Host smart-a0044996-8095-4ab3-82ef-289cc643dc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059391225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3059391225
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.831510845
Short name T483
Test name
Test status
Simulation time 244529905 ps
CPU time 1.05 seconds
Started Jun 22 04:59:25 PM PDT 24
Finished Jun 22 04:59:27 PM PDT 24
Peak memory 218092 kb
Host smart-80567892-6ffb-40bd-9223-91e8b74c5e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831510845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.831510845
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3874386558
Short name T14
Test name
Test status
Simulation time 216989044 ps
CPU time 0.92 seconds
Started Jun 22 04:59:17 PM PDT 24
Finished Jun 22 04:59:19 PM PDT 24
Peak memory 200496 kb
Host smart-be8f6c11-e192-4289-bc35-4db1a3a04088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874386558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3874386558
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.734683951
Short name T424
Test name
Test status
Simulation time 1485749652 ps
CPU time 5.68 seconds
Started Jun 22 04:59:15 PM PDT 24
Finished Jun 22 04:59:22 PM PDT 24
Peak memory 200884 kb
Host smart-dbe3a876-5437-4f42-acfa-7e91678c606d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734683951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.734683951
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3776466762
Short name T257
Test name
Test status
Simulation time 160982783 ps
CPU time 1.1 seconds
Started Jun 22 04:59:07 PM PDT 24
Finished Jun 22 04:59:10 PM PDT 24
Peak memory 200712 kb
Host smart-1c0e245d-d8c3-4ddc-ac12-58552146717f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776466762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3776466762
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2975843845
Short name T472
Test name
Test status
Simulation time 120901924 ps
CPU time 1.26 seconds
Started Jun 22 04:59:22 PM PDT 24
Finished Jun 22 04:59:24 PM PDT 24
Peak memory 201128 kb
Host smart-4f95e62f-5c0d-446b-8609-de73b341ccd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975843845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2975843845
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3790076422
Short name T93
Test name
Test status
Simulation time 7400583420 ps
CPU time 33.21 seconds
Started Jun 22 04:59:18 PM PDT 24
Finished Jun 22 04:59:52 PM PDT 24
Peak memory 200960 kb
Host smart-500f9fe3-d555-4189-832a-be0b35c028fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790076422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3790076422
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3015309523
Short name T12
Test name
Test status
Simulation time 382368082 ps
CPU time 2.51 seconds
Started Jun 22 04:59:07 PM PDT 24
Finished Jun 22 04:59:11 PM PDT 24
Peak memory 200716 kb
Host smart-27bbdd36-ef29-4064-a20f-d7d1423f2f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015309523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3015309523
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1519598757
Short name T255
Test name
Test status
Simulation time 66189916 ps
CPU time 0.8 seconds
Started Jun 22 04:59:10 PM PDT 24
Finished Jun 22 04:59:13 PM PDT 24
Peak memory 200700 kb
Host smart-4a1f6e08-6d4c-44a1-9b3c-a759c085e984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519598757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1519598757
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.2388652307
Short name T165
Test name
Test status
Simulation time 71273869 ps
CPU time 0.77 seconds
Started Jun 22 04:59:08 PM PDT 24
Finished Jun 22 04:59:11 PM PDT 24
Peak memory 200492 kb
Host smart-82e682aa-9d86-470e-9f21-303871139141
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388652307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2388652307
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3892004108
Short name T508
Test name
Test status
Simulation time 1236665229 ps
CPU time 5.14 seconds
Started Jun 22 04:59:25 PM PDT 24
Finished Jun 22 04:59:31 PM PDT 24
Peak memory 230636 kb
Host smart-d7cd40b0-9d08-42ff-b113-d2e44508296a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892004108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3892004108
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2223185648
Short name T9
Test name
Test status
Simulation time 244207500 ps
CPU time 1.17 seconds
Started Jun 22 04:59:08 PM PDT 24
Finished Jun 22 04:59:11 PM PDT 24
Peak memory 218008 kb
Host smart-5b980d3a-2b44-4e95-a51e-405e4f93747a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223185648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2223185648
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1866026559
Short name T21
Test name
Test status
Simulation time 183989284 ps
CPU time 0.88 seconds
Started Jun 22 04:59:16 PM PDT 24
Finished Jun 22 04:59:18 PM PDT 24
Peak memory 200512 kb
Host smart-b4d60ceb-6f58-4f3a-a0ec-0aeaae6331a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866026559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1866026559
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2188954145
Short name T329
Test name
Test status
Simulation time 1275879888 ps
CPU time 5.02 seconds
Started Jun 22 04:59:09 PM PDT 24
Finished Jun 22 04:59:16 PM PDT 24
Peak memory 200952 kb
Host smart-a93876d1-1eab-4811-9ef7-6b18aaa31137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188954145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2188954145
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3100887187
Short name T504
Test name
Test status
Simulation time 182666092 ps
CPU time 1.24 seconds
Started Jun 22 04:59:10 PM PDT 24
Finished Jun 22 04:59:13 PM PDT 24
Peak memory 200708 kb
Host smart-68f81e32-9078-4b53-a2fb-9760a9e7096f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100887187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3100887187
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1887585184
Short name T324
Test name
Test status
Simulation time 230564640 ps
CPU time 1.45 seconds
Started Jun 22 04:59:18 PM PDT 24
Finished Jun 22 04:59:21 PM PDT 24
Peak memory 200912 kb
Host smart-2852839d-d287-45a2-8233-1f7e8170f45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887585184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1887585184
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1357301748
Short name T343
Test name
Test status
Simulation time 5966585605 ps
CPU time 26.36 seconds
Started Jun 22 04:59:12 PM PDT 24
Finished Jun 22 04:59:39 PM PDT 24
Peak memory 209176 kb
Host smart-3a018d46-1103-4d5d-aec8-73de7fa4042a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357301748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1357301748
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.282247717
Short name T218
Test name
Test status
Simulation time 375954249 ps
CPU time 2.39 seconds
Started Jun 22 04:59:17 PM PDT 24
Finished Jun 22 04:59:20 PM PDT 24
Peak memory 200936 kb
Host smart-b3335f83-eaf5-4ddd-afe2-806c501858b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282247717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.282247717
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2476902167
Short name T176
Test name
Test status
Simulation time 287900134 ps
CPU time 1.52 seconds
Started Jun 22 04:59:12 PM PDT 24
Finished Jun 22 04:59:15 PM PDT 24
Peak memory 200896 kb
Host smart-177de413-119d-48a6-ae6a-440ba1b5f662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476902167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2476902167
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.4129857174
Short name T4
Test name
Test status
Simulation time 80063299 ps
CPU time 0.82 seconds
Started Jun 22 04:58:22 PM PDT 24
Finished Jun 22 04:58:25 PM PDT 24
Peak memory 200492 kb
Host smart-b1442472-6e2e-4bf1-b479-ff5b1483de8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129857174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.4129857174
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.3494872334
Short name T52
Test name
Test status
Simulation time 1908091170 ps
CPU time 7.29 seconds
Started Jun 22 04:58:21 PM PDT 24
Finished Jun 22 04:58:29 PM PDT 24
Peak memory 218436 kb
Host smart-ba2aefb4-fd7c-481e-812f-3dc698f5817c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494872334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3494872334
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2040224412
Short name T187
Test name
Test status
Simulation time 246111808 ps
CPU time 1.05 seconds
Started Jun 22 04:58:21 PM PDT 24
Finished Jun 22 04:58:22 PM PDT 24
Peak memory 217984 kb
Host smart-3b9fd632-c338-4317-8708-558fd616ddf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040224412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2040224412
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3308427020
Short name T196
Test name
Test status
Simulation time 117903862 ps
CPU time 0.79 seconds
Started Jun 22 04:58:14 PM PDT 24
Finished Jun 22 04:58:17 PM PDT 24
Peak memory 200448 kb
Host smart-7cf8c9f8-e5fd-4c0d-8ce2-0ff8e6653802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308427020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3308427020
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1350975862
Short name T100
Test name
Test status
Simulation time 1520370248 ps
CPU time 5.46 seconds
Started Jun 22 04:58:13 PM PDT 24
Finished Jun 22 04:58:20 PM PDT 24
Peak memory 200888 kb
Host smart-01061bb8-0525-40d7-becc-6dc080ea9b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350975862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1350975862
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.2572761788
Short name T62
Test name
Test status
Simulation time 8691971862 ps
CPU time 12.79 seconds
Started Jun 22 04:58:20 PM PDT 24
Finished Jun 22 04:58:33 PM PDT 24
Peak memory 218236 kb
Host smart-f3581a94-1507-4d49-adb2-5066ebdf4e79
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572761788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2572761788
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2114424652
Short name T477
Test name
Test status
Simulation time 158703329 ps
CPU time 1.19 seconds
Started Jun 22 04:58:21 PM PDT 24
Finished Jun 22 04:58:24 PM PDT 24
Peak memory 200688 kb
Host smart-005fb61f-bb0e-4520-862d-d9265fb4dff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114424652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2114424652
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3622164126
Short name T11
Test name
Test status
Simulation time 107327013 ps
CPU time 1.17 seconds
Started Jun 22 04:58:15 PM PDT 24
Finished Jun 22 04:58:17 PM PDT 24
Peak memory 200924 kb
Host smart-c2b68e93-94b7-4e6a-a637-8885d043ed3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622164126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3622164126
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.853537933
Short name T97
Test name
Test status
Simulation time 7302722572 ps
CPU time 24.54 seconds
Started Jun 22 04:58:21 PM PDT 24
Finished Jun 22 04:58:46 PM PDT 24
Peak memory 209152 kb
Host smart-e64f5269-da1d-4b21-8b4b-38fe0ca4a3f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853537933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.853537933
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.4118265282
Short name T287
Test name
Test status
Simulation time 135025123 ps
CPU time 1.78 seconds
Started Jun 22 04:58:23 PM PDT 24
Finished Jun 22 04:58:26 PM PDT 24
Peak memory 200680 kb
Host smart-e3bc124c-867c-45f2-9309-98b7a23fb663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118265282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.4118265282
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2814630103
Short name T396
Test name
Test status
Simulation time 135076636 ps
CPU time 1.2 seconds
Started Jun 22 04:58:22 PM PDT 24
Finished Jun 22 04:58:24 PM PDT 24
Peak memory 200928 kb
Host smart-99c0f945-d3e5-4c4c-b09e-28746425f3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814630103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2814630103
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2224562604
Short name T395
Test name
Test status
Simulation time 89040299 ps
CPU time 0.85 seconds
Started Jun 22 04:59:18 PM PDT 24
Finished Jun 22 04:59:20 PM PDT 24
Peak memory 200516 kb
Host smart-5abffa12-43df-43b1-a93f-799c2b2c5c73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224562604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2224562604
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.373866387
Short name T26
Test name
Test status
Simulation time 1898746201 ps
CPU time 7.62 seconds
Started Jun 22 04:59:09 PM PDT 24
Finished Jun 22 04:59:19 PM PDT 24
Peak memory 222400 kb
Host smart-921d688d-2c6c-4754-8a7b-4853fe8a0e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373866387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.373866387
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2547305662
Short name T197
Test name
Test status
Simulation time 244482127 ps
CPU time 1.07 seconds
Started Jun 22 04:59:16 PM PDT 24
Finished Jun 22 04:59:18 PM PDT 24
Peak memory 218100 kb
Host smart-42fe8ca3-d45c-4e82-bff0-1534f5bc498c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547305662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2547305662
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.1812062442
Short name T286
Test name
Test status
Simulation time 213023977 ps
CPU time 0.96 seconds
Started Jun 22 04:59:17 PM PDT 24
Finished Jun 22 04:59:19 PM PDT 24
Peak memory 200488 kb
Host smart-eb71fd62-d286-4c05-9c39-bd2db2de86da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812062442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1812062442
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.1901172603
Short name T120
Test name
Test status
Simulation time 2163512287 ps
CPU time 8.19 seconds
Started Jun 22 04:59:08 PM PDT 24
Finished Jun 22 04:59:18 PM PDT 24
Peak memory 200948 kb
Host smart-7f58efb8-740d-4ae3-89b7-9e3bae314af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901172603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.1901172603
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3579809008
Short name T159
Test name
Test status
Simulation time 158125022 ps
CPU time 1.16 seconds
Started Jun 22 04:59:06 PM PDT 24
Finished Jun 22 04:59:09 PM PDT 24
Peak memory 200728 kb
Host smart-997f948c-bf7c-4f09-a3a7-68bfa84799df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579809008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3579809008
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3025604476
Short name T312
Test name
Test status
Simulation time 198773370 ps
CPU time 1.37 seconds
Started Jun 22 04:59:17 PM PDT 24
Finished Jun 22 04:59:19 PM PDT 24
Peak memory 200792 kb
Host smart-0fcbb60b-51c1-453c-8533-4f355892230f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025604476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3025604476
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.1267886365
Short name T360
Test name
Test status
Simulation time 7383223227 ps
CPU time 26.91 seconds
Started Jun 22 04:59:13 PM PDT 24
Finished Jun 22 04:59:41 PM PDT 24
Peak memory 200920 kb
Host smart-a8e2c7bf-678f-4d06-bb84-dbb7f246550e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267886365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1267886365
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.938834084
Short name T350
Test name
Test status
Simulation time 113161405 ps
CPU time 1.48 seconds
Started Jun 22 04:59:13 PM PDT 24
Finished Jun 22 04:59:15 PM PDT 24
Peak memory 200700 kb
Host smart-41165b14-0f30-4d8d-a88d-e25e849acee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938834084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.938834084
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3719922252
Short name T368
Test name
Test status
Simulation time 99445459 ps
CPU time 0.89 seconds
Started Jun 22 04:59:13 PM PDT 24
Finished Jun 22 04:59:15 PM PDT 24
Peak memory 200728 kb
Host smart-e155c6e9-2d11-4658-8027-1d0ba4b3909c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719922252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3719922252
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1215930614
Short name T70
Test name
Test status
Simulation time 66455023 ps
CPU time 0.74 seconds
Started Jun 22 04:59:13 PM PDT 24
Finished Jun 22 04:59:15 PM PDT 24
Peak memory 200516 kb
Host smart-dcab23dc-92ff-49cc-a81f-06be78f6ed07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215930614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1215930614
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2910451716
Short name T524
Test name
Test status
Simulation time 2179128158 ps
CPU time 7.85 seconds
Started Jun 22 04:59:12 PM PDT 24
Finished Jun 22 04:59:21 PM PDT 24
Peak memory 218556 kb
Host smart-b4f4a7ac-1762-4718-bda4-a7a22be0f15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910451716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2910451716
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3613791573
Short name T475
Test name
Test status
Simulation time 243945549 ps
CPU time 1.04 seconds
Started Jun 22 04:59:11 PM PDT 24
Finished Jun 22 04:59:14 PM PDT 24
Peak memory 218128 kb
Host smart-f01f7c47-07fa-41b3-96c5-425b20f53c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613791573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3613791573
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1374651216
Short name T318
Test name
Test status
Simulation time 123117764 ps
CPU time 0.81 seconds
Started Jun 22 04:59:12 PM PDT 24
Finished Jun 22 04:59:14 PM PDT 24
Peak memory 200508 kb
Host smart-85041e8d-fbc3-4744-a5a6-f396a3e90faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374651216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1374651216
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2281871775
Short name T465
Test name
Test status
Simulation time 1512511205 ps
CPU time 5.34 seconds
Started Jun 22 04:59:15 PM PDT 24
Finished Jun 22 04:59:22 PM PDT 24
Peak memory 200932 kb
Host smart-60cf43c2-e884-4144-9936-ead098c6781e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281871775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2281871775
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.975781028
Short name T49
Test name
Test status
Simulation time 169442655 ps
CPU time 1.2 seconds
Started Jun 22 04:59:10 PM PDT 24
Finished Jun 22 04:59:12 PM PDT 24
Peak memory 200688 kb
Host smart-47b6c37d-cf80-4c80-ba6b-1d2ad9fecbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975781028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.975781028
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2275289364
Short name T525
Test name
Test status
Simulation time 189741943 ps
CPU time 1.48 seconds
Started Jun 22 04:59:10 PM PDT 24
Finished Jun 22 04:59:13 PM PDT 24
Peak memory 200876 kb
Host smart-4570b7d7-0858-4013-9a4f-2b2f69aff78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275289364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2275289364
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.654939083
Short name T227
Test name
Test status
Simulation time 7982795194 ps
CPU time 25.86 seconds
Started Jun 22 04:59:28 PM PDT 24
Finished Jun 22 04:59:55 PM PDT 24
Peak memory 200956 kb
Host smart-6ab5a1a5-df82-4315-b51d-c8cfe319498f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654939083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.654939083
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.123610694
Short name T229
Test name
Test status
Simulation time 143233525 ps
CPU time 1.82 seconds
Started Jun 22 04:59:12 PM PDT 24
Finished Jun 22 04:59:15 PM PDT 24
Peak memory 200720 kb
Host smart-fe91ea86-8a13-4ba8-8448-cbdc32ddf6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123610694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.123610694
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1738227830
Short name T140
Test name
Test status
Simulation time 110498678 ps
CPU time 0.99 seconds
Started Jun 22 04:59:11 PM PDT 24
Finished Jun 22 04:59:13 PM PDT 24
Peak memory 200688 kb
Host smart-61c86268-6e4a-4f06-8435-b6b4681b6c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738227830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1738227830
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1155546696
Short name T511
Test name
Test status
Simulation time 70365522 ps
CPU time 0.76 seconds
Started Jun 22 04:59:20 PM PDT 24
Finished Jun 22 04:59:21 PM PDT 24
Peak memory 200496 kb
Host smart-2cff7a72-9530-456d-99f5-4343634c927e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155546696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1155546696
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.4287891522
Short name T30
Test name
Test status
Simulation time 2366876212 ps
CPU time 8.39 seconds
Started Jun 22 04:59:17 PM PDT 24
Finished Jun 22 04:59:26 PM PDT 24
Peak memory 222832 kb
Host smart-bff54259-12f7-4443-9a6f-cdd6accd34e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287891522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.4287891522
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2189070656
Short name T178
Test name
Test status
Simulation time 243875681 ps
CPU time 1.15 seconds
Started Jun 22 04:59:21 PM PDT 24
Finished Jun 22 04:59:23 PM PDT 24
Peak memory 218332 kb
Host smart-35e3182d-1035-4bcf-b1b8-0c1e36f4e08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189070656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2189070656
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2878536715
Short name T322
Test name
Test status
Simulation time 98164134 ps
CPU time 0.8 seconds
Started Jun 22 04:59:29 PM PDT 24
Finished Jun 22 04:59:30 PM PDT 24
Peak memory 200508 kb
Host smart-9fc239c2-4eb4-41d9-af8e-869dbf5c451b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878536715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2878536715
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1531437132
Short name T308
Test name
Test status
Simulation time 1669995562 ps
CPU time 6.47 seconds
Started Jun 22 04:59:17 PM PDT 24
Finished Jun 22 04:59:25 PM PDT 24
Peak memory 200948 kb
Host smart-a55e5320-1ae7-4e77-936d-dfd27866d50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531437132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1531437132
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3263275656
Short name T148
Test name
Test status
Simulation time 104539841 ps
CPU time 0.99 seconds
Started Jun 22 04:59:09 PM PDT 24
Finished Jun 22 04:59:12 PM PDT 24
Peak memory 200728 kb
Host smart-662fa65b-0a41-43d3-94a3-64deb6135ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263275656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3263275656
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2784053864
Short name T134
Test name
Test status
Simulation time 119904954 ps
CPU time 1.2 seconds
Started Jun 22 04:59:26 PM PDT 24
Finished Jun 22 04:59:27 PM PDT 24
Peak memory 200928 kb
Host smart-f85ecb8c-9d11-40e7-be74-0e2c12277b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784053864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2784053864
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2721722945
Short name T383
Test name
Test status
Simulation time 883496058 ps
CPU time 4.41 seconds
Started Jun 22 04:59:10 PM PDT 24
Finished Jun 22 04:59:16 PM PDT 24
Peak memory 209124 kb
Host smart-76afce6d-d166-45aa-9d8f-3deb0bd4ac33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721722945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2721722945
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.453606926
Short name T437
Test name
Test status
Simulation time 515193520 ps
CPU time 2.93 seconds
Started Jun 22 04:59:13 PM PDT 24
Finished Jun 22 04:59:17 PM PDT 24
Peak memory 200708 kb
Host smart-b0fd9b07-5542-4768-b1a2-b357541778cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453606926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.453606926
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1209646975
Short name T73
Test name
Test status
Simulation time 245287063 ps
CPU time 1.37 seconds
Started Jun 22 04:59:17 PM PDT 24
Finished Jun 22 04:59:19 PM PDT 24
Peak memory 200716 kb
Host smart-3c32f90b-6925-4264-95ab-e4df884ce2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209646975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1209646975
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.4215287074
Short name T445
Test name
Test status
Simulation time 65526049 ps
CPU time 0.75 seconds
Started Jun 22 04:59:12 PM PDT 24
Finished Jun 22 04:59:14 PM PDT 24
Peak memory 200512 kb
Host smart-ab42c8f1-f23c-45e6-8305-08893a78cca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215287074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.4215287074
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.161038482
Short name T315
Test name
Test status
Simulation time 2361591159 ps
CPU time 8.13 seconds
Started Jun 22 04:59:30 PM PDT 24
Finished Jun 22 04:59:39 PM PDT 24
Peak memory 218624 kb
Host smart-70f7ba0e-fd5d-43cd-9564-ed22fa78efb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161038482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.161038482
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3698360178
Short name T209
Test name
Test status
Simulation time 243647865 ps
CPU time 1.06 seconds
Started Jun 22 04:59:15 PM PDT 24
Finished Jun 22 04:59:17 PM PDT 24
Peak memory 218104 kb
Host smart-dd6d708b-4f51-405f-9e72-55600918e075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698360178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3698360178
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3376576036
Short name T388
Test name
Test status
Simulation time 189824068 ps
CPU time 0.87 seconds
Started Jun 22 04:59:24 PM PDT 24
Finished Jun 22 04:59:25 PM PDT 24
Peak memory 200472 kb
Host smart-067fcd24-fa8a-4472-866d-64e0d69f3b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376576036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3376576036
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.3389580031
Short name T235
Test name
Test status
Simulation time 889739580 ps
CPU time 4.41 seconds
Started Jun 22 04:59:17 PM PDT 24
Finished Jun 22 04:59:23 PM PDT 24
Peak memory 200840 kb
Host smart-da779933-9035-44ba-9f06-21f86a88dedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389580031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3389580031
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3711836300
Short name T121
Test name
Test status
Simulation time 183403221 ps
CPU time 1.31 seconds
Started Jun 22 04:59:33 PM PDT 24
Finished Jun 22 04:59:36 PM PDT 24
Peak memory 200720 kb
Host smart-807e83f6-2b84-470b-ab91-68e8ece63ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711836300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3711836300
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.910412590
Short name T42
Test name
Test status
Simulation time 118081377 ps
CPU time 1.13 seconds
Started Jun 22 04:59:28 PM PDT 24
Finished Jun 22 04:59:30 PM PDT 24
Peak memory 200876 kb
Host smart-f84a8722-8a94-4a0e-bb2c-f11d18328073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910412590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.910412590
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.2059549958
Short name T98
Test name
Test status
Simulation time 915336663 ps
CPU time 3.94 seconds
Started Jun 22 04:59:25 PM PDT 24
Finished Jun 22 04:59:29 PM PDT 24
Peak memory 209124 kb
Host smart-538846b8-9d20-4c20-a812-7b13270691bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059549958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2059549958
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.2611372708
Short name T526
Test name
Test status
Simulation time 303992493 ps
CPU time 2 seconds
Started Jun 22 04:59:21 PM PDT 24
Finished Jun 22 04:59:24 PM PDT 24
Peak memory 208956 kb
Host smart-a949e425-5758-46f2-830b-0c5628f70767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611372708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2611372708
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.2459875327
Short name T138
Test name
Test status
Simulation time 76451444 ps
CPU time 0.79 seconds
Started Jun 22 04:59:21 PM PDT 24
Finished Jun 22 04:59:22 PM PDT 24
Peak memory 200728 kb
Host smart-12492978-566e-405f-8f01-e6971d379224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459875327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2459875327
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.4143792174
Short name T219
Test name
Test status
Simulation time 71194260 ps
CPU time 0.77 seconds
Started Jun 22 04:59:14 PM PDT 24
Finished Jun 22 04:59:16 PM PDT 24
Peak memory 200512 kb
Host smart-ecc29d08-bbf6-4bcb-bc59-04f693009428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143792174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.4143792174
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3356785954
Short name T494
Test name
Test status
Simulation time 2353012837 ps
CPU time 7.76 seconds
Started Jun 22 04:59:26 PM PDT 24
Finished Jun 22 04:59:34 PM PDT 24
Peak memory 217888 kb
Host smart-c94ff099-a60e-4c49-a0e9-5b0deccccbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356785954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3356785954
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2518167696
Short name T234
Test name
Test status
Simulation time 247165237 ps
CPU time 1.05 seconds
Started Jun 22 04:59:42 PM PDT 24
Finished Jun 22 04:59:43 PM PDT 24
Peak memory 218180 kb
Host smart-26e8367a-f687-40ca-919b-f6cdcc6aa44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518167696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2518167696
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3160577468
Short name T332
Test name
Test status
Simulation time 119111505 ps
CPU time 0.84 seconds
Started Jun 22 04:59:27 PM PDT 24
Finished Jun 22 04:59:28 PM PDT 24
Peak memory 200504 kb
Host smart-268743b3-25bd-4a53-895f-5854d91dec8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160577468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3160577468
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3236660265
Short name T387
Test name
Test status
Simulation time 1761593992 ps
CPU time 6.45 seconds
Started Jun 22 04:59:22 PM PDT 24
Finished Jun 22 04:59:29 PM PDT 24
Peak memory 200948 kb
Host smart-429a20bb-1d52-4ebb-b0d1-a0b3f551afc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236660265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3236660265
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3546059858
Short name T132
Test name
Test status
Simulation time 171414417 ps
CPU time 1.29 seconds
Started Jun 22 04:59:28 PM PDT 24
Finished Jun 22 04:59:30 PM PDT 24
Peak memory 200720 kb
Host smart-98ebb204-704a-4fc3-8475-bc1dd15d6715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546059858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3546059858
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3641994342
Short name T500
Test name
Test status
Simulation time 202744230 ps
CPU time 1.35 seconds
Started Jun 22 04:59:32 PM PDT 24
Finished Jun 22 04:59:35 PM PDT 24
Peak memory 200852 kb
Host smart-2dc74d0f-7e1b-4b31-922a-cd00bdbef2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641994342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3641994342
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1159134638
Short name T277
Test name
Test status
Simulation time 1906294917 ps
CPU time 8.47 seconds
Started Jun 22 04:59:31 PM PDT 24
Finished Jun 22 04:59:41 PM PDT 24
Peak memory 200892 kb
Host smart-7315e620-ee81-42a1-8136-a94cd6bdcea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159134638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1159134638
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3891270625
Short name T534
Test name
Test status
Simulation time 443359000 ps
CPU time 2.41 seconds
Started Jun 22 04:59:20 PM PDT 24
Finished Jun 22 04:59:23 PM PDT 24
Peak memory 208932 kb
Host smart-25b4885a-5a1a-429e-b0de-307d861d49f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891270625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3891270625
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1353113717
Short name T420
Test name
Test status
Simulation time 72581129 ps
CPU time 0.81 seconds
Started Jun 22 04:59:15 PM PDT 24
Finished Jun 22 04:59:17 PM PDT 24
Peak memory 200660 kb
Host smart-191f04f8-6fc2-40af-a424-61e378d4ffc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353113717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1353113717
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.2101339658
Short name T372
Test name
Test status
Simulation time 66233538 ps
CPU time 0.75 seconds
Started Jun 22 04:59:32 PM PDT 24
Finished Jun 22 04:59:34 PM PDT 24
Peak memory 200516 kb
Host smart-70c43c30-36f2-473d-8f79-51c4ec21614a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101339658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2101339658
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1132028906
Short name T29
Test name
Test status
Simulation time 1225132363 ps
CPU time 6.08 seconds
Started Jun 22 04:59:23 PM PDT 24
Finished Jun 22 04:59:29 PM PDT 24
Peak memory 222448 kb
Host smart-44d1a1ac-7127-41cf-be4e-93f51211816a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132028906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1132028906
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1475399328
Short name T453
Test name
Test status
Simulation time 244363179 ps
CPU time 1.13 seconds
Started Jun 22 04:59:23 PM PDT 24
Finished Jun 22 04:59:25 PM PDT 24
Peak memory 217088 kb
Host smart-1691ccd4-6242-458e-9d9c-0665b4725c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475399328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1475399328
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3795609210
Short name T326
Test name
Test status
Simulation time 108983871 ps
CPU time 0.78 seconds
Started Jun 22 04:59:30 PM PDT 24
Finished Jun 22 04:59:31 PM PDT 24
Peak memory 200508 kb
Host smart-622df7e0-cf13-4627-9dcb-b59cb8462ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795609210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3795609210
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.3544827338
Short name T91
Test name
Test status
Simulation time 1524294991 ps
CPU time 5.98 seconds
Started Jun 22 04:59:39 PM PDT 24
Finished Jun 22 04:59:46 PM PDT 24
Peak memory 200888 kb
Host smart-de43b73b-6fff-434e-b108-0bcfa74a180e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544827338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3544827338
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.341619634
Short name T156
Test name
Test status
Simulation time 148155327 ps
CPU time 1.06 seconds
Started Jun 22 04:59:42 PM PDT 24
Finished Jun 22 04:59:44 PM PDT 24
Peak memory 200728 kb
Host smart-b375deaa-a6ea-45b4-953a-3a7934e3ef55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341619634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.341619634
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.909734410
Short name T163
Test name
Test status
Simulation time 188652194 ps
CPU time 1.35 seconds
Started Jun 22 04:59:18 PM PDT 24
Finished Jun 22 04:59:21 PM PDT 24
Peak memory 200888 kb
Host smart-7d3a70c5-25aa-4add-aa71-d74419bed8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909734410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.909734410
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1823648879
Short name T439
Test name
Test status
Simulation time 3191439584 ps
CPU time 13.93 seconds
Started Jun 22 04:59:24 PM PDT 24
Finished Jun 22 04:59:38 PM PDT 24
Peak memory 200920 kb
Host smart-b2d60bfb-1346-490d-be86-1fc81b274b97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823648879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1823648879
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.4270263894
Short name T79
Test name
Test status
Simulation time 490443037 ps
CPU time 2.78 seconds
Started Jun 22 04:59:31 PM PDT 24
Finished Jun 22 04:59:35 PM PDT 24
Peak memory 200756 kb
Host smart-d15d3159-e1d1-4b0d-afbf-1f8a992f7527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270263894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.4270263894
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.356756147
Short name T426
Test name
Test status
Simulation time 179987179 ps
CPU time 1.1 seconds
Started Jun 22 04:59:21 PM PDT 24
Finished Jun 22 04:59:22 PM PDT 24
Peak memory 200688 kb
Host smart-67d2a3cc-55d7-4a73-9133-fdec6c7b63d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356756147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.356756147
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.449778367
Short name T174
Test name
Test status
Simulation time 64991532 ps
CPU time 0.83 seconds
Started Jun 22 04:59:22 PM PDT 24
Finished Jun 22 04:59:24 PM PDT 24
Peak memory 200756 kb
Host smart-f6afd8d7-1f6b-4a03-a443-36391cc8823e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449778367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.449778367
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.2842694166
Short name T51
Test name
Test status
Simulation time 1901759933 ps
CPU time 7.6 seconds
Started Jun 22 04:59:21 PM PDT 24
Finished Jun 22 04:59:29 PM PDT 24
Peak memory 217980 kb
Host smart-6bf29cec-4371-4511-96b5-482d03542983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842694166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2842694166
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1609163549
Short name T428
Test name
Test status
Simulation time 244571354 ps
CPU time 1.07 seconds
Started Jun 22 04:59:17 PM PDT 24
Finished Jun 22 04:59:19 PM PDT 24
Peak memory 218084 kb
Host smart-8a109e06-ad5c-475e-ae5e-75f405b00cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609163549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1609163549
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3586054108
Short name T417
Test name
Test status
Simulation time 156398774 ps
CPU time 0.88 seconds
Started Jun 22 04:59:16 PM PDT 24
Finished Jun 22 04:59:18 PM PDT 24
Peak memory 200484 kb
Host smart-2ff94b4c-ffc5-46be-a288-9dfb5f3d6564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586054108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3586054108
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3906018684
Short name T335
Test name
Test status
Simulation time 2090751667 ps
CPU time 8.24 seconds
Started Jun 22 04:59:27 PM PDT 24
Finished Jun 22 04:59:36 PM PDT 24
Peak memory 200892 kb
Host smart-b9648888-75cd-49ef-889c-4914bd556de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906018684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3906018684
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.309907905
Short name T248
Test name
Test status
Simulation time 109613368 ps
CPU time 1.06 seconds
Started Jun 22 04:59:17 PM PDT 24
Finished Jun 22 04:59:19 PM PDT 24
Peak memory 200724 kb
Host smart-e3a21333-4c75-4373-bd09-b5c14b189ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309907905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.309907905
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.116178480
Short name T230
Test name
Test status
Simulation time 225989818 ps
CPU time 1.39 seconds
Started Jun 22 04:59:15 PM PDT 24
Finished Jun 22 04:59:18 PM PDT 24
Peak memory 200860 kb
Host smart-b5fe6afc-0221-49ae-bcc1-5f5d9a3ef26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116178480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.116178480
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.141006434
Short name T522
Test name
Test status
Simulation time 3563148789 ps
CPU time 16.51 seconds
Started Jun 22 04:59:23 PM PDT 24
Finished Jun 22 04:59:41 PM PDT 24
Peak memory 209672 kb
Host smart-6154a044-e4b3-4b0a-b553-36fc266be57b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141006434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.141006434
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.1439425935
Short name T43
Test name
Test status
Simulation time 524324082 ps
CPU time 2.93 seconds
Started Jun 22 04:59:14 PM PDT 24
Finished Jun 22 04:59:18 PM PDT 24
Peak memory 200720 kb
Host smart-0278beac-0c92-429f-91d9-3b244eaba7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439425935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1439425935
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.3615401421
Short name T367
Test name
Test status
Simulation time 136524093 ps
CPU time 1.02 seconds
Started Jun 22 04:59:26 PM PDT 24
Finished Jun 22 04:59:27 PM PDT 24
Peak memory 200756 kb
Host smart-1a5fb892-eaab-48f3-b6a1-9a213c5da633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615401421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.3615401421
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.895820156
Short name T418
Test name
Test status
Simulation time 63147916 ps
CPU time 0.76 seconds
Started Jun 22 04:59:47 PM PDT 24
Finished Jun 22 04:59:48 PM PDT 24
Peak memory 200508 kb
Host smart-f81df53d-1233-41d1-906f-c2dff0c23186
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895820156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.895820156
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3097640797
Short name T416
Test name
Test status
Simulation time 1221288325 ps
CPU time 5.28 seconds
Started Jun 22 04:59:23 PM PDT 24
Finished Jun 22 04:59:29 PM PDT 24
Peak memory 222444 kb
Host smart-b8bc4f97-79ad-4d32-b443-fc3c99c0c7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097640797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3097640797
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1786236063
Short name T162
Test name
Test status
Simulation time 243906939 ps
CPU time 1 seconds
Started Jun 22 04:59:35 PM PDT 24
Finished Jun 22 04:59:38 PM PDT 24
Peak memory 218108 kb
Host smart-e06d9e97-a771-4170-b7a0-69e12c867406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786236063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1786236063
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.4112425707
Short name T198
Test name
Test status
Simulation time 84654752 ps
CPU time 0.77 seconds
Started Jun 22 04:59:40 PM PDT 24
Finished Jun 22 04:59:42 PM PDT 24
Peak memory 200504 kb
Host smart-f7ca5650-9a49-422b-8b8a-76445b1c3ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112425707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.4112425707
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2367881676
Short name T67
Test name
Test status
Simulation time 935706338 ps
CPU time 5.08 seconds
Started Jun 22 04:59:38 PM PDT 24
Finished Jun 22 04:59:44 PM PDT 24
Peak memory 200896 kb
Host smart-ad9ef510-594e-4372-89f5-cdfe34625f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367881676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2367881676
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3623415550
Short name T421
Test name
Test status
Simulation time 96779810 ps
CPU time 1.05 seconds
Started Jun 22 04:59:37 PM PDT 24
Finished Jun 22 04:59:40 PM PDT 24
Peak memory 200700 kb
Host smart-8bb98f18-7224-483f-ab3e-2a0b2488ec5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623415550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3623415550
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2897147225
Short name T296
Test name
Test status
Simulation time 187953172 ps
CPU time 1.37 seconds
Started Jun 22 04:59:39 PM PDT 24
Finished Jun 22 04:59:41 PM PDT 24
Peak memory 200892 kb
Host smart-884bda5c-c8ff-4a6a-8ffd-4510d12a9259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897147225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2897147225
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.739400850
Short name T45
Test name
Test status
Simulation time 7354888688 ps
CPU time 29.32 seconds
Started Jun 22 04:59:33 PM PDT 24
Finished Jun 22 05:00:03 PM PDT 24
Peak memory 209152 kb
Host smart-a9ecfafd-c5c2-4e67-a766-6dc934a7d81b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739400850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.739400850
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.286485760
Short name T461
Test name
Test status
Simulation time 129899812 ps
CPU time 1.53 seconds
Started Jun 22 04:59:45 PM PDT 24
Finished Jun 22 04:59:47 PM PDT 24
Peak memory 208888 kb
Host smart-24f2ab31-7db6-4d6f-b221-340684a48fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286485760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.286485760
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3496699638
Short name T450
Test name
Test status
Simulation time 114867772 ps
CPU time 1.02 seconds
Started Jun 22 04:59:31 PM PDT 24
Finished Jun 22 04:59:34 PM PDT 24
Peak memory 200756 kb
Host smart-bb85df3f-70d9-4d8e-8d99-5766cdc4fb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496699638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3496699638
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.2584627535
Short name T131
Test name
Test status
Simulation time 66828546 ps
CPU time 0.81 seconds
Started Jun 22 04:59:35 PM PDT 24
Finished Jun 22 04:59:37 PM PDT 24
Peak memory 200512 kb
Host smart-27d33551-5468-40aa-88aa-4762f238d19d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584627535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2584627535
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1821396192
Short name T256
Test name
Test status
Simulation time 1221209569 ps
CPU time 6.14 seconds
Started Jun 22 04:59:31 PM PDT 24
Finished Jun 22 04:59:38 PM PDT 24
Peak memory 218532 kb
Host smart-610efa91-af70-4ec2-96b2-4e6fba223004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821396192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1821396192
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3234621502
Short name T48
Test name
Test status
Simulation time 244066312 ps
CPU time 1.06 seconds
Started Jun 22 04:59:35 PM PDT 24
Finished Jun 22 04:59:38 PM PDT 24
Peak memory 218068 kb
Host smart-d45d91ff-0c41-4887-aad1-eacba5c86968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234621502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3234621502
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3068461418
Short name T247
Test name
Test status
Simulation time 191569464 ps
CPU time 0.86 seconds
Started Jun 22 04:59:41 PM PDT 24
Finished Jun 22 04:59:42 PM PDT 24
Peak memory 200512 kb
Host smart-0004c726-d063-4800-8265-b35d09b4576a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068461418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3068461418
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3150343810
Short name T46
Test name
Test status
Simulation time 1771211222 ps
CPU time 6.6 seconds
Started Jun 22 04:59:32 PM PDT 24
Finished Jun 22 04:59:40 PM PDT 24
Peak memory 200876 kb
Host smart-b555ca8d-55db-488a-8aec-a7b861c85c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150343810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3150343810
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1265039977
Short name T130
Test name
Test status
Simulation time 159405953 ps
CPU time 1.23 seconds
Started Jun 22 04:59:35 PM PDT 24
Finished Jun 22 04:59:37 PM PDT 24
Peak memory 200928 kb
Host smart-57c48a05-f5fd-4e76-b12c-83ceccc1a361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265039977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1265039977
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2514419061
Short name T191
Test name
Test status
Simulation time 114206518 ps
CPU time 1.22 seconds
Started Jun 22 04:59:28 PM PDT 24
Finished Jun 22 04:59:30 PM PDT 24
Peak memory 200948 kb
Host smart-f322a86c-8d7e-42ff-8cec-a6c58c3262fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514419061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2514419061
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.193104884
Short name T99
Test name
Test status
Simulation time 3813520736 ps
CPU time 13.38 seconds
Started Jun 22 04:59:34 PM PDT 24
Finished Jun 22 04:59:49 PM PDT 24
Peak memory 200936 kb
Host smart-c0200c4e-c856-4970-bd4b-a3737811f94c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193104884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.193104884
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2046058377
Short name T331
Test name
Test status
Simulation time 110738344 ps
CPU time 1.4 seconds
Started Jun 22 04:59:35 PM PDT 24
Finished Jun 22 04:59:38 PM PDT 24
Peak memory 200716 kb
Host smart-aba305c9-6d9b-4465-8c03-9f4feda3ab77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046058377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2046058377
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2906510914
Short name T2
Test name
Test status
Simulation time 145785905 ps
CPU time 1.12 seconds
Started Jun 22 04:59:25 PM PDT 24
Finished Jun 22 04:59:26 PM PDT 24
Peak memory 200712 kb
Host smart-5a5cd1d1-29ac-4d68-8620-3ff6fe98b3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906510914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2906510914
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.161757301
Short name T298
Test name
Test status
Simulation time 75026467 ps
CPU time 0.76 seconds
Started Jun 22 04:59:34 PM PDT 24
Finished Jun 22 04:59:35 PM PDT 24
Peak memory 200516 kb
Host smart-e37659d3-f7d8-46c6-9c7d-d681bf95db14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161757301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.161757301
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2420976123
Short name T497
Test name
Test status
Simulation time 1900164604 ps
CPU time 7.14 seconds
Started Jun 22 04:59:50 PM PDT 24
Finished Jun 22 04:59:58 PM PDT 24
Peak memory 222052 kb
Host smart-93b7c56e-2970-4d5b-bafa-0d03352c65cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420976123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2420976123
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2964577006
Short name T467
Test name
Test status
Simulation time 243115954 ps
CPU time 1.05 seconds
Started Jun 22 04:59:37 PM PDT 24
Finished Jun 22 04:59:39 PM PDT 24
Peak memory 218092 kb
Host smart-652281b5-9f35-4f81-9aba-7cfd96e30282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964577006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2964577006
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2810129425
Short name T290
Test name
Test status
Simulation time 174583161 ps
CPU time 0.92 seconds
Started Jun 22 04:59:44 PM PDT 24
Finished Jun 22 04:59:46 PM PDT 24
Peak memory 200468 kb
Host smart-ed0dd1ce-a96a-4f99-b666-0ea1c13e20a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810129425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2810129425
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2927134884
Short name T47
Test name
Test status
Simulation time 1291078199 ps
CPU time 5.5 seconds
Started Jun 22 04:59:39 PM PDT 24
Finished Jun 22 04:59:45 PM PDT 24
Peak memory 200952 kb
Host smart-1965fad8-d4a5-4243-8852-4b67cb1d3556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927134884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2927134884
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1978042923
Short name T292
Test name
Test status
Simulation time 110610789 ps
CPU time 1 seconds
Started Jun 22 04:59:37 PM PDT 24
Finished Jun 22 04:59:40 PM PDT 24
Peak memory 200712 kb
Host smart-073a1f3b-b92b-45c4-b0bf-c5895d6828de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978042923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1978042923
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.66446641
Short name T160
Test name
Test status
Simulation time 119946263 ps
CPU time 1.14 seconds
Started Jun 22 04:59:43 PM PDT 24
Finished Jun 22 04:59:45 PM PDT 24
Peak memory 200772 kb
Host smart-2894199f-92a3-4915-9a7c-9564936156fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66446641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.66446641
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3558377137
Short name T6
Test name
Test status
Simulation time 7665265980 ps
CPU time 28.42 seconds
Started Jun 22 04:59:40 PM PDT 24
Finished Jun 22 05:00:09 PM PDT 24
Peak memory 200960 kb
Host smart-c617991e-effe-46a2-acf0-cfb65c31eb35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558377137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3558377137
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3432172268
Short name T323
Test name
Test status
Simulation time 543582149 ps
CPU time 2.67 seconds
Started Jun 22 04:59:34 PM PDT 24
Finished Jun 22 04:59:37 PM PDT 24
Peak memory 200656 kb
Host smart-5130b1b4-7fda-42a2-abd3-aa05aea327d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432172268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3432172268
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1149239569
Short name T75
Test name
Test status
Simulation time 183194932 ps
CPU time 1.25 seconds
Started Jun 22 04:59:21 PM PDT 24
Finished Jun 22 04:59:23 PM PDT 24
Peak memory 200676 kb
Host smart-bf5323fd-e56d-486c-b39e-6d67e20a48cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149239569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1149239569
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2234023211
Short name T358
Test name
Test status
Simulation time 73313081 ps
CPU time 0.86 seconds
Started Jun 22 04:58:22 PM PDT 24
Finished Jun 22 04:58:25 PM PDT 24
Peak memory 200508 kb
Host smart-a32996bd-2eef-4b76-93c0-8cf576883d4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234023211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2234023211
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3011442885
Short name T38
Test name
Test status
Simulation time 1897343421 ps
CPU time 6.91 seconds
Started Jun 22 04:58:20 PM PDT 24
Finished Jun 22 04:58:27 PM PDT 24
Peak memory 218004 kb
Host smart-c51092e8-f1d4-4f03-8cc8-e88789d610d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011442885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3011442885
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.426346786
Short name T185
Test name
Test status
Simulation time 244070689 ps
CPU time 1.1 seconds
Started Jun 22 04:58:25 PM PDT 24
Finished Jun 22 04:58:27 PM PDT 24
Peak memory 218096 kb
Host smart-380e1b9e-b540-4723-a0f7-3bd6461a28d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426346786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.426346786
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.804518116
Short name T240
Test name
Test status
Simulation time 141990186 ps
CPU time 0.83 seconds
Started Jun 22 04:58:21 PM PDT 24
Finished Jun 22 04:58:22 PM PDT 24
Peak memory 200472 kb
Host smart-33879845-cf81-462c-882a-45427d44c083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804518116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.804518116
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2263113801
Short name T399
Test name
Test status
Simulation time 1636042359 ps
CPU time 6.44 seconds
Started Jun 22 04:58:24 PM PDT 24
Finished Jun 22 04:58:31 PM PDT 24
Peak memory 200876 kb
Host smart-9b29551f-ec38-4eca-9270-dd0b1bd878f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263113801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2263113801
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1246334325
Short name T339
Test name
Test status
Simulation time 105070881 ps
CPU time 1.04 seconds
Started Jun 22 04:58:21 PM PDT 24
Finished Jun 22 04:58:22 PM PDT 24
Peak memory 200720 kb
Host smart-ab47e80f-59a1-4b74-833d-8b0a4a83870b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246334325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1246334325
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2486995213
Short name T430
Test name
Test status
Simulation time 121828565 ps
CPU time 1.2 seconds
Started Jun 22 04:58:22 PM PDT 24
Finished Jun 22 04:58:25 PM PDT 24
Peak memory 200884 kb
Host smart-087610d2-b14e-4f08-9c80-616aebedd609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486995213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2486995213
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1502490671
Short name T448
Test name
Test status
Simulation time 7495927415 ps
CPU time 26.74 seconds
Started Jun 22 04:58:22 PM PDT 24
Finished Jun 22 04:58:51 PM PDT 24
Peak memory 209076 kb
Host smart-5bd5baf7-92f7-4203-8b62-9d78ef8bdb6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502490671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1502490671
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.2256621064
Short name T226
Test name
Test status
Simulation time 123117497 ps
CPU time 1.51 seconds
Started Jun 22 04:58:21 PM PDT 24
Finished Jun 22 04:58:24 PM PDT 24
Peak memory 208856 kb
Host smart-db8d27f6-f504-4841-98ac-c6d6e38bb95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256621064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.2256621064
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1629678594
Short name T515
Test name
Test status
Simulation time 110451813 ps
CPU time 0.99 seconds
Started Jun 22 04:58:20 PM PDT 24
Finished Jun 22 04:58:22 PM PDT 24
Peak memory 200684 kb
Host smart-2e327607-e696-48ac-9fc2-2fe129190a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629678594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1629678594
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2808481277
Short name T392
Test name
Test status
Simulation time 76619092 ps
CPU time 0.81 seconds
Started Jun 22 04:58:21 PM PDT 24
Finished Jun 22 04:58:23 PM PDT 24
Peak memory 200484 kb
Host smart-294db2f6-591f-479e-8fa4-0b6f268dffc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808481277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2808481277
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1869701037
Short name T13
Test name
Test status
Simulation time 1880596895 ps
CPU time 7.74 seconds
Started Jun 22 04:58:24 PM PDT 24
Finished Jun 22 04:58:33 PM PDT 24
Peak memory 218524 kb
Host smart-8c21c689-198a-482e-bd47-1f1bc2d11918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869701037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1869701037
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2476797889
Short name T171
Test name
Test status
Simulation time 244125369 ps
CPU time 1.15 seconds
Started Jun 22 04:58:22 PM PDT 24
Finished Jun 22 04:58:24 PM PDT 24
Peak memory 217988 kb
Host smart-51260857-deb0-4239-a657-2c70a2839747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476797889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2476797889
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1467005580
Short name T16
Test name
Test status
Simulation time 180988096 ps
CPU time 0.9 seconds
Started Jun 22 04:58:21 PM PDT 24
Finished Jun 22 04:58:24 PM PDT 24
Peak memory 200504 kb
Host smart-1e2dcb96-5975-4262-9b91-0e5c6d2cbef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467005580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1467005580
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.4010704680
Short name T536
Test name
Test status
Simulation time 1834870749 ps
CPU time 7.22 seconds
Started Jun 22 04:58:22 PM PDT 24
Finished Jun 22 04:58:31 PM PDT 24
Peak memory 200788 kb
Host smart-00210841-102e-4b49-8602-ad4a0cfd46a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010704680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.4010704680
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1636416417
Short name T415
Test name
Test status
Simulation time 110565001 ps
CPU time 1.07 seconds
Started Jun 22 04:58:21 PM PDT 24
Finished Jun 22 04:58:24 PM PDT 24
Peak memory 200648 kb
Host smart-66f38782-99e8-46ff-ade8-1743d2896c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636416417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1636416417
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.631264794
Short name T245
Test name
Test status
Simulation time 208789618 ps
CPU time 1.33 seconds
Started Jun 22 04:58:20 PM PDT 24
Finished Jun 22 04:58:22 PM PDT 24
Peak memory 200876 kb
Host smart-db907501-8154-4889-a00e-c43bac10ba00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631264794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.631264794
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3094387873
Short name T164
Test name
Test status
Simulation time 3489139667 ps
CPU time 12.98 seconds
Started Jun 22 04:58:20 PM PDT 24
Finished Jun 22 04:58:34 PM PDT 24
Peak memory 200860 kb
Host smart-204ffc30-455e-4581-9444-fa5c8763b756
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094387873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3094387873
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1829081517
Short name T184
Test name
Test status
Simulation time 291457506 ps
CPU time 1.48 seconds
Started Jun 22 04:58:22 PM PDT 24
Finished Jun 22 04:58:25 PM PDT 24
Peak memory 200892 kb
Host smart-aeb5ccc0-ce4a-492d-84eb-ccfb871dfe49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829081517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1829081517
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.940061113
Short name T405
Test name
Test status
Simulation time 54196062 ps
CPU time 0.72 seconds
Started Jun 22 04:58:22 PM PDT 24
Finished Jun 22 04:58:24 PM PDT 24
Peak memory 200760 kb
Host smart-0b5ff637-6df9-411b-817e-3b776cb37616
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940061113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.940061113
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1670834040
Short name T309
Test name
Test status
Simulation time 1220491566 ps
CPU time 5.7 seconds
Started Jun 22 04:58:22 PM PDT 24
Finished Jun 22 04:58:30 PM PDT 24
Peak memory 218532 kb
Host smart-e4d1e741-5070-403c-842a-d85dc13336a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670834040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1670834040
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.477418951
Short name T133
Test name
Test status
Simulation time 244154369 ps
CPU time 1.1 seconds
Started Jun 22 04:58:24 PM PDT 24
Finished Jun 22 04:58:26 PM PDT 24
Peak memory 218080 kb
Host smart-5a4b7da3-bfb6-4e80-94d7-fb4a448a257b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477418951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.477418951
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.3419447951
Short name T519
Test name
Test status
Simulation time 139483482 ps
CPU time 0.83 seconds
Started Jun 22 04:58:21 PM PDT 24
Finished Jun 22 04:58:22 PM PDT 24
Peak memory 200508 kb
Host smart-822b6a70-3b5d-4900-90a8-5e491b9ed23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419447951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3419447951
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.2301582326
Short name T175
Test name
Test status
Simulation time 1613052765 ps
CPU time 6.25 seconds
Started Jun 22 04:58:20 PM PDT 24
Finished Jun 22 04:58:27 PM PDT 24
Peak memory 200896 kb
Host smart-0b6b55f0-5235-4ece-9481-99dd518554f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301582326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2301582326
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2673762511
Short name T375
Test name
Test status
Simulation time 98618364 ps
CPU time 1.02 seconds
Started Jun 22 04:58:20 PM PDT 24
Finished Jun 22 04:58:21 PM PDT 24
Peak memory 200644 kb
Host smart-b90f7024-23ab-4cba-9070-bbf9074f7cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673762511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2673762511
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3810721723
Short name T346
Test name
Test status
Simulation time 203906008 ps
CPU time 1.41 seconds
Started Jun 22 04:58:20 PM PDT 24
Finished Jun 22 04:58:22 PM PDT 24
Peak memory 200828 kb
Host smart-7bca61dd-2ec3-4d04-9e56-f743176e208f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810721723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3810721723
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2381186896
Short name T499
Test name
Test status
Simulation time 7945301751 ps
CPU time 26.33 seconds
Started Jun 22 04:58:22 PM PDT 24
Finished Jun 22 04:58:49 PM PDT 24
Peak memory 200948 kb
Host smart-a518b9c7-6de5-4ca9-9413-d1bbff3b4d22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381186896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2381186896
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.2993001401
Short name T261
Test name
Test status
Simulation time 141403426 ps
CPU time 1.88 seconds
Started Jun 22 04:58:22 PM PDT 24
Finished Jun 22 04:58:26 PM PDT 24
Peak memory 200620 kb
Host smart-00fbce56-37aa-4324-98b4-ddfce3c7e002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993001401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2993001401
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3572109972
Short name T487
Test name
Test status
Simulation time 176608487 ps
CPU time 1.15 seconds
Started Jun 22 04:58:25 PM PDT 24
Finished Jun 22 04:58:27 PM PDT 24
Peak memory 200728 kb
Host smart-056fff6a-0888-428c-a46f-730fa5ef5957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572109972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3572109972
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.458500081
Short name T521
Test name
Test status
Simulation time 52783062 ps
CPU time 0.69 seconds
Started Jun 22 04:58:40 PM PDT 24
Finished Jun 22 04:58:41 PM PDT 24
Peak memory 200520 kb
Host smart-55f940f9-ef1b-4ee4-a221-e891673a594b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458500081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.458500081
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2087422877
Short name T362
Test name
Test status
Simulation time 2156710562 ps
CPU time 8.92 seconds
Started Jun 22 04:58:24 PM PDT 24
Finished Jun 22 04:58:34 PM PDT 24
Peak memory 218556 kb
Host smart-81b4b7a0-7be4-40c4-9f3f-3466be93cf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087422877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2087422877
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.125440368
Short name T484
Test name
Test status
Simulation time 244279931 ps
CPU time 1.08 seconds
Started Jun 22 04:58:27 PM PDT 24
Finished Jun 22 04:58:28 PM PDT 24
Peak memory 218312 kb
Host smart-0284e5cf-f238-4617-aa9f-50b2d713a94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125440368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.125440368
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2733294806
Short name T414
Test name
Test status
Simulation time 167039617 ps
CPU time 0.84 seconds
Started Jun 22 04:58:21 PM PDT 24
Finished Jun 22 04:58:22 PM PDT 24
Peak memory 200504 kb
Host smart-c0635db0-a673-4f83-a835-5ce4d6476da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733294806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2733294806
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.902906040
Short name T490
Test name
Test status
Simulation time 1678535706 ps
CPU time 6.84 seconds
Started Jun 22 04:58:22 PM PDT 24
Finished Jun 22 04:58:31 PM PDT 24
Peak memory 200732 kb
Host smart-686a97f7-9998-4db1-afb2-25a4eb6855ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902906040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.902906040
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1383127614
Short name T489
Test name
Test status
Simulation time 93482051 ps
CPU time 1.01 seconds
Started Jun 22 04:58:22 PM PDT 24
Finished Jun 22 04:58:25 PM PDT 24
Peak memory 200680 kb
Host smart-e77d2608-5117-4543-85b2-cef102c30725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383127614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1383127614
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2748411601
Short name T215
Test name
Test status
Simulation time 253910987 ps
CPU time 1.59 seconds
Started Jun 22 04:58:22 PM PDT 24
Finished Jun 22 04:58:26 PM PDT 24
Peak memory 200896 kb
Host smart-892c6e34-4608-443e-aee5-33b266de19b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748411601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2748411601
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.4223465652
Short name T228
Test name
Test status
Simulation time 10820317325 ps
CPU time 38.84 seconds
Started Jun 22 04:58:29 PM PDT 24
Finished Jun 22 04:59:08 PM PDT 24
Peak memory 211124 kb
Host smart-ad028be6-bdfa-474e-9ec8-ea0720e275fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223465652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.4223465652
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.638621852
Short name T365
Test name
Test status
Simulation time 139022192 ps
CPU time 1.69 seconds
Started Jun 22 04:58:21 PM PDT 24
Finished Jun 22 04:58:23 PM PDT 24
Peak memory 200676 kb
Host smart-06f24fee-1e4a-4c3e-9cc5-a3c8f10bb0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638621852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.638621852
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2721831631
Short name T150
Test name
Test status
Simulation time 214989574 ps
CPU time 1.35 seconds
Started Jun 22 04:58:23 PM PDT 24
Finished Jun 22 04:58:26 PM PDT 24
Peak memory 200688 kb
Host smart-600ea866-d912-4bf6-a1fc-7e5dc91d15bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721831631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2721831631
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.94400934
Short name T23
Test name
Test status
Simulation time 61289455 ps
CPU time 0.81 seconds
Started Jun 22 04:58:32 PM PDT 24
Finished Jun 22 04:58:33 PM PDT 24
Peak memory 200468 kb
Host smart-413377cc-c800-433b-91fa-04ac06524bb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94400934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.94400934
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.578634092
Short name T473
Test name
Test status
Simulation time 2175831747 ps
CPU time 8.51 seconds
Started Jun 22 04:58:28 PM PDT 24
Finished Jun 22 04:58:37 PM PDT 24
Peak memory 218604 kb
Host smart-479c199c-7fee-4b50-bbeb-40a3cf0397cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578634092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.578634092
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.242931845
Short name T207
Test name
Test status
Simulation time 244235505 ps
CPU time 1.07 seconds
Started Jun 22 04:58:27 PM PDT 24
Finished Jun 22 04:58:28 PM PDT 24
Peak memory 218108 kb
Host smart-d3c341e9-26d8-47cf-938f-85a246376c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242931845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.242931845
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3802319437
Short name T295
Test name
Test status
Simulation time 195831034 ps
CPU time 0.99 seconds
Started Jun 22 04:58:29 PM PDT 24
Finished Jun 22 04:58:31 PM PDT 24
Peak memory 200436 kb
Host smart-064d3e37-2e5c-4169-864a-bf1c1ffea653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802319437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3802319437
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.2378851325
Short name T258
Test name
Test status
Simulation time 1698663226 ps
CPU time 6.08 seconds
Started Jun 22 04:58:29 PM PDT 24
Finished Jun 22 04:58:36 PM PDT 24
Peak memory 200848 kb
Host smart-f341f8ba-d904-42e1-b978-1edb5efa8109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378851325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2378851325
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1824167801
Short name T259
Test name
Test status
Simulation time 110607927 ps
CPU time 1 seconds
Started Jun 22 04:58:40 PM PDT 24
Finished Jun 22 04:58:41 PM PDT 24
Peak memory 200724 kb
Host smart-9446f22b-368b-410e-a054-cb3cc76ed7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824167801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1824167801
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2695307953
Short name T168
Test name
Test status
Simulation time 203701476 ps
CPU time 1.48 seconds
Started Jun 22 04:58:29 PM PDT 24
Finished Jun 22 04:58:31 PM PDT 24
Peak memory 200892 kb
Host smart-2cd59cec-96d2-480c-bcad-31c2385b1d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695307953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2695307953
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3316688545
Short name T537
Test name
Test status
Simulation time 4535110845 ps
CPU time 17.46 seconds
Started Jun 22 04:58:29 PM PDT 24
Finished Jun 22 04:58:48 PM PDT 24
Peak memory 210132 kb
Host smart-bcad8ce8-271c-40c4-a78a-d2a036765518
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316688545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3316688545
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2013985065
Short name T528
Test name
Test status
Simulation time 120247730 ps
CPU time 1.46 seconds
Started Jun 22 04:58:29 PM PDT 24
Finished Jun 22 04:58:31 PM PDT 24
Peak memory 200712 kb
Host smart-57f9c2c0-92c8-4c33-8de4-52ec654c3c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013985065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2013985065
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1901221267
Short name T217
Test name
Test status
Simulation time 157906179 ps
CPU time 1.15 seconds
Started Jun 22 04:58:30 PM PDT 24
Finished Jun 22 04:58:32 PM PDT 24
Peak memory 200704 kb
Host smart-4aae67ab-a08b-43ec-a231-391fda6d2733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901221267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1901221267
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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