Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9026

1

T5

33

T6

16

T7

31

auto[1]

11703

1

T5

29

T6

85

T7

27

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6287	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	7016	1			T1	1		T2	1		T3	1
reset_info_cp[2]	3179	1			T5	10		T6	18		T7	10
reset_info_cp[4]	4301	1			T5	13		T6	17		T7	13
reset_info_cp[8]	127	1			T5	1		T6	1		T10	1
reset_info_cp[16]	105	1			T25	1		T44	2		T101	1
reset_info_cp[32]	111	1			T5	1		T7	1		T42	2
reset_info_cp[64]	99	1			T6	1		T44	1		T101	1
reset_info_cp[128]	124	1			T6	1		T7	2		T8	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3379	1			T5	10		T6	16		T7	11
reset_info_cp[1]	auto[1]	3017	1			T5	10		T6	10		T7	8
reset_info_cp[2]	auto[0]	1080	1			T5	4		T7	6		T8	1
reset_info_cp[2]	auto[1]	2099	1			T5	6		T6	18		T7	4
reset_info_cp[4]	auto[0]	1619	1			T5	7		T7	6		T8	6
reset_info_cp[4]	auto[1]	2682	1			T5	6		T6	17		T7	7
reset_info_cp[8]	auto[0]	51	1			T14	1		T85	1		T88	1
reset_info_cp[8]	auto[1]	76	1			T5	1		T6	1		T10	1
reset_info_cp[16]	auto[0]	48	1			T101	1		T88	2		T128	1
reset_info_cp[16]	auto[1]	57	1			T25	1		T44	2		T88	2
reset_info_cp[32]	auto[0]	40	1			T7	1		T42	1		T88	1
reset_info_cp[32]	auto[1]	71	1			T5	1		T42	1		T43	1
reset_info_cp[64]	auto[0]	49	1			T101	1		T88	2		T89	1
reset_info_cp[64]	auto[1]	50	1			T6	1		T44	1		T91	2
reset_info_cp[128]	auto[0]	47	1			T8	1		T38	1		T85	1
reset_info_cp[128]	auto[1]	77	1			T6	1		T7	2		T14	1