Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T534 /workspace/coverage/default/21.rstmgr_sw_rst.2414709656 Jun 23 05:08:34 PM PDT 24 Jun 23 05:08:37 PM PDT 24 282738427 ps
T535 /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2905358625 Jun 23 05:09:06 PM PDT 24 Jun 23 05:09:08 PM PDT 24 106739210 ps
T536 /workspace/coverage/default/25.rstmgr_alert_test.3095023151 Jun 23 05:08:51 PM PDT 24 Jun 23 05:08:52 PM PDT 24 66572416 ps
T537 /workspace/coverage/default/43.rstmgr_stress_all.727049637 Jun 23 05:09:43 PM PDT 24 Jun 23 05:09:45 PM PDT 24 210788407 ps
T538 /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3073706841 Jun 23 05:08:06 PM PDT 24 Jun 23 05:08:08 PM PDT 24 244499955 ps
T68 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.460299270 Jun 23 05:05:49 PM PDT 24 Jun 23 05:05:51 PM PDT 24 76607187 ps
T69 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1833255635 Jun 23 05:06:01 PM PDT 24 Jun 23 05:06:04 PM PDT 24 198113953 ps
T72 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1578504029 Jun 23 05:05:56 PM PDT 24 Jun 23 05:06:00 PM PDT 24 474501386 ps
T70 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2236850073 Jun 23 05:05:53 PM PDT 24 Jun 23 05:05:55 PM PDT 24 115487080 ps
T71 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1799159572 Jun 23 05:05:49 PM PDT 24 Jun 23 05:05:52 PM PDT 24 487374867 ps
T92 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1149871099 Jun 23 05:05:58 PM PDT 24 Jun 23 05:06:00 PM PDT 24 135447580 ps
T98 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.143535455 Jun 23 05:05:53 PM PDT 24 Jun 23 05:05:56 PM PDT 24 487777215 ps
T105 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.687006573 Jun 23 05:05:59 PM PDT 24 Jun 23 05:06:01 PM PDT 24 224620422 ps
T93 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2484608172 Jun 23 05:05:52 PM PDT 24 Jun 23 05:05:53 PM PDT 24 165657433 ps
T106 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1688783754 Jun 23 05:06:02 PM PDT 24 Jun 23 05:06:04 PM PDT 24 66736776 ps
T97 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2645673791 Jun 23 05:05:54 PM PDT 24 Jun 23 05:05:55 PM PDT 24 145066161 ps
T73 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3389695216 Jun 23 05:05:55 PM PDT 24 Jun 23 05:05:59 PM PDT 24 766826185 ps
T107 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3153336833 Jun 23 05:05:56 PM PDT 24 Jun 23 05:05:58 PM PDT 24 155910583 ps
T94 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3961382435 Jun 23 05:06:03 PM PDT 24 Jun 23 05:06:05 PM PDT 24 139490190 ps
T539 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.38769251 Jun 23 05:05:50 PM PDT 24 Jun 23 05:05:54 PM PDT 24 271666166 ps
T108 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1656424662 Jun 23 05:05:57 PM PDT 24 Jun 23 05:05:59 PM PDT 24 72483284 ps
T109 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1468186520 Jun 23 05:06:00 PM PDT 24 Jun 23 05:06:02 PM PDT 24 229036987 ps
T110 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3364042416 Jun 23 05:05:53 PM PDT 24 Jun 23 05:05:55 PM PDT 24 79780832 ps
T95 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1079060722 Jun 23 05:05:55 PM PDT 24 Jun 23 05:05:57 PM PDT 24 123025946 ps
T111 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.530886763 Jun 23 05:05:58 PM PDT 24 Jun 23 05:06:00 PM PDT 24 106653544 ps
T112 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3775771287 Jun 23 05:06:04 PM PDT 24 Jun 23 05:06:06 PM PDT 24 68648664 ps
T74 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2435352856 Jun 23 05:05:49 PM PDT 24 Jun 23 05:05:52 PM PDT 24 784032002 ps
T113 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1014751203 Jun 23 05:05:53 PM PDT 24 Jun 23 05:05:55 PM PDT 24 187025787 ps
T96 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2603575860 Jun 23 05:06:01 PM PDT 24 Jun 23 05:06:03 PM PDT 24 110497535 ps
T99 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3654714826 Jun 23 05:06:02 PM PDT 24 Jun 23 05:06:04 PM PDT 24 492871835 ps
T122 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3734932282 Jun 23 05:05:58 PM PDT 24 Jun 23 05:06:02 PM PDT 24 946046472 ps
T118 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3614417760 Jun 23 05:05:55 PM PDT 24 Jun 23 05:05:59 PM PDT 24 793710994 ps
T540 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2346334129 Jun 23 05:05:56 PM PDT 24 Jun 23 05:05:58 PM PDT 24 143662091 ps
T114 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1284569797 Jun 23 05:05:51 PM PDT 24 Jun 23 05:05:54 PM PDT 24 803334918 ps
T116 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1277444772 Jun 23 05:06:08 PM PDT 24 Jun 23 05:06:12 PM PDT 24 194691598 ps
T115 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3044318966 Jun 23 05:06:04 PM PDT 24 Jun 23 05:06:07 PM PDT 24 869624353 ps
T541 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.921197200 Jun 23 05:05:48 PM PDT 24 Jun 23 05:05:54 PM PDT 24 1011421272 ps
T542 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.4245857829 Jun 23 05:05:48 PM PDT 24 Jun 23 05:05:49 PM PDT 24 107038051 ps
T543 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3461256150 Jun 23 05:05:51 PM PDT 24 Jun 23 05:05:53 PM PDT 24 142034099 ps
T121 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1321250419 Jun 23 05:05:57 PM PDT 24 Jun 23 05:06:00 PM PDT 24 158071427 ps
T117 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1002407165 Jun 23 05:06:02 PM PDT 24 Jun 23 05:06:05 PM PDT 24 346532710 ps
T544 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.335254052 Jun 23 05:05:54 PM PDT 24 Jun 23 05:05:55 PM PDT 24 63155790 ps
T545 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1759293075 Jun 23 05:05:44 PM PDT 24 Jun 23 05:05:49 PM PDT 24 807540995 ps
T546 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.155898589 Jun 23 05:06:03 PM PDT 24 Jun 23 05:06:04 PM PDT 24 75868035 ps
T547 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.4090279996 Jun 23 05:05:56 PM PDT 24 Jun 23 05:05:58 PM PDT 24 318154688 ps
T548 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.980683800 Jun 23 05:05:54 PM PDT 24 Jun 23 05:05:55 PM PDT 24 142321271 ps
T549 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3009399783 Jun 23 05:05:54 PM PDT 24 Jun 23 05:05:56 PM PDT 24 109063709 ps
T120 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.4053450905 Jun 23 05:05:54 PM PDT 24 Jun 23 05:05:58 PM PDT 24 915792041 ps
T550 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1568626548 Jun 23 05:05:57 PM PDT 24 Jun 23 05:05:58 PM PDT 24 74163471 ps
T551 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2138939650 Jun 23 05:06:00 PM PDT 24 Jun 23 05:06:02 PM PDT 24 212821808 ps
T552 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.530302873 Jun 23 05:05:49 PM PDT 24 Jun 23 05:05:52 PM PDT 24 520792986 ps
T553 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3562843975 Jun 23 05:05:58 PM PDT 24 Jun 23 05:05:59 PM PDT 24 71439946 ps
T119 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1006055437 Jun 23 05:05:43 PM PDT 24 Jun 23 05:05:45 PM PDT 24 438737017 ps
T554 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3929053271 Jun 23 05:05:59 PM PDT 24 Jun 23 05:06:01 PM PDT 24 89163781 ps
T555 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3997379026 Jun 23 05:05:51 PM PDT 24 Jun 23 05:05:52 PM PDT 24 96732461 ps
T556 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.400028462 Jun 23 05:05:59 PM PDT 24 Jun 23 05:06:02 PM PDT 24 280459418 ps
T557 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1807547334 Jun 23 05:05:57 PM PDT 24 Jun 23 05:05:59 PM PDT 24 194738776 ps
T558 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3626851593 Jun 23 05:06:07 PM PDT 24 Jun 23 05:06:09 PM PDT 24 116906802 ps
T559 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2650850811 Jun 23 05:06:01 PM PDT 24 Jun 23 05:06:04 PM PDT 24 473998746 ps
T560 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1637081853 Jun 23 05:05:50 PM PDT 24 Jun 23 05:05:52 PM PDT 24 55445123 ps
T561 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2242913584 Jun 23 05:06:02 PM PDT 24 Jun 23 05:06:03 PM PDT 24 117438842 ps
T562 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3253915211 Jun 23 05:05:54 PM PDT 24 Jun 23 05:05:56 PM PDT 24 143328446 ps
T563 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2217287455 Jun 23 05:05:48 PM PDT 24 Jun 23 05:05:50 PM PDT 24 157996997 ps
T564 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.441978092 Jun 23 05:05:55 PM PDT 24 Jun 23 05:05:57 PM PDT 24 188694669 ps
T565 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3251639039 Jun 23 05:06:01 PM PDT 24 Jun 23 05:06:02 PM PDT 24 73235855 ps
T566 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2166800049 Jun 23 05:05:57 PM PDT 24 Jun 23 05:05:59 PM PDT 24 63988745 ps
T567 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2447112349 Jun 23 05:05:49 PM PDT 24 Jun 23 05:05:50 PM PDT 24 141986891 ps
T568 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.534033293 Jun 23 05:05:57 PM PDT 24 Jun 23 05:05:59 PM PDT 24 119860168 ps
T569 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.689544045 Jun 23 05:05:49 PM PDT 24 Jun 23 05:05:52 PM PDT 24 405490489 ps
T570 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2436713360 Jun 23 05:05:53 PM PDT 24 Jun 23 05:05:54 PM PDT 24 123900469 ps
T571 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1713599077 Jun 23 05:05:52 PM PDT 24 Jun 23 05:05:53 PM PDT 24 127240116 ps
T572 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2337326208 Jun 23 05:05:58 PM PDT 24 Jun 23 05:06:00 PM PDT 24 424828093 ps
T573 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1859901890 Jun 23 05:05:56 PM PDT 24 Jun 23 05:05:57 PM PDT 24 68151131 ps
T574 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.969060310 Jun 23 05:05:57 PM PDT 24 Jun 23 05:05:58 PM PDT 24 71112391 ps
T575 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1671519711 Jun 23 05:05:50 PM PDT 24 Jun 23 05:05:52 PM PDT 24 62826124 ps
T576 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3886343153 Jun 23 05:06:07 PM PDT 24 Jun 23 05:06:11 PM PDT 24 479822427 ps
T577 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.357349442 Jun 23 05:05:53 PM PDT 24 Jun 23 05:05:56 PM PDT 24 101857336 ps
T578 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.473205366 Jun 23 05:05:42 PM PDT 24 Jun 23 05:05:43 PM PDT 24 60860267 ps
T579 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1000394565 Jun 23 05:05:57 PM PDT 24 Jun 23 05:05:59 PM PDT 24 142663608 ps
T580 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3177377427 Jun 23 05:05:52 PM PDT 24 Jun 23 05:05:54 PM PDT 24 447872204 ps
T581 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2458853784 Jun 23 05:05:53 PM PDT 24 Jun 23 05:05:54 PM PDT 24 74788033 ps
T582 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1210245619 Jun 23 05:05:44 PM PDT 24 Jun 23 05:05:48 PM PDT 24 459608135 ps
T583 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.4259524573 Jun 23 05:05:55 PM PDT 24 Jun 23 05:05:58 PM PDT 24 203207162 ps
T584 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1795783176 Jun 23 05:06:01 PM PDT 24 Jun 23 05:06:03 PM PDT 24 65080957 ps
T585 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3658719497 Jun 23 05:05:55 PM PDT 24 Jun 23 05:05:59 PM PDT 24 881041860 ps
T586 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.177537866 Jun 23 05:05:47 PM PDT 24 Jun 23 05:05:50 PM PDT 24 179958084 ps
T587 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.814511830 Jun 23 05:05:53 PM PDT 24 Jun 23 05:05:57 PM PDT 24 269579124 ps
T588 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2991150325 Jun 23 05:05:53 PM PDT 24 Jun 23 05:05:55 PM PDT 24 100279862 ps
T589 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1431169044 Jun 23 05:06:06 PM PDT 24 Jun 23 05:06:08 PM PDT 24 197855864 ps
T590 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2374372637 Jun 23 05:05:51 PM PDT 24 Jun 23 05:05:55 PM PDT 24 233824467 ps
T591 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3359304266 Jun 23 05:05:51 PM PDT 24 Jun 23 05:05:54 PM PDT 24 351453474 ps
T592 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4001927726 Jun 23 05:05:47 PM PDT 24 Jun 23 05:05:49 PM PDT 24 113570142 ps
T593 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.67543104 Jun 23 05:05:59 PM PDT 24 Jun 23 05:06:00 PM PDT 24 73400055 ps
T594 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1865110913 Jun 23 05:06:01 PM PDT 24 Jun 23 05:06:04 PM PDT 24 117664859 ps
T595 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3002454553 Jun 23 05:05:48 PM PDT 24 Jun 23 05:05:49 PM PDT 24 111955645 ps
T596 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1671658867 Jun 23 05:05:53 PM PDT 24 Jun 23 05:05:54 PM PDT 24 83576360 ps
T597 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1977738935 Jun 23 05:05:49 PM PDT 24 Jun 23 05:05:50 PM PDT 24 86368237 ps
T598 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3640404770 Jun 23 05:05:59 PM PDT 24 Jun 23 05:06:01 PM PDT 24 83949428 ps
T599 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1040034737 Jun 23 05:05:49 PM PDT 24 Jun 23 05:05:52 PM PDT 24 346120107 ps
T600 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2676765151 Jun 23 05:05:53 PM PDT 24 Jun 23 05:05:55 PM PDT 24 143124450 ps
T601 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2748476632 Jun 23 05:05:59 PM PDT 24 Jun 23 05:06:01 PM PDT 24 76867704 ps
T602 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3270244394 Jun 23 05:05:57 PM PDT 24 Jun 23 05:05:59 PM PDT 24 79238087 ps
T603 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2506085530 Jun 23 05:05:57 PM PDT 24 Jun 23 05:06:00 PM PDT 24 233499184 ps
T604 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3059178882 Jun 23 05:05:59 PM PDT 24 Jun 23 05:06:03 PM PDT 24 866167475 ps
T605 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4156048909 Jun 23 05:05:54 PM PDT 24 Jun 23 05:05:56 PM PDT 24 166863585 ps
T606 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3801265395 Jun 23 05:06:01 PM PDT 24 Jun 23 05:06:03 PM PDT 24 197068695 ps
T607 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2065175964 Jun 23 05:05:59 PM PDT 24 Jun 23 05:06:02 PM PDT 24 373411039 ps
T608 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3336689431 Jun 23 05:06:02 PM PDT 24 Jun 23 05:06:04 PM PDT 24 70746163 ps
T609 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2416568197 Jun 23 05:06:01 PM PDT 24 Jun 23 05:06:04 PM PDT 24 1077121271 ps
T610 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2788667335 Jun 23 05:05:58 PM PDT 24 Jun 23 05:06:01 PM PDT 24 127993807 ps
T611 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3946760131 Jun 23 05:05:51 PM PDT 24 Jun 23 05:05:55 PM PDT 24 213495107 ps
T612 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.465876287 Jun 23 05:06:02 PM PDT 24 Jun 23 05:06:06 PM PDT 24 201276835 ps
T613 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3677556137 Jun 23 05:06:01 PM PDT 24 Jun 23 05:06:05 PM PDT 24 565702105 ps
T614 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2927959058 Jun 23 05:05:43 PM PDT 24 Jun 23 05:05:45 PM PDT 24 128328769 ps
T615 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2359028278 Jun 23 05:05:51 PM PDT 24 Jun 23 05:05:56 PM PDT 24 794954334 ps
T616 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3063115361 Jun 23 05:05:50 PM PDT 24 Jun 23 05:05:53 PM PDT 24 381326547 ps
T617 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.399928759 Jun 23 05:06:00 PM PDT 24 Jun 23 05:06:02 PM PDT 24 218066297 ps
T618 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1631289684 Jun 23 05:05:57 PM PDT 24 Jun 23 05:06:01 PM PDT 24 941407140 ps
T619 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1883348659 Jun 23 05:05:50 PM PDT 24 Jun 23 05:05:53 PM PDT 24 201691760 ps
T620 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.771257260 Jun 23 05:05:56 PM PDT 24 Jun 23 05:05:59 PM PDT 24 778445220 ps

Test location /workspace/coverage/default/41.rstmgr_stress_all.1228569123
Short name T7
Test name
Test status
Simulation time 2234842275 ps
CPU time 9.51 seconds
Started Jun 23 05:09:36 PM PDT 24
Finished Jun 23 05:09:46 PM PDT 24
Peak memory 200980 kb
Host smart-4fce05f4-2aab-4aab-8424-81abe5ecf95b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228569123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1228569123
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3422318288
Short name T11
Test name
Test status
Simulation time 156572364 ps
CPU time 1.92 seconds
Started Jun 23 05:08:46 PM PDT 24
Finished Jun 23 05:08:49 PM PDT 24
Peak memory 200664 kb
Host smart-1355a1be-af34-44e8-973d-36bcc7195d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422318288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3422318288
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1833255635
Short name T69
Test name
Test status
Simulation time 198113953 ps
CPU time 1.42 seconds
Started Jun 23 05:06:01 PM PDT 24
Finished Jun 23 05:06:04 PM PDT 24
Peak memory 208896 kb
Host smart-a45c0a7c-b807-4193-af2c-3c7f0e14e7f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833255635 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.1833255635
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1888026241
Short name T75
Test name
Test status
Simulation time 16552829411 ps
CPU time 25.1 seconds
Started Jun 23 05:07:24 PM PDT 24
Finished Jun 23 05:07:49 PM PDT 24
Peak memory 218276 kb
Host smart-9fe022e0-a266-4911-9fb2-fc6e64ab3721
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888026241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1888026241
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.164152693
Short name T6
Test name
Test status
Simulation time 1238827100 ps
CPU time 5.59 seconds
Started Jun 23 05:09:05 PM PDT 24
Finished Jun 23 05:09:11 PM PDT 24
Peak memory 222428 kb
Host smart-1b2415e6-224a-46aa-9243-7a99be8687ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164152693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.164152693
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1200810551
Short name T83
Test name
Test status
Simulation time 7791675335 ps
CPU time 36.21 seconds
Started Jun 23 05:08:04 PM PDT 24
Finished Jun 23 05:08:41 PM PDT 24
Peak memory 200952 kb
Host smart-e5cc71e0-9929-40cc-a192-15a2c21304a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200810551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1200810551
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2435352856
Short name T74
Test name
Test status
Simulation time 784032002 ps
CPU time 2.74 seconds
Started Jun 23 05:05:49 PM PDT 24
Finished Jun 23 05:05:52 PM PDT 24
Peak memory 200964 kb
Host smart-03ac2882-9e3c-46b7-b656-5676af21a82b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435352856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.2435352856
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.540184602
Short name T129
Test name
Test status
Simulation time 58291007 ps
CPU time 0.74 seconds
Started Jun 23 05:07:27 PM PDT 24
Finished Jun 23 05:07:28 PM PDT 24
Peak memory 200548 kb
Host smart-b665f5bd-1522-474f-9891-97e7be63350a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540184602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.540184602
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1578504029
Short name T72
Test name
Test status
Simulation time 474501386 ps
CPU time 3.6 seconds
Started Jun 23 05:05:56 PM PDT 24
Finished Jun 23 05:06:00 PM PDT 24
Peak memory 212232 kb
Host smart-58bb64f2-179b-4a4c-beb4-d05547959087
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578504029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1578504029
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3274984034
Short name T148
Test name
Test status
Simulation time 97146810 ps
CPU time 0.97 seconds
Started Jun 23 05:08:06 PM PDT 24
Finished Jun 23 05:08:08 PM PDT 24
Peak memory 200656 kb
Host smart-3cb9fdda-42a4-4e27-a359-21285a296cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274984034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3274984034
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3123240530
Short name T25
Test name
Test status
Simulation time 2370960674 ps
CPU time 8.17 seconds
Started Jun 23 05:09:05 PM PDT 24
Finished Jun 23 05:09:14 PM PDT 24
Peak memory 218552 kb
Host smart-4152c873-680a-483b-8998-4bab7334c131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123240530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3123240530
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2497626432
Short name T53
Test name
Test status
Simulation time 1893872690 ps
CPU time 7.4 seconds
Started Jun 23 05:08:33 PM PDT 24
Finished Jun 23 05:08:41 PM PDT 24
Peak memory 222480 kb
Host smart-2edef7cb-77e1-4fbc-b62c-f288084d97a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497626432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2497626432
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.403054340
Short name T128
Test name
Test status
Simulation time 286040829 ps
CPU time 1.44 seconds
Started Jun 23 05:07:36 PM PDT 24
Finished Jun 23 05:07:38 PM PDT 24
Peak memory 200920 kb
Host smart-e0f4da88-ac44-4876-a703-c77988c50c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403054340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.403054340
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3044318966
Short name T115
Test name
Test status
Simulation time 869624353 ps
CPU time 3.01 seconds
Started Jun 23 05:06:04 PM PDT 24
Finished Jun 23 05:06:07 PM PDT 24
Peak memory 200872 kb
Host smart-5c7d8ac7-6a70-4d8e-827a-d2332b3306e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044318966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3044318966
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.460299270
Short name T68
Test name
Test status
Simulation time 76607187 ps
CPU time 1 seconds
Started Jun 23 05:05:49 PM PDT 24
Finished Jun 23 05:05:51 PM PDT 24
Peak memory 200604 kb
Host smart-9befb231-ba6c-4a75-9d4c-dae0d726ec67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460299270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sam
e_csr_outstanding.460299270
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3126568891
Short name T24
Test name
Test status
Simulation time 216446718 ps
CPU time 1.01 seconds
Started Jun 23 05:08:30 PM PDT 24
Finished Jun 23 05:08:31 PM PDT 24
Peak memory 200504 kb
Host smart-f9e70a08-2810-4fd7-908f-6e8da2cc8871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126568891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3126568891
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3786686251
Short name T157
Test name
Test status
Simulation time 244571587 ps
CPU time 1.05 seconds
Started Jun 23 05:07:20 PM PDT 24
Finished Jun 23 05:07:21 PM PDT 24
Peak memory 218128 kb
Host smart-61de1324-fc78-4298-941d-9f8bc313d8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786686251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3786686251
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.2586776161
Short name T46
Test name
Test status
Simulation time 1218244785 ps
CPU time 6.24 seconds
Started Jun 23 05:08:04 PM PDT 24
Finished Jun 23 05:08:11 PM PDT 24
Peak memory 222500 kb
Host smart-0e721fd7-0895-400b-9cd5-84c95f21c540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586776161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.2586776161
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1006055437
Short name T119
Test name
Test status
Simulation time 438737017 ps
CPU time 1.87 seconds
Started Jun 23 05:05:43 PM PDT 24
Finished Jun 23 05:05:45 PM PDT 24
Peak memory 200844 kb
Host smart-a4a25d84-8365-4e01-a48a-8cf755d7fc11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006055437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1006055437
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4001927726
Short name T592
Test name
Test status
Simulation time 113570142 ps
CPU time 1.35 seconds
Started Jun 23 05:05:47 PM PDT 24
Finished Jun 23 05:05:49 PM PDT 24
Peak memory 201020 kb
Host smart-651cf84d-fdc2-467f-a247-5eb4dc393a80
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001927726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.4
001927726
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1759293075
Short name T545
Test name
Test status
Simulation time 807540995 ps
CPU time 4.19 seconds
Started Jun 23 05:05:44 PM PDT 24
Finished Jun 23 05:05:49 PM PDT 24
Peak memory 200828 kb
Host smart-054abef8-44c7-4fc6-a30d-782392be4d2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759293075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
759293075
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2927959058
Short name T614
Test name
Test status
Simulation time 128328769 ps
CPU time 0.96 seconds
Started Jun 23 05:05:43 PM PDT 24
Finished Jun 23 05:05:45 PM PDT 24
Peak memory 200648 kb
Host smart-3f6b7dde-3623-45ca-aecc-290af1749f61
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927959058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
927959058
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2484608172
Short name T93
Test name
Test status
Simulation time 165657433 ps
CPU time 1.15 seconds
Started Jun 23 05:05:52 PM PDT 24
Finished Jun 23 05:05:53 PM PDT 24
Peak memory 210316 kb
Host smart-6d99c644-e502-4a40-8174-9edae550c85f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484608172 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2484608172
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.473205366
Short name T578
Test name
Test status
Simulation time 60860267 ps
CPU time 0.77 seconds
Started Jun 23 05:05:42 PM PDT 24
Finished Jun 23 05:05:43 PM PDT 24
Peak memory 200496 kb
Host smart-fe87905d-193f-4513-900e-a4c5f582cafe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473205366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.473205366
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1210245619
Short name T582
Test name
Test status
Simulation time 459608135 ps
CPU time 3.09 seconds
Started Jun 23 05:05:44 PM PDT 24
Finished Jun 23 05:05:48 PM PDT 24
Peak memory 209212 kb
Host smart-aea0af2c-5e18-4dc3-8a0e-1d93d8c3f5ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210245619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1210245619
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2991150325
Short name T588
Test name
Test status
Simulation time 100279862 ps
CPU time 1.36 seconds
Started Jun 23 05:05:53 PM PDT 24
Finished Jun 23 05:05:55 PM PDT 24
Peak memory 201000 kb
Host smart-e5443dc1-429d-4fb6-8e7a-7f950d332bb8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991150325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
991150325
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2359028278
Short name T615
Test name
Test status
Simulation time 794954334 ps
CPU time 4.49 seconds
Started Jun 23 05:05:51 PM PDT 24
Finished Jun 23 05:05:56 PM PDT 24
Peak memory 200876 kb
Host smart-74e481a4-8008-4666-b3f8-13e79a30d19b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359028278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
359028278
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.980683800
Short name T548
Test name
Test status
Simulation time 142321271 ps
CPU time 0.94 seconds
Started Jun 23 05:05:54 PM PDT 24
Finished Jun 23 05:05:55 PM PDT 24
Peak memory 200728 kb
Host smart-b2e4b627-9386-4dc2-b227-3e66424256d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980683800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.980683800
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1713599077
Short name T571
Test name
Test status
Simulation time 127240116 ps
CPU time 0.98 seconds
Started Jun 23 05:05:52 PM PDT 24
Finished Jun 23 05:05:53 PM PDT 24
Peak memory 200760 kb
Host smart-901b2c61-0230-434c-874b-49d92a37183b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713599077 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1713599077
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1671519711
Short name T575
Test name
Test status
Simulation time 62826124 ps
CPU time 0.78 seconds
Started Jun 23 05:05:50 PM PDT 24
Finished Jun 23 05:05:52 PM PDT 24
Peak memory 200696 kb
Host smart-4a2c3689-a478-47b5-9098-fc6c8e5d0e9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671519711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1671519711
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1883348659
Short name T619
Test name
Test status
Simulation time 201691760 ps
CPU time 1.45 seconds
Started Jun 23 05:05:50 PM PDT 24
Finished Jun 23 05:05:53 PM PDT 24
Peak memory 200872 kb
Host smart-52306103-1af9-4200-8d57-2f34575ce34b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883348659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1883348659
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3946760131
Short name T611
Test name
Test status
Simulation time 213495107 ps
CPU time 2.96 seconds
Started Jun 23 05:05:51 PM PDT 24
Finished Jun 23 05:05:55 PM PDT 24
Peak memory 209064 kb
Host smart-0f8f5a92-3660-4375-a782-f71c4a7e2678
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946760131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3946760131
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2676765151
Short name T600
Test name
Test status
Simulation time 143124450 ps
CPU time 1.23 seconds
Started Jun 23 05:05:53 PM PDT 24
Finished Jun 23 05:05:55 PM PDT 24
Peak memory 208900 kb
Host smart-c374a5a4-18d8-4398-95cb-331786cccb1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676765151 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2676765151
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.335254052
Short name T544
Test name
Test status
Simulation time 63155790 ps
CPU time 0.78 seconds
Started Jun 23 05:05:54 PM PDT 24
Finished Jun 23 05:05:55 PM PDT 24
Peak memory 200648 kb
Host smart-1794077d-e67d-40bd-b128-e7c3c9b76b9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335254052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.335254052
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.530886763
Short name T111
Test name
Test status
Simulation time 106653544 ps
CPU time 1.23 seconds
Started Jun 23 05:05:58 PM PDT 24
Finished Jun 23 05:06:00 PM PDT 24
Peak memory 200868 kb
Host smart-1405d592-baed-45b7-bba0-c6a4138cbb16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530886763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.530886763
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.4259524573
Short name T583
Test name
Test status
Simulation time 203207162 ps
CPU time 2.99 seconds
Started Jun 23 05:05:55 PM PDT 24
Finished Jun 23 05:05:58 PM PDT 24
Peak memory 209140 kb
Host smart-a36cf6a6-e5cc-4e8f-80af-6c94c6b45d28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259524573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.4259524573
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3614417760
Short name T118
Test name
Test status
Simulation time 793710994 ps
CPU time 2.81 seconds
Started Jun 23 05:05:55 PM PDT 24
Finished Jun 23 05:05:59 PM PDT 24
Peak memory 201060 kb
Host smart-f5b2c936-0d04-4cbc-aae8-403e14386c3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614417760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3614417760
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.534033293
Short name T568
Test name
Test status
Simulation time 119860168 ps
CPU time 0.98 seconds
Started Jun 23 05:05:57 PM PDT 24
Finished Jun 23 05:05:59 PM PDT 24
Peak memory 200716 kb
Host smart-49bce5ee-a1b9-4186-a3c7-1cfe0b24482c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534033293 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.534033293
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.969060310
Short name T574
Test name
Test status
Simulation time 71112391 ps
CPU time 0.8 seconds
Started Jun 23 05:05:57 PM PDT 24
Finished Jun 23 05:05:58 PM PDT 24
Peak memory 200696 kb
Host smart-c2a0b9d6-e265-4ae8-ab79-8de11ead155e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969060310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.969060310
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3153336833
Short name T107
Test name
Test status
Simulation time 155910583 ps
CPU time 1.17 seconds
Started Jun 23 05:05:56 PM PDT 24
Finished Jun 23 05:05:58 PM PDT 24
Peak memory 200608 kb
Host smart-6cd2c2f2-7fdf-4770-acd0-2b08bffa4bb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153336833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.3153336833
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.357349442
Short name T577
Test name
Test status
Simulation time 101857336 ps
CPU time 1.4 seconds
Started Jun 23 05:05:53 PM PDT 24
Finished Jun 23 05:05:56 PM PDT 24
Peak memory 209092 kb
Host smart-40be4a56-5a4a-4b92-9e21-e0ee3dcc2895
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357349442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.357349442
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2337326208
Short name T572
Test name
Test status
Simulation time 424828093 ps
CPU time 1.79 seconds
Started Jun 23 05:05:58 PM PDT 24
Finished Jun 23 05:06:00 PM PDT 24
Peak memory 200952 kb
Host smart-018e7abd-6497-416e-8a7f-8d571f87ccc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337326208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2337326208
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1807547334
Short name T557
Test name
Test status
Simulation time 194738776 ps
CPU time 1.22 seconds
Started Jun 23 05:05:57 PM PDT 24
Finished Jun 23 05:05:59 PM PDT 24
Peak memory 208940 kb
Host smart-70286cea-c011-4d4b-aa7f-0cb09d33a4f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807547334 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1807547334
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3562843975
Short name T553
Test name
Test status
Simulation time 71439946 ps
CPU time 0.79 seconds
Started Jun 23 05:05:58 PM PDT 24
Finished Jun 23 05:05:59 PM PDT 24
Peak memory 200696 kb
Host smart-fd48b7a2-f633-4075-8ac1-34e1ffa2da8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562843975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3562843975
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3009399783
Short name T549
Test name
Test status
Simulation time 109063709 ps
CPU time 1.28 seconds
Started Jun 23 05:05:54 PM PDT 24
Finished Jun 23 05:05:56 PM PDT 24
Peak memory 200896 kb
Host smart-d1683a20-2b66-4d5e-ba0e-591c0f282cdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009399783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.3009399783
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.400028462
Short name T556
Test name
Test status
Simulation time 280459418 ps
CPU time 2.11 seconds
Started Jun 23 05:05:59 PM PDT 24
Finished Jun 23 05:06:02 PM PDT 24
Peak memory 209160 kb
Host smart-0d0d34da-cb5b-42f9-96b2-1082172f6006
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400028462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.400028462
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.143535455
Short name T98
Test name
Test status
Simulation time 487777215 ps
CPU time 1.93 seconds
Started Jun 23 05:05:53 PM PDT 24
Finished Jun 23 05:05:56 PM PDT 24
Peak memory 200880 kb
Host smart-9df1164d-3ce0-4b27-b5bf-4b6191339277
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143535455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.143535455
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1000394565
Short name T579
Test name
Test status
Simulation time 142663608 ps
CPU time 1.15 seconds
Started Jun 23 05:05:57 PM PDT 24
Finished Jun 23 05:05:59 PM PDT 24
Peak memory 208840 kb
Host smart-d3c81f91-65f6-4a94-ac1d-0d898b7aadd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000394565 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.1000394565
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1656424662
Short name T108
Test name
Test status
Simulation time 72483284 ps
CPU time 0.9 seconds
Started Jun 23 05:05:57 PM PDT 24
Finished Jun 23 05:05:59 PM PDT 24
Peak memory 200616 kb
Host smart-a28dac4e-5bcd-442b-b1a4-8b68770fe372
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656424662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1656424662
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1014751203
Short name T113
Test name
Test status
Simulation time 187025787 ps
CPU time 1.49 seconds
Started Jun 23 05:05:53 PM PDT 24
Finished Jun 23 05:05:55 PM PDT 24
Peak memory 200768 kb
Host smart-c16aa5c9-0e89-4c27-aa46-4a0b368174dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014751203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1014751203
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.4090279996
Short name T547
Test name
Test status
Simulation time 318154688 ps
CPU time 2.07 seconds
Started Jun 23 05:05:56 PM PDT 24
Finished Jun 23 05:05:58 PM PDT 24
Peak memory 209028 kb
Host smart-fdb29e80-8d0b-4b5b-8cf0-006511b7e7c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090279996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.4090279996
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3389695216
Short name T73
Test name
Test status
Simulation time 766826185 ps
CPU time 3.06 seconds
Started Jun 23 05:05:55 PM PDT 24
Finished Jun 23 05:05:59 PM PDT 24
Peak memory 200884 kb
Host smart-e7857fc9-8a2e-464a-92c7-5cb65514f4ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389695216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3389695216
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2242913584
Short name T561
Test name
Test status
Simulation time 117438842 ps
CPU time 1.01 seconds
Started Jun 23 05:06:02 PM PDT 24
Finished Jun 23 05:06:03 PM PDT 24
Peak memory 200748 kb
Host smart-a8c5bbc9-5c4d-4b47-8cf0-91d75a23b22c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242913584 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2242913584
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3336689431
Short name T608
Test name
Test status
Simulation time 70746163 ps
CPU time 0.8 seconds
Started Jun 23 05:06:02 PM PDT 24
Finished Jun 23 05:06:04 PM PDT 24
Peak memory 200584 kb
Host smart-0b96f5ab-95a4-4385-b2ed-eeee85ffd294
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336689431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3336689431
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2748476632
Short name T601
Test name
Test status
Simulation time 76867704 ps
CPU time 0.93 seconds
Started Jun 23 05:05:59 PM PDT 24
Finished Jun 23 05:06:01 PM PDT 24
Peak memory 200596 kb
Host smart-966cb9ce-eabb-4e56-945c-35940c633cf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748476632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2748476632
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1002407165
Short name T117
Test name
Test status
Simulation time 346532710 ps
CPU time 2.59 seconds
Started Jun 23 05:06:02 PM PDT 24
Finished Jun 23 05:06:05 PM PDT 24
Peak memory 212824 kb
Host smart-1cf205a1-62f1-43bb-a4ee-cbda067442d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002407165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1002407165
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2650850811
Short name T559
Test name
Test status
Simulation time 473998746 ps
CPU time 2.13 seconds
Started Jun 23 05:06:01 PM PDT 24
Finished Jun 23 05:06:04 PM PDT 24
Peak memory 200892 kb
Host smart-0a0160a6-c4af-45ff-a534-b06ac1d90de2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650850811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2650850811
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3801265395
Short name T606
Test name
Test status
Simulation time 197068695 ps
CPU time 1.39 seconds
Started Jun 23 05:06:01 PM PDT 24
Finished Jun 23 05:06:03 PM PDT 24
Peak memory 200724 kb
Host smart-5b4fd221-d5cf-4100-8511-9178dce07c25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801265395 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3801265395
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3251639039
Short name T565
Test name
Test status
Simulation time 73235855 ps
CPU time 0.84 seconds
Started Jun 23 05:06:01 PM PDT 24
Finished Jun 23 05:06:02 PM PDT 24
Peak memory 200524 kb
Host smart-7f0750bf-6c32-49e3-af65-eecbe3af6842
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251639039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3251639039
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3640404770
Short name T598
Test name
Test status
Simulation time 83949428 ps
CPU time 0.99 seconds
Started Jun 23 05:05:59 PM PDT 24
Finished Jun 23 05:06:01 PM PDT 24
Peak memory 200572 kb
Host smart-57583efe-de34-46cb-8be1-e88b25e860fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640404770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.3640404770
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2138939650
Short name T551
Test name
Test status
Simulation time 212821808 ps
CPU time 1.83 seconds
Started Jun 23 05:06:00 PM PDT 24
Finished Jun 23 05:06:02 PM PDT 24
Peak memory 211688 kb
Host smart-b6e1dad6-6e7b-410e-aed4-d61a1f694e1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138939650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2138939650
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2603575860
Short name T96
Test name
Test status
Simulation time 110497535 ps
CPU time 1.2 seconds
Started Jun 23 05:06:01 PM PDT 24
Finished Jun 23 05:06:03 PM PDT 24
Peak memory 208880 kb
Host smart-2e070b35-7776-4404-a5a2-e1c359758348
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603575860 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2603575860
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1795783176
Short name T584
Test name
Test status
Simulation time 65080957 ps
CPU time 0.84 seconds
Started Jun 23 05:06:01 PM PDT 24
Finished Jun 23 05:06:03 PM PDT 24
Peak memory 200616 kb
Host smart-eca6e64f-a7e1-4453-b604-39eb54ad941d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795783176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1795783176
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1468186520
Short name T109
Test name
Test status
Simulation time 229036987 ps
CPU time 1.55 seconds
Started Jun 23 05:06:00 PM PDT 24
Finished Jun 23 05:06:02 PM PDT 24
Peak memory 200860 kb
Host smart-9fea37d0-42df-4df5-8350-30eea3a128f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468186520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1468186520
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3677556137
Short name T613
Test name
Test status
Simulation time 565702105 ps
CPU time 3.86 seconds
Started Jun 23 05:06:01 PM PDT 24
Finished Jun 23 05:06:05 PM PDT 24
Peak memory 208968 kb
Host smart-0f522b00-b11a-4f9c-affe-4f42d79291ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677556137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3677556137
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3059178882
Short name T604
Test name
Test status
Simulation time 866167475 ps
CPU time 3.13 seconds
Started Jun 23 05:05:59 PM PDT 24
Finished Jun 23 05:06:03 PM PDT 24
Peak memory 200860 kb
Host smart-bc5fa87e-8ce3-4c9e-8046-79d123c3f407
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059178882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3059178882
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1688783754
Short name T106
Test name
Test status
Simulation time 66736776 ps
CPU time 0.85 seconds
Started Jun 23 05:06:02 PM PDT 24
Finished Jun 23 05:06:04 PM PDT 24
Peak memory 200652 kb
Host smart-16006240-7da0-4425-8b41-c1ea1282d0e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688783754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1688783754
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.399928759
Short name T617
Test name
Test status
Simulation time 218066297 ps
CPU time 1.46 seconds
Started Jun 23 05:06:00 PM PDT 24
Finished Jun 23 05:06:02 PM PDT 24
Peak memory 200864 kb
Host smart-ec3b9353-ffc0-4569-b446-088b2ccbd5d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399928759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.399928759
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.465876287
Short name T612
Test name
Test status
Simulation time 201276835 ps
CPU time 3.14 seconds
Started Jun 23 05:06:02 PM PDT 24
Finished Jun 23 05:06:06 PM PDT 24
Peak memory 217184 kb
Host smart-011367b9-473f-4d9b-b9d1-60ed551c90df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465876287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.465876287
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3654714826
Short name T99
Test name
Test status
Simulation time 492871835 ps
CPU time 1.96 seconds
Started Jun 23 05:06:02 PM PDT 24
Finished Jun 23 05:06:04 PM PDT 24
Peak memory 200904 kb
Host smart-9dc7ab86-8bdb-4018-9cbe-c7c382784e60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654714826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3654714826
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3961382435
Short name T94
Test name
Test status
Simulation time 139490190 ps
CPU time 1.16 seconds
Started Jun 23 05:06:03 PM PDT 24
Finished Jun 23 05:06:05 PM PDT 24
Peak memory 200704 kb
Host smart-3d08eabc-c86f-467d-a9e2-290fd24f27f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961382435 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3961382435
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3929053271
Short name T554
Test name
Test status
Simulation time 89163781 ps
CPU time 0.92 seconds
Started Jun 23 05:05:59 PM PDT 24
Finished Jun 23 05:06:01 PM PDT 24
Peak memory 200696 kb
Host smart-fa695e8b-ac8e-46e9-a408-3eda39272fb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929053271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3929053271
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.155898589
Short name T546
Test name
Test status
Simulation time 75868035 ps
CPU time 0.99 seconds
Started Jun 23 05:06:03 PM PDT 24
Finished Jun 23 05:06:04 PM PDT 24
Peak memory 200680 kb
Host smart-ec370528-7e24-4dbf-980a-ff781729d449
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155898589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.155898589
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1865110913
Short name T594
Test name
Test status
Simulation time 117664859 ps
CPU time 1.6 seconds
Started Jun 23 05:06:01 PM PDT 24
Finished Jun 23 05:06:04 PM PDT 24
Peak memory 209092 kb
Host smart-29055dea-d69a-4422-b636-d51858e2586b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865110913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1865110913
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2416568197
Short name T609
Test name
Test status
Simulation time 1077121271 ps
CPU time 3.26 seconds
Started Jun 23 05:06:01 PM PDT 24
Finished Jun 23 05:06:04 PM PDT 24
Peak memory 201024 kb
Host smart-b5349bd7-9c56-45fe-8c05-9b79f5ac752a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416568197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2416568197
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1431169044
Short name T589
Test name
Test status
Simulation time 197855864 ps
CPU time 1.37 seconds
Started Jun 23 05:06:06 PM PDT 24
Finished Jun 23 05:06:08 PM PDT 24
Peak memory 208856 kb
Host smart-14d78242-3b2f-4568-bc8d-3c133b69ebe5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431169044 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1431169044
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3775771287
Short name T112
Test name
Test status
Simulation time 68648664 ps
CPU time 0.75 seconds
Started Jun 23 05:06:04 PM PDT 24
Finished Jun 23 05:06:06 PM PDT 24
Peak memory 200692 kb
Host smart-80a31ce6-e92d-4859-943e-32a75fe4e93a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775771287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3775771287
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3626851593
Short name T558
Test name
Test status
Simulation time 116906802 ps
CPU time 1.22 seconds
Started Jun 23 05:06:07 PM PDT 24
Finished Jun 23 05:06:09 PM PDT 24
Peak memory 200872 kb
Host smart-a3163b1f-0f1c-4051-9523-261c39f73e6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626851593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3626851593
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1277444772
Short name T116
Test name
Test status
Simulation time 194691598 ps
CPU time 2.72 seconds
Started Jun 23 05:06:08 PM PDT 24
Finished Jun 23 05:06:12 PM PDT 24
Peak memory 208992 kb
Host smart-0f88ec6a-a8a8-4c35-a883-775470c2403f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277444772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1277444772
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3886343153
Short name T576
Test name
Test status
Simulation time 479822427 ps
CPU time 2.07 seconds
Started Jun 23 05:06:07 PM PDT 24
Finished Jun 23 05:06:11 PM PDT 24
Peak memory 201024 kb
Host smart-5804a914-edba-4805-a5ee-5d6d976d2a35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886343153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3886343153
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3359304266
Short name T591
Test name
Test status
Simulation time 351453474 ps
CPU time 2.25 seconds
Started Jun 23 05:05:51 PM PDT 24
Finished Jun 23 05:05:54 PM PDT 24
Peak memory 200948 kb
Host smart-baa0667f-f15f-4431-9559-3ba15095013e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359304266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
359304266
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.921197200
Short name T541
Test name
Test status
Simulation time 1011421272 ps
CPU time 5.09 seconds
Started Jun 23 05:05:48 PM PDT 24
Finished Jun 23 05:05:54 PM PDT 24
Peak memory 200880 kb
Host smart-1e1f4c51-9d0b-477a-902d-812d60d742ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921197200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.921197200
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2447112349
Short name T567
Test name
Test status
Simulation time 141986891 ps
CPU time 0.92 seconds
Started Jun 23 05:05:49 PM PDT 24
Finished Jun 23 05:05:50 PM PDT 24
Peak memory 200636 kb
Host smart-4dcca687-c72c-4308-8f6b-732896f55eaf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447112349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
447112349
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.4245857829
Short name T542
Test name
Test status
Simulation time 107038051 ps
CPU time 0.92 seconds
Started Jun 23 05:05:48 PM PDT 24
Finished Jun 23 05:05:49 PM PDT 24
Peak memory 200736 kb
Host smart-21cbe0b1-7232-4e7e-b8fe-8dc9b7432381
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245857829 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.4245857829
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1637081853
Short name T560
Test name
Test status
Simulation time 55445123 ps
CPU time 0.77 seconds
Started Jun 23 05:05:50 PM PDT 24
Finished Jun 23 05:05:52 PM PDT 24
Peak memory 200860 kb
Host smart-da26e746-3033-4c2b-b330-53845234f9fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637081853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1637081853
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2217287455
Short name T563
Test name
Test status
Simulation time 157996997 ps
CPU time 1.13 seconds
Started Jun 23 05:05:48 PM PDT 24
Finished Jun 23 05:05:50 PM PDT 24
Peak memory 200640 kb
Host smart-08326904-e9e0-4c5f-87a2-bffe782650b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217287455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2217287455
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.177537866
Short name T586
Test name
Test status
Simulation time 179958084 ps
CPU time 2.59 seconds
Started Jun 23 05:05:47 PM PDT 24
Finished Jun 23 05:05:50 PM PDT 24
Peak memory 209060 kb
Host smart-58c9f004-1e25-4795-88f0-2b45d80da85a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177537866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.177537866
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1284569797
Short name T114
Test name
Test status
Simulation time 803334918 ps
CPU time 2.81 seconds
Started Jun 23 05:05:51 PM PDT 24
Finished Jun 23 05:05:54 PM PDT 24
Peak memory 200800 kb
Host smart-29f077ea-2363-4e73-b8db-c0723f343ad8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284569797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1284569797
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.689544045
Short name T569
Test name
Test status
Simulation time 405490489 ps
CPU time 2.5 seconds
Started Jun 23 05:05:49 PM PDT 24
Finished Jun 23 05:05:52 PM PDT 24
Peak memory 200896 kb
Host smart-b12f7746-1433-4bbc-8b23-db69f3254faa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689544045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.689544045
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.814511830
Short name T587
Test name
Test status
Simulation time 269579124 ps
CPU time 3.28 seconds
Started Jun 23 05:05:53 PM PDT 24
Finished Jun 23 05:05:57 PM PDT 24
Peak memory 200828 kb
Host smart-8ecff8ae-cb44-4558-b05a-a45da6822f14
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814511830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.814511830
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3997379026
Short name T555
Test name
Test status
Simulation time 96732461 ps
CPU time 0.84 seconds
Started Jun 23 05:05:51 PM PDT 24
Finished Jun 23 05:05:52 PM PDT 24
Peak memory 200684 kb
Host smart-cb4147b2-07c1-4e6c-85c3-1f51e9a53fc7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997379026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
997379026
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2236850073
Short name T70
Test name
Test status
Simulation time 115487080 ps
CPU time 1.16 seconds
Started Jun 23 05:05:53 PM PDT 24
Finished Jun 23 05:05:55 PM PDT 24
Peak memory 208852 kb
Host smart-fbd96f72-d306-485d-9ae4-4fae98c83eda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236850073 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2236850073
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3364042416
Short name T110
Test name
Test status
Simulation time 79780832 ps
CPU time 0.89 seconds
Started Jun 23 05:05:53 PM PDT 24
Finished Jun 23 05:05:55 PM PDT 24
Peak memory 200736 kb
Host smart-4a8e9656-6f04-4014-8ef4-e1a039254517
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364042416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3364042416
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3002454553
Short name T595
Test name
Test status
Simulation time 111955645 ps
CPU time 0.98 seconds
Started Jun 23 05:05:48 PM PDT 24
Finished Jun 23 05:05:49 PM PDT 24
Peak memory 200688 kb
Host smart-c3664c69-80b2-450d-9df7-de0050b0f6e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002454553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3002454553
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3063115361
Short name T616
Test name
Test status
Simulation time 381326547 ps
CPU time 2.58 seconds
Started Jun 23 05:05:50 PM PDT 24
Finished Jun 23 05:05:53 PM PDT 24
Peak memory 212288 kb
Host smart-1869a555-5ede-4da9-a172-f36c901f3131
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063115361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3063115361
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3177377427
Short name T580
Test name
Test status
Simulation time 447872204 ps
CPU time 2.04 seconds
Started Jun 23 05:05:52 PM PDT 24
Finished Jun 23 05:05:54 PM PDT 24
Peak memory 200900 kb
Host smart-5c05a56b-4698-46dc-ac54-e19a1d6b5b38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177377427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3177377427
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1040034737
Short name T599
Test name
Test status
Simulation time 346120107 ps
CPU time 2.47 seconds
Started Jun 23 05:05:49 PM PDT 24
Finished Jun 23 05:05:52 PM PDT 24
Peak memory 200960 kb
Host smart-58cf2892-850a-4b80-9187-aa50a24afb6c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040034737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
040034737
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.38769251
Short name T539
Test name
Test status
Simulation time 271666166 ps
CPU time 3.18 seconds
Started Jun 23 05:05:50 PM PDT 24
Finished Jun 23 05:05:54 PM PDT 24
Peak memory 200792 kb
Host smart-7862641d-58ae-4b35-9bd2-6ef36d67811a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38769251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.38769251
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1977738935
Short name T597
Test name
Test status
Simulation time 86368237 ps
CPU time 0.8 seconds
Started Jun 23 05:05:49 PM PDT 24
Finished Jun 23 05:05:50 PM PDT 24
Peak memory 200740 kb
Host smart-246c6a1a-3171-4ec2-8e75-2bdbea257bcb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977738935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
977738935
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3461256150
Short name T543
Test name
Test status
Simulation time 142034099 ps
CPU time 1.19 seconds
Started Jun 23 05:05:51 PM PDT 24
Finished Jun 23 05:05:53 PM PDT 24
Peak memory 200680 kb
Host smart-481c6da1-cf15-47ad-a61a-48c3e5762a90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461256150 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.3461256150
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1671658867
Short name T596
Test name
Test status
Simulation time 83576360 ps
CPU time 0.88 seconds
Started Jun 23 05:05:53 PM PDT 24
Finished Jun 23 05:05:54 PM PDT 24
Peak memory 200696 kb
Host smart-8cb242fe-3f63-4673-ba71-d7635b740747
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671658867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1671658867
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4156048909
Short name T605
Test name
Test status
Simulation time 166863585 ps
CPU time 1.24 seconds
Started Jun 23 05:05:54 PM PDT 24
Finished Jun 23 05:05:56 PM PDT 24
Peak memory 200568 kb
Host smart-2669404c-2d55-4a8d-8dac-c4977dec9670
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156048909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.4156048909
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2374372637
Short name T590
Test name
Test status
Simulation time 233824467 ps
CPU time 3.44 seconds
Started Jun 23 05:05:51 PM PDT 24
Finished Jun 23 05:05:55 PM PDT 24
Peak memory 209116 kb
Host smart-e21d4766-5d5e-4105-84ea-c6618470e3f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374372637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2374372637
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1799159572
Short name T71
Test name
Test status
Simulation time 487374867 ps
CPU time 2.04 seconds
Started Jun 23 05:05:49 PM PDT 24
Finished Jun 23 05:05:52 PM PDT 24
Peak memory 200852 kb
Host smart-da8402cb-1816-46c0-b435-371fa8ca3e0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799159572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1799159572
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2436713360
Short name T570
Test name
Test status
Simulation time 123900469 ps
CPU time 0.97 seconds
Started Jun 23 05:05:53 PM PDT 24
Finished Jun 23 05:05:54 PM PDT 24
Peak memory 200616 kb
Host smart-8ad26fc3-fed3-4094-ba4a-f491b1687615
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436713360 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2436713360
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.67543104
Short name T593
Test name
Test status
Simulation time 73400055 ps
CPU time 0.81 seconds
Started Jun 23 05:05:59 PM PDT 24
Finished Jun 23 05:06:00 PM PDT 24
Peak memory 200624 kb
Host smart-400090a2-038c-4f7f-9454-407285306710
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67543104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.67543104
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3253915211
Short name T562
Test name
Test status
Simulation time 143328446 ps
CPU time 1.1 seconds
Started Jun 23 05:05:54 PM PDT 24
Finished Jun 23 05:05:56 PM PDT 24
Peak memory 200684 kb
Host smart-44a104ef-8058-4bc1-91fa-d21540fbad44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253915211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3253915211
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.530302873
Short name T552
Test name
Test status
Simulation time 520792986 ps
CPU time 3.06 seconds
Started Jun 23 05:05:49 PM PDT 24
Finished Jun 23 05:05:52 PM PDT 24
Peak memory 212708 kb
Host smart-65213ced-07fc-4c54-8746-f7ae49217ce3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530302873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.530302873
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3658719497
Short name T585
Test name
Test status
Simulation time 881041860 ps
CPU time 2.91 seconds
Started Jun 23 05:05:55 PM PDT 24
Finished Jun 23 05:05:59 PM PDT 24
Peak memory 200792 kb
Host smart-3e84901d-55e3-4984-ac52-49496b019f0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658719497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.3658719497
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1149871099
Short name T92
Test name
Test status
Simulation time 135447580 ps
CPU time 1.06 seconds
Started Jun 23 05:05:58 PM PDT 24
Finished Jun 23 05:06:00 PM PDT 24
Peak memory 209400 kb
Host smart-ce86dadf-dff0-4cf7-83d6-dfa77e96348c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149871099 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1149871099
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1568626548
Short name T550
Test name
Test status
Simulation time 74163471 ps
CPU time 0.78 seconds
Started Jun 23 05:05:57 PM PDT 24
Finished Jun 23 05:05:58 PM PDT 24
Peak memory 200688 kb
Host smart-eda80f01-cf7e-4b94-9bdc-ea14eebd0a03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568626548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1568626548
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.687006573
Short name T105
Test name
Test status
Simulation time 224620422 ps
CPU time 1.64 seconds
Started Jun 23 05:05:59 PM PDT 24
Finished Jun 23 05:06:01 PM PDT 24
Peak memory 200940 kb
Host smart-175ff2b7-a2c8-48ac-b64a-60e728d7b010
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687006573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.687006573
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1321250419
Short name T121
Test name
Test status
Simulation time 158071427 ps
CPU time 2.23 seconds
Started Jun 23 05:05:57 PM PDT 24
Finished Jun 23 05:06:00 PM PDT 24
Peak memory 209080 kb
Host smart-9a1f2459-8b54-48cb-b40a-0ee899703baa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321250419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1321250419
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.4053450905
Short name T120
Test name
Test status
Simulation time 915792041 ps
CPU time 2.97 seconds
Started Jun 23 05:05:54 PM PDT 24
Finished Jun 23 05:05:58 PM PDT 24
Peak memory 200784 kb
Host smart-e588e98e-ecca-44ec-bb03-c2ebd8070501
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053450905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.4053450905
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1079060722
Short name T95
Test name
Test status
Simulation time 123025946 ps
CPU time 1.44 seconds
Started Jun 23 05:05:55 PM PDT 24
Finished Jun 23 05:05:57 PM PDT 24
Peak memory 209184 kb
Host smart-bafa5b8d-81f7-4517-b9c8-59573539aa3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079060722 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1079060722
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2166800049
Short name T566
Test name
Test status
Simulation time 63988745 ps
CPU time 0.9 seconds
Started Jun 23 05:05:57 PM PDT 24
Finished Jun 23 05:05:59 PM PDT 24
Peak memory 200640 kb
Host smart-ac583c1f-77bd-4b3d-b537-81d42280d775
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166800049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2166800049
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2346334129
Short name T540
Test name
Test status
Simulation time 143662091 ps
CPU time 1.31 seconds
Started Jun 23 05:05:56 PM PDT 24
Finished Jun 23 05:05:58 PM PDT 24
Peak memory 200776 kb
Host smart-2e3c2188-1153-443e-b4a2-1ad06eac3798
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346334129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.2346334129
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2065175964
Short name T607
Test name
Test status
Simulation time 373411039 ps
CPU time 2.81 seconds
Started Jun 23 05:05:59 PM PDT 24
Finished Jun 23 05:06:02 PM PDT 24
Peak memory 209112 kb
Host smart-c35bb0ff-2844-4a60-ac06-31853122bd48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065175964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2065175964
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1631289684
Short name T618
Test name
Test status
Simulation time 941407140 ps
CPU time 3.25 seconds
Started Jun 23 05:05:57 PM PDT 24
Finished Jun 23 05:06:01 PM PDT 24
Peak memory 200760 kb
Host smart-f4cff2ae-1f62-4f03-8731-a4f92bb49293
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631289684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.1631289684
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2645673791
Short name T97
Test name
Test status
Simulation time 145066161 ps
CPU time 1.11 seconds
Started Jun 23 05:05:54 PM PDT 24
Finished Jun 23 05:05:55 PM PDT 24
Peak memory 200760 kb
Host smart-8f3a68ff-b215-4378-a714-0bf3f31c7ec3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645673791 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2645673791
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3270244394
Short name T602
Test name
Test status
Simulation time 79238087 ps
CPU time 0.78 seconds
Started Jun 23 05:05:57 PM PDT 24
Finished Jun 23 05:05:59 PM PDT 24
Peak memory 200548 kb
Host smart-e7298f57-ecc2-4cc3-a1cb-2afc1a6ef345
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270244394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3270244394
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2458853784
Short name T581
Test name
Test status
Simulation time 74788033 ps
CPU time 0.95 seconds
Started Jun 23 05:05:53 PM PDT 24
Finished Jun 23 05:05:54 PM PDT 24
Peak memory 200660 kb
Host smart-61892c09-5fea-44f1-a04e-624e8a13d639
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458853784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.2458853784
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2788667335
Short name T610
Test name
Test status
Simulation time 127993807 ps
CPU time 1.95 seconds
Started Jun 23 05:05:58 PM PDT 24
Finished Jun 23 05:06:01 PM PDT 24
Peak memory 212448 kb
Host smart-ab616743-f932-43e5-9deb-46b4928d839a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788667335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2788667335
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3734932282
Short name T122
Test name
Test status
Simulation time 946046472 ps
CPU time 3 seconds
Started Jun 23 05:05:58 PM PDT 24
Finished Jun 23 05:06:02 PM PDT 24
Peak memory 200800 kb
Host smart-523dfd3b-5290-4638-811e-982ab0b38171
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734932282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3734932282
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.441978092
Short name T564
Test name
Test status
Simulation time 188694669 ps
CPU time 1.86 seconds
Started Jun 23 05:05:55 PM PDT 24
Finished Jun 23 05:05:57 PM PDT 24
Peak memory 209124 kb
Host smart-0025e33e-eca4-456f-abd0-77c07de2db42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441978092 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.441978092
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1859901890
Short name T573
Test name
Test status
Simulation time 68151131 ps
CPU time 0.79 seconds
Started Jun 23 05:05:56 PM PDT 24
Finished Jun 23 05:05:57 PM PDT 24
Peak memory 200580 kb
Host smart-f706ccae-cc20-4916-9354-d0991ecf2aba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859901890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1859901890
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2506085530
Short name T603
Test name
Test status
Simulation time 233499184 ps
CPU time 1.56 seconds
Started Jun 23 05:05:57 PM PDT 24
Finished Jun 23 05:06:00 PM PDT 24
Peak memory 200848 kb
Host smart-11b1a004-3cab-42d5-ae98-77c404bd7152
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506085530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.2506085530
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.771257260
Short name T620
Test name
Test status
Simulation time 778445220 ps
CPU time 2.81 seconds
Started Jun 23 05:05:56 PM PDT 24
Finished Jun 23 05:05:59 PM PDT 24
Peak memory 200828 kb
Host smart-f941aca2-d38d-45b0-9625-ebda079183bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771257260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
771257260
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2621719860
Short name T503
Test name
Test status
Simulation time 1895177612 ps
CPU time 6.74 seconds
Started Jun 23 05:07:17 PM PDT 24
Finished Jun 23 05:07:25 PM PDT 24
Peak memory 222060 kb
Host smart-cd3dc978-8719-4f0f-9616-a0e6311944b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621719860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2621719860
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.2690666167
Short name T523
Test name
Test status
Simulation time 220988467 ps
CPU time 0.92 seconds
Started Jun 23 05:07:19 PM PDT 24
Finished Jun 23 05:07:20 PM PDT 24
Peak memory 200560 kb
Host smart-4ebaefdf-b082-4608-b887-ba876fd5fbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690666167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2690666167
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1077185222
Short name T10
Test name
Test status
Simulation time 930245576 ps
CPU time 4.63 seconds
Started Jun 23 05:07:19 PM PDT 24
Finished Jun 23 05:07:24 PM PDT 24
Peak memory 200972 kb
Host smart-15d933b1-6811-4704-bb0d-f91e6637fa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077185222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1077185222
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.3101201394
Short name T67
Test name
Test status
Simulation time 17027172960 ps
CPU time 24.21 seconds
Started Jun 23 05:07:26 PM PDT 24
Finished Jun 23 05:07:51 PM PDT 24
Peak memory 217472 kb
Host smart-e1c3bf2b-487c-4944-8b91-41df57a6f8bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101201394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3101201394
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3508824600
Short name T400
Test name
Test status
Simulation time 176373262 ps
CPU time 1.18 seconds
Started Jun 23 05:07:22 PM PDT 24
Finished Jun 23 05:07:24 PM PDT 24
Peak memory 200748 kb
Host smart-fa2b698a-a532-4a8d-a87a-391bc3b092f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508824600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3508824600
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.3307176554
Short name T314
Test name
Test status
Simulation time 112279588 ps
CPU time 1.16 seconds
Started Jun 23 05:07:18 PM PDT 24
Finished Jun 23 05:07:19 PM PDT 24
Peak memory 200976 kb
Host smart-d3c8bf8e-0b60-43d8-9bb0-c9f655f5521b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307176554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3307176554
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.2630035808
Short name T255
Test name
Test status
Simulation time 95273994 ps
CPU time 0.87 seconds
Started Jun 23 05:07:17 PM PDT 24
Finished Jun 23 05:07:18 PM PDT 24
Peak memory 200488 kb
Host smart-57bf6bf0-c641-49f3-b870-3236a90ddfa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630035808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2630035808
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2978874359
Short name T183
Test name
Test status
Simulation time 308330381 ps
CPU time 2.2 seconds
Started Jun 23 05:07:19 PM PDT 24
Finished Jun 23 05:07:22 PM PDT 24
Peak memory 200672 kb
Host smart-70eb6908-dbc3-4e84-9ea9-014722addf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978874359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2978874359
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.269601405
Short name T185
Test name
Test status
Simulation time 223912431 ps
CPU time 1.41 seconds
Started Jun 23 05:07:20 PM PDT 24
Finished Jun 23 05:07:22 PM PDT 24
Peak memory 200664 kb
Host smart-bddda753-9b8a-48b2-be60-a5ce5e0269c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269601405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.269601405
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.928644411
Short name T168
Test name
Test status
Simulation time 60331092 ps
CPU time 0.77 seconds
Started Jun 23 05:07:23 PM PDT 24
Finished Jun 23 05:07:24 PM PDT 24
Peak memory 200472 kb
Host smart-87f013fb-d6e6-4691-9850-4fea6d40e277
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928644411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.928644411
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1828715262
Short name T49
Test name
Test status
Simulation time 2354002373 ps
CPU time 8.62 seconds
Started Jun 23 05:07:27 PM PDT 24
Finished Jun 23 05:07:37 PM PDT 24
Peak memory 222504 kb
Host smart-3d84dc41-b817-4459-b258-6e307448b42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828715262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1828715262
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3440205249
Short name T492
Test name
Test status
Simulation time 244367151 ps
CPU time 1.09 seconds
Started Jun 23 05:07:25 PM PDT 24
Finished Jun 23 05:07:26 PM PDT 24
Peak memory 218100 kb
Host smart-7ef905d9-38c3-4f70-82f1-9c4c2fcf324c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440205249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3440205249
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.1516966472
Short name T502
Test name
Test status
Simulation time 151454178 ps
CPU time 0.82 seconds
Started Jun 23 05:07:26 PM PDT 24
Finished Jun 23 05:07:27 PM PDT 24
Peak memory 200488 kb
Host smart-571d0347-cb4e-403e-a7f4-256c82c1997c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516966472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.1516966472
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.47775707
Short name T336
Test name
Test status
Simulation time 1486826841 ps
CPU time 5.68 seconds
Started Jun 23 05:07:27 PM PDT 24
Finished Jun 23 05:07:33 PM PDT 24
Peak memory 200976 kb
Host smart-db644b78-2639-49bf-b572-c392a2239b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47775707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.47775707
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2188591016
Short name T291
Test name
Test status
Simulation time 104949283 ps
CPU time 1.16 seconds
Started Jun 23 05:07:26 PM PDT 24
Finished Jun 23 05:07:28 PM PDT 24
Peak memory 200748 kb
Host smart-19730443-7a4d-4b73-a4ae-99c775956570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188591016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2188591016
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.3618481632
Short name T325
Test name
Test status
Simulation time 196417105 ps
CPU time 1.39 seconds
Started Jun 23 05:07:26 PM PDT 24
Finished Jun 23 05:07:28 PM PDT 24
Peak memory 200888 kb
Host smart-ca76d533-9630-491e-b0bc-af933021ade7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618481632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3618481632
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3627365454
Short name T489
Test name
Test status
Simulation time 4843283652 ps
CPU time 19.17 seconds
Started Jun 23 05:07:24 PM PDT 24
Finished Jun 23 05:07:43 PM PDT 24
Peak memory 209056 kb
Host smart-c3e4e196-2fba-4aca-8c3b-bef1b7615e15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627365454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3627365454
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3320367692
Short name T208
Test name
Test status
Simulation time 143409149 ps
CPU time 1.9 seconds
Started Jun 23 05:07:27 PM PDT 24
Finished Jun 23 05:07:30 PM PDT 24
Peak memory 200740 kb
Host smart-0bcf1f09-76f2-4a4a-89de-e70b9263f8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320367692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3320367692
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1879191360
Short name T228
Test name
Test status
Simulation time 149697552 ps
CPU time 1.2 seconds
Started Jun 23 05:07:22 PM PDT 24
Finished Jun 23 05:07:24 PM PDT 24
Peak memory 200748 kb
Host smart-756ce684-f726-40ec-a1d0-06e7b0006f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879191360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1879191360
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.89646299
Short name T367
Test name
Test status
Simulation time 66162261 ps
CPU time 0.73 seconds
Started Jun 23 05:08:04 PM PDT 24
Finished Jun 23 05:08:06 PM PDT 24
Peak memory 200544 kb
Host smart-d4f4ed67-72d7-4f2f-80ca-692cb66ae12f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89646299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.89646299
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3160756975
Short name T322
Test name
Test status
Simulation time 245356716 ps
CPU time 1.06 seconds
Started Jun 23 05:08:05 PM PDT 24
Finished Jun 23 05:08:07 PM PDT 24
Peak memory 218128 kb
Host smart-9ee439fc-be96-4f04-ba48-79ad9b6edfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160756975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3160756975
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.4178390150
Short name T405
Test name
Test status
Simulation time 163525219 ps
CPU time 0.89 seconds
Started Jun 23 05:07:57 PM PDT 24
Finished Jun 23 05:07:59 PM PDT 24
Peak memory 200532 kb
Host smart-92097850-332f-428d-9a71-3966d8410912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178390150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.4178390150
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.1286769775
Short name T342
Test name
Test status
Simulation time 822708055 ps
CPU time 4.2 seconds
Started Jun 23 05:07:58 PM PDT 24
Finished Jun 23 05:08:03 PM PDT 24
Peak memory 200976 kb
Host smart-eaf65b14-a17e-499b-8fd6-cc55d575875a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286769775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.1286769775
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.4232566780
Short name T317
Test name
Test status
Simulation time 113161693 ps
CPU time 1.01 seconds
Started Jun 23 05:07:58 PM PDT 24
Finished Jun 23 05:08:00 PM PDT 24
Peak memory 200676 kb
Host smart-b5637ebc-ceaf-4da5-b049-340cfaec1f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232566780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.4232566780
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.943144041
Short name T517
Test name
Test status
Simulation time 124534116 ps
CPU time 1.19 seconds
Started Jun 23 05:07:56 PM PDT 24
Finished Jun 23 05:07:58 PM PDT 24
Peak memory 200980 kb
Host smart-8abbb685-4510-4d51-9aeb-b753b99b11e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943144041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.943144041
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3149816333
Short name T297
Test name
Test status
Simulation time 148698222 ps
CPU time 1.94 seconds
Started Jun 23 05:07:59 PM PDT 24
Finished Jun 23 05:08:02 PM PDT 24
Peak memory 200744 kb
Host smart-66ffa8a9-c5b1-40ff-8c11-6401cd6a7342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149816333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3149816333
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2240258511
Short name T462
Test name
Test status
Simulation time 139494557 ps
CPU time 1.03 seconds
Started Jun 23 05:07:57 PM PDT 24
Finished Jun 23 05:08:00 PM PDT 24
Peak memory 200684 kb
Host smart-bade4826-dc9e-445c-a51c-6e5bd00dd606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240258511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2240258511
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.3363792261
Short name T138
Test name
Test status
Simulation time 87950338 ps
CPU time 1.09 seconds
Started Jun 23 05:08:03 PM PDT 24
Finished Jun 23 05:08:06 PM PDT 24
Peak memory 200556 kb
Host smart-c88b9666-caed-4446-8df6-a439ed16690a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363792261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3363792261
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.11041296
Short name T52
Test name
Test status
Simulation time 1218371842 ps
CPU time 5.4 seconds
Started Jun 23 05:08:06 PM PDT 24
Finished Jun 23 05:08:12 PM PDT 24
Peak memory 218472 kb
Host smart-b28462c6-2a6c-4d42-a986-43893570af11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11041296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.11041296
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2383151000
Short name T360
Test name
Test status
Simulation time 244397761 ps
CPU time 1.02 seconds
Started Jun 23 05:08:05 PM PDT 24
Finished Jun 23 05:08:07 PM PDT 24
Peak memory 218068 kb
Host smart-8098ae51-8267-4770-b850-c66b5c0cc685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383151000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.2383151000
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1215576280
Short name T480
Test name
Test status
Simulation time 159994447 ps
CPU time 0.91 seconds
Started Jun 23 05:08:04 PM PDT 24
Finished Jun 23 05:08:06 PM PDT 24
Peak memory 200488 kb
Host smart-99f27fd0-5126-45a7-b4dd-07a54f564e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215576280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1215576280
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.3062375842
Short name T103
Test name
Test status
Simulation time 1509369522 ps
CPU time 5.41 seconds
Started Jun 23 05:08:03 PM PDT 24
Finished Jun 23 05:08:09 PM PDT 24
Peak memory 200888 kb
Host smart-c400d211-bf08-4198-98d5-714c7037ace2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062375842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3062375842
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1856876696
Short name T158
Test name
Test status
Simulation time 206288953 ps
CPU time 1.46 seconds
Started Jun 23 05:08:06 PM PDT 24
Finished Jun 23 05:08:08 PM PDT 24
Peak memory 200960 kb
Host smart-5c705066-2ca8-469f-8c27-12be5f1ea058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856876696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1856876696
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3200403018
Short name T345
Test name
Test status
Simulation time 2493296200 ps
CPU time 13.05 seconds
Started Jun 23 05:08:03 PM PDT 24
Finished Jun 23 05:08:18 PM PDT 24
Peak memory 200952 kb
Host smart-3f7833cc-4edf-4adc-b5f9-af637a392f9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200403018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3200403018
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1242027383
Short name T140
Test name
Test status
Simulation time 120166170 ps
CPU time 1.62 seconds
Started Jun 23 05:08:05 PM PDT 24
Finished Jun 23 05:08:07 PM PDT 24
Peak memory 208916 kb
Host smart-b69e00ed-5e07-4e61-9733-7cb14d99932a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242027383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1242027383
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2207367548
Short name T89
Test name
Test status
Simulation time 221737997 ps
CPU time 1.36 seconds
Started Jun 23 05:08:07 PM PDT 24
Finished Jun 23 05:08:09 PM PDT 24
Peak memory 200756 kb
Host smart-cec83abd-e9b9-492a-bda2-28673877d2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207367548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2207367548
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.439203504
Short name T442
Test name
Test status
Simulation time 89285977 ps
CPU time 0.88 seconds
Started Jun 23 05:08:11 PM PDT 24
Finished Jun 23 05:08:13 PM PDT 24
Peak memory 200516 kb
Host smart-af09c98a-871c-4d4d-bd0c-af2e30133871
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439203504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.439203504
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.1994121248
Short name T473
Test name
Test status
Simulation time 1222668127 ps
CPU time 5.7 seconds
Started Jun 23 05:08:04 PM PDT 24
Finished Jun 23 05:08:10 PM PDT 24
Peak memory 218556 kb
Host smart-dcc15042-52c8-4732-8eb9-44546c1632f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994121248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1994121248
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3073706841
Short name T538
Test name
Test status
Simulation time 244499955 ps
CPU time 1.1 seconds
Started Jun 23 05:08:06 PM PDT 24
Finished Jun 23 05:08:08 PM PDT 24
Peak memory 218140 kb
Host smart-d5c23498-196a-4424-8f14-e7b5d65e02e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073706841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3073706841
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3611069870
Short name T481
Test name
Test status
Simulation time 142247799 ps
CPU time 0.88 seconds
Started Jun 23 05:08:05 PM PDT 24
Finished Jun 23 05:08:07 PM PDT 24
Peak memory 200564 kb
Host smart-ea5713a2-9f1a-405f-bc98-192e7448536e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611069870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3611069870
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.145815212
Short name T161
Test name
Test status
Simulation time 936749031 ps
CPU time 4.76 seconds
Started Jun 23 05:08:04 PM PDT 24
Finished Jun 23 05:08:10 PM PDT 24
Peak memory 200820 kb
Host smart-07115c14-8213-4a13-aed7-c64bb7c564ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145815212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.145815212
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.974634864
Short name T155
Test name
Test status
Simulation time 109827055 ps
CPU time 1.01 seconds
Started Jun 23 05:08:06 PM PDT 24
Finished Jun 23 05:08:08 PM PDT 24
Peak memory 200664 kb
Host smart-5bca90d8-4407-48d5-82d4-6597d51c3cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974634864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.974634864
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.856819354
Short name T471
Test name
Test status
Simulation time 119699043 ps
CPU time 1.17 seconds
Started Jun 23 05:08:04 PM PDT 24
Finished Jun 23 05:08:06 PM PDT 24
Peak memory 200868 kb
Host smart-f420b94d-bcaf-41db-9f17-5936c5525d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856819354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.856819354
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.1670870074
Short name T124
Test name
Test status
Simulation time 12557431587 ps
CPU time 48.85 seconds
Started Jun 23 05:08:12 PM PDT 24
Finished Jun 23 05:09:03 PM PDT 24
Peak memory 200880 kb
Host smart-ed66928a-5481-4f9d-a652-d60bdb2bb2d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670870074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1670870074
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1044693607
Short name T468
Test name
Test status
Simulation time 405572149 ps
CPU time 2.34 seconds
Started Jun 23 05:08:06 PM PDT 24
Finished Jun 23 05:08:10 PM PDT 24
Peak memory 200740 kb
Host smart-f3784381-8e66-490c-989b-b617ae0be877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044693607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1044693607
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.4246751047
Short name T271
Test name
Test status
Simulation time 129237430 ps
CPU time 1.18 seconds
Started Jun 23 05:08:02 PM PDT 24
Finished Jun 23 05:08:05 PM PDT 24
Peak memory 200704 kb
Host smart-7615dcd7-1209-4bd0-b002-de5481d000d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246751047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.4246751047
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.218775956
Short name T425
Test name
Test status
Simulation time 79571876 ps
CPU time 0.87 seconds
Started Jun 23 05:08:11 PM PDT 24
Finished Jun 23 05:08:12 PM PDT 24
Peak memory 200496 kb
Host smart-f1253957-4de8-4076-9ae4-b657ec2d0785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218775956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.218775956
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3191300566
Short name T525
Test name
Test status
Simulation time 1900577781 ps
CPU time 7.53 seconds
Started Jun 23 05:08:13 PM PDT 24
Finished Jun 23 05:08:22 PM PDT 24
Peak memory 218480 kb
Host smart-0cc683e3-761b-4a76-b29b-31072eabc3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191300566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3191300566
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.216607509
Short name T225
Test name
Test status
Simulation time 244192721 ps
CPU time 1.14 seconds
Started Jun 23 05:08:12 PM PDT 24
Finished Jun 23 05:08:15 PM PDT 24
Peak memory 218128 kb
Host smart-e5a538ca-e113-4c0d-9583-efc6283f56f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216607509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.216607509
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3251345710
Short name T395
Test name
Test status
Simulation time 112030734 ps
CPU time 0.85 seconds
Started Jun 23 05:08:11 PM PDT 24
Finished Jun 23 05:08:13 PM PDT 24
Peak memory 200564 kb
Host smart-033801a8-f0a8-46ab-b815-92c8e78b2ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251345710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3251345710
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.1580134470
Short name T363
Test name
Test status
Simulation time 871452614 ps
CPU time 4.24 seconds
Started Jun 23 05:08:10 PM PDT 24
Finished Jun 23 05:08:15 PM PDT 24
Peak memory 200884 kb
Host smart-3ba129fd-eae4-4f1c-bf41-2cc36667bb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580134470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1580134470
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3904983275
Short name T380
Test name
Test status
Simulation time 113244658 ps
CPU time 1.02 seconds
Started Jun 23 05:08:14 PM PDT 24
Finished Jun 23 05:08:16 PM PDT 24
Peak memory 200704 kb
Host smart-81eefc02-c538-484d-822e-3f8a75ebd2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904983275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3904983275
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2085140745
Short name T457
Test name
Test status
Simulation time 197486286 ps
CPU time 1.39 seconds
Started Jun 23 05:08:12 PM PDT 24
Finished Jun 23 05:08:15 PM PDT 24
Peak memory 200964 kb
Host smart-29497a90-990e-458f-877e-12ad9eb58bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085140745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2085140745
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1163314099
Short name T394
Test name
Test status
Simulation time 8187761008 ps
CPU time 30.33 seconds
Started Jun 23 05:08:13 PM PDT 24
Finished Jun 23 05:08:45 PM PDT 24
Peak memory 209112 kb
Host smart-fc2d1a05-59b1-47c2-9932-13ce66a1c579
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163314099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1163314099
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2538787788
Short name T177
Test name
Test status
Simulation time 260651525 ps
CPU time 1.73 seconds
Started Jun 23 05:08:13 PM PDT 24
Finished Jun 23 05:08:16 PM PDT 24
Peak memory 200744 kb
Host smart-f750c988-3063-490a-997a-a01d60b3695f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538787788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2538787788
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.4243060385
Short name T200
Test name
Test status
Simulation time 162652873 ps
CPU time 1.29 seconds
Started Jun 23 05:08:11 PM PDT 24
Finished Jun 23 05:08:13 PM PDT 24
Peak memory 200932 kb
Host smart-e4492467-774c-4e51-9860-deb36c1c7137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243060385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.4243060385
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3214041959
Short name T349
Test name
Test status
Simulation time 70072488 ps
CPU time 0.8 seconds
Started Jun 23 05:08:20 PM PDT 24
Finished Jun 23 05:08:22 PM PDT 24
Peak memory 200568 kb
Host smart-2528ebc9-8d9c-4f8f-8a4e-e1a4e87c69bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214041959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3214041959
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.4036973641
Short name T45
Test name
Test status
Simulation time 2160631622 ps
CPU time 8.01 seconds
Started Jun 23 05:08:13 PM PDT 24
Finished Jun 23 05:08:23 PM PDT 24
Peak memory 222440 kb
Host smart-ff071cd9-4dc1-46c7-bcb8-ae264034136b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036973641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.4036973641
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.4088888559
Short name T283
Test name
Test status
Simulation time 243996264 ps
CPU time 1.05 seconds
Started Jun 23 05:08:14 PM PDT 24
Finished Jun 23 05:08:16 PM PDT 24
Peak memory 218076 kb
Host smart-dea08c73-9b7a-41b8-ab26-ff7572eb825e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088888559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.4088888559
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.662459165
Short name T423
Test name
Test status
Simulation time 107946110 ps
CPU time 0.75 seconds
Started Jun 23 05:08:12 PM PDT 24
Finished Jun 23 05:08:15 PM PDT 24
Peak memory 200536 kb
Host smart-e3a41e73-27e6-4a2b-b770-7a5761bcdcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662459165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.662459165
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.1097842940
Short name T176
Test name
Test status
Simulation time 1143756623 ps
CPU time 5.78 seconds
Started Jun 23 05:08:12 PM PDT 24
Finished Jun 23 05:08:20 PM PDT 24
Peak memory 200944 kb
Host smart-6d8de901-1bf7-4ebb-a504-8d8323a1ef15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097842940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1097842940
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.455314788
Short name T339
Test name
Test status
Simulation time 165903702 ps
CPU time 1.13 seconds
Started Jun 23 05:08:11 PM PDT 24
Finished Jun 23 05:08:13 PM PDT 24
Peak memory 200744 kb
Host smart-d7fd829a-eae8-4d49-921b-0b3bbf49ee27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455314788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.455314788
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2534949013
Short name T260
Test name
Test status
Simulation time 199691987 ps
CPU time 1.36 seconds
Started Jun 23 05:08:15 PM PDT 24
Finished Jun 23 05:08:17 PM PDT 24
Peak memory 200908 kb
Host smart-3753c0e9-18a5-456d-a34b-59a3091ca056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534949013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2534949013
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2819767173
Short name T179
Test name
Test status
Simulation time 4635902688 ps
CPU time 17.74 seconds
Started Jun 23 05:08:19 PM PDT 24
Finished Jun 23 05:08:38 PM PDT 24
Peak memory 200880 kb
Host smart-c94a0725-9ed2-4b19-94a8-4545ad71b57b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819767173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2819767173
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1831828963
Short name T306
Test name
Test status
Simulation time 147740676 ps
CPU time 1.81 seconds
Started Jun 23 05:08:11 PM PDT 24
Finished Jun 23 05:08:14 PM PDT 24
Peak memory 200752 kb
Host smart-cc14fbc3-618b-4de5-930c-25388cd84f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831828963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1831828963
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.4155969915
Short name T143
Test name
Test status
Simulation time 116532560 ps
CPU time 0.93 seconds
Started Jun 23 05:08:14 PM PDT 24
Finished Jun 23 05:08:16 PM PDT 24
Peak memory 200756 kb
Host smart-8250609e-cda9-4e50-9131-1ab39bf49d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155969915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.4155969915
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.1046067491
Short name T153
Test name
Test status
Simulation time 61493098 ps
CPU time 0.76 seconds
Started Jun 23 05:08:23 PM PDT 24
Finished Jun 23 05:08:25 PM PDT 24
Peak memory 200464 kb
Host smart-de9dda9b-1b79-462e-bc10-6d5fcc31c6a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046067491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.1046067491
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2541228464
Short name T482
Test name
Test status
Simulation time 1222240110 ps
CPU time 5.61 seconds
Started Jun 23 05:08:16 PM PDT 24
Finished Jun 23 05:08:22 PM PDT 24
Peak memory 222080 kb
Host smart-8b4e7af6-84e7-467f-b3b3-1a8f88beb644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541228464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2541228464
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3644989536
Short name T287
Test name
Test status
Simulation time 244359001 ps
CPU time 1.14 seconds
Started Jun 23 05:08:17 PM PDT 24
Finished Jun 23 05:08:19 PM PDT 24
Peak memory 218120 kb
Host smart-d08075ee-f1d3-4efb-8cfe-88278783d5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644989536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3644989536
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3362451221
Short name T359
Test name
Test status
Simulation time 132121790 ps
CPU time 0.83 seconds
Started Jun 23 05:08:18 PM PDT 24
Finished Jun 23 05:08:19 PM PDT 24
Peak memory 200488 kb
Host smart-1f36df1f-51e1-4cb3-9dc3-565ac5daf862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362451221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3362451221
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3813383685
Short name T199
Test name
Test status
Simulation time 1456083558 ps
CPU time 5.7 seconds
Started Jun 23 05:08:18 PM PDT 24
Finished Jun 23 05:08:25 PM PDT 24
Peak memory 200952 kb
Host smart-68fa503d-9a12-42ae-80f2-7ec310bae6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813383685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3813383685
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.36654803
Short name T238
Test name
Test status
Simulation time 101327214 ps
CPU time 1.01 seconds
Started Jun 23 05:08:18 PM PDT 24
Finished Jun 23 05:08:20 PM PDT 24
Peak memory 200708 kb
Host smart-ea101800-557e-4e58-b5c1-2214fcc3c09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36654803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.36654803
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.928778236
Short name T206
Test name
Test status
Simulation time 205080924 ps
CPU time 1.49 seconds
Started Jun 23 05:08:17 PM PDT 24
Finished Jun 23 05:08:19 PM PDT 24
Peak memory 200944 kb
Host smart-f43a1979-000d-4260-8591-7d44a1cda78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928778236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.928778236
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2416114310
Short name T189
Test name
Test status
Simulation time 878576226 ps
CPU time 4.24 seconds
Started Jun 23 05:08:20 PM PDT 24
Finished Jun 23 05:08:25 PM PDT 24
Peak memory 200876 kb
Host smart-b08bc55f-660f-4bc8-a935-c7e1d18443cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416114310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2416114310
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2921748805
Short name T528
Test name
Test status
Simulation time 290077564 ps
CPU time 1.84 seconds
Started Jun 23 05:08:20 PM PDT 24
Finished Jun 23 05:08:22 PM PDT 24
Peak memory 200664 kb
Host smart-848f3b60-5cee-46bd-8a29-82c649a5c8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921748805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2921748805
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3231779165
Short name T419
Test name
Test status
Simulation time 123564645 ps
CPU time 1.16 seconds
Started Jun 23 05:08:17 PM PDT 24
Finished Jun 23 05:08:19 PM PDT 24
Peak memory 200700 kb
Host smart-dec74ec0-c19e-4db8-9c3e-b70488dd4478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231779165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3231779165
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1850055011
Short name T426
Test name
Test status
Simulation time 72536965 ps
CPU time 0.87 seconds
Started Jun 23 05:08:18 PM PDT 24
Finished Jun 23 05:08:19 PM PDT 24
Peak memory 200556 kb
Host smart-fc94aecf-486d-44d7-8609-f9028ebf94f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850055011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1850055011
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1274121962
Short name T428
Test name
Test status
Simulation time 1229577804 ps
CPU time 5.59 seconds
Started Jun 23 05:08:20 PM PDT 24
Finished Jun 23 05:08:27 PM PDT 24
Peak memory 218468 kb
Host smart-ea1e538b-215a-469a-bdc0-b8047606a59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274121962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1274121962
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.1269821035
Short name T338
Test name
Test status
Simulation time 243609636 ps
CPU time 1.1 seconds
Started Jun 23 05:08:18 PM PDT 24
Finished Jun 23 05:08:20 PM PDT 24
Peak memory 218052 kb
Host smart-67ca89b0-d78d-45bb-9610-90fd320b70db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269821035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.1269821035
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3538444995
Short name T169
Test name
Test status
Simulation time 148357412 ps
CPU time 0.84 seconds
Started Jun 23 05:08:18 PM PDT 24
Finished Jun 23 05:08:19 PM PDT 24
Peak memory 200564 kb
Host smart-7c6bc930-2a5f-41c5-ba0b-573ddd5c0965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538444995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3538444995
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.1788709081
Short name T412
Test name
Test status
Simulation time 2013959232 ps
CPU time 7.18 seconds
Started Jun 23 05:08:19 PM PDT 24
Finished Jun 23 05:08:27 PM PDT 24
Peak memory 200960 kb
Host smart-1ee712ec-597c-4404-9c8f-c80696f0f969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788709081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1788709081
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1860054429
Short name T250
Test name
Test status
Simulation time 143778245 ps
CPU time 1.17 seconds
Started Jun 23 05:08:20 PM PDT 24
Finished Jun 23 05:08:22 PM PDT 24
Peak memory 200684 kb
Host smart-44eb942d-638f-4840-9120-6a50569383d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860054429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1860054429
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2882989607
Short name T515
Test name
Test status
Simulation time 128106484 ps
CPU time 1.22 seconds
Started Jun 23 05:08:16 PM PDT 24
Finished Jun 23 05:08:18 PM PDT 24
Peak memory 200976 kb
Host smart-68152b07-9ed0-4f97-9562-70e2da88dce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882989607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2882989607
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1655128322
Short name T149
Test name
Test status
Simulation time 5367689595 ps
CPU time 25.21 seconds
Started Jun 23 05:08:22 PM PDT 24
Finished Jun 23 05:08:48 PM PDT 24
Peak memory 201032 kb
Host smart-294d60bd-7837-4d9a-bbaf-097586457d0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655128322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1655128322
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3168587839
Short name T194
Test name
Test status
Simulation time 388287509 ps
CPU time 2.07 seconds
Started Jun 23 05:08:18 PM PDT 24
Finished Jun 23 05:08:21 PM PDT 24
Peak memory 200692 kb
Host smart-77728215-1a4e-45c6-95f3-6b0f3255531a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168587839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3168587839
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1971034375
Short name T253
Test name
Test status
Simulation time 76740953 ps
CPU time 0.86 seconds
Started Jun 23 05:08:17 PM PDT 24
Finished Jun 23 05:08:19 PM PDT 24
Peak memory 200748 kb
Host smart-bef40cc8-3bbd-4833-b404-986da39ba233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971034375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1971034375
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.437976510
Short name T244
Test name
Test status
Simulation time 63577424 ps
CPU time 0.77 seconds
Started Jun 23 05:08:28 PM PDT 24
Finished Jun 23 05:08:30 PM PDT 24
Peak memory 200496 kb
Host smart-eb298f01-3d4f-480f-afc6-e795703c6f51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437976510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.437976510
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.808560502
Short name T54
Test name
Test status
Simulation time 1224282378 ps
CPU time 5.74 seconds
Started Jun 23 05:08:28 PM PDT 24
Finished Jun 23 05:08:35 PM PDT 24
Peak memory 222076 kb
Host smart-e38b8d94-16e0-4f52-b6f9-d0802bd1cbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808560502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.808560502
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1532215529
Short name T173
Test name
Test status
Simulation time 244614750 ps
CPU time 1.22 seconds
Started Jun 23 05:08:20 PM PDT 24
Finished Jun 23 05:08:22 PM PDT 24
Peak memory 218140 kb
Host smart-bd4318c0-48c9-4f16-8e55-9315a0865904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532215529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1532215529
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3657414041
Short name T461
Test name
Test status
Simulation time 159773026 ps
CPU time 0.81 seconds
Started Jun 23 05:08:23 PM PDT 24
Finished Jun 23 05:08:24 PM PDT 24
Peak memory 200508 kb
Host smart-6f1d6668-e605-4c8f-82ae-4d359cd350e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657414041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3657414041
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1983596959
Short name T217
Test name
Test status
Simulation time 1022089251 ps
CPU time 4.62 seconds
Started Jun 23 05:08:28 PM PDT 24
Finished Jun 23 05:08:33 PM PDT 24
Peak memory 200932 kb
Host smart-9e705127-6764-45cd-88d6-c3aae92ff772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983596959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1983596959
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.4239293085
Short name T529
Test name
Test status
Simulation time 110699719 ps
CPU time 1.03 seconds
Started Jun 23 05:08:24 PM PDT 24
Finished Jun 23 05:08:26 PM PDT 24
Peak memory 200784 kb
Host smart-aaff8437-8b62-4fab-93f6-b8f9907d059e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239293085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.4239293085
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.624455284
Short name T532
Test name
Test status
Simulation time 203366835 ps
CPU time 1.33 seconds
Started Jun 23 05:08:15 PM PDT 24
Finished Jun 23 05:08:17 PM PDT 24
Peak memory 200956 kb
Host smart-7c2d58d8-f910-42f0-be1c-908f854e0911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624455284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.624455284
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3894863236
Short name T401
Test name
Test status
Simulation time 5580785388 ps
CPU time 24.23 seconds
Started Jun 23 05:08:24 PM PDT 24
Finished Jun 23 05:08:49 PM PDT 24
Peak memory 209216 kb
Host smart-7d017600-8625-4c70-9611-82def53954be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894863236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3894863236
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2018460543
Short name T430
Test name
Test status
Simulation time 255695570 ps
CPU time 1.88 seconds
Started Jun 23 05:08:24 PM PDT 24
Finished Jun 23 05:08:27 PM PDT 24
Peak memory 200672 kb
Host smart-9deeb4ae-1707-42f3-ad6a-3466beb6859c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018460543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2018460543
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.1531501658
Short name T479
Test name
Test status
Simulation time 84064357 ps
CPU time 0.88 seconds
Started Jun 23 05:08:25 PM PDT 24
Finished Jun 23 05:08:27 PM PDT 24
Peak memory 200764 kb
Host smart-675a906f-237f-41e4-bc8a-d2f7c2b0231d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531501658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1531501658
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1331870228
Short name T319
Test name
Test status
Simulation time 71957429 ps
CPU time 0.78 seconds
Started Jun 23 05:08:31 PM PDT 24
Finished Jun 23 05:08:32 PM PDT 24
Peak memory 200500 kb
Host smart-7f38f480-c63e-42ed-a569-1f523e390a05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331870228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1331870228
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3945543346
Short name T404
Test name
Test status
Simulation time 1218870020 ps
CPU time 6.08 seconds
Started Jun 23 05:08:22 PM PDT 24
Finished Jun 23 05:08:29 PM PDT 24
Peak memory 218056 kb
Host smart-ec55ab7b-66da-45f5-a67c-28d260242f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945543346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3945543346
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.841302445
Short name T133
Test name
Test status
Simulation time 244165592 ps
CPU time 1.08 seconds
Started Jun 23 05:08:22 PM PDT 24
Finished Jun 23 05:08:24 PM PDT 24
Peak memory 218104 kb
Host smart-ce57ab90-a4ac-43da-8323-63656cd4c144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841302445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.841302445
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1552212443
Short name T456
Test name
Test status
Simulation time 184282235 ps
CPU time 0.92 seconds
Started Jun 23 05:08:21 PM PDT 24
Finished Jun 23 05:08:23 PM PDT 24
Peak memory 200732 kb
Host smart-74680e0d-bf17-4d88-af46-6f0a063db666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552212443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1552212443
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.786102665
Short name T513
Test name
Test status
Simulation time 1842081354 ps
CPU time 6.89 seconds
Started Jun 23 05:08:25 PM PDT 24
Finished Jun 23 05:08:32 PM PDT 24
Peak memory 200948 kb
Host smart-03bcfd47-2d8f-4f8b-a2a1-fd77deddebd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786102665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.786102665
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3846981695
Short name T285
Test name
Test status
Simulation time 167652270 ps
CPU time 1.17 seconds
Started Jun 23 05:08:24 PM PDT 24
Finished Jun 23 05:08:26 PM PDT 24
Peak memory 200676 kb
Host smart-52bc20d8-ad7f-4b7b-804f-e9f6ce2ba8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846981695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3846981695
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.635868189
Short name T369
Test name
Test status
Simulation time 196814764 ps
CPU time 1.41 seconds
Started Jun 23 05:08:21 PM PDT 24
Finished Jun 23 05:08:23 PM PDT 24
Peak memory 200812 kb
Host smart-d41c61d6-4b49-42b6-93f4-8f5929906707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635868189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.635868189
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.1204085262
Short name T212
Test name
Test status
Simulation time 3484299939 ps
CPU time 16.33 seconds
Started Jun 23 05:08:22 PM PDT 24
Finished Jun 23 05:08:40 PM PDT 24
Peak memory 200972 kb
Host smart-0005f434-4188-494b-ab9b-639f71ae44c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204085262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1204085262
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1188011463
Short name T474
Test name
Test status
Simulation time 135440253 ps
CPU time 1.62 seconds
Started Jun 23 05:08:24 PM PDT 24
Finished Jun 23 05:08:26 PM PDT 24
Peak memory 200772 kb
Host smart-aae5006f-1294-43b4-b4ab-670e3ec91f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188011463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1188011463
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1612514147
Short name T178
Test name
Test status
Simulation time 187957746 ps
CPU time 1.23 seconds
Started Jun 23 05:08:28 PM PDT 24
Finished Jun 23 05:08:30 PM PDT 24
Peak memory 200708 kb
Host smart-734624f4-2e56-4564-a7b9-9783be531762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612514147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1612514147
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.3853255217
Short name T130
Test name
Test status
Simulation time 82067011 ps
CPU time 0.81 seconds
Started Jun 23 05:08:27 PM PDT 24
Finished Jun 23 05:08:29 PM PDT 24
Peak memory 200496 kb
Host smart-b6741764-6d86-440a-8efd-10e4b0c5ce0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853255217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3853255217
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.51736003
Short name T519
Test name
Test status
Simulation time 2362926428 ps
CPU time 8.08 seconds
Started Jun 23 05:08:29 PM PDT 24
Finished Jun 23 05:08:38 PM PDT 24
Peak memory 230780 kb
Host smart-38ce10de-86d1-42ba-bcf4-616747f00649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51736003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.51736003
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1213812761
Short name T84
Test name
Test status
Simulation time 244821999 ps
CPU time 1.12 seconds
Started Jun 23 05:08:27 PM PDT 24
Finished Jun 23 05:08:29 PM PDT 24
Peak memory 218040 kb
Host smart-aa19e8cd-82e4-4c80-a7a6-3b60b2114dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213812761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1213812761
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3769375470
Short name T248
Test name
Test status
Simulation time 80195086 ps
CPU time 0.75 seconds
Started Jun 23 05:08:30 PM PDT 24
Finished Jun 23 05:08:31 PM PDT 24
Peak memory 200488 kb
Host smart-13c69d90-f743-423a-8909-10b097d11b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769375470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3769375470
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.811415568
Short name T62
Test name
Test status
Simulation time 736545308 ps
CPU time 3.81 seconds
Started Jun 23 05:08:32 PM PDT 24
Finished Jun 23 05:08:37 PM PDT 24
Peak memory 200908 kb
Host smart-d81e9d6f-7cc3-4bf1-9f11-d72a480e9851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811415568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.811415568
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3167564071
Short name T251
Test name
Test status
Simulation time 106608230 ps
CPU time 1.01 seconds
Started Jun 23 05:08:28 PM PDT 24
Finished Jun 23 05:08:30 PM PDT 24
Peak memory 200728 kb
Host smart-cd7c476c-ba44-476a-9a31-8e38f0e21e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167564071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3167564071
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3498755477
Short name T324
Test name
Test status
Simulation time 108912028 ps
CPU time 1.17 seconds
Started Jun 23 05:08:29 PM PDT 24
Finished Jun 23 05:08:31 PM PDT 24
Peak memory 200872 kb
Host smart-e95ec423-757d-4ee7-82c5-a75e5c33fe81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498755477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3498755477
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1736084089
Short name T312
Test name
Test status
Simulation time 398485319 ps
CPU time 1.69 seconds
Started Jun 23 05:08:28 PM PDT 24
Finished Jun 23 05:08:31 PM PDT 24
Peak memory 200916 kb
Host smart-40333715-7ea0-4134-b4dd-d5ac503ace8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736084089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1736084089
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.571696215
Short name T330
Test name
Test status
Simulation time 258115013 ps
CPU time 1.78 seconds
Started Jun 23 05:08:28 PM PDT 24
Finished Jun 23 05:08:30 PM PDT 24
Peak memory 200752 kb
Host smart-35796e84-6fb2-420a-a3c4-028b852ae84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571696215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.571696215
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2699390304
Short name T175
Test name
Test status
Simulation time 106571245 ps
CPU time 1.02 seconds
Started Jun 23 05:08:27 PM PDT 24
Finished Jun 23 05:08:29 PM PDT 24
Peak memory 200760 kb
Host smart-4d2085a3-dd3c-4cae-9560-28530e92ae14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699390304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2699390304
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.184583867
Short name T273
Test name
Test status
Simulation time 72738357 ps
CPU time 0.81 seconds
Started Jun 23 05:07:36 PM PDT 24
Finished Jun 23 05:07:37 PM PDT 24
Peak memory 200520 kb
Host smart-3fe08742-c3de-428b-a352-fd8f29040b17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184583867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.184583867
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.1642803150
Short name T35
Test name
Test status
Simulation time 2371928139 ps
CPU time 8.61 seconds
Started Jun 23 05:07:25 PM PDT 24
Finished Jun 23 05:07:35 PM PDT 24
Peak memory 218296 kb
Host smart-eea10257-db85-4797-a1b7-6a02d0182bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642803150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.1642803150
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3019765017
Short name T323
Test name
Test status
Simulation time 244492158 ps
CPU time 1.11 seconds
Started Jun 23 05:07:38 PM PDT 24
Finished Jun 23 05:07:40 PM PDT 24
Peak memory 218036 kb
Host smart-f280887f-6b34-4e1a-b178-a9ff05650d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019765017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3019765017
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1929094800
Short name T280
Test name
Test status
Simulation time 167997156 ps
CPU time 0.88 seconds
Started Jun 23 05:07:26 PM PDT 24
Finished Jun 23 05:07:28 PM PDT 24
Peak memory 200452 kb
Host smart-2b41105c-e4b0-41d6-9bc7-5010ad10e289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929094800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1929094800
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2645940529
Short name T410
Test name
Test status
Simulation time 734901687 ps
CPU time 3.93 seconds
Started Jun 23 05:07:27 PM PDT 24
Finished Jun 23 05:07:32 PM PDT 24
Peak memory 200976 kb
Host smart-1b0bb269-be16-4d35-8b53-c7ec7531fd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645940529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2645940529
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.3733316307
Short name T76
Test name
Test status
Simulation time 16532906777 ps
CPU time 24.77 seconds
Started Jun 23 05:07:36 PM PDT 24
Finished Jun 23 05:08:02 PM PDT 24
Peak memory 217692 kb
Host smart-751c4f15-c45e-4136-a585-3a757a8fcb84
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733316307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3733316307
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2664064547
Short name T268
Test name
Test status
Simulation time 141999294 ps
CPU time 1.08 seconds
Started Jun 23 05:07:26 PM PDT 24
Finished Jun 23 05:07:28 PM PDT 24
Peak memory 200676 kb
Host smart-39e9ab05-af61-4ef9-9a46-422abda84900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664064547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2664064547
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1989648521
Short name T294
Test name
Test status
Simulation time 255249171 ps
CPU time 1.56 seconds
Started Jun 23 05:07:26 PM PDT 24
Finished Jun 23 05:07:28 PM PDT 24
Peak memory 200888 kb
Host smart-219e7ee8-77cd-4ea6-b461-a91ecf47d99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989648521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1989648521
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2806230771
Short name T234
Test name
Test status
Simulation time 7447961730 ps
CPU time 26.33 seconds
Started Jun 23 05:07:37 PM PDT 24
Finished Jun 23 05:08:04 PM PDT 24
Peak memory 200944 kb
Host smart-552f9fde-577b-4d75-a6a0-ffc52228b4fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806230771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2806230771
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2827079117
Short name T87
Test name
Test status
Simulation time 326871871 ps
CPU time 2.4 seconds
Started Jun 23 05:07:24 PM PDT 24
Finished Jun 23 05:07:27 PM PDT 24
Peak memory 200780 kb
Host smart-3c438059-3535-47d6-b6ca-eaa24cfafa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827079117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2827079117
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3109005192
Short name T467
Test name
Test status
Simulation time 65942496 ps
CPU time 0.78 seconds
Started Jun 23 05:07:26 PM PDT 24
Finished Jun 23 05:07:28 PM PDT 24
Peak memory 200752 kb
Host smart-be7e00fb-ec25-406d-93d3-ed3b7e0559e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109005192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3109005192
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3440541851
Short name T3
Test name
Test status
Simulation time 61324115 ps
CPU time 0.79 seconds
Started Jun 23 05:08:36 PM PDT 24
Finished Jun 23 05:08:37 PM PDT 24
Peak memory 200556 kb
Host smart-52831199-8ebe-43b5-8056-6c89de809f1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440541851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3440541851
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2476311722
Short name T398
Test name
Test status
Simulation time 244024837 ps
CPU time 1.12 seconds
Started Jun 23 05:08:34 PM PDT 24
Finished Jun 23 05:08:35 PM PDT 24
Peak memory 218148 kb
Host smart-f1bc0027-f615-4d1b-b21c-1626491d07c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476311722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2476311722
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_reset.206117485
Short name T144
Test name
Test status
Simulation time 789364135 ps
CPU time 4.38 seconds
Started Jun 23 05:08:28 PM PDT 24
Finished Jun 23 05:08:34 PM PDT 24
Peak memory 200868 kb
Host smart-726b94ae-d043-42d1-b94d-7cda938e417a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206117485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.206117485
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.4293265833
Short name T174
Test name
Test status
Simulation time 108280555 ps
CPU time 1.06 seconds
Started Jun 23 05:08:29 PM PDT 24
Finished Jun 23 05:08:31 PM PDT 24
Peak memory 200664 kb
Host smart-2e205260-753b-4147-b5d2-d33c14c9353c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293265833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.4293265833
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2893020643
Short name T86
Test name
Test status
Simulation time 245945268 ps
CPU time 1.58 seconds
Started Jun 23 05:08:30 PM PDT 24
Finished Jun 23 05:08:32 PM PDT 24
Peak memory 200952 kb
Host smart-054b635c-ce12-4e68-b91a-144b9f03d5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893020643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2893020643
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.416142510
Short name T242
Test name
Test status
Simulation time 13409644699 ps
CPU time 54.9 seconds
Started Jun 23 05:08:32 PM PDT 24
Finished Jun 23 05:09:28 PM PDT 24
Peak memory 209184 kb
Host smart-1fb04fe6-9a93-4667-9028-07b0f7af9d01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416142510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.416142510
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.4169023985
Short name T79
Test name
Test status
Simulation time 389738514 ps
CPU time 2.42 seconds
Started Jun 23 05:08:28 PM PDT 24
Finished Jun 23 05:08:32 PM PDT 24
Peak memory 208900 kb
Host smart-27ac8cc7-89d7-4720-8fde-aa4acf9cb053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169023985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.4169023985
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2482509851
Short name T445
Test name
Test status
Simulation time 83914433 ps
CPU time 0.86 seconds
Started Jun 23 05:08:26 PM PDT 24
Finished Jun 23 05:08:27 PM PDT 24
Peak memory 200676 kb
Host smart-c41ff429-0c5f-4e69-984f-e1768da0fbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482509851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2482509851
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.419863135
Short name T320
Test name
Test status
Simulation time 80112192 ps
CPU time 0.82 seconds
Started Jun 23 05:08:35 PM PDT 24
Finished Jun 23 05:08:36 PM PDT 24
Peak memory 200552 kb
Host smart-8eebb789-9c7a-4780-9878-ea90fd746116
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419863135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.419863135
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1150611723
Short name T57
Test name
Test status
Simulation time 2359013334 ps
CPU time 8.37 seconds
Started Jun 23 05:08:34 PM PDT 24
Finished Jun 23 05:08:43 PM PDT 24
Peak memory 222496 kb
Host smart-7c8c9b75-ea13-4fbd-8812-89fbaff033c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150611723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1150611723
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3664262519
Short name T210
Test name
Test status
Simulation time 244533644 ps
CPU time 1.09 seconds
Started Jun 23 05:08:35 PM PDT 24
Finished Jun 23 05:08:36 PM PDT 24
Peak memory 218064 kb
Host smart-6644aef2-ef74-4dd1-a6f8-840384d80a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664262519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3664262519
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1871449095
Short name T507
Test name
Test status
Simulation time 145541892 ps
CPU time 0.83 seconds
Started Jun 23 05:08:38 PM PDT 24
Finished Jun 23 05:08:39 PM PDT 24
Peak memory 200516 kb
Host smart-af92c49e-fca5-4b86-9ffd-c2b7c3168f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871449095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1871449095
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3709749695
Short name T371
Test name
Test status
Simulation time 1481993769 ps
CPU time 5.67 seconds
Started Jun 23 05:08:33 PM PDT 24
Finished Jun 23 05:08:40 PM PDT 24
Peak memory 201092 kb
Host smart-fc39d856-60b9-406d-a52e-13eb47ab4b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709749695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3709749695
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3491914427
Short name T392
Test name
Test status
Simulation time 178909781 ps
CPU time 1.28 seconds
Started Jun 23 05:08:36 PM PDT 24
Finished Jun 23 05:08:38 PM PDT 24
Peak memory 200732 kb
Host smart-4d3701a6-bb59-4942-9d3d-bb35d0a05c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491914427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3491914427
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.104225922
Short name T205
Test name
Test status
Simulation time 114324813 ps
CPU time 1.22 seconds
Started Jun 23 05:08:40 PM PDT 24
Finished Jun 23 05:08:43 PM PDT 24
Peak memory 200948 kb
Host smart-80ffc6e2-b4e4-4835-b8b4-bea4f4287234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104225922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.104225922
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.4011395098
Short name T421
Test name
Test status
Simulation time 3760343891 ps
CPU time 16.39 seconds
Started Jun 23 05:08:34 PM PDT 24
Finished Jun 23 05:08:51 PM PDT 24
Peak memory 209132 kb
Host smart-db8912c7-80d6-4fba-9c8a-f58fa3994e37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011395098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.4011395098
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2414709656
Short name T534
Test name
Test status
Simulation time 282738427 ps
CPU time 2.09 seconds
Started Jun 23 05:08:34 PM PDT 24
Finished Jun 23 05:08:37 PM PDT 24
Peak memory 208944 kb
Host smart-1320978f-31b4-4b3b-927a-dcb3faafc5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414709656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2414709656
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1444295791
Short name T13
Test name
Test status
Simulation time 77329985 ps
CPU time 0.79 seconds
Started Jun 23 05:08:33 PM PDT 24
Finished Jun 23 05:08:34 PM PDT 24
Peak memory 200752 kb
Host smart-799e73fb-5066-47db-ae68-227ce1ae26cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444295791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1444295791
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2485963094
Short name T411
Test name
Test status
Simulation time 74372714 ps
CPU time 0.72 seconds
Started Jun 23 05:08:40 PM PDT 24
Finished Jun 23 05:08:42 PM PDT 24
Peak memory 200452 kb
Host smart-bfbc274f-3e9e-404c-af0e-3e8695e8b01b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485963094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2485963094
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1361655837
Short name T310
Test name
Test status
Simulation time 2377462591 ps
CPU time 8.79 seconds
Started Jun 23 05:08:38 PM PDT 24
Finished Jun 23 05:08:47 PM PDT 24
Peak memory 209976 kb
Host smart-d2d22ca3-06a0-4721-940e-c246fd95f032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361655837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1361655837
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.245743102
Short name T501
Test name
Test status
Simulation time 244496740 ps
CPU time 1.03 seconds
Started Jun 23 05:08:39 PM PDT 24
Finished Jun 23 05:08:41 PM PDT 24
Peak memory 218048 kb
Host smart-b2fde91d-1f05-4e02-8810-e503b8188ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245743102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.245743102
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.298610661
Short name T372
Test name
Test status
Simulation time 81618191 ps
CPU time 0.71 seconds
Started Jun 23 05:08:46 PM PDT 24
Finished Jun 23 05:08:48 PM PDT 24
Peak memory 200488 kb
Host smart-a549c8f1-5479-4469-9551-ddd77b5661b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298610661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.298610661
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.436449475
Short name T172
Test name
Test status
Simulation time 851421526 ps
CPU time 4.39 seconds
Started Jun 23 05:08:40 PM PDT 24
Finished Jun 23 05:08:46 PM PDT 24
Peak memory 200984 kb
Host smart-187677eb-9389-404c-98fa-5a0b4daaa31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436449475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.436449475
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1949756692
Short name T454
Test name
Test status
Simulation time 137488033 ps
CPU time 1.05 seconds
Started Jun 23 05:08:38 PM PDT 24
Finished Jun 23 05:08:39 PM PDT 24
Peak memory 200720 kb
Host smart-228238a9-785c-4033-a716-baf6dbe93c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949756692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1949756692
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2573080522
Short name T150
Test name
Test status
Simulation time 256743203 ps
CPU time 1.45 seconds
Started Jun 23 05:08:33 PM PDT 24
Finished Jun 23 05:08:35 PM PDT 24
Peak memory 200936 kb
Host smart-3380e577-5f5b-4259-8583-a06b109a0631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573080522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2573080522
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.4128025628
Short name T88
Test name
Test status
Simulation time 11283004541 ps
CPU time 37.67 seconds
Started Jun 23 05:08:38 PM PDT 24
Finished Jun 23 05:09:16 PM PDT 24
Peak memory 201028 kb
Host smart-1a68ffa8-7e5c-436b-a193-57d66615b2eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128025628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.4128025628
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1991619411
Short name T245
Test name
Test status
Simulation time 203750292 ps
CPU time 1.36 seconds
Started Jun 23 05:08:40 PM PDT 24
Finished Jun 23 05:08:43 PM PDT 24
Peak memory 200736 kb
Host smart-73eedb7c-40ed-4823-9089-60235bfc2ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991619411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1991619411
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3701039648
Short name T464
Test name
Test status
Simulation time 91030614 ps
CPU time 0.77 seconds
Started Jun 23 05:08:41 PM PDT 24
Finished Jun 23 05:08:42 PM PDT 24
Peak memory 200452 kb
Host smart-b8915502-b676-4360-8ad7-6d655d36aa67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701039648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3701039648
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1160121360
Short name T315
Test name
Test status
Simulation time 1878709790 ps
CPU time 8.1 seconds
Started Jun 23 05:08:39 PM PDT 24
Finished Jun 23 05:08:48 PM PDT 24
Peak memory 222476 kb
Host smart-0db1a2d2-72ef-4207-a1ec-f2c5f1386da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160121360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1160121360
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.849678385
Short name T332
Test name
Test status
Simulation time 244989796 ps
CPU time 1.1 seconds
Started Jun 23 05:08:39 PM PDT 24
Finished Jun 23 05:08:41 PM PDT 24
Peak memory 218052 kb
Host smart-b663e144-eb3c-4511-b266-906ef212e33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849678385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.849678385
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1898844121
Short name T427
Test name
Test status
Simulation time 142577641 ps
CPU time 0.82 seconds
Started Jun 23 05:08:37 PM PDT 24
Finished Jun 23 05:08:38 PM PDT 24
Peak memory 200568 kb
Host smart-54d0abc6-32a8-49c1-bbfa-4135052241f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898844121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1898844121
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.261754120
Short name T190
Test name
Test status
Simulation time 792237399 ps
CPU time 4.25 seconds
Started Jun 23 05:08:40 PM PDT 24
Finished Jun 23 05:08:46 PM PDT 24
Peak memory 200876 kb
Host smart-8c05dd91-821c-440c-a96c-c8fd65306c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261754120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.261754120
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.674764961
Short name T459
Test name
Test status
Simulation time 152705750 ps
CPU time 1.1 seconds
Started Jun 23 05:08:46 PM PDT 24
Finished Jun 23 05:08:48 PM PDT 24
Peak memory 200724 kb
Host smart-fe358f34-93da-4410-a29a-cd0b99b7d5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674764961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.674764961
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1215268775
Short name T354
Test name
Test status
Simulation time 192072947 ps
CPU time 1.36 seconds
Started Jun 23 05:08:41 PM PDT 24
Finished Jun 23 05:08:43 PM PDT 24
Peak memory 200892 kb
Host smart-6d9fa0f3-a0ee-4156-8d5b-eb3d0ce4b8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215268775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1215268775
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3199938673
Short name T154
Test name
Test status
Simulation time 5211860151 ps
CPU time 24.33 seconds
Started Jun 23 05:08:41 PM PDT 24
Finished Jun 23 05:09:06 PM PDT 24
Peak memory 209176 kb
Host smart-e0f5d769-e11f-4e2e-91d0-8ddb997ad0a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199938673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3199938673
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.698516439
Short name T256
Test name
Test status
Simulation time 138029429 ps
CPU time 1.57 seconds
Started Jun 23 05:08:40 PM PDT 24
Finished Jun 23 05:08:43 PM PDT 24
Peak memory 208844 kb
Host smart-1fd08dba-fb22-4f5d-a158-4e060e12eecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698516439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.698516439
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.647189784
Short name T478
Test name
Test status
Simulation time 55537182 ps
CPU time 0.72 seconds
Started Jun 23 05:08:37 PM PDT 24
Finished Jun 23 05:08:38 PM PDT 24
Peak memory 200696 kb
Host smart-3a44ae77-fa7f-4464-91df-6c3a2d352d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647189784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.647189784
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3932510349
Short name T184
Test name
Test status
Simulation time 82912566 ps
CPU time 0.84 seconds
Started Jun 23 05:08:45 PM PDT 24
Finished Jun 23 05:08:46 PM PDT 24
Peak memory 200556 kb
Host smart-a4e28966-a909-41e2-8868-c4eeda7ee482
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932510349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3932510349
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1839879320
Short name T356
Test name
Test status
Simulation time 1897412444 ps
CPU time 7.25 seconds
Started Jun 23 05:08:46 PM PDT 24
Finished Jun 23 05:08:54 PM PDT 24
Peak memory 222384 kb
Host smart-ed887170-8d65-424f-b20f-42d51f595d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839879320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1839879320
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2845719423
Short name T504
Test name
Test status
Simulation time 244400712 ps
CPU time 1.12 seconds
Started Jun 23 05:08:48 PM PDT 24
Finished Jun 23 05:08:50 PM PDT 24
Peak memory 218116 kb
Host smart-7a5fb8bd-d863-4a36-a250-d52f432ab09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845719423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2845719423
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.607410128
Short name T346
Test name
Test status
Simulation time 233279866 ps
CPU time 0.96 seconds
Started Jun 23 05:08:43 PM PDT 24
Finished Jun 23 05:08:44 PM PDT 24
Peak memory 200484 kb
Host smart-8efbdb6a-f0ac-4ecd-9a8c-39673f6d91ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607410128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.607410128
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.1728939122
Short name T100
Test name
Test status
Simulation time 1206414729 ps
CPU time 5.26 seconds
Started Jun 23 05:08:44 PM PDT 24
Finished Jun 23 05:08:50 PM PDT 24
Peak memory 201012 kb
Host smart-7e8ab3b0-1018-47f3-88f3-4a5da8609c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728939122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1728939122
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.2104517735
Short name T353
Test name
Test status
Simulation time 151980870 ps
CPU time 1.12 seconds
Started Jun 23 05:08:43 PM PDT 24
Finished Jun 23 05:08:45 PM PDT 24
Peak memory 200748 kb
Host smart-904e70ad-b525-4707-81a9-1a740802a1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104517735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.2104517735
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1748304079
Short name T406
Test name
Test status
Simulation time 124774698 ps
CPU time 1.21 seconds
Started Jun 23 05:08:43 PM PDT 24
Finished Jun 23 05:08:45 PM PDT 24
Peak memory 200944 kb
Host smart-c6216374-1bc5-4d26-848b-f070a9281ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748304079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1748304079
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.1437397313
Short name T422
Test name
Test status
Simulation time 1959622040 ps
CPU time 8.41 seconds
Started Jun 23 05:08:44 PM PDT 24
Finished Jun 23 05:08:53 PM PDT 24
Peak memory 200968 kb
Host smart-780c3ae2-8f54-4abd-9cd2-229283e5a71d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437397313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1437397313
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1074966749
Short name T127
Test name
Test status
Simulation time 380200303 ps
CPU time 2.39 seconds
Started Jun 23 05:08:47 PM PDT 24
Finished Jun 23 05:08:50 PM PDT 24
Peak memory 200740 kb
Host smart-ae7b102d-f874-4937-8efc-74a9b5e94f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074966749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1074966749
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3036047336
Short name T463
Test name
Test status
Simulation time 110829889 ps
CPU time 0.93 seconds
Started Jun 23 05:08:44 PM PDT 24
Finished Jun 23 05:08:46 PM PDT 24
Peak memory 200760 kb
Host smart-096f9665-c445-4166-9dc0-5aa54a6224b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036047336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3036047336
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3095023151
Short name T536
Test name
Test status
Simulation time 66572416 ps
CPU time 0.73 seconds
Started Jun 23 05:08:51 PM PDT 24
Finished Jun 23 05:08:52 PM PDT 24
Peak memory 200520 kb
Host smart-c8e51f50-1a9f-405a-9bbf-ff420f41272f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095023151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3095023151
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2124023283
Short name T486
Test name
Test status
Simulation time 2356049905 ps
CPU time 9 seconds
Started Jun 23 05:08:48 PM PDT 24
Finished Jun 23 05:08:58 PM PDT 24
Peak memory 222544 kb
Host smart-20011f60-8cc4-4a26-9811-8ce4829630b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124023283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2124023283
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3414462155
Short name T505
Test name
Test status
Simulation time 244398476 ps
CPU time 1.11 seconds
Started Jun 23 05:08:49 PM PDT 24
Finished Jun 23 05:08:51 PM PDT 24
Peak memory 218124 kb
Host smart-04bbb2d3-88b7-465d-807d-efd3d2272fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414462155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3414462155
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1307788398
Short name T231
Test name
Test status
Simulation time 189576088 ps
CPU time 0.91 seconds
Started Jun 23 05:08:46 PM PDT 24
Finished Jun 23 05:08:47 PM PDT 24
Peak memory 200488 kb
Host smart-bd195308-1191-46aa-aa5c-968ed38636bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307788398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1307788398
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.3184903113
Short name T230
Test name
Test status
Simulation time 1918084895 ps
CPU time 6.81 seconds
Started Jun 23 05:08:46 PM PDT 24
Finished Jun 23 05:08:53 PM PDT 24
Peak memory 200976 kb
Host smart-ef95f9cb-d4c1-405f-a983-be3770ceafa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184903113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3184903113
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3641195200
Short name T453
Test name
Test status
Simulation time 177458226 ps
CPU time 1.19 seconds
Started Jun 23 05:08:46 PM PDT 24
Finished Jun 23 05:08:48 PM PDT 24
Peak memory 200684 kb
Host smart-e87637e5-104b-4c33-9ee6-1701a9ffd6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641195200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3641195200
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2032344342
Short name T146
Test name
Test status
Simulation time 255993046 ps
CPU time 1.5 seconds
Started Jun 23 05:08:43 PM PDT 24
Finished Jun 23 05:08:45 PM PDT 24
Peak memory 200916 kb
Host smart-2e153c0b-e932-49c7-a087-4459e62fe9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032344342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2032344342
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1029274739
Short name T261
Test name
Test status
Simulation time 3750861479 ps
CPU time 17.49 seconds
Started Jun 23 05:08:49 PM PDT 24
Finished Jun 23 05:09:07 PM PDT 24
Peak memory 201168 kb
Host smart-605000e7-ca43-4cf9-ae28-7cfe352b9c0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029274739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1029274739
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.977015345
Short name T237
Test name
Test status
Simulation time 107402185 ps
CPU time 1.47 seconds
Started Jun 23 05:08:43 PM PDT 24
Finished Jun 23 05:08:45 PM PDT 24
Peak memory 200744 kb
Host smart-1c393d6d-fb1f-4871-97ba-79d3849d3982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977015345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.977015345
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.429843663
Short name T152
Test name
Test status
Simulation time 111910174 ps
CPU time 1.04 seconds
Started Jun 23 05:08:43 PM PDT 24
Finished Jun 23 05:08:45 PM PDT 24
Peak memory 200700 kb
Host smart-9ceba7eb-ef57-4514-a714-4e22be74e215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429843663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.429843663
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.4066584570
Short name T384
Test name
Test status
Simulation time 93248282 ps
CPU time 0.85 seconds
Started Jun 23 05:08:51 PM PDT 24
Finished Jun 23 05:08:52 PM PDT 24
Peak memory 200472 kb
Host smart-23d5d50b-6698-4812-81c9-4fda90952a81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066584570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.4066584570
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1792319531
Short name T31
Test name
Test status
Simulation time 1217456467 ps
CPU time 6.12 seconds
Started Jun 23 05:08:52 PM PDT 24
Finished Jun 23 05:08:59 PM PDT 24
Peak memory 218556 kb
Host smart-fef3771d-f758-4a3d-9164-f04ea93ef7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792319531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1792319531
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.416960020
Short name T26
Test name
Test status
Simulation time 244523243 ps
CPU time 1.08 seconds
Started Jun 23 05:08:50 PM PDT 24
Finished Jun 23 05:08:51 PM PDT 24
Peak memory 218156 kb
Host smart-52877dda-ca54-4708-ac7d-1c17076bc0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416960020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.416960020
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2398696410
Short name T533
Test name
Test status
Simulation time 224902080 ps
CPU time 0.99 seconds
Started Jun 23 05:08:51 PM PDT 24
Finished Jun 23 05:08:53 PM PDT 24
Peak memory 200532 kb
Host smart-2a4c0a8f-4514-47c3-a112-206ec6b2ad22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398696410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2398696410
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.634039224
Short name T126
Test name
Test status
Simulation time 2115675589 ps
CPU time 9.06 seconds
Started Jun 23 05:08:48 PM PDT 24
Finished Jun 23 05:08:58 PM PDT 24
Peak memory 200868 kb
Host smart-33669ce7-0823-4dd4-8842-85534aacdf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634039224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.634039224
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3038311096
Short name T240
Test name
Test status
Simulation time 175982030 ps
CPU time 1.16 seconds
Started Jun 23 05:08:49 PM PDT 24
Finished Jun 23 05:08:51 PM PDT 24
Peak memory 200740 kb
Host smart-7cac6b8d-a933-4304-8d2e-5989bc1a93c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038311096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3038311096
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.341425382
Short name T399
Test name
Test status
Simulation time 193358510 ps
CPU time 1.42 seconds
Started Jun 23 05:08:48 PM PDT 24
Finished Jun 23 05:08:50 PM PDT 24
Peak memory 200936 kb
Host smart-bfbd9ca3-eff1-4ee0-ad49-d13c0608301c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341425382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.341425382
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.4266438629
Short name T458
Test name
Test status
Simulation time 1448495733 ps
CPU time 7.29 seconds
Started Jun 23 05:08:51 PM PDT 24
Finished Jun 23 05:08:59 PM PDT 24
Peak memory 209176 kb
Host smart-b2a619bd-e66b-4025-8606-90335b26fc14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266438629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.4266438629
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2412149514
Short name T506
Test name
Test status
Simulation time 434083168 ps
CPU time 2.43 seconds
Started Jun 23 05:08:50 PM PDT 24
Finished Jun 23 05:08:54 PM PDT 24
Peak memory 208840 kb
Host smart-aa2a1524-4016-44f2-9d38-189fe620d097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412149514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2412149514
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.99469249
Short name T278
Test name
Test status
Simulation time 157285827 ps
CPU time 1.31 seconds
Started Jun 23 05:08:50 PM PDT 24
Finished Jun 23 05:08:52 PM PDT 24
Peak memory 200804 kb
Host smart-24e89682-2d59-466f-bb97-da56a0c1a0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99469249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.99469249
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.4172525473
Short name T288
Test name
Test status
Simulation time 67231112 ps
CPU time 0.78 seconds
Started Jun 23 05:08:55 PM PDT 24
Finished Jun 23 05:08:56 PM PDT 24
Peak memory 200532 kb
Host smart-51ae0fc6-c4b7-4640-85e2-69be4bf7a7e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172525473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.4172525473
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.415795435
Short name T58
Test name
Test status
Simulation time 1876918474 ps
CPU time 7.86 seconds
Started Jun 23 05:08:57 PM PDT 24
Finished Jun 23 05:09:05 PM PDT 24
Peak memory 218548 kb
Host smart-f00a562a-6be1-484c-88b3-e6001352c2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415795435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.415795435
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2182460856
Short name T204
Test name
Test status
Simulation time 244160843 ps
CPU time 1.09 seconds
Started Jun 23 05:08:55 PM PDT 24
Finished Jun 23 05:08:57 PM PDT 24
Peak memory 218132 kb
Host smart-fbbdac01-08c0-4e4c-94e6-383cd449b898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182460856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2182460856
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2588601756
Short name T415
Test name
Test status
Simulation time 143243720 ps
CPU time 0.86 seconds
Started Jun 23 05:08:52 PM PDT 24
Finished Jun 23 05:08:53 PM PDT 24
Peak memory 200572 kb
Host smart-338c8982-e031-4516-b89f-3eccc9907d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588601756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2588601756
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.3569590871
Short name T219
Test name
Test status
Simulation time 667787678 ps
CPU time 3.46 seconds
Started Jun 23 05:08:54 PM PDT 24
Finished Jun 23 05:08:58 PM PDT 24
Peak memory 200940 kb
Host smart-fe4cf814-45b2-4527-a05e-7648ce0738fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569590871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.3569590871
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1034967222
Short name T321
Test name
Test status
Simulation time 147744413 ps
CPU time 1.16 seconds
Started Jun 23 05:08:58 PM PDT 24
Finished Jun 23 05:09:00 PM PDT 24
Peak memory 200740 kb
Host smart-1581bcb6-ce57-48e6-a96e-312e7bf5e5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034967222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1034967222
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.454074778
Short name T446
Test name
Test status
Simulation time 224457508 ps
CPU time 1.54 seconds
Started Jun 23 05:08:50 PM PDT 24
Finished Jun 23 05:08:53 PM PDT 24
Peak memory 200904 kb
Host smart-78745704-0da0-43d7-b807-d40a13203b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454074778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.454074778
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1861677662
Short name T379
Test name
Test status
Simulation time 4707560509 ps
CPU time 21.57 seconds
Started Jun 23 05:08:54 PM PDT 24
Finished Jun 23 05:09:16 PM PDT 24
Peak memory 209204 kb
Host smart-c277efd7-1da7-477c-ac86-4a66b98fc00b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861677662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1861677662
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2912003327
Short name T414
Test name
Test status
Simulation time 433034197 ps
CPU time 2.6 seconds
Started Jun 23 05:08:58 PM PDT 24
Finished Jun 23 05:09:01 PM PDT 24
Peak memory 208984 kb
Host smart-e66e4118-0891-415c-9ec0-60521a8a4c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912003327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2912003327
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1183627875
Short name T433
Test name
Test status
Simulation time 241156486 ps
CPU time 1.43 seconds
Started Jun 23 05:08:54 PM PDT 24
Finished Jun 23 05:08:56 PM PDT 24
Peak memory 200972 kb
Host smart-55d4d2b9-e20b-4c8d-bb20-94af89594888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183627875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1183627875
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1261716039
Short name T366
Test name
Test status
Simulation time 69237969 ps
CPU time 0.79 seconds
Started Jun 23 05:09:07 PM PDT 24
Finished Jun 23 05:09:09 PM PDT 24
Peak memory 200556 kb
Host smart-e47d2090-97b9-4f47-8841-eb888e5d4604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261716039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1261716039
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.557993049
Short name T30
Test name
Test status
Simulation time 1225497568 ps
CPU time 5.53 seconds
Started Jun 23 05:08:54 PM PDT 24
Finished Jun 23 05:09:00 PM PDT 24
Peak memory 218688 kb
Host smart-deb3fc90-f492-420e-99c6-08cd5ae96dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557993049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.557993049
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.4077673993
Short name T455
Test name
Test status
Simulation time 245909769 ps
CPU time 1.13 seconds
Started Jun 23 05:09:01 PM PDT 24
Finished Jun 23 05:09:03 PM PDT 24
Peak memory 218996 kb
Host smart-8bebb65b-32c1-4fb8-a987-05967990c68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077673993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.4077673993
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2017411948
Short name T449
Test name
Test status
Simulation time 99580224 ps
CPU time 0.75 seconds
Started Jun 23 05:08:55 PM PDT 24
Finished Jun 23 05:08:56 PM PDT 24
Peak memory 200572 kb
Host smart-b717138a-3a11-44c8-89cd-996b0903bda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017411948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2017411948
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3632553721
Short name T444
Test name
Test status
Simulation time 1171289550 ps
CPU time 5.1 seconds
Started Jun 23 05:08:54 PM PDT 24
Finished Jun 23 05:09:00 PM PDT 24
Peak memory 200808 kb
Host smart-852c6852-bd92-42c0-9d30-15231a6a88fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632553721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3632553721
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1557345219
Short name T378
Test name
Test status
Simulation time 143871350 ps
CPU time 1.04 seconds
Started Jun 23 05:08:58 PM PDT 24
Finished Jun 23 05:09:00 PM PDT 24
Peak memory 200740 kb
Host smart-9e84de3c-dde2-4b12-9817-3de18c6dc8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557345219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1557345219
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1122704336
Short name T218
Test name
Test status
Simulation time 119862858 ps
CPU time 1.16 seconds
Started Jun 23 05:08:59 PM PDT 24
Finished Jun 23 05:09:00 PM PDT 24
Peak memory 200944 kb
Host smart-bf58feee-0b39-4219-b956-0b445dde63d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122704336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1122704336
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1554101388
Short name T266
Test name
Test status
Simulation time 1426259390 ps
CPU time 7.01 seconds
Started Jun 23 05:09:01 PM PDT 24
Finished Jun 23 05:09:09 PM PDT 24
Peak memory 209088 kb
Host smart-8aa6ca09-b014-48fc-8d35-ad9654e0cb25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554101388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1554101388
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3000695431
Short name T272
Test name
Test status
Simulation time 509531843 ps
CPU time 2.69 seconds
Started Jun 23 05:08:55 PM PDT 24
Finished Jun 23 05:08:58 PM PDT 24
Peak memory 200748 kb
Host smart-2725e553-765b-4f0a-aa15-9e90423b383d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000695431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3000695431
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1178769941
Short name T451
Test name
Test status
Simulation time 74230351 ps
CPU time 0.83 seconds
Started Jun 23 05:08:57 PM PDT 24
Finished Jun 23 05:08:58 PM PDT 24
Peak memory 200728 kb
Host smart-0848cc8b-cb88-48e9-b5a4-126932acddf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178769941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1178769941
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.699437113
Short name T139
Test name
Test status
Simulation time 74729730 ps
CPU time 0.78 seconds
Started Jun 23 05:09:00 PM PDT 24
Finished Jun 23 05:09:01 PM PDT 24
Peak memory 200556 kb
Host smart-7346cd85-5c3b-49f8-bb0b-0352edca86b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699437113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.699437113
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.4219180184
Short name T156
Test name
Test status
Simulation time 244958808 ps
CPU time 1.11 seconds
Started Jun 23 05:08:59 PM PDT 24
Finished Jun 23 05:09:00 PM PDT 24
Peak memory 218128 kb
Host smart-f52dd1a3-b3da-4056-9ec3-c27a4261877d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219180184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.4219180184
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1267158606
Short name T19
Test name
Test status
Simulation time 76577838 ps
CPU time 0.76 seconds
Started Jun 23 05:09:06 PM PDT 24
Finished Jun 23 05:09:07 PM PDT 24
Peak memory 200572 kb
Host smart-74257a1e-0126-4ceb-8a81-772c10f0015d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267158606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1267158606
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.854886236
Short name T104
Test name
Test status
Simulation time 1080031521 ps
CPU time 4.5 seconds
Started Jun 23 05:09:00 PM PDT 24
Finished Jun 23 05:09:05 PM PDT 24
Peak memory 200948 kb
Host smart-abc825c0-98ff-4be0-891f-2173ef3cf1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854886236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.854886236
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.4135937440
Short name T41
Test name
Test status
Simulation time 187619459 ps
CPU time 1.2 seconds
Started Jun 23 05:09:01 PM PDT 24
Finished Jun 23 05:09:03 PM PDT 24
Peak memory 200660 kb
Host smart-ef6de5fc-c938-4053-8a31-edc369512366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135937440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.4135937440
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3104753238
Short name T142
Test name
Test status
Simulation time 192982928 ps
CPU time 1.52 seconds
Started Jun 23 05:09:06 PM PDT 24
Finished Jun 23 05:09:08 PM PDT 24
Peak memory 200964 kb
Host smart-a1b3cb94-dc4d-4483-b88b-fdc6b85d5f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104753238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3104753238
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.117945661
Short name T447
Test name
Test status
Simulation time 9780196163 ps
CPU time 42.13 seconds
Started Jun 23 05:09:00 PM PDT 24
Finished Jun 23 05:09:42 PM PDT 24
Peak memory 200852 kb
Host smart-efd02369-7446-40cb-bfca-74f84d37e8fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117945661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.117945661
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.655907191
Short name T269
Test name
Test status
Simulation time 288150764 ps
CPU time 1.95 seconds
Started Jun 23 05:09:02 PM PDT 24
Finished Jun 23 05:09:04 PM PDT 24
Peak memory 200676 kb
Host smart-3d77a9e7-64bc-4fa8-9997-e9e3039dc6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655907191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.655907191
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3363964148
Short name T254
Test name
Test status
Simulation time 162902849 ps
CPU time 1.11 seconds
Started Jun 23 05:09:05 PM PDT 24
Finished Jun 23 05:09:07 PM PDT 24
Peak memory 200724 kb
Host smart-3e6f7257-2bb6-4a79-8575-0bc5b6f933f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363964148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3363964148
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1417905571
Short name T211
Test name
Test status
Simulation time 65194998 ps
CPU time 0.77 seconds
Started Jun 23 05:07:36 PM PDT 24
Finished Jun 23 05:07:38 PM PDT 24
Peak memory 200560 kb
Host smart-bd6b106f-a817-4cd4-bbb8-53af3e4159b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417905571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1417905571
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3782855754
Short name T475
Test name
Test status
Simulation time 2188308034 ps
CPU time 8.3 seconds
Started Jun 23 05:07:36 PM PDT 24
Finished Jun 23 05:07:45 PM PDT 24
Peak memory 222504 kb
Host smart-7d187de9-ffaa-4385-8ad1-e51e32bca270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782855754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3782855754
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.520379918
Short name T340
Test name
Test status
Simulation time 243374786 ps
CPU time 1.14 seconds
Started Jun 23 05:07:33 PM PDT 24
Finished Jun 23 05:07:35 PM PDT 24
Peak memory 218060 kb
Host smart-b9078f87-604a-4f41-a2b0-6e137457eaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520379918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.520379918
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1974221546
Short name T364
Test name
Test status
Simulation time 166660883 ps
CPU time 0.9 seconds
Started Jun 23 05:07:36 PM PDT 24
Finished Jun 23 05:07:38 PM PDT 24
Peak memory 200492 kb
Host smart-5f81ce73-572c-48b5-a3b6-2943a72417e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974221546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1974221546
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.184854148
Short name T257
Test name
Test status
Simulation time 831666552 ps
CPU time 4.15 seconds
Started Jun 23 05:07:34 PM PDT 24
Finished Jun 23 05:07:38 PM PDT 24
Peak memory 200920 kb
Host smart-b2550a85-10c5-492b-bed8-51664725081f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184854148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.184854148
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.153116398
Short name T77
Test name
Test status
Simulation time 8395896939 ps
CPU time 12.7 seconds
Started Jun 23 05:07:35 PM PDT 24
Finished Jun 23 05:07:49 PM PDT 24
Peak memory 217828 kb
Host smart-c3f5b2b1-ff45-45a7-af12-b1db65285a04
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153116398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.153116398
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3129299932
Short name T508
Test name
Test status
Simulation time 173732050 ps
CPU time 1.13 seconds
Started Jun 23 05:07:35 PM PDT 24
Finished Jun 23 05:07:36 PM PDT 24
Peak memory 200696 kb
Host smart-329b5965-7ae0-45d3-8e19-6b0c7ca83840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129299932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3129299932
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.3748943167
Short name T295
Test name
Test status
Simulation time 114196168 ps
CPU time 1.19 seconds
Started Jun 23 05:07:38 PM PDT 24
Finished Jun 23 05:07:40 PM PDT 24
Peak memory 200952 kb
Host smart-2e747ad0-12b6-467f-9330-2245dd5eb810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748943167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3748943167
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1415866415
Short name T520
Test name
Test status
Simulation time 9668948772 ps
CPU time 33.61 seconds
Started Jun 23 05:07:36 PM PDT 24
Finished Jun 23 05:08:10 PM PDT 24
Peak memory 209176 kb
Host smart-fd837c52-cbbc-401b-bc81-ea53e560351c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415866415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1415866415
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.957555657
Short name T246
Test name
Test status
Simulation time 300153940 ps
CPU time 2.09 seconds
Started Jun 23 05:07:36 PM PDT 24
Finished Jun 23 05:07:39 PM PDT 24
Peak memory 208908 kb
Host smart-bc561028-b040-43d0-8aae-6738eeee4584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957555657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.957555657
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.4271126773
Short name T262
Test name
Test status
Simulation time 57859633 ps
CPU time 0.76 seconds
Started Jun 23 05:07:35 PM PDT 24
Finished Jun 23 05:07:37 PM PDT 24
Peak memory 200752 kb
Host smart-9bb1456a-7f2b-40d7-b352-7f2837260912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271126773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.4271126773
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.206520657
Short name T263
Test name
Test status
Simulation time 96075595 ps
CPU time 0.81 seconds
Started Jun 23 05:09:09 PM PDT 24
Finished Jun 23 05:09:10 PM PDT 24
Peak memory 200556 kb
Host smart-5cc11af3-eb78-45d6-be0b-7514a499da8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206520657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.206520657
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1309048363
Short name T34
Test name
Test status
Simulation time 2154542339 ps
CPU time 7.75 seconds
Started Jun 23 05:09:00 PM PDT 24
Finished Jun 23 05:09:08 PM PDT 24
Peak memory 218584 kb
Host smart-303b1fec-ccd4-4557-8f65-68b85a6b0121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309048363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1309048363
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1875122093
Short name T355
Test name
Test status
Simulation time 245209285 ps
CPU time 1.07 seconds
Started Jun 23 05:09:07 PM PDT 24
Finished Jun 23 05:09:10 PM PDT 24
Peak memory 218128 kb
Host smart-fe4fa5fd-2af5-4e1b-b0ee-587c8dfe2b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875122093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1875122093
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2660412240
Short name T361
Test name
Test status
Simulation time 216652218 ps
CPU time 0.96 seconds
Started Jun 23 05:08:59 PM PDT 24
Finished Jun 23 05:09:01 PM PDT 24
Peak memory 200432 kb
Host smart-47feb9f4-562d-4855-b62f-ee18ab2d49dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660412240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2660412240
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.557462350
Short name T226
Test name
Test status
Simulation time 1278955302 ps
CPU time 5.73 seconds
Started Jun 23 05:08:59 PM PDT 24
Finished Jun 23 05:09:06 PM PDT 24
Peak memory 200980 kb
Host smart-090fa617-37af-4b50-88d8-74d76f6e6ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557462350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.557462350
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2905358625
Short name T535
Test name
Test status
Simulation time 106739210 ps
CPU time 1.02 seconds
Started Jun 23 05:09:06 PM PDT 24
Finished Jun 23 05:09:08 PM PDT 24
Peak memory 200728 kb
Host smart-2a3fd817-ddfe-46da-aa7b-e6a2ceb5380c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905358625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2905358625
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2503353078
Short name T159
Test name
Test status
Simulation time 106648531 ps
CPU time 1.18 seconds
Started Jun 23 05:09:06 PM PDT 24
Finished Jun 23 05:09:09 PM PDT 24
Peak memory 200944 kb
Host smart-5059be30-522d-4745-97bf-01507602bb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503353078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2503353078
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.714812598
Short name T334
Test name
Test status
Simulation time 6274370984 ps
CPU time 27.3 seconds
Started Jun 23 05:09:02 PM PDT 24
Finished Jun 23 05:09:30 PM PDT 24
Peak memory 200924 kb
Host smart-bc408c48-8c10-4375-8cd5-334c951d81c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714812598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.714812598
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.2656324846
Short name T66
Test name
Test status
Simulation time 131579893 ps
CPU time 1.74 seconds
Started Jun 23 05:08:59 PM PDT 24
Finished Jun 23 05:09:01 PM PDT 24
Peak memory 208940 kb
Host smart-b4951cb9-fc05-4578-b5d3-a332e0053e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656324846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2656324846
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.904610716
Short name T409
Test name
Test status
Simulation time 94117752 ps
CPU time 1.02 seconds
Started Jun 23 05:09:09 PM PDT 24
Finished Jun 23 05:09:11 PM PDT 24
Peak memory 200760 kb
Host smart-561a6297-bcce-4d27-b901-f88e949fae09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904610716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.904610716
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2270819783
Short name T192
Test name
Test status
Simulation time 67030399 ps
CPU time 0.75 seconds
Started Jun 23 05:09:06 PM PDT 24
Finished Jun 23 05:09:08 PM PDT 24
Peak memory 200552 kb
Host smart-b7ac4062-9d47-43aa-97b4-c79c8e8ca58d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270819783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2270819783
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1141095833
Short name T279
Test name
Test status
Simulation time 2163841569 ps
CPU time 8.86 seconds
Started Jun 23 05:09:09 PM PDT 24
Finished Jun 23 05:09:19 PM PDT 24
Peak memory 218632 kb
Host smart-65d2d255-8c9c-4ca5-849e-ca00f6131d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141095833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1141095833
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.4131273201
Short name T311
Test name
Test status
Simulation time 244326552 ps
CPU time 1.07 seconds
Started Jun 23 05:09:06 PM PDT 24
Finished Jun 23 05:09:09 PM PDT 24
Peak memory 218088 kb
Host smart-6c2337f9-bc6e-402b-99ba-18cb617d0e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131273201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.4131273201
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1716341870
Short name T490
Test name
Test status
Simulation time 75997559 ps
CPU time 0.76 seconds
Started Jun 23 05:09:07 PM PDT 24
Finished Jun 23 05:09:09 PM PDT 24
Peak memory 200508 kb
Host smart-1493e123-a81c-4ce9-b02a-d90e61662a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716341870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1716341870
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.18211051
Short name T408
Test name
Test status
Simulation time 1555204770 ps
CPU time 5.83 seconds
Started Jun 23 05:09:10 PM PDT 24
Finished Jun 23 05:09:16 PM PDT 24
Peak memory 200928 kb
Host smart-e92308bc-dda0-468c-874f-b93fd9e4eae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18211051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.18211051
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3052863079
Short name T203
Test name
Test status
Simulation time 151068268 ps
CPU time 1.12 seconds
Started Jun 23 05:09:06 PM PDT 24
Finished Jun 23 05:09:08 PM PDT 24
Peak memory 200680 kb
Host smart-aaa81c3b-3612-4f7c-a16d-4c4027c5cd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052863079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3052863079
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.963761135
Short name T170
Test name
Test status
Simulation time 116908055 ps
CPU time 1.22 seconds
Started Jun 23 05:09:07 PM PDT 24
Finished Jun 23 05:09:10 PM PDT 24
Peak memory 200884 kb
Host smart-dd1c3ab9-897b-4ab6-8931-beeb4157d965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963761135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.963761135
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.1039457887
Short name T243
Test name
Test status
Simulation time 153648219 ps
CPU time 1.06 seconds
Started Jun 23 05:09:08 PM PDT 24
Finished Jun 23 05:09:10 PM PDT 24
Peak memory 200496 kb
Host smart-85947e60-da4b-40b0-bc72-a6b8af0595fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039457887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.1039457887
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.969360294
Short name T491
Test name
Test status
Simulation time 383862365 ps
CPU time 2.42 seconds
Started Jun 23 05:09:09 PM PDT 24
Finished Jun 23 05:09:12 PM PDT 24
Peak memory 200720 kb
Host smart-c1890a44-9ee5-4d22-9fef-4395d3a56889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969360294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.969360294
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2609946250
Short name T235
Test name
Test status
Simulation time 273492423 ps
CPU time 1.57 seconds
Started Jun 23 05:09:08 PM PDT 24
Finished Jun 23 05:09:11 PM PDT 24
Peak memory 200704 kb
Host smart-1f808da6-025b-4043-aaf4-6855ca83a62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609946250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2609946250
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3632269255
Short name T313
Test name
Test status
Simulation time 59739481 ps
CPU time 0.78 seconds
Started Jun 23 05:09:12 PM PDT 24
Finished Jun 23 05:09:14 PM PDT 24
Peak memory 200552 kb
Host smart-20c2a62f-c04a-4113-9728-54b332094b56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632269255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3632269255
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.727590025
Short name T2
Test name
Test status
Simulation time 244947089 ps
CPU time 1.15 seconds
Started Jun 23 05:09:13 PM PDT 24
Finished Jun 23 05:09:15 PM PDT 24
Peak memory 218044 kb
Host smart-d2036d58-e3ef-4639-8992-de8175691d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727590025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.727590025
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.139024512
Short name T450
Test name
Test status
Simulation time 174198157 ps
CPU time 0.88 seconds
Started Jun 23 05:09:07 PM PDT 24
Finished Jun 23 05:09:10 PM PDT 24
Peak memory 200540 kb
Host smart-ce01ea7e-8e22-480d-b30b-ff579c81d23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139024512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.139024512
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.3715761311
Short name T429
Test name
Test status
Simulation time 1140280285 ps
CPU time 5.9 seconds
Started Jun 23 05:09:08 PM PDT 24
Finished Jun 23 05:09:15 PM PDT 24
Peak memory 200912 kb
Host smart-eaa18ce3-ae8d-42bd-8a7b-53e836aa7909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715761311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3715761311
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1343280602
Short name T222
Test name
Test status
Simulation time 146404646 ps
CPU time 1.08 seconds
Started Jun 23 05:09:07 PM PDT 24
Finished Jun 23 05:09:09 PM PDT 24
Peak memory 200732 kb
Host smart-9864efeb-2ad3-4e5a-a950-9ea95e755ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343280602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1343280602
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2964018602
Short name T477
Test name
Test status
Simulation time 118284869 ps
CPU time 1.24 seconds
Started Jun 23 05:09:07 PM PDT 24
Finished Jun 23 05:09:10 PM PDT 24
Peak memory 200940 kb
Host smart-59c3a41b-cb2b-426b-ad94-11f20a48cea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964018602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2964018602
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.3170654502
Short name T516
Test name
Test status
Simulation time 5308361299 ps
CPU time 17.7 seconds
Started Jun 23 05:09:12 PM PDT 24
Finished Jun 23 05:09:30 PM PDT 24
Peak memory 200916 kb
Host smart-733250a5-aa3a-4ad0-8da1-41044de34dc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170654502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3170654502
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3375754273
Short name T472
Test name
Test status
Simulation time 503368405 ps
CPU time 2.84 seconds
Started Jun 23 05:09:06 PM PDT 24
Finished Jun 23 05:09:10 PM PDT 24
Peak memory 200744 kb
Host smart-7946ee90-be6e-4a88-8fe8-3088228a5f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375754273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3375754273
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.387992680
Short name T151
Test name
Test status
Simulation time 145872639 ps
CPU time 1.06 seconds
Started Jun 23 05:09:07 PM PDT 24
Finished Jun 23 05:09:10 PM PDT 24
Peak memory 200704 kb
Host smart-ffa2914d-6a81-40d8-8ccb-09467ff08bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387992680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.387992680
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.3868132340
Short name T526
Test name
Test status
Simulation time 65819047 ps
CPU time 0.75 seconds
Started Jun 23 05:09:13 PM PDT 24
Finished Jun 23 05:09:15 PM PDT 24
Peak memory 200532 kb
Host smart-9eaa20bb-fe8a-4b5a-be98-0677e3598f42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868132340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.3868132340
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2559132638
Short name T382
Test name
Test status
Simulation time 1899544854 ps
CPU time 7.54 seconds
Started Jun 23 05:09:17 PM PDT 24
Finished Jun 23 05:09:25 PM PDT 24
Peak memory 218536 kb
Host smart-df2817e1-ee83-4a77-8f01-bb351cd45ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559132638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2559132638
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1904696860
Short name T385
Test name
Test status
Simulation time 244694879 ps
CPU time 1.07 seconds
Started Jun 23 05:09:10 PM PDT 24
Finished Jun 23 05:09:12 PM PDT 24
Peak memory 218128 kb
Host smart-47d75fdb-0007-4b6d-9f31-35401d4179e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904696860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1904696860
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2394080722
Short name T20
Test name
Test status
Simulation time 199695264 ps
CPU time 0.93 seconds
Started Jun 23 05:09:16 PM PDT 24
Finished Jun 23 05:09:18 PM PDT 24
Peak memory 200564 kb
Host smart-2d50a18e-1a8a-47fd-acdf-e8154f0e6a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394080722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2394080722
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3585715098
Short name T136
Test name
Test status
Simulation time 1297241593 ps
CPU time 5.77 seconds
Started Jun 23 05:09:11 PM PDT 24
Finished Jun 23 05:09:18 PM PDT 24
Peak memory 201120 kb
Host smart-5adddf84-c36d-481f-b8cb-1b02af2e894e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585715098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3585715098
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.822042672
Short name T193
Test name
Test status
Simulation time 106116278 ps
CPU time 1.03 seconds
Started Jun 23 05:09:17 PM PDT 24
Finished Jun 23 05:09:19 PM PDT 24
Peak memory 200740 kb
Host smart-7b7761e4-23c2-4953-b71a-d711ca482bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822042672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.822042672
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3557211571
Short name T390
Test name
Test status
Simulation time 230285874 ps
CPU time 1.55 seconds
Started Jun 23 05:09:12 PM PDT 24
Finished Jun 23 05:09:14 PM PDT 24
Peak memory 200952 kb
Host smart-96ad3485-9412-4dbe-bb7f-5222964bf032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557211571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3557211571
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.556932476
Short name T181
Test name
Test status
Simulation time 5783328284 ps
CPU time 26.48 seconds
Started Jun 23 05:09:17 PM PDT 24
Finished Jun 23 05:09:44 PM PDT 24
Peak memory 210864 kb
Host smart-a4807c5b-393c-44aa-aa37-35ec3c0ec2f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556932476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.556932476
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2624030198
Short name T377
Test name
Test status
Simulation time 122904099 ps
CPU time 1.58 seconds
Started Jun 23 05:09:10 PM PDT 24
Finished Jun 23 05:09:12 PM PDT 24
Peak memory 200744 kb
Host smart-5828194b-c95f-4d17-a95e-13839e34fd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624030198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2624030198
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2610910308
Short name T303
Test name
Test status
Simulation time 121196113 ps
CPU time 0.99 seconds
Started Jun 23 05:09:14 PM PDT 24
Finished Jun 23 05:09:15 PM PDT 24
Peak memory 200680 kb
Host smart-908e3f89-27aa-4312-9135-e6e3af7e21ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610910308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2610910308
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.1231471025
Short name T351
Test name
Test status
Simulation time 71039181 ps
CPU time 0.8 seconds
Started Jun 23 05:09:20 PM PDT 24
Finished Jun 23 05:09:21 PM PDT 24
Peak memory 200556 kb
Host smart-65a0006e-150d-4449-9173-bee909895156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231471025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1231471025
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3180920447
Short name T43
Test name
Test status
Simulation time 1231949373 ps
CPU time 5.44 seconds
Started Jun 23 05:09:20 PM PDT 24
Finished Jun 23 05:09:26 PM PDT 24
Peak memory 218404 kb
Host smart-02614dfb-a1a1-4db1-9d11-d9978e7bf081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180920447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3180920447
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1892772046
Short name T362
Test name
Test status
Simulation time 244237027 ps
CPU time 1.08 seconds
Started Jun 23 05:09:19 PM PDT 24
Finished Jun 23 05:09:21 PM PDT 24
Peak memory 218128 kb
Host smart-90e79ece-7ab4-46e3-a327-aa024fdd1acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892772046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1892772046
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.199207958
Short name T431
Test name
Test status
Simulation time 179233745 ps
CPU time 0.86 seconds
Started Jun 23 05:09:10 PM PDT 24
Finished Jun 23 05:09:11 PM PDT 24
Peak memory 200464 kb
Host smart-02600c7b-05f4-4e4d-bffa-e1299c3b419a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199207958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.199207958
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2412432788
Short name T14
Test name
Test status
Simulation time 1157573504 ps
CPU time 4.71 seconds
Started Jun 23 05:09:14 PM PDT 24
Finished Jun 23 05:09:19 PM PDT 24
Peak memory 200984 kb
Host smart-6e12154d-ba33-4116-bd2e-ea9b29df95c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412432788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2412432788
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.2346556521
Short name T365
Test name
Test status
Simulation time 187540295 ps
CPU time 1.2 seconds
Started Jun 23 05:09:18 PM PDT 24
Finished Jun 23 05:09:19 PM PDT 24
Peak memory 200696 kb
Host smart-ffbf7430-37ff-48ad-a604-2525336d2230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346556521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.2346556521
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3787733200
Short name T182
Test name
Test status
Simulation time 119563847 ps
CPU time 1.26 seconds
Started Jun 23 05:09:15 PM PDT 24
Finished Jun 23 05:09:17 PM PDT 24
Peak memory 200988 kb
Host smart-8a971386-af75-43e2-9806-b3f337b1ffa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787733200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3787733200
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3262549083
Short name T90
Test name
Test status
Simulation time 3985607377 ps
CPU time 14.51 seconds
Started Jun 23 05:09:18 PM PDT 24
Finished Jun 23 05:09:33 PM PDT 24
Peak memory 217268 kb
Host smart-8e45bcee-f6b4-4e71-ac71-ad8756d546ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262549083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3262549083
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3425835754
Short name T223
Test name
Test status
Simulation time 130027429 ps
CPU time 1.57 seconds
Started Jun 23 05:09:13 PM PDT 24
Finished Jun 23 05:09:16 PM PDT 24
Peak memory 200732 kb
Host smart-758c7e1c-ae42-448a-bbe9-3c7c97675fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425835754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3425835754
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.2395875965
Short name T195
Test name
Test status
Simulation time 84580940 ps
CPU time 0.84 seconds
Started Jun 23 05:09:15 PM PDT 24
Finished Jun 23 05:09:16 PM PDT 24
Peak memory 200680 kb
Host smart-3115dd1c-ff48-43d3-b8cf-3c0b4a110859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395875965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2395875965
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.4133015014
Short name T347
Test name
Test status
Simulation time 55527773 ps
CPU time 0.74 seconds
Started Jun 23 05:09:17 PM PDT 24
Finished Jun 23 05:09:19 PM PDT 24
Peak memory 200548 kb
Host smart-6e025871-d338-444d-bc17-cc95c2ab39f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133015014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.4133015014
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1719453654
Short name T259
Test name
Test status
Simulation time 1215533142 ps
CPU time 5.8 seconds
Started Jun 23 05:09:21 PM PDT 24
Finished Jun 23 05:09:27 PM PDT 24
Peak memory 218556 kb
Host smart-d958fb1a-a28f-45cf-ad09-f98f3a029e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719453654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1719453654
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1169686644
Short name T188
Test name
Test status
Simulation time 244373160 ps
CPU time 1.16 seconds
Started Jun 23 05:09:17 PM PDT 24
Finished Jun 23 05:09:19 PM PDT 24
Peak memory 218152 kb
Host smart-f06e0c14-95b0-415e-90d1-7e9f2efb742e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169686644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1169686644
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.242256462
Short name T514
Test name
Test status
Simulation time 80372691 ps
CPU time 0.76 seconds
Started Jun 23 05:09:18 PM PDT 24
Finished Jun 23 05:09:20 PM PDT 24
Peak memory 200544 kb
Host smart-e74bfeae-655e-4860-bd30-ee7f0d56d40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242256462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.242256462
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3146079425
Short name T264
Test name
Test status
Simulation time 1780630270 ps
CPU time 6.86 seconds
Started Jun 23 05:09:18 PM PDT 24
Finished Jun 23 05:09:26 PM PDT 24
Peak memory 200924 kb
Host smart-b2aca988-7c97-42c6-ba94-5d0c577edb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146079425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3146079425
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2430232338
Short name T39
Test name
Test status
Simulation time 110706081 ps
CPU time 1.04 seconds
Started Jun 23 05:09:19 PM PDT 24
Finished Jun 23 05:09:21 PM PDT 24
Peak memory 200688 kb
Host smart-66186af8-64ed-435e-a789-d91c9313b637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430232338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2430232338
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2892784663
Short name T493
Test name
Test status
Simulation time 191317334 ps
CPU time 1.29 seconds
Started Jun 23 05:09:15 PM PDT 24
Finished Jun 23 05:09:16 PM PDT 24
Peak memory 200888 kb
Host smart-4cf376c9-e861-49c3-af1a-d18af7094f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892784663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2892784663
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2795888908
Short name T335
Test name
Test status
Simulation time 5794654869 ps
CPU time 25 seconds
Started Jun 23 05:09:21 PM PDT 24
Finished Jun 23 05:09:46 PM PDT 24
Peak memory 200916 kb
Host smart-1cb370c1-11c1-409b-9928-0d1f7bcc5a4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795888908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2795888908
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.2409342850
Short name T229
Test name
Test status
Simulation time 413542173 ps
CPU time 2.23 seconds
Started Jun 23 05:09:19 PM PDT 24
Finished Jun 23 05:09:22 PM PDT 24
Peak memory 200748 kb
Host smart-60ce1faa-bc5a-4107-846a-ef9f30d065f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409342850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2409342850
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2535900469
Short name T167
Test name
Test status
Simulation time 80154800 ps
CPU time 0.88 seconds
Started Jun 23 05:09:17 PM PDT 24
Finished Jun 23 05:09:19 PM PDT 24
Peak memory 200652 kb
Host smart-5737375e-b188-41d1-901a-07913fa31a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535900469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2535900469
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.4247970391
Short name T187
Test name
Test status
Simulation time 76902591 ps
CPU time 0.78 seconds
Started Jun 23 05:09:22 PM PDT 24
Finished Jun 23 05:09:24 PM PDT 24
Peak memory 200536 kb
Host smart-e2e05b1c-08e3-45d2-98f3-434b76416106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247970391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.4247970391
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3716478570
Short name T55
Test name
Test status
Simulation time 1210713235 ps
CPU time 5.55 seconds
Started Jun 23 05:09:20 PM PDT 24
Finished Jun 23 05:09:26 PM PDT 24
Peak memory 217960 kb
Host smart-b65fbc2c-3a7e-407a-8e85-3ecac11defb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716478570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3716478570
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3280292675
Short name T318
Test name
Test status
Simulation time 244820010 ps
CPU time 1.01 seconds
Started Jun 23 05:09:19 PM PDT 24
Finished Jun 23 05:09:21 PM PDT 24
Peak memory 218096 kb
Host smart-f9a76d86-e2fd-4eeb-a9ae-a22d6fbea273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280292675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3280292675
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.977133466
Short name T511
Test name
Test status
Simulation time 80327355 ps
CPU time 0.82 seconds
Started Jun 23 05:09:19 PM PDT 24
Finished Jun 23 05:09:21 PM PDT 24
Peak memory 200392 kb
Host smart-ca1ab3f2-0940-4e67-82cf-bac03bd907d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977133466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.977133466
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.606165459
Short name T284
Test name
Test status
Simulation time 1600575973 ps
CPU time 5.63 seconds
Started Jun 23 05:09:17 PM PDT 24
Finished Jun 23 05:09:24 PM PDT 24
Peak memory 200924 kb
Host smart-23ad4f19-5ab2-4439-9f2a-35260ebb1a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606165459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.606165459
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.4225337182
Short name T12
Test name
Test status
Simulation time 140942778 ps
CPU time 1.06 seconds
Started Jun 23 05:09:22 PM PDT 24
Finished Jun 23 05:09:24 PM PDT 24
Peak memory 200740 kb
Host smart-1f2dc908-71c8-4140-9acd-777e6dc3f959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225337182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.4225337182
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.453194365
Short name T249
Test name
Test status
Simulation time 125328192 ps
CPU time 1.21 seconds
Started Jun 23 05:09:17 PM PDT 24
Finished Jun 23 05:09:18 PM PDT 24
Peak memory 200952 kb
Host smart-93d91fe3-3714-4eb5-811b-d04fcb8770f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453194365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.453194365
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2574564999
Short name T494
Test name
Test status
Simulation time 5190738975 ps
CPU time 25.83 seconds
Started Jun 23 05:09:23 PM PDT 24
Finished Jun 23 05:09:50 PM PDT 24
Peak memory 210800 kb
Host smart-b85b071a-8fc3-49c4-8785-189d6dc7277d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574564999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2574564999
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3621636059
Short name T485
Test name
Test status
Simulation time 280164350 ps
CPU time 1.93 seconds
Started Jun 23 05:09:16 PM PDT 24
Finished Jun 23 05:09:19 PM PDT 24
Peak memory 200692 kb
Host smart-c4118d54-cb2c-4107-b8c9-0a7caa75e371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621636059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3621636059
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1256372636
Short name T224
Test name
Test status
Simulation time 91938676 ps
CPU time 0.89 seconds
Started Jun 23 05:09:19 PM PDT 24
Finished Jun 23 05:09:21 PM PDT 24
Peak memory 200556 kb
Host smart-8dea57cc-04ff-4e09-b7a5-ac14591ce36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256372636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1256372636
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3320706877
Short name T221
Test name
Test status
Simulation time 67206061 ps
CPU time 0.77 seconds
Started Jun 23 05:09:24 PM PDT 24
Finished Jun 23 05:09:26 PM PDT 24
Peak memory 200548 kb
Host smart-b3eda0c1-1985-4126-b532-ed4fa37e9e68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320706877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3320706877
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3707241472
Short name T509
Test name
Test status
Simulation time 1232873756 ps
CPU time 5.77 seconds
Started Jun 23 05:09:23 PM PDT 24
Finished Jun 23 05:09:30 PM PDT 24
Peak memory 222140 kb
Host smart-06baf440-2aa5-4708-99e9-540c04485af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707241472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3707241472
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3759798952
Short name T407
Test name
Test status
Simulation time 244662494 ps
CPU time 1.09 seconds
Started Jun 23 05:09:26 PM PDT 24
Finished Jun 23 05:09:27 PM PDT 24
Peak memory 218148 kb
Host smart-346527eb-d267-479f-9b0c-d61a3a5f6bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759798952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3759798952
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1580479092
Short name T17
Test name
Test status
Simulation time 221356707 ps
CPU time 0.89 seconds
Started Jun 23 05:09:29 PM PDT 24
Finished Jun 23 05:09:30 PM PDT 24
Peak memory 200512 kb
Host smart-77941aa6-19c9-4abb-9083-b2fd6a22410e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580479092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1580479092
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.3780495516
Short name T101
Test name
Test status
Simulation time 819627528 ps
CPU time 4.17 seconds
Started Jun 23 05:09:23 PM PDT 24
Finished Jun 23 05:09:28 PM PDT 24
Peak memory 200944 kb
Host smart-3dd9e5d3-276f-4805-90fa-a8671580b7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780495516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3780495516
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.589683004
Short name T241
Test name
Test status
Simulation time 96524360 ps
CPU time 1.05 seconds
Started Jun 23 05:09:26 PM PDT 24
Finished Jun 23 05:09:27 PM PDT 24
Peak memory 200744 kb
Host smart-85696c59-4ca9-44d6-823c-b4fbf7e1af96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589683004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.589683004
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2104191747
Short name T495
Test name
Test status
Simulation time 224356110 ps
CPU time 1.48 seconds
Started Jun 23 05:09:22 PM PDT 24
Finished Jun 23 05:09:24 PM PDT 24
Peak memory 200940 kb
Host smart-31378005-bfb1-4717-a974-317142c93a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104191747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2104191747
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3969030322
Short name T252
Test name
Test status
Simulation time 4456231580 ps
CPU time 20.55 seconds
Started Jun 23 05:09:22 PM PDT 24
Finished Jun 23 05:09:43 PM PDT 24
Peak memory 209228 kb
Host smart-0b00e8cf-d67c-44fc-81a4-7ce9cfda279a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969030322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3969030322
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2153999901
Short name T344
Test name
Test status
Simulation time 307617867 ps
CPU time 1.87 seconds
Started Jun 23 05:09:24 PM PDT 24
Finished Jun 23 05:09:27 PM PDT 24
Peak memory 200748 kb
Host smart-d9b2abe3-f534-4ad3-aa2b-0425b8405acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153999901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2153999901
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.211555880
Short name T15
Test name
Test status
Simulation time 76037401 ps
CPU time 0.86 seconds
Started Jun 23 05:09:22 PM PDT 24
Finished Jun 23 05:09:23 PM PDT 24
Peak memory 200760 kb
Host smart-36a3fcf4-c902-4bfb-a18f-b52a5896c881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211555880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.211555880
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.1859489858
Short name T220
Test name
Test status
Simulation time 77416297 ps
CPU time 0.78 seconds
Started Jun 23 05:09:40 PM PDT 24
Finished Jun 23 05:09:41 PM PDT 24
Peak memory 200516 kb
Host smart-c927260a-8a1d-4219-a8d0-1a016b9721ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859489858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1859489858
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2960800582
Short name T59
Test name
Test status
Simulation time 1228883741 ps
CPU time 5.82 seconds
Started Jun 23 05:09:26 PM PDT 24
Finished Jun 23 05:09:32 PM PDT 24
Peak memory 218480 kb
Host smart-15fe3331-5d95-47a6-b0cc-50bd76f809ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960800582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2960800582
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1618253135
Short name T171
Test name
Test status
Simulation time 244584381 ps
CPU time 1.08 seconds
Started Jun 23 05:09:29 PM PDT 24
Finished Jun 23 05:09:30 PM PDT 24
Peak memory 218152 kb
Host smart-aaba725e-a4d1-4386-b0fc-22c0227356a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618253135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1618253135
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.1772149479
Short name T213
Test name
Test status
Simulation time 89274345 ps
CPU time 0.76 seconds
Started Jun 23 05:09:25 PM PDT 24
Finished Jun 23 05:09:26 PM PDT 24
Peak memory 200584 kb
Host smart-9137c508-113f-46f6-be0e-a9b6bd448aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772149479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1772149479
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1056714507
Short name T298
Test name
Test status
Simulation time 1690499317 ps
CPU time 6.65 seconds
Started Jun 23 05:09:26 PM PDT 24
Finished Jun 23 05:09:33 PM PDT 24
Peak memory 200748 kb
Host smart-9c9a5228-0dec-4742-824d-068c45f57315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056714507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1056714507
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3816457838
Short name T530
Test name
Test status
Simulation time 156241706 ps
CPU time 1.2 seconds
Started Jun 23 05:09:22 PM PDT 24
Finished Jun 23 05:09:24 PM PDT 24
Peak memory 200676 kb
Host smart-96fc9ef8-659b-441a-9f78-e612441e4cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816457838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3816457838
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.243165961
Short name T418
Test name
Test status
Simulation time 202910231 ps
CPU time 1.42 seconds
Started Jun 23 05:09:22 PM PDT 24
Finished Jun 23 05:09:25 PM PDT 24
Peak memory 200892 kb
Host smart-b3b1ffa4-253e-4d20-98df-f64a7cad10e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243165961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.243165961
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.2523502357
Short name T440
Test name
Test status
Simulation time 2523753908 ps
CPU time 13.25 seconds
Started Jun 23 05:09:27 PM PDT 24
Finished Jun 23 05:09:40 PM PDT 24
Peak memory 209128 kb
Host smart-bf9029ba-8c8e-4a85-b94c-9eaf3177c652
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523502357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2523502357
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3183610628
Short name T393
Test name
Test status
Simulation time 435416562 ps
CPU time 2.53 seconds
Started Jun 23 05:09:24 PM PDT 24
Finished Jun 23 05:09:27 PM PDT 24
Peak memory 200784 kb
Host smart-d9d31666-48df-4385-a0d7-f5e453f493aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183610628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3183610628
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1663923777
Short name T267
Test name
Test status
Simulation time 65207143 ps
CPU time 0.78 seconds
Started Jun 23 05:09:24 PM PDT 24
Finished Jun 23 05:09:25 PM PDT 24
Peak memory 200752 kb
Host smart-e3913c87-246b-4cec-b295-d256bd66fd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663923777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1663923777
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.871352756
Short name T1
Test name
Test status
Simulation time 67121789 ps
CPU time 0.78 seconds
Started Jun 23 05:09:31 PM PDT 24
Finished Jun 23 05:09:33 PM PDT 24
Peak memory 200608 kb
Host smart-0b8b7f84-1ad9-475c-905e-4c5d8c0e27af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871352756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.871352756
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.646641344
Short name T33
Test name
Test status
Simulation time 1228911291 ps
CPU time 5.34 seconds
Started Jun 23 05:09:30 PM PDT 24
Finished Jun 23 05:09:36 PM PDT 24
Peak memory 218512 kb
Host smart-64fd0186-7217-410c-b61c-d6d8ec9a4380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646641344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.646641344
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1201727727
Short name T438
Test name
Test status
Simulation time 244192575 ps
CPU time 1.08 seconds
Started Jun 23 05:09:40 PM PDT 24
Finished Jun 23 05:09:42 PM PDT 24
Peak memory 218108 kb
Host smart-e19aa73e-aec2-4e12-a2e8-524cb83f8a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201727727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1201727727
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.3170430576
Short name T290
Test name
Test status
Simulation time 162694034 ps
CPU time 0.88 seconds
Started Jun 23 05:09:29 PM PDT 24
Finished Jun 23 05:09:30 PM PDT 24
Peak memory 200492 kb
Host smart-bdd0b4bf-d0d4-4e12-8bf7-899e2559f886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170430576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3170430576
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.335624209
Short name T42
Test name
Test status
Simulation time 1102043472 ps
CPU time 5.55 seconds
Started Jun 23 05:09:31 PM PDT 24
Finished Jun 23 05:09:37 PM PDT 24
Peak memory 200864 kb
Host smart-d4f105fb-8a56-44c5-bf0e-77ce35355b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335624209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.335624209
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.607144885
Short name T420
Test name
Test status
Simulation time 98290606 ps
CPU time 0.98 seconds
Started Jun 23 05:09:29 PM PDT 24
Finished Jun 23 05:09:31 PM PDT 24
Peak memory 200744 kb
Host smart-c7971177-6b52-40fa-9e7f-73e7c1b8c059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607144885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.607144885
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1673304261
Short name T282
Test name
Test status
Simulation time 182120363 ps
CPU time 1.31 seconds
Started Jun 23 05:09:31 PM PDT 24
Finished Jun 23 05:09:32 PM PDT 24
Peak memory 200900 kb
Host smart-5cf4d232-26fe-4a0c-983d-e067f781b148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673304261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1673304261
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.868972628
Short name T328
Test name
Test status
Simulation time 3665928088 ps
CPU time 13.1 seconds
Started Jun 23 05:09:28 PM PDT 24
Finished Jun 23 05:09:42 PM PDT 24
Peak memory 200984 kb
Host smart-6e757c36-391b-4835-92e3-198260250559
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868972628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.868972628
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.4047108614
Short name T488
Test name
Test status
Simulation time 328164825 ps
CPU time 2.15 seconds
Started Jun 23 05:09:28 PM PDT 24
Finished Jun 23 05:09:30 PM PDT 24
Peak memory 200748 kb
Host smart-23528d86-8322-41b9-aac8-6054f987a63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047108614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.4047108614
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.4120051229
Short name T350
Test name
Test status
Simulation time 174567819 ps
CPU time 1.28 seconds
Started Jun 23 05:09:29 PM PDT 24
Finished Jun 23 05:09:31 PM PDT 24
Peak memory 200752 kb
Host smart-56b42d79-cce6-4eb9-b724-e5eaaf008647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120051229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.4120051229
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.961995798
Short name T207
Test name
Test status
Simulation time 69361198 ps
CPU time 0.8 seconds
Started Jun 23 05:07:39 PM PDT 24
Finished Jun 23 05:07:41 PM PDT 24
Peak memory 200544 kb
Host smart-f88550b9-54f8-4f91-8860-b069458f2071
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961995798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.961995798
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1219873669
Short name T512
Test name
Test status
Simulation time 2352763442 ps
CPU time 8.76 seconds
Started Jun 23 05:07:36 PM PDT 24
Finished Jun 23 05:07:45 PM PDT 24
Peak memory 222392 kb
Host smart-bd7fd65e-7ff2-4b4a-9340-2fe5a28cfe88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219873669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1219873669
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2599372420
Short name T470
Test name
Test status
Simulation time 244373399 ps
CPU time 1.1 seconds
Started Jun 23 05:07:39 PM PDT 24
Finished Jun 23 05:07:41 PM PDT 24
Peak memory 218128 kb
Host smart-694c2577-9cb1-4e57-80d8-b1af1aa44850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599372420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2599372420
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.452081694
Short name T23
Test name
Test status
Simulation time 89815095 ps
CPU time 0.77 seconds
Started Jun 23 05:07:35 PM PDT 24
Finished Jun 23 05:07:36 PM PDT 24
Peak memory 200556 kb
Host smart-a1cc9914-7ae0-460f-b7f5-3c6e4a9ab24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452081694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.452081694
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2259736463
Short name T61
Test name
Test status
Simulation time 1401589035 ps
CPU time 6.31 seconds
Started Jun 23 05:07:38 PM PDT 24
Finished Jun 23 05:07:45 PM PDT 24
Peak memory 200944 kb
Host smart-f55df842-0877-42d7-918a-205f050cea71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259736463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2259736463
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.434959472
Short name T78
Test name
Test status
Simulation time 8284144970 ps
CPU time 13.3 seconds
Started Jun 23 05:07:47 PM PDT 24
Finished Jun 23 05:08:01 PM PDT 24
Peak memory 217744 kb
Host smart-529a65b4-4c8c-4288-97e3-ff9bf6d58a33
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434959472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.434959472
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.298648639
Short name T443
Test name
Test status
Simulation time 107704572 ps
CPU time 0.99 seconds
Started Jun 23 05:07:37 PM PDT 24
Finished Jun 23 05:07:39 PM PDT 24
Peak memory 200732 kb
Host smart-aba9be7a-e40d-4a37-92ed-60d24d22b85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298648639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.298648639
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.141730945
Short name T82
Test name
Test status
Simulation time 237361463 ps
CPU time 1.63 seconds
Started Jun 23 05:07:35 PM PDT 24
Finished Jun 23 05:07:37 PM PDT 24
Peak memory 201096 kb
Host smart-82848186-e186-4dda-8226-5e15e4108011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141730945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.141730945
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2379101582
Short name T65
Test name
Test status
Simulation time 5963455056 ps
CPU time 21.75 seconds
Started Jun 23 05:07:36 PM PDT 24
Finished Jun 23 05:07:59 PM PDT 24
Peak memory 209840 kb
Host smart-0f00aee8-105f-4f3b-b9eb-3bc19dd413ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379101582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2379101582
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2891919064
Short name T302
Test name
Test status
Simulation time 123240344 ps
CPU time 1.59 seconds
Started Jun 23 05:07:37 PM PDT 24
Finished Jun 23 05:07:40 PM PDT 24
Peak memory 200780 kb
Host smart-6e14f160-0d1e-4d9c-ad96-8ee2d7862d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891919064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2891919064
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.542098151
Short name T132
Test name
Test status
Simulation time 68537857 ps
CPU time 0.75 seconds
Started Jun 23 05:09:37 PM PDT 24
Finished Jun 23 05:09:38 PM PDT 24
Peak memory 200556 kb
Host smart-2502272f-59c1-4784-b230-5dbe9c430da7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542098151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.542098151
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.3877675216
Short name T483
Test name
Test status
Simulation time 2172253843 ps
CPU time 7.92 seconds
Started Jun 23 05:09:36 PM PDT 24
Finished Jun 23 05:09:45 PM PDT 24
Peak memory 218544 kb
Host smart-39c90ca5-6a5b-4d1b-9baa-96d60443a771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877675216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3877675216
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2772626831
Short name T296
Test name
Test status
Simulation time 243083075 ps
CPU time 1.1 seconds
Started Jun 23 05:09:39 PM PDT 24
Finished Jun 23 05:09:41 PM PDT 24
Peak memory 218104 kb
Host smart-1419fe35-1605-4a1f-b7c1-bbe76459204f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772626831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2772626831
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.1354752834
Short name T18
Test name
Test status
Simulation time 183529663 ps
CPU time 0.93 seconds
Started Jun 23 05:09:31 PM PDT 24
Finished Jun 23 05:09:32 PM PDT 24
Peak memory 200576 kb
Host smart-80b8347b-2a32-4057-881b-526ca8607067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354752834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1354752834
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.4237421524
Short name T466
Test name
Test status
Simulation time 1161629196 ps
CPU time 5.32 seconds
Started Jun 23 05:09:31 PM PDT 24
Finished Jun 23 05:09:37 PM PDT 24
Peak memory 200972 kb
Host smart-fd0b23d5-0a2a-4df2-84ca-301fcca5b366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237421524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.4237421524
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3005849225
Short name T441
Test name
Test status
Simulation time 105159062 ps
CPU time 1 seconds
Started Jun 23 05:09:35 PM PDT 24
Finished Jun 23 05:09:36 PM PDT 24
Peak memory 200732 kb
Host smart-e5b59e44-5b37-4169-a64b-45b361bc3178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005849225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3005849225
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.4176282122
Short name T227
Test name
Test status
Simulation time 198191797 ps
CPU time 1.5 seconds
Started Jun 23 05:09:31 PM PDT 24
Finished Jun 23 05:09:33 PM PDT 24
Peak memory 200836 kb
Host smart-7bca9acf-d275-4b78-b31c-f5a170f056e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176282122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.4176282122
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2619225836
Short name T125
Test name
Test status
Simulation time 9693610916 ps
CPU time 34.29 seconds
Started Jun 23 05:09:46 PM PDT 24
Finished Jun 23 05:10:22 PM PDT 24
Peak memory 200924 kb
Host smart-67c52d9e-8e6c-4aa5-839d-a445e7f45f6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619225836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2619225836
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.3308740244
Short name T527
Test name
Test status
Simulation time 120661564 ps
CPU time 1.58 seconds
Started Jun 23 05:09:46 PM PDT 24
Finished Jun 23 05:09:49 PM PDT 24
Peak memory 208936 kb
Host smart-73b67f60-7b9f-461d-8480-ad4864db0a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308740244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3308740244
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.826606435
Short name T289
Test name
Test status
Simulation time 139619303 ps
CPU time 1.2 seconds
Started Jun 23 05:09:33 PM PDT 24
Finished Jun 23 05:09:34 PM PDT 24
Peak memory 200748 kb
Host smart-739634bc-d625-4423-8a84-0104b08bc6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826606435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.826606435
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1969721580
Short name T305
Test name
Test status
Simulation time 70273598 ps
CPU time 0.85 seconds
Started Jun 23 05:09:34 PM PDT 24
Finished Jun 23 05:09:35 PM PDT 24
Peak memory 200480 kb
Host smart-21da0aed-d1d6-48c5-9e48-979b8fb68e9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969721580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1969721580
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3355827811
Short name T301
Test name
Test status
Simulation time 1884668492 ps
CPU time 7.48 seconds
Started Jun 23 05:09:33 PM PDT 24
Finished Jun 23 05:09:41 PM PDT 24
Peak memory 218712 kb
Host smart-e2a82da2-6a2e-422c-a36f-741ab8dc6333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355827811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3355827811
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3433663799
Short name T197
Test name
Test status
Simulation time 244325819 ps
CPU time 1.04 seconds
Started Jun 23 05:09:46 PM PDT 24
Finished Jun 23 05:09:48 PM PDT 24
Peak memory 218104 kb
Host smart-0c1f15e7-7c9a-4cd4-9f31-4a9d3380389b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433663799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3433663799
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.2277538557
Short name T357
Test name
Test status
Simulation time 100898620 ps
CPU time 0.81 seconds
Started Jun 23 05:09:33 PM PDT 24
Finished Jun 23 05:09:34 PM PDT 24
Peak memory 200524 kb
Host smart-196b2239-bb0b-475c-81e3-65d9ca8233cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277538557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2277538557
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2429606554
Short name T164
Test name
Test status
Simulation time 980333388 ps
CPU time 4.57 seconds
Started Jun 23 05:09:39 PM PDT 24
Finished Jun 23 05:09:44 PM PDT 24
Peak memory 200916 kb
Host smart-da44117e-e93a-462d-bb1e-415a78c03385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429606554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2429606554
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2379201474
Short name T381
Test name
Test status
Simulation time 103290808 ps
CPU time 1.01 seconds
Started Jun 23 05:09:36 PM PDT 24
Finished Jun 23 05:09:38 PM PDT 24
Peak memory 200656 kb
Host smart-927a9eb2-ed6a-471b-ad99-d9a9c71c2854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379201474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2379201474
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3574314804
Short name T131
Test name
Test status
Simulation time 112909870 ps
CPU time 1.19 seconds
Started Jun 23 05:09:46 PM PDT 24
Finished Jun 23 05:09:48 PM PDT 24
Peak memory 200936 kb
Host smart-4206b7a2-46c0-4b15-bf6f-a301352f703a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574314804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3574314804
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3751788161
Short name T500
Test name
Test status
Simulation time 130326502 ps
CPU time 1.6 seconds
Started Jun 23 05:09:34 PM PDT 24
Finished Jun 23 05:09:37 PM PDT 24
Peak memory 208916 kb
Host smart-0602a24c-f930-41c5-92a7-c5303ffe39c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751788161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3751788161
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.676744819
Short name T316
Test name
Test status
Simulation time 296232713 ps
CPU time 1.49 seconds
Started Jun 23 05:09:33 PM PDT 24
Finished Jun 23 05:09:35 PM PDT 24
Peak memory 200904 kb
Host smart-d52135ad-4b2d-4f32-9633-6c0df5913777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676744819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.676744819
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3779516031
Short name T469
Test name
Test status
Simulation time 91329791 ps
CPU time 0.85 seconds
Started Jun 23 05:09:43 PM PDT 24
Finished Jun 23 05:09:44 PM PDT 24
Peak memory 200552 kb
Host smart-95ed1b9b-4e86-4500-b865-69430120aa49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779516031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3779516031
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.3390649865
Short name T436
Test name
Test status
Simulation time 2348920368 ps
CPU time 9.38 seconds
Started Jun 23 05:09:41 PM PDT 24
Finished Jun 23 05:09:51 PM PDT 24
Peak memory 218596 kb
Host smart-e6025a8d-c17c-4458-a2de-149489a3cf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390649865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.3390649865
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.178273629
Short name T510
Test name
Test status
Simulation time 243910140 ps
CPU time 1.12 seconds
Started Jun 23 05:09:38 PM PDT 24
Finished Jun 23 05:09:40 PM PDT 24
Peak memory 217984 kb
Host smart-065da88a-0aa4-4d63-b67c-ee5385127a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178273629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.178273629
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2669368476
Short name T417
Test name
Test status
Simulation time 147113643 ps
CPU time 0.86 seconds
Started Jun 23 05:09:38 PM PDT 24
Finished Jun 23 05:09:39 PM PDT 24
Peak memory 200568 kb
Host smart-df4f835a-daa9-42a3-9d45-b01c8adb5637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669368476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2669368476
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1863826901
Short name T232
Test name
Test status
Simulation time 1702538470 ps
CPU time 6.78 seconds
Started Jun 23 05:09:41 PM PDT 24
Finished Jun 23 05:09:48 PM PDT 24
Peak memory 200836 kb
Host smart-79d12e1b-ab9c-4e8d-8f50-da0e72208eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863826901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1863826901
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.398606685
Short name T337
Test name
Test status
Simulation time 182538925 ps
CPU time 1.18 seconds
Started Jun 23 05:09:40 PM PDT 24
Finished Jun 23 05:09:41 PM PDT 24
Peak memory 200740 kb
Host smart-266a3306-e819-42e1-91f4-dd49abd70ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398606685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.398606685
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.786715005
Short name T434
Test name
Test status
Simulation time 190279215 ps
CPU time 1.57 seconds
Started Jun 23 05:09:40 PM PDT 24
Finished Jun 23 05:09:42 PM PDT 24
Peak memory 201100 kb
Host smart-9c6dda58-5983-4dec-869d-42316c6e58a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786715005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.786715005
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1779258416
Short name T307
Test name
Test status
Simulation time 1535246547 ps
CPU time 6.64 seconds
Started Jun 23 05:09:40 PM PDT 24
Finished Jun 23 05:09:47 PM PDT 24
Peak memory 200936 kb
Host smart-5ed177e4-2345-40ba-bc4e-695ee2a7d58e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779258416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1779258416
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2073987911
Short name T276
Test name
Test status
Simulation time 281990919 ps
CPU time 1.99 seconds
Started Jun 23 05:09:41 PM PDT 24
Finished Jun 23 05:09:44 PM PDT 24
Peak memory 208880 kb
Host smart-4cabab80-65f5-4ef8-a98b-c59c9c74db32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073987911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2073987911
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3326726786
Short name T38
Test name
Test status
Simulation time 90205633 ps
CPU time 0.88 seconds
Started Jun 23 05:09:42 PM PDT 24
Finished Jun 23 05:09:43 PM PDT 24
Peak memory 200704 kb
Host smart-a641d7db-3d05-4bc6-99bb-bb3ad6254820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326726786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3326726786
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2888053095
Short name T416
Test name
Test status
Simulation time 66689329 ps
CPU time 0.79 seconds
Started Jun 23 05:09:46 PM PDT 24
Finished Jun 23 05:09:48 PM PDT 24
Peak memory 200568 kb
Host smart-906d0547-effe-4e80-bcad-a67b123642eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888053095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2888053095
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2651460636
Short name T27
Test name
Test status
Simulation time 2161425857 ps
CPU time 7.86 seconds
Started Jun 23 05:09:48 PM PDT 24
Finished Jun 23 05:09:56 PM PDT 24
Peak memory 218604 kb
Host smart-b37e0194-7412-4be5-9ea4-a7e1177bc236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651460636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2651460636
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3292090969
Short name T300
Test name
Test status
Simulation time 243941600 ps
CPU time 1.15 seconds
Started Jun 23 05:09:44 PM PDT 24
Finished Jun 23 05:09:46 PM PDT 24
Peak memory 218132 kb
Host smart-452b4253-73f9-408c-8b70-cc83d056fc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292090969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3292090969
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.1613189249
Short name T286
Test name
Test status
Simulation time 215197919 ps
CPU time 0.89 seconds
Started Jun 23 05:09:43 PM PDT 24
Finished Jun 23 05:09:44 PM PDT 24
Peak memory 200584 kb
Host smart-8e71c89e-4962-45e0-9395-a6040e0ed8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613189249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1613189249
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1850066618
Short name T331
Test name
Test status
Simulation time 750579955 ps
CPU time 3.71 seconds
Started Jun 23 05:09:47 PM PDT 24
Finished Jun 23 05:09:51 PM PDT 24
Peak memory 200988 kb
Host smart-eb2e2b25-61f6-4c30-bc55-032bcec4811c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850066618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1850066618
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1056574704
Short name T236
Test name
Test status
Simulation time 103282568 ps
CPU time 1.02 seconds
Started Jun 23 05:09:45 PM PDT 24
Finished Jun 23 05:09:47 PM PDT 24
Peak memory 200736 kb
Host smart-72dc0797-d152-414f-b306-574dd86fcd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056574704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1056574704
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.874499184
Short name T402
Test name
Test status
Simulation time 122705955 ps
CPU time 1.2 seconds
Started Jun 23 05:09:41 PM PDT 24
Finished Jun 23 05:09:43 PM PDT 24
Peak memory 200832 kb
Host smart-0841cde1-21e1-47fc-91b9-4636d7004ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874499184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.874499184
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.727049637
Short name T537
Test name
Test status
Simulation time 210788407 ps
CPU time 1.22 seconds
Started Jun 23 05:09:43 PM PDT 24
Finished Jun 23 05:09:45 PM PDT 24
Peak memory 200748 kb
Host smart-37b59155-3471-4ed6-b9ed-c8a8fa637464
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727049637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.727049637
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1246857770
Short name T439
Test name
Test status
Simulation time 363441852 ps
CPU time 2.33 seconds
Started Jun 23 05:09:48 PM PDT 24
Finished Jun 23 05:09:51 PM PDT 24
Peak memory 200752 kb
Host smart-69bbb61d-0454-4082-ba5d-7f2305a1952a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246857770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1246857770
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1690878923
Short name T198
Test name
Test status
Simulation time 224208898 ps
CPU time 1.34 seconds
Started Jun 23 05:09:47 PM PDT 24
Finished Jun 23 05:09:49 PM PDT 24
Peak memory 200688 kb
Host smart-d94b4aed-caa8-4d27-baaf-82d9015d64af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690878923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1690878923
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1642241795
Short name T135
Test name
Test status
Simulation time 91365534 ps
CPU time 0.85 seconds
Started Jun 23 05:09:44 PM PDT 24
Finished Jun 23 05:09:45 PM PDT 24
Peak memory 200512 kb
Host smart-9e4532a2-0949-41f4-830a-48b76b025fdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642241795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1642241795
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2179882806
Short name T32
Test name
Test status
Simulation time 1891797653 ps
CPU time 7.01 seconds
Started Jun 23 05:09:44 PM PDT 24
Finished Jun 23 05:09:52 PM PDT 24
Peak memory 218472 kb
Host smart-847d5382-7e85-4045-b3b1-ae0889017ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179882806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2179882806
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2631670092
Short name T134
Test name
Test status
Simulation time 255904116 ps
CPU time 1.05 seconds
Started Jun 23 05:09:44 PM PDT 24
Finished Jun 23 05:09:46 PM PDT 24
Peak memory 218132 kb
Host smart-fb7ab89e-592b-440f-a864-4c6150a4f2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631670092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2631670092
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.1934242549
Short name T16
Test name
Test status
Simulation time 109658019 ps
CPU time 0.77 seconds
Started Jun 23 05:09:46 PM PDT 24
Finished Jun 23 05:09:48 PM PDT 24
Peak memory 200568 kb
Host smart-4967934b-dab1-4b5d-b6e6-45a25a60a253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934242549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1934242549
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.647965689
Short name T247
Test name
Test status
Simulation time 967294910 ps
CPU time 5.01 seconds
Started Jun 23 05:09:49 PM PDT 24
Finished Jun 23 05:09:54 PM PDT 24
Peak memory 200868 kb
Host smart-47b55a2e-6247-40d2-ac34-6a357510c2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647965689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.647965689
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3104571287
Short name T270
Test name
Test status
Simulation time 166571214 ps
CPU time 1.27 seconds
Started Jun 23 05:09:46 PM PDT 24
Finished Jun 23 05:09:48 PM PDT 24
Peak memory 200788 kb
Host smart-4cb32b6d-34c0-40da-b907-cab59b0ca757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104571287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3104571287
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.493469799
Short name T162
Test name
Test status
Simulation time 126651617 ps
CPU time 1.24 seconds
Started Jun 23 05:09:49 PM PDT 24
Finished Jun 23 05:09:50 PM PDT 24
Peak memory 200980 kb
Host smart-361d64c4-da27-469e-8b90-fb4e97a4d0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493469799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.493469799
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3600994131
Short name T91
Test name
Test status
Simulation time 8066628617 ps
CPU time 30.28 seconds
Started Jun 23 05:09:47 PM PDT 24
Finished Jun 23 05:10:18 PM PDT 24
Peak memory 209208 kb
Host smart-09172571-6ab2-48d0-ab01-17e030173244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600994131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3600994131
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1695786192
Short name T452
Test name
Test status
Simulation time 380200572 ps
CPU time 2.4 seconds
Started Jun 23 05:09:50 PM PDT 24
Finished Jun 23 05:09:53 PM PDT 24
Peak memory 200752 kb
Host smart-fb64f1d4-0dec-4563-ae04-9de2f528dd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695786192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1695786192
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.313642472
Short name T376
Test name
Test status
Simulation time 70023760 ps
CPU time 0.77 seconds
Started Jun 23 05:09:44 PM PDT 24
Finished Jun 23 05:09:46 PM PDT 24
Peak memory 200752 kb
Host smart-4524d039-94ee-484a-888a-ef5e4279e6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313642472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.313642472
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.404179118
Short name T60
Test name
Test status
Simulation time 75910418 ps
CPU time 0.79 seconds
Started Jun 23 05:09:51 PM PDT 24
Finished Jun 23 05:09:53 PM PDT 24
Peak memory 200548 kb
Host smart-9cf72cfc-2692-4cd5-8500-1e6773811029
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404179118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.404179118
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.3075501558
Short name T476
Test name
Test status
Simulation time 2172877775 ps
CPU time 8.1 seconds
Started Jun 23 05:09:52 PM PDT 24
Finished Jun 23 05:10:00 PM PDT 24
Peak memory 222584 kb
Host smart-7ec1be3a-36e9-4097-a62a-70d7fd857edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075501558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.3075501558
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3615639682
Short name T460
Test name
Test status
Simulation time 244833093 ps
CPU time 1.03 seconds
Started Jun 23 05:09:49 PM PDT 24
Finished Jun 23 05:09:50 PM PDT 24
Peak memory 218132 kb
Host smart-ae4d0b00-adba-4bc0-b3b1-93d545a871df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615639682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3615639682
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.335901825
Short name T21
Test name
Test status
Simulation time 215916452 ps
CPU time 0.89 seconds
Started Jun 23 05:09:48 PM PDT 24
Finished Jun 23 05:09:49 PM PDT 24
Peak memory 200464 kb
Host smart-5e374255-0d52-4b3d-a84f-2eb0a32c7219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335901825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.335901825
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.4130822537
Short name T214
Test name
Test status
Simulation time 903490984 ps
CPU time 4.28 seconds
Started Jun 23 05:09:51 PM PDT 24
Finished Jun 23 05:09:56 PM PDT 24
Peak memory 200820 kb
Host smart-53e3315a-44df-4abb-8574-18ea2a1633a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130822537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.4130822537
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2551196655
Short name T51
Test name
Test status
Simulation time 162365447 ps
CPU time 1.12 seconds
Started Jun 23 05:09:49 PM PDT 24
Finished Jun 23 05:09:51 PM PDT 24
Peak memory 200732 kb
Host smart-f2dcd9f1-d64b-40cd-8dc2-5f86e6c55a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551196655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2551196655
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1926613395
Short name T388
Test name
Test status
Simulation time 205081186 ps
CPU time 1.38 seconds
Started Jun 23 05:09:48 PM PDT 24
Finished Jun 23 05:09:50 PM PDT 24
Peak memory 200844 kb
Host smart-74505df2-24c2-4a49-b052-79c252393936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926613395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1926613395
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3156211858
Short name T123
Test name
Test status
Simulation time 9068194769 ps
CPU time 35.42 seconds
Started Jun 23 05:09:48 PM PDT 24
Finished Jun 23 05:10:25 PM PDT 24
Peak memory 209184 kb
Host smart-1b480a2f-b97c-4cf0-9cf0-ae12584e3aaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156211858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3156211858
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1122452408
Short name T522
Test name
Test status
Simulation time 148285563 ps
CPU time 1.73 seconds
Started Jun 23 05:09:50 PM PDT 24
Finished Jun 23 05:09:54 PM PDT 24
Peak memory 200692 kb
Host smart-a303e03c-b39b-4a39-a394-cc1bbf574972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122452408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1122452408
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.869471165
Short name T147
Test name
Test status
Simulation time 157999162 ps
CPU time 1.24 seconds
Started Jun 23 05:09:49 PM PDT 24
Finished Jun 23 05:09:51 PM PDT 24
Peak memory 200700 kb
Host smart-e5c37ef5-0d9c-49e4-998a-19b18b19aa32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869471165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.869471165
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2658854760
Short name T343
Test name
Test status
Simulation time 82613515 ps
CPU time 0.79 seconds
Started Jun 23 05:09:57 PM PDT 24
Finished Jun 23 05:09:59 PM PDT 24
Peak memory 200556 kb
Host smart-4ce7800f-1976-4054-b84c-c74bc09b4c2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658854760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2658854760
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3737365587
Short name T56
Test name
Test status
Simulation time 2367971779 ps
CPU time 7.81 seconds
Started Jun 23 05:09:55 PM PDT 24
Finished Jun 23 05:10:03 PM PDT 24
Peak memory 222332 kb
Host smart-23ce3a56-08bd-4169-a603-4ddaf1b39d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737365587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3737365587
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1310666580
Short name T308
Test name
Test status
Simulation time 243534369 ps
CPU time 1.07 seconds
Started Jun 23 05:09:55 PM PDT 24
Finished Jun 23 05:09:57 PM PDT 24
Peak memory 218096 kb
Host smart-443f7429-60e6-49a1-9ec5-97cf50b769ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310666580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1310666580
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3548244656
Short name T329
Test name
Test status
Simulation time 95819393 ps
CPU time 0.78 seconds
Started Jun 23 05:09:49 PM PDT 24
Finished Jun 23 05:09:50 PM PDT 24
Peak memory 200560 kb
Host smart-bf3e1b3f-c3c0-4057-86f6-fc55afe4c4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548244656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3548244656
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.732178165
Short name T215
Test name
Test status
Simulation time 791288465 ps
CPU time 4.64 seconds
Started Jun 23 05:09:50 PM PDT 24
Finished Jun 23 05:09:56 PM PDT 24
Peak memory 200940 kb
Host smart-6753dea2-dc3e-4de6-bb32-046646e50bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732178165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.732178165
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3638622005
Short name T521
Test name
Test status
Simulation time 151816859 ps
CPU time 1.19 seconds
Started Jun 23 05:09:53 PM PDT 24
Finished Jun 23 05:09:54 PM PDT 24
Peak memory 200724 kb
Host smart-b8194932-6228-4994-80c1-c6cab5537153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638622005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3638622005
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.2279949726
Short name T389
Test name
Test status
Simulation time 202746851 ps
CPU time 1.34 seconds
Started Jun 23 05:09:50 PM PDT 24
Finished Jun 23 05:09:53 PM PDT 24
Peak memory 200948 kb
Host smart-bc955bc0-071c-4e68-8ff2-1a173757bb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279949726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2279949726
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.4175102624
Short name T327
Test name
Test status
Simulation time 2139883267 ps
CPU time 9.92 seconds
Started Jun 23 05:09:58 PM PDT 24
Finished Jun 23 05:10:08 PM PDT 24
Peak memory 217292 kb
Host smart-ab7c9271-ca97-4c6d-9927-0311e1c1891d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175102624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.4175102624
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.958222015
Short name T487
Test name
Test status
Simulation time 361329171 ps
CPU time 2.38 seconds
Started Jun 23 05:09:55 PM PDT 24
Finished Jun 23 05:09:58 PM PDT 24
Peak memory 200732 kb
Host smart-6bb0eff8-f3c0-452b-889c-56ab68266c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958222015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.958222015
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2539518770
Short name T145
Test name
Test status
Simulation time 102577072 ps
CPU time 0.91 seconds
Started Jun 23 05:09:49 PM PDT 24
Finished Jun 23 05:09:50 PM PDT 24
Peak memory 200716 kb
Host smart-49d08a7d-fc92-4fbd-ba3c-c7ffaa0684f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539518770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2539518770
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1062676657
Short name T160
Test name
Test status
Simulation time 64730416 ps
CPU time 0.8 seconds
Started Jun 23 05:09:56 PM PDT 24
Finished Jun 23 05:09:57 PM PDT 24
Peak memory 200548 kb
Host smart-3cf8ee28-28da-44e4-b759-413e52b8203f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062676657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1062676657
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1126127038
Short name T387
Test name
Test status
Simulation time 1896161158 ps
CPU time 8.19 seconds
Started Jun 23 05:09:56 PM PDT 24
Finished Jun 23 05:10:05 PM PDT 24
Peak memory 222392 kb
Host smart-6a74238f-83e7-4a1c-9e6f-9d80f5569150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126127038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1126127038
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.246887386
Short name T186
Test name
Test status
Simulation time 244279360 ps
CPU time 1.18 seconds
Started Jun 23 05:09:57 PM PDT 24
Finished Jun 23 05:09:59 PM PDT 24
Peak memory 218284 kb
Host smart-3fa46a48-330a-42d0-b5cf-32513130b5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246887386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.246887386
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.1916959074
Short name T424
Test name
Test status
Simulation time 177746885 ps
CPU time 0.89 seconds
Started Jun 23 05:09:59 PM PDT 24
Finished Jun 23 05:10:00 PM PDT 24
Peak memory 200584 kb
Host smart-11692763-9d9c-4f2e-a0ad-bd6c19cdaab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916959074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1916959074
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1921005445
Short name T102
Test name
Test status
Simulation time 1066130959 ps
CPU time 4.99 seconds
Started Jun 23 05:09:58 PM PDT 24
Finished Jun 23 05:10:03 PM PDT 24
Peak memory 200896 kb
Host smart-cb10bf55-7f9b-4db7-bd3a-74d9b0139227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921005445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1921005445
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.390662864
Short name T277
Test name
Test status
Simulation time 101819713 ps
CPU time 1.01 seconds
Started Jun 23 05:09:59 PM PDT 24
Finished Jun 23 05:10:01 PM PDT 24
Peak memory 200708 kb
Host smart-a4f3ff3b-4df8-452c-9270-2245647198d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390662864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.390662864
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.3941813143
Short name T165
Test name
Test status
Simulation time 120192761 ps
CPU time 1.14 seconds
Started Jun 23 05:09:55 PM PDT 24
Finished Jun 23 05:09:57 PM PDT 24
Peak memory 200952 kb
Host smart-9df3149f-42ef-4138-b549-7c36e61ed9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941813143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3941813143
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.3676098471
Short name T403
Test name
Test status
Simulation time 4982871527 ps
CPU time 21.93 seconds
Started Jun 23 05:09:57 PM PDT 24
Finished Jun 23 05:10:20 PM PDT 24
Peak memory 209352 kb
Host smart-fc9341ed-3877-4021-bf2d-cb76c8aa15f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676098471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3676098471
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.376335384
Short name T265
Test name
Test status
Simulation time 336321002 ps
CPU time 2.11 seconds
Started Jun 23 05:10:07 PM PDT 24
Finished Jun 23 05:10:09 PM PDT 24
Peak memory 200672 kb
Host smart-1c3491ac-dc2d-4b17-acd8-70906f0b7b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376335384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.376335384
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.244282717
Short name T202
Test name
Test status
Simulation time 86370239 ps
CPU time 0.91 seconds
Started Jun 23 05:09:59 PM PDT 24
Finished Jun 23 05:10:00 PM PDT 24
Peak memory 200756 kb
Host smart-0ffbe6dd-d02c-4824-92c8-9c6bf5b7d984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244282717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.244282717
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.482491999
Short name T435
Test name
Test status
Simulation time 66705262 ps
CPU time 0.76 seconds
Started Jun 23 05:09:59 PM PDT 24
Finished Jun 23 05:10:00 PM PDT 24
Peak memory 200568 kb
Host smart-00d9e076-c61d-4fc3-aef9-7cbf9803b69f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482491999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.482491999
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.171331397
Short name T44
Test name
Test status
Simulation time 1218496911 ps
CPU time 6.11 seconds
Started Jun 23 05:09:59 PM PDT 24
Finished Jun 23 05:10:06 PM PDT 24
Peak memory 217456 kb
Host smart-0f5b5020-1005-4f9d-965a-566e5268ecc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171331397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.171331397
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2170447463
Short name T137
Test name
Test status
Simulation time 244825395 ps
CPU time 1.11 seconds
Started Jun 23 05:09:55 PM PDT 24
Finished Jun 23 05:09:57 PM PDT 24
Peak memory 218064 kb
Host smart-dade4e36-3d66-42fa-bd88-9285d1ca9d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170447463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2170447463
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1865311466
Short name T4
Test name
Test status
Simulation time 176032501 ps
CPU time 0.87 seconds
Started Jun 23 05:09:57 PM PDT 24
Finished Jun 23 05:09:59 PM PDT 24
Peak memory 200564 kb
Host smart-3b0ce013-6793-490f-bdaa-dc58e182bd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865311466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1865311466
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.4206502054
Short name T309
Test name
Test status
Simulation time 892254846 ps
CPU time 4.5 seconds
Started Jun 23 05:10:00 PM PDT 24
Finished Jun 23 05:10:05 PM PDT 24
Peak memory 200952 kb
Host smart-9fb16d73-1925-483c-8842-680fcaeaf2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206502054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.4206502054
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2180274755
Short name T166
Test name
Test status
Simulation time 110580431 ps
CPU time 1.05 seconds
Started Jun 23 05:09:59 PM PDT 24
Finished Jun 23 05:10:01 PM PDT 24
Peak memory 200736 kb
Host smart-fd3fd8ae-35fb-456d-812b-8a1d8800fff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180274755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2180274755
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.389382900
Short name T524
Test name
Test status
Simulation time 113200726 ps
CPU time 1.18 seconds
Started Jun 23 05:09:56 PM PDT 24
Finished Jun 23 05:09:57 PM PDT 24
Peak memory 200884 kb
Host smart-e202d7af-d475-4d9d-b080-bbf896a659ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389382900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.389382900
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3897551068
Short name T163
Test name
Test status
Simulation time 4822976090 ps
CPU time 21.32 seconds
Started Jun 23 05:10:02 PM PDT 24
Finished Jun 23 05:10:24 PM PDT 24
Peak memory 209188 kb
Host smart-de5c219d-2488-4912-8d9c-8ebe839ba4f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897551068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3897551068
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2888218243
Short name T37
Test name
Test status
Simulation time 433235114 ps
CPU time 2.61 seconds
Started Jun 23 05:09:57 PM PDT 24
Finished Jun 23 05:10:01 PM PDT 24
Peak memory 200748 kb
Host smart-a11aeb60-f8eb-4af5-95db-7d532228004b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888218243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2888218243
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2167597384
Short name T85
Test name
Test status
Simulation time 160612255 ps
CPU time 1.31 seconds
Started Jun 23 05:10:02 PM PDT 24
Finished Jun 23 05:10:04 PM PDT 24
Peak memory 200944 kb
Host smart-f647e9b2-dfa4-4c4b-8567-7258d95f4d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167597384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2167597384
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2380612917
Short name T9
Test name
Test status
Simulation time 64407149 ps
CPU time 0.83 seconds
Started Jun 23 05:09:57 PM PDT 24
Finished Jun 23 05:09:59 PM PDT 24
Peak memory 200472 kb
Host smart-8ec2147c-3d3b-4b22-873c-fa9e73b335cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380612917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2380612917
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.4265481012
Short name T47
Test name
Test status
Simulation time 2186637957 ps
CPU time 7.6 seconds
Started Jun 23 05:09:59 PM PDT 24
Finished Jun 23 05:10:07 PM PDT 24
Peak memory 218244 kb
Host smart-d325aa9b-04a5-4c3d-90f8-d803d490e00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265481012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.4265481012
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1834761935
Short name T437
Test name
Test status
Simulation time 244940007 ps
CPU time 1.02 seconds
Started Jun 23 05:09:57 PM PDT 24
Finished Jun 23 05:09:58 PM PDT 24
Peak memory 218140 kb
Host smart-2ef224cd-b2fa-4587-9827-bf0ab1ff71c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834761935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1834761935
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.3483528708
Short name T498
Test name
Test status
Simulation time 187532142 ps
CPU time 0.85 seconds
Started Jun 23 05:09:57 PM PDT 24
Finished Jun 23 05:09:59 PM PDT 24
Peak memory 200536 kb
Host smart-bcc4867e-11ec-42e9-9cff-01305de8cb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483528708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3483528708
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.1881041680
Short name T5
Test name
Test status
Simulation time 991908546 ps
CPU time 5.12 seconds
Started Jun 23 05:09:57 PM PDT 24
Finished Jun 23 05:10:03 PM PDT 24
Peak memory 200984 kb
Host smart-9fdca0cc-7572-4132-a992-db2d0b94308b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881041680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1881041680
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2880111739
Short name T201
Test name
Test status
Simulation time 101695224 ps
CPU time 0.94 seconds
Started Jun 23 05:09:59 PM PDT 24
Finished Jun 23 05:10:01 PM PDT 24
Peak memory 200756 kb
Host smart-7dadfc1a-58ac-4249-b59c-d269801c0499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880111739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2880111739
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.20316017
Short name T531
Test name
Test status
Simulation time 260945669 ps
CPU time 1.49 seconds
Started Jun 23 05:09:57 PM PDT 24
Finished Jun 23 05:09:59 PM PDT 24
Peak memory 200852 kb
Host smart-c4837eeb-665f-40a4-91a6-0964310a1302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20316017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.20316017
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.4241155959
Short name T383
Test name
Test status
Simulation time 17590631404 ps
CPU time 60.27 seconds
Started Jun 23 05:10:00 PM PDT 24
Finished Jun 23 05:11:00 PM PDT 24
Peak memory 209224 kb
Host smart-5391afaf-5531-42f7-bd29-a957669afe6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241155959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.4241155959
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.1679792400
Short name T209
Test name
Test status
Simulation time 118950562 ps
CPU time 1.66 seconds
Started Jun 23 05:10:00 PM PDT 24
Finished Jun 23 05:10:02 PM PDT 24
Peak memory 200676 kb
Host smart-7cca34fc-b7ad-408d-b0bf-198a573b5cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679792400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1679792400
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3436097907
Short name T293
Test name
Test status
Simulation time 160281785 ps
CPU time 1.32 seconds
Started Jun 23 05:09:56 PM PDT 24
Finished Jun 23 05:09:58 PM PDT 24
Peak memory 200956 kb
Host smart-ec8dcde9-fe3b-45c1-8f6d-7f354ad41794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436097907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3436097907
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2667644502
Short name T292
Test name
Test status
Simulation time 77735352 ps
CPU time 0.82 seconds
Started Jun 23 05:07:44 PM PDT 24
Finished Jun 23 05:07:46 PM PDT 24
Peak memory 200476 kb
Host smart-d29d5ae4-a059-4953-b9ac-f6dec514d000
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667644502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2667644502
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2795837045
Short name T36
Test name
Test status
Simulation time 1214166797 ps
CPU time 5.55 seconds
Started Jun 23 05:07:40 PM PDT 24
Finished Jun 23 05:07:47 PM PDT 24
Peak memory 218560 kb
Host smart-a383fdd5-d98d-4707-8ccc-9180cfd6da7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795837045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2795837045
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2227721535
Short name T180
Test name
Test status
Simulation time 245570262 ps
CPU time 1.01 seconds
Started Jun 23 05:07:39 PM PDT 24
Finished Jun 23 05:07:41 PM PDT 24
Peak memory 218052 kb
Host smart-e91595cd-e0d7-4ac1-b0b5-1c53605f976f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227721535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2227721535
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1560822023
Short name T518
Test name
Test status
Simulation time 135903222 ps
CPU time 0.84 seconds
Started Jun 23 05:07:38 PM PDT 24
Finished Jun 23 05:07:40 PM PDT 24
Peak memory 200564 kb
Host smart-90fe92a8-2fa4-4f37-be99-4936928c6f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560822023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1560822023
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.3720381739
Short name T341
Test name
Test status
Simulation time 725736811 ps
CPU time 4.14 seconds
Started Jun 23 05:07:38 PM PDT 24
Finished Jun 23 05:07:43 PM PDT 24
Peak memory 200940 kb
Host smart-0b77149e-96f3-4758-be97-e51498d8d354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720381739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3720381739
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.876737465
Short name T348
Test name
Test status
Simulation time 98857773 ps
CPU time 1 seconds
Started Jun 23 05:07:38 PM PDT 24
Finished Jun 23 05:07:40 PM PDT 24
Peak memory 200660 kb
Host smart-6aac679e-7a3e-48b0-9b54-e91bf69e3174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876737465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.876737465
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2135675855
Short name T326
Test name
Test status
Simulation time 261734506 ps
CPU time 1.55 seconds
Started Jun 23 05:07:38 PM PDT 24
Finished Jun 23 05:07:40 PM PDT 24
Peak memory 200868 kb
Host smart-12503687-c022-43b2-bc05-6cf67e1deef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135675855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2135675855
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3456573093
Short name T465
Test name
Test status
Simulation time 9706558616 ps
CPU time 35.53 seconds
Started Jun 23 05:07:43 PM PDT 24
Finished Jun 23 05:08:20 PM PDT 24
Peak memory 200932 kb
Host smart-bd8a5bea-aced-4895-adf1-6daa2f71ff92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456573093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3456573093
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.2083581901
Short name T373
Test name
Test status
Simulation time 126073356 ps
CPU time 1.53 seconds
Started Jun 23 05:07:39 PM PDT 24
Finished Jun 23 05:07:41 PM PDT 24
Peak memory 200956 kb
Host smart-4f59a9a5-a645-4479-8924-ba8754357db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083581901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.2083581901
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.3661551486
Short name T368
Test name
Test status
Simulation time 136490373 ps
CPU time 1.08 seconds
Started Jun 23 05:07:41 PM PDT 24
Finished Jun 23 05:07:43 PM PDT 24
Peak memory 200752 kb
Host smart-16cd4cc1-9831-4485-8ade-cb19ba2bc225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661551486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3661551486
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3434950548
Short name T374
Test name
Test status
Simulation time 68900409 ps
CPU time 0.79 seconds
Started Jun 23 05:07:47 PM PDT 24
Finished Jun 23 05:07:48 PM PDT 24
Peak memory 200476 kb
Host smart-a1b198a6-0c3e-494c-be8c-1540aeacd20d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434950548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3434950548
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.580979528
Short name T304
Test name
Test status
Simulation time 1889665872 ps
CPU time 7.69 seconds
Started Jun 23 05:07:43 PM PDT 24
Finished Jun 23 05:07:52 PM PDT 24
Peak memory 218488 kb
Host smart-ac9eb499-7ac5-49c4-a933-7760f3f899fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580979528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.580979528
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3155443683
Short name T63
Test name
Test status
Simulation time 245080040 ps
CPU time 1.03 seconds
Started Jun 23 05:07:42 PM PDT 24
Finished Jun 23 05:07:43 PM PDT 24
Peak memory 218012 kb
Host smart-4a93cffe-a4db-4c58-b3d9-2d24c3c2e6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155443683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3155443683
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3975632592
Short name T375
Test name
Test status
Simulation time 207948238 ps
CPU time 0.97 seconds
Started Jun 23 05:07:44 PM PDT 24
Finished Jun 23 05:07:46 PM PDT 24
Peak memory 200564 kb
Host smart-226456cd-e702-4c4b-a542-970b45a2518f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975632592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3975632592
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.495969717
Short name T275
Test name
Test status
Simulation time 1421216474 ps
CPU time 5.05 seconds
Started Jun 23 05:07:44 PM PDT 24
Finished Jun 23 05:07:50 PM PDT 24
Peak memory 200956 kb
Host smart-72a15ec7-cde8-4add-a6da-017af987dead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495969717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.495969717
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.556828877
Short name T299
Test name
Test status
Simulation time 112775850 ps
CPU time 1.01 seconds
Started Jun 23 05:07:53 PM PDT 24
Finished Jun 23 05:07:55 PM PDT 24
Peak memory 200652 kb
Host smart-fe03701d-74f8-4100-9288-6d8d49364a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556828877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.556828877
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1618447000
Short name T358
Test name
Test status
Simulation time 193413865 ps
CPU time 1.35 seconds
Started Jun 23 05:07:53 PM PDT 24
Finished Jun 23 05:07:55 PM PDT 24
Peak memory 200812 kb
Host smart-695849db-0097-4a4c-aa15-28b9412fc149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618447000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1618447000
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.2251834177
Short name T333
Test name
Test status
Simulation time 7146120469 ps
CPU time 23.69 seconds
Started Jun 23 05:07:43 PM PDT 24
Finished Jun 23 05:08:07 PM PDT 24
Peak memory 209156 kb
Host smart-158ff3cb-4de8-4b7a-80e5-e6a5ac0de5db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251834177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2251834177
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1937789868
Short name T448
Test name
Test status
Simulation time 112573843 ps
CPU time 1.4 seconds
Started Jun 23 05:07:42 PM PDT 24
Finished Jun 23 05:07:45 PM PDT 24
Peak memory 200736 kb
Host smart-b47fc90c-76a6-4a01-9e60-2be7af372b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937789868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1937789868
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3673106624
Short name T499
Test name
Test status
Simulation time 112205697 ps
CPU time 0.98 seconds
Started Jun 23 05:07:44 PM PDT 24
Finished Jun 23 05:07:47 PM PDT 24
Peak memory 200700 kb
Host smart-37bcd084-d12f-49e5-84ad-27e889d9f4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673106624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3673106624
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1110271193
Short name T40
Test name
Test status
Simulation time 184275674 ps
CPU time 0.94 seconds
Started Jun 23 05:07:51 PM PDT 24
Finished Jun 23 05:07:54 PM PDT 24
Peak memory 200492 kb
Host smart-5b71d5f7-e02d-4667-8af9-70f69d1a4d38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110271193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1110271193
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2846834131
Short name T29
Test name
Test status
Simulation time 2355426826 ps
CPU time 8.97 seconds
Started Jun 23 05:07:51 PM PDT 24
Finished Jun 23 05:08:01 PM PDT 24
Peak memory 218512 kb
Host smart-111630a5-0692-4ddf-93ba-3b930afecbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846834131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2846834131
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1849208232
Short name T386
Test name
Test status
Simulation time 244068891 ps
CPU time 1.12 seconds
Started Jun 23 05:07:48 PM PDT 24
Finished Jun 23 05:07:50 PM PDT 24
Peak memory 218148 kb
Host smart-03c05fae-2313-41c8-a102-9c033f02639b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849208232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1849208232
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1908818479
Short name T258
Test name
Test status
Simulation time 206648599 ps
CPU time 0.93 seconds
Started Jun 23 05:07:43 PM PDT 24
Finished Jun 23 05:07:45 PM PDT 24
Peak memory 200496 kb
Host smart-6c731f28-2d3b-4188-8171-f431bbd2ae37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908818479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1908818479
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.491461999
Short name T8
Test name
Test status
Simulation time 748247992 ps
CPU time 4.18 seconds
Started Jun 23 05:07:43 PM PDT 24
Finished Jun 23 05:07:49 PM PDT 24
Peak memory 200932 kb
Host smart-d4c886f6-229b-4130-95ab-8a17ee5e5e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491461999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.491461999
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1246304173
Short name T64
Test name
Test status
Simulation time 145320699 ps
CPU time 1.08 seconds
Started Jun 23 05:07:49 PM PDT 24
Finished Jun 23 05:07:51 PM PDT 24
Peak memory 200744 kb
Host smart-2fdc52ba-9e29-4aa5-83d2-9bffa2c5b2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246304173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1246304173
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2508891918
Short name T497
Test name
Test status
Simulation time 192111560 ps
CPU time 1.35 seconds
Started Jun 23 05:07:44 PM PDT 24
Finished Jun 23 05:07:46 PM PDT 24
Peak memory 200872 kb
Host smart-a328252b-bcb5-4f73-939a-efa488333986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508891918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2508891918
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2255353126
Short name T496
Test name
Test status
Simulation time 7500849044 ps
CPU time 33.18 seconds
Started Jun 23 05:07:50 PM PDT 24
Finished Jun 23 05:08:25 PM PDT 24
Peak memory 210760 kb
Host smart-bf1f81ca-56f4-4544-9568-ae775b609df9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255353126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2255353126
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3994438765
Short name T370
Test name
Test status
Simulation time 386283739 ps
CPU time 2.06 seconds
Started Jun 23 05:07:43 PM PDT 24
Finished Jun 23 05:07:47 PM PDT 24
Peak memory 200672 kb
Host smart-72f305ad-320b-4f2d-b5f1-1647dfe727f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994438765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3994438765
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.525678138
Short name T239
Test name
Test status
Simulation time 97747375 ps
CPU time 0.83 seconds
Started Jun 23 05:07:42 PM PDT 24
Finished Jun 23 05:07:44 PM PDT 24
Peak memory 200744 kb
Host smart-ba21d80f-3f51-489b-b598-959d7f4aae70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525678138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.525678138
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2262459769
Short name T81
Test name
Test status
Simulation time 64858812 ps
CPU time 0.8 seconds
Started Jun 23 05:07:58 PM PDT 24
Finished Jun 23 05:08:00 PM PDT 24
Peak memory 200532 kb
Host smart-12b1428c-3b77-47fa-bba8-49856622bee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262459769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2262459769
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2900941876
Short name T28
Test name
Test status
Simulation time 1894712466 ps
CPU time 6.9 seconds
Started Jun 23 05:07:53 PM PDT 24
Finished Jun 23 05:08:01 PM PDT 24
Peak memory 218000 kb
Host smart-3c210ce9-0d4f-48a6-b5d1-f0f73800f74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900941876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2900941876
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1919633187
Short name T432
Test name
Test status
Simulation time 246316616 ps
CPU time 1.03 seconds
Started Jun 23 05:07:52 PM PDT 24
Finished Jun 23 05:07:54 PM PDT 24
Peak memory 218068 kb
Host smart-058d3ce9-50cc-48c7-b548-94b6cd115683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919633187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1919633187
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3822706938
Short name T22
Test name
Test status
Simulation time 173491077 ps
CPU time 0.89 seconds
Started Jun 23 05:07:49 PM PDT 24
Finished Jun 23 05:07:50 PM PDT 24
Peak memory 200488 kb
Host smart-06749a55-2750-4569-b4bc-550853dc8908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822706938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3822706938
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3558475525
Short name T141
Test name
Test status
Simulation time 976704078 ps
CPU time 4.98 seconds
Started Jun 23 05:07:50 PM PDT 24
Finished Jun 23 05:07:57 PM PDT 24
Peak memory 200940 kb
Host smart-fd2fe3c1-aed0-45b2-95c6-99c002f3b4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558475525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3558475525
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3493197252
Short name T281
Test name
Test status
Simulation time 103664476 ps
CPU time 1 seconds
Started Jun 23 05:07:50 PM PDT 24
Finished Jun 23 05:07:53 PM PDT 24
Peak memory 200696 kb
Host smart-165c3422-e399-49ef-baf3-8741cb7aa010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493197252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3493197252
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3325203621
Short name T396
Test name
Test status
Simulation time 239702244 ps
CPU time 1.4 seconds
Started Jun 23 05:07:49 PM PDT 24
Finished Jun 23 05:07:52 PM PDT 24
Peak memory 200940 kb
Host smart-2d1465e0-ff12-449d-ad8d-8b01392109a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325203621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3325203621
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.4122227966
Short name T216
Test name
Test status
Simulation time 16117748520 ps
CPU time 59.39 seconds
Started Jun 23 05:07:57 PM PDT 24
Finished Jun 23 05:08:58 PM PDT 24
Peak memory 209180 kb
Host smart-bbaa68c4-c407-452e-bbea-f4e09e093e01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122227966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.4122227966
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3570967829
Short name T50
Test name
Test status
Simulation time 249079058 ps
CPU time 1.8 seconds
Started Jun 23 05:07:48 PM PDT 24
Finished Jun 23 05:07:50 PM PDT 24
Peak memory 200672 kb
Host smart-2b7a9230-d0c4-4b77-bf6a-f0615c13322a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570967829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3570967829
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1405275502
Short name T397
Test name
Test status
Simulation time 123291190 ps
CPU time 0.99 seconds
Started Jun 23 05:07:50 PM PDT 24
Finished Jun 23 05:07:52 PM PDT 24
Peak memory 200908 kb
Host smart-e129f4b8-4e82-42ee-948a-6a355fe18eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405275502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1405275502
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2014992492
Short name T391
Test name
Test status
Simulation time 79161545 ps
CPU time 0.79 seconds
Started Jun 23 05:07:56 PM PDT 24
Finished Jun 23 05:07:58 PM PDT 24
Peak memory 200532 kb
Host smart-ac7de1fa-adb7-45d1-bae7-930d65f3f3c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014992492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2014992492
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1032780368
Short name T48
Test name
Test status
Simulation time 1226997185 ps
CPU time 5.87 seconds
Started Jun 23 05:08:03 PM PDT 24
Finished Jun 23 05:08:10 PM PDT 24
Peak memory 218112 kb
Host smart-f6c905ea-6a3d-4951-9506-b9fc099ce39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032780368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1032780368
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3523604706
Short name T196
Test name
Test status
Simulation time 243949655 ps
CPU time 1.05 seconds
Started Jun 23 05:07:56 PM PDT 24
Finished Jun 23 05:07:57 PM PDT 24
Peak memory 218072 kb
Host smart-902a7812-274c-4175-b416-4250a00f1fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523604706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3523604706
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3044911726
Short name T413
Test name
Test status
Simulation time 92369648 ps
CPU time 0.78 seconds
Started Jun 23 05:08:03 PM PDT 24
Finished Jun 23 05:08:05 PM PDT 24
Peak memory 200580 kb
Host smart-965c9a6d-d59c-4257-96eb-e10aaeea0265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044911726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3044911726
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.1785677958
Short name T191
Test name
Test status
Simulation time 628413380 ps
CPU time 3.34 seconds
Started Jun 23 05:07:56 PM PDT 24
Finished Jun 23 05:08:00 PM PDT 24
Peak memory 200956 kb
Host smart-46fcbdad-5a25-434f-87a4-fdd3f5053466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785677958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1785677958
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.678246958
Short name T233
Test name
Test status
Simulation time 108234423 ps
CPU time 0.97 seconds
Started Jun 23 05:07:56 PM PDT 24
Finished Jun 23 05:07:57 PM PDT 24
Peak memory 200656 kb
Host smart-9a0d2a76-17df-47b0-bc0f-d52d06aee083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678246958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.678246958
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.3051951949
Short name T274
Test name
Test status
Simulation time 111690133 ps
CPU time 1.12 seconds
Started Jun 23 05:07:56 PM PDT 24
Finished Jun 23 05:07:58 PM PDT 24
Peak memory 200952 kb
Host smart-30910799-7c86-4918-b404-b8eb9796f69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051951949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3051951949
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1065195758
Short name T80
Test name
Test status
Simulation time 3781051457 ps
CPU time 14.66 seconds
Started Jun 23 05:07:56 PM PDT 24
Finished Jun 23 05:08:12 PM PDT 24
Peak memory 200908 kb
Host smart-21f45167-3cd8-48d9-97d0-2cffb5860cd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065195758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1065195758
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2737178511
Short name T352
Test name
Test status
Simulation time 123481181 ps
CPU time 1.68 seconds
Started Jun 23 05:07:56 PM PDT 24
Finished Jun 23 05:07:58 PM PDT 24
Peak memory 208924 kb
Host smart-f46e3d55-d5f0-4ee1-8504-407826f6a438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737178511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2737178511
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1686984207
Short name T484
Test name
Test status
Simulation time 153647823 ps
CPU time 1.22 seconds
Started Jun 23 05:07:57 PM PDT 24
Finished Jun 23 05:08:00 PM PDT 24
Peak memory 200724 kb
Host smart-22096500-8c19-4131-be64-36d0fb1c1f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686984207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1686984207
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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