Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7755

1

T1

1

T7

3

T8

12

auto[1]

10758

1

T1

1

T4

4

T7

1

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5695	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6267	1			T1	1		T2	1		T3	1
reset_info_cp[2]	2901	1			T4	1		T9	16		T10	11
reset_info_cp[4]	3754	1			T4	1		T9	16		T10	22
reset_info_cp[8]	111	1			T8	1		T9	1		T10	3
reset_info_cp[16]	100	1			T9	1		T44	1		T59	2
reset_info_cp[32]	99	1			T10	2		T12	1		T14	1
reset_info_cp[64]	100	1			T7	1		T8	2		T10	1
reset_info_cp[128]	106	1			T8	1		T44	1		T58	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2994	1			T9	19		T10	18		T42	19
reset_info_cp[1]	auto[1]	2653	1			T4	1		T9	7		T10	8
reset_info_cp[2]	auto[0]	905	1			T44	18		T58	14		T59	9
reset_info_cp[2]	auto[1]	1996	1			T4	1		T9	16		T10	11
reset_info_cp[4]	auto[0]	1317	1			T44	25		T58	34		T59	8
reset_info_cp[4]	auto[1]	2437	1			T4	1		T9	16		T10	22
reset_info_cp[8]	auto[0]	45	1			T8	1		T12	1		T58	1
reset_info_cp[8]	auto[1]	66	1			T9	1		T10	3		T42	1
reset_info_cp[16]	auto[0]	39	1			T44	1		T59	2		T94	1
reset_info_cp[16]	auto[1]	61	1			T9	1		T25	1		T30	1
reset_info_cp[32]	auto[0]	43	1			T12	1		T14	1		T44	1
reset_info_cp[32]	auto[1]	56	1			T10	2		T42	1		T58	2
reset_info_cp[64]	auto[0]	39	1			T7	1		T8	1		T63	3
reset_info_cp[64]	auto[1]	61	1			T8	1		T10	1		T42	1
reset_info_cp[128]	auto[0]	43	1			T8	1		T58	1		T98	1
reset_info_cp[128]	auto[1]	63	1			T44	1		T45	1		T34	1