Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.43 99.40 99.24 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T534 /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2336405720 Jun 24 05:35:02 PM PDT 24 Jun 24 05:35:06 PM PDT 24 148163747 ps
T535 /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.4214077749 Jun 24 05:35:48 PM PDT 24 Jun 24 05:35:51 PM PDT 24 99451950 ps
T536 /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3675814870 Jun 24 05:35:57 PM PDT 24 Jun 24 05:36:00 PM PDT 24 184243135 ps
T537 /workspace/coverage/default/39.rstmgr_stress_all.502821269 Jun 24 05:35:56 PM PDT 24 Jun 24 05:36:11 PM PDT 24 3381896860 ps
T538 /workspace/coverage/default/35.rstmgr_sw_rst.887205767 Jun 24 05:35:55 PM PDT 24 Jun 24 05:35:59 PM PDT 24 135986184 ps
T64 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.391525763 Jun 24 05:30:30 PM PDT 24 Jun 24 05:30:35 PM PDT 24 907406438 ps
T65 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3998793759 Jun 24 05:30:50 PM PDT 24 Jun 24 05:30:54 PM PDT 24 1088794426 ps
T66 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1196814207 Jun 24 05:30:41 PM PDT 24 Jun 24 05:30:45 PM PDT 24 79814673 ps
T67 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3495720993 Jun 24 05:30:53 PM PDT 24 Jun 24 05:30:59 PM PDT 24 465945056 ps
T68 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1569634977 Jun 24 05:30:40 PM PDT 24 Jun 24 05:30:44 PM PDT 24 162657241 ps
T102 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3092501538 Jun 24 05:30:43 PM PDT 24 Jun 24 05:30:47 PM PDT 24 93617020 ps
T539 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3919410022 Jun 24 05:30:46 PM PDT 24 Jun 24 05:30:49 PM PDT 24 99610080 ps
T69 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1563399570 Jun 24 05:30:28 PM PDT 24 Jun 24 05:30:31 PM PDT 24 106904360 ps
T540 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1476808641 Jun 24 05:30:46 PM PDT 24 Jun 24 05:30:54 PM PDT 24 488693874 ps
T70 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.352609510 Jun 24 05:30:30 PM PDT 24 Jun 24 05:30:34 PM PDT 24 793046846 ps
T103 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2387438131 Jun 24 05:30:52 PM PDT 24 Jun 24 05:30:54 PM PDT 24 84159501 ps
T83 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.4000222430 Jun 24 05:30:40 PM PDT 24 Jun 24 05:30:44 PM PDT 24 171530843 ps
T77 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2676826790 Jun 24 05:30:39 PM PDT 24 Jun 24 05:30:44 PM PDT 24 931415845 ps
T541 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2840350624 Jun 24 05:30:39 PM PDT 24 Jun 24 05:30:42 PM PDT 24 242695297 ps
T92 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.830354189 Jun 24 05:30:39 PM PDT 24 Jun 24 05:30:42 PM PDT 24 173987212 ps
T542 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.684977784 Jun 24 05:30:38 PM PDT 24 Jun 24 05:30:41 PM PDT 24 243023477 ps
T104 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2338742419 Jun 24 05:30:40 PM PDT 24 Jun 24 05:30:43 PM PDT 24 58531747 ps
T543 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.402623180 Jun 24 05:30:27 PM PDT 24 Jun 24 05:30:31 PM PDT 24 158072252 ps
T544 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2291897455 Jun 24 05:30:39 PM PDT 24 Jun 24 05:30:40 PM PDT 24 106622251 ps
T78 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.782633076 Jun 24 05:30:40 PM PDT 24 Jun 24 05:30:44 PM PDT 24 179239699 ps
T105 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1410607215 Jun 24 05:30:41 PM PDT 24 Jun 24 05:30:45 PM PDT 24 102398326 ps
T545 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3349082159 Jun 24 05:30:54 PM PDT 24 Jun 24 05:30:57 PM PDT 24 96412297 ps
T546 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.727079966 Jun 24 05:30:52 PM PDT 24 Jun 24 05:30:54 PM PDT 24 75146874 ps
T85 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.290483443 Jun 24 05:30:43 PM PDT 24 Jun 24 05:30:47 PM PDT 24 134957378 ps
T75 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1304590162 Jun 24 05:30:33 PM PDT 24 Jun 24 05:30:37 PM PDT 24 196564309 ps
T547 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3873926554 Jun 24 05:30:28 PM PDT 24 Jun 24 05:30:34 PM PDT 24 273324939 ps
T106 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1897191674 Jun 24 05:30:40 PM PDT 24 Jun 24 05:30:44 PM PDT 24 136190050 ps
T93 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3134329527 Jun 24 05:30:27 PM PDT 24 Jun 24 05:30:31 PM PDT 24 215399759 ps
T107 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2346265305 Jun 24 05:30:40 PM PDT 24 Jun 24 05:30:43 PM PDT 24 148250295 ps
T548 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1622707127 Jun 24 05:30:52 PM PDT 24 Jun 24 05:30:55 PM PDT 24 189773262 ps
T549 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2758396164 Jun 24 05:30:39 PM PDT 24 Jun 24 05:30:41 PM PDT 24 85624491 ps
T550 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2623367906 Jun 24 05:30:41 PM PDT 24 Jun 24 05:30:45 PM PDT 24 69120940 ps
T551 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2372505303 Jun 24 05:30:28 PM PDT 24 Jun 24 05:30:31 PM PDT 24 125773009 ps
T552 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1470840806 Jun 24 05:30:42 PM PDT 24 Jun 24 05:30:46 PM PDT 24 75202243 ps
T108 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.75802241 Jun 24 05:30:40 PM PDT 24 Jun 24 05:30:43 PM PDT 24 67455047 ps
T553 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.4005779252 Jun 24 05:30:43 PM PDT 24 Jun 24 05:30:49 PM PDT 24 800494974 ps
T84 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1061147251 Jun 24 05:30:46 PM PDT 24 Jun 24 05:30:51 PM PDT 24 188746329 ps
T554 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.914949227 Jun 24 05:30:45 PM PDT 24 Jun 24 05:30:49 PM PDT 24 188950477 ps
T109 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1874487765 Jun 24 05:30:44 PM PDT 24 Jun 24 05:30:49 PM PDT 24 203491700 ps
T555 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3357352096 Jun 24 05:30:40 PM PDT 24 Jun 24 05:30:44 PM PDT 24 201691948 ps
T556 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1056468839 Jun 24 05:30:24 PM PDT 24 Jun 24 05:30:27 PM PDT 24 262731965 ps
T110 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3708592615 Jun 24 05:30:27 PM PDT 24 Jun 24 05:30:31 PM PDT 24 87285333 ps
T557 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3699965959 Jun 24 05:30:42 PM PDT 24 Jun 24 05:30:47 PM PDT 24 363197683 ps
T76 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1447938691 Jun 24 05:30:40 PM PDT 24 Jun 24 05:30:46 PM PDT 24 535329828 ps
T558 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.575906095 Jun 24 05:30:39 PM PDT 24 Jun 24 05:30:41 PM PDT 24 116897595 ps
T559 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.39362018 Jun 24 05:30:37 PM PDT 24 Jun 24 05:30:38 PM PDT 24 84329215 ps
T560 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.850302493 Jun 24 05:30:43 PM PDT 24 Jun 24 05:30:48 PM PDT 24 209320100 ps
T561 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.614356178 Jun 24 05:30:39 PM PDT 24 Jun 24 05:30:41 PM PDT 24 75856746 ps
T562 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3610787782 Jun 24 05:30:40 PM PDT 24 Jun 24 05:30:48 PM PDT 24 1168664523 ps
T563 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2524771600 Jun 24 05:30:27 PM PDT 24 Jun 24 05:30:30 PM PDT 24 187077666 ps
T564 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.369297004 Jun 24 05:30:39 PM PDT 24 Jun 24 05:30:42 PM PDT 24 119289016 ps
T82 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1834100540 Jun 24 05:30:40 PM PDT 24 Jun 24 05:30:46 PM PDT 24 791795063 ps
T565 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.380541945 Jun 24 05:30:55 PM PDT 24 Jun 24 05:30:57 PM PDT 24 83648314 ps
T566 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3030471119 Jun 24 05:30:43 PM PDT 24 Jun 24 05:30:49 PM PDT 24 322988300 ps
T567 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2329088652 Jun 24 05:30:42 PM PDT 24 Jun 24 05:30:48 PM PDT 24 160566512 ps
T568 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2640577588 Jun 24 05:30:40 PM PDT 24 Jun 24 05:30:43 PM PDT 24 253581073 ps
T569 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2872154999 Jun 24 05:30:50 PM PDT 24 Jun 24 05:30:54 PM PDT 24 227041319 ps
T570 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.4117120150 Jun 24 05:30:29 PM PDT 24 Jun 24 05:30:32 PM PDT 24 55665426 ps
T571 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.593209381 Jun 24 05:30:50 PM PDT 24 Jun 24 05:30:52 PM PDT 24 142199084 ps
T572 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1488976934 Jun 24 05:30:57 PM PDT 24 Jun 24 05:31:00 PM PDT 24 194864310 ps
T573 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1406645103 Jun 24 05:30:41 PM PDT 24 Jun 24 05:30:45 PM PDT 24 110693096 ps
T574 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3883702297 Jun 24 05:30:53 PM PDT 24 Jun 24 05:30:56 PM PDT 24 196235489 ps
T575 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2781457003 Jun 24 05:30:41 PM PDT 24 Jun 24 05:30:44 PM PDT 24 71944292 ps
T576 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2376890862 Jun 24 05:30:52 PM PDT 24 Jun 24 05:30:54 PM PDT 24 70945088 ps
T577 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2290684719 Jun 24 05:30:51 PM PDT 24 Jun 24 05:30:53 PM PDT 24 183697515 ps
T79 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2960268840 Jun 24 05:30:38 PM PDT 24 Jun 24 05:30:41 PM PDT 24 468197613 ps
T578 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.738293415 Jun 24 05:30:42 PM PDT 24 Jun 24 05:30:46 PM PDT 24 71647132 ps
T579 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.4040287966 Jun 24 05:30:43 PM PDT 24 Jun 24 05:30:48 PM PDT 24 490993960 ps
T80 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.942044641 Jun 24 05:30:39 PM PDT 24 Jun 24 05:30:44 PM PDT 24 471113448 ps
T580 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.93423186 Jun 24 05:30:39 PM PDT 24 Jun 24 05:30:51 PM PDT 24 2308889136 ps
T581 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.769657062 Jun 24 05:30:29 PM PDT 24 Jun 24 05:30:37 PM PDT 24 480199487 ps
T582 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1687982106 Jun 24 05:30:50 PM PDT 24 Jun 24 05:30:53 PM PDT 24 278251323 ps
T583 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3506905840 Jun 24 05:30:40 PM PDT 24 Jun 24 05:30:44 PM PDT 24 104992208 ps
T584 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3684654451 Jun 24 05:30:27 PM PDT 24 Jun 24 05:30:30 PM PDT 24 70482396 ps
T81 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.199457281 Jun 24 05:30:52 PM PDT 24 Jun 24 05:30:56 PM PDT 24 792952026 ps
T585 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3238488505 Jun 24 05:30:28 PM PDT 24 Jun 24 05:30:32 PM PDT 24 166031091 ps
T586 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1067511407 Jun 24 05:30:41 PM PDT 24 Jun 24 05:30:46 PM PDT 24 153869890 ps
T587 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3442838623 Jun 24 05:30:44 PM PDT 24 Jun 24 05:30:48 PM PDT 24 102529395 ps
T588 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2362089431 Jun 24 05:30:40 PM PDT 24 Jun 24 05:30:45 PM PDT 24 250951124 ps
T589 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1508025628 Jun 24 05:30:28 PM PDT 24 Jun 24 05:30:31 PM PDT 24 95458096 ps
T590 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.370513514 Jun 24 05:30:44 PM PDT 24 Jun 24 05:30:48 PM PDT 24 176274565 ps
T591 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4080511545 Jun 24 05:30:43 PM PDT 24 Jun 24 05:30:47 PM PDT 24 205747983 ps
T592 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1873421288 Jun 24 05:30:27 PM PDT 24 Jun 24 05:30:32 PM PDT 24 243325247 ps
T593 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1263254943 Jun 24 05:30:30 PM PDT 24 Jun 24 05:30:34 PM PDT 24 499708919 ps
T117 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.710095069 Jun 24 05:30:41 PM PDT 24 Jun 24 05:30:47 PM PDT 24 893367734 ps
T118 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.4207956361 Jun 24 05:30:53 PM PDT 24 Jun 24 05:30:58 PM PDT 24 800087529 ps
T594 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2262220054 Jun 24 05:30:50 PM PDT 24 Jun 24 05:30:52 PM PDT 24 87082830 ps
T595 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.814859816 Jun 24 05:30:41 PM PDT 24 Jun 24 05:30:45 PM PDT 24 125443244 ps
T596 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.38049861 Jun 24 05:30:42 PM PDT 24 Jun 24 05:30:46 PM PDT 24 74622995 ps
T119 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3738819817 Jun 24 05:30:41 PM PDT 24 Jun 24 05:30:46 PM PDT 24 421873667 ps
T597 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2409610199 Jun 24 05:30:43 PM PDT 24 Jun 24 05:30:47 PM PDT 24 88782523 ps
T598 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1755495000 Jun 24 05:30:43 PM PDT 24 Jun 24 05:30:47 PM PDT 24 72947058 ps
T599 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1098856371 Jun 24 05:30:51 PM PDT 24 Jun 24 05:30:53 PM PDT 24 188401194 ps
T600 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.531976546 Jun 24 05:30:51 PM PDT 24 Jun 24 05:30:54 PM PDT 24 189737383 ps
T601 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2966350295 Jun 24 05:30:40 PM PDT 24 Jun 24 05:30:45 PM PDT 24 225574518 ps
T602 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1283167647 Jun 24 05:30:39 PM PDT 24 Jun 24 05:30:42 PM PDT 24 491652929 ps
T603 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1348577654 Jun 24 05:30:42 PM PDT 24 Jun 24 05:30:47 PM PDT 24 104947465 ps
T604 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2506214150 Jun 24 05:30:38 PM PDT 24 Jun 24 05:30:39 PM PDT 24 95526214 ps
T120 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1230530212 Jun 24 05:30:42 PM PDT 24 Jun 24 05:30:48 PM PDT 24 477609922 ps
T605 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2401736457 Jun 24 05:30:44 PM PDT 24 Jun 24 05:30:48 PM PDT 24 80412578 ps
T606 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1918532418 Jun 24 05:30:46 PM PDT 24 Jun 24 05:30:51 PM PDT 24 955630514 ps
T607 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1355881347 Jun 24 05:30:43 PM PDT 24 Jun 24 05:30:48 PM PDT 24 126997149 ps
T608 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2836915999 Jun 24 05:30:41 PM PDT 24 Jun 24 05:30:45 PM PDT 24 193412170 ps
T609 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2646431040 Jun 24 05:30:43 PM PDT 24 Jun 24 05:30:48 PM PDT 24 149398365 ps
T610 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.641881981 Jun 24 05:30:50 PM PDT 24 Jun 24 05:30:53 PM PDT 24 769704377 ps
T611 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2780023698 Jun 24 05:30:53 PM PDT 24 Jun 24 05:30:57 PM PDT 24 109648812 ps
T612 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1041758822 Jun 24 05:30:39 PM PDT 24 Jun 24 05:30:41 PM PDT 24 114205690 ps
T613 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.123127529 Jun 24 05:30:40 PM PDT 24 Jun 24 05:30:45 PM PDT 24 498377581 ps
T614 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.240239985 Jun 24 05:30:53 PM PDT 24 Jun 24 05:30:57 PM PDT 24 227397973 ps
T615 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3186574921 Jun 24 05:30:40 PM PDT 24 Jun 24 05:30:45 PM PDT 24 174191486 ps
T616 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2888688656 Jun 24 05:30:43 PM PDT 24 Jun 24 05:30:47 PM PDT 24 127569442 ps
T617 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3261814028 Jun 24 05:30:53 PM PDT 24 Jun 24 05:30:58 PM PDT 24 807157234 ps
T618 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3107008327 Jun 24 05:30:50 PM PDT 24 Jun 24 05:30:52 PM PDT 24 126574423 ps
T619 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1393897916 Jun 24 05:30:51 PM PDT 24 Jun 24 05:30:54 PM PDT 24 112939858 ps
T620 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3478223668 Jun 24 05:30:54 PM PDT 24 Jun 24 05:30:57 PM PDT 24 115028930 ps

Test location /workspace/coverage/default/34.rstmgr_smoke.728171604
Short name T4
Test name
Test status
Simulation time 193119851 ps
CPU time 1.37 seconds
Started Jun 24 05:35:52 PM PDT 24
Finished Jun 24 05:35:54 PM PDT 24
Peak memory 200884 kb
Host smart-44e9ee26-5b39-4ef3-93ea-45d110261320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728171604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.728171604
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1431981849
Short name T58
Test name
Test status
Simulation time 6694416114 ps
CPU time 24.98 seconds
Started Jun 24 05:35:22 PM PDT 24
Finished Jun 24 05:35:49 PM PDT 24
Peak memory 200968 kb
Host smart-83056e52-4e5c-4a16-aeb1-8cffcdbcf0a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431981849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1431981849
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3017023093
Short name T3
Test name
Test status
Simulation time 533412140 ps
CPU time 2.6 seconds
Started Jun 24 05:35:36 PM PDT 24
Finished Jun 24 05:35:40 PM PDT 24
Peak memory 200932 kb
Host smart-9490fb5b-cb31-4b45-8018-fbee83d76a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017023093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3017023093
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.391525763
Short name T64
Test name
Test status
Simulation time 907406438 ps
CPU time 2.89 seconds
Started Jun 24 05:30:30 PM PDT 24
Finished Jun 24 05:30:35 PM PDT 24
Peak memory 200896 kb
Host smart-1816ef90-ad6c-4668-9e23-f49eb286bfc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391525763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
391525763
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1703663867
Short name T2
Test name
Test status
Simulation time 8379178159 ps
CPU time 13 seconds
Started Jun 24 05:34:54 PM PDT 24
Finished Jun 24 05:35:08 PM PDT 24
Peak memory 217680 kb
Host smart-84fe0003-5470-49fb-bf58-88ca909af83b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703663867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1703663867
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3976081064
Short name T25
Test name
Test status
Simulation time 1233287286 ps
CPU time 6.27 seconds
Started Jun 24 05:36:00 PM PDT 24
Finished Jun 24 05:36:07 PM PDT 24
Peak memory 221468 kb
Host smart-98821cff-f180-4ea1-bc13-9a62dcf651eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976081064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3976081064
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3495720993
Short name T67
Test name
Test status
Simulation time 465945056 ps
CPU time 3.43 seconds
Started Jun 24 05:30:53 PM PDT 24
Finished Jun 24 05:30:59 PM PDT 24
Peak memory 208988 kb
Host smart-00800d28-8c7c-48e8-86b7-37f1992f8429
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495720993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3495720993
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3000616194
Short name T113
Test name
Test status
Simulation time 17296219983 ps
CPU time 55.96 seconds
Started Jun 24 05:35:17 PM PDT 24
Finished Jun 24 05:36:14 PM PDT 24
Peak memory 210820 kb
Host smart-e770e337-2178-4c9e-b1bf-4bb41369e685
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000616194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3000616194
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.649052558
Short name T123
Test name
Test status
Simulation time 78153233 ps
CPU time 0.8 seconds
Started Jun 24 05:35:00 PM PDT 24
Finished Jun 24 05:35:02 PM PDT 24
Peak memory 200500 kb
Host smart-5f9b3ace-4cf8-4e4e-96e0-4ba91d3a7da3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649052558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.649052558
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2316294737
Short name T55
Test name
Test status
Simulation time 100404778 ps
CPU time 1.03 seconds
Started Jun 24 05:35:22 PM PDT 24
Finished Jun 24 05:35:25 PM PDT 24
Peak memory 200700 kb
Host smart-6a5e4e12-a27b-4b40-bf68-7d5f0826ad72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316294737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2316294737
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.259736693
Short name T34
Test name
Test status
Simulation time 2368458989 ps
CPU time 7.99 seconds
Started Jun 24 05:35:04 PM PDT 24
Finished Jun 24 05:35:15 PM PDT 24
Peak memory 218564 kb
Host smart-b515b22f-45ee-4c64-97f8-2e63714c69d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259736693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.259736693
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1239003808
Short name T14
Test name
Test status
Simulation time 154783731 ps
CPU time 1.18 seconds
Started Jun 24 05:35:17 PM PDT 24
Finished Jun 24 05:35:19 PM PDT 24
Peak memory 200704 kb
Host smart-e69cbd36-cc6c-4e5a-8aea-f7d248ec0759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239003808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1239003808
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.199457281
Short name T81
Test name
Test status
Simulation time 792952026 ps
CPU time 2.83 seconds
Started Jun 24 05:30:52 PM PDT 24
Finished Jun 24 05:30:56 PM PDT 24
Peak memory 200664 kb
Host smart-0443fa22-ba1a-4083-92ea-633ee6bc6d58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199457281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.199457281
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3261814028
Short name T617
Test name
Test status
Simulation time 807157234 ps
CPU time 2.83 seconds
Started Jun 24 05:30:53 PM PDT 24
Finished Jun 24 05:30:58 PM PDT 24
Peak memory 200828 kb
Host smart-83a9b28e-3454-4852-b8c3-f5a0bc57e12b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261814028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3261814028
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1569634977
Short name T68
Test name
Test status
Simulation time 162657241 ps
CPU time 2.58 seconds
Started Jun 24 05:30:40 PM PDT 24
Finished Jun 24 05:30:44 PM PDT 24
Peak memory 209000 kb
Host smart-4ff7e55c-ea20-48bb-86b4-6dc2424f809a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569634977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1569634977
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2489477365
Short name T90
Test name
Test status
Simulation time 3137687510 ps
CPU time 16.18 seconds
Started Jun 24 05:36:13 PM PDT 24
Finished Jun 24 05:36:30 PM PDT 24
Peak memory 200944 kb
Host smart-9e9505e4-524d-4afe-923f-247defa260ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489477365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2489477365
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.748638165
Short name T36
Test name
Test status
Simulation time 2374723066 ps
CPU time 8.18 seconds
Started Jun 24 05:35:21 PM PDT 24
Finished Jun 24 05:35:30 PM PDT 24
Peak memory 221996 kb
Host smart-5ff944e2-1e50-453b-bd50-db4edbe2679b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748638165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.748638165
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3708592615
Short name T110
Test name
Test status
Simulation time 87285333 ps
CPU time 1.02 seconds
Started Jun 24 05:30:27 PM PDT 24
Finished Jun 24 05:30:31 PM PDT 24
Peak memory 200644 kb
Host smart-c67f50a8-97ae-4ced-bf5d-59c47dd40f00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708592615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3708592615
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.2476412524
Short name T17
Test name
Test status
Simulation time 83617107 ps
CPU time 0.74 seconds
Started Jun 24 05:34:53 PM PDT 24
Finished Jun 24 05:34:55 PM PDT 24
Peak memory 200432 kb
Host smart-a6028154-2d3f-4091-a12f-e157017cf803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476412524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2476412524
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3664678879
Short name T145
Test name
Test status
Simulation time 244815525 ps
CPU time 1.14 seconds
Started Jun 24 05:35:00 PM PDT 24
Finished Jun 24 05:35:02 PM PDT 24
Peak memory 218296 kb
Host smart-7e16662e-c884-4253-8e6f-bb7a92f72f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664678879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3664678879
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.402623180
Short name T543
Test name
Test status
Simulation time 158072252 ps
CPU time 2.11 seconds
Started Jun 24 05:30:27 PM PDT 24
Finished Jun 24 05:30:31 PM PDT 24
Peak memory 200784 kb
Host smart-9cc3b109-6290-4b97-aecf-95db3b0de8ee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402623180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.402623180
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.769657062
Short name T581
Test name
Test status
Simulation time 480199487 ps
CPU time 5.85 seconds
Started Jun 24 05:30:29 PM PDT 24
Finished Jun 24 05:30:37 PM PDT 24
Peak memory 200852 kb
Host smart-c119b5a3-35e6-4422-aa9e-701f44b4711d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769657062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.769657062
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1508025628
Short name T589
Test name
Test status
Simulation time 95458096 ps
CPU time 0.84 seconds
Started Jun 24 05:30:28 PM PDT 24
Finished Jun 24 05:30:31 PM PDT 24
Peak memory 200720 kb
Host smart-7b9897a5-78ca-49bc-b0d9-867c2118e852
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508025628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
508025628
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1563399570
Short name T69
Test name
Test status
Simulation time 106904360 ps
CPU time 1.21 seconds
Started Jun 24 05:30:28 PM PDT 24
Finished Jun 24 05:30:31 PM PDT 24
Peak memory 211704 kb
Host smart-6c6b0da2-ad6a-4cd6-a025-6b43d2ad8867
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563399570 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1563399570
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.4117120150
Short name T570
Test name
Test status
Simulation time 55665426 ps
CPU time 0.77 seconds
Started Jun 24 05:30:29 PM PDT 24
Finished Jun 24 05:30:32 PM PDT 24
Peak memory 200584 kb
Host smart-b3bea084-4510-4716-9302-8ab195ce8996
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117120150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.4117120150
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1056468839
Short name T556
Test name
Test status
Simulation time 262731965 ps
CPU time 1.85 seconds
Started Jun 24 05:30:24 PM PDT 24
Finished Jun 24 05:30:27 PM PDT 24
Peak memory 200868 kb
Host smart-8eff6fda-1bd0-4990-bcf0-61dfe4acb17c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056468839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1056468839
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.352609510
Short name T70
Test name
Test status
Simulation time 793046846 ps
CPU time 2.74 seconds
Started Jun 24 05:30:30 PM PDT 24
Finished Jun 24 05:30:34 PM PDT 24
Peak memory 200828 kb
Host smart-aa528f1e-84d7-4610-9298-dce25e0e44ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352609510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.
352609510
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3238488505
Short name T585
Test name
Test status
Simulation time 166031091 ps
CPU time 1.99 seconds
Started Jun 24 05:30:28 PM PDT 24
Finished Jun 24 05:30:32 PM PDT 24
Peak memory 209092 kb
Host smart-643e7680-d1a9-40c2-8912-227cc2ce8b8e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238488505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
238488505
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3873926554
Short name T547
Test name
Test status
Simulation time 273324939 ps
CPU time 3.46 seconds
Started Jun 24 05:30:28 PM PDT 24
Finished Jun 24 05:30:34 PM PDT 24
Peak memory 200936 kb
Host smart-3e98cc3d-384d-4228-8b2f-d73930b6987e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873926554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
873926554
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2372505303
Short name T551
Test name
Test status
Simulation time 125773009 ps
CPU time 0.96 seconds
Started Jun 24 05:30:28 PM PDT 24
Finished Jun 24 05:30:31 PM PDT 24
Peak memory 200720 kb
Host smart-9343c096-bb40-47ea-b712-d79daa7b1c90
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372505303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
372505303
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3134329527
Short name T93
Test name
Test status
Simulation time 215399759 ps
CPU time 1.35 seconds
Started Jun 24 05:30:27 PM PDT 24
Finished Jun 24 05:30:31 PM PDT 24
Peak memory 208980 kb
Host smart-9c5d3497-d7bb-4572-a191-cba419a95cf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134329527 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3134329527
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3684654451
Short name T584
Test name
Test status
Simulation time 70482396 ps
CPU time 0.75 seconds
Started Jun 24 05:30:27 PM PDT 24
Finished Jun 24 05:30:30 PM PDT 24
Peak memory 200652 kb
Host smart-62295110-87b6-4dfb-84dc-5a3e8180c054
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684654451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3684654451
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1873421288
Short name T592
Test name
Test status
Simulation time 243325247 ps
CPU time 1.55 seconds
Started Jun 24 05:30:27 PM PDT 24
Finished Jun 24 05:30:32 PM PDT 24
Peak memory 200792 kb
Host smart-b2fcf7d7-3d80-4877-83e5-33c5605cb1ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873421288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1873421288
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2524771600
Short name T563
Test name
Test status
Simulation time 187077666 ps
CPU time 1.5 seconds
Started Jun 24 05:30:27 PM PDT 24
Finished Jun 24 05:30:30 PM PDT 24
Peak memory 209020 kb
Host smart-70ca834c-37a2-4a1c-a44c-5bf85bb8dabf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524771600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2524771600
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.4000222430
Short name T83
Test name
Test status
Simulation time 171530843 ps
CPU time 1.43 seconds
Started Jun 24 05:30:40 PM PDT 24
Finished Jun 24 05:30:44 PM PDT 24
Peak memory 209092 kb
Host smart-2cfa75c4-f951-40bc-85ea-96ea45a5fb63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000222430 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.4000222430
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.75802241
Short name T108
Test name
Test status
Simulation time 67455047 ps
CPU time 0.83 seconds
Started Jun 24 05:30:40 PM PDT 24
Finished Jun 24 05:30:43 PM PDT 24
Peak memory 200660 kb
Host smart-a1bd56ef-b1e1-4503-99b2-519f7ae0289a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75802241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.75802241
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2640577588
Short name T568
Test name
Test status
Simulation time 253581073 ps
CPU time 1.53 seconds
Started Jun 24 05:30:40 PM PDT 24
Finished Jun 24 05:30:43 PM PDT 24
Peak memory 200804 kb
Host smart-666cbc24-6ac5-4eba-a8b0-6b0ba6d99248
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640577588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.2640577588
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.4005779252
Short name T553
Test name
Test status
Simulation time 800494974 ps
CPU time 2.97 seconds
Started Jun 24 05:30:43 PM PDT 24
Finished Jun 24 05:30:49 PM PDT 24
Peak memory 200908 kb
Host smart-d06bf2ff-88c2-4924-b9d1-7b9f8572c997
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005779252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.4005779252
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3442838623
Short name T587
Test name
Test status
Simulation time 102529395 ps
CPU time 1.05 seconds
Started Jun 24 05:30:44 PM PDT 24
Finished Jun 24 05:30:48 PM PDT 24
Peak memory 200640 kb
Host smart-b7a48fdc-9842-4ff0-970f-f91e883e09f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442838623 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3442838623
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2623367906
Short name T550
Test name
Test status
Simulation time 69120940 ps
CPU time 0.79 seconds
Started Jun 24 05:30:41 PM PDT 24
Finished Jun 24 05:30:45 PM PDT 24
Peak memory 200608 kb
Host smart-96306f43-0815-4129-a61e-98d0090cc32e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623367906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2623367906
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3092501538
Short name T102
Test name
Test status
Simulation time 93617020 ps
CPU time 1.16 seconds
Started Jun 24 05:30:43 PM PDT 24
Finished Jun 24 05:30:47 PM PDT 24
Peak memory 200908 kb
Host smart-0af200a5-06e7-4b95-a9b3-7a39c0931635
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092501538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.3092501538
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1067511407
Short name T586
Test name
Test status
Simulation time 153869890 ps
CPU time 2.15 seconds
Started Jun 24 05:30:41 PM PDT 24
Finished Jun 24 05:30:46 PM PDT 24
Peak memory 209040 kb
Host smart-95d0dcd3-9528-4fe1-9580-7b7a57d8f7a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067511407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1067511407
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1918532418
Short name T606
Test name
Test status
Simulation time 955630514 ps
CPU time 3.22 seconds
Started Jun 24 05:30:46 PM PDT 24
Finished Jun 24 05:30:51 PM PDT 24
Peak memory 200848 kb
Host smart-6e27ae1f-99df-49a0-b7cb-40169b86d2f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918532418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1918532418
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.914949227
Short name T554
Test name
Test status
Simulation time 188950477 ps
CPU time 1.28 seconds
Started Jun 24 05:30:45 PM PDT 24
Finished Jun 24 05:30:49 PM PDT 24
Peak memory 200656 kb
Host smart-59c4573f-21b2-4ca1-a2b8-997e58b4af05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914949227 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.914949227
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.38049861
Short name T596
Test name
Test status
Simulation time 74622995 ps
CPU time 0.79 seconds
Started Jun 24 05:30:42 PM PDT 24
Finished Jun 24 05:30:46 PM PDT 24
Peak memory 200532 kb
Host smart-00de6ac3-96b2-480f-b7ec-5664a2ea0a6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38049861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.38049861
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2409610199
Short name T597
Test name
Test status
Simulation time 88782523 ps
CPU time 1.09 seconds
Started Jun 24 05:30:43 PM PDT 24
Finished Jun 24 05:30:47 PM PDT 24
Peak memory 200388 kb
Host smart-09f21963-5771-4f7e-b581-031e65aa2389
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409610199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.2409610199
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.850302493
Short name T560
Test name
Test status
Simulation time 209320100 ps
CPU time 1.74 seconds
Started Jun 24 05:30:43 PM PDT 24
Finished Jun 24 05:30:48 PM PDT 24
Peak memory 217140 kb
Host smart-c75a9b8b-05c8-4dd9-8fa5-72627e23eaba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850302493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.850302493
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.123127529
Short name T613
Test name
Test status
Simulation time 498377581 ps
CPU time 1.96 seconds
Started Jun 24 05:30:40 PM PDT 24
Finished Jun 24 05:30:45 PM PDT 24
Peak memory 200812 kb
Host smart-3b49bc1e-03e2-4a38-adf4-edad7e124b24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123127529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.123127529
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4080511545
Short name T591
Test name
Test status
Simulation time 205747983 ps
CPU time 1.31 seconds
Started Jun 24 05:30:43 PM PDT 24
Finished Jun 24 05:30:47 PM PDT 24
Peak memory 208948 kb
Host smart-cd28c2e7-c90d-4d81-a3a4-8658a4578490
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080511545 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.4080511545
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2401736457
Short name T605
Test name
Test status
Simulation time 80412578 ps
CPU time 0.89 seconds
Started Jun 24 05:30:44 PM PDT 24
Finished Jun 24 05:30:48 PM PDT 24
Peak memory 200652 kb
Host smart-19c7ea84-9954-4cfe-8527-0206326b2d72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401736457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2401736457
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1874487765
Short name T109
Test name
Test status
Simulation time 203491700 ps
CPU time 1.49 seconds
Started Jun 24 05:30:44 PM PDT 24
Finished Jun 24 05:30:49 PM PDT 24
Peak memory 200752 kb
Host smart-5e8f6144-93d9-49f5-a82c-b8f89abd4905
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874487765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1874487765
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3030471119
Short name T566
Test name
Test status
Simulation time 322988300 ps
CPU time 2.26 seconds
Started Jun 24 05:30:43 PM PDT 24
Finished Jun 24 05:30:49 PM PDT 24
Peak memory 209016 kb
Host smart-537f48a7-e340-4403-b552-08ddd4744b6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030471119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3030471119
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.4040287966
Short name T579
Test name
Test status
Simulation time 490993960 ps
CPU time 1.97 seconds
Started Jun 24 05:30:43 PM PDT 24
Finished Jun 24 05:30:48 PM PDT 24
Peak memory 200916 kb
Host smart-be71ea3a-771d-4ab6-a8fb-aebec9a5630f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040287966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.4040287966
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3107008327
Short name T618
Test name
Test status
Simulation time 126574423 ps
CPU time 1.43 seconds
Started Jun 24 05:30:50 PM PDT 24
Finished Jun 24 05:30:52 PM PDT 24
Peak memory 209080 kb
Host smart-7f2e43f4-2f7d-478c-b553-fc9244bd4157
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107008327 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3107008327
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.39362018
Short name T559
Test name
Test status
Simulation time 84329215 ps
CPU time 0.91 seconds
Started Jun 24 05:30:37 PM PDT 24
Finished Jun 24 05:30:38 PM PDT 24
Peak memory 200656 kb
Host smart-1994aeac-74f6-456e-a38e-aa545123eb43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39362018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.39362018
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.370513514
Short name T590
Test name
Test status
Simulation time 176274565 ps
CPU time 1.27 seconds
Started Jun 24 05:30:44 PM PDT 24
Finished Jun 24 05:30:48 PM PDT 24
Peak memory 200644 kb
Host smart-308688e6-3adf-47fe-8bd5-d41dadfcec90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370513514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_sa
me_csr_outstanding.370513514
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2646431040
Short name T609
Test name
Test status
Simulation time 149398365 ps
CPU time 2.12 seconds
Started Jun 24 05:30:43 PM PDT 24
Finished Jun 24 05:30:48 PM PDT 24
Peak memory 200896 kb
Host smart-e2fa311e-b4ef-4f0c-8062-30ef5891ab86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646431040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2646431040
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1230530212
Short name T120
Test name
Test status
Simulation time 477609922 ps
CPU time 1.92 seconds
Started Jun 24 05:30:42 PM PDT 24
Finished Jun 24 05:30:48 PM PDT 24
Peak memory 200916 kb
Host smart-56e8b2f2-e992-4bb8-8cf4-38f567a588d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230530212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1230530212
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3883702297
Short name T574
Test name
Test status
Simulation time 196235489 ps
CPU time 1.96 seconds
Started Jun 24 05:30:53 PM PDT 24
Finished Jun 24 05:30:56 PM PDT 24
Peak memory 209140 kb
Host smart-09ab3e56-83ee-431e-9f91-38e329b4ecfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883702297 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3883702297
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2262220054
Short name T594
Test name
Test status
Simulation time 87082830 ps
CPU time 0.89 seconds
Started Jun 24 05:30:50 PM PDT 24
Finished Jun 24 05:30:52 PM PDT 24
Peak memory 200572 kb
Host smart-77e35619-41b6-47ba-b7aa-d1479752ff26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262220054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2262220054
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1098856371
Short name T599
Test name
Test status
Simulation time 188401194 ps
CPU time 1.36 seconds
Started Jun 24 05:30:51 PM PDT 24
Finished Jun 24 05:30:53 PM PDT 24
Peak memory 200804 kb
Host smart-38ed20de-0325-4744-97a5-df0d818267b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098856371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1098856371
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1687982106
Short name T582
Test name
Test status
Simulation time 278251323 ps
CPU time 2.33 seconds
Started Jun 24 05:30:50 PM PDT 24
Finished Jun 24 05:30:53 PM PDT 24
Peak memory 209028 kb
Host smart-cff88702-9d2e-4e2b-a595-b8ab7f027ff3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687982106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1687982106
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3998793759
Short name T65
Test name
Test status
Simulation time 1088794426 ps
CPU time 3.34 seconds
Started Jun 24 05:30:50 PM PDT 24
Finished Jun 24 05:30:54 PM PDT 24
Peak memory 200964 kb
Host smart-5da02e07-c77e-4bb9-b6b2-da5389e3c3b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998793759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3998793759
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1393897916
Short name T619
Test name
Test status
Simulation time 112939858 ps
CPU time 0.94 seconds
Started Jun 24 05:30:51 PM PDT 24
Finished Jun 24 05:30:54 PM PDT 24
Peak memory 200652 kb
Host smart-845f65bc-1214-401f-81ad-55cdf1089e5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393897916 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.1393897916
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2376890862
Short name T576
Test name
Test status
Simulation time 70945088 ps
CPU time 0.77 seconds
Started Jun 24 05:30:52 PM PDT 24
Finished Jun 24 05:30:54 PM PDT 24
Peak memory 200584 kb
Host smart-24b75281-3b90-487e-9f01-aa2f33440e76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376890862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2376890862
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1488976934
Short name T572
Test name
Test status
Simulation time 194864310 ps
CPU time 1.45 seconds
Started Jun 24 05:30:57 PM PDT 24
Finished Jun 24 05:31:00 PM PDT 24
Peak memory 200848 kb
Host smart-5a0d6fe0-5106-49e8-b9ef-fd46cd0b334d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488976934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1488976934
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.4207956361
Short name T118
Test name
Test status
Simulation time 800087529 ps
CPU time 2.74 seconds
Started Jun 24 05:30:53 PM PDT 24
Finished Jun 24 05:30:58 PM PDT 24
Peak memory 201116 kb
Host smart-f373938e-6f60-4269-b594-e698db100fc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207956361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.4207956361
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2290684719
Short name T577
Test name
Test status
Simulation time 183697515 ps
CPU time 1.18 seconds
Started Jun 24 05:30:51 PM PDT 24
Finished Jun 24 05:30:53 PM PDT 24
Peak memory 200656 kb
Host smart-f6b06f10-e650-4313-afcc-fa73ea803505
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290684719 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2290684719
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.727079966
Short name T546
Test name
Test status
Simulation time 75146874 ps
CPU time 0.83 seconds
Started Jun 24 05:30:52 PM PDT 24
Finished Jun 24 05:30:54 PM PDT 24
Peak memory 200476 kb
Host smart-067354a8-4245-4184-a9c9-7c62e066cf65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727079966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.727079966
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.593209381
Short name T571
Test name
Test status
Simulation time 142199084 ps
CPU time 1.21 seconds
Started Jun 24 05:30:50 PM PDT 24
Finished Jun 24 05:30:52 PM PDT 24
Peak memory 200620 kb
Host smart-8a84aec9-d2b8-4fc5-9b90-9c65e30a9dc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593209381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.593209381
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2780023698
Short name T611
Test name
Test status
Simulation time 109648812 ps
CPU time 1.65 seconds
Started Jun 24 05:30:53 PM PDT 24
Finished Jun 24 05:30:57 PM PDT 24
Peak memory 209012 kb
Host smart-85173831-bc4a-4369-94c4-bbdfb902ecde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780023698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2780023698
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1622707127
Short name T548
Test name
Test status
Simulation time 189773262 ps
CPU time 1.31 seconds
Started Jun 24 05:30:52 PM PDT 24
Finished Jun 24 05:30:55 PM PDT 24
Peak memory 209096 kb
Host smart-94ba9e4a-03be-4c89-8bb8-374618c0cd55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622707127 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1622707127
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.380541945
Short name T565
Test name
Test status
Simulation time 83648314 ps
CPU time 0.84 seconds
Started Jun 24 05:30:55 PM PDT 24
Finished Jun 24 05:30:57 PM PDT 24
Peak memory 200664 kb
Host smart-d42c98b9-0964-4c28-9e87-134f815ef63d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380541945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.380541945
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2387438131
Short name T103
Test name
Test status
Simulation time 84159501 ps
CPU time 0.96 seconds
Started Jun 24 05:30:52 PM PDT 24
Finished Jun 24 05:30:54 PM PDT 24
Peak memory 200564 kb
Host smart-33a7fbad-a4cf-4e9f-9ff4-00723ad94e58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387438131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2387438131
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.531976546
Short name T600
Test name
Test status
Simulation time 189737383 ps
CPU time 1.55 seconds
Started Jun 24 05:30:51 PM PDT 24
Finished Jun 24 05:30:54 PM PDT 24
Peak memory 208880 kb
Host smart-285c655a-5591-45cf-8fa9-5b99be05f637
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531976546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.531976546
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3478223668
Short name T620
Test name
Test status
Simulation time 115028930 ps
CPU time 0.93 seconds
Started Jun 24 05:30:54 PM PDT 24
Finished Jun 24 05:30:57 PM PDT 24
Peak memory 200648 kb
Host smart-5e7725a9-0850-4375-a4d9-7c2007bff2a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478223668 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3478223668
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3349082159
Short name T545
Test name
Test status
Simulation time 96412297 ps
CPU time 0.86 seconds
Started Jun 24 05:30:54 PM PDT 24
Finished Jun 24 05:30:57 PM PDT 24
Peak memory 200664 kb
Host smart-e490cec9-82da-45b4-a7bc-34b926683358
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349082159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3349082159
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.240239985
Short name T614
Test name
Test status
Simulation time 227397973 ps
CPU time 1.51 seconds
Started Jun 24 05:30:53 PM PDT 24
Finished Jun 24 05:30:57 PM PDT 24
Peak memory 200812 kb
Host smart-0e7c7801-7c85-44a7-a508-8a434586ab58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240239985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.240239985
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2872154999
Short name T569
Test name
Test status
Simulation time 227041319 ps
CPU time 3.28 seconds
Started Jun 24 05:30:50 PM PDT 24
Finished Jun 24 05:30:54 PM PDT 24
Peak memory 209004 kb
Host smart-053850c1-21f0-4634-bff7-9570c39b5ca1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872154999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2872154999
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.641881981
Short name T610
Test name
Test status
Simulation time 769704377 ps
CPU time 2.74 seconds
Started Jun 24 05:30:50 PM PDT 24
Finished Jun 24 05:30:53 PM PDT 24
Peak memory 200896 kb
Host smart-5f8bba80-e193-4769-95a5-a9f664d8f96c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641881981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.641881981
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1348577654
Short name T603
Test name
Test status
Simulation time 104947465 ps
CPU time 1.37 seconds
Started Jun 24 05:30:42 PM PDT 24
Finished Jun 24 05:30:47 PM PDT 24
Peak memory 200976 kb
Host smart-f2fac12c-f8da-4b61-8336-04e3e547f941
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348577654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1
348577654
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.93423186
Short name T580
Test name
Test status
Simulation time 2308889136 ps
CPU time 10.31 seconds
Started Jun 24 05:30:39 PM PDT 24
Finished Jun 24 05:30:51 PM PDT 24
Peak memory 200956 kb
Host smart-de93aa78-cfb1-4aa4-a6a0-729970ecee92
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93423186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.93423186
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.369297004
Short name T564
Test name
Test status
Simulation time 119289016 ps
CPU time 0.89 seconds
Started Jun 24 05:30:39 PM PDT 24
Finished Jun 24 05:30:42 PM PDT 24
Peak memory 200684 kb
Host smart-04b2f414-a7a2-4bdd-b437-dce1f0e5366d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369297004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.369297004
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.290483443
Short name T85
Test name
Test status
Simulation time 134957378 ps
CPU time 1.07 seconds
Started Jun 24 05:30:43 PM PDT 24
Finished Jun 24 05:30:47 PM PDT 24
Peak memory 210876 kb
Host smart-38f3bcbc-33ad-4796-9f6e-3751c713266e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290483443 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.290483443
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.614356178
Short name T561
Test name
Test status
Simulation time 75856746 ps
CPU time 0.81 seconds
Started Jun 24 05:30:39 PM PDT 24
Finished Jun 24 05:30:41 PM PDT 24
Peak memory 200624 kb
Host smart-397a1fa5-6df3-4690-8c61-b4b7c945c885
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614356178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.614356178
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1410607215
Short name T105
Test name
Test status
Simulation time 102398326 ps
CPU time 1.29 seconds
Started Jun 24 05:30:41 PM PDT 24
Finished Jun 24 05:30:45 PM PDT 24
Peak memory 200848 kb
Host smart-f1ae78bc-a802-4722-a29b-f98b462dc2f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410607215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1410607215
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1304590162
Short name T75
Test name
Test status
Simulation time 196564309 ps
CPU time 2.9 seconds
Started Jun 24 05:30:33 PM PDT 24
Finished Jun 24 05:30:37 PM PDT 24
Peak memory 209096 kb
Host smart-79343470-fc2d-4082-8cdd-271760a098ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304590162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1304590162
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1263254943
Short name T593
Test name
Test status
Simulation time 499708919 ps
CPU time 1.89 seconds
Started Jun 24 05:30:30 PM PDT 24
Finished Jun 24 05:30:34 PM PDT 24
Peak memory 200900 kb
Host smart-451acf4e-952d-4128-a9ab-dc388ad7062c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263254943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1263254943
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.684977784
Short name T542
Test name
Test status
Simulation time 243023477 ps
CPU time 1.64 seconds
Started Jun 24 05:30:38 PM PDT 24
Finished Jun 24 05:30:41 PM PDT 24
Peak memory 201080 kb
Host smart-59c44fe0-13e2-4f1b-ad1e-a2ae5a7efaa0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684977784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.684977784
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1476808641
Short name T540
Test name
Test status
Simulation time 488693874 ps
CPU time 6.18 seconds
Started Jun 24 05:30:46 PM PDT 24
Finished Jun 24 05:30:54 PM PDT 24
Peak memory 200920 kb
Host smart-63dff8ea-5fbf-461a-97b8-bb792ae2db4f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476808641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
476808641
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3919410022
Short name T539
Test name
Test status
Simulation time 99610080 ps
CPU time 0.83 seconds
Started Jun 24 05:30:46 PM PDT 24
Finished Jun 24 05:30:49 PM PDT 24
Peak memory 200712 kb
Host smart-3996de3d-3090-41eb-a14b-ea3a7eca0d1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919410022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
919410022
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2836915999
Short name T608
Test name
Test status
Simulation time 193412170 ps
CPU time 1.36 seconds
Started Jun 24 05:30:41 PM PDT 24
Finished Jun 24 05:30:45 PM PDT 24
Peak memory 208772 kb
Host smart-73094622-9ba6-4a13-a3d5-92d941ff107f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836915999 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2836915999
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2781457003
Short name T575
Test name
Test status
Simulation time 71944292 ps
CPU time 0.83 seconds
Started Jun 24 05:30:41 PM PDT 24
Finished Jun 24 05:30:44 PM PDT 24
Peak memory 200596 kb
Host smart-cf6ec0b6-b8ec-425d-b017-d660fa74694a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781457003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.2781457003
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2346265305
Short name T107
Test name
Test status
Simulation time 148250295 ps
CPU time 1.16 seconds
Started Jun 24 05:30:40 PM PDT 24
Finished Jun 24 05:30:43 PM PDT 24
Peak memory 200644 kb
Host smart-71480a61-8ac4-41ff-aec8-2e324c8e816c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346265305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2346265305
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1447938691
Short name T76
Test name
Test status
Simulation time 535329828 ps
CPU time 3.76 seconds
Started Jun 24 05:30:40 PM PDT 24
Finished Jun 24 05:30:46 PM PDT 24
Peak memory 217020 kb
Host smart-680ea73a-a2ca-476c-b5bf-21458ae5fc88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447938691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1447938691
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1834100540
Short name T82
Test name
Test status
Simulation time 791795063 ps
CPU time 2.94 seconds
Started Jun 24 05:30:40 PM PDT 24
Finished Jun 24 05:30:46 PM PDT 24
Peak memory 200908 kb
Host smart-d06fec41-b50f-4b47-a122-0e30f973cb5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834100540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1834100540
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2840350624
Short name T541
Test name
Test status
Simulation time 242695297 ps
CPU time 1.8 seconds
Started Jun 24 05:30:39 PM PDT 24
Finished Jun 24 05:30:42 PM PDT 24
Peak memory 200968 kb
Host smart-e6007928-c6a9-462e-acee-2e8ffbcdf411
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840350624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
840350624
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3610787782
Short name T562
Test name
Test status
Simulation time 1168664523 ps
CPU time 4.8 seconds
Started Jun 24 05:30:40 PM PDT 24
Finished Jun 24 05:30:48 PM PDT 24
Peak memory 201164 kb
Host smart-da17a140-02be-4dfe-93ee-c539bce0a1fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610787782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3
610787782
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2291897455
Short name T544
Test name
Test status
Simulation time 106622251 ps
CPU time 0.87 seconds
Started Jun 24 05:30:39 PM PDT 24
Finished Jun 24 05:30:40 PM PDT 24
Peak memory 200708 kb
Host smart-170fda68-7404-475b-bb28-a1ce15bd9353
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291897455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
291897455
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1041758822
Short name T612
Test name
Test status
Simulation time 114205690 ps
CPU time 0.94 seconds
Started Jun 24 05:30:39 PM PDT 24
Finished Jun 24 05:30:41 PM PDT 24
Peak memory 200644 kb
Host smart-bf3b0aec-748f-42b7-a201-7c8aa0305811
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041758822 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1041758822
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.738293415
Short name T578
Test name
Test status
Simulation time 71647132 ps
CPU time 0.8 seconds
Started Jun 24 05:30:42 PM PDT 24
Finished Jun 24 05:30:46 PM PDT 24
Peak memory 200648 kb
Host smart-dc9a6d8c-072f-450b-a516-cd5c8dbbf3d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738293415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.738293415
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1897191674
Short name T106
Test name
Test status
Simulation time 136190050 ps
CPU time 1.1 seconds
Started Jun 24 05:30:40 PM PDT 24
Finished Jun 24 05:30:44 PM PDT 24
Peak memory 200576 kb
Host smart-4b03b945-df4a-48ca-83ac-41cb64753c8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897191674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1897191674
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2329088652
Short name T567
Test name
Test status
Simulation time 160566512 ps
CPU time 2.35 seconds
Started Jun 24 05:30:42 PM PDT 24
Finished Jun 24 05:30:48 PM PDT 24
Peak memory 209056 kb
Host smart-1d7b3f08-fb18-45a5-9e4b-73dfe382848c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329088652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2329088652
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2960268840
Short name T79
Test name
Test status
Simulation time 468197613 ps
CPU time 1.96 seconds
Started Jun 24 05:30:38 PM PDT 24
Finished Jun 24 05:30:41 PM PDT 24
Peak memory 200820 kb
Host smart-c5f9acd7-9ef3-4c3d-9dcc-95113613d137
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960268840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2960268840
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.830354189
Short name T92
Test name
Test status
Simulation time 173987212 ps
CPU time 1.22 seconds
Started Jun 24 05:30:39 PM PDT 24
Finished Jun 24 05:30:42 PM PDT 24
Peak memory 200732 kb
Host smart-5f89ee15-0694-449e-bd23-7e79cc80e6ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830354189 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.830354189
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2758396164
Short name T549
Test name
Test status
Simulation time 85624491 ps
CPU time 0.86 seconds
Started Jun 24 05:30:39 PM PDT 24
Finished Jun 24 05:30:41 PM PDT 24
Peak memory 200652 kb
Host smart-6711a2aa-d2d2-4c41-b409-dcba6660c3cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758396164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2758396164
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1406645103
Short name T573
Test name
Test status
Simulation time 110693096 ps
CPU time 1.28 seconds
Started Jun 24 05:30:41 PM PDT 24
Finished Jun 24 05:30:45 PM PDT 24
Peak memory 200828 kb
Host smart-9210b8a9-2d13-4e49-8baf-6c884c484464
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406645103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1406645103
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3506905840
Short name T583
Test name
Test status
Simulation time 104992208 ps
CPU time 1.47 seconds
Started Jun 24 05:30:40 PM PDT 24
Finished Jun 24 05:30:44 PM PDT 24
Peak memory 209024 kb
Host smart-98334559-23d7-4c94-bb59-a62cd9111bd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506905840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3506905840
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.710095069
Short name T117
Test name
Test status
Simulation time 893367734 ps
CPU time 2.97 seconds
Started Jun 24 05:30:41 PM PDT 24
Finished Jun 24 05:30:47 PM PDT 24
Peak memory 200908 kb
Host smart-81c96520-bea1-472a-945b-ad3c5fe9dcb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710095069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.
710095069
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1355881347
Short name T607
Test name
Test status
Simulation time 126997149 ps
CPU time 1.44 seconds
Started Jun 24 05:30:43 PM PDT 24
Finished Jun 24 05:30:48 PM PDT 24
Peak memory 208836 kb
Host smart-4b92264d-66d7-40a0-9081-f4fa45a35b3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355881347 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1355881347
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1470840806
Short name T552
Test name
Test status
Simulation time 75202243 ps
CPU time 0.83 seconds
Started Jun 24 05:30:42 PM PDT 24
Finished Jun 24 05:30:46 PM PDT 24
Peak memory 200656 kb
Host smart-08ded122-ffbb-43ac-bd60-a2ed9abf5d39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470840806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1470840806
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.814859816
Short name T595
Test name
Test status
Simulation time 125443244 ps
CPU time 1.08 seconds
Started Jun 24 05:30:41 PM PDT 24
Finished Jun 24 05:30:45 PM PDT 24
Peak memory 200644 kb
Host smart-d1f47a2d-b131-42f9-8956-a1e9e40f7854
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814859816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.814859816
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3186574921
Short name T615
Test name
Test status
Simulation time 174191486 ps
CPU time 2.49 seconds
Started Jun 24 05:30:40 PM PDT 24
Finished Jun 24 05:30:45 PM PDT 24
Peak memory 209024 kb
Host smart-a4b3a12a-f801-4152-8af7-5223ededf185
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186574921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3186574921
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2676826790
Short name T77
Test name
Test status
Simulation time 931415845 ps
CPU time 3.42 seconds
Started Jun 24 05:30:39 PM PDT 24
Finished Jun 24 05:30:44 PM PDT 24
Peak memory 200828 kb
Host smart-bf0b5edd-fa01-4261-97a3-8d85b223a241
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676826790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.2676826790
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.575906095
Short name T558
Test name
Test status
Simulation time 116897595 ps
CPU time 1.18 seconds
Started Jun 24 05:30:39 PM PDT 24
Finished Jun 24 05:30:41 PM PDT 24
Peak memory 211408 kb
Host smart-bfdb0bde-ab63-4d41-8f05-b81d1b506a6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575906095 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.575906095
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1196814207
Short name T66
Test name
Test status
Simulation time 79814673 ps
CPU time 0.88 seconds
Started Jun 24 05:30:41 PM PDT 24
Finished Jun 24 05:30:45 PM PDT 24
Peak memory 200652 kb
Host smart-1b6e515e-7477-49e4-8eb9-23884bbc87c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196814207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1196814207
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2362089431
Short name T588
Test name
Test status
Simulation time 250951124 ps
CPU time 1.57 seconds
Started Jun 24 05:30:40 PM PDT 24
Finished Jun 24 05:30:45 PM PDT 24
Peak memory 200852 kb
Host smart-a2d4f0d4-3212-472a-be33-71048824d5a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362089431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.2362089431
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.782633076
Short name T78
Test name
Test status
Simulation time 179239699 ps
CPU time 1.48 seconds
Started Jun 24 05:30:40 PM PDT 24
Finished Jun 24 05:30:44 PM PDT 24
Peak memory 211844 kb
Host smart-44b2c63b-5876-4cb2-96e3-0fc0ef3326fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782633076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.782633076
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.942044641
Short name T80
Test name
Test status
Simulation time 471113448 ps
CPU time 1.9 seconds
Started Jun 24 05:30:39 PM PDT 24
Finished Jun 24 05:30:44 PM PDT 24
Peak memory 200836 kb
Host smart-b5402070-e560-47d0-a14d-b84ecaf19e7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942044641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
942044641
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3357352096
Short name T555
Test name
Test status
Simulation time 201691948 ps
CPU time 1.38 seconds
Started Jun 24 05:30:40 PM PDT 24
Finished Jun 24 05:30:44 PM PDT 24
Peak memory 208848 kb
Host smart-d7c302d9-62af-4739-a290-b96aae4219b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357352096 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3357352096
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2506214150
Short name T604
Test name
Test status
Simulation time 95526214 ps
CPU time 0.9 seconds
Started Jun 24 05:30:38 PM PDT 24
Finished Jun 24 05:30:39 PM PDT 24
Peak memory 200676 kb
Host smart-1628a099-0ece-44ef-8a7a-169d4c6a01b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506214150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.2506214150
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2966350295
Short name T601
Test name
Test status
Simulation time 225574518 ps
CPU time 1.48 seconds
Started Jun 24 05:30:40 PM PDT 24
Finished Jun 24 05:30:45 PM PDT 24
Peak memory 200768 kb
Host smart-83fd1706-8dc2-4539-872b-0612885bbee5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966350295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.2966350295
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1061147251
Short name T84
Test name
Test status
Simulation time 188746329 ps
CPU time 2.69 seconds
Started Jun 24 05:30:46 PM PDT 24
Finished Jun 24 05:30:51 PM PDT 24
Peak memory 209008 kb
Host smart-ba5b5cf5-7e60-47c5-8c93-2c7ea8a34d5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061147251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1061147251
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3738819817
Short name T119
Test name
Test status
Simulation time 421873667 ps
CPU time 1.74 seconds
Started Jun 24 05:30:41 PM PDT 24
Finished Jun 24 05:30:46 PM PDT 24
Peak memory 200832 kb
Host smart-f3bb7b92-9fcc-459b-ace1-88c8e13d7394
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738819817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3738819817
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2888688656
Short name T616
Test name
Test status
Simulation time 127569442 ps
CPU time 1.34 seconds
Started Jun 24 05:30:43 PM PDT 24
Finished Jun 24 05:30:47 PM PDT 24
Peak memory 208924 kb
Host smart-7766d0f3-1c14-4ab0-836a-79ebc798d24b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888688656 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2888688656
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2338742419
Short name T104
Test name
Test status
Simulation time 58531747 ps
CPU time 0.75 seconds
Started Jun 24 05:30:40 PM PDT 24
Finished Jun 24 05:30:43 PM PDT 24
Peak memory 200572 kb
Host smart-b91ded9c-d555-4c6d-9f9c-7aca07493f4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338742419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2338742419
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1755495000
Short name T598
Test name
Test status
Simulation time 72947058 ps
CPU time 0.99 seconds
Started Jun 24 05:30:43 PM PDT 24
Finished Jun 24 05:30:47 PM PDT 24
Peak memory 200644 kb
Host smart-295f04c4-c835-4fe7-996c-9c0118263804
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755495000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1755495000
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3699965959
Short name T557
Test name
Test status
Simulation time 363197683 ps
CPU time 2.61 seconds
Started Jun 24 05:30:42 PM PDT 24
Finished Jun 24 05:30:47 PM PDT 24
Peak memory 209020 kb
Host smart-e45d60ab-da4a-48cb-90b9-e1e2bd51985e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699965959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3699965959
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1283167647
Short name T602
Test name
Test status
Simulation time 491652929 ps
CPU time 1.91 seconds
Started Jun 24 05:30:39 PM PDT 24
Finished Jun 24 05:30:42 PM PDT 24
Peak memory 200836 kb
Host smart-ea6b97ed-c59b-41d9-a97c-195dbacfeb12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283167647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1283167647
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.704096177
Short name T532
Test name
Test status
Simulation time 1231091892 ps
CPU time 5.8 seconds
Started Jun 24 05:34:55 PM PDT 24
Finished Jun 24 05:35:02 PM PDT 24
Peak memory 218460 kb
Host smart-eb85ef76-4d26-4e6b-8c07-eabba50ec7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704096177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.704096177
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.14023867
Short name T427
Test name
Test status
Simulation time 244620580 ps
CPU time 1.09 seconds
Started Jun 24 05:34:54 PM PDT 24
Finished Jun 24 05:34:55 PM PDT 24
Peak memory 218064 kb
Host smart-dd419f37-d966-4773-aae6-46f2ffe487dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14023867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.14023867
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_reset.2103598447
Short name T350
Test name
Test status
Simulation time 1078544265 ps
CPU time 4.55 seconds
Started Jun 24 05:34:53 PM PDT 24
Finished Jun 24 05:34:58 PM PDT 24
Peak memory 200812 kb
Host smart-765a7637-f12c-48f9-97ea-9367e8d5aee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103598447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2103598447
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.4159599298
Short name T531
Test name
Test status
Simulation time 171778100 ps
CPU time 1.18 seconds
Started Jun 24 05:35:06 PM PDT 24
Finished Jun 24 05:35:10 PM PDT 24
Peak memory 200700 kb
Host smart-eaea153c-70cf-430a-9d3e-4a45ad9dddb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159599298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.4159599298
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2375650048
Short name T193
Test name
Test status
Simulation time 195328508 ps
CPU time 1.36 seconds
Started Jun 24 05:34:53 PM PDT 24
Finished Jun 24 05:34:55 PM PDT 24
Peak memory 200884 kb
Host smart-12337aec-f22d-4483-b277-6d758f350eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375650048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2375650048
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.2519016721
Short name T484
Test name
Test status
Simulation time 3191799535 ps
CPU time 13.23 seconds
Started Jun 24 05:34:52 PM PDT 24
Finished Jun 24 05:35:06 PM PDT 24
Peak memory 200884 kb
Host smart-2c035b95-48d0-462d-ab41-67b12082ce78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519016721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2519016721
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1847103352
Short name T341
Test name
Test status
Simulation time 541405119 ps
CPU time 3.01 seconds
Started Jun 24 05:35:07 PM PDT 24
Finished Jun 24 05:35:12 PM PDT 24
Peak memory 200696 kb
Host smart-d452fce6-1573-4c06-aafb-bb67711eadfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847103352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1847103352
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.770130891
Short name T452
Test name
Test status
Simulation time 131161252 ps
CPU time 1.14 seconds
Started Jun 24 05:34:57 PM PDT 24
Finished Jun 24 05:34:59 PM PDT 24
Peak memory 200704 kb
Host smart-cac0aa12-4945-4b3a-aca5-e6ad1c8be222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770130891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.770130891
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3023139931
Short name T124
Test name
Test status
Simulation time 70786965 ps
CPU time 0.83 seconds
Started Jun 24 05:35:03 PM PDT 24
Finished Jun 24 05:35:06 PM PDT 24
Peak memory 200500 kb
Host smart-d4e931f5-6a05-482a-b838-af89e3e164ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023139931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3023139931
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2273923968
Short name T354
Test name
Test status
Simulation time 212874700 ps
CPU time 0.89 seconds
Started Jun 24 05:35:02 PM PDT 24
Finished Jun 24 05:35:04 PM PDT 24
Peak memory 200448 kb
Host smart-d10a480a-b310-4775-996b-ea2c7aaf838c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273923968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2273923968
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.4256382623
Short name T112
Test name
Test status
Simulation time 1635166956 ps
CPU time 5.75 seconds
Started Jun 24 05:35:01 PM PDT 24
Finished Jun 24 05:35:08 PM PDT 24
Peak memory 200888 kb
Host smart-7dbf65ce-b093-4918-9041-dad2bbd15aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256382623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.4256382623
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3901756366
Short name T72
Test name
Test status
Simulation time 8344340296 ps
CPU time 14.91 seconds
Started Jun 24 05:35:06 PM PDT 24
Finished Jun 24 05:35:23 PM PDT 24
Peak memory 217640 kb
Host smart-738591d4-9497-4833-bc9d-6d41493d22ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901756366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3901756366
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3799712329
Short name T222
Test name
Test status
Simulation time 168272373 ps
CPU time 1.11 seconds
Started Jun 24 05:35:24 PM PDT 24
Finished Jun 24 05:35:27 PM PDT 24
Peak memory 200700 kb
Host smart-84c7f11e-ae0e-4c29-ab88-ebf3d742a9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799712329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3799712329
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.2403867949
Short name T260
Test name
Test status
Simulation time 191898244 ps
CPU time 1.32 seconds
Started Jun 24 05:35:17 PM PDT 24
Finished Jun 24 05:35:19 PM PDT 24
Peak memory 200888 kb
Host smart-422b7454-b9e4-48f9-a1df-bbd1ff478c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403867949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2403867949
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2490355051
Short name T457
Test name
Test status
Simulation time 3243470793 ps
CPU time 12.85 seconds
Started Jun 24 05:35:05 PM PDT 24
Finished Jun 24 05:35:21 PM PDT 24
Peak memory 209168 kb
Host smart-7e35c10e-1422-4190-8037-a46e20131dcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490355051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2490355051
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.109726603
Short name T432
Test name
Test status
Simulation time 140912966 ps
CPU time 1.76 seconds
Started Jun 24 05:35:03 PM PDT 24
Finished Jun 24 05:35:08 PM PDT 24
Peak memory 208816 kb
Host smart-a9b1f239-d511-4316-affb-40a0b4c38bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109726603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.109726603
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.784596101
Short name T164
Test name
Test status
Simulation time 131232989 ps
CPU time 1.02 seconds
Started Jun 24 05:35:02 PM PDT 24
Finished Jun 24 05:35:05 PM PDT 24
Peak memory 200716 kb
Host smart-db3a4b55-99d7-4420-ab92-fcc4523e6662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784596101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.784596101
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1404298325
Short name T455
Test name
Test status
Simulation time 84563806 ps
CPU time 0.81 seconds
Started Jun 24 05:35:25 PM PDT 24
Finished Jun 24 05:35:28 PM PDT 24
Peak memory 200432 kb
Host smart-91c28248-7eaa-4e40-8e93-73c206ca3169
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404298325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1404298325
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1441448637
Short name T10
Test name
Test status
Simulation time 1217408443 ps
CPU time 5.15 seconds
Started Jun 24 05:35:38 PM PDT 24
Finished Jun 24 05:35:45 PM PDT 24
Peak memory 222480 kb
Host smart-4faee8d4-c69f-4d17-a1e4-4b279aa24adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441448637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1441448637
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1317373469
Short name T326
Test name
Test status
Simulation time 245287299 ps
CPU time 1.06 seconds
Started Jun 24 05:35:18 PM PDT 24
Finished Jun 24 05:35:20 PM PDT 24
Peak memory 218072 kb
Host smart-7c50d854-e357-43af-851c-648393a0b60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317373469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1317373469
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.1056424066
Short name T347
Test name
Test status
Simulation time 79735553 ps
CPU time 0.77 seconds
Started Jun 24 05:35:21 PM PDT 24
Finished Jun 24 05:35:23 PM PDT 24
Peak memory 200512 kb
Host smart-ed4d4641-5b09-42b2-90d2-30d3ed6101e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056424066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.1056424066
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2802607221
Short name T459
Test name
Test status
Simulation time 1343580693 ps
CPU time 6.13 seconds
Started Jun 24 05:35:12 PM PDT 24
Finished Jun 24 05:35:19 PM PDT 24
Peak memory 200884 kb
Host smart-2f51bc87-3f47-4598-9794-93054fbbf4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802607221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2802607221
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2601601818
Short name T367
Test name
Test status
Simulation time 97371824 ps
CPU time 1.01 seconds
Started Jun 24 05:35:11 PM PDT 24
Finished Jun 24 05:35:14 PM PDT 24
Peak memory 200712 kb
Host smart-7eb17c8c-8b2d-4177-b0ee-ab4404adb946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601601818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2601601818
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.3041876535
Short name T463
Test name
Test status
Simulation time 120121310 ps
CPU time 1.18 seconds
Started Jun 24 05:35:11 PM PDT 24
Finished Jun 24 05:35:13 PM PDT 24
Peak memory 200920 kb
Host smart-efa49b82-ddcd-4825-b06a-e40081c0173e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041876535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3041876535
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.977957430
Short name T348
Test name
Test status
Simulation time 7762087319 ps
CPU time 28.47 seconds
Started Jun 24 05:35:20 PM PDT 24
Finished Jun 24 05:35:50 PM PDT 24
Peak memory 200920 kb
Host smart-ecdda89c-bb95-46dc-a246-5e2cdd912f3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977957430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.977957430
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2212027715
Short name T396
Test name
Test status
Simulation time 347456517 ps
CPU time 2.26 seconds
Started Jun 24 05:35:09 PM PDT 24
Finished Jun 24 05:35:13 PM PDT 24
Peak memory 200692 kb
Host smart-dfb96501-2d2a-45ab-928e-e72b7bf3275d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212027715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2212027715
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2886431762
Short name T236
Test name
Test status
Simulation time 126199250 ps
CPU time 0.96 seconds
Started Jun 24 05:35:12 PM PDT 24
Finished Jun 24 05:35:14 PM PDT 24
Peak memory 200708 kb
Host smart-04776150-6088-420a-9738-05ec40f02a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886431762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2886431762
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.444086886
Short name T467
Test name
Test status
Simulation time 63953205 ps
CPU time 0.78 seconds
Started Jun 24 05:35:13 PM PDT 24
Finished Jun 24 05:35:15 PM PDT 24
Peak memory 200496 kb
Host smart-770bee4a-8f0c-4fe9-a2b0-adcaf652e56b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444086886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.444086886
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2548665242
Short name T346
Test name
Test status
Simulation time 1224673882 ps
CPU time 5.48 seconds
Started Jun 24 05:35:30 PM PDT 24
Finished Jun 24 05:35:37 PM PDT 24
Peak memory 217940 kb
Host smart-e47f939b-f7a9-4ba2-a60f-3d3e06bed5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548665242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2548665242
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3203283856
Short name T337
Test name
Test status
Simulation time 246166208 ps
CPU time 1.07 seconds
Started Jun 24 05:35:29 PM PDT 24
Finished Jun 24 05:35:32 PM PDT 24
Peak memory 218060 kb
Host smart-d2932a3a-a877-45cd-9ee0-2cb89f4ca8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203283856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3203283856
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1544578992
Short name T15
Test name
Test status
Simulation time 132161955 ps
CPU time 0.79 seconds
Started Jun 24 05:35:27 PM PDT 24
Finished Jun 24 05:35:30 PM PDT 24
Peak memory 200444 kb
Host smart-906e4ae3-1497-4c36-95f7-3f35ff0111da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544578992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1544578992
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.3808676402
Short name T247
Test name
Test status
Simulation time 1023408216 ps
CPU time 4.73 seconds
Started Jun 24 05:35:12 PM PDT 24
Finished Jun 24 05:35:17 PM PDT 24
Peak memory 200808 kb
Host smart-7485fdc6-cdcd-4e6c-85ac-17465486eea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808676402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3808676402
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3285494277
Short name T167
Test name
Test status
Simulation time 108327890 ps
CPU time 1.05 seconds
Started Jun 24 05:35:15 PM PDT 24
Finished Jun 24 05:35:17 PM PDT 24
Peak memory 200232 kb
Host smart-ff3db994-8f93-40a2-9896-0345cde9d094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285494277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3285494277
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2412010395
Short name T324
Test name
Test status
Simulation time 250326295 ps
CPU time 1.47 seconds
Started Jun 24 05:35:11 PM PDT 24
Finished Jun 24 05:35:14 PM PDT 24
Peak memory 200872 kb
Host smart-bf20517a-a1ad-4c1c-a5c0-1a4d7ef3e2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412010395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2412010395
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.4025720300
Short name T284
Test name
Test status
Simulation time 6183333159 ps
CPU time 21.95 seconds
Started Jun 24 05:35:14 PM PDT 24
Finished Jun 24 05:35:36 PM PDT 24
Peak memory 200964 kb
Host smart-05a1cc03-3536-4281-945d-f450110ee7da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025720300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.4025720300
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2093329253
Short name T351
Test name
Test status
Simulation time 121787988 ps
CPU time 1.56 seconds
Started Jun 24 05:35:17 PM PDT 24
Finished Jun 24 05:35:19 PM PDT 24
Peak memory 200712 kb
Host smart-358f9ac2-c165-4490-a017-ac87e5403c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093329253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2093329253
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3798743917
Short name T295
Test name
Test status
Simulation time 199000034 ps
CPU time 1.24 seconds
Started Jun 24 05:35:18 PM PDT 24
Finished Jun 24 05:35:20 PM PDT 24
Peak memory 200672 kb
Host smart-444ba799-c5b2-4790-ab45-158eef4beff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798743917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3798743917
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1300745553
Short name T328
Test name
Test status
Simulation time 84440149 ps
CPU time 0.83 seconds
Started Jun 24 05:35:12 PM PDT 24
Finished Jun 24 05:35:13 PM PDT 24
Peak memory 200492 kb
Host smart-0af51395-1ad9-43d2-b391-1b80f94f1b0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300745553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1300745553
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.185198233
Short name T42
Test name
Test status
Simulation time 1886211177 ps
CPU time 7.66 seconds
Started Jun 24 05:35:14 PM PDT 24
Finished Jun 24 05:35:23 PM PDT 24
Peak memory 217964 kb
Host smart-7041cad8-1f6e-4452-9625-224b96c1f6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185198233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.185198233
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3247513686
Short name T289
Test name
Test status
Simulation time 252870622 ps
CPU time 1.06 seconds
Started Jun 24 05:35:12 PM PDT 24
Finished Jun 24 05:35:14 PM PDT 24
Peak memory 218084 kb
Host smart-82e5dd92-57be-4ab2-9429-1c840c16bbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247513686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3247513686
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.661591985
Short name T441
Test name
Test status
Simulation time 190356322 ps
CPU time 0.94 seconds
Started Jun 24 05:35:17 PM PDT 24
Finished Jun 24 05:35:19 PM PDT 24
Peak memory 200468 kb
Host smart-464ecccb-4cdd-445b-ae1e-763bd65d7028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661591985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.661591985
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2266511138
Short name T415
Test name
Test status
Simulation time 786670278 ps
CPU time 4.23 seconds
Started Jun 24 05:35:16 PM PDT 24
Finished Jun 24 05:35:21 PM PDT 24
Peak memory 200736 kb
Host smart-dd068caf-8405-4ae6-b5a7-787641a6ca45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266511138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2266511138
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3280393690
Short name T501
Test name
Test status
Simulation time 110992074 ps
CPU time 1.14 seconds
Started Jun 24 05:35:16 PM PDT 24
Finished Jun 24 05:35:18 PM PDT 24
Peak memory 200864 kb
Host smart-2495c608-8f59-4ab1-8381-7ed8286d9616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280393690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3280393690
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.1564391645
Short name T398
Test name
Test status
Simulation time 3805680769 ps
CPU time 18.74 seconds
Started Jun 24 05:35:26 PM PDT 24
Finished Jun 24 05:35:46 PM PDT 24
Peak memory 200840 kb
Host smart-4544c0b4-7bb2-4919-b0e7-06b87f8d1fc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564391645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1564391645
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.4037061295
Short name T425
Test name
Test status
Simulation time 125564648 ps
CPU time 1.65 seconds
Started Jun 24 05:35:30 PM PDT 24
Finished Jun 24 05:35:33 PM PDT 24
Peak memory 208852 kb
Host smart-45b57a22-a58a-4c65-a589-e0e3d90d38ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037061295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.4037061295
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3757371398
Short name T523
Test name
Test status
Simulation time 92249634 ps
CPU time 0.95 seconds
Started Jun 24 05:35:16 PM PDT 24
Finished Jun 24 05:35:17 PM PDT 24
Peak memory 200692 kb
Host smart-59f810d8-409e-4f8a-bfd1-c68425c8b5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757371398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3757371398
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1328895272
Short name T291
Test name
Test status
Simulation time 65569975 ps
CPU time 0.76 seconds
Started Jun 24 05:35:11 PM PDT 24
Finished Jun 24 05:35:13 PM PDT 24
Peak memory 200516 kb
Host smart-a9033652-ce66-466e-9755-7132ecd45c0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328895272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1328895272
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.4276939821
Short name T60
Test name
Test status
Simulation time 2354472037 ps
CPU time 8.63 seconds
Started Jun 24 05:35:17 PM PDT 24
Finished Jun 24 05:35:27 PM PDT 24
Peak memory 222496 kb
Host smart-9d02cf11-ef15-4d49-a0d6-4f031050ce4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276939821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.4276939821
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2091651697
Short name T371
Test name
Test status
Simulation time 244153884 ps
CPU time 1.18 seconds
Started Jun 24 05:35:22 PM PDT 24
Finished Jun 24 05:35:25 PM PDT 24
Peak memory 218072 kb
Host smart-d444d196-712c-409c-a853-0647b34c2b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091651697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2091651697
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.742567028
Short name T170
Test name
Test status
Simulation time 228733448 ps
CPU time 0.9 seconds
Started Jun 24 05:35:12 PM PDT 24
Finished Jun 24 05:35:14 PM PDT 24
Peak memory 200436 kb
Host smart-4f297223-bfb6-490c-9c7a-a9e008d808d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742567028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.742567028
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.1430999139
Short name T54
Test name
Test status
Simulation time 1555165668 ps
CPU time 6.62 seconds
Started Jun 24 05:35:28 PM PDT 24
Finished Jun 24 05:35:36 PM PDT 24
Peak memory 200904 kb
Host smart-c2c5a5db-0097-4474-bf3e-4fcce3dd1d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430999139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1430999139
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2477959918
Short name T143
Test name
Test status
Simulation time 160537487 ps
CPU time 1.11 seconds
Started Jun 24 05:35:16 PM PDT 24
Finished Jun 24 05:35:18 PM PDT 24
Peak memory 200552 kb
Host smart-614000e3-9128-4e92-a79b-dfbc6ce454eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477959918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2477959918
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2534473927
Short name T185
Test name
Test status
Simulation time 124691545 ps
CPU time 1.25 seconds
Started Jun 24 05:35:17 PM PDT 24
Finished Jun 24 05:35:20 PM PDT 24
Peak memory 200848 kb
Host smart-b889ac02-5265-4067-bf68-b92035ca5a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534473927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2534473927
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3205813880
Short name T478
Test name
Test status
Simulation time 350625730 ps
CPU time 2.13 seconds
Started Jun 24 05:35:23 PM PDT 24
Finished Jun 24 05:35:28 PM PDT 24
Peak memory 208884 kb
Host smart-ee189bcb-d87b-4d98-af7b-beddd9b8ea3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205813880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3205813880
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3357796065
Short name T200
Test name
Test status
Simulation time 76567115 ps
CPU time 0.82 seconds
Started Jun 24 05:35:25 PM PDT 24
Finished Jun 24 05:35:28 PM PDT 24
Peak memory 200444 kb
Host smart-cc427504-ad66-4ddc-a7b5-059640ae7149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357796065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3357796065
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1086428846
Short name T381
Test name
Test status
Simulation time 2175464597 ps
CPU time 8.1 seconds
Started Jun 24 05:35:20 PM PDT 24
Finished Jun 24 05:35:28 PM PDT 24
Peak memory 218252 kb
Host smart-33ebfdcc-99c3-4fdf-a757-fb53ff770eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086428846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1086428846
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2714936991
Short name T218
Test name
Test status
Simulation time 243358867 ps
CPU time 1.17 seconds
Started Jun 24 05:35:26 PM PDT 24
Finished Jun 24 05:35:29 PM PDT 24
Peak memory 218076 kb
Host smart-57367df2-7bf9-49ad-be82-38b979c46a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714936991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2714936991
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2099861913
Short name T477
Test name
Test status
Simulation time 121566021 ps
CPU time 0.84 seconds
Started Jun 24 05:35:29 PM PDT 24
Finished Jun 24 05:35:31 PM PDT 24
Peak memory 200512 kb
Host smart-a369534b-e170-43c1-a8f9-2aee3d456cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099861913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2099861913
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.936232812
Short name T228
Test name
Test status
Simulation time 1256133842 ps
CPU time 6.17 seconds
Started Jun 24 05:35:37 PM PDT 24
Finished Jun 24 05:35:45 PM PDT 24
Peak memory 200936 kb
Host smart-375aaac0-86d2-47b7-a977-35b0a76ed418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936232812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.936232812
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2137070648
Short name T495
Test name
Test status
Simulation time 178164724 ps
CPU time 1.23 seconds
Started Jun 24 05:35:40 PM PDT 24
Finished Jun 24 05:35:44 PM PDT 24
Peak memory 200600 kb
Host smart-aedb375a-31a4-419c-b3c0-c34dde852e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137070648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2137070648
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.4163837987
Short name T150
Test name
Test status
Simulation time 248734678 ps
CPU time 1.52 seconds
Started Jun 24 05:35:12 PM PDT 24
Finished Jun 24 05:35:14 PM PDT 24
Peak memory 201112 kb
Host smart-53f8e99a-8df7-44da-87c4-21b02d950549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163837987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.4163837987
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1408640930
Short name T319
Test name
Test status
Simulation time 9621026846 ps
CPU time 34.7 seconds
Started Jun 24 05:35:22 PM PDT 24
Finished Jun 24 05:35:57 PM PDT 24
Peak memory 209168 kb
Host smart-fa8e298e-50c5-4b05-8bd9-a7b963f4d271
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408640930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1408640930
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2612530081
Short name T366
Test name
Test status
Simulation time 134486154 ps
CPU time 1.75 seconds
Started Jun 24 05:35:37 PM PDT 24
Finished Jun 24 05:35:40 PM PDT 24
Peak memory 200696 kb
Host smart-7685f9b2-fbc9-4dec-8d9a-edf876e0b9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612530081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2612530081
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.73148357
Short name T393
Test name
Test status
Simulation time 152108130 ps
CPU time 1.11 seconds
Started Jun 24 05:35:34 PM PDT 24
Finished Jun 24 05:35:36 PM PDT 24
Peak memory 200700 kb
Host smart-58b28a40-9e6f-4431-b4bf-307838057033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73148357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.73148357
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2186830922
Short name T437
Test name
Test status
Simulation time 72289862 ps
CPU time 0.82 seconds
Started Jun 24 05:35:23 PM PDT 24
Finished Jun 24 05:35:25 PM PDT 24
Peak memory 200492 kb
Host smart-001239e4-9546-4233-a677-4179d074091d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186830922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2186830922
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2802510356
Short name T254
Test name
Test status
Simulation time 243623681 ps
CPU time 1.17 seconds
Started Jun 24 05:35:20 PM PDT 24
Finished Jun 24 05:35:22 PM PDT 24
Peak memory 218044 kb
Host smart-5917f3b9-dd64-413e-92aa-6f169f309645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802510356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2802510356
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3260466753
Short name T281
Test name
Test status
Simulation time 210325716 ps
CPU time 0.94 seconds
Started Jun 24 05:35:40 PM PDT 24
Finished Jun 24 05:35:42 PM PDT 24
Peak memory 200512 kb
Host smart-5932e38c-8678-4f74-b376-50ad45768335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260466753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3260466753
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1821173863
Short name T229
Test name
Test status
Simulation time 1238922365 ps
CPU time 4.98 seconds
Started Jun 24 05:35:29 PM PDT 24
Finished Jun 24 05:35:35 PM PDT 24
Peak memory 200884 kb
Host smart-3bfc8a31-6a2d-4e05-9195-d1bb2542fbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821173863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1821173863
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2929418534
Short name T518
Test name
Test status
Simulation time 171832880 ps
CPU time 1.18 seconds
Started Jun 24 05:35:39 PM PDT 24
Finished Jun 24 05:35:41 PM PDT 24
Peak memory 200684 kb
Host smart-d5703e06-744b-4105-85a1-d4a583172ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929418534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2929418534
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1398613815
Short name T190
Test name
Test status
Simulation time 120454111 ps
CPU time 1.23 seconds
Started Jun 24 05:35:24 PM PDT 24
Finished Jun 24 05:35:28 PM PDT 24
Peak memory 200908 kb
Host smart-504ae625-e91b-4c0f-9d69-715037c461fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398613815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1398613815
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2014301818
Short name T378
Test name
Test status
Simulation time 5538737764 ps
CPU time 27.13 seconds
Started Jun 24 05:35:24 PM PDT 24
Finished Jun 24 05:35:54 PM PDT 24
Peak memory 209144 kb
Host smart-ce9d38c1-bcff-4a7a-8985-547645ba9ded
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014301818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2014301818
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.3698920522
Short name T430
Test name
Test status
Simulation time 465997354 ps
CPU time 2.73 seconds
Started Jun 24 05:35:24 PM PDT 24
Finished Jun 24 05:35:29 PM PDT 24
Peak memory 200688 kb
Host smart-ba9e1c35-e089-49b0-8a62-175175dc38c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698920522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.3698920522
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1417429544
Short name T63
Test name
Test status
Simulation time 131772659 ps
CPU time 1.09 seconds
Started Jun 24 05:35:35 PM PDT 24
Finished Jun 24 05:35:37 PM PDT 24
Peak memory 200708 kb
Host smart-1cda9fe6-cabe-43e0-89cc-f35f2d8bb2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417429544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1417429544
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.4223092896
Short name T469
Test name
Test status
Simulation time 75071249 ps
CPU time 0.81 seconds
Started Jun 24 05:35:29 PM PDT 24
Finished Jun 24 05:35:31 PM PDT 24
Peak memory 200496 kb
Host smart-8e1816f9-45a8-4d4a-8bec-62253e904d4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223092896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.4223092896
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1104912227
Short name T186
Test name
Test status
Simulation time 1232840819 ps
CPU time 6.2 seconds
Started Jun 24 05:35:37 PM PDT 24
Finished Jun 24 05:35:45 PM PDT 24
Peak memory 218420 kb
Host smart-2893b91f-f4b7-4c05-a9bc-9be0669a53d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104912227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1104912227
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.672616729
Short name T189
Test name
Test status
Simulation time 243864238 ps
CPU time 1.08 seconds
Started Jun 24 05:35:38 PM PDT 24
Finished Jun 24 05:35:40 PM PDT 24
Peak memory 218100 kb
Host smart-fba34338-160b-4a01-a9a3-29a195c8bd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672616729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.672616729
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.696074765
Short name T239
Test name
Test status
Simulation time 127706954 ps
CPU time 0.79 seconds
Started Jun 24 05:35:38 PM PDT 24
Finished Jun 24 05:35:40 PM PDT 24
Peak memory 200488 kb
Host smart-0d3de185-ae9d-4568-b844-ce8874acf918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696074765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.696074765
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.736812901
Short name T246
Test name
Test status
Simulation time 867117607 ps
CPU time 4.48 seconds
Started Jun 24 05:35:23 PM PDT 24
Finished Jun 24 05:35:29 PM PDT 24
Peak memory 200904 kb
Host smart-22648018-ad4e-4542-b5cb-515a51072843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736812901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.736812901
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3432811215
Short name T125
Test name
Test status
Simulation time 103525004 ps
CPU time 1 seconds
Started Jun 24 05:35:22 PM PDT 24
Finished Jun 24 05:35:24 PM PDT 24
Peak memory 200688 kb
Host smart-43b45450-d714-49b2-afbc-9fd0fa01a43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432811215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3432811215
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.4056814165
Short name T408
Test name
Test status
Simulation time 201900267 ps
CPU time 1.38 seconds
Started Jun 24 05:35:25 PM PDT 24
Finished Jun 24 05:35:29 PM PDT 24
Peak memory 200888 kb
Host smart-9465801a-9fe1-490f-8de9-f51b2808008d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056814165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.4056814165
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.963056974
Short name T365
Test name
Test status
Simulation time 2169208785 ps
CPU time 7.75 seconds
Started Jun 24 05:35:23 PM PDT 24
Finished Jun 24 05:35:33 PM PDT 24
Peak memory 200964 kb
Host smart-8923fa92-3c2a-4d9f-ab42-c57c27505759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963056974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.963056974
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.1061692299
Short name T380
Test name
Test status
Simulation time 132581449 ps
CPU time 1.74 seconds
Started Jun 24 05:35:23 PM PDT 24
Finished Jun 24 05:35:26 PM PDT 24
Peak memory 200712 kb
Host smart-73d3b4e6-6836-4993-be60-02ce0607433d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061692299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1061692299
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.4067015308
Short name T230
Test name
Test status
Simulation time 127398474 ps
CPU time 0.98 seconds
Started Jun 24 05:35:40 PM PDT 24
Finished Jun 24 05:35:43 PM PDT 24
Peak memory 200704 kb
Host smart-931e0c26-e9bd-4dd2-a564-99cc31704e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067015308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.4067015308
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.4146098084
Short name T395
Test name
Test status
Simulation time 65859453 ps
CPU time 0.85 seconds
Started Jun 24 05:35:28 PM PDT 24
Finished Jun 24 05:35:30 PM PDT 24
Peak memory 200488 kb
Host smart-b10cf175-6101-4ce9-b210-d4f0abe3a342
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146098084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.4146098084
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.247865250
Short name T255
Test name
Test status
Simulation time 1902257788 ps
CPU time 6.76 seconds
Started Jun 24 05:35:33 PM PDT 24
Finished Jun 24 05:35:40 PM PDT 24
Peak memory 218328 kb
Host smart-9af4a816-d487-4288-9138-3d1ec094f5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247865250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.247865250
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3851652184
Short name T399
Test name
Test status
Simulation time 245746944 ps
CPU time 1.07 seconds
Started Jun 24 05:35:23 PM PDT 24
Finished Jun 24 05:35:25 PM PDT 24
Peak memory 218056 kb
Host smart-756762b4-49f7-49e8-a0a1-8271178a97e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851652184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3851652184
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.892560970
Short name T315
Test name
Test status
Simulation time 198999569 ps
CPU time 0.89 seconds
Started Jun 24 05:35:41 PM PDT 24
Finished Jun 24 05:35:44 PM PDT 24
Peak memory 200484 kb
Host smart-cd9cc5f8-4041-4986-9d3c-c5350f818acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892560970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.892560970
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2778474351
Short name T298
Test name
Test status
Simulation time 1651089228 ps
CPU time 6.76 seconds
Started Jun 24 05:35:36 PM PDT 24
Finished Jun 24 05:35:43 PM PDT 24
Peak memory 200904 kb
Host smart-3f087d0b-0d42-4d82-a9c4-f54ef869e00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778474351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2778474351
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3621051853
Short name T345
Test name
Test status
Simulation time 98032848 ps
CPU time 1.03 seconds
Started Jun 24 05:35:30 PM PDT 24
Finished Jun 24 05:35:32 PM PDT 24
Peak memory 200704 kb
Host smart-dd45f147-294f-449a-8954-221cb549b91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621051853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3621051853
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3706265246
Short name T359
Test name
Test status
Simulation time 121280013 ps
CPU time 1.21 seconds
Started Jun 24 05:35:22 PM PDT 24
Finished Jun 24 05:35:25 PM PDT 24
Peak memory 200884 kb
Host smart-ffdd8e75-5ad5-4626-befc-f9fe044f990c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706265246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3706265246
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.2505500833
Short name T448
Test name
Test status
Simulation time 11693418635 ps
CPU time 39.3 seconds
Started Jun 24 05:35:24 PM PDT 24
Finished Jun 24 05:36:06 PM PDT 24
Peak memory 209084 kb
Host smart-4493f428-4d9a-47fe-8cea-295abbe17e16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505500833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2505500833
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1046382654
Short name T215
Test name
Test status
Simulation time 135944711 ps
CPU time 1.63 seconds
Started Jun 24 05:35:36 PM PDT 24
Finished Jun 24 05:35:38 PM PDT 24
Peak memory 208884 kb
Host smart-ffa8efca-3d2a-4993-bb08-f182dc90fe0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046382654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1046382654
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.702643172
Short name T43
Test name
Test status
Simulation time 67789739 ps
CPU time 0.79 seconds
Started Jun 24 05:35:20 PM PDT 24
Finished Jun 24 05:35:22 PM PDT 24
Peak memory 200700 kb
Host smart-d48bb9e9-86e9-4ef1-a952-8d0d1b208bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702643172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.702643172
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1999297582
Short name T269
Test name
Test status
Simulation time 61576607 ps
CPU time 0.83 seconds
Started Jun 24 05:35:23 PM PDT 24
Finished Jun 24 05:35:26 PM PDT 24
Peak memory 200496 kb
Host smart-f10ff382-5914-4847-ba86-c35caee71ecf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999297582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1999297582
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.228470908
Short name T496
Test name
Test status
Simulation time 1892221934 ps
CPU time 7.2 seconds
Started Jun 24 05:35:29 PM PDT 24
Finished Jun 24 05:35:37 PM PDT 24
Peak memory 222388 kb
Host smart-782ca9dd-4d69-4e7f-a171-388691bce308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228470908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.228470908
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2778999666
Short name T152
Test name
Test status
Simulation time 244497521 ps
CPU time 1.04 seconds
Started Jun 24 05:35:22 PM PDT 24
Finished Jun 24 05:35:24 PM PDT 24
Peak memory 218092 kb
Host smart-eac7f8ff-3513-4e3b-805f-f474a08053e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778999666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2778999666
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.4273826971
Short name T342
Test name
Test status
Simulation time 172279037 ps
CPU time 0.9 seconds
Started Jun 24 05:35:23 PM PDT 24
Finished Jun 24 05:35:25 PM PDT 24
Peak memory 200496 kb
Host smart-7b805028-933e-4cd9-b07b-d2f0caf49c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273826971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.4273826971
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.190513119
Short name T524
Test name
Test status
Simulation time 678409693 ps
CPU time 3.88 seconds
Started Jun 24 05:35:22 PM PDT 24
Finished Jun 24 05:35:28 PM PDT 24
Peak memory 200888 kb
Host smart-460733e2-0e25-4859-b73a-52393a8d6064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190513119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.190513119
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2786268050
Short name T286
Test name
Test status
Simulation time 147618546 ps
CPU time 1.15 seconds
Started Jun 24 05:35:20 PM PDT 24
Finished Jun 24 05:35:22 PM PDT 24
Peak memory 200696 kb
Host smart-b106d704-7c09-4e62-a053-4adc458e08e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786268050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2786268050
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1575368836
Short name T440
Test name
Test status
Simulation time 118234286 ps
CPU time 1.2 seconds
Started Jun 24 05:35:34 PM PDT 24
Finished Jun 24 05:35:36 PM PDT 24
Peak memory 200944 kb
Host smart-e23ab415-ce5a-4754-86a5-5b5150a99cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575368836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1575368836
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.313955119
Short name T59
Test name
Test status
Simulation time 4883616878 ps
CPU time 20.59 seconds
Started Jun 24 05:35:23 PM PDT 24
Finished Jun 24 05:35:46 PM PDT 24
Peak memory 210912 kb
Host smart-55c55623-88d2-4447-99fc-c8639e7709e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313955119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.313955119
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3041806860
Short name T436
Test name
Test status
Simulation time 397904699 ps
CPU time 2.28 seconds
Started Jun 24 05:35:32 PM PDT 24
Finished Jun 24 05:35:35 PM PDT 24
Peak memory 200876 kb
Host smart-10eec020-07ae-4de1-8010-4c270eedbfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041806860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3041806860
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.4178055067
Short name T139
Test name
Test status
Simulation time 136691511 ps
CPU time 1.25 seconds
Started Jun 24 05:35:21 PM PDT 24
Finished Jun 24 05:35:23 PM PDT 24
Peak memory 200704 kb
Host smart-b4f62024-5398-4dd0-8e92-b944c0ac8983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178055067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.4178055067
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.3123692597
Short name T242
Test name
Test status
Simulation time 78281544 ps
CPU time 0.82 seconds
Started Jun 24 05:35:37 PM PDT 24
Finished Jun 24 05:35:39 PM PDT 24
Peak memory 200496 kb
Host smart-3dde1922-033f-4218-8e9f-2bf6a35220c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123692597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3123692597
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.4139929917
Short name T49
Test name
Test status
Simulation time 1895877860 ps
CPU time 7.7 seconds
Started Jun 24 05:35:23 PM PDT 24
Finished Jun 24 05:35:32 PM PDT 24
Peak memory 222456 kb
Host smart-ffe50af8-b4bc-4618-bc09-3aa25f4f6c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139929917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.4139929917
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3049135871
Short name T301
Test name
Test status
Simulation time 244450468 ps
CPU time 1.01 seconds
Started Jun 24 05:35:20 PM PDT 24
Finished Jun 24 05:35:22 PM PDT 24
Peak memory 218064 kb
Host smart-64dd1990-1d29-4caa-8914-5e648555025c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049135871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3049135871
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.464563212
Short name T423
Test name
Test status
Simulation time 136163401 ps
CPU time 0.83 seconds
Started Jun 24 05:35:23 PM PDT 24
Finished Jun 24 05:35:26 PM PDT 24
Peak memory 200472 kb
Host smart-480ace65-d36d-496b-ad06-72c9f06ec112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464563212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.464563212
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.87892420
Short name T451
Test name
Test status
Simulation time 915203253 ps
CPU time 4.58 seconds
Started Jun 24 05:35:23 PM PDT 24
Finished Jun 24 05:35:30 PM PDT 24
Peak memory 200876 kb
Host smart-d881bc8c-ef33-4239-a68b-814706024229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87892420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.87892420
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3216298919
Short name T431
Test name
Test status
Simulation time 143867428 ps
CPU time 1.14 seconds
Started Jun 24 05:35:36 PM PDT 24
Finished Jun 24 05:35:38 PM PDT 24
Peak memory 200872 kb
Host smart-ed2b8f4e-5dc9-4599-8f66-a1b7bd909c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216298919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3216298919
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.1579558291
Short name T483
Test name
Test status
Simulation time 121077387 ps
CPU time 1.23 seconds
Started Jun 24 05:35:23 PM PDT 24
Finished Jun 24 05:35:27 PM PDT 24
Peak memory 200884 kb
Host smart-b548cd4f-2b96-440c-a5a0-e2657a3fc8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579558291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1579558291
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3900764895
Short name T340
Test name
Test status
Simulation time 362693173 ps
CPU time 2.1 seconds
Started Jun 24 05:35:23 PM PDT 24
Finished Jun 24 05:35:28 PM PDT 24
Peak memory 208892 kb
Host smart-b691310b-6007-465c-afe5-0fbe50624a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900764895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3900764895
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1218077949
Short name T251
Test name
Test status
Simulation time 148079127 ps
CPU time 1.1 seconds
Started Jun 24 05:35:22 PM PDT 24
Finished Jun 24 05:35:23 PM PDT 24
Peak memory 200720 kb
Host smart-d602942f-cf9d-482b-9e04-5e305dc18fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218077949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1218077949
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1119469671
Short name T299
Test name
Test status
Simulation time 64113641 ps
CPU time 0.75 seconds
Started Jun 24 05:35:01 PM PDT 24
Finished Jun 24 05:35:04 PM PDT 24
Peak memory 200400 kb
Host smart-cee67ea0-8fc0-4ecd-a85f-a9cb15857969
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119469671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1119469671
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.4131208312
Short name T352
Test name
Test status
Simulation time 1224202062 ps
CPU time 6.22 seconds
Started Jun 24 05:35:02 PM PDT 24
Finished Jun 24 05:35:10 PM PDT 24
Peak memory 222308 kb
Host smart-54520d85-34e7-4cdb-9c78-b0e109fd33c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131208312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.4131208312
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.206598879
Short name T188
Test name
Test status
Simulation time 243948776 ps
CPU time 1.06 seconds
Started Jun 24 05:35:26 PM PDT 24
Finished Jun 24 05:35:29 PM PDT 24
Peak memory 218064 kb
Host smart-51ff0891-1693-450e-a8ca-3610496ac082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206598879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.206598879
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3137091451
Short name T517
Test name
Test status
Simulation time 129855489 ps
CPU time 0.84 seconds
Started Jun 24 05:35:05 PM PDT 24
Finished Jun 24 05:35:09 PM PDT 24
Peak memory 200508 kb
Host smart-485d1f58-3789-47d8-8a9a-6bddc190b2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137091451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3137091451
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2136670155
Short name T412
Test name
Test status
Simulation time 1227291774 ps
CPU time 5.38 seconds
Started Jun 24 05:35:02 PM PDT 24
Finished Jun 24 05:35:09 PM PDT 24
Peak memory 200792 kb
Host smart-880bb686-b759-4412-9548-cc8412270b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136670155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2136670155
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.4164855101
Short name T74
Test name
Test status
Simulation time 16523252433 ps
CPU time 28.23 seconds
Started Jun 24 05:35:04 PM PDT 24
Finished Jun 24 05:35:35 PM PDT 24
Peak memory 217688 kb
Host smart-17bd4d2a-092d-42b3-afd1-6ed5056d281b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164855101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.4164855101
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2897714745
Short name T214
Test name
Test status
Simulation time 153953183 ps
CPU time 1.16 seconds
Started Jun 24 05:35:05 PM PDT 24
Finished Jun 24 05:35:09 PM PDT 24
Peak memory 200692 kb
Host smart-c7adc3ab-67c8-44a5-831d-44c9b02a043c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897714745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2897714745
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.836093070
Short name T141
Test name
Test status
Simulation time 200332452 ps
CPU time 1.35 seconds
Started Jun 24 05:35:03 PM PDT 24
Finished Jun 24 05:35:07 PM PDT 24
Peak memory 200884 kb
Host smart-a48f9401-f466-471b-8d2c-c7cbd419ebd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836093070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.836093070
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.3933095326
Short name T224
Test name
Test status
Simulation time 4469191819 ps
CPU time 14.35 seconds
Started Jun 24 05:35:19 PM PDT 24
Finished Jun 24 05:35:34 PM PDT 24
Peak memory 209136 kb
Host smart-e7a64bac-5cf8-4b1c-8afa-4d868da6bc2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933095326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3933095326
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1988595625
Short name T312
Test name
Test status
Simulation time 415780908 ps
CPU time 2.32 seconds
Started Jun 24 05:35:00 PM PDT 24
Finished Jun 24 05:35:03 PM PDT 24
Peak memory 200692 kb
Host smart-05fc3aad-0e7f-4e01-8c6b-27e15f62da3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988595625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1988595625
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1675841359
Short name T290
Test name
Test status
Simulation time 139866917 ps
CPU time 1.03 seconds
Started Jun 24 05:35:04 PM PDT 24
Finished Jun 24 05:35:08 PM PDT 24
Peak memory 200636 kb
Host smart-0c852c73-94c9-4187-8423-46026c665ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675841359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1675841359
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2845900134
Short name T163
Test name
Test status
Simulation time 68820984 ps
CPU time 0.8 seconds
Started Jun 24 05:35:49 PM PDT 24
Finished Jun 24 05:35:52 PM PDT 24
Peak memory 200496 kb
Host smart-1c997370-1c01-4a5f-a656-c28cfc73034c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845900134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2845900134
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2480004619
Short name T487
Test name
Test status
Simulation time 1224048610 ps
CPU time 5.52 seconds
Started Jun 24 05:35:43 PM PDT 24
Finished Jun 24 05:35:52 PM PDT 24
Peak memory 218120 kb
Host smart-650a649d-cb3a-4ebc-aaae-66e16f5e0b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480004619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2480004619
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.524181327
Short name T364
Test name
Test status
Simulation time 244693793 ps
CPU time 1.07 seconds
Started Jun 24 05:35:31 PM PDT 24
Finished Jun 24 05:35:33 PM PDT 24
Peak memory 218088 kb
Host smart-b287f186-42f5-44f8-a4da-9e858cfaef4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524181327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.524181327
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.233251272
Short name T389
Test name
Test status
Simulation time 172749937 ps
CPU time 0.94 seconds
Started Jun 24 05:35:45 PM PDT 24
Finished Jun 24 05:35:49 PM PDT 24
Peak memory 200488 kb
Host smart-66f0a0f3-f6c3-4504-813c-4e34f6b30d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233251272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.233251272
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.884643137
Short name T94
Test name
Test status
Simulation time 1692995376 ps
CPU time 5.86 seconds
Started Jun 24 05:35:37 PM PDT 24
Finished Jun 24 05:35:44 PM PDT 24
Peak memory 200888 kb
Host smart-e5153cde-a1cc-49a4-bdeb-572e2e7c013d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884643137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.884643137
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3627466704
Short name T497
Test name
Test status
Simulation time 147332995 ps
CPU time 1.14 seconds
Started Jun 24 05:35:30 PM PDT 24
Finished Jun 24 05:35:32 PM PDT 24
Peak memory 200680 kb
Host smart-25c25765-84fe-4407-b5ff-4d761638ec25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627466704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3627466704
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2108152722
Short name T257
Test name
Test status
Simulation time 119913930 ps
CPU time 1.24 seconds
Started Jun 24 05:35:40 PM PDT 24
Finished Jun 24 05:35:44 PM PDT 24
Peak memory 200896 kb
Host smart-478254ef-13c3-4f6b-ae95-f3052582079b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108152722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2108152722
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.352460067
Short name T458
Test name
Test status
Simulation time 11401173051 ps
CPU time 40.36 seconds
Started Jun 24 05:35:38 PM PDT 24
Finished Jun 24 05:36:20 PM PDT 24
Peak memory 200932 kb
Host smart-d617e0ec-f2a6-4fac-b4cb-44fe8cb0aa90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352460067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.352460067
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2140918303
Short name T433
Test name
Test status
Simulation time 346164026 ps
CPU time 2.31 seconds
Started Jun 24 05:35:34 PM PDT 24
Finished Jun 24 05:35:37 PM PDT 24
Peak memory 200728 kb
Host smart-41b4376a-0827-4aee-8775-562e5ce40c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140918303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2140918303
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1613298027
Short name T511
Test name
Test status
Simulation time 116496916 ps
CPU time 0.95 seconds
Started Jun 24 05:35:44 PM PDT 24
Finished Jun 24 05:35:49 PM PDT 24
Peak memory 200728 kb
Host smart-2b2529ab-b00e-47eb-a9e3-8451e0c7e290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613298027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1613298027
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3305240732
Short name T196
Test name
Test status
Simulation time 82699976 ps
CPU time 0.89 seconds
Started Jun 24 05:35:40 PM PDT 24
Finished Jun 24 05:35:43 PM PDT 24
Peak memory 200500 kb
Host smart-d77c3887-86c1-43e3-b7f1-a636eecde42a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305240732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3305240732
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.11524594
Short name T305
Test name
Test status
Simulation time 2349552031 ps
CPU time 8.78 seconds
Started Jun 24 05:35:46 PM PDT 24
Finished Jun 24 05:35:58 PM PDT 24
Peak memory 218500 kb
Host smart-e9b343d6-1a92-4fc7-b095-50f31a4dc947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11524594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.11524594
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1442295296
Short name T142
Test name
Test status
Simulation time 243665276 ps
CPU time 1.04 seconds
Started Jun 24 05:35:38 PM PDT 24
Finished Jun 24 05:35:40 PM PDT 24
Peak memory 218064 kb
Host smart-16383c77-332e-42fe-9ee6-5f51c2cfa1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442295296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1442295296
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3065396742
Short name T16
Test name
Test status
Simulation time 172500240 ps
CPU time 0.88 seconds
Started Jun 24 05:35:40 PM PDT 24
Finished Jun 24 05:35:42 PM PDT 24
Peak memory 200492 kb
Host smart-dcd368b8-ff9e-41cf-a339-07b527cf7eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065396742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3065396742
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.1414685348
Short name T245
Test name
Test status
Simulation time 1808257497 ps
CPU time 6.58 seconds
Started Jun 24 05:35:40 PM PDT 24
Finished Jun 24 05:35:49 PM PDT 24
Peak memory 200888 kb
Host smart-c4af9d69-a64b-4de6-9174-9b8cd5c19d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414685348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.1414685348
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2552898226
Short name T277
Test name
Test status
Simulation time 155409942 ps
CPU time 1.09 seconds
Started Jun 24 05:35:44 PM PDT 24
Finished Jun 24 05:35:48 PM PDT 24
Peak memory 200696 kb
Host smart-79515e88-41ea-4224-bf65-2406aaed0b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552898226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2552898226
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3115426509
Short name T87
Test name
Test status
Simulation time 226661217 ps
CPU time 1.49 seconds
Started Jun 24 05:35:40 PM PDT 24
Finished Jun 24 05:35:44 PM PDT 24
Peak memory 200888 kb
Host smart-b43eaefc-e21b-472b-a68d-83b45e4ee849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115426509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3115426509
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1456915488
Short name T316
Test name
Test status
Simulation time 10686154758 ps
CPU time 37.19 seconds
Started Jun 24 05:35:38 PM PDT 24
Finished Jun 24 05:36:17 PM PDT 24
Peak memory 210724 kb
Host smart-778b54f4-917b-4c88-8564-5ca3ee242bc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456915488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1456915488
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.4129466669
Short name T376
Test name
Test status
Simulation time 379750941 ps
CPU time 2.45 seconds
Started Jun 24 05:35:43 PM PDT 24
Finished Jun 24 05:35:48 PM PDT 24
Peak memory 200876 kb
Host smart-c62d54a2-4e35-4b08-8ca8-bd7d50440072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129466669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.4129466669
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3698617419
Short name T147
Test name
Test status
Simulation time 142355868 ps
CPU time 1.02 seconds
Started Jun 24 05:35:37 PM PDT 24
Finished Jun 24 05:35:39 PM PDT 24
Peak memory 200628 kb
Host smart-1abe0fac-45c3-4a2e-8767-cbb5b3f6f974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698617419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3698617419
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2078899662
Short name T217
Test name
Test status
Simulation time 62819291 ps
CPU time 0.73 seconds
Started Jun 24 05:35:39 PM PDT 24
Finished Jun 24 05:35:41 PM PDT 24
Peak memory 200428 kb
Host smart-3924e1ef-602c-476f-a2cd-bf93deeb1a31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078899662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2078899662
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2606584175
Short name T474
Test name
Test status
Simulation time 2357295537 ps
CPU time 7.9 seconds
Started Jun 24 05:35:42 PM PDT 24
Finished Jun 24 05:35:53 PM PDT 24
Peak memory 222464 kb
Host smart-406a878b-2160-4967-a71e-3b440be1c4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606584175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2606584175
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.4075243126
Short name T137
Test name
Test status
Simulation time 244950005 ps
CPU time 1.08 seconds
Started Jun 24 05:35:42 PM PDT 24
Finished Jun 24 05:35:46 PM PDT 24
Peak memory 218092 kb
Host smart-43ba3c7b-9e92-4fdf-9ff0-66f8abe2bb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075243126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.4075243126
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3830597224
Short name T439
Test name
Test status
Simulation time 159817838 ps
CPU time 0.87 seconds
Started Jun 24 05:35:35 PM PDT 24
Finished Jun 24 05:35:37 PM PDT 24
Peak memory 200488 kb
Host smart-5adcf8af-0db7-4d82-b18f-31d1b5c602f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830597224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3830597224
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3199762782
Short name T56
Test name
Test status
Simulation time 1885885589 ps
CPU time 7.32 seconds
Started Jun 24 05:35:32 PM PDT 24
Finished Jun 24 05:35:40 PM PDT 24
Peak memory 200836 kb
Host smart-56b9ec02-2273-47c4-b9e4-3333b34f7173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199762782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3199762782
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3624742597
Short name T273
Test name
Test status
Simulation time 151208060 ps
CPU time 1.45 seconds
Started Jun 24 05:35:43 PM PDT 24
Finished Jun 24 05:35:47 PM PDT 24
Peak memory 200696 kb
Host smart-37a11548-f040-42c6-beef-e5d5ea050708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624742597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3624742597
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.673202204
Short name T335
Test name
Test status
Simulation time 238991656 ps
CPU time 1.56 seconds
Started Jun 24 05:35:43 PM PDT 24
Finished Jun 24 05:35:48 PM PDT 24
Peak memory 201056 kb
Host smart-f025a8cf-060d-4544-88fc-ce91e74ca00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673202204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.673202204
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.3796359370
Short name T88
Test name
Test status
Simulation time 209745492 ps
CPU time 1.78 seconds
Started Jun 24 05:35:41 PM PDT 24
Finished Jun 24 05:35:45 PM PDT 24
Peak memory 200716 kb
Host smart-6a5dfd48-8671-41e1-9951-2823c5cc38a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796359370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3796359370
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2171282790
Short name T226
Test name
Test status
Simulation time 286696438 ps
CPU time 2.07 seconds
Started Jun 24 05:35:39 PM PDT 24
Finished Jun 24 05:35:44 PM PDT 24
Peak memory 200708 kb
Host smart-10e78455-3b57-43a6-b188-24474ac5c5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171282790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2171282790
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3938666931
Short name T241
Test name
Test status
Simulation time 237537751 ps
CPU time 1.36 seconds
Started Jun 24 05:35:48 PM PDT 24
Finished Jun 24 05:35:52 PM PDT 24
Peak memory 200720 kb
Host smart-6b093013-927f-4401-9865-b7ed6b13d082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938666931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3938666931
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1920458849
Short name T306
Test name
Test status
Simulation time 71358410 ps
CPU time 0.8 seconds
Started Jun 24 05:35:34 PM PDT 24
Finished Jun 24 05:35:35 PM PDT 24
Peak memory 200448 kb
Host smart-3aae8929-7a3e-454f-a972-07aa26c4a669
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920458849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1920458849
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.550352330
Short name T353
Test name
Test status
Simulation time 2347629692 ps
CPU time 8.03 seconds
Started Jun 24 05:35:43 PM PDT 24
Finished Jun 24 05:35:55 PM PDT 24
Peak memory 218540 kb
Host smart-676c5159-bf23-478d-8b83-4c3d94cc8e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550352330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.550352330
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.966011037
Short name T330
Test name
Test status
Simulation time 244579319 ps
CPU time 1.05 seconds
Started Jun 24 05:35:33 PM PDT 24
Finished Jun 24 05:35:34 PM PDT 24
Peak memory 218148 kb
Host smart-79b5835b-a777-4b34-990d-fe537f959a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966011037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.966011037
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2344429440
Short name T219
Test name
Test status
Simulation time 134607309 ps
CPU time 0.82 seconds
Started Jun 24 05:35:44 PM PDT 24
Finished Jun 24 05:35:49 PM PDT 24
Peak memory 200672 kb
Host smart-922f3cde-6589-4918-84e1-361ad667066b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344429440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2344429440
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1293385052
Short name T370
Test name
Test status
Simulation time 2041628181 ps
CPU time 7.45 seconds
Started Jun 24 05:35:37 PM PDT 24
Finished Jun 24 05:35:45 PM PDT 24
Peak memory 200888 kb
Host smart-2934052e-cc7c-451a-83ef-32e56f659118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293385052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1293385052
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3635230014
Short name T525
Test name
Test status
Simulation time 169200068 ps
CPU time 1.19 seconds
Started Jun 24 05:35:37 PM PDT 24
Finished Jun 24 05:35:39 PM PDT 24
Peak memory 200696 kb
Host smart-1ad87901-51ca-474b-9ef1-dcae54688327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635230014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3635230014
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.3049764484
Short name T283
Test name
Test status
Simulation time 120992326 ps
CPU time 1.21 seconds
Started Jun 24 05:35:37 PM PDT 24
Finished Jun 24 05:35:39 PM PDT 24
Peak memory 201152 kb
Host smart-826263d4-8895-464f-bdf8-62f7825e7227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049764484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3049764484
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3336338702
Short name T111
Test name
Test status
Simulation time 2679228453 ps
CPU time 10.64 seconds
Started Jun 24 05:35:40 PM PDT 24
Finished Jun 24 05:35:52 PM PDT 24
Peak memory 200936 kb
Host smart-765248a8-a188-483a-9ddb-e2ca7ebfb25c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336338702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3336338702
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3939194218
Short name T404
Test name
Test status
Simulation time 79360407 ps
CPU time 0.88 seconds
Started Jun 24 05:35:44 PM PDT 24
Finished Jun 24 05:35:48 PM PDT 24
Peak memory 200696 kb
Host smart-3323e2c5-1687-4457-b2a2-31849d848bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939194218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3939194218
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3460651037
Short name T464
Test name
Test status
Simulation time 62397305 ps
CPU time 0.78 seconds
Started Jun 24 05:35:40 PM PDT 24
Finished Jun 24 05:35:43 PM PDT 24
Peak memory 200504 kb
Host smart-0cb90f3a-4124-472a-9ed4-530f36401425
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460651037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3460651037
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3386774966
Short name T275
Test name
Test status
Simulation time 1231922982 ps
CPU time 5.41 seconds
Started Jun 24 05:35:34 PM PDT 24
Finished Jun 24 05:35:40 PM PDT 24
Peak memory 222012 kb
Host smart-2cf57cff-a54c-4d95-979f-ed706aa04490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386774966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3386774966
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3361221606
Short name T194
Test name
Test status
Simulation time 245532753 ps
CPU time 1.11 seconds
Started Jun 24 05:35:40 PM PDT 24
Finished Jun 24 05:35:43 PM PDT 24
Peak memory 218072 kb
Host smart-f28c75c8-3b5b-4d5f-a897-a04cbb3ac649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361221606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3361221606
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3406596425
Short name T375
Test name
Test status
Simulation time 133945115 ps
CPU time 0.79 seconds
Started Jun 24 05:35:31 PM PDT 24
Finished Jun 24 05:35:33 PM PDT 24
Peak memory 200512 kb
Host smart-afd64d54-79e2-4085-93ef-dccb8972eb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406596425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3406596425
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.1470595931
Short name T99
Test name
Test status
Simulation time 995363680 ps
CPU time 4.79 seconds
Started Jun 24 05:35:41 PM PDT 24
Finished Jun 24 05:35:48 PM PDT 24
Peak memory 200896 kb
Host smart-f44efc9d-4279-4528-93c6-72afb8529569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470595931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1470595931
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.559716823
Short name T485
Test name
Test status
Simulation time 112204615 ps
CPU time 1.08 seconds
Started Jun 24 05:35:39 PM PDT 24
Finished Jun 24 05:35:42 PM PDT 24
Peak memory 200700 kb
Host smart-1105e5ff-8d9d-48f5-9572-356131301cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559716823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.559716823
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.982231665
Short name T13
Test name
Test status
Simulation time 208996373 ps
CPU time 1.37 seconds
Started Jun 24 05:35:39 PM PDT 24
Finished Jun 24 05:35:43 PM PDT 24
Peak memory 200920 kb
Host smart-1e428613-8da1-4b9c-9bfd-384f1db2e2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982231665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.982231665
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.1835823448
Short name T322
Test name
Test status
Simulation time 1760842658 ps
CPU time 6.69 seconds
Started Jun 24 05:35:39 PM PDT 24
Finished Jun 24 05:35:48 PM PDT 24
Peak memory 200876 kb
Host smart-c602dd03-193c-4d08-b3de-7922cc151664
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835823448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1835823448
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.3266542740
Short name T499
Test name
Test status
Simulation time 351608485 ps
CPU time 2.45 seconds
Started Jun 24 05:35:44 PM PDT 24
Finished Jun 24 05:35:50 PM PDT 24
Peak memory 200724 kb
Host smart-31bf185f-3830-4dfa-8ff3-3a6fcebfe9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266542740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.3266542740
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3011698794
Short name T271
Test name
Test status
Simulation time 174956162 ps
CPU time 1.31 seconds
Started Jun 24 05:35:37 PM PDT 24
Finished Jun 24 05:35:40 PM PDT 24
Peak memory 200860 kb
Host smart-ce5a9f41-41fd-4f5e-971e-b0780c8678e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011698794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3011698794
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3663611189
Short name T148
Test name
Test status
Simulation time 67863151 ps
CPU time 0.74 seconds
Started Jun 24 05:35:40 PM PDT 24
Finished Jun 24 05:35:43 PM PDT 24
Peak memory 200536 kb
Host smart-0be6ef90-e95d-4164-995d-0dbfa13b808c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663611189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3663611189
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1666266044
Short name T46
Test name
Test status
Simulation time 1232576148 ps
CPU time 5.8 seconds
Started Jun 24 05:35:37 PM PDT 24
Finished Jun 24 05:35:44 PM PDT 24
Peak memory 222440 kb
Host smart-09f4306b-4c03-4924-829f-d6d76f0fcccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666266044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1666266044
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2023106136
Short name T321
Test name
Test status
Simulation time 244449483 ps
CPU time 1.09 seconds
Started Jun 24 05:35:40 PM PDT 24
Finished Jun 24 05:35:43 PM PDT 24
Peak memory 218080 kb
Host smart-f41bf2d0-93ce-4db6-9d85-da950e958d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023106136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2023106136
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.2484127547
Short name T293
Test name
Test status
Simulation time 123898196 ps
CPU time 0.87 seconds
Started Jun 24 05:35:39 PM PDT 24
Finished Jun 24 05:35:42 PM PDT 24
Peak memory 200488 kb
Host smart-e22573d4-ac69-4143-bea0-3b8b73dd59e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484127547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2484127547
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1674341783
Short name T406
Test name
Test status
Simulation time 743201719 ps
CPU time 3.79 seconds
Started Jun 24 05:35:44 PM PDT 24
Finished Jun 24 05:35:51 PM PDT 24
Peak memory 200936 kb
Host smart-454357b6-f420-4e36-9366-33084773b3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674341783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1674341783
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1280299190
Short name T165
Test name
Test status
Simulation time 152063853 ps
CPU time 1.19 seconds
Started Jun 24 05:35:29 PM PDT 24
Finished Jun 24 05:35:31 PM PDT 24
Peak memory 200696 kb
Host smart-f0b5e2ab-54ef-47c0-868e-ab0bc89948eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280299190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1280299190
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2685242940
Short name T402
Test name
Test status
Simulation time 189779070 ps
CPU time 1.42 seconds
Started Jun 24 05:35:38 PM PDT 24
Finished Jun 24 05:35:40 PM PDT 24
Peak memory 200884 kb
Host smart-4749b4a5-1b69-4271-9105-6cbef94bb010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685242940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2685242940
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.347136136
Short name T270
Test name
Test status
Simulation time 3872974621 ps
CPU time 17.52 seconds
Started Jun 24 05:35:37 PM PDT 24
Finished Jun 24 05:35:55 PM PDT 24
Peak memory 200960 kb
Host smart-dde7c04a-d73c-412a-9476-70030135734b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347136136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.347136136
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.2044449721
Short name T53
Test name
Test status
Simulation time 435830055 ps
CPU time 2.26 seconds
Started Jun 24 05:35:31 PM PDT 24
Finished Jun 24 05:35:34 PM PDT 24
Peak memory 200616 kb
Host smart-232f4d0a-6530-40b9-99cf-eebddfb3141f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044449721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.2044449721
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.385087614
Short name T7
Test name
Test status
Simulation time 77159326 ps
CPU time 0.81 seconds
Started Jun 24 05:35:42 PM PDT 24
Finished Jun 24 05:35:45 PM PDT 24
Peak memory 200740 kb
Host smart-5f90d9c0-7e03-4756-a72d-ca17dc68cc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385087614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.385087614
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.974775834
Short name T27
Test name
Test status
Simulation time 60745735 ps
CPU time 0.75 seconds
Started Jun 24 05:35:45 PM PDT 24
Finished Jun 24 05:35:49 PM PDT 24
Peak memory 200496 kb
Host smart-38317d91-ff0a-4713-831a-906cce00a135
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974775834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.974775834
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.3597711186
Short name T61
Test name
Test status
Simulation time 1232995553 ps
CPU time 5.79 seconds
Started Jun 24 05:35:42 PM PDT 24
Finished Jun 24 05:35:51 PM PDT 24
Peak memory 222428 kb
Host smart-e49b7806-b79a-454b-bdb4-ac8d864c3d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597711186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3597711186
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2490372807
Short name T202
Test name
Test status
Simulation time 243702803 ps
CPU time 1.08 seconds
Started Jun 24 05:35:40 PM PDT 24
Finished Jun 24 05:35:43 PM PDT 24
Peak memory 218056 kb
Host smart-2df29533-8cca-4d01-a1ac-f49f8f5ca221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490372807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2490372807
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2384527643
Short name T475
Test name
Test status
Simulation time 237900688 ps
CPU time 0.89 seconds
Started Jun 24 05:35:37 PM PDT 24
Finished Jun 24 05:35:39 PM PDT 24
Peak memory 200512 kb
Host smart-5b5099c2-087b-494b-9e4b-b83cab7d2bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384527643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2384527643
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3980390058
Short name T98
Test name
Test status
Simulation time 770750481 ps
CPU time 4.26 seconds
Started Jun 24 05:35:39 PM PDT 24
Finished Jun 24 05:35:45 PM PDT 24
Peak memory 200924 kb
Host smart-76bde715-d5f7-4e89-9a76-fcfd118aa470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980390058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3980390058
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2614938552
Short name T126
Test name
Test status
Simulation time 184316666 ps
CPU time 1.24 seconds
Started Jun 24 05:35:45 PM PDT 24
Finished Jun 24 05:35:50 PM PDT 24
Peak memory 200692 kb
Host smart-2e3a4a6f-cba7-4469-820a-ad6275d60a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614938552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2614938552
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1652542713
Short name T208
Test name
Test status
Simulation time 189649855 ps
CPU time 1.38 seconds
Started Jun 24 05:35:43 PM PDT 24
Finished Jun 24 05:35:48 PM PDT 24
Peak memory 200856 kb
Host smart-e1288bb2-ceac-4521-a59d-e07ab78ddc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652542713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1652542713
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.1042875623
Short name T151
Test name
Test status
Simulation time 1902917359 ps
CPU time 7.16 seconds
Started Jun 24 05:35:44 PM PDT 24
Finished Jun 24 05:35:55 PM PDT 24
Peak memory 200780 kb
Host smart-e168c16c-eaf9-43e8-9041-0f387c39dfb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042875623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1042875623
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.573603594
Short name T379
Test name
Test status
Simulation time 129036168 ps
CPU time 1.68 seconds
Started Jun 24 05:36:04 PM PDT 24
Finished Jun 24 05:36:07 PM PDT 24
Peak memory 208892 kb
Host smart-2aee5d15-5d5e-426d-82ae-52459994255c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573603594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.573603594
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.1011334162
Short name T237
Test name
Test status
Simulation time 170236157 ps
CPU time 1.26 seconds
Started Jun 24 05:35:44 PM PDT 24
Finished Jun 24 05:35:48 PM PDT 24
Peak memory 200840 kb
Host smart-fea01fb4-ab7a-4e84-82b2-fd71e8659ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011334162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1011334162
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.656597932
Short name T138
Test name
Test status
Simulation time 72155824 ps
CPU time 0.88 seconds
Started Jun 24 05:35:47 PM PDT 24
Finished Jun 24 05:35:51 PM PDT 24
Peak memory 200496 kb
Host smart-40d12c9b-0069-4c39-945e-8a92f71fd6b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656597932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.656597932
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2609834374
Short name T62
Test name
Test status
Simulation time 1237507940 ps
CPU time 5.42 seconds
Started Jun 24 05:35:43 PM PDT 24
Finished Jun 24 05:35:52 PM PDT 24
Peak memory 218480 kb
Host smart-108bfa54-d13f-4c44-9d6a-5c580ad35cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609834374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2609834374
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.86462801
Short name T460
Test name
Test status
Simulation time 244026424 ps
CPU time 1.09 seconds
Started Jun 24 05:35:51 PM PDT 24
Finished Jun 24 05:35:53 PM PDT 24
Peak memory 218060 kb
Host smart-ded4100c-4a17-4d18-852d-046e2ceed7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86462801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.86462801
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2748198039
Short name T162
Test name
Test status
Simulation time 96039151 ps
CPU time 0.77 seconds
Started Jun 24 05:35:49 PM PDT 24
Finished Jun 24 05:35:51 PM PDT 24
Peak memory 200536 kb
Host smart-9907c402-6269-432a-919e-a4d03dd7c785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748198039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2748198039
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1087692560
Short name T134
Test name
Test status
Simulation time 1356584002 ps
CPU time 5.9 seconds
Started Jun 24 05:35:41 PM PDT 24
Finished Jun 24 05:35:50 PM PDT 24
Peak memory 200792 kb
Host smart-59ebe674-b09e-4044-9112-4fc784bd02dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087692560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1087692560
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1155999247
Short name T191
Test name
Test status
Simulation time 104574446 ps
CPU time 1.07 seconds
Started Jun 24 05:35:45 PM PDT 24
Finished Jun 24 05:35:49 PM PDT 24
Peak memory 200696 kb
Host smart-48e76cfd-dcf3-4db2-aaa3-b65e5970fb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155999247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1155999247
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2563611928
Short name T338
Test name
Test status
Simulation time 200911385 ps
CPU time 1.37 seconds
Started Jun 24 05:35:44 PM PDT 24
Finished Jun 24 05:35:49 PM PDT 24
Peak memory 201116 kb
Host smart-662271b4-7fb6-4d94-9e0f-4308aa2ef845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563611928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2563611928
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1289712102
Short name T96
Test name
Test status
Simulation time 4098603500 ps
CPU time 18.62 seconds
Started Jun 24 05:35:48 PM PDT 24
Finished Jun 24 05:36:09 PM PDT 24
Peak memory 217244 kb
Host smart-7609f72b-6151-4b1c-aba5-815877dfa4de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289712102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1289712102
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1925830537
Short name T258
Test name
Test status
Simulation time 134949036 ps
CPU time 1.76 seconds
Started Jun 24 05:35:40 PM PDT 24
Finished Jun 24 05:35:44 PM PDT 24
Peak memory 200672 kb
Host smart-41ea4533-2f66-4136-bfa9-7489449a3010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925830537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1925830537
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1834725246
Short name T468
Test name
Test status
Simulation time 232737414 ps
CPU time 1.39 seconds
Started Jun 24 05:35:52 PM PDT 24
Finished Jun 24 05:35:54 PM PDT 24
Peak memory 200628 kb
Host smart-9f3177bf-8f5d-43b6-8aa8-9fec042bfef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834725246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1834725246
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.659490964
Short name T388
Test name
Test status
Simulation time 77319773 ps
CPU time 0.82 seconds
Started Jun 24 05:35:41 PM PDT 24
Finished Jun 24 05:35:44 PM PDT 24
Peak memory 200496 kb
Host smart-eb1b96fe-2b16-4e3e-8f58-e92cc3e5112b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659490964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.659490964
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3635631369
Short name T47
Test name
Test status
Simulation time 2152211565 ps
CPU time 8.53 seconds
Started Jun 24 05:35:42 PM PDT 24
Finished Jun 24 05:35:53 PM PDT 24
Peak memory 218076 kb
Host smart-e4e8ddf5-6869-486b-9e24-e961f16410d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635631369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3635631369
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2495677424
Short name T274
Test name
Test status
Simulation time 243902340 ps
CPU time 1.1 seconds
Started Jun 24 05:35:42 PM PDT 24
Finished Jun 24 05:35:46 PM PDT 24
Peak memory 218084 kb
Host smart-204e4828-691f-415e-b22a-c565c98e807f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495677424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2495677424
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.737044279
Short name T401
Test name
Test status
Simulation time 111160494 ps
CPU time 0.8 seconds
Started Jun 24 05:35:43 PM PDT 24
Finished Jun 24 05:35:47 PM PDT 24
Peak memory 200420 kb
Host smart-1c0efd85-5795-4df2-9936-ccb93f9d6a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737044279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.737044279
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.2980795571
Short name T57
Test name
Test status
Simulation time 1634924851 ps
CPU time 6.55 seconds
Started Jun 24 05:35:41 PM PDT 24
Finished Jun 24 05:35:50 PM PDT 24
Peak memory 200888 kb
Host smart-dc74be09-be56-4cf8-bda4-be7e72a29449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980795571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.2980795571
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3410565858
Short name T304
Test name
Test status
Simulation time 100915602 ps
CPU time 1.09 seconds
Started Jun 24 05:35:42 PM PDT 24
Finished Jun 24 05:35:47 PM PDT 24
Peak memory 200680 kb
Host smart-3eefd3c1-9eec-4991-8dab-4fdb36a9d57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410565858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3410565858
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1284914117
Short name T426
Test name
Test status
Simulation time 115490366 ps
CPU time 1.2 seconds
Started Jun 24 05:35:39 PM PDT 24
Finished Jun 24 05:35:41 PM PDT 24
Peak memory 200940 kb
Host smart-6bf1961c-478d-458a-82ad-6516b313f5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284914117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1284914117
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.309697255
Short name T471
Test name
Test status
Simulation time 3803686467 ps
CPU time 13.86 seconds
Started Jun 24 05:35:44 PM PDT 24
Finished Jun 24 05:36:01 PM PDT 24
Peak memory 201156 kb
Host smart-38f9c3d1-913a-488e-bcfd-a55cc1fa44f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309697255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.309697255
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.305375140
Short name T454
Test name
Test status
Simulation time 120111072 ps
CPU time 1.66 seconds
Started Jun 24 05:35:48 PM PDT 24
Finished Jun 24 05:35:52 PM PDT 24
Peak memory 208924 kb
Host smart-d10dcaef-f6a0-47df-b864-957393c88ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305375140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.305375140
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.744895435
Short name T12
Test name
Test status
Simulation time 123286286 ps
CPU time 0.96 seconds
Started Jun 24 05:35:41 PM PDT 24
Finished Jun 24 05:35:45 PM PDT 24
Peak memory 200692 kb
Host smart-0ce7130f-ea85-467c-b681-ba2fd17ffa3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744895435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.744895435
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.2723056751
Short name T213
Test name
Test status
Simulation time 60148525 ps
CPU time 0.74 seconds
Started Jun 24 05:35:54 PM PDT 24
Finished Jun 24 05:35:57 PM PDT 24
Peak memory 200444 kb
Host smart-a4d483ff-2c7a-4f4f-b75c-02aec9305479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723056751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2723056751
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2479093881
Short name T482
Test name
Test status
Simulation time 2359760497 ps
CPU time 9.18 seconds
Started Jun 24 05:35:43 PM PDT 24
Finished Jun 24 05:35:55 PM PDT 24
Peak memory 218512 kb
Host smart-cf260fb5-37ab-46ba-aecb-528c598c4d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479093881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2479093881
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.1974102949
Short name T233
Test name
Test status
Simulation time 244577852 ps
CPU time 1.06 seconds
Started Jun 24 05:35:42 PM PDT 24
Finished Jun 24 05:35:47 PM PDT 24
Peak memory 218072 kb
Host smart-7e66a084-058c-4fcd-b897-bbd79a14b67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974102949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.1974102949
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2422253079
Short name T411
Test name
Test status
Simulation time 234953018 ps
CPU time 0.9 seconds
Started Jun 24 05:35:45 PM PDT 24
Finished Jun 24 05:35:49 PM PDT 24
Peak memory 200432 kb
Host smart-bacfe54b-43de-42e9-88ed-8f6f48bfba58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422253079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2422253079
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3866442847
Short name T383
Test name
Test status
Simulation time 1753329670 ps
CPU time 6.86 seconds
Started Jun 24 05:35:44 PM PDT 24
Finished Jun 24 05:35:54 PM PDT 24
Peak memory 200920 kb
Host smart-bcafbfdf-df58-45ea-a5fb-fd7a5b2bb8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866442847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3866442847
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.4214077749
Short name T535
Test name
Test status
Simulation time 99451950 ps
CPU time 0.96 seconds
Started Jun 24 05:35:48 PM PDT 24
Finished Jun 24 05:35:51 PM PDT 24
Peak memory 200608 kb
Host smart-679c578b-5fdd-48c8-b8b7-233b6397c725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214077749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.4214077749
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2558406055
Short name T442
Test name
Test status
Simulation time 253823190 ps
CPU time 1.48 seconds
Started Jun 24 05:35:48 PM PDT 24
Finished Jun 24 05:35:52 PM PDT 24
Peak memory 200888 kb
Host smart-c9dcbf15-dc53-4de2-9359-be4af7121cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558406055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2558406055
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3405121105
Short name T456
Test name
Test status
Simulation time 4296599025 ps
CPU time 20.2 seconds
Started Jun 24 05:35:39 PM PDT 24
Finished Jun 24 05:36:00 PM PDT 24
Peak memory 209164 kb
Host smart-a36431b8-5e68-4db0-9f3c-a25686ead2aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405121105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3405121105
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3949171864
Short name T33
Test name
Test status
Simulation time 461334985 ps
CPU time 2.58 seconds
Started Jun 24 05:35:42 PM PDT 24
Finished Jun 24 05:35:47 PM PDT 24
Peak memory 200688 kb
Host smart-7757d109-42f1-4c0c-8117-4cbf12eba4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949171864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3949171864
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1438296728
Short name T223
Test name
Test status
Simulation time 200485288 ps
CPU time 1.22 seconds
Started Jun 24 05:35:48 PM PDT 24
Finished Jun 24 05:35:52 PM PDT 24
Peak memory 200628 kb
Host smart-2b0ab47a-6651-42ef-99b6-0f60d8aa1066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438296728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1438296728
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.4104683575
Short name T5
Test name
Test status
Simulation time 63608918 ps
CPU time 0.75 seconds
Started Jun 24 05:35:02 PM PDT 24
Finished Jun 24 05:35:04 PM PDT 24
Peak memory 200512 kb
Host smart-96af80d5-a868-40af-8b59-813c94fe1278
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104683575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.4104683575
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1913733958
Short name T203
Test name
Test status
Simulation time 1231489440 ps
CPU time 5.5 seconds
Started Jun 24 05:35:12 PM PDT 24
Finished Jun 24 05:35:19 PM PDT 24
Peak memory 222484 kb
Host smart-0dc32d4a-8bdc-4066-8cb2-45c2f18a9abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913733958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1913733958
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.663899914
Short name T382
Test name
Test status
Simulation time 244120952 ps
CPU time 1.09 seconds
Started Jun 24 05:35:04 PM PDT 24
Finished Jun 24 05:35:08 PM PDT 24
Peak memory 218056 kb
Host smart-c29adf8c-5f80-41a0-941a-48faea0cffe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663899914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.663899914
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.694406939
Short name T19
Test name
Test status
Simulation time 155689481 ps
CPU time 0.8 seconds
Started Jun 24 05:35:19 PM PDT 24
Finished Jun 24 05:35:21 PM PDT 24
Peak memory 200488 kb
Host smart-6d0e8c48-f1f3-4385-a9aa-ed417319f323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694406939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.694406939
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2854195860
Short name T435
Test name
Test status
Simulation time 721994753 ps
CPU time 3.66 seconds
Started Jun 24 05:35:08 PM PDT 24
Finished Jun 24 05:35:13 PM PDT 24
Peak memory 200900 kb
Host smart-9697c2e9-6590-4bf6-8be2-7fb629f69f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854195860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2854195860
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1277408743
Short name T73
Test name
Test status
Simulation time 8432684196 ps
CPU time 12.58 seconds
Started Jun 24 05:35:04 PM PDT 24
Finished Jun 24 05:35:19 PM PDT 24
Peak memory 217556 kb
Host smart-08a95769-0641-4557-8e96-8d036232bae5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277408743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1277408743
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.416100489
Short name T294
Test name
Test status
Simulation time 153815906 ps
CPU time 1.13 seconds
Started Jun 24 05:35:01 PM PDT 24
Finished Jun 24 05:35:03 PM PDT 24
Peak memory 200724 kb
Host smart-f39dae8e-161a-4bb1-8a7e-5c26f770e890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416100489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.416100489
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.3788260153
Short name T227
Test name
Test status
Simulation time 199456647 ps
CPU time 1.47 seconds
Started Jun 24 05:35:02 PM PDT 24
Finished Jun 24 05:35:05 PM PDT 24
Peak memory 201052 kb
Host smart-f95ccf8a-ba7c-433c-8237-a3523090b752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788260153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3788260153
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1915770063
Short name T256
Test name
Test status
Simulation time 3792730293 ps
CPU time 14.74 seconds
Started Jun 24 05:35:02 PM PDT 24
Finished Jun 24 05:35:19 PM PDT 24
Peak memory 200968 kb
Host smart-d3f0b7f5-84ad-4273-b6cd-ce70e4eb1cab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915770063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1915770063
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2019655823
Short name T391
Test name
Test status
Simulation time 124825853 ps
CPU time 1.66 seconds
Started Jun 24 05:35:05 PM PDT 24
Finished Jun 24 05:35:10 PM PDT 24
Peak memory 200624 kb
Host smart-7d8a7e5d-03bb-4485-a9e1-a9501a56230a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019655823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2019655823
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2336405720
Short name T534
Test name
Test status
Simulation time 148163747 ps
CPU time 1.04 seconds
Started Jun 24 05:35:02 PM PDT 24
Finished Jun 24 05:35:06 PM PDT 24
Peak memory 200728 kb
Host smart-a89ae3c6-9290-4780-af0e-5fdaddd5fb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336405720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2336405720
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.728685655
Short name T225
Test name
Test status
Simulation time 65619588 ps
CPU time 0.79 seconds
Started Jun 24 05:35:45 PM PDT 24
Finished Jun 24 05:35:49 PM PDT 24
Peak memory 200496 kb
Host smart-e05e3a7f-5a80-4e0f-9f88-491df864ab72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728685655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.728685655
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3412924664
Short name T325
Test name
Test status
Simulation time 1223992320 ps
CPU time 5.1 seconds
Started Jun 24 05:35:45 PM PDT 24
Finished Jun 24 05:35:57 PM PDT 24
Peak memory 217596 kb
Host smart-dc084043-ed07-4de9-8749-90c1adf01731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412924664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3412924664
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2952653560
Short name T206
Test name
Test status
Simulation time 245038249 ps
CPU time 1.04 seconds
Started Jun 24 05:35:51 PM PDT 24
Finished Jun 24 05:35:53 PM PDT 24
Peak memory 218076 kb
Host smart-9eb1c1a5-a701-41b7-9f74-eb1827d66190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952653560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2952653560
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.517674395
Short name T374
Test name
Test status
Simulation time 255982026 ps
CPU time 0.95 seconds
Started Jun 24 05:35:44 PM PDT 24
Finished Jun 24 05:35:48 PM PDT 24
Peak memory 200424 kb
Host smart-f7a7f3b1-6119-414d-b3d8-4ef69977543b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517674395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.517674395
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.4007372200
Short name T414
Test name
Test status
Simulation time 1613551612 ps
CPU time 6.44 seconds
Started Jun 24 05:35:39 PM PDT 24
Finished Jun 24 05:35:47 PM PDT 24
Peak memory 200928 kb
Host smart-8667da68-c083-4e00-8d92-7b8c4fa39967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007372200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.4007372200
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1589534727
Short name T309
Test name
Test status
Simulation time 174563950 ps
CPU time 1.17 seconds
Started Jun 24 05:35:44 PM PDT 24
Finished Jun 24 05:35:48 PM PDT 24
Peak memory 200696 kb
Host smart-91e567b8-d596-4d4c-94a5-116b2a573f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589534727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1589534727
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2594221350
Short name T267
Test name
Test status
Simulation time 121955033 ps
CPU time 1.14 seconds
Started Jun 24 05:35:50 PM PDT 24
Finished Jun 24 05:35:52 PM PDT 24
Peak memory 200860 kb
Host smart-1c8e08f9-a69e-4adc-99f9-e05587e766fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594221350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2594221350
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.4160920997
Short name T493
Test name
Test status
Simulation time 3294646165 ps
CPU time 12.2 seconds
Started Jun 24 05:35:53 PM PDT 24
Finished Jun 24 05:36:06 PM PDT 24
Peak memory 200940 kb
Host smart-75de5de5-5cf9-49f9-93e9-084e9b907a8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160920997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.4160920997
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.90491886
Short name T91
Test name
Test status
Simulation time 115495466 ps
CPU time 1.49 seconds
Started Jun 24 05:35:40 PM PDT 24
Finished Jun 24 05:35:43 PM PDT 24
Peak memory 200708 kb
Host smart-058f7bb6-bd55-40fa-a602-ec2958b13974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90491886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.90491886
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3148923974
Short name T522
Test name
Test status
Simulation time 90940259 ps
CPU time 0.83 seconds
Started Jun 24 05:35:52 PM PDT 24
Finished Jun 24 05:35:54 PM PDT 24
Peak memory 200636 kb
Host smart-8c1c9844-5b52-4a7d-a366-172604f44821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148923974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3148923974
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.732752108
Short name T513
Test name
Test status
Simulation time 77362844 ps
CPU time 0.77 seconds
Started Jun 24 05:35:42 PM PDT 24
Finished Jun 24 05:35:47 PM PDT 24
Peak memory 200496 kb
Host smart-e5a18db0-c781-4f5e-9142-f10fe15102d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732752108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.732752108
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2844219371
Short name T37
Test name
Test status
Simulation time 1887833926 ps
CPU time 7.37 seconds
Started Jun 24 05:35:43 PM PDT 24
Finished Jun 24 05:35:54 PM PDT 24
Peak memory 222372 kb
Host smart-41af4a03-6038-4af7-b59f-4e5406060893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844219371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2844219371
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.502228874
Short name T292
Test name
Test status
Simulation time 244022888 ps
CPU time 1.1 seconds
Started Jun 24 05:35:49 PM PDT 24
Finished Jun 24 05:35:53 PM PDT 24
Peak memory 218276 kb
Host smart-de21cfaa-e5c6-4b08-a741-2da34d4d7a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502228874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.502228874
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.3835338398
Short name T403
Test name
Test status
Simulation time 139234263 ps
CPU time 0.89 seconds
Started Jun 24 05:35:44 PM PDT 24
Finished Jun 24 05:35:49 PM PDT 24
Peak memory 200524 kb
Host smart-163dc0a0-5ad7-448a-ab8d-dc8963444c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835338398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3835338398
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2037378770
Short name T209
Test name
Test status
Simulation time 961788196 ps
CPU time 4.83 seconds
Started Jun 24 05:35:43 PM PDT 24
Finished Jun 24 05:35:51 PM PDT 24
Peak memory 200884 kb
Host smart-21bdf160-d793-44d4-a51c-a87f514648a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037378770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2037378770
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3250537014
Short name T268
Test name
Test status
Simulation time 149166406 ps
CPU time 1.14 seconds
Started Jun 24 05:35:51 PM PDT 24
Finished Jun 24 05:35:53 PM PDT 24
Peak memory 200636 kb
Host smart-45f15e54-b993-4387-b510-6b3d227e4ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250537014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3250537014
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3500822424
Short name T355
Test name
Test status
Simulation time 112448788 ps
CPU time 1.16 seconds
Started Jun 24 05:35:42 PM PDT 24
Finished Jun 24 05:35:46 PM PDT 24
Peak memory 200920 kb
Host smart-f04fab3a-db6d-407f-aa01-ebe5215aab7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500822424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3500822424
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.1135740285
Short name T357
Test name
Test status
Simulation time 2494256009 ps
CPU time 11.39 seconds
Started Jun 24 05:35:43 PM PDT 24
Finished Jun 24 05:35:58 PM PDT 24
Peak memory 209156 kb
Host smart-6cb87804-4034-4beb-852c-10564fc8742c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135740285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.1135740285
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2641611488
Short name T130
Test name
Test status
Simulation time 379289357 ps
CPU time 2.63 seconds
Started Jun 24 05:35:41 PM PDT 24
Finished Jun 24 05:35:47 PM PDT 24
Peak memory 200632 kb
Host smart-703c0282-7347-41cd-9a2b-af75d1365618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641611488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2641611488
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1231481198
Short name T512
Test name
Test status
Simulation time 102028116 ps
CPU time 0.9 seconds
Started Jun 24 05:35:49 PM PDT 24
Finished Jun 24 05:35:52 PM PDT 24
Peak memory 200716 kb
Host smart-b6773ed6-7be0-4e0e-9d29-44111ba6d0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231481198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1231481198
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.734321899
Short name T133
Test name
Test status
Simulation time 73529393 ps
CPU time 0.79 seconds
Started Jun 24 05:35:51 PM PDT 24
Finished Jun 24 05:35:53 PM PDT 24
Peak memory 200444 kb
Host smart-c998d108-11be-4df2-b98c-099c60a4ba43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734321899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.734321899
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2036205000
Short name T39
Test name
Test status
Simulation time 1894672670 ps
CPU time 7.93 seconds
Started Jun 24 05:35:42 PM PDT 24
Finished Jun 24 05:35:53 PM PDT 24
Peak memory 222380 kb
Host smart-8b21a9db-7ec7-4842-ac55-3e3dc701ec64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036205000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2036205000
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.26840720
Short name T361
Test name
Test status
Simulation time 243994029 ps
CPU time 1.15 seconds
Started Jun 24 05:35:46 PM PDT 24
Finished Jun 24 05:35:50 PM PDT 24
Peak memory 218060 kb
Host smart-ca32b281-6454-4099-ba6a-f5f44f898687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26840720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.26840720
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.890760319
Short name T416
Test name
Test status
Simulation time 175411599 ps
CPU time 1.02 seconds
Started Jun 24 05:36:02 PM PDT 24
Finished Jun 24 05:36:04 PM PDT 24
Peak memory 200416 kb
Host smart-a3a26bef-3111-413a-84e3-d3e5a7314e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890760319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.890760319
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1387896567
Short name T115
Test name
Test status
Simulation time 1636134122 ps
CPU time 6.75 seconds
Started Jun 24 05:35:46 PM PDT 24
Finished Jun 24 05:35:56 PM PDT 24
Peak memory 200844 kb
Host smart-a2cc57e8-e5a6-4462-aa59-125bc8785293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387896567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1387896567
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2115053990
Short name T303
Test name
Test status
Simulation time 98856282 ps
CPU time 1 seconds
Started Jun 24 05:35:43 PM PDT 24
Finished Jun 24 05:35:47 PM PDT 24
Peak memory 200628 kb
Host smart-bc377f9b-fa45-4c75-9425-96ce76e416b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115053990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2115053990
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1359193613
Short name T369
Test name
Test status
Simulation time 247114665 ps
CPU time 1.44 seconds
Started Jun 24 05:35:46 PM PDT 24
Finished Jun 24 05:35:51 PM PDT 24
Peak memory 200892 kb
Host smart-2b2603c3-35a5-4dac-a409-ff4914c2e30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359193613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1359193613
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.195743083
Short name T272
Test name
Test status
Simulation time 5825544100 ps
CPU time 19.37 seconds
Started Jun 24 05:36:02 PM PDT 24
Finished Jun 24 05:36:22 PM PDT 24
Peak memory 200864 kb
Host smart-6916b13d-fe9f-44e9-84fa-0b6bc5c93f36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195743083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.195743083
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.1555849640
Short name T527
Test name
Test status
Simulation time 363485365 ps
CPU time 2.29 seconds
Started Jun 24 05:35:41 PM PDT 24
Finished Jun 24 05:35:47 PM PDT 24
Peak memory 208904 kb
Host smart-45e21251-d88e-4aa1-bf43-59822bec6a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555849640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1555849640
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2293204500
Short name T386
Test name
Test status
Simulation time 83480192 ps
CPU time 0.86 seconds
Started Jun 24 05:35:55 PM PDT 24
Finished Jun 24 05:35:57 PM PDT 24
Peak memory 200708 kb
Host smart-1f752a0e-2223-4f4c-8b3e-962346b0431e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293204500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2293204500
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.42306577
Short name T32
Test name
Test status
Simulation time 65533923 ps
CPU time 0.72 seconds
Started Jun 24 05:35:53 PM PDT 24
Finished Jun 24 05:35:54 PM PDT 24
Peak memory 200540 kb
Host smart-76745f76-4666-4861-ad55-be1b4cea9e27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42306577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.42306577
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3709210575
Short name T428
Test name
Test status
Simulation time 244567461 ps
CPU time 1.17 seconds
Started Jun 24 05:36:10 PM PDT 24
Finished Jun 24 05:36:12 PM PDT 24
Peak memory 218084 kb
Host smart-5b7cb2ff-2832-4370-a23f-44759e590176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709210575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3709210575
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2936781191
Short name T18
Test name
Test status
Simulation time 179576961 ps
CPU time 0.84 seconds
Started Jun 24 05:35:50 PM PDT 24
Finished Jun 24 05:35:52 PM PDT 24
Peak memory 200500 kb
Host smart-abf98283-1915-461c-b5de-bb22d010be22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936781191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2936781191
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.264451459
Short name T101
Test name
Test status
Simulation time 1137624380 ps
CPU time 5.37 seconds
Started Jun 24 05:35:47 PM PDT 24
Finished Jun 24 05:35:55 PM PDT 24
Peak memory 200864 kb
Host smart-0bb6b592-383a-4a57-b970-bcd81e711df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264451459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.264451459
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1815595260
Short name T183
Test name
Test status
Simulation time 146080141 ps
CPU time 1.12 seconds
Started Jun 24 05:35:44 PM PDT 24
Finished Jun 24 05:35:49 PM PDT 24
Peak memory 200620 kb
Host smart-61f055ef-ee42-4b86-a95b-336bc6259005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815595260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1815595260
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.1101561558
Short name T311
Test name
Test status
Simulation time 259530475 ps
CPU time 1.5 seconds
Started Jun 24 05:35:43 PM PDT 24
Finished Jun 24 05:35:48 PM PDT 24
Peak memory 200892 kb
Host smart-7a96625a-158d-4d86-820a-42410fc4f51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101561558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1101561558
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2888769876
Short name T407
Test name
Test status
Simulation time 5879123918 ps
CPU time 20.7 seconds
Started Jun 24 05:35:54 PM PDT 24
Finished Jun 24 05:36:16 PM PDT 24
Peak memory 210188 kb
Host smart-1c1d719b-859d-435b-b451-d12b517186c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888769876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2888769876
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2416670056
Short name T358
Test name
Test status
Simulation time 378277498 ps
CPU time 2.49 seconds
Started Jun 24 05:36:01 PM PDT 24
Finished Jun 24 05:36:04 PM PDT 24
Peak memory 208816 kb
Host smart-5009cfa9-50d6-4ef5-9e17-7f2d37bc14bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416670056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2416670056
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2171704902
Short name T387
Test name
Test status
Simulation time 109953806 ps
CPU time 1.02 seconds
Started Jun 24 05:35:46 PM PDT 24
Finished Jun 24 05:35:50 PM PDT 24
Peak memory 200716 kb
Host smart-573f6a63-fec6-4836-8319-724bf45c0795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171704902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2171704902
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.4225095332
Short name T417
Test name
Test status
Simulation time 69282035 ps
CPU time 0.77 seconds
Started Jun 24 05:36:01 PM PDT 24
Finished Jun 24 05:36:03 PM PDT 24
Peak memory 200500 kb
Host smart-8a038584-a521-4696-bf9b-f9cb7ab01d51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225095332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.4225095332
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.514263823
Short name T481
Test name
Test status
Simulation time 2348337022 ps
CPU time 9.74 seconds
Started Jun 24 05:35:57 PM PDT 24
Finished Jun 24 05:36:09 PM PDT 24
Peak memory 222492 kb
Host smart-35511cdb-200d-4a76-80bc-3c44aaf0c27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514263823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.514263823
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3038919786
Short name T248
Test name
Test status
Simulation time 245067190 ps
CPU time 1.06 seconds
Started Jun 24 05:35:57 PM PDT 24
Finished Jun 24 05:36:00 PM PDT 24
Peak memory 218124 kb
Host smart-2a37e7a0-3bc4-45e5-bce6-551631cab2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038919786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3038919786
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1561021770
Short name T249
Test name
Test status
Simulation time 218873592 ps
CPU time 0.93 seconds
Started Jun 24 05:35:56 PM PDT 24
Finished Jun 24 05:35:59 PM PDT 24
Peak memory 200444 kb
Host smart-15ed914a-08c4-4ab0-891d-416fbc8f96c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561021770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1561021770
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.644405325
Short name T157
Test name
Test status
Simulation time 841654202 ps
CPU time 4.02 seconds
Started Jun 24 05:35:56 PM PDT 24
Finished Jun 24 05:36:02 PM PDT 24
Peak memory 200892 kb
Host smart-ea9302aa-8f1f-4525-a8ad-de109f7ac80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644405325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.644405325
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3675814870
Short name T536
Test name
Test status
Simulation time 184243135 ps
CPU time 1.12 seconds
Started Jun 24 05:35:57 PM PDT 24
Finished Jun 24 05:36:00 PM PDT 24
Peak memory 200628 kb
Host smart-c1856c7e-4f5a-4422-998a-6f31572c0fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675814870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3675814870
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1197519001
Short name T331
Test name
Test status
Simulation time 4483067687 ps
CPU time 16.43 seconds
Started Jun 24 05:35:57 PM PDT 24
Finished Jun 24 05:36:15 PM PDT 24
Peak memory 200960 kb
Host smart-ca346485-4e61-4b53-b17c-8dacb3663d72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197519001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1197519001
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1137284965
Short name T300
Test name
Test status
Simulation time 148540141 ps
CPU time 1.85 seconds
Started Jun 24 05:35:55 PM PDT 24
Finished Jun 24 05:35:58 PM PDT 24
Peak memory 200696 kb
Host smart-383ec8ed-8fa7-433e-8198-e2682620c031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137284965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1137284965
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.695979038
Short name T343
Test name
Test status
Simulation time 136283090 ps
CPU time 1.03 seconds
Started Jun 24 05:36:00 PM PDT 24
Finished Jun 24 05:36:02 PM PDT 24
Peak memory 200680 kb
Host smart-1db6572c-eb9f-4521-b838-ef83490ec30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695979038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.695979038
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3277826929
Short name T438
Test name
Test status
Simulation time 74106818 ps
CPU time 0.87 seconds
Started Jun 24 05:35:57 PM PDT 24
Finished Jun 24 05:36:00 PM PDT 24
Peak memory 200516 kb
Host smart-b2c40739-7f35-4771-9062-3fe83bd2efee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277826929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3277826929
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.361409077
Short name T314
Test name
Test status
Simulation time 2354417552 ps
CPU time 8.34 seconds
Started Jun 24 05:35:54 PM PDT 24
Finished Jun 24 05:36:03 PM PDT 24
Peak memory 218416 kb
Host smart-57b00554-f5c9-4fcc-bc00-7914b4a56b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361409077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.361409077
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.122371220
Short name T504
Test name
Test status
Simulation time 244031647 ps
CPU time 1.09 seconds
Started Jun 24 05:35:56 PM PDT 24
Finished Jun 24 05:36:00 PM PDT 24
Peak memory 218068 kb
Host smart-a38227cf-a57a-4ea2-8939-e141b4dc2485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122371220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.122371220
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1498047438
Short name T489
Test name
Test status
Simulation time 189481393 ps
CPU time 0.93 seconds
Started Jun 24 05:35:57 PM PDT 24
Finished Jun 24 05:36:00 PM PDT 24
Peak memory 200508 kb
Host smart-bc58da3d-b681-4c6a-83a6-dc480a2c7058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498047438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1498047438
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.922926160
Short name T434
Test name
Test status
Simulation time 1408755448 ps
CPU time 5.57 seconds
Started Jun 24 05:35:55 PM PDT 24
Finished Jun 24 05:36:02 PM PDT 24
Peak memory 200888 kb
Host smart-819a1241-e22b-4792-bb3d-0dc5949ea6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922926160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.922926160
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3528474606
Short name T400
Test name
Test status
Simulation time 114372263 ps
CPU time 1.03 seconds
Started Jun 24 05:36:05 PM PDT 24
Finished Jun 24 05:36:07 PM PDT 24
Peak memory 200696 kb
Host smart-7530b883-27b0-40f1-836c-02981a9c7238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528474606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3528474606
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2068490219
Short name T264
Test name
Test status
Simulation time 118664576 ps
CPU time 1.21 seconds
Started Jun 24 05:35:56 PM PDT 24
Finished Jun 24 05:35:59 PM PDT 24
Peak memory 200896 kb
Host smart-31d6fdd8-f327-4d2c-accc-568dd29a8b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068490219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2068490219
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2798313444
Short name T320
Test name
Test status
Simulation time 253750935 ps
CPU time 1.78 seconds
Started Jun 24 05:35:57 PM PDT 24
Finished Jun 24 05:36:01 PM PDT 24
Peak memory 200820 kb
Host smart-0774b306-1be1-4b51-8466-072bef3ef48f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798313444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2798313444
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.887205767
Short name T538
Test name
Test status
Simulation time 135986184 ps
CPU time 1.66 seconds
Started Jun 24 05:35:55 PM PDT 24
Finished Jun 24 05:35:59 PM PDT 24
Peak memory 208924 kb
Host smart-a5409727-3e5e-4723-9c10-df929a0a9287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887205767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.887205767
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.403897590
Short name T8
Test name
Test status
Simulation time 175328090 ps
CPU time 1.3 seconds
Started Jun 24 05:35:57 PM PDT 24
Finished Jun 24 05:36:01 PM PDT 24
Peak memory 200704 kb
Host smart-8b0a3d94-af84-429d-85b3-9a21a579e7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403897590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.403897590
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2544817993
Short name T127
Test name
Test status
Simulation time 95944797 ps
CPU time 0.84 seconds
Started Jun 24 05:35:54 PM PDT 24
Finished Jun 24 05:35:56 PM PDT 24
Peak memory 200500 kb
Host smart-367e942d-b04a-49ce-81ed-c705915c29a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544817993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2544817993
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2661234163
Short name T48
Test name
Test status
Simulation time 1228716871 ps
CPU time 5.98 seconds
Started Jun 24 05:36:09 PM PDT 24
Finished Jun 24 05:36:15 PM PDT 24
Peak memory 218460 kb
Host smart-f95aafa9-42d1-42f4-9780-88960d996561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661234163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2661234163
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3918514913
Short name T490
Test name
Test status
Simulation time 244876079 ps
CPU time 1.04 seconds
Started Jun 24 05:35:54 PM PDT 24
Finished Jun 24 05:35:57 PM PDT 24
Peak memory 218064 kb
Host smart-0ad31334-0a8f-48ed-b998-3e02ba3f09e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918514913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3918514913
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.2152528591
Short name T422
Test name
Test status
Simulation time 205036286 ps
CPU time 0.88 seconds
Started Jun 24 05:36:01 PM PDT 24
Finished Jun 24 05:36:03 PM PDT 24
Peak memory 200516 kb
Host smart-0978e78f-d55f-4072-b8ea-766bb7dfcbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152528591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.2152528591
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.2769487041
Short name T30
Test name
Test status
Simulation time 1624633252 ps
CPU time 7.44 seconds
Started Jun 24 05:36:05 PM PDT 24
Finished Jun 24 05:36:13 PM PDT 24
Peak memory 200872 kb
Host smart-6b10b041-02be-4ddf-9620-af06922dcf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769487041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2769487041
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1162060761
Short name T146
Test name
Test status
Simulation time 148319661 ps
CPU time 1.15 seconds
Started Jun 24 05:35:59 PM PDT 24
Finished Jun 24 05:36:02 PM PDT 24
Peak memory 200692 kb
Host smart-29bf28d1-de65-4955-aa52-9597f59847f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162060761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1162060761
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2998051124
Short name T285
Test name
Test status
Simulation time 252667626 ps
CPU time 1.5 seconds
Started Jun 24 05:35:52 PM PDT 24
Finished Jun 24 05:35:54 PM PDT 24
Peak memory 200884 kb
Host smart-b36f5ef8-653a-4a09-90a9-09fde759af2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998051124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2998051124
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2959983625
Short name T212
Test name
Test status
Simulation time 5917452894 ps
CPU time 25.09 seconds
Started Jun 24 05:35:53 PM PDT 24
Finished Jun 24 05:36:19 PM PDT 24
Peak memory 200912 kb
Host smart-69a63a10-8151-4941-946c-336bf62f488f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959983625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2959983625
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1837037335
Short name T360
Test name
Test status
Simulation time 348117921 ps
CPU time 2.26 seconds
Started Jun 24 05:35:59 PM PDT 24
Finished Jun 24 05:36:03 PM PDT 24
Peak memory 200688 kb
Host smart-eb185ae8-84ba-499b-8a17-993a76397a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837037335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1837037335
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1686798312
Short name T297
Test name
Test status
Simulation time 289705675 ps
CPU time 1.62 seconds
Started Jun 24 05:35:55 PM PDT 24
Finished Jun 24 05:35:59 PM PDT 24
Peak memory 200892 kb
Host smart-ebeeca64-a594-4432-a0b3-544ddeab1010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686798312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1686798312
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1608362279
Short name T128
Test name
Test status
Simulation time 80074210 ps
CPU time 0.8 seconds
Started Jun 24 05:35:53 PM PDT 24
Finished Jun 24 05:35:55 PM PDT 24
Peak memory 200520 kb
Host smart-607eda05-6452-4e13-8bbb-c9c89a54358e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608362279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1608362279
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3843295690
Short name T9
Test name
Test status
Simulation time 1875623520 ps
CPU time 7.56 seconds
Started Jun 24 05:36:00 PM PDT 24
Finished Jun 24 05:36:08 PM PDT 24
Peak memory 218220 kb
Host smart-92931b1f-01af-4e59-bcab-cf117f3ab784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843295690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3843295690
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2984432923
Short name T356
Test name
Test status
Simulation time 243734512 ps
CPU time 1.15 seconds
Started Jun 24 05:35:54 PM PDT 24
Finished Jun 24 05:35:57 PM PDT 24
Peak memory 218068 kb
Host smart-7ba64d4c-5ff9-42f3-8be9-3f78daf34044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984432923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2984432923
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.428545207
Short name T20
Test name
Test status
Simulation time 177162153 ps
CPU time 0.86 seconds
Started Jun 24 05:36:04 PM PDT 24
Finished Jun 24 05:36:06 PM PDT 24
Peak memory 200468 kb
Host smart-c49ebf7c-8e55-42aa-9988-2fa1c48194e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428545207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.428545207
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.260669055
Short name T259
Test name
Test status
Simulation time 772618326 ps
CPU time 4.05 seconds
Started Jun 24 05:35:54 PM PDT 24
Finished Jun 24 05:36:00 PM PDT 24
Peak memory 200892 kb
Host smart-7d78ea85-ff5a-4b8e-9e10-8111e8dffa6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260669055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.260669055
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2092183474
Short name T199
Test name
Test status
Simulation time 175538389 ps
CPU time 1.17 seconds
Started Jun 24 05:35:56 PM PDT 24
Finished Jun 24 05:36:00 PM PDT 24
Peak memory 200700 kb
Host smart-71420c22-98e6-472c-9ba4-66655b858f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092183474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2092183474
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1143800908
Short name T153
Test name
Test status
Simulation time 199900114 ps
CPU time 1.39 seconds
Started Jun 24 05:35:56 PM PDT 24
Finished Jun 24 05:36:00 PM PDT 24
Peak memory 200896 kb
Host smart-934b8601-b675-4a7a-9004-cd79e40925d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143800908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1143800908
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3980403866
Short name T521
Test name
Test status
Simulation time 8513603862 ps
CPU time 27.82 seconds
Started Jun 24 05:36:05 PM PDT 24
Finished Jun 24 05:36:34 PM PDT 24
Peak memory 209084 kb
Host smart-32cb1075-4588-4a2d-9692-1b8c926e20b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980403866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3980403866
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.1512279945
Short name T221
Test name
Test status
Simulation time 377073252 ps
CPU time 2.39 seconds
Started Jun 24 05:35:54 PM PDT 24
Finished Jun 24 05:35:57 PM PDT 24
Peak memory 200720 kb
Host smart-5a1f9c7f-ebf8-4771-9bbf-22f6959f3847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512279945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1512279945
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1125209180
Short name T480
Test name
Test status
Simulation time 296121683 ps
CPU time 1.55 seconds
Started Jun 24 05:36:02 PM PDT 24
Finished Jun 24 05:36:05 PM PDT 24
Peak memory 200892 kb
Host smart-030fa4af-20f2-4420-9f81-8bbaa9488c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125209180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1125209180
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3586247602
Short name T210
Test name
Test status
Simulation time 67201738 ps
CPU time 0.77 seconds
Started Jun 24 05:35:56 PM PDT 24
Finished Jun 24 05:35:59 PM PDT 24
Peak memory 200520 kb
Host smart-80b6670c-deb0-4d34-9c3d-01e244cad1c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586247602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3586247602
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1545696241
Short name T349
Test name
Test status
Simulation time 1219464121 ps
CPU time 5.76 seconds
Started Jun 24 05:36:00 PM PDT 24
Finished Jun 24 05:36:07 PM PDT 24
Peak memory 222392 kb
Host smart-7d9594d7-a264-4dcb-bd8a-5ef4e4f01d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545696241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1545696241
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2980704847
Short name T6
Test name
Test status
Simulation time 243778274 ps
CPU time 1.06 seconds
Started Jun 24 05:35:55 PM PDT 24
Finished Jun 24 05:35:58 PM PDT 24
Peak memory 218068 kb
Host smart-dde8330c-d6e6-4129-ab44-33e0581f6bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980704847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2980704847
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3611647092
Short name T24
Test name
Test status
Simulation time 148608315 ps
CPU time 0.83 seconds
Started Jun 24 05:35:57 PM PDT 24
Finished Jun 24 05:36:00 PM PDT 24
Peak memory 200512 kb
Host smart-1447ce6b-2e57-4cf0-ba2a-3f6bc3bbc7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611647092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3611647092
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1522724957
Short name T413
Test name
Test status
Simulation time 1856878077 ps
CPU time 7.1 seconds
Started Jun 24 05:35:54 PM PDT 24
Finished Jun 24 05:36:03 PM PDT 24
Peak memory 201072 kb
Host smart-9b189c1e-2f6e-462a-9475-4f4ba8bd89fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522724957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1522724957
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1854528967
Short name T476
Test name
Test status
Simulation time 154332394 ps
CPU time 1.17 seconds
Started Jun 24 05:35:54 PM PDT 24
Finished Jun 24 05:35:57 PM PDT 24
Peak memory 200716 kb
Host smart-6ae0f12d-6b5a-43bd-be96-a604ec7c4b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854528967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1854528967
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.305448744
Short name T179
Test name
Test status
Simulation time 124323086 ps
CPU time 1.21 seconds
Started Jun 24 05:35:55 PM PDT 24
Finished Jun 24 05:35:58 PM PDT 24
Peak memory 200904 kb
Host smart-ea6c5431-87e5-4c67-adca-518659b24992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305448744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.305448744
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1929063792
Short name T195
Test name
Test status
Simulation time 4459809731 ps
CPU time 20.11 seconds
Started Jun 24 05:35:50 PM PDT 24
Finished Jun 24 05:36:21 PM PDT 24
Peak memory 217304 kb
Host smart-371c2f4d-ee53-4406-873d-b8502b68cedb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929063792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1929063792
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2937206233
Short name T479
Test name
Test status
Simulation time 314949213 ps
CPU time 2.11 seconds
Started Jun 24 05:36:02 PM PDT 24
Finished Jun 24 05:36:05 PM PDT 24
Peak memory 200692 kb
Host smart-dc48559a-a36b-485b-8400-21981cff16d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937206233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2937206233
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2025782485
Short name T385
Test name
Test status
Simulation time 291326714 ps
CPU time 1.59 seconds
Started Jun 24 05:36:07 PM PDT 24
Finished Jun 24 05:36:09 PM PDT 24
Peak memory 200892 kb
Host smart-3c7caafb-8b32-49f4-af6a-9ffa49571aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025782485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2025782485
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.614597114
Short name T205
Test name
Test status
Simulation time 58706126 ps
CPU time 0.73 seconds
Started Jun 24 05:35:57 PM PDT 24
Finished Jun 24 05:36:00 PM PDT 24
Peak memory 200344 kb
Host smart-101328fc-f890-4cca-b629-43ed4f55b890
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614597114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.614597114
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2753407421
Short name T40
Test name
Test status
Simulation time 1219958672 ps
CPU time 6.01 seconds
Started Jun 24 05:36:01 PM PDT 24
Finished Jun 24 05:36:08 PM PDT 24
Peak memory 218504 kb
Host smart-22730927-e6b6-4ba0-8641-a0ab5123d065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753407421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2753407421
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.71721605
Short name T86
Test name
Test status
Simulation time 243653267 ps
CPU time 1.05 seconds
Started Jun 24 05:35:57 PM PDT 24
Finished Jun 24 05:36:01 PM PDT 24
Peak memory 217940 kb
Host smart-cd88e3e4-2da5-4eaf-9aab-c984dae63311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71721605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.71721605
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2780566874
Short name T235
Test name
Test status
Simulation time 216901464 ps
CPU time 0.93 seconds
Started Jun 24 05:35:54 PM PDT 24
Finished Jun 24 05:35:55 PM PDT 24
Peak memory 200416 kb
Host smart-b877ad0d-a6e8-4fb1-a675-77ada341254a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780566874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2780566874
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2685823537
Short name T100
Test name
Test status
Simulation time 1700038467 ps
CPU time 7.13 seconds
Started Jun 24 05:35:54 PM PDT 24
Finished Jun 24 05:36:03 PM PDT 24
Peak memory 200892 kb
Host smart-339f0eca-f5f4-48b8-a198-7cef4b60ca1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685823537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2685823537
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2149179719
Short name T50
Test name
Test status
Simulation time 177322280 ps
CPU time 1.22 seconds
Started Jun 24 05:36:06 PM PDT 24
Finished Jun 24 05:36:08 PM PDT 24
Peak memory 200684 kb
Host smart-0b04d4ec-5406-4406-ac3f-ed87cd77a289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149179719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2149179719
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3228954089
Short name T156
Test name
Test status
Simulation time 208486972 ps
CPU time 1.38 seconds
Started Jun 24 05:35:55 PM PDT 24
Finished Jun 24 05:35:59 PM PDT 24
Peak memory 200892 kb
Host smart-1f2bbde7-2220-4b4a-b586-98f5703f1879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228954089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3228954089
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.502821269
Short name T537
Test name
Test status
Simulation time 3381896860 ps
CPU time 12.15 seconds
Started Jun 24 05:35:56 PM PDT 24
Finished Jun 24 05:36:11 PM PDT 24
Peak memory 209120 kb
Host smart-846a03fe-3d4c-458b-ab75-a78bd73185bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502821269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.502821269
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2367883892
Short name T89
Test name
Test status
Simulation time 253529968 ps
CPU time 1.78 seconds
Started Jun 24 05:35:57 PM PDT 24
Finished Jun 24 05:36:01 PM PDT 24
Peak memory 200704 kb
Host smart-7b2160f5-22f3-4c9b-8fe0-8614a72f67f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367883892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2367883892
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1503937502
Short name T1
Test name
Test status
Simulation time 93358874 ps
CPU time 0.92 seconds
Started Jun 24 05:35:56 PM PDT 24
Finished Jun 24 05:35:59 PM PDT 24
Peak memory 200704 kb
Host smart-7ed1547b-4037-46c3-b6a1-8266a60bc515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503937502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1503937502
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.527146518
Short name T280
Test name
Test status
Simulation time 66324761 ps
CPU time 0.74 seconds
Started Jun 24 05:35:21 PM PDT 24
Finished Jun 24 05:35:23 PM PDT 24
Peak memory 200500 kb
Host smart-c4a86987-e3d2-475f-9f97-188c686427ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527146518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.527146518
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2178712727
Short name T302
Test name
Test status
Simulation time 1897385893 ps
CPU time 6.93 seconds
Started Jun 24 05:35:05 PM PDT 24
Finished Jun 24 05:35:15 PM PDT 24
Peak memory 218476 kb
Host smart-069e1681-ad51-44f5-bd6c-d17bbf9335ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178712727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2178712727
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1004010670
Short name T234
Test name
Test status
Simulation time 243957950 ps
CPU time 1.11 seconds
Started Jun 24 05:35:10 PM PDT 24
Finished Jun 24 05:35:12 PM PDT 24
Peak memory 218068 kb
Host smart-3ee141ab-54f8-4dd1-85a6-e1043b30bca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004010670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1004010670
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.2902735155
Short name T520
Test name
Test status
Simulation time 105618242 ps
CPU time 0.85 seconds
Started Jun 24 05:35:02 PM PDT 24
Finished Jun 24 05:35:05 PM PDT 24
Peak memory 200512 kb
Host smart-35803214-fb27-41d5-b880-7600a118efce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902735155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2902735155
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.4290908407
Short name T445
Test name
Test status
Simulation time 1426924505 ps
CPU time 6.21 seconds
Started Jun 24 05:35:04 PM PDT 24
Finished Jun 24 05:35:13 PM PDT 24
Peak memory 200900 kb
Host smart-cc3f3298-984f-40f2-a61c-654b1f5051f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290908407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.4290908407
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.1478551105
Short name T71
Test name
Test status
Simulation time 16545668005 ps
CPU time 26.64 seconds
Started Jun 24 05:35:00 PM PDT 24
Finished Jun 24 05:35:27 PM PDT 24
Peak memory 217656 kb
Host smart-8bd70440-217c-4355-8543-c21bcef48a7a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478551105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1478551105
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1016609348
Short name T144
Test name
Test status
Simulation time 101824697 ps
CPU time 1.03 seconds
Started Jun 24 05:35:02 PM PDT 24
Finished Jun 24 05:35:05 PM PDT 24
Peak memory 200692 kb
Host smart-8a8bd39b-fb8c-457c-9322-28fe2aeeeec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016609348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1016609348
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3703637536
Short name T184
Test name
Test status
Simulation time 211273597 ps
CPU time 1.38 seconds
Started Jun 24 05:35:02 PM PDT 24
Finished Jun 24 05:35:05 PM PDT 24
Peak memory 200872 kb
Host smart-8fa69cfe-4046-4a9d-a49a-69a7705d9235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703637536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3703637536
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3957332923
Short name T334
Test name
Test status
Simulation time 4223738050 ps
CPU time 14.76 seconds
Started Jun 24 05:35:06 PM PDT 24
Finished Jun 24 05:35:24 PM PDT 24
Peak memory 209136 kb
Host smart-cc9dfee8-6eda-4079-88d7-c064ce2f9d5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957332923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3957332923
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2643579256
Short name T287
Test name
Test status
Simulation time 512817245 ps
CPU time 2.7 seconds
Started Jun 24 05:35:02 PM PDT 24
Finished Jun 24 05:35:07 PM PDT 24
Peak memory 200692 kb
Host smart-3279e6a9-f04d-491d-8b81-98a9eb361f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643579256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2643579256
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.3351844863
Short name T211
Test name
Test status
Simulation time 123738745 ps
CPU time 1.06 seconds
Started Jun 24 05:35:13 PM PDT 24
Finished Jun 24 05:35:15 PM PDT 24
Peak memory 200704 kb
Host smart-0b9756e9-574a-4e76-baee-e04cee9bdba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351844863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.3351844863
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.4185052918
Short name T131
Test name
Test status
Simulation time 61660496 ps
CPU time 0.82 seconds
Started Jun 24 05:35:55 PM PDT 24
Finished Jun 24 05:35:57 PM PDT 24
Peak memory 200496 kb
Host smart-b7dd8df0-cdd4-4f92-aba9-488dbfe8b7e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185052918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.4185052918
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2468866512
Short name T530
Test name
Test status
Simulation time 1229739042 ps
CPU time 6.1 seconds
Started Jun 24 05:35:55 PM PDT 24
Finished Jun 24 05:36:04 PM PDT 24
Peak memory 218444 kb
Host smart-4f37aeb6-92c2-4b2f-b813-fb274cbf6968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468866512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2468866512
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1793237758
Short name T266
Test name
Test status
Simulation time 245276192 ps
CPU time 1.14 seconds
Started Jun 24 05:35:55 PM PDT 24
Finished Jun 24 05:35:59 PM PDT 24
Peak memory 218084 kb
Host smart-6f0dff21-a896-48c8-8d5c-8b5647f16ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793237758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1793237758
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.1256423667
Short name T21
Test name
Test status
Simulation time 136951722 ps
CPU time 0.81 seconds
Started Jun 24 05:36:07 PM PDT 24
Finished Jun 24 05:36:09 PM PDT 24
Peak memory 200488 kb
Host smart-2b026e56-c848-41ae-920a-cd53b5f285a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256423667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1256423667
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.1979118569
Short name T492
Test name
Test status
Simulation time 1299007641 ps
CPU time 4.98 seconds
Started Jun 24 05:35:59 PM PDT 24
Finished Jun 24 05:36:05 PM PDT 24
Peak memory 200924 kb
Host smart-45546a8b-c630-4668-be25-148354dc8bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979118569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.1979118569
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1409038131
Short name T122
Test name
Test status
Simulation time 174772836 ps
CPU time 1.19 seconds
Started Jun 24 05:35:56 PM PDT 24
Finished Jun 24 05:35:59 PM PDT 24
Peak memory 200696 kb
Host smart-a0fb5374-cdd8-465a-9440-ad151bcfbde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409038131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1409038131
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.4059521133
Short name T446
Test name
Test status
Simulation time 123076949 ps
CPU time 1.18 seconds
Started Jun 24 05:35:59 PM PDT 24
Finished Jun 24 05:36:01 PM PDT 24
Peak memory 200904 kb
Host smart-ccef9b67-2d86-4c64-8c1d-2ad9b6de4cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059521133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.4059521133
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2876867133
Short name T192
Test name
Test status
Simulation time 5002452842 ps
CPU time 24.45 seconds
Started Jun 24 05:35:54 PM PDT 24
Finished Jun 24 05:36:20 PM PDT 24
Peak memory 209132 kb
Host smart-c8ce3a70-355e-42f5-8200-ea72118415d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876867133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2876867133
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.3484195065
Short name T178
Test name
Test status
Simulation time 450906213 ps
CPU time 2.42 seconds
Started Jun 24 05:35:57 PM PDT 24
Finished Jun 24 05:36:01 PM PDT 24
Peak memory 200728 kb
Host smart-efe031e0-6adf-43ac-a4ff-3aabf9b69d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484195065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3484195065
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3736373916
Short name T187
Test name
Test status
Simulation time 173993849 ps
CPU time 1.31 seconds
Started Jun 24 05:35:53 PM PDT 24
Finished Jun 24 05:35:56 PM PDT 24
Peak memory 200932 kb
Host smart-ebce8555-0566-4018-b0d2-f1e328cee51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736373916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3736373916
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3197350379
Short name T160
Test name
Test status
Simulation time 82407216 ps
CPU time 0.86 seconds
Started Jun 24 05:36:09 PM PDT 24
Finished Jun 24 05:36:11 PM PDT 24
Peak memory 200740 kb
Host smart-75accb24-d48e-4b5c-8793-88c3817eabf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197350379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3197350379
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2750283897
Short name T238
Test name
Test status
Simulation time 2179164281 ps
CPU time 8.11 seconds
Started Jun 24 05:36:08 PM PDT 24
Finished Jun 24 05:36:17 PM PDT 24
Peak memory 218760 kb
Host smart-6a1d7bbd-f521-411a-80a8-9a15cbd91e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750283897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2750283897
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.4012102248
Short name T159
Test name
Test status
Simulation time 244277610 ps
CPU time 1.24 seconds
Started Jun 24 05:36:08 PM PDT 24
Finished Jun 24 05:36:10 PM PDT 24
Peak memory 218084 kb
Host smart-8da6ec2a-c9db-4bf6-b3a3-64cb4d12a6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012102248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.4012102248
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.2404221715
Short name T307
Test name
Test status
Simulation time 202456858 ps
CPU time 0.88 seconds
Started Jun 24 05:36:02 PM PDT 24
Finished Jun 24 05:36:04 PM PDT 24
Peak memory 200448 kb
Host smart-6a9843da-7d04-4321-8914-a1cfb1cabf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404221715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2404221715
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3844809801
Short name T132
Test name
Test status
Simulation time 1482338525 ps
CPU time 6.23 seconds
Started Jun 24 05:36:03 PM PDT 24
Finished Jun 24 05:36:10 PM PDT 24
Peak memory 200888 kb
Host smart-f16262c8-ba0a-4ef9-8df0-98efbfe6b0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844809801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3844809801
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.4204942202
Short name T444
Test name
Test status
Simulation time 161444316 ps
CPU time 1.17 seconds
Started Jun 24 05:36:02 PM PDT 24
Finished Jun 24 05:36:05 PM PDT 24
Peak memory 200700 kb
Host smart-97d3deeb-6b81-4f90-8139-4e3d932874e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204942202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.4204942202
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.4251638326
Short name T296
Test name
Test status
Simulation time 253029411 ps
CPU time 1.49 seconds
Started Jun 24 05:35:55 PM PDT 24
Finished Jun 24 05:35:58 PM PDT 24
Peak memory 200892 kb
Host smart-ac9fee62-d2e3-41d5-9c76-b9251231bc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251638326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.4251638326
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3713932487
Short name T419
Test name
Test status
Simulation time 3392554888 ps
CPU time 11.78 seconds
Started Jun 24 05:36:12 PM PDT 24
Finished Jun 24 05:36:25 PM PDT 24
Peak memory 209136 kb
Host smart-83c2d18a-76f2-4ecd-989a-94fbc7c04dc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713932487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3713932487
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1610424518
Short name T405
Test name
Test status
Simulation time 112748002 ps
CPU time 1.51 seconds
Started Jun 24 05:36:06 PM PDT 24
Finished Jun 24 05:36:08 PM PDT 24
Peak memory 200920 kb
Host smart-6011b573-6cd2-4875-a7f3-3875e8de8afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610424518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1610424518
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1019036411
Short name T421
Test name
Test status
Simulation time 67453437 ps
CPU time 0.82 seconds
Started Jun 24 05:36:08 PM PDT 24
Finished Jun 24 05:36:09 PM PDT 24
Peak memory 200708 kb
Host smart-f689dca6-fd68-46d6-bf6e-24fd164db8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019036411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1019036411
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3884578624
Short name T409
Test name
Test status
Simulation time 88037827 ps
CPU time 0.84 seconds
Started Jun 24 05:36:02 PM PDT 24
Finished Jun 24 05:36:04 PM PDT 24
Peak memory 200428 kb
Host smart-8e689c8e-aeb0-4f46-8698-6dc29f351ba7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884578624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3884578624
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.3034905604
Short name T45
Test name
Test status
Simulation time 1874035802 ps
CPU time 6.85 seconds
Started Jun 24 05:35:55 PM PDT 24
Finished Jun 24 05:36:04 PM PDT 24
Peak memory 217448 kb
Host smart-e4d56f5b-aab2-4c0b-ac91-f2a8a78b8874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034905604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.3034905604
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.233761485
Short name T519
Test name
Test status
Simulation time 245069057 ps
CPU time 1.09 seconds
Started Jun 24 05:35:59 PM PDT 24
Finished Jun 24 05:36:01 PM PDT 24
Peak memory 217996 kb
Host smart-dd061391-7395-4908-a1f8-a0b967419280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233761485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.233761485
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2953040356
Short name T443
Test name
Test status
Simulation time 151040700 ps
CPU time 0.81 seconds
Started Jun 24 05:35:57 PM PDT 24
Finished Jun 24 05:36:00 PM PDT 24
Peak memory 200440 kb
Host smart-484ddf3b-5dc1-4560-8872-78d7479d85ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953040356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2953040356
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.2267993393
Short name T204
Test name
Test status
Simulation time 915406822 ps
CPU time 5.1 seconds
Started Jun 24 05:36:03 PM PDT 24
Finished Jun 24 05:36:09 PM PDT 24
Peak memory 200892 kb
Host smart-97a7b175-431f-48bd-95c0-ff92fbe4fbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267993393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2267993393
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.621565105
Short name T244
Test name
Test status
Simulation time 171579698 ps
CPU time 1.31 seconds
Started Jun 24 05:36:08 PM PDT 24
Finished Jun 24 05:36:10 PM PDT 24
Peak memory 200912 kb
Host smart-af015b9e-4ff2-48b6-90f8-5cd98dc9ca14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621565105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.621565105
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.1995752546
Short name T333
Test name
Test status
Simulation time 201705838 ps
CPU time 1.42 seconds
Started Jun 24 05:36:09 PM PDT 24
Finished Jun 24 05:36:11 PM PDT 24
Peak memory 200888 kb
Host smart-e01a313d-2de2-4d42-a831-be361ec9ce5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995752546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1995752546
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.3268396330
Short name T288
Test name
Test status
Simulation time 4644353851 ps
CPU time 17.89 seconds
Started Jun 24 05:36:04 PM PDT 24
Finished Jun 24 05:36:22 PM PDT 24
Peak memory 200940 kb
Host smart-fa1aed29-221b-4561-b958-bf6229880283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268396330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3268396330
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.19234184
Short name T175
Test name
Test status
Simulation time 125578638 ps
CPU time 1.59 seconds
Started Jun 24 05:36:03 PM PDT 24
Finished Jun 24 05:36:06 PM PDT 24
Peak memory 200736 kb
Host smart-2e878f30-4568-440d-816a-9f1314e3328a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19234184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.19234184
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.2093479207
Short name T252
Test name
Test status
Simulation time 169730803 ps
CPU time 1.17 seconds
Started Jun 24 05:36:04 PM PDT 24
Finished Jun 24 05:36:06 PM PDT 24
Peak memory 200736 kb
Host smart-986266a0-e1aa-4371-88f2-65be84ed978a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093479207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2093479207
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3396916392
Short name T453
Test name
Test status
Simulation time 66859944 ps
CPU time 0.79 seconds
Started Jun 24 05:36:16 PM PDT 24
Finished Jun 24 05:36:19 PM PDT 24
Peak memory 200428 kb
Host smart-dca9350a-edb6-4510-a875-7929fc81aef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396916392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3396916392
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2800201598
Short name T35
Test name
Test status
Simulation time 1223496770 ps
CPU time 5.33 seconds
Started Jun 24 05:36:19 PM PDT 24
Finished Jun 24 05:36:26 PM PDT 24
Peak memory 217532 kb
Host smart-debc9d4c-e41f-4277-9b11-6952bc1dc467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800201598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2800201598
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.374118916
Short name T172
Test name
Test status
Simulation time 244237701 ps
CPU time 1.04 seconds
Started Jun 24 05:36:11 PM PDT 24
Finished Jun 24 05:36:13 PM PDT 24
Peak memory 218072 kb
Host smart-8b96e616-10de-4a74-97fb-a4cf1cca8d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374118916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.374118916
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.1917552459
Short name T461
Test name
Test status
Simulation time 122579017 ps
CPU time 0.81 seconds
Started Jun 24 05:36:01 PM PDT 24
Finished Jun 24 05:36:03 PM PDT 24
Peak memory 200516 kb
Host smart-d7f30c68-ada9-4664-8f54-622fc185a312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917552459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1917552459
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1260467912
Short name T491
Test name
Test status
Simulation time 1423661477 ps
CPU time 5.41 seconds
Started Jun 24 05:35:59 PM PDT 24
Finished Jun 24 05:36:06 PM PDT 24
Peak memory 200848 kb
Host smart-3af1b984-d320-4fe9-9305-83d020f1386b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260467912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1260467912
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3828565274
Short name T514
Test name
Test status
Simulation time 108982491 ps
CPU time 1.04 seconds
Started Jun 24 05:35:55 PM PDT 24
Finished Jun 24 05:35:57 PM PDT 24
Peak memory 200680 kb
Host smart-b7f54da0-e5b8-4a07-8d8d-3bcee2fc0728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828565274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3828565274
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1354190863
Short name T220
Test name
Test status
Simulation time 246069492 ps
CPU time 1.62 seconds
Started Jun 24 05:35:57 PM PDT 24
Finished Jun 24 05:36:01 PM PDT 24
Peak memory 200900 kb
Host smart-120a9754-1224-4c75-ade5-cf05d31ede0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354190863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1354190863
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1857101091
Short name T533
Test name
Test status
Simulation time 1038582821 ps
CPU time 4.63 seconds
Started Jun 24 05:36:27 PM PDT 24
Finished Jun 24 05:36:34 PM PDT 24
Peak memory 200872 kb
Host smart-7c26fb70-b524-464e-a3fe-ca608e134091
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857101091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1857101091
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.321064398
Short name T526
Test name
Test status
Simulation time 472026986 ps
CPU time 2.68 seconds
Started Jun 24 05:35:59 PM PDT 24
Finished Jun 24 05:36:03 PM PDT 24
Peak memory 208872 kb
Host smart-9c128271-fe85-46b5-810f-4f6821c89b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321064398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.321064398
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.4191673726
Short name T494
Test name
Test status
Simulation time 127372553 ps
CPU time 1.13 seconds
Started Jun 24 05:36:03 PM PDT 24
Finished Jun 24 05:36:05 PM PDT 24
Peak memory 200716 kb
Host smart-8ae3ce05-da73-45a9-99fd-c8edae8f99bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191673726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.4191673726
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3086534083
Short name T529
Test name
Test status
Simulation time 82523528 ps
CPU time 0.77 seconds
Started Jun 24 05:36:16 PM PDT 24
Finished Jun 24 05:36:19 PM PDT 24
Peak memory 200476 kb
Host smart-d2e4b291-99b1-46b4-adf3-c9c0fb06d6b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086534083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3086534083
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.851233067
Short name T410
Test name
Test status
Simulation time 1225795090 ps
CPU time 5.6 seconds
Started Jun 24 05:36:19 PM PDT 24
Finished Jun 24 05:36:27 PM PDT 24
Peak memory 218480 kb
Host smart-cd867926-ccde-4adf-a5f1-aaf2ab6abe53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851233067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.851233067
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1523534292
Short name T500
Test name
Test status
Simulation time 243917461 ps
CPU time 1.11 seconds
Started Jun 24 05:36:10 PM PDT 24
Finished Jun 24 05:36:12 PM PDT 24
Peak memory 218120 kb
Host smart-17d2d246-e249-4c0f-a980-752d1123f17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523534292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1523534292
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3476964154
Short name T502
Test name
Test status
Simulation time 214148775 ps
CPU time 0.87 seconds
Started Jun 24 05:36:14 PM PDT 24
Finished Jun 24 05:36:17 PM PDT 24
Peak memory 200516 kb
Host smart-19d950c7-4000-4438-82fa-0d25862e4b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476964154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3476964154
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.275115240
Short name T262
Test name
Test status
Simulation time 707252827 ps
CPU time 3.81 seconds
Started Jun 24 05:36:16 PM PDT 24
Finished Jun 24 05:36:21 PM PDT 24
Peak memory 200900 kb
Host smart-3173923c-4d57-422e-9c87-1c53695db547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275115240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.275115240
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1156165433
Short name T449
Test name
Test status
Simulation time 112822207 ps
CPU time 1 seconds
Started Jun 24 05:36:13 PM PDT 24
Finished Jun 24 05:36:15 PM PDT 24
Peak memory 200696 kb
Host smart-775c697b-7190-4918-b708-91389a4b80d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156165433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1156165433
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3113510042
Short name T158
Test name
Test status
Simulation time 127829212 ps
CPU time 1.27 seconds
Started Jun 24 05:36:24 PM PDT 24
Finished Jun 24 05:36:27 PM PDT 24
Peak memory 200892 kb
Host smart-4977eae1-f400-4cd1-a934-23314336487c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113510042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3113510042
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1938457916
Short name T377
Test name
Test status
Simulation time 12378889745 ps
CPU time 42.73 seconds
Started Jun 24 05:36:15 PM PDT 24
Finished Jun 24 05:37:00 PM PDT 24
Peak memory 200936 kb
Host smart-2c366b64-1b93-47c9-b1eb-95395b97b7c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938457916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1938457916
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.2680772355
Short name T136
Test name
Test status
Simulation time 383357709 ps
CPU time 2.45 seconds
Started Jun 24 05:36:13 PM PDT 24
Finished Jun 24 05:36:17 PM PDT 24
Peak memory 200708 kb
Host smart-119553fe-62a0-421f-94af-4c99f2f456df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680772355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2680772355
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1914766766
Short name T31
Test name
Test status
Simulation time 122653290 ps
CPU time 1.05 seconds
Started Jun 24 05:36:10 PM PDT 24
Finished Jun 24 05:36:12 PM PDT 24
Peak memory 200628 kb
Host smart-df27c4c9-0155-4f91-92cb-25c89c1e8542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914766766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1914766766
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.2299547214
Short name T473
Test name
Test status
Simulation time 61247689 ps
CPU time 0.76 seconds
Started Jun 24 05:36:17 PM PDT 24
Finished Jun 24 05:36:19 PM PDT 24
Peak memory 200420 kb
Host smart-73cdadf0-02db-4b8f-9045-fb86bb951ade
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299547214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2299547214
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.435088905
Short name T510
Test name
Test status
Simulation time 1220255085 ps
CPU time 5.57 seconds
Started Jun 24 05:36:23 PM PDT 24
Finished Jun 24 05:36:31 PM PDT 24
Peak memory 218488 kb
Host smart-bf4e50d3-f3f7-4f26-a23b-3ff3b28e3b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435088905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.435088905
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3729408538
Short name T174
Test name
Test status
Simulation time 245281546 ps
CPU time 1.16 seconds
Started Jun 24 05:36:25 PM PDT 24
Finished Jun 24 05:36:29 PM PDT 24
Peak memory 218012 kb
Host smart-b669153a-be97-4026-8b1a-bbdd5dbfdbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729408538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3729408538
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1456828541
Short name T488
Test name
Test status
Simulation time 95031336 ps
CPU time 0.8 seconds
Started Jun 24 05:36:21 PM PDT 24
Finished Jun 24 05:36:24 PM PDT 24
Peak memory 200444 kb
Host smart-8b6cb2d5-027c-49af-a830-3056eb29bb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456828541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1456828541
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2552254407
Short name T515
Test name
Test status
Simulation time 1737459635 ps
CPU time 7.03 seconds
Started Jun 24 05:36:17 PM PDT 24
Finished Jun 24 05:36:25 PM PDT 24
Peak memory 200848 kb
Host smart-97bbda7b-e7ce-44b3-b6f5-febe5cc46c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552254407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2552254407
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3484659370
Short name T161
Test name
Test status
Simulation time 107732184 ps
CPU time 0.99 seconds
Started Jun 24 05:36:13 PM PDT 24
Finished Jun 24 05:36:15 PM PDT 24
Peak memory 200716 kb
Host smart-245430f9-2ece-4d21-b390-3f7d258c2ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484659370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3484659370
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2966092969
Short name T384
Test name
Test status
Simulation time 257449054 ps
CPU time 1.47 seconds
Started Jun 24 05:36:10 PM PDT 24
Finished Jun 24 05:36:12 PM PDT 24
Peak memory 200884 kb
Host smart-d4bb3d51-284d-4711-bd67-4e733f053f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966092969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2966092969
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1688292941
Short name T44
Test name
Test status
Simulation time 5639983944 ps
CPU time 21.02 seconds
Started Jun 24 05:36:11 PM PDT 24
Finished Jun 24 05:36:33 PM PDT 24
Peak memory 209752 kb
Host smart-30335154-bf77-4a63-b1f5-5c648e649ddf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688292941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1688292941
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1179443741
Short name T323
Test name
Test status
Simulation time 145288317 ps
CPU time 1.89 seconds
Started Jun 24 05:36:07 PM PDT 24
Finished Jun 24 05:36:10 PM PDT 24
Peak memory 200680 kb
Host smart-e99d4342-e8b6-4366-81a6-8b40d93850f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179443741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1179443741
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2460407721
Short name T278
Test name
Test status
Simulation time 131119930 ps
CPU time 1.05 seconds
Started Jun 24 05:36:10 PM PDT 24
Finished Jun 24 05:36:11 PM PDT 24
Peak memory 200708 kb
Host smart-79e35bd4-d3b5-46f2-b5a3-5413997ec820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460407721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2460407721
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3590813374
Short name T177
Test name
Test status
Simulation time 68697511 ps
CPU time 0.82 seconds
Started Jun 24 05:36:16 PM PDT 24
Finished Jun 24 05:36:18 PM PDT 24
Peak memory 200476 kb
Host smart-3315edf9-83ef-452b-b423-d4b15516f66a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590813374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3590813374
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.2788953707
Short name T509
Test name
Test status
Simulation time 1228756571 ps
CPU time 5.7 seconds
Started Jun 24 05:36:21 PM PDT 24
Finished Jun 24 05:36:28 PM PDT 24
Peak memory 222432 kb
Host smart-fbb9b03e-043d-4264-bb98-6b9c487400c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788953707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2788953707
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1388055330
Short name T392
Test name
Test status
Simulation time 245781964 ps
CPU time 1.06 seconds
Started Jun 24 05:36:17 PM PDT 24
Finished Jun 24 05:36:20 PM PDT 24
Peak memory 218064 kb
Host smart-ddfa6d9e-6f17-40a1-995d-7f923acd2d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388055330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1388055330
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3788971104
Short name T216
Test name
Test status
Simulation time 105031747 ps
CPU time 0.79 seconds
Started Jun 24 05:36:15 PM PDT 24
Finished Jun 24 05:36:18 PM PDT 24
Peak memory 200512 kb
Host smart-03c9410f-57d7-44f6-9837-09649507bc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788971104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3788971104
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.4032416022
Short name T516
Test name
Test status
Simulation time 2008347342 ps
CPU time 7.92 seconds
Started Jun 24 05:36:14 PM PDT 24
Finished Jun 24 05:36:23 PM PDT 24
Peak memory 200924 kb
Host smart-22234225-11c2-4918-a277-0466b625544c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032416022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.4032416022
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.179511678
Short name T462
Test name
Test status
Simulation time 183370628 ps
CPU time 1.17 seconds
Started Jun 24 05:36:15 PM PDT 24
Finished Jun 24 05:36:18 PM PDT 24
Peak memory 200688 kb
Host smart-76be530c-b7a8-4cad-8fbc-ee96004181ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179511678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.179511678
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.586057573
Short name T450
Test name
Test status
Simulation time 119412654 ps
CPU time 1.23 seconds
Started Jun 24 05:36:15 PM PDT 24
Finished Jun 24 05:36:18 PM PDT 24
Peak memory 200900 kb
Host smart-45d17276-0cb6-47af-a2bb-c20fd628ba86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586057573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.586057573
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1012260263
Short name T176
Test name
Test status
Simulation time 1969969539 ps
CPU time 10.37 seconds
Started Jun 24 05:36:13 PM PDT 24
Finished Jun 24 05:36:24 PM PDT 24
Peak memory 209104 kb
Host smart-1b61277c-15be-46b5-8a86-f2d4c62e0483
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012260263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1012260263
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.1736963980
Short name T181
Test name
Test status
Simulation time 375664219 ps
CPU time 2.21 seconds
Started Jun 24 05:36:14 PM PDT 24
Finished Jun 24 05:36:18 PM PDT 24
Peak memory 200688 kb
Host smart-ec43abca-5ed1-43d7-acc4-0a89f2e5f537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736963980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1736963980
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2088525479
Short name T465
Test name
Test status
Simulation time 181445871 ps
CPU time 1.31 seconds
Started Jun 24 05:36:21 PM PDT 24
Finished Jun 24 05:36:24 PM PDT 24
Peak memory 200708 kb
Host smart-a3fa6af3-67de-429a-82c0-e5560862744b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088525479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2088525479
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.292423568
Short name T498
Test name
Test status
Simulation time 82120698 ps
CPU time 0.89 seconds
Started Jun 24 05:36:16 PM PDT 24
Finished Jun 24 05:36:19 PM PDT 24
Peak memory 200516 kb
Host smart-352e33e2-1f7a-4893-b0e6-944db43d20e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292423568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.292423568
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3585793117
Short name T339
Test name
Test status
Simulation time 1216792541 ps
CPU time 5.44 seconds
Started Jun 24 05:36:19 PM PDT 24
Finished Jun 24 05:36:26 PM PDT 24
Peak memory 218456 kb
Host smart-12a5d1b8-36ea-4c8c-8abf-1c86c9bec526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585793117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3585793117
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2328486113
Short name T279
Test name
Test status
Simulation time 244440419 ps
CPU time 1.01 seconds
Started Jun 24 05:36:20 PM PDT 24
Finished Jun 24 05:36:23 PM PDT 24
Peak memory 218068 kb
Host smart-2a60e647-b054-4bc6-b699-358816325229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328486113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2328486113
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.1388188010
Short name T22
Test name
Test status
Simulation time 203280990 ps
CPU time 1.01 seconds
Started Jun 24 05:36:16 PM PDT 24
Finished Jun 24 05:36:18 PM PDT 24
Peak memory 200512 kb
Host smart-cc4cb833-a2b6-4849-8cfc-ad27bdc30159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388188010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1388188010
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1451965318
Short name T97
Test name
Test status
Simulation time 980673109 ps
CPU time 4.95 seconds
Started Jun 24 05:36:14 PM PDT 24
Finished Jun 24 05:36:21 PM PDT 24
Peak memory 200888 kb
Host smart-3d937b49-bc0d-46bd-868c-a3bcb4e6e77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451965318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1451965318
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3672190923
Short name T528
Test name
Test status
Simulation time 153983608 ps
CPU time 1.13 seconds
Started Jun 24 05:36:20 PM PDT 24
Finished Jun 24 05:36:23 PM PDT 24
Peak memory 200704 kb
Host smart-3f81ca1c-7feb-4fff-a75e-6a45d8164837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672190923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3672190923
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1335497793
Short name T507
Test name
Test status
Simulation time 114248759 ps
CPU time 1.22 seconds
Started Jun 24 05:36:12 PM PDT 24
Finished Jun 24 05:36:14 PM PDT 24
Peak memory 200864 kb
Host smart-aaaddf76-18eb-47c7-8b89-e3a28df6ef26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335497793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1335497793
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.150425079
Short name T372
Test name
Test status
Simulation time 138149816 ps
CPU time 1.81 seconds
Started Jun 24 05:36:22 PM PDT 24
Finished Jun 24 05:36:26 PM PDT 24
Peak memory 200692 kb
Host smart-db703e5a-ac19-468d-864b-2e83077b66eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150425079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.150425079
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2119542332
Short name T418
Test name
Test status
Simulation time 195416661 ps
CPU time 1.23 seconds
Started Jun 24 05:36:13 PM PDT 24
Finished Jun 24 05:36:16 PM PDT 24
Peak memory 200704 kb
Host smart-7929d116-5616-4472-b643-40267bfebfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119542332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2119542332
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3534471741
Short name T154
Test name
Test status
Simulation time 61275696 ps
CPU time 0.78 seconds
Started Jun 24 05:36:13 PM PDT 24
Finished Jun 24 05:36:14 PM PDT 24
Peak memory 200500 kb
Host smart-8177c984-5e52-4f56-a40b-0faedc57942b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534471741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3534471741
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1646265139
Short name T466
Test name
Test status
Simulation time 1227658227 ps
CPU time 5.92 seconds
Started Jun 24 05:36:15 PM PDT 24
Finished Jun 24 05:36:23 PM PDT 24
Peak memory 218192 kb
Host smart-ad8243be-3361-48ed-acef-8e71dbd74bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646265139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1646265139
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1166768720
Short name T171
Test name
Test status
Simulation time 243792308 ps
CPU time 1.08 seconds
Started Jun 24 05:36:14 PM PDT 24
Finished Jun 24 05:36:16 PM PDT 24
Peak memory 218072 kb
Host smart-e1546c56-1662-4310-ad1d-7586674ae433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166768720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1166768720
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1470887529
Short name T243
Test name
Test status
Simulation time 230500453 ps
CPU time 1.04 seconds
Started Jun 24 05:36:26 PM PDT 24
Finished Jun 24 05:36:30 PM PDT 24
Peak memory 200516 kb
Host smart-3ece53da-7a1c-4a85-bf8b-f481f81e4ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470887529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1470887529
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.572994032
Short name T313
Test name
Test status
Simulation time 1559414777 ps
CPU time 6 seconds
Started Jun 24 05:36:19 PM PDT 24
Finished Jun 24 05:36:27 PM PDT 24
Peak memory 200888 kb
Host smart-a02b3329-1685-4ec7-bdd9-c49757a7eec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572994032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.572994032
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2774458216
Short name T166
Test name
Test status
Simulation time 182448695 ps
CPU time 1.28 seconds
Started Jun 24 05:36:28 PM PDT 24
Finished Jun 24 05:36:31 PM PDT 24
Peak memory 200936 kb
Host smart-ff745c90-5950-4d2a-8a70-b384331b04b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774458216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2774458216
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.713347705
Short name T363
Test name
Test status
Simulation time 244124097 ps
CPU time 1.43 seconds
Started Jun 24 05:36:14 PM PDT 24
Finished Jun 24 05:36:17 PM PDT 24
Peak memory 200868 kb
Host smart-c3622e81-9961-4969-a0c1-eab7c5659413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713347705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.713347705
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3421964640
Short name T114
Test name
Test status
Simulation time 2108890088 ps
CPU time 7.31 seconds
Started Jun 24 05:36:10 PM PDT 24
Finished Jun 24 05:36:18 PM PDT 24
Peak memory 200880 kb
Host smart-78073828-2d67-43fc-b7ed-466b3ea9ae47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421964640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3421964640
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2548302421
Short name T198
Test name
Test status
Simulation time 308278073 ps
CPU time 2.09 seconds
Started Jun 24 05:36:13 PM PDT 24
Finished Jun 24 05:36:15 PM PDT 24
Peak memory 208892 kb
Host smart-a4c9575d-d61e-4035-8a7e-af2aa8d8d9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548302421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2548302421
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.1393588107
Short name T282
Test name
Test status
Simulation time 123572558 ps
CPU time 0.97 seconds
Started Jun 24 05:36:23 PM PDT 24
Finished Jun 24 05:36:26 PM PDT 24
Peak memory 200712 kb
Host smart-902a873b-8c2a-4cfe-ab6d-a8305c617108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393588107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1393588107
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1101922055
Short name T121
Test name
Test status
Simulation time 64910297 ps
CPU time 0.78 seconds
Started Jun 24 05:36:09 PM PDT 24
Finished Jun 24 05:36:10 PM PDT 24
Peak memory 200500 kb
Host smart-4b59ee04-93f0-4202-a3c4-e202aee162d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101922055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1101922055
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2642205640
Short name T486
Test name
Test status
Simulation time 2344389570 ps
CPU time 8.19 seconds
Started Jun 24 05:36:16 PM PDT 24
Finished Jun 24 05:36:26 PM PDT 24
Peak memory 222452 kb
Host smart-06699078-bafc-424e-9043-d4a3bc3c86dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642205640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2642205640
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.375720027
Short name T155
Test name
Test status
Simulation time 244113352 ps
CPU time 1.16 seconds
Started Jun 24 05:36:18 PM PDT 24
Finished Jun 24 05:36:20 PM PDT 24
Peak memory 217984 kb
Host smart-3d688eee-7171-42bd-b219-069cedbbc03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375720027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.375720027
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2515992243
Short name T373
Test name
Test status
Simulation time 127374928 ps
CPU time 0.81 seconds
Started Jun 24 05:36:14 PM PDT 24
Finished Jun 24 05:36:16 PM PDT 24
Peak memory 200496 kb
Host smart-145c9b8d-8cdc-4991-84ab-b421a1633401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515992243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2515992243
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.1704678459
Short name T26
Test name
Test status
Simulation time 1285799500 ps
CPU time 5.39 seconds
Started Jun 24 05:36:13 PM PDT 24
Finished Jun 24 05:36:20 PM PDT 24
Peak memory 200924 kb
Host smart-db8ebf67-8a80-4fdd-b41a-1fc611e4a44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704678459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1704678459
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2201688782
Short name T168
Test name
Test status
Simulation time 111242396 ps
CPU time 1 seconds
Started Jun 24 05:36:29 PM PDT 24
Finished Jun 24 05:36:32 PM PDT 24
Peak memory 200700 kb
Host smart-e259108d-3d94-44eb-b5ed-63b403ffa960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201688782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2201688782
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2923703941
Short name T470
Test name
Test status
Simulation time 198115701 ps
CPU time 1.45 seconds
Started Jun 24 05:36:11 PM PDT 24
Finished Jun 24 05:36:13 PM PDT 24
Peak memory 200892 kb
Host smart-2339d571-dc8a-4a13-a5d7-8c0e730dd37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923703941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2923703941
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.138085297
Short name T201
Test name
Test status
Simulation time 5501736444 ps
CPU time 21.94 seconds
Started Jun 24 05:36:16 PM PDT 24
Finished Jun 24 05:36:39 PM PDT 24
Peak memory 209792 kb
Host smart-e87b5f6d-4708-4543-bc7c-59666f369ac1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138085297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.138085297
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2249387078
Short name T149
Test name
Test status
Simulation time 347690531 ps
CPU time 2.31 seconds
Started Jun 24 05:36:15 PM PDT 24
Finished Jun 24 05:36:19 PM PDT 24
Peak memory 200732 kb
Host smart-e02cac43-a73a-4a3d-ad57-1320a9c16745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249387078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2249387078
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1461031541
Short name T265
Test name
Test status
Simulation time 69065362 ps
CPU time 0.8 seconds
Started Jun 24 05:36:15 PM PDT 24
Finished Jun 24 05:36:18 PM PDT 24
Peak memory 200704 kb
Host smart-9cdae92e-2b77-4fd4-b4d7-65f58811ba10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461031541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1461031541
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.627494793
Short name T310
Test name
Test status
Simulation time 64359109 ps
CPU time 0.77 seconds
Started Jun 24 05:35:04 PM PDT 24
Finished Jun 24 05:35:08 PM PDT 24
Peak memory 200488 kb
Host smart-331451b5-27c1-47c5-92ce-a9ec256e75df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627494793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.627494793
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2008084638
Short name T503
Test name
Test status
Simulation time 1906263930 ps
CPU time 7.97 seconds
Started Jun 24 05:35:03 PM PDT 24
Finished Jun 24 05:35:14 PM PDT 24
Peak memory 222336 kb
Host smart-741d112f-4fac-49ac-8bd4-b085ccf0ecf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008084638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2008084638
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.812732444
Short name T344
Test name
Test status
Simulation time 244827086 ps
CPU time 1.11 seconds
Started Jun 24 05:35:04 PM PDT 24
Finished Jun 24 05:35:08 PM PDT 24
Peak memory 218072 kb
Host smart-42301f5f-f3df-451d-8ded-2c30feca9418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812732444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.812732444
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.2318421914
Short name T169
Test name
Test status
Simulation time 161748322 ps
CPU time 0.85 seconds
Started Jun 24 05:35:02 PM PDT 24
Finished Jun 24 05:35:04 PM PDT 24
Peak memory 200492 kb
Host smart-543ca90a-0fa1-4428-9244-053e92b53c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318421914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2318421914
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2454053006
Short name T263
Test name
Test status
Simulation time 1206665781 ps
CPU time 5.17 seconds
Started Jun 24 05:35:04 PM PDT 24
Finished Jun 24 05:35:12 PM PDT 24
Peak memory 200568 kb
Host smart-0dfcbe92-2321-4241-a6bf-78dc27870924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454053006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2454053006
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.841647433
Short name T308
Test name
Test status
Simulation time 111980412 ps
CPU time 1.04 seconds
Started Jun 24 05:35:01 PM PDT 24
Finished Jun 24 05:35:03 PM PDT 24
Peak memory 200704 kb
Host smart-f5bc3089-eb44-40e8-a61a-3c08e254c8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841647433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.841647433
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2731267481
Short name T11
Test name
Test status
Simulation time 199111583 ps
CPU time 1.38 seconds
Started Jun 24 05:35:03 PM PDT 24
Finished Jun 24 05:35:07 PM PDT 24
Peak memory 200892 kb
Host smart-6de23f14-1431-4762-b1d3-899f7e95bc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731267481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2731267481
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.107373185
Short name T240
Test name
Test status
Simulation time 6382959189 ps
CPU time 27.67 seconds
Started Jun 24 05:35:03 PM PDT 24
Finished Jun 24 05:35:34 PM PDT 24
Peak memory 200956 kb
Host smart-b7798c0a-a330-447e-a8fe-ef8da5f585b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107373185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.107373185
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1793764183
Short name T116
Test name
Test status
Simulation time 406832981 ps
CPU time 2.15 seconds
Started Jun 24 05:35:04 PM PDT 24
Finished Jun 24 05:35:09 PM PDT 24
Peak memory 200600 kb
Host smart-84e4ab56-2465-48ba-a2c0-1790265b8c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793764183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1793764183
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.651762767
Short name T250
Test name
Test status
Simulation time 79194781 ps
CPU time 0.85 seconds
Started Jun 24 05:35:04 PM PDT 24
Finished Jun 24 05:35:08 PM PDT 24
Peak memory 200700 kb
Host smart-fad25c24-dcec-4a33-9413-5e7c6bb34d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651762767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.651762767
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.956997451
Short name T129
Test name
Test status
Simulation time 66987807 ps
CPU time 0.76 seconds
Started Jun 24 05:35:04 PM PDT 24
Finished Jun 24 05:35:07 PM PDT 24
Peak memory 200500 kb
Host smart-3a9cb37d-b809-4f77-9827-bab5a27cd1e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956997451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.956997451
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1107623947
Short name T505
Test name
Test status
Simulation time 1230298692 ps
CPU time 5.64 seconds
Started Jun 24 05:35:06 PM PDT 24
Finished Jun 24 05:35:14 PM PDT 24
Peak memory 222460 kb
Host smart-ee2deff2-001e-4ad3-aa6e-e11b2e05295a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107623947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1107623947
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.260956106
Short name T332
Test name
Test status
Simulation time 244781648 ps
CPU time 1.11 seconds
Started Jun 24 05:35:04 PM PDT 24
Finished Jun 24 05:35:08 PM PDT 24
Peak memory 218064 kb
Host smart-40100cd6-c1fe-4907-8f98-f7c56058dbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260956106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.260956106
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.4171209453
Short name T276
Test name
Test status
Simulation time 169703632 ps
CPU time 0.86 seconds
Started Jun 24 05:35:02 PM PDT 24
Finished Jun 24 05:35:05 PM PDT 24
Peak memory 200508 kb
Host smart-fb7025e5-544b-48cc-9e22-e2febc898a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171209453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.4171209453
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.587419230
Short name T362
Test name
Test status
Simulation time 823329165 ps
CPU time 3.97 seconds
Started Jun 24 05:35:21 PM PDT 24
Finished Jun 24 05:35:26 PM PDT 24
Peak memory 200908 kb
Host smart-287949e8-1d9e-4f3a-9466-91ed08e41c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587419230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.587419230
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3456006594
Short name T508
Test name
Test status
Simulation time 115663510 ps
CPU time 1.02 seconds
Started Jun 24 05:35:01 PM PDT 24
Finished Jun 24 05:35:04 PM PDT 24
Peak memory 200696 kb
Host smart-732cc876-782a-4211-ad79-20d5733d7107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456006594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3456006594
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.101919594
Short name T28
Test name
Test status
Simulation time 252774301 ps
CPU time 1.47 seconds
Started Jun 24 05:35:08 PM PDT 24
Finished Jun 24 05:35:11 PM PDT 24
Peak memory 200872 kb
Host smart-b7067377-e8aa-4945-8d4d-12ec72ef8a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101919594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.101919594
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.152342348
Short name T180
Test name
Test status
Simulation time 2527597260 ps
CPU time 11.28 seconds
Started Jun 24 05:35:04 PM PDT 24
Finished Jun 24 05:35:19 PM PDT 24
Peak memory 200584 kb
Host smart-e5c850a5-5e2e-4d81-b64c-9efb9c7f67c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152342348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.152342348
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1644636387
Short name T41
Test name
Test status
Simulation time 366700395 ps
CPU time 2.46 seconds
Started Jun 24 05:35:00 PM PDT 24
Finished Jun 24 05:35:04 PM PDT 24
Peak memory 200696 kb
Host smart-13a8f7a8-e73d-4180-8dde-4762bbf8c89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644636387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1644636387
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.4013598208
Short name T197
Test name
Test status
Simulation time 101496532 ps
CPU time 0.89 seconds
Started Jun 24 05:35:03 PM PDT 24
Finished Jun 24 05:35:07 PM PDT 24
Peak memory 200728 kb
Host smart-8b12a70f-88bf-4ad3-a5f5-ac1a03cf3781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013598208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.4013598208
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2473182074
Short name T329
Test name
Test status
Simulation time 71816073 ps
CPU time 0.78 seconds
Started Jun 24 05:35:04 PM PDT 24
Finished Jun 24 05:35:08 PM PDT 24
Peak memory 200404 kb
Host smart-296346b6-88ff-40c6-ab3e-ab3bdd90f897
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473182074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2473182074
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.259531519
Short name T38
Test name
Test status
Simulation time 1907004198 ps
CPU time 7.9 seconds
Started Jun 24 05:35:05 PM PDT 24
Finished Jun 24 05:35:15 PM PDT 24
Peak memory 222460 kb
Host smart-14de8ea8-a89a-45c6-bd8f-9f093ca45bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259531519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.259531519
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.88886522
Short name T207
Test name
Test status
Simulation time 244535720 ps
CPU time 1.2 seconds
Started Jun 24 05:35:04 PM PDT 24
Finished Jun 24 05:35:07 PM PDT 24
Peak memory 218144 kb
Host smart-f8d0209e-786f-4b8a-bd3d-fe767662ea68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88886522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.88886522
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.254245134
Short name T182
Test name
Test status
Simulation time 134412099 ps
CPU time 0.85 seconds
Started Jun 24 05:35:03 PM PDT 24
Finished Jun 24 05:35:06 PM PDT 24
Peak memory 200484 kb
Host smart-94f24f2c-e8bf-4908-9ee4-2faf31b7b552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254245134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.254245134
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3133073008
Short name T135
Test name
Test status
Simulation time 849071807 ps
CPU time 4.17 seconds
Started Jun 24 05:35:03 PM PDT 24
Finished Jun 24 05:35:09 PM PDT 24
Peak memory 200900 kb
Host smart-44ab6490-ed5b-4540-bf63-7cd971e09693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133073008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3133073008
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.4233326673
Short name T390
Test name
Test status
Simulation time 100327592 ps
CPU time 1.02 seconds
Started Jun 24 05:35:04 PM PDT 24
Finished Jun 24 05:35:08 PM PDT 24
Peak memory 200604 kb
Host smart-c1fdd3ff-632f-4db0-afbf-cb7cb8ee358a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233326673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.4233326673
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.1029121281
Short name T397
Test name
Test status
Simulation time 234285030 ps
CPU time 1.45 seconds
Started Jun 24 05:35:02 PM PDT 24
Finished Jun 24 05:35:06 PM PDT 24
Peak memory 200892 kb
Host smart-b7390009-0b72-42a1-9938-541628be1dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029121281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.1029121281
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.222409670
Short name T394
Test name
Test status
Simulation time 6957832423 ps
CPU time 23.49 seconds
Started Jun 24 05:35:03 PM PDT 24
Finished Jun 24 05:35:28 PM PDT 24
Peak memory 209052 kb
Host smart-c06a6dde-1832-4a7b-8951-59216e0e40b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222409670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.222409670
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.760955419
Short name T51
Test name
Test status
Simulation time 122540470 ps
CPU time 1.7 seconds
Started Jun 24 05:35:02 PM PDT 24
Finished Jun 24 05:35:06 PM PDT 24
Peak memory 208924 kb
Host smart-cac82ec4-f4e3-41f9-b987-f6b772d1072c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760955419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.760955419
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.115854163
Short name T336
Test name
Test status
Simulation time 234232708 ps
CPU time 1.43 seconds
Started Jun 24 05:35:02 PM PDT 24
Finished Jun 24 05:35:06 PM PDT 24
Peak memory 200700 kb
Host smart-47ae60e6-882c-4bc3-85a3-c402b88a29a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115854163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.115854163
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1577022660
Short name T231
Test name
Test status
Simulation time 73980915 ps
CPU time 0.81 seconds
Started Jun 24 05:35:20 PM PDT 24
Finished Jun 24 05:35:21 PM PDT 24
Peak memory 200496 kb
Host smart-d9aecfb6-78aa-4f54-b2e0-3e037364e972
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577022660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1577022660
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.589352375
Short name T317
Test name
Test status
Simulation time 1224117208 ps
CPU time 5.87 seconds
Started Jun 24 05:35:23 PM PDT 24
Finished Jun 24 05:35:31 PM PDT 24
Peak memory 218480 kb
Host smart-ed52f4ca-15d4-40fa-b71b-767e16ba9ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589352375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.589352375
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3591509632
Short name T261
Test name
Test status
Simulation time 245525055 ps
CPU time 1.09 seconds
Started Jun 24 05:35:35 PM PDT 24
Finished Jun 24 05:35:37 PM PDT 24
Peak memory 218092 kb
Host smart-77c3049d-b998-4b8d-9f13-a17614947386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591509632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3591509632
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.150386567
Short name T23
Test name
Test status
Simulation time 151486275 ps
CPU time 0.82 seconds
Started Jun 24 05:35:03 PM PDT 24
Finished Jun 24 05:35:07 PM PDT 24
Peak memory 200372 kb
Host smart-5d470cd5-430f-4510-b553-5835b48a1e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150386567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.150386567
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.785007563
Short name T95
Test name
Test status
Simulation time 1573131167 ps
CPU time 6.1 seconds
Started Jun 24 05:35:19 PM PDT 24
Finished Jun 24 05:35:26 PM PDT 24
Peak memory 200908 kb
Host smart-4fa8fa2d-6289-461f-b486-56c49735b1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785007563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.785007563
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2647278763
Short name T29
Test name
Test status
Simulation time 115201614 ps
CPU time 1.08 seconds
Started Jun 24 05:35:15 PM PDT 24
Finished Jun 24 05:35:17 PM PDT 24
Peak memory 200168 kb
Host smart-97a3d6ad-d830-49b0-8a99-8978bd9204a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647278763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2647278763
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3992683909
Short name T140
Test name
Test status
Simulation time 204368817 ps
CPU time 1.4 seconds
Started Jun 24 05:35:22 PM PDT 24
Finished Jun 24 05:35:25 PM PDT 24
Peak memory 200892 kb
Host smart-17372ca2-0cb0-4509-9bbf-eda0f5a9c842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992683909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3992683909
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2416884870
Short name T472
Test name
Test status
Simulation time 12678671509 ps
CPU time 41.05 seconds
Started Jun 24 05:35:23 PM PDT 24
Finished Jun 24 05:36:07 PM PDT 24
Peak memory 210676 kb
Host smart-8669cf2c-7194-4fed-ae88-0726a2987d0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416884870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2416884870
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3397812815
Short name T368
Test name
Test status
Simulation time 542277711 ps
CPU time 2.76 seconds
Started Jun 24 05:35:23 PM PDT 24
Finished Jun 24 05:35:28 PM PDT 24
Peak memory 200932 kb
Host smart-b7cde6ae-555c-46c9-8b3c-b88f84f41aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397812815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3397812815
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1429436110
Short name T327
Test name
Test status
Simulation time 134696259 ps
CPU time 1.17 seconds
Started Jun 24 05:35:19 PM PDT 24
Finished Jun 24 05:35:21 PM PDT 24
Peak memory 200704 kb
Host smart-ff1fc1ba-e13e-4cb0-89e7-286b413d1255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429436110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1429436110
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.538299395
Short name T429
Test name
Test status
Simulation time 65747242 ps
CPU time 0.79 seconds
Started Jun 24 05:35:15 PM PDT 24
Finished Jun 24 05:35:17 PM PDT 24
Peak memory 200500 kb
Host smart-118ef302-6cc6-4fb4-a7d9-aede2ce1b65a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538299395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.538299395
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.3508491630
Short name T253
Test name
Test status
Simulation time 1884415757 ps
CPU time 7.23 seconds
Started Jun 24 05:35:12 PM PDT 24
Finished Jun 24 05:35:20 PM PDT 24
Peak memory 218724 kb
Host smart-ffc7be88-24a4-4109-aeeb-8dde2fb44800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508491630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3508491630
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.900563979
Short name T52
Test name
Test status
Simulation time 244288069 ps
CPU time 1.18 seconds
Started Jun 24 05:35:25 PM PDT 24
Finished Jun 24 05:35:28 PM PDT 24
Peak memory 218008 kb
Host smart-cc2522dc-b0b8-40f9-a526-f1ce093ca6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900563979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.900563979
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.788601254
Short name T424
Test name
Test status
Simulation time 203119258 ps
CPU time 1.09 seconds
Started Jun 24 05:35:26 PM PDT 24
Finished Jun 24 05:35:29 PM PDT 24
Peak memory 200488 kb
Host smart-5e8ca004-b06b-40da-828e-56d7a9abe896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788601254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.788601254
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.1437184522
Short name T506
Test name
Test status
Simulation time 1341740687 ps
CPU time 5.62 seconds
Started Jun 24 05:35:12 PM PDT 24
Finished Jun 24 05:35:18 PM PDT 24
Peak memory 200868 kb
Host smart-21f12ee6-6a42-4bc7-90a8-4e7bcedc259d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437184522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1437184522
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1531129174
Short name T420
Test name
Test status
Simulation time 96318656 ps
CPU time 1.05 seconds
Started Jun 24 05:35:16 PM PDT 24
Finished Jun 24 05:35:18 PM PDT 24
Peak memory 200692 kb
Host smart-39e79364-4d33-434d-9669-95b4f0f748f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531129174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1531129174
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.4095893637
Short name T173
Test name
Test status
Simulation time 260249740 ps
CPU time 1.72 seconds
Started Jun 24 05:35:30 PM PDT 24
Finished Jun 24 05:35:33 PM PDT 24
Peak memory 200908 kb
Host smart-20edfde1-1021-4a7c-9fb1-317246867926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095893637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.4095893637
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1684637495
Short name T447
Test name
Test status
Simulation time 4684404203 ps
CPU time 21.46 seconds
Started Jun 24 05:35:24 PM PDT 24
Finished Jun 24 05:35:48 PM PDT 24
Peak memory 209168 kb
Host smart-8cd091ed-bce1-439d-8bcf-47c1de9a9cf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684637495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1684637495
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1924533216
Short name T232
Test name
Test status
Simulation time 441288823 ps
CPU time 2.82 seconds
Started Jun 24 05:35:25 PM PDT 24
Finished Jun 24 05:35:30 PM PDT 24
Peak memory 200728 kb
Host smart-183ab284-ecfc-4527-b502-40d72f71b8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924533216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1924533216
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1294424874
Short name T318
Test name
Test status
Simulation time 130695866 ps
CPU time 1.05 seconds
Started Jun 24 05:35:10 PM PDT 24
Finished Jun 24 05:35:12 PM PDT 24
Peak memory 200676 kb
Host smart-86901fff-2262-42e9-9881-0dce45b1f964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294424874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1294424874
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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