Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7067

1

T7

28

T11

23

T12

27

auto[1]

9998

1

T1

4

T2

4

T7

54

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5296	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	5782	1			T1	2		T2	2		T3	1
reset_info_cp[2]	2716	1			T1	1		T2	1		T7	16
reset_info_cp[4]	3399	1			T1	1		T2	1		T7	18
reset_info_cp[8]	104	1			T7	1		T21	1		T35	1
reset_info_cp[16]	100	1			T7	1		T21	1		T33	2
reset_info_cp[32]	81	1			T21	1		T33	1		T35	3
reset_info_cp[64]	110	1			T11	1		T34	1		T35	1
reset_info_cp[128]	97	1			T11	1		T13	1		T33	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2789	1			T7	11		T11	8		T12	7
reset_info_cp[1]	auto[1]	2373	1			T1	1		T2	1		T7	16
reset_info_cp[2]	auto[0]	781	1			T7	3		T11	3		T12	3
reset_info_cp[2]	auto[1]	1935	1			T1	1		T2	1		T7	13
reset_info_cp[4]	auto[0]	1204	1			T7	7		T11	6		T12	8
reset_info_cp[4]	auto[1]	2195	1			T1	1		T2	1		T7	11
reset_info_cp[8]	auto[0]	33	1			T35	1		T99	2		T102	1
reset_info_cp[8]	auto[1]	71	1			T7	1		T21	1		T45	1
reset_info_cp[16]	auto[0]	39	1			T33	2		T84	1		T98	1
reset_info_cp[16]	auto[1]	61	1			T7	1		T21	1		T130	1
reset_info_cp[32]	auto[0]	32	1			T35	2		T99	1		T131	2
reset_info_cp[32]	auto[1]	49	1			T21	1		T33	1		T35	1
reset_info_cp[64]	auto[0]	48	1			T11	1		T84	1		T124	1
reset_info_cp[64]	auto[1]	62	1			T34	1		T35	1		T24	1
reset_info_cp[128]	auto[0]	41	1			T11	1		T33	1		T43	1
reset_info_cp[128]	auto[1]	56	1			T13	1		T33	1		T35	1